[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include <linux/pci-aspm.h>
#include <linux/ath9k_platform.h>
#include "ath9k.h"

static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
	{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
	{ 0 }
};


/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unpleasant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct ath9k_platform_data *pdata = sc->dev->platform_data;

	if (pdata) {
		if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
			ath_err(common,
				"%s: eeprom read failed, offset %08x is out of range\n",
				__func__, off);
		}

		*data = pdata->eeprom_data[off];
	} else {
		struct ath_hw *ah = (struct ath_hw *) common->ah;

		common->ops->read(ah, AR5416_EEPROM_OFFSET +
				      (off << AR5416_EEPROM_S));

		if (!ath9k_hw_wait(ah,
				   AR_EEPROM_STATUS_DATA,
				   AR_EEPROM_STATUS_DATA_BUSY |
				   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
				   AH_WAIT_TIMEOUT)) {
			return false;
		}

		*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
			   AR_EEPROM_STATUS_DATA_VAL);
	}

	return true;
}

static void ath_pci_extn_synch_enable(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 lnkctl;

	pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
	lnkctl |= PCI_EXP_LNKCTL_ES;
	pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
}

/* Need to be called after we discover btcoex capabilities */
static void ath_pci_aspm_init(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct ath_hw *ah = sc->sc_ah;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	struct pci_dev *parent;
	int pos;
	u8 aspm;

	pos = pci_pcie_cap(pdev);
	if (!pos)
		return;

	parent = pdev->bus->self;
	if (!parent)
		return;

	if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) {
		/* Bluetooth coexistance requires disabling ASPM. */
		pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
		pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);

		/*
		 * Both upstream and downstream PCIe components should
		 * have the same ASPM settings.
		 */
		pos = pci_pcie_cap(parent);
		pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
		pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);

		return;
	}

	pos = pci_pcie_cap(parent);
	pci_read_config_byte(parent, pos +  PCI_EXP_LNKCTL, &aspm);
	if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
		ah->aspm_enabled = true;
		/* Initialize PCIe PM and SERDES registers. */
		ath9k_hw_configpcipowersave(ah, false);
	}
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath_pci_read_cachesize,
	.eeprom_read = ath_pci_eeprom_read,
	.extn_synch_en = ath_pci_extn_synch_enable,
	.aspm_init = ath_pci_aspm_init,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u32 val;
	int ret = 0;
	char hw_name[64];

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto err_dma;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto err_dma;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto err_region;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto err_iomap;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_alloc_hw;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	sc = hw->priv;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;

	/* Will be cleared in ath9k_start() */
	sc->sc_flags |= SC_OP_INVALID;

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto err_irq;
	}

	sc->irq = pdev->irq;

	ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize device\n");
		goto err_init;
	}

	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
		   hw_name, (unsigned long)mem, pdev->irq);

	return 0;

err_init:
	free_irq(sc->irq, sc);
err_irq:
	ieee80211_free_hw(hw);
err_alloc_hw:
	pci_iounmap(pdev, mem);
err_iomap:
	pci_release_region(pdev, 0);
err_region:
	/* Nothing */
err_dma:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;
	void __iomem *mem = sc->mem;

	if (!is_ath9k_unloaded)
		sc->sc_ah->ah_flags |= AH_UNPLUGGED;
	ath9k_deinit_device(sc);
	free_irq(sc->irq, sc);
	ieee80211_free_hw(sc->hw);

	pci_iounmap(pdev, mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	/* The device has to be moved to FULLSLEEP forcibly.
	 * Otherwise the chip never moved to full sleep,
	 * when no interface is up.
	 */
	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);

	return 0;
}

static int ath_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;
	u32 val;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	  /*
	   * Reset key cache to sane defaults (all entries cleared) instead of
	   * semi-random values after suspend/resume.
	   */
	ath9k_ps_wakeup(sc);
	ath9k_cmn_init_crypto(sc->sc_ah);
	ath9k_ps_restore(sc);

	sc->ps_idle = true;
	ath_radio_disable(sc, hw);

	return 0;
}

static const struct dev_pm_ops ath9k_pm_ops = {
	.suspend = ath_pci_suspend,
	.resume = ath_pci_resume,
	.freeze = ath_pci_suspend,
	.thaw = ath_pci_resume,
	.poweroff = ath_pci_suspend,
	.restore = ath_pci_resume,
};

#define ATH9K_PM_OPS	(&ath9k_pm_ops)

#else /* !CONFIG_PM */

#define ATH9K_PM_OPS	NULL

#endif /* !CONFIG_PM */


MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
	.driver.pm  = ATH9K_PM_OPS,
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
d4930086	19	#include <linux/pci-aspm.h>
a05b5d45	20	#include <linux/ath9k_platform.h>
394cf0a1	21	#include "ath9k.h"
6baff7f9	22
a3aa1884	23	static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
6baff7f9 GJ	24	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	25	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	26	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	27	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	28	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	29	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
5ffaf8a3	30	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
ac88b6ec VN	31	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	32	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
0efabd51	33	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
1435894d	34	{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
6baff7f9 GJ	35	{ 0 }
	36	};
	37
84c87dc8	38
6baff7f9	39	/* return bus cachesize in 4B word units */
5bb12791	40	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	41	{
bc974f4a	42	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	43	u8 u8tmp;
6baff7f9 GJ	44
f020979d	45	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	46	*csz = (int)u8tmp;
	47
	48	/*
25985edc	49	* This check was put in to avoid "unpleasant" consequences if
6baff7f9 GJ	50	* the bootrom has not fully initialized all PCI devices.
	51	* Sometimes the cache line size register is not set
	52	*/
	53
	54	if (*csz == 0)
	55	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	56	}
	57
5bb12791	58	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	59	{
a05b5d45 FF	60	struct ath_softc sc = (struct ath_softc ) common->priv;
	61	struct ath9k_platform_data *pdata = sc->dev->platform_data;
	62
	63	if (pdata) {
	64	if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
3800276a JP	65	ath_err(common,
	66	"%s: eeprom read failed, offset %08x is out of range\n",
	67	__func__, off);
a05b5d45 FF	68	}
	69
	70	*data = pdata->eeprom_data[off];
	71	} else {
	72	struct ath_hw ah = (struct ath_hw ) common->ah;
	73
	74	common->ops->read(ah, AR5416_EEPROM_OFFSET +
	75	(off << AR5416_EEPROM_S));
	76
	77	if (!ath9k_hw_wait(ah,
	78	AR_EEPROM_STATUS_DATA,
	79	AR_EEPROM_STATUS_DATA_BUSY \|
	80	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
	81	AH_WAIT_TIMEOUT)) {
	82	return false;
	83	}
	84
	85	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
	86	AR_EEPROM_STATUS_DATA_VAL);
9dbeb91a GJ	87	}
9dbeb91a GJ	88
9dbeb91a GJ	89	return true;
	90	}
	91
8060e169 VT	92	static void ath_pci_extn_synch_enable(struct ath_common *common)
	93	{
	94	struct ath_softc sc = (struct ath_softc ) common->priv;
	95	struct pci_dev *pdev = to_pci_dev(sc->dev);
	96	u8 lnkctl;
	97
	98	pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
	99	lnkctl \|= PCI_EXP_LNKCTL_ES;
	100	pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
	101	}
	102
69ce674b	103	/* Need to be called after we discover btcoex capabilities */
d4930086 SG	104	static void ath_pci_aspm_init(struct ath_common *common)
	105	{
	106	struct ath_softc sc = (struct ath_softc ) common->priv;
	107	struct ath_hw *ah = sc->sc_ah;
	108	struct pci_dev *pdev = to_pci_dev(sc->dev);
	109	struct pci_dev *parent;
	110	int pos;
	111	u8 aspm;
	112
69ce674b SG	113	pos = pci_pcie_cap(pdev);
69ce674b SG	114	if (!pos)
d4930086 SG	115	return;
	116
	117	parent = pdev->bus->self;
22c55e6e JL	118	if (!parent)
22c55e6e JL	119	return;
69ce674b SG	120
	121	if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) {
	122	/* Bluetooth coexistance requires disabling ASPM. */
	123	pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
	124	aspm &= ~(PCIE_LINK_STATE_L0S \| PCIE_LINK_STATE_L1);
	125	pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
	126
	127	/*
	128	* Both upstream and downstream PCIe components should
	129	* have the same ASPM settings.
	130	*/
69ce674b SG	131	pos = pci_pcie_cap(parent);
	132	pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
	133	aspm &= ~(PCIE_LINK_STATE_L0S \| PCIE_LINK_STATE_L1);
	134	pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
	135
	136	return;
	137	}
	138
d4930086 SG	139	pos = pci_pcie_cap(parent);
	140	pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
	141	if (aspm & (PCIE_LINK_STATE_L0S \| PCIE_LINK_STATE_L1)) {
	142	ah->aspm_enabled = true;
	143	/* Initialize PCIe PM and SERDES registers. */
84c87dc8	144	ath9k_hw_configpcipowersave(ah, false);
d4930086 SG	145	}
	146	}
	147
83bd11a0	148	static const struct ath_bus_ops ath_pci_bus_ops = {
497ad9ad	149	.ath_bus_type = ATH_PCI,
6baff7f9	150	.read_cachesize = ath_pci_read_cachesize,
9dbeb91a	151	.eeprom_read = ath_pci_eeprom_read,
8060e169	152	.extn_synch_en = ath_pci_extn_synch_enable,
d4930086	153	.aspm_init = ath_pci_aspm_init,
6baff7f9 GJ	154	};
	155
	156	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	157	{
	158	void __iomem *mem;
	159	struct ath_softc *sc;
	160	struct ieee80211_hw *hw;
	161	u8 csz;
f0214843	162	u32 val;
6baff7f9	163	int ret = 0;
f934c4d9	164	char hw_name[64];
6baff7f9 GJ	165
	166	if (pci_enable_device(pdev))
	167	return -EIO;
	168
e930438c	169	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	170	if (ret) {
6baff7f9 GJ	171	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
285f2dda	172	goto err_dma;
6baff7f9 GJ	173	}
6baff7f9 GJ	174
e930438c	175	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	176	if (ret) {
	177	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	178	"DMA enable failed\n");
285f2dda	179	goto err_dma;
6baff7f9 GJ	180	}
	181
	182	/*
	183	* Cache line size is used to size and align various
	184	* structures used to communicate with the hardware.
	185	*/
	186	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	187	if (csz == 0) {
	188	/*
	189	* Linux 2.4.18 (at least) writes the cache line size
	190	* register as a 16-bit wide register which is wrong.
	191	* We must have this setup properly for rx buffer
	192	* DMA to work so force a reasonable value here if it
	193	* comes up zero.
	194	*/
	195	csz = L1_CACHE_BYTES / sizeof(u32);
	196	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	197	}
	198	/*
	199	* The default setting of latency timer yields poor results,
	200	* set it to the value used by other systems. It may be worth
	201	* tweaking this setting more.
	202	*/
	203	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	204
	205	pci_set_master(pdev);
	206
f0214843 JM	207	/*
	208	* Disable the RETRY_TIMEOUT register (0x41) to keep
	209	* PCI Tx retries from interfering with C3 CPU state.
	210	*/
	211	pci_read_config_dword(pdev, 0x40, &val);
	212	if ((val & 0x0000ff00) != 0)
	213	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	214
6baff7f9 GJ	215	ret = pci_request_region(pdev, 0, "ath9k");
	216	if (ret) {
	217	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	218	ret = -ENODEV;
285f2dda	219	goto err_region;
6baff7f9 GJ	220	}
	221
	222	mem = pci_iomap(pdev, 0, 0);
	223	if (!mem) {
	224	printk(KERN_ERR "PCI memory map error\n") ;
	225	ret = -EIO;
285f2dda	226	goto err_iomap;
6baff7f9 GJ	227	}
6baff7f9 GJ	228
9ac58615	229	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
db6be53c	230	if (!hw) {
285f2dda	231	dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
db6be53c	232	ret = -ENOMEM;
285f2dda	233	goto err_alloc_hw;
6baff7f9 GJ	234	}
	235
	236	SET_IEEE80211_DEV(hw, &pdev->dev);
	237	pci_set_drvdata(pdev, hw);
	238
9ac58615	239	sc = hw->priv;
6baff7f9 GJ	240	sc->hw = hw;
	241	sc->dev = &pdev->dev;
	242	sc->mem = mem;
6baff7f9	243
5e4ea1f0 S	244	/* Will be cleared in ath9k_start() */
5e4ea1f0 S	245	sc->sc_flags \|= SC_OP_INVALID;
6baff7f9	246
fc548af8	247	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	248	if (ret) {
580171f7 LR	249	dev_err(&pdev->dev, "request_irq failed\n");
285f2dda	250	goto err_irq;
6baff7f9 GJ	251	}
	252
	253	sc->irq = pdev->irq;
	254
eb93e891	255	ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
285f2dda S	256	if (ret) {
	257	dev_err(&pdev->dev, "Failed to initialize device\n");
	258	goto err_init;
	259	}
	260
	261	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
c96c31e4 JP	262	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
c96c31e4 JP	263	hw_name, (unsigned long)mem, pdev->irq);
6baff7f9 GJ	264
6baff7f9 GJ	265	return 0;
285f2dda S	266
	267	err_init:
	268	free_irq(sc->irq, sc);
	269	err_irq:
6baff7f9	270	ieee80211_free_hw(hw);
285f2dda	271	err_alloc_hw:
6baff7f9	272	pci_iounmap(pdev, mem);
285f2dda	273	err_iomap:
6baff7f9	274	pci_release_region(pdev, 0);
285f2dda S	275	err_region:
	276	/* Nothing */
	277	err_dma:
6baff7f9 GJ	278	pci_disable_device(pdev);
	279	return ret;
	280	}
	281
	282	static void ath_pci_remove(struct pci_dev *pdev)
	283	{
	284	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
9ac58615	285	struct ath_softc *sc = hw->priv;
ab5132a2	286	void __iomem *mem = sc->mem;
6baff7f9	287
d584747b RM	288	if (!is_ath9k_unloaded)
d584747b RM	289	sc->sc_ah->ah_flags \|= AH_UNPLUGGED;
285f2dda S	290	ath9k_deinit_device(sc);
	291	free_irq(sc->irq, sc);
	292	ieee80211_free_hw(sc->hw);
ab5132a2 PR	293
	294	pci_iounmap(pdev, mem);
	295	pci_disable_device(pdev);
	296	pci_release_region(pdev, 0);
6baff7f9 GJ	297	}
	298
	299	#ifdef CONFIG_PM
	300
f0e94b47	301	static int ath_pci_suspend(struct device *device)
6baff7f9	302	{
f0e94b47	303	struct pci_dev *pdev = to_pci_dev(device);
6baff7f9	304	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
9ac58615	305	struct ath_softc *sc = hw->priv;
6baff7f9	306
08fc5c1b	307	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	308
c31eb8e9 RM	309	/* The device has to be moved to FULLSLEEP forcibly.
	310	* Otherwise the chip never moved to full sleep,
	311	* when no interface is up.
	312	*/
	313	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
	314
6baff7f9 GJ	315	return 0;
	316	}
	317
f0e94b47	318	static int ath_pci_resume(struct device *device)
6baff7f9	319	{
f0e94b47	320	struct pci_dev *pdev = to_pci_dev(device);
6baff7f9	321	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
9ac58615	322	struct ath_softc *sc = hw->priv;
f0214843	323	u32 val;
523c36fc	324
f0214843 JM	325	/*
	326	* Suspend/Resume resets the PCI configuration space, so we have to
	327	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	328	* PCI Tx retries from interfering with C3 CPU state
	329	*/
	330	pci_read_config_dword(pdev, 0x40, &val);
	331	if ((val & 0x0000ff00) != 0)
	332	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	333
6baff7f9 GJ	334	/* Enable LED */
08fc5c1b	335	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	336	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	337	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	338
db7ec38d MSS	339	/*
	340	* Reset key cache to sane defaults (all entries cleared) instead of
	341	* semi-random values after suspend/resume.
	342	*/
	343	ath9k_ps_wakeup(sc);
f82b4bde	344	ath9k_cmn_init_crypto(sc->sc_ah);
db7ec38d MSS	345	ath9k_ps_restore(sc);
db7ec38d MSS	346
a08e7ade LR	347	sc->ps_idle = true;
	348	ath_radio_disable(sc, hw);
	349
6baff7f9 GJ	350	return 0;
	351	}
	352
f0e94b47 RW	353	static const struct dev_pm_ops ath9k_pm_ops = {
	354	.suspend = ath_pci_suspend,
	355	.resume = ath_pci_resume,
	356	.freeze = ath_pci_suspend,
	357	.thaw = ath_pci_resume,
	358	.poweroff = ath_pci_suspend,
	359	.restore = ath_pci_resume,
	360	};
	361
	362	#define ATH9K_PM_OPS (&ath9k_pm_ops)
	363
	364	#else /* !CONFIG_PM */
	365
	366	#define ATH9K_PM_OPS NULL
	367
	368	#endif /* !CONFIG_PM */
	369
6baff7f9 GJ	370
	371	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	372
	373	static struct pci_driver ath_pci_driver = {
	374	.name = "ath9k",
	375	.id_table = ath_pci_id_table,
	376	.probe = ath_pci_probe,
	377	.remove = ath_pci_remove,
f0e94b47	378	.driver.pm = ATH9K_PM_OPS,
6baff7f9 GJ	379	};
6baff7f9 GJ	380
db0f41f5	381	int ath_pci_init(void)
6baff7f9 GJ	382	{
	383	return pci_register_driver(&ath_pci_driver);
	384	}
	385
	386	void ath_pci_exit(void)
	387	{
	388	pci_unregister_driver(&ath_pci_driver);
	389	}