[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include <linux/ath9k_platform.h>
#include "ath9k.h"

static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
	{ 0 }
};

/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unplesant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct ath9k_platform_data *pdata = sc->dev->platform_data;

	if (pdata) {
		if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
			ath_err(common,
				"%s: eeprom read failed, offset %08x is out of range\n",
				__func__, off);
		}

		*data = pdata->eeprom_data[off];
	} else {
		struct ath_hw *ah = (struct ath_hw *) common->ah;

		common->ops->read(ah, AR5416_EEPROM_OFFSET +
				      (off << AR5416_EEPROM_S));

		if (!ath9k_hw_wait(ah,
				   AR_EEPROM_STATUS_DATA,
				   AR_EEPROM_STATUS_DATA_BUSY |
				   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
				   AH_WAIT_TIMEOUT)) {
			return false;
		}

		*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
			   AR_EEPROM_STATUS_DATA_VAL);
	}

	return true;
}

/*
 * Bluetooth coexistance requires disabling ASPM.
 */
static void ath_pci_bt_coex_prep(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 aspm;

	if (!pdev->is_pcie)
		return;

	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
}

static void ath_pci_extn_synch_enable(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 lnkctl;

	pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
	lnkctl |= PCI_EXP_LNKCTL_ES;
	pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath_pci_read_cachesize,
	.eeprom_read = ath_pci_eeprom_read,
	.bt_coex_prep = ath_pci_bt_coex_prep,
	.extn_synch_en = ath_pci_extn_synch_enable,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_wiphy *aphy;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u16 subsysid;
	u32 val;
	int ret = 0;
	char hw_name[64];

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto err_dma;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto err_dma;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto err_region;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto err_iomap;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
				sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_alloc_hw;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	aphy = hw->priv;
	sc = (struct ath_softc *) (aphy + 1);
	aphy->sc = sc;
	aphy->hw = hw;
	sc->pri_wiphy = aphy;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;

	/* Will be cleared in ath9k_start() */
	sc->sc_flags |= SC_OP_INVALID;

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto err_irq;
	}

	sc->irq = pdev->irq;

	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize device\n");
		goto err_init;
	}

	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
		   hw_name, (unsigned long)mem, pdev->irq);

	return 0;

err_init:
	free_irq(sc->irq, sc);
err_irq:
	ieee80211_free_hw(hw);
err_alloc_hw:
	pci_iounmap(pdev, mem);
err_iomap:
	pci_release_region(pdev, 0);
err_region:
	/* Nothing */
err_dma:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	void __iomem *mem = sc->mem;

	ath9k_deinit_device(sc);
	free_irq(sc->irq, sc);
	ieee80211_free_hw(sc->hw);

	pci_iounmap(pdev, mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

static int ath_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	u32 val;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

static const struct dev_pm_ops ath9k_pm_ops = {
	.suspend = ath_pci_suspend,
	.resume = ath_pci_resume,
	.freeze = ath_pci_suspend,
	.thaw = ath_pci_resume,
	.poweroff = ath_pci_suspend,
	.restore = ath_pci_resume,
};

#define ATH9K_PM_OPS	(&ath9k_pm_ops)

#else /* !CONFIG_PM */

#define ATH9K_PM_OPS	NULL

#endif /* !CONFIG_PM */


MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
	.driver.pm  = ATH9K_PM_OPS,
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
a05b5d45	19	#include <linux/ath9k_platform.h>
394cf0a1	20	#include "ath9k.h"
6baff7f9	21
a3aa1884	22	static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
6baff7f9 GJ	23	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	24	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	25	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	26	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	27	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	28	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
5ffaf8a3	29	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
ac88b6ec VN	30	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	31	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
0efabd51	32	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
6baff7f9 GJ	33	{ 0 }
	34	};
	35
	36	/* return bus cachesize in 4B word units */
5bb12791	37	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	38	{
bc974f4a	39	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	40	u8 u8tmp;
6baff7f9 GJ	41
f020979d	42	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	43	*csz = (int)u8tmp;
	44
	45	/*
	46	* This check was put in to avoid "unplesant" consequences if
	47	* the bootrom has not fully initialized all PCI devices.
	48	* Sometimes the cache line size register is not set
	49	*/
	50
	51	if (*csz == 0)
	52	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	53	}
	54
5bb12791	55	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	56	{
a05b5d45 FF	57	struct ath_softc sc = (struct ath_softc ) common->priv;
	58	struct ath9k_platform_data *pdata = sc->dev->platform_data;
	59
	60	if (pdata) {
	61	if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
3800276a JP	62	ath_err(common,
	63	"%s: eeprom read failed, offset %08x is out of range\n",
	64	__func__, off);
a05b5d45 FF	65	}
	66
	67	*data = pdata->eeprom_data[off];
	68	} else {
	69	struct ath_hw ah = (struct ath_hw ) common->ah;
	70
	71	common->ops->read(ah, AR5416_EEPROM_OFFSET +
	72	(off << AR5416_EEPROM_S));
	73
	74	if (!ath9k_hw_wait(ah,
	75	AR_EEPROM_STATUS_DATA,
	76	AR_EEPROM_STATUS_DATA_BUSY \|
	77	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
	78	AH_WAIT_TIMEOUT)) {
	79	return false;
	80	}
	81
	82	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
	83	AR_EEPROM_STATUS_DATA_VAL);
9dbeb91a GJ	84	}
9dbeb91a GJ	85
9dbeb91a GJ	86	return true;
	87	}
	88
867633f0 LR	89	/*
	90	* Bluetooth coexistance requires disabling ASPM.
	91	*/
5bb12791	92	static void ath_pci_bt_coex_prep(struct ath_common *common)
867633f0	93	{
bc974f4a	94	struct ath_softc sc = (struct ath_softc ) common->priv;
867633f0 LR	95	struct pci_dev *pdev = to_pci_dev(sc->dev);
	96	u8 aspm;
	97
	98	if (!pdev->is_pcie)
	99	return;
	100
	101	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	102	aspm &= ~(ATH_PCIE_CAP_LINK_L0S \| ATH_PCIE_CAP_LINK_L1);
	103	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
	104	}
	105
8060e169 VT	106	static void ath_pci_extn_synch_enable(struct ath_common *common)
	107	{
	108	struct ath_softc sc = (struct ath_softc ) common->priv;
	109	struct pci_dev *pdev = to_pci_dev(sc->dev);
	110	u8 lnkctl;
	111
	112	pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
	113	lnkctl \|= PCI_EXP_LNKCTL_ES;
	114	pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
	115	}
	116
83bd11a0	117	static const struct ath_bus_ops ath_pci_bus_ops = {
497ad9ad	118	.ath_bus_type = ATH_PCI,
6baff7f9	119	.read_cachesize = ath_pci_read_cachesize,
9dbeb91a	120	.eeprom_read = ath_pci_eeprom_read,
867633f0	121	.bt_coex_prep = ath_pci_bt_coex_prep,
8060e169	122	.extn_synch_en = ath_pci_extn_synch_enable,
6baff7f9 GJ	123	};
	124
	125	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	126	{
	127	void __iomem *mem;
bce048d7	128	struct ath_wiphy *aphy;
6baff7f9 GJ	129	struct ath_softc *sc;
	130	struct ieee80211_hw *hw;
	131	u8 csz;
aeac355d	132	u16 subsysid;
f0214843	133	u32 val;
6baff7f9	134	int ret = 0;
f934c4d9	135	char hw_name[64];
6baff7f9 GJ	136
	137	if (pci_enable_device(pdev))
	138	return -EIO;
	139
e930438c	140	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	141	if (ret) {
6baff7f9 GJ	142	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
285f2dda	143	goto err_dma;
6baff7f9 GJ	144	}
6baff7f9 GJ	145
e930438c	146	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	147	if (ret) {
	148	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	149	"DMA enable failed\n");
285f2dda	150	goto err_dma;
6baff7f9 GJ	151	}
	152
	153	/*
	154	* Cache line size is used to size and align various
	155	* structures used to communicate with the hardware.
	156	*/
	157	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	158	if (csz == 0) {
	159	/*
	160	* Linux 2.4.18 (at least) writes the cache line size
	161	* register as a 16-bit wide register which is wrong.
	162	* We must have this setup properly for rx buffer
	163	* DMA to work so force a reasonable value here if it
	164	* comes up zero.
	165	*/
	166	csz = L1_CACHE_BYTES / sizeof(u32);
	167	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	168	}
	169	/*
	170	* The default setting of latency timer yields poor results,
	171	* set it to the value used by other systems. It may be worth
	172	* tweaking this setting more.
	173	*/
	174	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	175
	176	pci_set_master(pdev);
	177
f0214843 JM	178	/*
	179	* Disable the RETRY_TIMEOUT register (0x41) to keep
	180	* PCI Tx retries from interfering with C3 CPU state.
	181	*/
	182	pci_read_config_dword(pdev, 0x40, &val);
	183	if ((val & 0x0000ff00) != 0)
	184	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	185
6baff7f9 GJ	186	ret = pci_request_region(pdev, 0, "ath9k");
	187	if (ret) {
	188	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	189	ret = -ENODEV;
285f2dda	190	goto err_region;
6baff7f9 GJ	191	}
	192
	193	mem = pci_iomap(pdev, 0, 0);
	194	if (!mem) {
	195	printk(KERN_ERR "PCI memory map error\n") ;
	196	ret = -EIO;
285f2dda	197	goto err_iomap;
6baff7f9 GJ	198	}
6baff7f9 GJ	199
bce048d7 JM	200	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
bce048d7 JM	201	sizeof(struct ath_softc), &ath9k_ops);
db6be53c	202	if (!hw) {
285f2dda	203	dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
db6be53c	204	ret = -ENOMEM;
285f2dda	205	goto err_alloc_hw;
6baff7f9 GJ	206	}
	207
	208	SET_IEEE80211_DEV(hw, &pdev->dev);
	209	pci_set_drvdata(pdev, hw);
	210
bce048d7 JM	211	aphy = hw->priv;
	212	sc = (struct ath_softc *) (aphy + 1);
	213	aphy->sc = sc;
	214	aphy->hw = hw;
	215	sc->pri_wiphy = aphy;
6baff7f9 GJ	216	sc->hw = hw;
	217	sc->dev = &pdev->dev;
	218	sc->mem = mem;
6baff7f9	219
5e4ea1f0 S	220	/* Will be cleared in ath9k_start() */
5e4ea1f0 S	221	sc->sc_flags \|= SC_OP_INVALID;
6baff7f9	222
fc548af8	223	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	224	if (ret) {
580171f7 LR	225	dev_err(&pdev->dev, "request_irq failed\n");
285f2dda	226	goto err_irq;
6baff7f9 GJ	227	}
	228
	229	sc->irq = pdev->irq;
	230
285f2dda S	231	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	232	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	233	if (ret) {
	234	dev_err(&pdev->dev, "Failed to initialize device\n");
	235	goto err_init;
	236	}
	237
	238	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
c96c31e4 JP	239	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
c96c31e4 JP	240	hw_name, (unsigned long)mem, pdev->irq);
6baff7f9 GJ	241
6baff7f9 GJ	242	return 0;
285f2dda S	243
	244	err_init:
	245	free_irq(sc->irq, sc);
	246	err_irq:
6baff7f9	247	ieee80211_free_hw(hw);
285f2dda	248	err_alloc_hw:
6baff7f9	249	pci_iounmap(pdev, mem);
285f2dda	250	err_iomap:
6baff7f9	251	pci_release_region(pdev, 0);
285f2dda S	252	err_region:
	253	/* Nothing */
	254	err_dma:
6baff7f9 GJ	255	pci_disable_device(pdev);
	256	return ret;
	257	}
	258
	259	static void ath_pci_remove(struct pci_dev *pdev)
	260	{
	261	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	262	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	263	struct ath_softc *sc = aphy->sc;
ab5132a2	264	void __iomem *mem = sc->mem;
6baff7f9	265
285f2dda S	266	ath9k_deinit_device(sc);
	267	free_irq(sc->irq, sc);
	268	ieee80211_free_hw(sc->hw);
ab5132a2 PR	269
	270	pci_iounmap(pdev, mem);
	271	pci_disable_device(pdev);
	272	pci_release_region(pdev, 0);
6baff7f9 GJ	273	}
	274
	275	#ifdef CONFIG_PM
	276
f0e94b47	277	static int ath_pci_suspend(struct device *device)
6baff7f9	278	{
f0e94b47	279	struct pci_dev *pdev = to_pci_dev(device);
6baff7f9	280	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	281	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	282	struct ath_softc *sc = aphy->sc;
6baff7f9	283
08fc5c1b	284	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	285
6baff7f9 GJ	286	return 0;
	287	}
	288
f0e94b47	289	static int ath_pci_resume(struct device *device)
6baff7f9	290	{
f0e94b47	291	struct pci_dev *pdev = to_pci_dev(device);
6baff7f9	292	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	293	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	294	struct ath_softc *sc = aphy->sc;
f0214843	295	u32 val;
523c36fc	296
f0214843 JM	297	/*
	298	* Suspend/Resume resets the PCI configuration space, so we have to
	299	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	300	* PCI Tx retries from interfering with C3 CPU state
	301	*/
	302	pci_read_config_dword(pdev, 0x40, &val);
	303	if ((val & 0x0000ff00) != 0)
	304	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	305
6baff7f9 GJ	306	/* Enable LED */
08fc5c1b	307	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	308	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	309	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	310
6baff7f9 GJ	311	return 0;
	312	}
	313
f0e94b47 RW	314	static const struct dev_pm_ops ath9k_pm_ops = {
	315	.suspend = ath_pci_suspend,
	316	.resume = ath_pci_resume,
	317	.freeze = ath_pci_suspend,
	318	.thaw = ath_pci_resume,
	319	.poweroff = ath_pci_suspend,
	320	.restore = ath_pci_resume,
	321	};
	322
	323	#define ATH9K_PM_OPS (&ath9k_pm_ops)
	324
	325	#else /* !CONFIG_PM */
	326
	327	#define ATH9K_PM_OPS NULL
	328
	329	#endif /* !CONFIG_PM */
	330
6baff7f9 GJ	331
	332	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	333
	334	static struct pci_driver ath_pci_driver = {
	335	.name = "ath9k",
	336	.id_table = ath_pci_id_table,
	337	.probe = ath_pci_probe,
	338	.remove = ath_pci_remove,
f0e94b47	339	.driver.pm = ATH9K_PM_OPS,
6baff7f9 GJ	340	};
6baff7f9 GJ	341
db0f41f5	342	int ath_pci_init(void)
6baff7f9 GJ	343	{
	344	return pci_register_driver(&ath_pci_driver);
	345	}
	346
	347	void ath_pci_exit(void)
	348	{
	349	pci_unregister_driver(&ath_pci_driver);
	350	}