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f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209 20
b5c80475
FF
21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
102885a5
VT
23static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26{
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30}
31
b85c5734
MSS
32static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35{
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
66ce235a 43 case 2:
b85c5734
MSS
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58}
59
ededf1f8
VT
60static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61{
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64}
65
f078f209
LR
66/*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
f078f209 73 */
f078f209
LR
74static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75{
cbe61d8a 76 struct ath_hw *ah = sc->sc_ah;
cc861f74 77 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR
78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
be0418ad 84 ds->ds_link = 0; /* link to null */
f078f209
LR
85 ds->ds_data = bf->bf_buf_addr;
86
be0418ad 87 /* virtual addr of the beginning of the buffer. */
f078f209 88 skb = bf->bf_mpdu;
9680e8a3 89 BUG_ON(skb == NULL);
f078f209
LR
90 ds->ds_vdata = skb->data;
91
cc861f74
LR
92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
b4b6cda2 94 * how much data it can DMA to us and that we are prepared
cc861f74
LR
95 * to process
96 */
b77f483f 97 ath9k_hw_setuprxdesc(ah, ds,
cc861f74 98 common->rx_bufsize,
f078f209
LR
99 0);
100
b77f483f 101 if (sc->rx.rxlink == NULL)
f078f209
LR
102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
b77f483f 104 *sc->rx.rxlink = bf->bf_daddr;
f078f209 105
b77f483f 106 sc->rx.rxlink = &ds->ds_link;
f078f209
LR
107}
108
ff37e337
S
109static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110{
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
b77f483f
S
113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
ff37e337
S
115}
116
f078f209
LR
117static void ath_opmode_init(struct ath_softc *sc)
118{
cbe61d8a 119 struct ath_hw *ah = sc->sc_ah;
1510718d
LR
120 struct ath_common *common = ath9k_hw_common(ah);
121
f078f209
LR
122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
364734fa 129 ath_hw_setbssidmask(common);
f078f209
LR
130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
f078f209
LR
134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
f078f209 136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
f078f209
LR
137}
138
b5c80475
FF
139static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
f078f209 141{
b5c80475
FF
142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
f078f209
LR
144 struct sk_buff *skb;
145 struct ath_buf *bf;
f078f209 146
b5c80475
FF
147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
f078f209 150
b5c80475
FF
151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
f078f209 153
b5c80475
FF
154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
f078f209 160
b5c80475
FF
161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
f078f209 164
b5c80475
FF
165 return true;
166}
167
168static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170{
b5c80475
FF
171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
172 u32 nbuf = 0;
173
b5c80475 174 if (list_empty(&sc->rx.rxbuf)) {
226afe68 175 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
b5c80475 176 return;
797fe5cb 177 }
f078f209 178
b5c80475
FF
179 while (!list_empty(&sc->rx.rxbuf)) {
180 nbuf++;
181
182 if (!ath_rx_edma_buf_link(sc, qtype))
183 break;
184
185 if (nbuf >= size)
186 break;
187 }
188}
189
190static void ath_rx_remove_buffer(struct ath_softc *sc,
191 enum ath9k_rx_qtype qtype)
192{
193 struct ath_buf *bf;
194 struct ath_rx_edma *rx_edma;
195 struct sk_buff *skb;
196
197 rx_edma = &sc->rx.rx_edma[qtype];
198
199 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
200 bf = SKB_CB_ATHBUF(skb);
201 BUG_ON(!bf);
202 list_add_tail(&bf->list, &sc->rx.rxbuf);
203 }
204}
205
206static void ath_rx_edma_cleanup(struct ath_softc *sc)
207{
ba542385
MSS
208 struct ath_hw *ah = sc->sc_ah;
209 struct ath_common *common = ath9k_hw_common(ah);
b5c80475
FF
210 struct ath_buf *bf;
211
212 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
213 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
214
797fe5cb 215 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
ba542385
MSS
216 if (bf->bf_mpdu) {
217 dma_unmap_single(sc->dev, bf->bf_buf_addr,
218 common->rx_bufsize,
219 DMA_BIDIRECTIONAL);
b5c80475 220 dev_kfree_skb_any(bf->bf_mpdu);
ba542385
MSS
221 bf->bf_buf_addr = 0;
222 bf->bf_mpdu = NULL;
223 }
b5c80475
FF
224 }
225
226 INIT_LIST_HEAD(&sc->rx.rxbuf);
227
228 kfree(sc->rx.rx_bufptr);
229 sc->rx.rx_bufptr = NULL;
230}
231
232static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
233{
234 skb_queue_head_init(&rx_edma->rx_fifo);
235 skb_queue_head_init(&rx_edma->rx_buffers);
236 rx_edma->rx_fifo_hwsize = size;
237}
238
239static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
240{
241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
242 struct ath_hw *ah = sc->sc_ah;
243 struct sk_buff *skb;
244 struct ath_buf *bf;
245 int error = 0, i;
246 u32 size;
247
b5c80475
FF
248 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
249 ah->caps.rx_status_len);
250
251 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
252 ah->caps.rx_lp_qdepth);
253 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
254 ah->caps.rx_hp_qdepth);
255
256 size = sizeof(struct ath_buf) * nbufs;
257 bf = kzalloc(size, GFP_KERNEL);
258 if (!bf)
259 return -ENOMEM;
260
261 INIT_LIST_HEAD(&sc->rx.rxbuf);
262 sc->rx.rx_bufptr = bf;
263
264 for (i = 0; i < nbufs; i++, bf++) {
cc861f74 265 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
b5c80475 266 if (!skb) {
797fe5cb 267 error = -ENOMEM;
b5c80475 268 goto rx_init_fail;
f078f209 269 }
f078f209 270
b5c80475 271 memset(skb->data, 0, common->rx_bufsize);
797fe5cb 272 bf->bf_mpdu = skb;
b5c80475 273
797fe5cb 274 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
cc861f74 275 common->rx_bufsize,
b5c80475 276 DMA_BIDIRECTIONAL);
797fe5cb 277 if (unlikely(dma_mapping_error(sc->dev,
b5c80475
FF
278 bf->bf_buf_addr))) {
279 dev_kfree_skb_any(skb);
280 bf->bf_mpdu = NULL;
6cf9e995 281 bf->bf_buf_addr = 0;
3800276a 282 ath_err(common,
b5c80475
FF
283 "dma_mapping_error() on RX init\n");
284 error = -ENOMEM;
285 goto rx_init_fail;
286 }
287
288 list_add_tail(&bf->list, &sc->rx.rxbuf);
289 }
290
291 return 0;
292
293rx_init_fail:
294 ath_rx_edma_cleanup(sc);
295 return error;
296}
297
298static void ath_edma_start_recv(struct ath_softc *sc)
299{
300 spin_lock_bh(&sc->rx.rxbuflock);
301
302 ath9k_hw_rxena(sc->sc_ah);
303
304 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
305 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
306
307 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
308 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
309
b5c80475
FF
310 ath_opmode_init(sc);
311
48a6a468 312 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
7583c550
LR
313
314 spin_unlock_bh(&sc->rx.rxbuflock);
b5c80475
FF
315}
316
317static void ath_edma_stop_recv(struct ath_softc *sc)
318{
b5c80475
FF
319 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
320 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
b5c80475
FF
321}
322
323int ath_rx_init(struct ath_softc *sc, int nbufs)
324{
325 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
326 struct sk_buff *skb;
327 struct ath_buf *bf;
328 int error = 0;
329
4bdd1e97 330 spin_lock_init(&sc->sc_pcu_lock);
b5c80475
FF
331 sc->sc_flags &= ~SC_OP_RXFLUSH;
332 spin_lock_init(&sc->rx.rxbuflock);
333
0d95521e
FF
334 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
335 sc->sc_ah->caps.rx_status_len;
336
b5c80475
FF
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
338 return ath_rx_edma_init(sc, nbufs);
339 } else {
226afe68
JP
340 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
341 common->cachelsz, common->rx_bufsize);
b5c80475
FF
342
343 /* Initialize rx descriptors */
344
345 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
4adfcded 346 "rx", nbufs, 1, 0);
b5c80475 347 if (error != 0) {
3800276a
JP
348 ath_err(common,
349 "failed to allocate rx descriptors: %d\n",
350 error);
797fe5cb
S
351 goto err;
352 }
b5c80475
FF
353
354 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
355 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
356 GFP_KERNEL);
357 if (skb == NULL) {
358 error = -ENOMEM;
359 goto err;
360 }
361
362 bf->bf_mpdu = skb;
363 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
364 common->rx_bufsize,
365 DMA_FROM_DEVICE);
366 if (unlikely(dma_mapping_error(sc->dev,
367 bf->bf_buf_addr))) {
368 dev_kfree_skb_any(skb);
369 bf->bf_mpdu = NULL;
6cf9e995 370 bf->bf_buf_addr = 0;
3800276a
JP
371 ath_err(common,
372 "dma_mapping_error() on RX init\n");
b5c80475
FF
373 error = -ENOMEM;
374 goto err;
375 }
b5c80475
FF
376 }
377 sc->rx.rxlink = NULL;
797fe5cb 378 }
f078f209 379
797fe5cb 380err:
f078f209
LR
381 if (error)
382 ath_rx_cleanup(sc);
383
384 return error;
385}
386
f078f209
LR
387void ath_rx_cleanup(struct ath_softc *sc)
388{
cc861f74
LR
389 struct ath_hw *ah = sc->sc_ah;
390 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR
391 struct sk_buff *skb;
392 struct ath_buf *bf;
393
b5c80475
FF
394 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
395 ath_rx_edma_cleanup(sc);
396 return;
397 } else {
398 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
399 skb = bf->bf_mpdu;
400 if (skb) {
401 dma_unmap_single(sc->dev, bf->bf_buf_addr,
402 common->rx_bufsize,
403 DMA_FROM_DEVICE);
404 dev_kfree_skb(skb);
6cf9e995
BG
405 bf->bf_buf_addr = 0;
406 bf->bf_mpdu = NULL;
b5c80475 407 }
051b9191 408 }
f078f209 409
b5c80475
FF
410 if (sc->rx.rxdma.dd_desc_len != 0)
411 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
412 }
f078f209
LR
413}
414
415/*
416 * Calculate the receive filter according to the
417 * operating mode and state:
418 *
419 * o always accept unicast, broadcast, and multicast traffic
420 * o maintain current state of phy error reception (the hal
421 * may enable phy error frames for noise immunity work)
422 * o probe request frames are accepted only when operating in
423 * hostap, adhoc, or monitor modes
424 * o enable promiscuous mode according to the interface state
425 * o accept beacons:
426 * - when operating in adhoc mode so the 802.11 layer creates
427 * node table entries for peers,
428 * - when operating in station mode for collecting rssi data when
429 * the station is otherwise quiet, or
430 * - when operating as a repeater so we see repeater-sta beacons
431 * - when scanning
432 */
433
434u32 ath_calcrxfilter(struct ath_softc *sc)
435{
f078f209
LR
436 u32 rfilt;
437
ac06697c 438 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
f078f209
LR
439 | ATH9K_RX_FILTER_MCAST;
440
9c1d8e4a 441 if (sc->rx.rxfilter & FIF_PROBE_REQ)
f078f209
LR
442 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
443
217ba9da
JM
444 /*
445 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
446 * mode interface or when in monitor mode. AP mode does not need this
447 * since it receives all in-BSS frames anyway.
448 */
2e286947 449 if (sc->sc_ah->is_monitoring)
f078f209 450 rfilt |= ATH9K_RX_FILTER_PROM;
f078f209 451
d42c6b71
S
452 if (sc->rx.rxfilter & FIF_CONTROL)
453 rfilt |= ATH9K_RX_FILTER_CONTROL;
454
dbaaa147 455 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
cfda6695 456 (sc->nvifs <= 1) &&
dbaaa147
VT
457 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
458 rfilt |= ATH9K_RX_FILTER_MYBEACON;
459 else
f078f209
LR
460 rfilt |= ATH9K_RX_FILTER_BEACON;
461
264bbec8 462 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
66afad01 463 (sc->rx.rxfilter & FIF_PSPOLL))
dbaaa147 464 rfilt |= ATH9K_RX_FILTER_PSPOLL;
be0418ad 465
7ea310be
S
466 if (conf_is_ht(&sc->hw->conf))
467 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
468
7545daf4 469 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
5eb6ba83
JC
470 /* The following may also be needed for other older chips */
471 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
472 rfilt |= ATH9K_RX_FILTER_PROM;
b93bce2a
JM
473 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
474 }
475
f078f209 476 return rfilt;
7dcfdcd9 477
f078f209
LR
478#undef RX_FILTER_PRESERVE
479}
480
f078f209
LR
481int ath_startrecv(struct ath_softc *sc)
482{
cbe61d8a 483 struct ath_hw *ah = sc->sc_ah;
f078f209
LR
484 struct ath_buf *bf, *tbf;
485
b5c80475
FF
486 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
487 ath_edma_start_recv(sc);
488 return 0;
489 }
490
b77f483f
S
491 spin_lock_bh(&sc->rx.rxbuflock);
492 if (list_empty(&sc->rx.rxbuf))
f078f209
LR
493 goto start_recv;
494
b77f483f
S
495 sc->rx.rxlink = NULL;
496 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
f078f209
LR
497 ath_rx_buf_link(sc, bf);
498 }
499
500 /* We could have deleted elements so the list may be empty now */
b77f483f 501 if (list_empty(&sc->rx.rxbuf))
f078f209
LR
502 goto start_recv;
503
b77f483f 504 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
f078f209 505 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
be0418ad 506 ath9k_hw_rxena(ah);
f078f209
LR
507
508start_recv:
be0418ad 509 ath_opmode_init(sc);
48a6a468 510 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
be0418ad 511
7583c550
LR
512 spin_unlock_bh(&sc->rx.rxbuflock);
513
f078f209
LR
514 return 0;
515}
516
f078f209
LR
517bool ath_stoprecv(struct ath_softc *sc)
518{
cbe61d8a 519 struct ath_hw *ah = sc->sc_ah;
5882da02 520 bool stopped, reset = false;
f078f209 521
1e450285 522 spin_lock_bh(&sc->rx.rxbuflock);
d47844a0 523 ath9k_hw_abortpcurecv(ah);
be0418ad 524 ath9k_hw_setrxfilter(ah, 0);
5882da02 525 stopped = ath9k_hw_stopdmarecv(ah, &reset);
b5c80475
FF
526
527 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
528 ath_edma_stop_recv(sc);
529 else
530 sc->rx.rxlink = NULL;
1e450285 531 spin_unlock_bh(&sc->rx.rxbuflock);
be0418ad 532
d584747b
RM
533 if (!(ah->ah_flags & AH_UNPLUGGED) &&
534 unlikely(!stopped)) {
d7fd1b50
BG
535 ath_err(ath9k_hw_common(sc->sc_ah),
536 "Could not stop RX, we could be "
537 "confusing the DMA engine when we start RX up\n");
538 ATH_DBG_WARN_ON_ONCE(!stopped);
539 }
2232d31b 540 return stopped && !reset;
f078f209
LR
541}
542
f078f209
LR
543void ath_flushrecv(struct ath_softc *sc)
544{
98deeea0 545 sc->sc_flags |= SC_OP_RXFLUSH;
b5c80475
FF
546 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
547 ath_rx_tasklet(sc, 1, true);
548 ath_rx_tasklet(sc, 1, false);
98deeea0 549 sc->sc_flags &= ~SC_OP_RXFLUSH;
f078f209
LR
550}
551
cc65965c
JM
552static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
553{
554 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
555 struct ieee80211_mgmt *mgmt;
556 u8 *pos, *end, id, elen;
557 struct ieee80211_tim_ie *tim;
558
559 mgmt = (struct ieee80211_mgmt *)skb->data;
560 pos = mgmt->u.beacon.variable;
561 end = skb->data + skb->len;
562
563 while (pos + 2 < end) {
564 id = *pos++;
565 elen = *pos++;
566 if (pos + elen > end)
567 break;
568
569 if (id == WLAN_EID_TIM) {
570 if (elen < sizeof(*tim))
571 break;
572 tim = (struct ieee80211_tim_ie *) pos;
573 if (tim->dtim_count != 0)
574 break;
575 return tim->bitmap_ctrl & 0x01;
576 }
577
578 pos += elen;
579 }
580
581 return false;
582}
583
cc65965c
JM
584static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
585{
1510718d 586 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM
587
588 if (skb->len < 24 + 8 + 2 + 2)
589 return;
590
1b04b930 591 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
293dc5df 592
1b04b930
S
593 if (sc->ps_flags & PS_BEACON_SYNC) {
594 sc->ps_flags &= ~PS_BEACON_SYNC;
226afe68
JP
595 ath_dbg(common, ATH_DBG_PS,
596 "Reconfigure Beacon timers based on timestamp from the AP\n");
99e4d43a 597 ath_set_beacon(sc);
ccdfeab6
JM
598 }
599
cc65965c
JM
600 if (ath_beacon_dtim_pending_cab(skb)) {
601 /*
602 * Remain awake waiting for buffered broadcast/multicast
58f5fffd
GJ
603 * frames. If the last broadcast/multicast frame is not
604 * received properly, the next beacon frame will work as
605 * a backup trigger for returning into NETWORK SLEEP state,
606 * so we are waiting for it as well.
cc65965c 607 */
226afe68
JP
608 ath_dbg(common, ATH_DBG_PS,
609 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
1b04b930 610 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
cc65965c
JM
611 return;
612 }
613
1b04b930 614 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
cc65965c
JM
615 /*
616 * This can happen if a broadcast frame is dropped or the AP
617 * fails to send a frame indicating that all CAB frames have
618 * been delivered.
619 */
1b04b930 620 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
226afe68
JP
621 ath_dbg(common, ATH_DBG_PS,
622 "PS wait for CAB frames timed out\n");
cc65965c 623 }
cc65965c
JM
624}
625
f73c604c 626static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
cc65965c
JM
627{
628 struct ieee80211_hdr *hdr;
c46917bb 629 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM
630
631 hdr = (struct ieee80211_hdr *)skb->data;
632
633 /* Process Beacon and CAB receive in PS state */
ededf1f8 634 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
f73c604c 635 && mybeacon)
cc65965c 636 ath_rx_ps_beacon(sc, skb);
1b04b930 637 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
cc65965c
JM
638 (ieee80211_is_data(hdr->frame_control) ||
639 ieee80211_is_action(hdr->frame_control)) &&
640 is_multicast_ether_addr(hdr->addr1) &&
641 !ieee80211_has_moredata(hdr->frame_control)) {
cc65965c
JM
642 /*
643 * No more broadcast/multicast frames to be received at this
644 * point.
645 */
3fac6dfd 646 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
226afe68
JP
647 ath_dbg(common, ATH_DBG_PS,
648 "All PS CAB frames received, back to sleep\n");
1b04b930 649 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
9a23f9ca
JM
650 !is_multicast_ether_addr(hdr->addr1) &&
651 !ieee80211_has_morefrags(hdr->frame_control)) {
1b04b930 652 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
226afe68
JP
653 ath_dbg(common, ATH_DBG_PS,
654 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
1b04b930
S
655 sc->ps_flags & (PS_WAIT_FOR_BEACON |
656 PS_WAIT_FOR_CAB |
657 PS_WAIT_FOR_PSPOLL_DATA |
658 PS_WAIT_FOR_TX_ACK));
cc65965c
JM
659 }
660}
661
b5c80475
FF
662static bool ath_edma_get_buffers(struct ath_softc *sc,
663 enum ath9k_rx_qtype qtype)
f078f209 664{
b5c80475
FF
665 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
666 struct ath_hw *ah = sc->sc_ah;
667 struct ath_common *common = ath9k_hw_common(ah);
668 struct sk_buff *skb;
669 struct ath_buf *bf;
670 int ret;
671
672 skb = skb_peek(&rx_edma->rx_fifo);
673 if (!skb)
674 return false;
675
676 bf = SKB_CB_ATHBUF(skb);
677 BUG_ON(!bf);
678
ce9426d1 679 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF
680 common->rx_bufsize, DMA_FROM_DEVICE);
681
682 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
ce9426d1
ML
683 if (ret == -EINPROGRESS) {
684 /*let device gain the buffer again*/
685 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
686 common->rx_bufsize, DMA_FROM_DEVICE);
b5c80475 687 return false;
ce9426d1 688 }
b5c80475
FF
689
690 __skb_unlink(skb, &rx_edma->rx_fifo);
691 if (ret == -EINVAL) {
692 /* corrupt descriptor, skip this one and the following one */
693 list_add_tail(&bf->list, &sc->rx.rxbuf);
694 ath_rx_edma_buf_link(sc, qtype);
695 skb = skb_peek(&rx_edma->rx_fifo);
696 if (!skb)
697 return true;
698
699 bf = SKB_CB_ATHBUF(skb);
700 BUG_ON(!bf);
701
702 __skb_unlink(skb, &rx_edma->rx_fifo);
703 list_add_tail(&bf->list, &sc->rx.rxbuf);
704 ath_rx_edma_buf_link(sc, qtype);
083e3e8d 705 return true;
b5c80475
FF
706 }
707 skb_queue_tail(&rx_edma->rx_buffers, skb);
708
709 return true;
710}
f078f209 711
b5c80475
FF
712static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
713 struct ath_rx_status *rs,
714 enum ath9k_rx_qtype qtype)
715{
716 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
717 struct sk_buff *skb;
be0418ad 718 struct ath_buf *bf;
b5c80475
FF
719
720 while (ath_edma_get_buffers(sc, qtype));
721 skb = __skb_dequeue(&rx_edma->rx_buffers);
722 if (!skb)
723 return NULL;
724
725 bf = SKB_CB_ATHBUF(skb);
726 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
727 return bf;
728}
729
730static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
731 struct ath_rx_status *rs)
732{
733 struct ath_hw *ah = sc->sc_ah;
734 struct ath_common *common = ath9k_hw_common(ah);
f078f209 735 struct ath_desc *ds;
b5c80475
FF
736 struct ath_buf *bf;
737 int ret;
738
739 if (list_empty(&sc->rx.rxbuf)) {
740 sc->rx.rxlink = NULL;
741 return NULL;
742 }
743
744 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
745 ds = bf->bf_desc;
746
747 /*
748 * Must provide the virtual address of the current
749 * descriptor, the physical address, and the virtual
750 * address of the next descriptor in the h/w chain.
751 * This allows the HAL to look ahead to see if the
752 * hardware is done with a descriptor by checking the
753 * done bit in the following descriptor and the address
754 * of the current descriptor the DMA engine is working
755 * on. All this is necessary because of our use of
756 * a self-linked list to avoid rx overruns.
757 */
3de21116 758 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
b5c80475
FF
759 if (ret == -EINPROGRESS) {
760 struct ath_rx_status trs;
761 struct ath_buf *tbf;
762 struct ath_desc *tds;
763
764 memset(&trs, 0, sizeof(trs));
765 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
766 sc->rx.rxlink = NULL;
767 return NULL;
768 }
769
770 tbf = list_entry(bf->list.next, struct ath_buf, list);
771
772 /*
773 * On some hardware the descriptor status words could
774 * get corrupted, including the done bit. Because of
775 * this, check if the next descriptor's done bit is
776 * set or not.
777 *
778 * If the next descriptor's done bit is set, the current
779 * descriptor has been corrupted. Force s/w to discard
780 * this descriptor and continue...
781 */
782
783 tds = tbf->bf_desc;
3de21116 784 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
b5c80475
FF
785 if (ret == -EINPROGRESS)
786 return NULL;
787 }
788
789 if (!bf->bf_mpdu)
790 return bf;
791
792 /*
793 * Synchronize the DMA transfer with CPU before
794 * 1. accessing the frame
795 * 2. requeueing the same buffer to h/w
796 */
ce9426d1 797 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF
798 common->rx_bufsize,
799 DMA_FROM_DEVICE);
800
801 return bf;
802}
803
d435700f
S
804/* Assumes you've already done the endian to CPU conversion */
805static bool ath9k_rx_accept(struct ath_common *common,
9f167f64 806 struct ieee80211_hdr *hdr,
d435700f
S
807 struct ieee80211_rx_status *rxs,
808 struct ath_rx_status *rx_stats,
809 bool *decrypt_error)
810{
ec205999 811 struct ath_softc *sc = (struct ath_softc *) common->priv;
66760eac 812 bool is_mc, is_valid_tkip, strip_mic, mic_error;
d435700f 813 struct ath_hw *ah = common->ah;
d435700f 814 __le16 fc;
b7b1b512 815 u8 rx_status_len = ah->caps.rx_status_len;
d435700f 816
d435700f
S
817 fc = hdr->frame_control;
818
66760eac
FF
819 is_mc = !!is_multicast_ether_addr(hdr->addr1);
820 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
821 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
152e585d
BJ
822 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
823 !(rx_stats->rs_status &
846d9363
FF
824 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
825 ATH9K_RXERR_KEYMISS));
66760eac 826
d435700f
S
827 if (!rx_stats->rs_datalen)
828 return false;
829 /*
830 * rs_status follows rs_datalen so if rs_datalen is too large
831 * we can take a hint that hardware corrupted it, so ignore
832 * those frames.
833 */
b7b1b512 834 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
d435700f
S
835 return false;
836
0d95521e 837 /* Only use error bits from the last fragment */
d435700f 838 if (rx_stats->rs_more)
0d95521e 839 return true;
d435700f 840
66760eac
FF
841 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
842 !ieee80211_has_morefrags(fc) &&
843 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
844 (rx_stats->rs_status & ATH9K_RXERR_MIC);
845
d435700f
S
846 /*
847 * The rx_stats->rs_status will not be set until the end of the
848 * chained descriptors so it can be ignored if rs_more is set. The
849 * rs_more will be false at the last element of the chained
850 * descriptors.
851 */
852 if (rx_stats->rs_status != 0) {
846d9363
FF
853 u8 status_mask;
854
66760eac 855 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
d435700f 856 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
66760eac
FF
857 mic_error = false;
858 }
d435700f
S
859 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
860 return false;
861
846d9363
FF
862 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
863 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
d435700f 864 *decrypt_error = true;
66760eac 865 mic_error = false;
d435700f 866 }
66760eac 867
d435700f
S
868 /*
869 * Reject error frames with the exception of
870 * decryption and MIC failures. For monitor mode,
871 * we also ignore the CRC error.
872 */
846d9363
FF
873 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
874 ATH9K_RXERR_KEYMISS;
875
ec205999 876 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
846d9363
FF
877 status_mask |= ATH9K_RXERR_CRC;
878
879 if (rx_stats->rs_status & ~status_mask)
880 return false;
d435700f 881 }
66760eac
FF
882
883 /*
884 * For unicast frames the MIC error bit can have false positives,
885 * so all MIC error reports need to be validated in software.
886 * False negatives are not common, so skip software verification
887 * if the hardware considers the MIC valid.
888 */
889 if (strip_mic)
890 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
891 else if (is_mc && mic_error)
892 rxs->flag |= RX_FLAG_MMIC_ERROR;
893
d435700f
S
894 return true;
895}
896
897static int ath9k_process_rate(struct ath_common *common,
898 struct ieee80211_hw *hw,
899 struct ath_rx_status *rx_stats,
9f167f64 900 struct ieee80211_rx_status *rxs)
d435700f
S
901{
902 struct ieee80211_supported_band *sband;
903 enum ieee80211_band band;
904 unsigned int i = 0;
905
906 band = hw->conf.channel->band;
907 sband = hw->wiphy->bands[band];
908
909 if (rx_stats->rs_rate & 0x80) {
910 /* HT rate */
911 rxs->flag |= RX_FLAG_HT;
912 if (rx_stats->rs_flags & ATH9K_RX_2040)
913 rxs->flag |= RX_FLAG_40MHZ;
914 if (rx_stats->rs_flags & ATH9K_RX_GI)
915 rxs->flag |= RX_FLAG_SHORT_GI;
916 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
917 return 0;
918 }
919
920 for (i = 0; i < sband->n_bitrates; i++) {
921 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
922 rxs->rate_idx = i;
923 return 0;
924 }
925 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
926 rxs->flag |= RX_FLAG_SHORTPRE;
927 rxs->rate_idx = i;
928 return 0;
929 }
930 }
931
932 /*
933 * No valid hardware bitrate found -- we should not get here
934 * because hardware has already validated this frame as OK.
935 */
9976f62e 936 ath_dbg(common, ATH_DBG_ANY,
226afe68
JP
937 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
938 rx_stats->rs_rate);
d435700f
S
939
940 return -EINVAL;
941}
942
943static void ath9k_process_rssi(struct ath_common *common,
944 struct ieee80211_hw *hw,
9f167f64 945 struct ieee80211_hdr *hdr,
d435700f
S
946 struct ath_rx_status *rx_stats)
947{
9ac58615 948 struct ath_softc *sc = hw->priv;
d435700f 949 struct ath_hw *ah = common->ah;
9fa23e17 950 int last_rssi;
d435700f 951
cf3af748
RM
952 if (!rx_stats->is_mybeacon ||
953 ((ah->opmode != NL80211_IFTYPE_STATION) &&
954 (ah->opmode != NL80211_IFTYPE_ADHOC)))
9fa23e17
FF
955 return;
956
9fa23e17 957 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
9ac58615 958 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
d435700f 959
9ac58615 960 last_rssi = sc->last_rssi;
d435700f
S
961 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
962 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
963 ATH_RSSI_EP_MULTIPLIER);
964 if (rx_stats->rs_rssi < 0)
965 rx_stats->rs_rssi = 0;
966
967 /* Update Beacon RSSI, this is used by ANI. */
9fa23e17 968 ah->stats.avgbrssi = rx_stats->rs_rssi;
d435700f
S
969}
970
971/*
972 * For Decrypt or Demic errors, we only mark packet status here and always push
973 * up the frame up to let mac80211 handle the actual error case, be it no
974 * decryption key or real decryption error. This let us keep statistics there.
975 */
976static int ath9k_rx_skb_preprocess(struct ath_common *common,
977 struct ieee80211_hw *hw,
9f167f64 978 struct ieee80211_hdr *hdr,
d435700f
S
979 struct ath_rx_status *rx_stats,
980 struct ieee80211_rx_status *rx_status,
981 bool *decrypt_error)
982{
f749b946
FF
983 struct ath_hw *ah = common->ah;
984
d435700f
S
985 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
986
987 /*
988 * everything but the rate is checked here, the rate check is done
989 * separately to avoid doing two lookups for a rate for each frame.
990 */
9f167f64 991 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
d435700f
S
992 return -EINVAL;
993
0d95521e
FF
994 /* Only use status info from the last fragment */
995 if (rx_stats->rs_more)
996 return 0;
997
9f167f64 998 ath9k_process_rssi(common, hw, hdr, rx_stats);
d435700f 999
9f167f64 1000 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
d435700f
S
1001 return -EINVAL;
1002
d435700f
S
1003 rx_status->band = hw->conf.channel->band;
1004 rx_status->freq = hw->conf.channel->center_freq;
f749b946 1005 rx_status->signal = ah->noise + rx_stats->rs_rssi;
d435700f 1006 rx_status->antenna = rx_stats->rs_antenna;
6ebacbb7 1007 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
d435700f
S
1008
1009 return 0;
1010}
1011
1012static void ath9k_rx_skb_postprocess(struct ath_common *common,
1013 struct sk_buff *skb,
1014 struct ath_rx_status *rx_stats,
1015 struct ieee80211_rx_status *rxs,
1016 bool decrypt_error)
1017{
1018 struct ath_hw *ah = common->ah;
1019 struct ieee80211_hdr *hdr;
1020 int hdrlen, padpos, padsize;
1021 u8 keyix;
1022 __le16 fc;
1023
1024 /* see if any padding is done by the hw and remove it */
1025 hdr = (struct ieee80211_hdr *) skb->data;
1026 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1027 fc = hdr->frame_control;
1028 padpos = ath9k_cmn_padpos(hdr->frame_control);
1029
1030 /* The MAC header is padded to have 32-bit boundary if the
1031 * packet payload is non-zero. The general calculation for
1032 * padsize would take into account odd header lengths:
1033 * padsize = (4 - padpos % 4) % 4; However, since only
1034 * even-length headers are used, padding can only be 0 or 2
1035 * bytes and we can optimize this a bit. In addition, we must
1036 * not try to remove padding from short control frames that do
1037 * not have payload. */
1038 padsize = padpos & 3;
1039 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1040 memmove(skb->data + padsize, skb->data, padpos);
1041 skb_pull(skb, padsize);
1042 }
1043
1044 keyix = rx_stats->rs_keyix;
1045
1046 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1047 ieee80211_has_protected(fc)) {
1048 rxs->flag |= RX_FLAG_DECRYPTED;
1049 } else if (ieee80211_has_protected(fc)
1050 && !decrypt_error && skb->len >= hdrlen + 4) {
1051 keyix = skb->data[hdrlen + 3] >> 6;
1052
1053 if (test_bit(keyix, common->keymap))
1054 rxs->flag |= RX_FLAG_DECRYPTED;
1055 }
1056 if (ah->sw_mgmt_crypto &&
1057 (rxs->flag & RX_FLAG_DECRYPTED) &&
1058 ieee80211_is_mgmt(fc))
1059 /* Use software decrypt for management frames. */
1060 rxs->flag &= ~RX_FLAG_DECRYPTED;
1061}
b5c80475 1062
102885a5
VT
1063static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1064 struct ath_hw_antcomb_conf ant_conf,
1065 int main_rssi_avg)
1066{
1067 antcomb->quick_scan_cnt = 0;
1068
1069 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1070 antcomb->rssi_lna2 = main_rssi_avg;
1071 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1072 antcomb->rssi_lna1 = main_rssi_avg;
1073
1074 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
223c5a87 1075 case 0x10: /* LNA2 A-B */
102885a5
VT
1076 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1077 antcomb->first_quick_scan_conf =
1078 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1079 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1080 break;
223c5a87 1081 case 0x20: /* LNA1 A-B */
102885a5
VT
1082 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1083 antcomb->first_quick_scan_conf =
1084 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1085 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1086 break;
223c5a87 1087 case 0x21: /* LNA1 LNA2 */
102885a5
VT
1088 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1089 antcomb->first_quick_scan_conf =
1090 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1091 antcomb->second_quick_scan_conf =
1092 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1093 break;
223c5a87 1094 case 0x12: /* LNA2 LNA1 */
102885a5
VT
1095 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1096 antcomb->first_quick_scan_conf =
1097 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1098 antcomb->second_quick_scan_conf =
1099 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1100 break;
223c5a87 1101 case 0x13: /* LNA2 A+B */
102885a5
VT
1102 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1103 antcomb->first_quick_scan_conf =
1104 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1105 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1106 break;
223c5a87 1107 case 0x23: /* LNA1 A+B */
102885a5
VT
1108 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1109 antcomb->first_quick_scan_conf =
1110 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1111 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1112 break;
1113 default:
1114 break;
1115 }
1116}
1117
1118static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1119 struct ath_hw_antcomb_conf *div_ant_conf,
1120 int main_rssi_avg, int alt_rssi_avg,
1121 int alt_ratio)
1122{
1123 /* alt_good */
1124 switch (antcomb->quick_scan_cnt) {
1125 case 0:
1126 /* set alt to main, and alt to first conf */
1127 div_ant_conf->main_lna_conf = antcomb->main_conf;
1128 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1129 break;
1130 case 1:
1131 /* set alt to main, and alt to first conf */
1132 div_ant_conf->main_lna_conf = antcomb->main_conf;
1133 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1134 antcomb->rssi_first = main_rssi_avg;
1135 antcomb->rssi_second = alt_rssi_avg;
1136
1137 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1138 /* main is LNA1 */
1139 if (ath_is_alt_ant_ratio_better(alt_ratio,
1140 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1141 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1142 main_rssi_avg, alt_rssi_avg,
1143 antcomb->total_pkt_count))
1144 antcomb->first_ratio = true;
1145 else
1146 antcomb->first_ratio = false;
1147 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1148 if (ath_is_alt_ant_ratio_better(alt_ratio,
1149 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1150 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1151 main_rssi_avg, alt_rssi_avg,
1152 antcomb->total_pkt_count))
1153 antcomb->first_ratio = true;
1154 else
1155 antcomb->first_ratio = false;
1156 } else {
1157 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1158 (alt_rssi_avg > main_rssi_avg +
1159 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1160 (alt_rssi_avg > main_rssi_avg)) &&
1161 (antcomb->total_pkt_count > 50))
1162 antcomb->first_ratio = true;
1163 else
1164 antcomb->first_ratio = false;
1165 }
1166 break;
1167 case 2:
1168 antcomb->alt_good = false;
1169 antcomb->scan_not_start = false;
1170 antcomb->scan = false;
1171 antcomb->rssi_first = main_rssi_avg;
1172 antcomb->rssi_third = alt_rssi_avg;
1173
1174 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1175 antcomb->rssi_lna1 = alt_rssi_avg;
1176 else if (antcomb->second_quick_scan_conf ==
1177 ATH_ANT_DIV_COMB_LNA2)
1178 antcomb->rssi_lna2 = alt_rssi_avg;
1179 else if (antcomb->second_quick_scan_conf ==
1180 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1181 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1182 antcomb->rssi_lna2 = main_rssi_avg;
1183 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1184 antcomb->rssi_lna1 = main_rssi_avg;
1185 }
1186
1187 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1188 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1189 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1190 else
1191 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1192
1193 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1194 if (ath_is_alt_ant_ratio_better(alt_ratio,
1195 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1196 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1197 main_rssi_avg, alt_rssi_avg,
1198 antcomb->total_pkt_count))
1199 antcomb->second_ratio = true;
1200 else
1201 antcomb->second_ratio = false;
1202 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1203 if (ath_is_alt_ant_ratio_better(alt_ratio,
1204 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1205 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1206 main_rssi_avg, alt_rssi_avg,
1207 antcomb->total_pkt_count))
1208 antcomb->second_ratio = true;
1209 else
1210 antcomb->second_ratio = false;
1211 } else {
1212 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1213 (alt_rssi_avg > main_rssi_avg +
1214 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1215 (alt_rssi_avg > main_rssi_avg)) &&
1216 (antcomb->total_pkt_count > 50))
1217 antcomb->second_ratio = true;
1218 else
1219 antcomb->second_ratio = false;
1220 }
1221
1222 /* set alt to the conf with maximun ratio */
1223 if (antcomb->first_ratio && antcomb->second_ratio) {
1224 if (antcomb->rssi_second > antcomb->rssi_third) {
1225 /* first alt*/
1226 if ((antcomb->first_quick_scan_conf ==
1227 ATH_ANT_DIV_COMB_LNA1) ||
1228 (antcomb->first_quick_scan_conf ==
1229 ATH_ANT_DIV_COMB_LNA2))
1230 /* Set alt LNA1 or LNA2*/
1231 if (div_ant_conf->main_lna_conf ==
1232 ATH_ANT_DIV_COMB_LNA2)
1233 div_ant_conf->alt_lna_conf =
1234 ATH_ANT_DIV_COMB_LNA1;
1235 else
1236 div_ant_conf->alt_lna_conf =
1237 ATH_ANT_DIV_COMB_LNA2;
1238 else
1239 /* Set alt to A+B or A-B */
1240 div_ant_conf->alt_lna_conf =
1241 antcomb->first_quick_scan_conf;
1242 } else if ((antcomb->second_quick_scan_conf ==
1243 ATH_ANT_DIV_COMB_LNA1) ||
1244 (antcomb->second_quick_scan_conf ==
1245 ATH_ANT_DIV_COMB_LNA2)) {
1246 /* Set alt LNA1 or LNA2 */
1247 if (div_ant_conf->main_lna_conf ==
1248 ATH_ANT_DIV_COMB_LNA2)
1249 div_ant_conf->alt_lna_conf =
1250 ATH_ANT_DIV_COMB_LNA1;
1251 else
1252 div_ant_conf->alt_lna_conf =
1253 ATH_ANT_DIV_COMB_LNA2;
1254 } else {
1255 /* Set alt to A+B or A-B */
1256 div_ant_conf->alt_lna_conf =
1257 antcomb->second_quick_scan_conf;
1258 }
1259 } else if (antcomb->first_ratio) {
1260 /* first alt */
1261 if ((antcomb->first_quick_scan_conf ==
1262 ATH_ANT_DIV_COMB_LNA1) ||
1263 (antcomb->first_quick_scan_conf ==
1264 ATH_ANT_DIV_COMB_LNA2))
1265 /* Set alt LNA1 or LNA2 */
1266 if (div_ant_conf->main_lna_conf ==
1267 ATH_ANT_DIV_COMB_LNA2)
1268 div_ant_conf->alt_lna_conf =
1269 ATH_ANT_DIV_COMB_LNA1;
1270 else
1271 div_ant_conf->alt_lna_conf =
1272 ATH_ANT_DIV_COMB_LNA2;
1273 else
1274 /* Set alt to A+B or A-B */
1275 div_ant_conf->alt_lna_conf =
1276 antcomb->first_quick_scan_conf;
1277 } else if (antcomb->second_ratio) {
1278 /* second alt */
1279 if ((antcomb->second_quick_scan_conf ==
1280 ATH_ANT_DIV_COMB_LNA1) ||
1281 (antcomb->second_quick_scan_conf ==
1282 ATH_ANT_DIV_COMB_LNA2))
1283 /* Set alt LNA1 or LNA2 */
1284 if (div_ant_conf->main_lna_conf ==
1285 ATH_ANT_DIV_COMB_LNA2)
1286 div_ant_conf->alt_lna_conf =
1287 ATH_ANT_DIV_COMB_LNA1;
1288 else
1289 div_ant_conf->alt_lna_conf =
1290 ATH_ANT_DIV_COMB_LNA2;
1291 else
1292 /* Set alt to A+B or A-B */
1293 div_ant_conf->alt_lna_conf =
1294 antcomb->second_quick_scan_conf;
1295 } else {
1296 /* main is largest */
1297 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1298 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1299 /* Set alt LNA1 or LNA2 */
1300 if (div_ant_conf->main_lna_conf ==
1301 ATH_ANT_DIV_COMB_LNA2)
1302 div_ant_conf->alt_lna_conf =
1303 ATH_ANT_DIV_COMB_LNA1;
1304 else
1305 div_ant_conf->alt_lna_conf =
1306 ATH_ANT_DIV_COMB_LNA2;
1307 else
1308 /* Set alt to A+B or A-B */
1309 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1310 }
1311 break;
1312 default:
1313 break;
1314 }
1315}
1316
3e9a212a
MSS
1317static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1318 struct ath_ant_comb *antcomb, int alt_ratio)
102885a5 1319{
3e9a212a
MSS
1320 if (ant_conf->div_group == 0) {
1321 /* Adjust the fast_div_bias based on main and alt lna conf */
1322 switch ((ant_conf->main_lna_conf << 4) |
1323 ant_conf->alt_lna_conf) {
223c5a87 1324 case 0x01: /* A-B LNA2 */
3e9a212a
MSS
1325 ant_conf->fast_div_bias = 0x3b;
1326 break;
223c5a87 1327 case 0x02: /* A-B LNA1 */
3e9a212a
MSS
1328 ant_conf->fast_div_bias = 0x3d;
1329 break;
223c5a87 1330 case 0x03: /* A-B A+B */
3e9a212a
MSS
1331 ant_conf->fast_div_bias = 0x1;
1332 break;
223c5a87 1333 case 0x10: /* LNA2 A-B */
3e9a212a
MSS
1334 ant_conf->fast_div_bias = 0x7;
1335 break;
223c5a87 1336 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS
1337 ant_conf->fast_div_bias = 0x2;
1338 break;
223c5a87 1339 case 0x13: /* LNA2 A+B */
3e9a212a
MSS
1340 ant_conf->fast_div_bias = 0x7;
1341 break;
223c5a87 1342 case 0x20: /* LNA1 A-B */
3e9a212a
MSS
1343 ant_conf->fast_div_bias = 0x6;
1344 break;
223c5a87 1345 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS
1346 ant_conf->fast_div_bias = 0x0;
1347 break;
223c5a87 1348 case 0x23: /* LNA1 A+B */
3e9a212a
MSS
1349 ant_conf->fast_div_bias = 0x6;
1350 break;
223c5a87 1351 case 0x30: /* A+B A-B */
3e9a212a
MSS
1352 ant_conf->fast_div_bias = 0x1;
1353 break;
223c5a87 1354 case 0x31: /* A+B LNA2 */
3e9a212a
MSS
1355 ant_conf->fast_div_bias = 0x3b;
1356 break;
223c5a87 1357 case 0x32: /* A+B LNA1 */
3e9a212a
MSS
1358 ant_conf->fast_div_bias = 0x3d;
1359 break;
1360 default:
1361 break;
1362 }
e7ef5bc0
GJ
1363 } else if (ant_conf->div_group == 1) {
1364 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1365 switch ((ant_conf->main_lna_conf << 4) |
1366 ant_conf->alt_lna_conf) {
1367 case 0x01: /* A-B LNA2 */
1368 ant_conf->fast_div_bias = 0x1;
1369 ant_conf->main_gaintb = 0;
1370 ant_conf->alt_gaintb = 0;
1371 break;
1372 case 0x02: /* A-B LNA1 */
1373 ant_conf->fast_div_bias = 0x1;
1374 ant_conf->main_gaintb = 0;
1375 ant_conf->alt_gaintb = 0;
1376 break;
1377 case 0x03: /* A-B A+B */
1378 ant_conf->fast_div_bias = 0x1;
1379 ant_conf->main_gaintb = 0;
1380 ant_conf->alt_gaintb = 0;
1381 break;
1382 case 0x10: /* LNA2 A-B */
1383 if (!(antcomb->scan) &&
1384 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1385 ant_conf->fast_div_bias = 0x3f;
1386 else
1387 ant_conf->fast_div_bias = 0x1;
1388 ant_conf->main_gaintb = 0;
1389 ant_conf->alt_gaintb = 0;
1390 break;
1391 case 0x12: /* LNA2 LNA1 */
1392 ant_conf->fast_div_bias = 0x1;
1393 ant_conf->main_gaintb = 0;
1394 ant_conf->alt_gaintb = 0;
1395 break;
1396 case 0x13: /* LNA2 A+B */
1397 if (!(antcomb->scan) &&
1398 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1399 ant_conf->fast_div_bias = 0x3f;
1400 else
1401 ant_conf->fast_div_bias = 0x1;
1402 ant_conf->main_gaintb = 0;
1403 ant_conf->alt_gaintb = 0;
1404 break;
1405 case 0x20: /* LNA1 A-B */
1406 if (!(antcomb->scan) &&
1407 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1408 ant_conf->fast_div_bias = 0x3f;
1409 else
1410 ant_conf->fast_div_bias = 0x1;
1411 ant_conf->main_gaintb = 0;
1412 ant_conf->alt_gaintb = 0;
1413 break;
1414 case 0x21: /* LNA1 LNA2 */
1415 ant_conf->fast_div_bias = 0x1;
1416 ant_conf->main_gaintb = 0;
1417 ant_conf->alt_gaintb = 0;
1418 break;
1419 case 0x23: /* LNA1 A+B */
1420 if (!(antcomb->scan) &&
1421 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1422 ant_conf->fast_div_bias = 0x3f;
1423 else
1424 ant_conf->fast_div_bias = 0x1;
1425 ant_conf->main_gaintb = 0;
1426 ant_conf->alt_gaintb = 0;
1427 break;
1428 case 0x30: /* A+B A-B */
1429 ant_conf->fast_div_bias = 0x1;
1430 ant_conf->main_gaintb = 0;
1431 ant_conf->alt_gaintb = 0;
1432 break;
1433 case 0x31: /* A+B LNA2 */
1434 ant_conf->fast_div_bias = 0x1;
1435 ant_conf->main_gaintb = 0;
1436 ant_conf->alt_gaintb = 0;
1437 break;
1438 case 0x32: /* A+B LNA1 */
1439 ant_conf->fast_div_bias = 0x1;
1440 ant_conf->main_gaintb = 0;
1441 ant_conf->alt_gaintb = 0;
1442 break;
1443 default:
1444 break;
1445 }
3e9a212a
MSS
1446 } else if (ant_conf->div_group == 2) {
1447 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1448 switch ((ant_conf->main_lna_conf << 4) |
1449 ant_conf->alt_lna_conf) {
223c5a87 1450 case 0x01: /* A-B LNA2 */
3e9a212a
MSS
1451 ant_conf->fast_div_bias = 0x1;
1452 ant_conf->main_gaintb = 0;
1453 ant_conf->alt_gaintb = 0;
1454 break;
223c5a87 1455 case 0x02: /* A-B LNA1 */
3e9a212a
MSS
1456 ant_conf->fast_div_bias = 0x1;
1457 ant_conf->main_gaintb = 0;
1458 ant_conf->alt_gaintb = 0;
1459 break;
223c5a87 1460 case 0x03: /* A-B A+B */
3e9a212a
MSS
1461 ant_conf->fast_div_bias = 0x1;
1462 ant_conf->main_gaintb = 0;
1463 ant_conf->alt_gaintb = 0;
1464 break;
223c5a87 1465 case 0x10: /* LNA2 A-B */
3e9a212a
MSS
1466 if (!(antcomb->scan) &&
1467 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1468 ant_conf->fast_div_bias = 0x1;
1469 else
1470 ant_conf->fast_div_bias = 0x2;
1471 ant_conf->main_gaintb = 0;
1472 ant_conf->alt_gaintb = 0;
1473 break;
223c5a87 1474 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS
1475 ant_conf->fast_div_bias = 0x1;
1476 ant_conf->main_gaintb = 0;
1477 ant_conf->alt_gaintb = 0;
1478 break;
223c5a87 1479 case 0x13: /* LNA2 A+B */
3e9a212a
MSS
1480 if (!(antcomb->scan) &&
1481 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1482 ant_conf->fast_div_bias = 0x1;
1483 else
1484 ant_conf->fast_div_bias = 0x2;
1485 ant_conf->main_gaintb = 0;
1486 ant_conf->alt_gaintb = 0;
1487 break;
223c5a87 1488 case 0x20: /* LNA1 A-B */
3e9a212a
MSS
1489 if (!(antcomb->scan) &&
1490 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1491 ant_conf->fast_div_bias = 0x1;
1492 else
1493 ant_conf->fast_div_bias = 0x2;
1494 ant_conf->main_gaintb = 0;
1495 ant_conf->alt_gaintb = 0;
1496 break;
223c5a87 1497 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS
1498 ant_conf->fast_div_bias = 0x1;
1499 ant_conf->main_gaintb = 0;
1500 ant_conf->alt_gaintb = 0;
1501 break;
223c5a87 1502 case 0x23: /* LNA1 A+B */
3e9a212a
MSS
1503 if (!(antcomb->scan) &&
1504 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1505 ant_conf->fast_div_bias = 0x1;
1506 else
1507 ant_conf->fast_div_bias = 0x2;
1508 ant_conf->main_gaintb = 0;
1509 ant_conf->alt_gaintb = 0;
1510 break;
223c5a87 1511 case 0x30: /* A+B A-B */
3e9a212a
MSS
1512 ant_conf->fast_div_bias = 0x1;
1513 ant_conf->main_gaintb = 0;
1514 ant_conf->alt_gaintb = 0;
1515 break;
223c5a87 1516 case 0x31: /* A+B LNA2 */
3e9a212a
MSS
1517 ant_conf->fast_div_bias = 0x1;
1518 ant_conf->main_gaintb = 0;
1519 ant_conf->alt_gaintb = 0;
1520 break;
223c5a87 1521 case 0x32: /* A+B LNA1 */
3e9a212a
MSS
1522 ant_conf->fast_div_bias = 0x1;
1523 ant_conf->main_gaintb = 0;
1524 ant_conf->alt_gaintb = 0;
1525 break;
1526 default:
1527 break;
1528 }
102885a5
VT
1529 }
1530}
1531
1532/* Antenna diversity and combining */
1533static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1534{
1535 struct ath_hw_antcomb_conf div_ant_conf;
1536 struct ath_ant_comb *antcomb = &sc->ant_comb;
1537 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
0ff2b5c0 1538 int curr_main_set;
102885a5
VT
1539 int main_rssi = rs->rs_rssi_ctl0;
1540 int alt_rssi = rs->rs_rssi_ctl1;
1541 int rx_ant_conf, main_ant_conf;
1542 bool short_scan = false;
1543
1544 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1545 ATH_ANT_RX_MASK;
1546 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1547 ATH_ANT_RX_MASK;
1548
21e8ee6d
MSS
1549 /* Record packet only when both main_rssi and alt_rssi is positive */
1550 if (main_rssi > 0 && alt_rssi > 0) {
102885a5
VT
1551 antcomb->total_pkt_count++;
1552 antcomb->main_total_rssi += main_rssi;
1553 antcomb->alt_total_rssi += alt_rssi;
1554 if (main_ant_conf == rx_ant_conf)
1555 antcomb->main_recv_cnt++;
1556 else
1557 antcomb->alt_recv_cnt++;
1558 }
1559
1560 /* Short scan check */
1561 if (antcomb->scan && antcomb->alt_good) {
1562 if (time_after(jiffies, antcomb->scan_start_time +
1563 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1564 short_scan = true;
1565 else
1566 if (antcomb->total_pkt_count ==
1567 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1568 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1569 antcomb->total_pkt_count);
1570 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1571 short_scan = true;
1572 }
1573 }
1574
1575 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1576 rs->rs_moreaggr) && !short_scan)
1577 return;
1578
1579 if (antcomb->total_pkt_count) {
1580 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1581 antcomb->total_pkt_count);
1582 main_rssi_avg = (antcomb->main_total_rssi /
1583 antcomb->total_pkt_count);
1584 alt_rssi_avg = (antcomb->alt_total_rssi /
1585 antcomb->total_pkt_count);
1586 }
1587
1588
1589 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1590 curr_alt_set = div_ant_conf.alt_lna_conf;
1591 curr_main_set = div_ant_conf.main_lna_conf;
102885a5
VT
1592
1593 antcomb->count++;
1594
1595 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1596 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1597 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1598 main_rssi_avg);
1599 antcomb->alt_good = true;
1600 } else {
1601 antcomb->alt_good = false;
1602 }
1603
1604 antcomb->count = 0;
1605 antcomb->scan = true;
1606 antcomb->scan_not_start = true;
1607 }
1608
1609 if (!antcomb->scan) {
b85c5734
MSS
1610 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1611 alt_ratio, curr_main_set, curr_alt_set,
1612 alt_rssi_avg, main_rssi_avg)) {
102885a5
VT
1613 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1614 /* Switch main and alt LNA */
1615 div_ant_conf.main_lna_conf =
1616 ATH_ANT_DIV_COMB_LNA2;
1617 div_ant_conf.alt_lna_conf =
1618 ATH_ANT_DIV_COMB_LNA1;
1619 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1620 div_ant_conf.main_lna_conf =
1621 ATH_ANT_DIV_COMB_LNA1;
1622 div_ant_conf.alt_lna_conf =
1623 ATH_ANT_DIV_COMB_LNA2;
1624 }
1625
1626 goto div_comb_done;
1627 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1628 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1629 /* Set alt to another LNA */
1630 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1631 div_ant_conf.alt_lna_conf =
1632 ATH_ANT_DIV_COMB_LNA1;
1633 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1634 div_ant_conf.alt_lna_conf =
1635 ATH_ANT_DIV_COMB_LNA2;
1636
1637 goto div_comb_done;
1638 }
1639
1640 if ((alt_rssi_avg < (main_rssi_avg +
8afbcc8b 1641 div_ant_conf.lna1_lna2_delta)))
102885a5
VT
1642 goto div_comb_done;
1643 }
1644
1645 if (!antcomb->scan_not_start) {
1646 switch (curr_alt_set) {
1647 case ATH_ANT_DIV_COMB_LNA2:
1648 antcomb->rssi_lna2 = alt_rssi_avg;
1649 antcomb->rssi_lna1 = main_rssi_avg;
1650 antcomb->scan = true;
1651 /* set to A+B */
1652 div_ant_conf.main_lna_conf =
1653 ATH_ANT_DIV_COMB_LNA1;
1654 div_ant_conf.alt_lna_conf =
1655 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1656 break;
1657 case ATH_ANT_DIV_COMB_LNA1:
1658 antcomb->rssi_lna1 = alt_rssi_avg;
1659 antcomb->rssi_lna2 = main_rssi_avg;
1660 antcomb->scan = true;
1661 /* set to A+B */
1662 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1663 div_ant_conf.alt_lna_conf =
1664 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1665 break;
1666 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1667 antcomb->rssi_add = alt_rssi_avg;
1668 antcomb->scan = true;
1669 /* set to A-B */
1670 div_ant_conf.alt_lna_conf =
1671 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1672 break;
1673 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1674 antcomb->rssi_sub = alt_rssi_avg;
1675 antcomb->scan = false;
1676 if (antcomb->rssi_lna2 >
1677 (antcomb->rssi_lna1 +
1678 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1679 /* use LNA2 as main LNA */
1680 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1681 (antcomb->rssi_add > antcomb->rssi_sub)) {
1682 /* set to A+B */
1683 div_ant_conf.main_lna_conf =
1684 ATH_ANT_DIV_COMB_LNA2;
1685 div_ant_conf.alt_lna_conf =
1686 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1687 } else if (antcomb->rssi_sub >
1688 antcomb->rssi_lna1) {
1689 /* set to A-B */
1690 div_ant_conf.main_lna_conf =
1691 ATH_ANT_DIV_COMB_LNA2;
1692 div_ant_conf.alt_lna_conf =
1693 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1694 } else {
1695 /* set to LNA1 */
1696 div_ant_conf.main_lna_conf =
1697 ATH_ANT_DIV_COMB_LNA2;
1698 div_ant_conf.alt_lna_conf =
1699 ATH_ANT_DIV_COMB_LNA1;
1700 }
1701 } else {
1702 /* use LNA1 as main LNA */
1703 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1704 (antcomb->rssi_add > antcomb->rssi_sub)) {
1705 /* set to A+B */
1706 div_ant_conf.main_lna_conf =
1707 ATH_ANT_DIV_COMB_LNA1;
1708 div_ant_conf.alt_lna_conf =
1709 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1710 } else if (antcomb->rssi_sub >
1711 antcomb->rssi_lna1) {
1712 /* set to A-B */
1713 div_ant_conf.main_lna_conf =
1714 ATH_ANT_DIV_COMB_LNA1;
1715 div_ant_conf.alt_lna_conf =
1716 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1717 } else {
1718 /* set to LNA2 */
1719 div_ant_conf.main_lna_conf =
1720 ATH_ANT_DIV_COMB_LNA1;
1721 div_ant_conf.alt_lna_conf =
1722 ATH_ANT_DIV_COMB_LNA2;
1723 }
1724 }
1725 break;
1726 default:
1727 break;
1728 }
1729 } else {
1730 if (!antcomb->alt_good) {
1731 antcomb->scan_not_start = false;
1732 /* Set alt to another LNA */
1733 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1734 div_ant_conf.main_lna_conf =
1735 ATH_ANT_DIV_COMB_LNA2;
1736 div_ant_conf.alt_lna_conf =
1737 ATH_ANT_DIV_COMB_LNA1;
1738 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1739 div_ant_conf.main_lna_conf =
1740 ATH_ANT_DIV_COMB_LNA1;
1741 div_ant_conf.alt_lna_conf =
1742 ATH_ANT_DIV_COMB_LNA2;
1743 }
1744 goto div_comb_done;
1745 }
1746 }
1747
1748 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1749 main_rssi_avg, alt_rssi_avg,
1750 alt_ratio);
1751
1752 antcomb->quick_scan_cnt++;
1753
1754div_comb_done:
3e9a212a 1755 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
102885a5
VT
1756 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1757
1758 antcomb->scan_start_time = jiffies;
1759 antcomb->total_pkt_count = 0;
1760 antcomb->main_total_rssi = 0;
1761 antcomb->alt_total_rssi = 0;
1762 antcomb->main_recv_cnt = 0;
1763 antcomb->alt_recv_cnt = 0;
1764}
1765
b5c80475
FF
1766int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1767{
1768 struct ath_buf *bf;
0d95521e 1769 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
5ca42627 1770 struct ieee80211_rx_status *rxs;
cbe61d8a 1771 struct ath_hw *ah = sc->sc_ah;
27c51f1a 1772 struct ath_common *common = ath9k_hw_common(ah);
7545daf4 1773 struct ieee80211_hw *hw = sc->hw;
be0418ad 1774 struct ieee80211_hdr *hdr;
c9b14170 1775 int retval;
be0418ad 1776 bool decrypt_error = false;
29bffa96 1777 struct ath_rx_status rs;
b5c80475
FF
1778 enum ath9k_rx_qtype qtype;
1779 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1780 int dma_type;
5c6dd921 1781 u8 rx_status_len = ah->caps.rx_status_len;
a6d2055b
FF
1782 u64 tsf = 0;
1783 u32 tsf_lower = 0;
8ab2cd09 1784 unsigned long flags;
be0418ad 1785
b5c80475 1786 if (edma)
b5c80475 1787 dma_type = DMA_BIDIRECTIONAL;
56824223
ML
1788 else
1789 dma_type = DMA_FROM_DEVICE;
b5c80475
FF
1790
1791 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
b77f483f 1792 spin_lock_bh(&sc->rx.rxbuflock);
f078f209 1793
a6d2055b
FF
1794 tsf = ath9k_hw_gettsf64(ah);
1795 tsf_lower = tsf & 0xffffffff;
1796
f078f209
LR
1797 do {
1798 /* If handling rx interrupt and flush is in progress => exit */
98deeea0 1799 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
f078f209
LR
1800 break;
1801
29bffa96 1802 memset(&rs, 0, sizeof(rs));
b5c80475
FF
1803 if (edma)
1804 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1805 else
1806 bf = ath_get_next_rx_buf(sc, &rs);
f078f209 1807
b5c80475
FF
1808 if (!bf)
1809 break;
f078f209 1810
f078f209 1811 skb = bf->bf_mpdu;
be0418ad 1812 if (!skb)
f078f209 1813 continue;
f078f209 1814
0d95521e
FF
1815 /*
1816 * Take frame header from the first fragment and RX status from
1817 * the last one.
1818 */
1819 if (sc->rx.frag)
1820 hdr_skb = sc->rx.frag;
1821 else
1822 hdr_skb = skb;
1823
1824 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1825 rxs = IEEE80211_SKB_RXCB(hdr_skb);
cf3af748
RM
1826 if (ieee80211_is_beacon(hdr->frame_control) &&
1827 !compare_ether_addr(hdr->addr3, common->curbssid))
1828 rs.is_mybeacon = true;
1829 else
1830 rs.is_mybeacon = false;
5ca42627 1831
29bffa96 1832 ath_debug_stat_rx(sc, &rs);
1395d3f0 1833
f078f209 1834 /*
be0418ad
S
1835 * If we're asked to flush receive queue, directly
1836 * chain it back at the queue without processing it.
f078f209 1837 */
3483288c 1838 if (sc->sc_flags & SC_OP_RXFLUSH)
0d95521e 1839 goto requeue_drop_frag;
f078f209 1840
c8f3b721
JF
1841 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1842 rxs, &decrypt_error);
1843 if (retval)
0d95521e 1844 goto requeue_drop_frag;
c8f3b721 1845
a6d2055b
FF
1846 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1847 if (rs.rs_tstamp > tsf_lower &&
1848 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1849 rxs->mactime -= 0x100000000ULL;
1850
1851 if (rs.rs_tstamp < tsf_lower &&
1852 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1853 rxs->mactime += 0x100000000ULL;
1854
cb71d9ba
LR
1855 /* Ensure we always have an skb to requeue once we are done
1856 * processing the current buffer's skb */
cc861f74 1857 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
cb71d9ba
LR
1858
1859 /* If there is no memory we ignore the current RX'd frame,
1860 * tell hardware it can give us a new frame using the old
b77f483f 1861 * skb and put it at the tail of the sc->rx.rxbuf list for
cb71d9ba
LR
1862 * processing. */
1863 if (!requeue_skb)
0d95521e 1864 goto requeue_drop_frag;
f078f209 1865
9bf9fca8 1866 /* Unmap the frame */
7da3c55c 1867 dma_unmap_single(sc->dev, bf->bf_buf_addr,
cc861f74 1868 common->rx_bufsize,
b5c80475 1869 dma_type);
f078f209 1870
b5c80475
FF
1871 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1872 if (ah->caps.rx_status_len)
1873 skb_pull(skb, ah->caps.rx_status_len);
be0418ad 1874
0d95521e
FF
1875 if (!rs.rs_more)
1876 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1877 rxs, decrypt_error);
be0418ad 1878
cb71d9ba
LR
1879 /* We will now give hardware our shiny new allocated skb */
1880 bf->bf_mpdu = requeue_skb;
7da3c55c 1881 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
cc861f74 1882 common->rx_bufsize,
b5c80475 1883 dma_type);
7da3c55c 1884 if (unlikely(dma_mapping_error(sc->dev,
f8316df1
LR
1885 bf->bf_buf_addr))) {
1886 dev_kfree_skb_any(requeue_skb);
1887 bf->bf_mpdu = NULL;
6cf9e995 1888 bf->bf_buf_addr = 0;
3800276a 1889 ath_err(common, "dma_mapping_error() on RX\n");
7545daf4 1890 ieee80211_rx(hw, skb);
f8316df1
LR
1891 break;
1892 }
f078f209 1893
0d95521e
FF
1894 if (rs.rs_more) {
1895 /*
1896 * rs_more indicates chained descriptors which can be
1897 * used to link buffers together for a sort of
1898 * scatter-gather operation.
1899 */
1900 if (sc->rx.frag) {
1901 /* too many fragments - cannot handle frame */
1902 dev_kfree_skb_any(sc->rx.frag);
1903 dev_kfree_skb_any(skb);
1904 skb = NULL;
1905 }
1906 sc->rx.frag = skb;
1907 goto requeue;
1908 }
1909
1910 if (sc->rx.frag) {
1911 int space = skb->len - skb_tailroom(hdr_skb);
1912
1913 sc->rx.frag = NULL;
1914
1915 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1916 dev_kfree_skb(skb);
1917 goto requeue_drop_frag;
1918 }
1919
1920 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1921 skb->len);
1922 dev_kfree_skb_any(skb);
1923 skb = hdr_skb;
1924 }
1925
f078f209
LR
1926 /*
1927 * change the default rx antenna if rx diversity chooses the
1928 * other antenna 3 times in a row.
1929 */
29bffa96 1930 if (sc->rx.defant != rs.rs_antenna) {
b77f483f 1931 if (++sc->rx.rxotherant >= 3)
29bffa96 1932 ath_setdefantenna(sc, rs.rs_antenna);
f078f209 1933 } else {
b77f483f 1934 sc->rx.rxotherant = 0;
f078f209 1935 }
3cbb5dd7 1936
66760eac
FF
1937 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1938 skb_trim(skb, skb->len - 8);
1939
8ab2cd09 1940 spin_lock_irqsave(&sc->sc_pm_lock, flags);
aaef24b4
MSS
1941
1942 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
f73c604c
RM
1943 PS_WAIT_FOR_CAB |
1944 PS_WAIT_FOR_PSPOLL_DATA)) ||
1945 ath9k_check_auto_sleep(sc))
1946 ath_rx_ps(sc, skb, rs.is_mybeacon);
8ab2cd09 1947 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
cc65965c 1948
43c35284 1949 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
102885a5
VT
1950 ath_ant_comb_scan(sc, &rs);
1951
7545daf4 1952 ieee80211_rx(hw, skb);
cc65965c 1953
0d95521e
FF
1954requeue_drop_frag:
1955 if (sc->rx.frag) {
1956 dev_kfree_skb_any(sc->rx.frag);
1957 sc->rx.frag = NULL;
1958 }
cb71d9ba 1959requeue:
b5c80475
FF
1960 if (edma) {
1961 list_add_tail(&bf->list, &sc->rx.rxbuf);
1962 ath_rx_edma_buf_link(sc, qtype);
1963 } else {
1964 list_move_tail(&bf->list, &sc->rx.rxbuf);
1965 ath_rx_buf_link(sc, bf);
3483288c
FF
1966 if (!flush)
1967 ath9k_hw_rxena(ah);
b5c80475 1968 }
be0418ad
S
1969 } while (1);
1970
b77f483f 1971 spin_unlock_bh(&sc->rx.rxbuflock);
f078f209 1972
29ab0b36
RM
1973 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1974 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 1975 ath9k_hw_set_interrupts(ah);
29ab0b36
RM
1976 }
1977
f078f209 1978 return 0;
f078f209 1979}