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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 | 19 | |
b5c80475 FF |
20 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
21 | ||
102885a5 VT |
22 | static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta, |
23 | int mindelta, int main_rssi_avg, | |
24 | int alt_rssi_avg, int pkt_count) | |
25 | { | |
26 | return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
27 | (alt_rssi_avg > main_rssi_avg + maxdelta)) || | |
28 | (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50); | |
29 | } | |
30 | ||
b85c5734 MSS |
31 | static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio, |
32 | int curr_main_set, int curr_alt_set, | |
33 | int alt_rssi_avg, int main_rssi_avg) | |
34 | { | |
35 | bool result = false; | |
36 | switch (div_group) { | |
37 | case 0: | |
38 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) | |
39 | result = true; | |
40 | break; | |
41 | case 1: | |
42 | if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) && | |
43 | (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) && | |
44 | (alt_rssi_avg >= (main_rssi_avg - 5))) || | |
45 | ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) && | |
46 | (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) && | |
47 | (alt_rssi_avg >= (main_rssi_avg - 2)))) && | |
48 | (alt_rssi_avg >= 4)) | |
49 | result = true; | |
50 | else | |
51 | result = false; | |
52 | break; | |
53 | } | |
54 | ||
55 | return result; | |
56 | } | |
57 | ||
ededf1f8 VT |
58 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
59 | { | |
60 | return sc->ps_enabled && | |
61 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
62 | } | |
63 | ||
f078f209 LR |
64 | /* |
65 | * Setup and link descriptors. | |
66 | * | |
67 | * 11N: we can no longer afford to self link the last descriptor. | |
68 | * MAC acknowledges BA status as long as it copies frames to host | |
69 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
70 | * to a sender if last desc is self-linked. | |
f078f209 | 71 | */ |
f078f209 LR |
72 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
73 | { | |
cbe61d8a | 74 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 75 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
76 | struct ath_desc *ds; |
77 | struct sk_buff *skb; | |
78 | ||
79 | ATH_RXBUF_RESET(bf); | |
80 | ||
81 | ds = bf->bf_desc; | |
be0418ad | 82 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
83 | ds->ds_data = bf->bf_buf_addr; |
84 | ||
be0418ad | 85 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 86 | skb = bf->bf_mpdu; |
9680e8a3 | 87 | BUG_ON(skb == NULL); |
f078f209 LR |
88 | ds->ds_vdata = skb->data; |
89 | ||
cc861f74 LR |
90 | /* |
91 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 92 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
93 | * to process |
94 | */ | |
b77f483f | 95 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 96 | common->rx_bufsize, |
f078f209 LR |
97 | 0); |
98 | ||
b77f483f | 99 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
100 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
101 | else | |
b77f483f | 102 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 103 | |
b77f483f | 104 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
105 | } |
106 | ||
ff37e337 S |
107 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
108 | { | |
109 | /* XXX block beacon interrupts */ | |
110 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
111 | sc->rx.defant = antenna; |
112 | sc->rx.rxotherant = 0; | |
ff37e337 S |
113 | } |
114 | ||
f078f209 LR |
115 | static void ath_opmode_init(struct ath_softc *sc) |
116 | { | |
cbe61d8a | 117 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
118 | struct ath_common *common = ath9k_hw_common(ah); |
119 | ||
f078f209 LR |
120 | u32 rfilt, mfilt[2]; |
121 | ||
122 | /* configure rx filter */ | |
123 | rfilt = ath_calcrxfilter(sc); | |
124 | ath9k_hw_setrxfilter(ah, rfilt); | |
125 | ||
126 | /* configure bssid mask */ | |
364734fa | 127 | ath_hw_setbssidmask(common); |
f078f209 LR |
128 | |
129 | /* configure operational mode */ | |
130 | ath9k_hw_setopmode(ah); | |
131 | ||
f078f209 LR |
132 | /* calculate and install multicast filter */ |
133 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 134 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
135 | } |
136 | ||
b5c80475 FF |
137 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
138 | enum ath9k_rx_qtype qtype) | |
f078f209 | 139 | { |
b5c80475 FF |
140 | struct ath_hw *ah = sc->sc_ah; |
141 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
142 | struct sk_buff *skb; |
143 | struct ath_buf *bf; | |
f078f209 | 144 | |
b5c80475 FF |
145 | rx_edma = &sc->rx.rx_edma[qtype]; |
146 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
147 | return false; | |
f078f209 | 148 | |
b5c80475 FF |
149 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
150 | list_del_init(&bf->list); | |
f078f209 | 151 | |
b5c80475 FF |
152 | skb = bf->bf_mpdu; |
153 | ||
154 | ATH_RXBUF_RESET(bf); | |
155 | memset(skb->data, 0, ah->caps.rx_status_len); | |
156 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
157 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 158 | |
b5c80475 FF |
159 | SKB_CB_ATHBUF(skb) = bf; |
160 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
161 | skb_queue_tail(&rx_edma->rx_fifo, skb); | |
f078f209 | 162 | |
b5c80475 FF |
163 | return true; |
164 | } | |
165 | ||
166 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
167 | enum ath9k_rx_qtype qtype, int size) | |
168 | { | |
b5c80475 FF |
169 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
170 | u32 nbuf = 0; | |
171 | ||
b5c80475 | 172 | if (list_empty(&sc->rx.rxbuf)) { |
226afe68 | 173 | ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); |
b5c80475 | 174 | return; |
797fe5cb | 175 | } |
f078f209 | 176 | |
b5c80475 FF |
177 | while (!list_empty(&sc->rx.rxbuf)) { |
178 | nbuf++; | |
179 | ||
180 | if (!ath_rx_edma_buf_link(sc, qtype)) | |
181 | break; | |
182 | ||
183 | if (nbuf >= size) | |
184 | break; | |
185 | } | |
186 | } | |
187 | ||
188 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
189 | enum ath9k_rx_qtype qtype) | |
190 | { | |
191 | struct ath_buf *bf; | |
192 | struct ath_rx_edma *rx_edma; | |
193 | struct sk_buff *skb; | |
194 | ||
195 | rx_edma = &sc->rx.rx_edma[qtype]; | |
196 | ||
197 | while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { | |
198 | bf = SKB_CB_ATHBUF(skb); | |
199 | BUG_ON(!bf); | |
200 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
201 | } | |
202 | } | |
203 | ||
204 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
205 | { | |
206 | struct ath_buf *bf; | |
207 | ||
208 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
209 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
210 | ||
797fe5cb | 211 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
b5c80475 FF |
212 | if (bf->bf_mpdu) |
213 | dev_kfree_skb_any(bf->bf_mpdu); | |
214 | } | |
215 | ||
216 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
217 | ||
218 | kfree(sc->rx.rx_bufptr); | |
219 | sc->rx.rx_bufptr = NULL; | |
220 | } | |
221 | ||
222 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
223 | { | |
224 | skb_queue_head_init(&rx_edma->rx_fifo); | |
225 | skb_queue_head_init(&rx_edma->rx_buffers); | |
226 | rx_edma->rx_fifo_hwsize = size; | |
227 | } | |
228 | ||
229 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
230 | { | |
231 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
232 | struct ath_hw *ah = sc->sc_ah; | |
233 | struct sk_buff *skb; | |
234 | struct ath_buf *bf; | |
235 | int error = 0, i; | |
236 | u32 size; | |
237 | ||
b5c80475 FF |
238 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
239 | ah->caps.rx_status_len); | |
240 | ||
241 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
242 | ah->caps.rx_lp_qdepth); | |
243 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
244 | ah->caps.rx_hp_qdepth); | |
245 | ||
246 | size = sizeof(struct ath_buf) * nbufs; | |
247 | bf = kzalloc(size, GFP_KERNEL); | |
248 | if (!bf) | |
249 | return -ENOMEM; | |
250 | ||
251 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
252 | sc->rx.rx_bufptr = bf; | |
253 | ||
254 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 255 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 256 | if (!skb) { |
797fe5cb | 257 | error = -ENOMEM; |
b5c80475 | 258 | goto rx_init_fail; |
f078f209 | 259 | } |
f078f209 | 260 | |
b5c80475 | 261 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 262 | bf->bf_mpdu = skb; |
b5c80475 | 263 | |
797fe5cb | 264 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 265 | common->rx_bufsize, |
b5c80475 | 266 | DMA_BIDIRECTIONAL); |
797fe5cb | 267 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
268 | bf->bf_buf_addr))) { |
269 | dev_kfree_skb_any(skb); | |
270 | bf->bf_mpdu = NULL; | |
6cf9e995 | 271 | bf->bf_buf_addr = 0; |
3800276a | 272 | ath_err(common, |
b5c80475 FF |
273 | "dma_mapping_error() on RX init\n"); |
274 | error = -ENOMEM; | |
275 | goto rx_init_fail; | |
276 | } | |
277 | ||
278 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
279 | } | |
280 | ||
281 | return 0; | |
282 | ||
283 | rx_init_fail: | |
284 | ath_rx_edma_cleanup(sc); | |
285 | return error; | |
286 | } | |
287 | ||
288 | static void ath_edma_start_recv(struct ath_softc *sc) | |
289 | { | |
290 | spin_lock_bh(&sc->rx.rxbuflock); | |
291 | ||
292 | ath9k_hw_rxena(sc->sc_ah); | |
293 | ||
294 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, | |
295 | sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); | |
296 | ||
297 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, | |
298 | sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); | |
299 | ||
b5c80475 FF |
300 | ath_opmode_init(sc); |
301 | ||
48a6a468 | 302 | ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
7583c550 LR |
303 | |
304 | spin_unlock_bh(&sc->rx.rxbuflock); | |
b5c80475 FF |
305 | } |
306 | ||
307 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
308 | { | |
b5c80475 FF |
309 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
310 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
311 | } |
312 | ||
313 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
314 | { | |
315 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
316 | struct sk_buff *skb; | |
317 | struct ath_buf *bf; | |
318 | int error = 0; | |
319 | ||
4bdd1e97 | 320 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 FF |
321 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
322 | spin_lock_init(&sc->rx.rxbuflock); | |
323 | ||
0d95521e FF |
324 | common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + |
325 | sc->sc_ah->caps.rx_status_len; | |
326 | ||
b5c80475 FF |
327 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
328 | return ath_rx_edma_init(sc, nbufs); | |
329 | } else { | |
226afe68 JP |
330 | ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
331 | common->cachelsz, common->rx_bufsize); | |
b5c80475 FF |
332 | |
333 | /* Initialize rx descriptors */ | |
334 | ||
335 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
4adfcded | 336 | "rx", nbufs, 1, 0); |
b5c80475 | 337 | if (error != 0) { |
3800276a JP |
338 | ath_err(common, |
339 | "failed to allocate rx descriptors: %d\n", | |
340 | error); | |
797fe5cb S |
341 | goto err; |
342 | } | |
b5c80475 FF |
343 | |
344 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
345 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
346 | GFP_KERNEL); | |
347 | if (skb == NULL) { | |
348 | error = -ENOMEM; | |
349 | goto err; | |
350 | } | |
351 | ||
352 | bf->bf_mpdu = skb; | |
353 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
354 | common->rx_bufsize, | |
355 | DMA_FROM_DEVICE); | |
356 | if (unlikely(dma_mapping_error(sc->dev, | |
357 | bf->bf_buf_addr))) { | |
358 | dev_kfree_skb_any(skb); | |
359 | bf->bf_mpdu = NULL; | |
6cf9e995 | 360 | bf->bf_buf_addr = 0; |
3800276a JP |
361 | ath_err(common, |
362 | "dma_mapping_error() on RX init\n"); | |
b5c80475 FF |
363 | error = -ENOMEM; |
364 | goto err; | |
365 | } | |
b5c80475 FF |
366 | } |
367 | sc->rx.rxlink = NULL; | |
797fe5cb | 368 | } |
f078f209 | 369 | |
797fe5cb | 370 | err: |
f078f209 LR |
371 | if (error) |
372 | ath_rx_cleanup(sc); | |
373 | ||
374 | return error; | |
375 | } | |
376 | ||
f078f209 LR |
377 | void ath_rx_cleanup(struct ath_softc *sc) |
378 | { | |
cc861f74 LR |
379 | struct ath_hw *ah = sc->sc_ah; |
380 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
381 | struct sk_buff *skb; |
382 | struct ath_buf *bf; | |
383 | ||
b5c80475 FF |
384 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
385 | ath_rx_edma_cleanup(sc); | |
386 | return; | |
387 | } else { | |
388 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
389 | skb = bf->bf_mpdu; | |
390 | if (skb) { | |
391 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
392 | common->rx_bufsize, | |
393 | DMA_FROM_DEVICE); | |
394 | dev_kfree_skb(skb); | |
6cf9e995 BG |
395 | bf->bf_buf_addr = 0; |
396 | bf->bf_mpdu = NULL; | |
b5c80475 | 397 | } |
051b9191 | 398 | } |
f078f209 | 399 | |
b5c80475 FF |
400 | if (sc->rx.rxdma.dd_desc_len != 0) |
401 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
402 | } | |
f078f209 LR |
403 | } |
404 | ||
405 | /* | |
406 | * Calculate the receive filter according to the | |
407 | * operating mode and state: | |
408 | * | |
409 | * o always accept unicast, broadcast, and multicast traffic | |
410 | * o maintain current state of phy error reception (the hal | |
411 | * may enable phy error frames for noise immunity work) | |
412 | * o probe request frames are accepted only when operating in | |
413 | * hostap, adhoc, or monitor modes | |
414 | * o enable promiscuous mode according to the interface state | |
415 | * o accept beacons: | |
416 | * - when operating in adhoc mode so the 802.11 layer creates | |
417 | * node table entries for peers, | |
418 | * - when operating in station mode for collecting rssi data when | |
419 | * the station is otherwise quiet, or | |
420 | * - when operating as a repeater so we see repeater-sta beacons | |
421 | * - when scanning | |
422 | */ | |
423 | ||
424 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
425 | { | |
426 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 427 | |
f078f209 LR |
428 | u32 rfilt; |
429 | ||
430 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
431 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
432 | | ATH9K_RX_FILTER_MCAST; | |
433 | ||
9c1d8e4a | 434 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
435 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
436 | ||
217ba9da JM |
437 | /* |
438 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
439 | * mode interface or when in monitor mode. AP mode does not need this | |
440 | * since it receives all in-BSS frames anyway. | |
441 | */ | |
2e286947 | 442 | if (sc->sc_ah->is_monitoring) |
f078f209 | 443 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 444 | |
d42c6b71 S |
445 | if (sc->rx.rxfilter & FIF_CONTROL) |
446 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
447 | ||
dbaaa147 | 448 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 449 | (sc->nvifs <= 1) && |
dbaaa147 VT |
450 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
451 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
452 | else | |
f078f209 LR |
453 | rfilt |= ATH9K_RX_FILTER_BEACON; |
454 | ||
264bbec8 | 455 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
66afad01 | 456 | (sc->rx.rxfilter & FIF_PSPOLL)) |
dbaaa147 | 457 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 458 | |
7ea310be S |
459 | if (conf_is_ht(&sc->hw->conf)) |
460 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
461 | ||
7545daf4 | 462 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
5eb6ba83 JC |
463 | /* The following may also be needed for other older chips */ |
464 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
465 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
466 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
467 | } | |
468 | ||
f078f209 | 469 | return rfilt; |
7dcfdcd9 | 470 | |
f078f209 LR |
471 | #undef RX_FILTER_PRESERVE |
472 | } | |
473 | ||
f078f209 LR |
474 | int ath_startrecv(struct ath_softc *sc) |
475 | { | |
cbe61d8a | 476 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
477 | struct ath_buf *bf, *tbf; |
478 | ||
b5c80475 FF |
479 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
480 | ath_edma_start_recv(sc); | |
481 | return 0; | |
482 | } | |
483 | ||
b77f483f S |
484 | spin_lock_bh(&sc->rx.rxbuflock); |
485 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
486 | goto start_recv; |
487 | ||
b77f483f S |
488 | sc->rx.rxlink = NULL; |
489 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
490 | ath_rx_buf_link(sc, bf); |
491 | } | |
492 | ||
493 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 494 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
495 | goto start_recv; |
496 | ||
b77f483f | 497 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 498 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 499 | ath9k_hw_rxena(ah); |
f078f209 LR |
500 | |
501 | start_recv: | |
be0418ad | 502 | ath_opmode_init(sc); |
48a6a468 | 503 | ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
be0418ad | 504 | |
7583c550 LR |
505 | spin_unlock_bh(&sc->rx.rxbuflock); |
506 | ||
f078f209 LR |
507 | return 0; |
508 | } | |
509 | ||
f078f209 LR |
510 | bool ath_stoprecv(struct ath_softc *sc) |
511 | { | |
cbe61d8a | 512 | struct ath_hw *ah = sc->sc_ah; |
5882da02 | 513 | bool stopped, reset = false; |
f078f209 | 514 | |
1e450285 | 515 | spin_lock_bh(&sc->rx.rxbuflock); |
d47844a0 | 516 | ath9k_hw_abortpcurecv(ah); |
be0418ad | 517 | ath9k_hw_setrxfilter(ah, 0); |
5882da02 | 518 | stopped = ath9k_hw_stopdmarecv(ah, &reset); |
b5c80475 FF |
519 | |
520 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
521 | ath_edma_stop_recv(sc); | |
522 | else | |
523 | sc->rx.rxlink = NULL; | |
1e450285 | 524 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad | 525 | |
d584747b RM |
526 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
527 | unlikely(!stopped)) { | |
d7fd1b50 BG |
528 | ath_err(ath9k_hw_common(sc->sc_ah), |
529 | "Could not stop RX, we could be " | |
530 | "confusing the DMA engine when we start RX up\n"); | |
531 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
532 | } | |
2232d31b | 533 | return stopped && !reset; |
f078f209 LR |
534 | } |
535 | ||
f078f209 LR |
536 | void ath_flushrecv(struct ath_softc *sc) |
537 | { | |
98deeea0 | 538 | sc->sc_flags |= SC_OP_RXFLUSH; |
b5c80475 FF |
539 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
540 | ath_rx_tasklet(sc, 1, true); | |
541 | ath_rx_tasklet(sc, 1, false); | |
98deeea0 | 542 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
543 | } |
544 | ||
cc65965c JM |
545 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
546 | { | |
547 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
548 | struct ieee80211_mgmt *mgmt; | |
549 | u8 *pos, *end, id, elen; | |
550 | struct ieee80211_tim_ie *tim; | |
551 | ||
552 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
553 | pos = mgmt->u.beacon.variable; | |
554 | end = skb->data + skb->len; | |
555 | ||
556 | while (pos + 2 < end) { | |
557 | id = *pos++; | |
558 | elen = *pos++; | |
559 | if (pos + elen > end) | |
560 | break; | |
561 | ||
562 | if (id == WLAN_EID_TIM) { | |
563 | if (elen < sizeof(*tim)) | |
564 | break; | |
565 | tim = (struct ieee80211_tim_ie *) pos; | |
566 | if (tim->dtim_count != 0) | |
567 | break; | |
568 | return tim->bitmap_ctrl & 0x01; | |
569 | } | |
570 | ||
571 | pos += elen; | |
572 | } | |
573 | ||
574 | return false; | |
575 | } | |
576 | ||
cc65965c JM |
577 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
578 | { | |
579 | struct ieee80211_mgmt *mgmt; | |
1510718d | 580 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
581 | |
582 | if (skb->len < 24 + 8 + 2 + 2) | |
583 | return; | |
584 | ||
585 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
4801416c BG |
586 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) { |
587 | /* TODO: This doesn't work well if you have stations | |
588 | * associated to two different APs because curbssid | |
589 | * is just the last AP that any of the stations associated | |
590 | * with. | |
591 | */ | |
cc65965c | 592 | return; /* not from our current AP */ |
4801416c | 593 | } |
cc65965c | 594 | |
1b04b930 | 595 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 596 | |
1b04b930 S |
597 | if (sc->ps_flags & PS_BEACON_SYNC) { |
598 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
226afe68 JP |
599 | ath_dbg(common, ATH_DBG_PS, |
600 | "Reconfigure Beacon timers based on timestamp from the AP\n"); | |
99e4d43a | 601 | ath_set_beacon(sc); |
deb75188 | 602 | sc->ps_flags &= ~PS_TSFOOR_SYNC; |
ccdfeab6 JM |
603 | } |
604 | ||
cc65965c JM |
605 | if (ath_beacon_dtim_pending_cab(skb)) { |
606 | /* | |
607 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
608 | * frames. If the last broadcast/multicast frame is not |
609 | * received properly, the next beacon frame will work as | |
610 | * a backup trigger for returning into NETWORK SLEEP state, | |
611 | * so we are waiting for it as well. | |
cc65965c | 612 | */ |
226afe68 JP |
613 | ath_dbg(common, ATH_DBG_PS, |
614 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); | |
1b04b930 | 615 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
616 | return; |
617 | } | |
618 | ||
1b04b930 | 619 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
620 | /* |
621 | * This can happen if a broadcast frame is dropped or the AP | |
622 | * fails to send a frame indicating that all CAB frames have | |
623 | * been delivered. | |
624 | */ | |
1b04b930 | 625 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
226afe68 JP |
626 | ath_dbg(common, ATH_DBG_PS, |
627 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 628 | } |
cc65965c JM |
629 | } |
630 | ||
631 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
632 | { | |
633 | struct ieee80211_hdr *hdr; | |
c46917bb | 634 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
635 | |
636 | hdr = (struct ieee80211_hdr *)skb->data; | |
637 | ||
638 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 VT |
639 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
640 | && ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c | 641 | ath_rx_ps_beacon(sc, skb); |
1b04b930 | 642 | else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
cc65965c JM |
643 | (ieee80211_is_data(hdr->frame_control) || |
644 | ieee80211_is_action(hdr->frame_control)) && | |
645 | is_multicast_ether_addr(hdr->addr1) && | |
646 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
647 | /* |
648 | * No more broadcast/multicast frames to be received at this | |
649 | * point. | |
650 | */ | |
3fac6dfd | 651 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
226afe68 JP |
652 | ath_dbg(common, ATH_DBG_PS, |
653 | "All PS CAB frames received, back to sleep\n"); | |
1b04b930 | 654 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
655 | !is_multicast_ether_addr(hdr->addr1) && |
656 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 657 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
226afe68 JP |
658 | ath_dbg(common, ATH_DBG_PS, |
659 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", | |
1b04b930 S |
660 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
661 | PS_WAIT_FOR_CAB | | |
662 | PS_WAIT_FOR_PSPOLL_DATA | | |
663 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
664 | } |
665 | } | |
666 | ||
b5c80475 FF |
667 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
668 | enum ath9k_rx_qtype qtype) | |
f078f209 | 669 | { |
b5c80475 FF |
670 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
671 | struct ath_hw *ah = sc->sc_ah; | |
672 | struct ath_common *common = ath9k_hw_common(ah); | |
673 | struct sk_buff *skb; | |
674 | struct ath_buf *bf; | |
675 | int ret; | |
676 | ||
677 | skb = skb_peek(&rx_edma->rx_fifo); | |
678 | if (!skb) | |
679 | return false; | |
680 | ||
681 | bf = SKB_CB_ATHBUF(skb); | |
682 | BUG_ON(!bf); | |
683 | ||
ce9426d1 | 684 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
685 | common->rx_bufsize, DMA_FROM_DEVICE); |
686 | ||
687 | ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data); | |
ce9426d1 ML |
688 | if (ret == -EINPROGRESS) { |
689 | /*let device gain the buffer again*/ | |
690 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
691 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 692 | return false; |
ce9426d1 | 693 | } |
b5c80475 FF |
694 | |
695 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
696 | if (ret == -EINVAL) { | |
697 | /* corrupt descriptor, skip this one and the following one */ | |
698 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
699 | ath_rx_edma_buf_link(sc, qtype); | |
700 | skb = skb_peek(&rx_edma->rx_fifo); | |
701 | if (!skb) | |
702 | return true; | |
703 | ||
704 | bf = SKB_CB_ATHBUF(skb); | |
705 | BUG_ON(!bf); | |
706 | ||
707 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
708 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
709 | ath_rx_edma_buf_link(sc, qtype); | |
083e3e8d | 710 | return true; |
b5c80475 FF |
711 | } |
712 | skb_queue_tail(&rx_edma->rx_buffers, skb); | |
713 | ||
714 | return true; | |
715 | } | |
f078f209 | 716 | |
b5c80475 FF |
717 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
718 | struct ath_rx_status *rs, | |
719 | enum ath9k_rx_qtype qtype) | |
720 | { | |
721 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; | |
722 | struct sk_buff *skb; | |
be0418ad | 723 | struct ath_buf *bf; |
b5c80475 FF |
724 | |
725 | while (ath_edma_get_buffers(sc, qtype)); | |
726 | skb = __skb_dequeue(&rx_edma->rx_buffers); | |
727 | if (!skb) | |
728 | return NULL; | |
729 | ||
730 | bf = SKB_CB_ATHBUF(skb); | |
731 | ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data); | |
732 | return bf; | |
733 | } | |
734 | ||
735 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
736 | struct ath_rx_status *rs) | |
737 | { | |
738 | struct ath_hw *ah = sc->sc_ah; | |
739 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 740 | struct ath_desc *ds; |
b5c80475 FF |
741 | struct ath_buf *bf; |
742 | int ret; | |
743 | ||
744 | if (list_empty(&sc->rx.rxbuf)) { | |
745 | sc->rx.rxlink = NULL; | |
746 | return NULL; | |
747 | } | |
748 | ||
749 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
750 | ds = bf->bf_desc; | |
751 | ||
752 | /* | |
753 | * Must provide the virtual address of the current | |
754 | * descriptor, the physical address, and the virtual | |
755 | * address of the next descriptor in the h/w chain. | |
756 | * This allows the HAL to look ahead to see if the | |
757 | * hardware is done with a descriptor by checking the | |
758 | * done bit in the following descriptor and the address | |
759 | * of the current descriptor the DMA engine is working | |
760 | * on. All this is necessary because of our use of | |
761 | * a self-linked list to avoid rx overruns. | |
762 | */ | |
763 | ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0); | |
764 | if (ret == -EINPROGRESS) { | |
765 | struct ath_rx_status trs; | |
766 | struct ath_buf *tbf; | |
767 | struct ath_desc *tds; | |
768 | ||
769 | memset(&trs, 0, sizeof(trs)); | |
770 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
771 | sc->rx.rxlink = NULL; | |
772 | return NULL; | |
773 | } | |
774 | ||
775 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
776 | ||
777 | /* | |
778 | * On some hardware the descriptor status words could | |
779 | * get corrupted, including the done bit. Because of | |
780 | * this, check if the next descriptor's done bit is | |
781 | * set or not. | |
782 | * | |
783 | * If the next descriptor's done bit is set, the current | |
784 | * descriptor has been corrupted. Force s/w to discard | |
785 | * this descriptor and continue... | |
786 | */ | |
787 | ||
788 | tds = tbf->bf_desc; | |
789 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0); | |
790 | if (ret == -EINPROGRESS) | |
791 | return NULL; | |
792 | } | |
793 | ||
794 | if (!bf->bf_mpdu) | |
795 | return bf; | |
796 | ||
797 | /* | |
798 | * Synchronize the DMA transfer with CPU before | |
799 | * 1. accessing the frame | |
800 | * 2. requeueing the same buffer to h/w | |
801 | */ | |
ce9426d1 | 802 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
803 | common->rx_bufsize, |
804 | DMA_FROM_DEVICE); | |
805 | ||
806 | return bf; | |
807 | } | |
808 | ||
d435700f S |
809 | /* Assumes you've already done the endian to CPU conversion */ |
810 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 811 | struct ieee80211_hdr *hdr, |
d435700f S |
812 | struct ieee80211_rx_status *rxs, |
813 | struct ath_rx_status *rx_stats, | |
814 | bool *decrypt_error) | |
815 | { | |
38852b20 SB |
816 | #define is_mc_or_valid_tkip_keyix ((is_mc || \ |
817 | (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \ | |
818 | test_bit(rx_stats->rs_keyix, common->tkip_keymap)))) | |
819 | ||
d435700f | 820 | struct ath_hw *ah = common->ah; |
d435700f | 821 | __le16 fc; |
b7b1b512 | 822 | u8 rx_status_len = ah->caps.rx_status_len; |
d435700f | 823 | |
d435700f S |
824 | fc = hdr->frame_control; |
825 | ||
826 | if (!rx_stats->rs_datalen) | |
827 | return false; | |
828 | /* | |
829 | * rs_status follows rs_datalen so if rs_datalen is too large | |
830 | * we can take a hint that hardware corrupted it, so ignore | |
831 | * those frames. | |
832 | */ | |
b7b1b512 | 833 | if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) |
d435700f S |
834 | return false; |
835 | ||
0d95521e | 836 | /* Only use error bits from the last fragment */ |
d435700f | 837 | if (rx_stats->rs_more) |
0d95521e | 838 | return true; |
d435700f S |
839 | |
840 | /* | |
841 | * The rx_stats->rs_status will not be set until the end of the | |
842 | * chained descriptors so it can be ignored if rs_more is set. The | |
843 | * rs_more will be false at the last element of the chained | |
844 | * descriptors. | |
845 | */ | |
846 | if (rx_stats->rs_status != 0) { | |
847 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
848 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; | |
849 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) | |
850 | return false; | |
851 | ||
852 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { | |
853 | *decrypt_error = true; | |
854 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { | |
38852b20 | 855 | bool is_mc; |
56363dde FF |
856 | /* |
857 | * The MIC error bit is only valid if the frame | |
858 | * is not a control frame or fragment, and it was | |
859 | * decrypted using a valid TKIP key. | |
860 | */ | |
38852b20 SB |
861 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
862 | ||
56363dde FF |
863 | if (!ieee80211_is_ctl(fc) && |
864 | !ieee80211_has_morefrags(fc) && | |
865 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
38852b20 | 866 | is_mc_or_valid_tkip_keyix) |
d435700f | 867 | rxs->flag |= RX_FLAG_MMIC_ERROR; |
56363dde FF |
868 | else |
869 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; | |
d435700f S |
870 | } |
871 | /* | |
872 | * Reject error frames with the exception of | |
873 | * decryption and MIC failures. For monitor mode, | |
874 | * we also ignore the CRC error. | |
875 | */ | |
5f841b41 | 876 | if (ah->is_monitoring) { |
d435700f S |
877 | if (rx_stats->rs_status & |
878 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
879 | ATH9K_RXERR_CRC)) | |
880 | return false; | |
881 | } else { | |
882 | if (rx_stats->rs_status & | |
883 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
884 | return false; | |
885 | } | |
886 | } | |
887 | } | |
888 | return true; | |
889 | } | |
890 | ||
891 | static int ath9k_process_rate(struct ath_common *common, | |
892 | struct ieee80211_hw *hw, | |
893 | struct ath_rx_status *rx_stats, | |
9f167f64 | 894 | struct ieee80211_rx_status *rxs) |
d435700f S |
895 | { |
896 | struct ieee80211_supported_band *sband; | |
897 | enum ieee80211_band band; | |
898 | unsigned int i = 0; | |
899 | ||
900 | band = hw->conf.channel->band; | |
901 | sband = hw->wiphy->bands[band]; | |
902 | ||
903 | if (rx_stats->rs_rate & 0x80) { | |
904 | /* HT rate */ | |
905 | rxs->flag |= RX_FLAG_HT; | |
906 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
907 | rxs->flag |= RX_FLAG_40MHZ; | |
908 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
909 | rxs->flag |= RX_FLAG_SHORT_GI; | |
910 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; | |
911 | return 0; | |
912 | } | |
913 | ||
914 | for (i = 0; i < sband->n_bitrates; i++) { | |
915 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
916 | rxs->rate_idx = i; | |
917 | return 0; | |
918 | } | |
919 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
920 | rxs->flag |= RX_FLAG_SHORTPRE; | |
921 | rxs->rate_idx = i; | |
922 | return 0; | |
923 | } | |
924 | } | |
925 | ||
926 | /* | |
927 | * No valid hardware bitrate found -- we should not get here | |
928 | * because hardware has already validated this frame as OK. | |
929 | */ | |
226afe68 JP |
930 | ath_dbg(common, ATH_DBG_XMIT, |
931 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", | |
932 | rx_stats->rs_rate); | |
d435700f S |
933 | |
934 | return -EINVAL; | |
935 | } | |
936 | ||
937 | static void ath9k_process_rssi(struct ath_common *common, | |
938 | struct ieee80211_hw *hw, | |
9f167f64 | 939 | struct ieee80211_hdr *hdr, |
d435700f S |
940 | struct ath_rx_status *rx_stats) |
941 | { | |
9ac58615 | 942 | struct ath_softc *sc = hw->priv; |
d435700f | 943 | struct ath_hw *ah = common->ah; |
9fa23e17 | 944 | int last_rssi; |
d435700f S |
945 | __le16 fc; |
946 | ||
2b892a98 RM |
947 | if ((ah->opmode != NL80211_IFTYPE_STATION) && |
948 | (ah->opmode != NL80211_IFTYPE_ADHOC)) | |
9fa23e17 FF |
949 | return; |
950 | ||
d435700f | 951 | fc = hdr->frame_control; |
9fa23e17 | 952 | if (!ieee80211_is_beacon(fc) || |
4801416c BG |
953 | compare_ether_addr(hdr->addr3, common->curbssid)) { |
954 | /* TODO: This doesn't work well if you have stations | |
955 | * associated to two different APs because curbssid | |
956 | * is just the last AP that any of the stations associated | |
957 | * with. | |
958 | */ | |
9fa23e17 | 959 | return; |
4801416c | 960 | } |
d435700f | 961 | |
9fa23e17 | 962 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
9ac58615 | 963 | ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi); |
d435700f | 964 | |
9ac58615 | 965 | last_rssi = sc->last_rssi; |
d435700f S |
966 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
967 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, | |
968 | ATH_RSSI_EP_MULTIPLIER); | |
969 | if (rx_stats->rs_rssi < 0) | |
970 | rx_stats->rs_rssi = 0; | |
971 | ||
972 | /* Update Beacon RSSI, this is used by ANI. */ | |
9fa23e17 | 973 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
d435700f S |
974 | } |
975 | ||
976 | /* | |
977 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
978 | * up the frame up to let mac80211 handle the actual error case, be it no | |
979 | * decryption key or real decryption error. This let us keep statistics there. | |
980 | */ | |
981 | static int ath9k_rx_skb_preprocess(struct ath_common *common, | |
982 | struct ieee80211_hw *hw, | |
9f167f64 | 983 | struct ieee80211_hdr *hdr, |
d435700f S |
984 | struct ath_rx_status *rx_stats, |
985 | struct ieee80211_rx_status *rx_status, | |
986 | bool *decrypt_error) | |
987 | { | |
d435700f S |
988 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
989 | ||
990 | /* | |
991 | * everything but the rate is checked here, the rate check is done | |
992 | * separately to avoid doing two lookups for a rate for each frame. | |
993 | */ | |
9f167f64 | 994 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
995 | return -EINVAL; |
996 | ||
0d95521e FF |
997 | /* Only use status info from the last fragment */ |
998 | if (rx_stats->rs_more) | |
999 | return 0; | |
1000 | ||
9f167f64 | 1001 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
d435700f | 1002 | |
9f167f64 | 1003 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
1004 | return -EINVAL; |
1005 | ||
d435700f S |
1006 | rx_status->band = hw->conf.channel->band; |
1007 | rx_status->freq = hw->conf.channel->center_freq; | |
1008 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; | |
1009 | rx_status->antenna = rx_stats->rs_antenna; | |
6ebacbb7 | 1010 | rx_status->flag |= RX_FLAG_MACTIME_MPDU; |
d435700f S |
1011 | |
1012 | return 0; | |
1013 | } | |
1014 | ||
1015 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
1016 | struct sk_buff *skb, | |
1017 | struct ath_rx_status *rx_stats, | |
1018 | struct ieee80211_rx_status *rxs, | |
1019 | bool decrypt_error) | |
1020 | { | |
1021 | struct ath_hw *ah = common->ah; | |
1022 | struct ieee80211_hdr *hdr; | |
1023 | int hdrlen, padpos, padsize; | |
1024 | u8 keyix; | |
1025 | __le16 fc; | |
1026 | ||
1027 | /* see if any padding is done by the hw and remove it */ | |
1028 | hdr = (struct ieee80211_hdr *) skb->data; | |
1029 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1030 | fc = hdr->frame_control; | |
1031 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1032 | ||
1033 | /* The MAC header is padded to have 32-bit boundary if the | |
1034 | * packet payload is non-zero. The general calculation for | |
1035 | * padsize would take into account odd header lengths: | |
1036 | * padsize = (4 - padpos % 4) % 4; However, since only | |
1037 | * even-length headers are used, padding can only be 0 or 2 | |
1038 | * bytes and we can optimize this a bit. In addition, we must | |
1039 | * not try to remove padding from short control frames that do | |
1040 | * not have payload. */ | |
1041 | padsize = padpos & 3; | |
1042 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1043 | memmove(skb->data + padsize, skb->data, padpos); | |
1044 | skb_pull(skb, padsize); | |
1045 | } | |
1046 | ||
1047 | keyix = rx_stats->rs_keyix; | |
1048 | ||
1049 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1050 | ieee80211_has_protected(fc)) { | |
1051 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1052 | } else if (ieee80211_has_protected(fc) | |
1053 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1054 | keyix = skb->data[hdrlen + 3] >> 6; | |
1055 | ||
1056 | if (test_bit(keyix, common->keymap)) | |
1057 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1058 | } | |
1059 | if (ah->sw_mgmt_crypto && | |
1060 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1061 | ieee80211_is_mgmt(fc)) | |
1062 | /* Use software decrypt for management frames. */ | |
1063 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1064 | } | |
b5c80475 | 1065 | |
102885a5 VT |
1066 | static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb, |
1067 | struct ath_hw_antcomb_conf ant_conf, | |
1068 | int main_rssi_avg) | |
1069 | { | |
1070 | antcomb->quick_scan_cnt = 0; | |
1071 | ||
1072 | if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2) | |
1073 | antcomb->rssi_lna2 = main_rssi_avg; | |
1074 | else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1) | |
1075 | antcomb->rssi_lna1 = main_rssi_avg; | |
1076 | ||
1077 | switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) { | |
1078 | case (0x10): /* LNA2 A-B */ | |
1079 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1080 | antcomb->first_quick_scan_conf = | |
1081 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1082 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1083 | break; | |
1084 | case (0x20): /* LNA1 A-B */ | |
1085 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1086 | antcomb->first_quick_scan_conf = | |
1087 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1088 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1089 | break; | |
1090 | case (0x21): /* LNA1 LNA2 */ | |
1091 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2; | |
1092 | antcomb->first_quick_scan_conf = | |
1093 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1094 | antcomb->second_quick_scan_conf = | |
1095 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1096 | break; | |
1097 | case (0x12): /* LNA2 LNA1 */ | |
1098 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1; | |
1099 | antcomb->first_quick_scan_conf = | |
1100 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1101 | antcomb->second_quick_scan_conf = | |
1102 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1103 | break; | |
1104 | case (0x13): /* LNA2 A+B */ | |
1105 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1106 | antcomb->first_quick_scan_conf = | |
1107 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1108 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1109 | break; | |
1110 | case (0x23): /* LNA1 A+B */ | |
1111 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1112 | antcomb->first_quick_scan_conf = | |
1113 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1114 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1115 | break; | |
1116 | default: | |
1117 | break; | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb, | |
1122 | struct ath_hw_antcomb_conf *div_ant_conf, | |
1123 | int main_rssi_avg, int alt_rssi_avg, | |
1124 | int alt_ratio) | |
1125 | { | |
1126 | /* alt_good */ | |
1127 | switch (antcomb->quick_scan_cnt) { | |
1128 | case 0: | |
1129 | /* set alt to main, and alt to first conf */ | |
1130 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1131 | div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf; | |
1132 | break; | |
1133 | case 1: | |
1134 | /* set alt to main, and alt to first conf */ | |
1135 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1136 | div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf; | |
1137 | antcomb->rssi_first = main_rssi_avg; | |
1138 | antcomb->rssi_second = alt_rssi_avg; | |
1139 | ||
1140 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1141 | /* main is LNA1 */ | |
1142 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1143 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1144 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1145 | main_rssi_avg, alt_rssi_avg, | |
1146 | antcomb->total_pkt_count)) | |
1147 | antcomb->first_ratio = true; | |
1148 | else | |
1149 | antcomb->first_ratio = false; | |
1150 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1151 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1152 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1153 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1154 | main_rssi_avg, alt_rssi_avg, | |
1155 | antcomb->total_pkt_count)) | |
1156 | antcomb->first_ratio = true; | |
1157 | else | |
1158 | antcomb->first_ratio = false; | |
1159 | } else { | |
1160 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1161 | (alt_rssi_avg > main_rssi_avg + | |
1162 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1163 | (alt_rssi_avg > main_rssi_avg)) && | |
1164 | (antcomb->total_pkt_count > 50)) | |
1165 | antcomb->first_ratio = true; | |
1166 | else | |
1167 | antcomb->first_ratio = false; | |
1168 | } | |
1169 | break; | |
1170 | case 2: | |
1171 | antcomb->alt_good = false; | |
1172 | antcomb->scan_not_start = false; | |
1173 | antcomb->scan = false; | |
1174 | antcomb->rssi_first = main_rssi_avg; | |
1175 | antcomb->rssi_third = alt_rssi_avg; | |
1176 | ||
1177 | if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1) | |
1178 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1179 | else if (antcomb->second_quick_scan_conf == | |
1180 | ATH_ANT_DIV_COMB_LNA2) | |
1181 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1182 | else if (antcomb->second_quick_scan_conf == | |
1183 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) { | |
1184 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) | |
1185 | antcomb->rssi_lna2 = main_rssi_avg; | |
1186 | else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) | |
1187 | antcomb->rssi_lna1 = main_rssi_avg; | |
1188 | } | |
1189 | ||
1190 | if (antcomb->rssi_lna2 > antcomb->rssi_lna1 + | |
1191 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA) | |
1192 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1193 | else | |
1194 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
1195 | ||
1196 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1197 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1198 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1199 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1200 | main_rssi_avg, alt_rssi_avg, | |
1201 | antcomb->total_pkt_count)) | |
1202 | antcomb->second_ratio = true; | |
1203 | else | |
1204 | antcomb->second_ratio = false; | |
1205 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1206 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1207 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1208 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1209 | main_rssi_avg, alt_rssi_avg, | |
1210 | antcomb->total_pkt_count)) | |
1211 | antcomb->second_ratio = true; | |
1212 | else | |
1213 | antcomb->second_ratio = false; | |
1214 | } else { | |
1215 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1216 | (alt_rssi_avg > main_rssi_avg + | |
1217 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1218 | (alt_rssi_avg > main_rssi_avg)) && | |
1219 | (antcomb->total_pkt_count > 50)) | |
1220 | antcomb->second_ratio = true; | |
1221 | else | |
1222 | antcomb->second_ratio = false; | |
1223 | } | |
1224 | ||
1225 | /* set alt to the conf with maximun ratio */ | |
1226 | if (antcomb->first_ratio && antcomb->second_ratio) { | |
1227 | if (antcomb->rssi_second > antcomb->rssi_third) { | |
1228 | /* first alt*/ | |
1229 | if ((antcomb->first_quick_scan_conf == | |
1230 | ATH_ANT_DIV_COMB_LNA1) || | |
1231 | (antcomb->first_quick_scan_conf == | |
1232 | ATH_ANT_DIV_COMB_LNA2)) | |
1233 | /* Set alt LNA1 or LNA2*/ | |
1234 | if (div_ant_conf->main_lna_conf == | |
1235 | ATH_ANT_DIV_COMB_LNA2) | |
1236 | div_ant_conf->alt_lna_conf = | |
1237 | ATH_ANT_DIV_COMB_LNA1; | |
1238 | else | |
1239 | div_ant_conf->alt_lna_conf = | |
1240 | ATH_ANT_DIV_COMB_LNA2; | |
1241 | else | |
1242 | /* Set alt to A+B or A-B */ | |
1243 | div_ant_conf->alt_lna_conf = | |
1244 | antcomb->first_quick_scan_conf; | |
1245 | } else if ((antcomb->second_quick_scan_conf == | |
1246 | ATH_ANT_DIV_COMB_LNA1) || | |
1247 | (antcomb->second_quick_scan_conf == | |
1248 | ATH_ANT_DIV_COMB_LNA2)) { | |
1249 | /* Set alt LNA1 or LNA2 */ | |
1250 | if (div_ant_conf->main_lna_conf == | |
1251 | ATH_ANT_DIV_COMB_LNA2) | |
1252 | div_ant_conf->alt_lna_conf = | |
1253 | ATH_ANT_DIV_COMB_LNA1; | |
1254 | else | |
1255 | div_ant_conf->alt_lna_conf = | |
1256 | ATH_ANT_DIV_COMB_LNA2; | |
1257 | } else { | |
1258 | /* Set alt to A+B or A-B */ | |
1259 | div_ant_conf->alt_lna_conf = | |
1260 | antcomb->second_quick_scan_conf; | |
1261 | } | |
1262 | } else if (antcomb->first_ratio) { | |
1263 | /* first alt */ | |
1264 | if ((antcomb->first_quick_scan_conf == | |
1265 | ATH_ANT_DIV_COMB_LNA1) || | |
1266 | (antcomb->first_quick_scan_conf == | |
1267 | ATH_ANT_DIV_COMB_LNA2)) | |
1268 | /* Set alt LNA1 or LNA2 */ | |
1269 | if (div_ant_conf->main_lna_conf == | |
1270 | ATH_ANT_DIV_COMB_LNA2) | |
1271 | div_ant_conf->alt_lna_conf = | |
1272 | ATH_ANT_DIV_COMB_LNA1; | |
1273 | else | |
1274 | div_ant_conf->alt_lna_conf = | |
1275 | ATH_ANT_DIV_COMB_LNA2; | |
1276 | else | |
1277 | /* Set alt to A+B or A-B */ | |
1278 | div_ant_conf->alt_lna_conf = | |
1279 | antcomb->first_quick_scan_conf; | |
1280 | } else if (antcomb->second_ratio) { | |
1281 | /* second alt */ | |
1282 | if ((antcomb->second_quick_scan_conf == | |
1283 | ATH_ANT_DIV_COMB_LNA1) || | |
1284 | (antcomb->second_quick_scan_conf == | |
1285 | ATH_ANT_DIV_COMB_LNA2)) | |
1286 | /* Set alt LNA1 or LNA2 */ | |
1287 | if (div_ant_conf->main_lna_conf == | |
1288 | ATH_ANT_DIV_COMB_LNA2) | |
1289 | div_ant_conf->alt_lna_conf = | |
1290 | ATH_ANT_DIV_COMB_LNA1; | |
1291 | else | |
1292 | div_ant_conf->alt_lna_conf = | |
1293 | ATH_ANT_DIV_COMB_LNA2; | |
1294 | else | |
1295 | /* Set alt to A+B or A-B */ | |
1296 | div_ant_conf->alt_lna_conf = | |
1297 | antcomb->second_quick_scan_conf; | |
1298 | } else { | |
1299 | /* main is largest */ | |
1300 | if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) || | |
1301 | (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)) | |
1302 | /* Set alt LNA1 or LNA2 */ | |
1303 | if (div_ant_conf->main_lna_conf == | |
1304 | ATH_ANT_DIV_COMB_LNA2) | |
1305 | div_ant_conf->alt_lna_conf = | |
1306 | ATH_ANT_DIV_COMB_LNA1; | |
1307 | else | |
1308 | div_ant_conf->alt_lna_conf = | |
1309 | ATH_ANT_DIV_COMB_LNA2; | |
1310 | else | |
1311 | /* Set alt to A+B or A-B */ | |
1312 | div_ant_conf->alt_lna_conf = antcomb->main_conf; | |
1313 | } | |
1314 | break; | |
1315 | default: | |
1316 | break; | |
1317 | } | |
1318 | } | |
1319 | ||
9bad82b8 | 1320 | static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf) |
102885a5 VT |
1321 | { |
1322 | /* Adjust the fast_div_bias based on main and alt lna conf */ | |
1323 | switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) { | |
1324 | case (0x01): /* A-B LNA2 */ | |
1325 | ant_conf->fast_div_bias = 0x3b; | |
1326 | break; | |
1327 | case (0x02): /* A-B LNA1 */ | |
1328 | ant_conf->fast_div_bias = 0x3d; | |
1329 | break; | |
1330 | case (0x03): /* A-B A+B */ | |
1331 | ant_conf->fast_div_bias = 0x1; | |
1332 | break; | |
1333 | case (0x10): /* LNA2 A-B */ | |
1334 | ant_conf->fast_div_bias = 0x7; | |
1335 | break; | |
1336 | case (0x12): /* LNA2 LNA1 */ | |
1337 | ant_conf->fast_div_bias = 0x2; | |
1338 | break; | |
1339 | case (0x13): /* LNA2 A+B */ | |
1340 | ant_conf->fast_div_bias = 0x7; | |
1341 | break; | |
1342 | case (0x20): /* LNA1 A-B */ | |
1343 | ant_conf->fast_div_bias = 0x6; | |
1344 | break; | |
1345 | case (0x21): /* LNA1 LNA2 */ | |
1346 | ant_conf->fast_div_bias = 0x0; | |
1347 | break; | |
1348 | case (0x23): /* LNA1 A+B */ | |
1349 | ant_conf->fast_div_bias = 0x6; | |
1350 | break; | |
1351 | case (0x30): /* A+B A-B */ | |
1352 | ant_conf->fast_div_bias = 0x1; | |
1353 | break; | |
1354 | case (0x31): /* A+B LNA2 */ | |
1355 | ant_conf->fast_div_bias = 0x3b; | |
1356 | break; | |
1357 | case (0x32): /* A+B LNA1 */ | |
1358 | ant_conf->fast_div_bias = 0x3d; | |
1359 | break; | |
1360 | default: | |
1361 | break; | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | /* Antenna diversity and combining */ | |
1366 | static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs) | |
1367 | { | |
1368 | struct ath_hw_antcomb_conf div_ant_conf; | |
1369 | struct ath_ant_comb *antcomb = &sc->ant_comb; | |
1370 | int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set; | |
0ff2b5c0 | 1371 | int curr_main_set; |
102885a5 VT |
1372 | int main_rssi = rs->rs_rssi_ctl0; |
1373 | int alt_rssi = rs->rs_rssi_ctl1; | |
1374 | int rx_ant_conf, main_ant_conf; | |
1375 | bool short_scan = false; | |
1376 | ||
1377 | rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) & | |
1378 | ATH_ANT_RX_MASK; | |
1379 | main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) & | |
1380 | ATH_ANT_RX_MASK; | |
1381 | ||
1382 | /* Record packet only when alt_rssi is positive */ | |
1383 | if (alt_rssi > 0) { | |
1384 | antcomb->total_pkt_count++; | |
1385 | antcomb->main_total_rssi += main_rssi; | |
1386 | antcomb->alt_total_rssi += alt_rssi; | |
1387 | if (main_ant_conf == rx_ant_conf) | |
1388 | antcomb->main_recv_cnt++; | |
1389 | else | |
1390 | antcomb->alt_recv_cnt++; | |
1391 | } | |
1392 | ||
1393 | /* Short scan check */ | |
1394 | if (antcomb->scan && antcomb->alt_good) { | |
1395 | if (time_after(jiffies, antcomb->scan_start_time + | |
1396 | msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR))) | |
1397 | short_scan = true; | |
1398 | else | |
1399 | if (antcomb->total_pkt_count == | |
1400 | ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) { | |
1401 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1402 | antcomb->total_pkt_count); | |
1403 | if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO) | |
1404 | short_scan = true; | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) || | |
1409 | rs->rs_moreaggr) && !short_scan) | |
1410 | return; | |
1411 | ||
1412 | if (antcomb->total_pkt_count) { | |
1413 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1414 | antcomb->total_pkt_count); | |
1415 | main_rssi_avg = (antcomb->main_total_rssi / | |
1416 | antcomb->total_pkt_count); | |
1417 | alt_rssi_avg = (antcomb->alt_total_rssi / | |
1418 | antcomb->total_pkt_count); | |
1419 | } | |
1420 | ||
1421 | ||
1422 | ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf); | |
1423 | curr_alt_set = div_ant_conf.alt_lna_conf; | |
1424 | curr_main_set = div_ant_conf.main_lna_conf; | |
102885a5 VT |
1425 | |
1426 | antcomb->count++; | |
1427 | ||
1428 | if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) { | |
1429 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { | |
1430 | ath_lnaconf_alt_good_scan(antcomb, div_ant_conf, | |
1431 | main_rssi_avg); | |
1432 | antcomb->alt_good = true; | |
1433 | } else { | |
1434 | antcomb->alt_good = false; | |
1435 | } | |
1436 | ||
1437 | antcomb->count = 0; | |
1438 | antcomb->scan = true; | |
1439 | antcomb->scan_not_start = true; | |
1440 | } | |
1441 | ||
1442 | if (!antcomb->scan) { | |
b85c5734 MSS |
1443 | if (ath_ant_div_comb_alt_check(div_ant_conf.div_group, |
1444 | alt_ratio, curr_main_set, curr_alt_set, | |
1445 | alt_rssi_avg, main_rssi_avg)) { | |
102885a5 VT |
1446 | if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) { |
1447 | /* Switch main and alt LNA */ | |
1448 | div_ant_conf.main_lna_conf = | |
1449 | ATH_ANT_DIV_COMB_LNA2; | |
1450 | div_ant_conf.alt_lna_conf = | |
1451 | ATH_ANT_DIV_COMB_LNA1; | |
1452 | } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) { | |
1453 | div_ant_conf.main_lna_conf = | |
1454 | ATH_ANT_DIV_COMB_LNA1; | |
1455 | div_ant_conf.alt_lna_conf = | |
1456 | ATH_ANT_DIV_COMB_LNA2; | |
1457 | } | |
1458 | ||
1459 | goto div_comb_done; | |
1460 | } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) && | |
1461 | (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) { | |
1462 | /* Set alt to another LNA */ | |
1463 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) | |
1464 | div_ant_conf.alt_lna_conf = | |
1465 | ATH_ANT_DIV_COMB_LNA1; | |
1466 | else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) | |
1467 | div_ant_conf.alt_lna_conf = | |
1468 | ATH_ANT_DIV_COMB_LNA2; | |
1469 | ||
1470 | goto div_comb_done; | |
1471 | } | |
1472 | ||
1473 | if ((alt_rssi_avg < (main_rssi_avg + | |
8afbcc8b | 1474 | div_ant_conf.lna1_lna2_delta))) |
102885a5 VT |
1475 | goto div_comb_done; |
1476 | } | |
1477 | ||
1478 | if (!antcomb->scan_not_start) { | |
1479 | switch (curr_alt_set) { | |
1480 | case ATH_ANT_DIV_COMB_LNA2: | |
1481 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1482 | antcomb->rssi_lna1 = main_rssi_avg; | |
1483 | antcomb->scan = true; | |
1484 | /* set to A+B */ | |
1485 | div_ant_conf.main_lna_conf = | |
1486 | ATH_ANT_DIV_COMB_LNA1; | |
1487 | div_ant_conf.alt_lna_conf = | |
1488 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1489 | break; | |
1490 | case ATH_ANT_DIV_COMB_LNA1: | |
1491 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1492 | antcomb->rssi_lna2 = main_rssi_avg; | |
1493 | antcomb->scan = true; | |
1494 | /* set to A+B */ | |
1495 | div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1496 | div_ant_conf.alt_lna_conf = | |
1497 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1498 | break; | |
1499 | case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2: | |
1500 | antcomb->rssi_add = alt_rssi_avg; | |
1501 | antcomb->scan = true; | |
1502 | /* set to A-B */ | |
1503 | div_ant_conf.alt_lna_conf = | |
1504 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1505 | break; | |
1506 | case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2: | |
1507 | antcomb->rssi_sub = alt_rssi_avg; | |
1508 | antcomb->scan = false; | |
1509 | if (antcomb->rssi_lna2 > | |
1510 | (antcomb->rssi_lna1 + | |
1511 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) { | |
1512 | /* use LNA2 as main LNA */ | |
1513 | if ((antcomb->rssi_add > antcomb->rssi_lna1) && | |
1514 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1515 | /* set to A+B */ | |
1516 | div_ant_conf.main_lna_conf = | |
1517 | ATH_ANT_DIV_COMB_LNA2; | |
1518 | div_ant_conf.alt_lna_conf = | |
1519 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1520 | } else if (antcomb->rssi_sub > | |
1521 | antcomb->rssi_lna1) { | |
1522 | /* set to A-B */ | |
1523 | div_ant_conf.main_lna_conf = | |
1524 | ATH_ANT_DIV_COMB_LNA2; | |
1525 | div_ant_conf.alt_lna_conf = | |
1526 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1527 | } else { | |
1528 | /* set to LNA1 */ | |
1529 | div_ant_conf.main_lna_conf = | |
1530 | ATH_ANT_DIV_COMB_LNA2; | |
1531 | div_ant_conf.alt_lna_conf = | |
1532 | ATH_ANT_DIV_COMB_LNA1; | |
1533 | } | |
1534 | } else { | |
1535 | /* use LNA1 as main LNA */ | |
1536 | if ((antcomb->rssi_add > antcomb->rssi_lna2) && | |
1537 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1538 | /* set to A+B */ | |
1539 | div_ant_conf.main_lna_conf = | |
1540 | ATH_ANT_DIV_COMB_LNA1; | |
1541 | div_ant_conf.alt_lna_conf = | |
1542 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1543 | } else if (antcomb->rssi_sub > | |
1544 | antcomb->rssi_lna1) { | |
1545 | /* set to A-B */ | |
1546 | div_ant_conf.main_lna_conf = | |
1547 | ATH_ANT_DIV_COMB_LNA1; | |
1548 | div_ant_conf.alt_lna_conf = | |
1549 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1550 | } else { | |
1551 | /* set to LNA2 */ | |
1552 | div_ant_conf.main_lna_conf = | |
1553 | ATH_ANT_DIV_COMB_LNA1; | |
1554 | div_ant_conf.alt_lna_conf = | |
1555 | ATH_ANT_DIV_COMB_LNA2; | |
1556 | } | |
1557 | } | |
1558 | break; | |
1559 | default: | |
1560 | break; | |
1561 | } | |
1562 | } else { | |
1563 | if (!antcomb->alt_good) { | |
1564 | antcomb->scan_not_start = false; | |
1565 | /* Set alt to another LNA */ | |
1566 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) { | |
1567 | div_ant_conf.main_lna_conf = | |
1568 | ATH_ANT_DIV_COMB_LNA2; | |
1569 | div_ant_conf.alt_lna_conf = | |
1570 | ATH_ANT_DIV_COMB_LNA1; | |
1571 | } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) { | |
1572 | div_ant_conf.main_lna_conf = | |
1573 | ATH_ANT_DIV_COMB_LNA1; | |
1574 | div_ant_conf.alt_lna_conf = | |
1575 | ATH_ANT_DIV_COMB_LNA2; | |
1576 | } | |
1577 | goto div_comb_done; | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf, | |
1582 | main_rssi_avg, alt_rssi_avg, | |
1583 | alt_ratio); | |
1584 | ||
1585 | antcomb->quick_scan_cnt++; | |
1586 | ||
1587 | div_comb_done: | |
1588 | ath_ant_div_conf_fast_divbias(&div_ant_conf); | |
1589 | ||
1590 | ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf); | |
1591 | ||
1592 | antcomb->scan_start_time = jiffies; | |
1593 | antcomb->total_pkt_count = 0; | |
1594 | antcomb->main_total_rssi = 0; | |
1595 | antcomb->alt_total_rssi = 0; | |
1596 | antcomb->main_recv_cnt = 0; | |
1597 | antcomb->alt_recv_cnt = 0; | |
1598 | } | |
1599 | ||
b5c80475 FF |
1600 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) |
1601 | { | |
1602 | struct ath_buf *bf; | |
0d95521e | 1603 | struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; |
5ca42627 | 1604 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1605 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 1606 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 | 1607 | /* |
cae6b74d | 1608 | * The hw can technically differ from common->hw when using ath9k |
b4afffc0 LR |
1609 | * virtual wiphy so to account for that we iterate over the active |
1610 | * wiphys and find the appropriate wiphy and therefore hw. | |
1611 | */ | |
7545daf4 | 1612 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1613 | struct ieee80211_hdr *hdr; |
c9b14170 | 1614 | int retval; |
be0418ad | 1615 | bool decrypt_error = false; |
29bffa96 | 1616 | struct ath_rx_status rs; |
b5c80475 FF |
1617 | enum ath9k_rx_qtype qtype; |
1618 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1619 | int dma_type; | |
5c6dd921 | 1620 | u8 rx_status_len = ah->caps.rx_status_len; |
a6d2055b FF |
1621 | u64 tsf = 0; |
1622 | u32 tsf_lower = 0; | |
8ab2cd09 | 1623 | unsigned long flags; |
be0418ad | 1624 | |
b5c80475 | 1625 | if (edma) |
b5c80475 | 1626 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1627 | else |
1628 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1629 | |
1630 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
b77f483f | 1631 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 | 1632 | |
a6d2055b FF |
1633 | tsf = ath9k_hw_gettsf64(ah); |
1634 | tsf_lower = tsf & 0xffffffff; | |
1635 | ||
f078f209 LR |
1636 | do { |
1637 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 1638 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
1639 | break; |
1640 | ||
29bffa96 | 1641 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1642 | if (edma) |
1643 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1644 | else | |
1645 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1646 | |
b5c80475 FF |
1647 | if (!bf) |
1648 | break; | |
f078f209 | 1649 | |
f078f209 | 1650 | skb = bf->bf_mpdu; |
be0418ad | 1651 | if (!skb) |
f078f209 | 1652 | continue; |
f078f209 | 1653 | |
0d95521e FF |
1654 | /* |
1655 | * Take frame header from the first fragment and RX status from | |
1656 | * the last one. | |
1657 | */ | |
1658 | if (sc->rx.frag) | |
1659 | hdr_skb = sc->rx.frag; | |
1660 | else | |
1661 | hdr_skb = skb; | |
1662 | ||
1663 | hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len); | |
1664 | rxs = IEEE80211_SKB_RXCB(hdr_skb); | |
5ca42627 | 1665 | |
29bffa96 | 1666 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1667 | |
f078f209 | 1668 | /* |
be0418ad S |
1669 | * If we're asked to flush receive queue, directly |
1670 | * chain it back at the queue without processing it. | |
f078f209 | 1671 | */ |
be0418ad | 1672 | if (flush) |
0d95521e | 1673 | goto requeue_drop_frag; |
f078f209 | 1674 | |
c8f3b721 JF |
1675 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, |
1676 | rxs, &decrypt_error); | |
1677 | if (retval) | |
0d95521e | 1678 | goto requeue_drop_frag; |
c8f3b721 | 1679 | |
a6d2055b FF |
1680 | rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; |
1681 | if (rs.rs_tstamp > tsf_lower && | |
1682 | unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) | |
1683 | rxs->mactime -= 0x100000000ULL; | |
1684 | ||
1685 | if (rs.rs_tstamp < tsf_lower && | |
1686 | unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) | |
1687 | rxs->mactime += 0x100000000ULL; | |
1688 | ||
cb71d9ba LR |
1689 | /* Ensure we always have an skb to requeue once we are done |
1690 | * processing the current buffer's skb */ | |
cc861f74 | 1691 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1692 | |
1693 | /* If there is no memory we ignore the current RX'd frame, | |
1694 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1695 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
1696 | * processing. */ |
1697 | if (!requeue_skb) | |
0d95521e | 1698 | goto requeue_drop_frag; |
f078f209 | 1699 | |
9bf9fca8 | 1700 | /* Unmap the frame */ |
7da3c55c | 1701 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 1702 | common->rx_bufsize, |
b5c80475 | 1703 | dma_type); |
f078f209 | 1704 | |
b5c80475 FF |
1705 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1706 | if (ah->caps.rx_status_len) | |
1707 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1708 | |
0d95521e FF |
1709 | if (!rs.rs_more) |
1710 | ath9k_rx_skb_postprocess(common, hdr_skb, &rs, | |
1711 | rxs, decrypt_error); | |
be0418ad | 1712 | |
cb71d9ba LR |
1713 | /* We will now give hardware our shiny new allocated skb */ |
1714 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 1715 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 | 1716 | common->rx_bufsize, |
b5c80475 | 1717 | dma_type); |
7da3c55c | 1718 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
1719 | bf->bf_buf_addr))) { |
1720 | dev_kfree_skb_any(requeue_skb); | |
1721 | bf->bf_mpdu = NULL; | |
6cf9e995 | 1722 | bf->bf_buf_addr = 0; |
3800276a | 1723 | ath_err(common, "dma_mapping_error() on RX\n"); |
7545daf4 | 1724 | ieee80211_rx(hw, skb); |
f8316df1 LR |
1725 | break; |
1726 | } | |
f078f209 | 1727 | |
0d95521e FF |
1728 | if (rs.rs_more) { |
1729 | /* | |
1730 | * rs_more indicates chained descriptors which can be | |
1731 | * used to link buffers together for a sort of | |
1732 | * scatter-gather operation. | |
1733 | */ | |
1734 | if (sc->rx.frag) { | |
1735 | /* too many fragments - cannot handle frame */ | |
1736 | dev_kfree_skb_any(sc->rx.frag); | |
1737 | dev_kfree_skb_any(skb); | |
1738 | skb = NULL; | |
1739 | } | |
1740 | sc->rx.frag = skb; | |
1741 | goto requeue; | |
1742 | } | |
1743 | ||
1744 | if (sc->rx.frag) { | |
1745 | int space = skb->len - skb_tailroom(hdr_skb); | |
1746 | ||
1747 | sc->rx.frag = NULL; | |
1748 | ||
1749 | if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { | |
1750 | dev_kfree_skb(skb); | |
1751 | goto requeue_drop_frag; | |
1752 | } | |
1753 | ||
1754 | skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), | |
1755 | skb->len); | |
1756 | dev_kfree_skb_any(skb); | |
1757 | skb = hdr_skb; | |
1758 | } | |
1759 | ||
f078f209 LR |
1760 | /* |
1761 | * change the default rx antenna if rx diversity chooses the | |
1762 | * other antenna 3 times in a row. | |
1763 | */ | |
29bffa96 | 1764 | if (sc->rx.defant != rs.rs_antenna) { |
b77f483f | 1765 | if (++sc->rx.rxotherant >= 3) |
29bffa96 | 1766 | ath_setdefantenna(sc, rs.rs_antenna); |
f078f209 | 1767 | } else { |
b77f483f | 1768 | sc->rx.rxotherant = 0; |
f078f209 | 1769 | } |
3cbb5dd7 | 1770 | |
8ab2cd09 | 1771 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
aaef24b4 MSS |
1772 | |
1773 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
ededf1f8 | 1774 | PS_WAIT_FOR_CAB | |
aaef24b4 | 1775 | PS_WAIT_FOR_PSPOLL_DATA)) || |
cedc7e3d | 1776 | ath9k_check_auto_sleep(sc)) |
cc65965c | 1777 | ath_rx_ps(sc, skb); |
8ab2cd09 | 1778 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
cc65965c | 1779 | |
102885a5 VT |
1780 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) |
1781 | ath_ant_comb_scan(sc, &rs); | |
1782 | ||
7545daf4 | 1783 | ieee80211_rx(hw, skb); |
cc65965c | 1784 | |
0d95521e FF |
1785 | requeue_drop_frag: |
1786 | if (sc->rx.frag) { | |
1787 | dev_kfree_skb_any(sc->rx.frag); | |
1788 | sc->rx.frag = NULL; | |
1789 | } | |
cb71d9ba | 1790 | requeue: |
b5c80475 FF |
1791 | if (edma) { |
1792 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
1793 | ath_rx_edma_buf_link(sc, qtype); | |
1794 | } else { | |
1795 | list_move_tail(&bf->list, &sc->rx.rxbuf); | |
1796 | ath_rx_buf_link(sc, bf); | |
95294973 | 1797 | ath9k_hw_rxena(ah); |
b5c80475 | 1798 | } |
be0418ad S |
1799 | } while (1); |
1800 | ||
b77f483f | 1801 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
1802 | |
1803 | return 0; | |
f078f209 | 1804 | } |