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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
e93d083f | 18 | #include <linux/relay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
b622a720 | 20 | #include "ar9003_mac.h" |
f078f209 | 21 | |
b5c80475 FF |
22 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
23 | ||
ededf1f8 VT |
24 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
25 | { | |
26 | return sc->ps_enabled && | |
27 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
28 | } | |
29 | ||
f078f209 LR |
30 | /* |
31 | * Setup and link descriptors. | |
32 | * | |
33 | * 11N: we can no longer afford to self link the last descriptor. | |
34 | * MAC acknowledges BA status as long as it copies frames to host | |
35 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
36 | * to a sender if last desc is self-linked. | |
f078f209 | 37 | */ |
f078f209 LR |
38 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
39 | { | |
cbe61d8a | 40 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 41 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
42 | struct ath_desc *ds; |
43 | struct sk_buff *skb; | |
44 | ||
45 | ATH_RXBUF_RESET(bf); | |
46 | ||
47 | ds = bf->bf_desc; | |
be0418ad | 48 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
49 | ds->ds_data = bf->bf_buf_addr; |
50 | ||
be0418ad | 51 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 52 | skb = bf->bf_mpdu; |
9680e8a3 | 53 | BUG_ON(skb == NULL); |
f078f209 LR |
54 | ds->ds_vdata = skb->data; |
55 | ||
cc861f74 LR |
56 | /* |
57 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 58 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
59 | * to process |
60 | */ | |
b77f483f | 61 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 62 | common->rx_bufsize, |
f078f209 LR |
63 | 0); |
64 | ||
b77f483f | 65 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
66 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
67 | else | |
b77f483f | 68 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 69 | |
b77f483f | 70 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
71 | } |
72 | ||
ff37e337 S |
73 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
74 | { | |
75 | /* XXX block beacon interrupts */ | |
76 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
77 | sc->rx.defant = antenna; |
78 | sc->rx.rxotherant = 0; | |
ff37e337 S |
79 | } |
80 | ||
f078f209 LR |
81 | static void ath_opmode_init(struct ath_softc *sc) |
82 | { | |
cbe61d8a | 83 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
84 | struct ath_common *common = ath9k_hw_common(ah); |
85 | ||
f078f209 LR |
86 | u32 rfilt, mfilt[2]; |
87 | ||
88 | /* configure rx filter */ | |
89 | rfilt = ath_calcrxfilter(sc); | |
90 | ath9k_hw_setrxfilter(ah, rfilt); | |
91 | ||
92 | /* configure bssid mask */ | |
364734fa | 93 | ath_hw_setbssidmask(common); |
f078f209 LR |
94 | |
95 | /* configure operational mode */ | |
96 | ath9k_hw_setopmode(ah); | |
97 | ||
f078f209 LR |
98 | /* calculate and install multicast filter */ |
99 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 100 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
101 | } |
102 | ||
b5c80475 FF |
103 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
104 | enum ath9k_rx_qtype qtype) | |
f078f209 | 105 | { |
b5c80475 FF |
106 | struct ath_hw *ah = sc->sc_ah; |
107 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
108 | struct sk_buff *skb; |
109 | struct ath_buf *bf; | |
f078f209 | 110 | |
b5c80475 FF |
111 | rx_edma = &sc->rx.rx_edma[qtype]; |
112 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
113 | return false; | |
f078f209 | 114 | |
b5c80475 FF |
115 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
116 | list_del_init(&bf->list); | |
f078f209 | 117 | |
b5c80475 FF |
118 | skb = bf->bf_mpdu; |
119 | ||
120 | ATH_RXBUF_RESET(bf); | |
121 | memset(skb->data, 0, ah->caps.rx_status_len); | |
122 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
123 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 124 | |
b5c80475 FF |
125 | SKB_CB_ATHBUF(skb) = bf; |
126 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
07236bf3 | 127 | __skb_queue_tail(&rx_edma->rx_fifo, skb); |
f078f209 | 128 | |
b5c80475 FF |
129 | return true; |
130 | } | |
131 | ||
132 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
7a897203 | 133 | enum ath9k_rx_qtype qtype) |
b5c80475 | 134 | { |
b5c80475 | 135 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6a01f0c0 | 136 | struct ath_buf *bf, *tbf; |
b5c80475 | 137 | |
b5c80475 | 138 | if (list_empty(&sc->rx.rxbuf)) { |
d2182b69 | 139 | ath_dbg(common, QUEUE, "No free rx buf available\n"); |
b5c80475 | 140 | return; |
797fe5cb | 141 | } |
f078f209 | 142 | |
6a01f0c0 | 143 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) |
b5c80475 FF |
144 | if (!ath_rx_edma_buf_link(sc, qtype)) |
145 | break; | |
146 | ||
b5c80475 FF |
147 | } |
148 | ||
149 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
150 | enum ath9k_rx_qtype qtype) | |
151 | { | |
152 | struct ath_buf *bf; | |
153 | struct ath_rx_edma *rx_edma; | |
154 | struct sk_buff *skb; | |
155 | ||
156 | rx_edma = &sc->rx.rx_edma[qtype]; | |
157 | ||
07236bf3 | 158 | while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) { |
b5c80475 FF |
159 | bf = SKB_CB_ATHBUF(skb); |
160 | BUG_ON(!bf); | |
161 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
162 | } | |
163 | } | |
164 | ||
165 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
166 | { | |
ba542385 MSS |
167 | struct ath_hw *ah = sc->sc_ah; |
168 | struct ath_common *common = ath9k_hw_common(ah); | |
b5c80475 FF |
169 | struct ath_buf *bf; |
170 | ||
171 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
172 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
173 | ||
797fe5cb | 174 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
ba542385 MSS |
175 | if (bf->bf_mpdu) { |
176 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
177 | common->rx_bufsize, | |
178 | DMA_BIDIRECTIONAL); | |
b5c80475 | 179 | dev_kfree_skb_any(bf->bf_mpdu); |
ba542385 MSS |
180 | bf->bf_buf_addr = 0; |
181 | bf->bf_mpdu = NULL; | |
182 | } | |
b5c80475 | 183 | } |
b5c80475 FF |
184 | } |
185 | ||
186 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
187 | { | |
188 | skb_queue_head_init(&rx_edma->rx_fifo); | |
b5c80475 FF |
189 | rx_edma->rx_fifo_hwsize = size; |
190 | } | |
191 | ||
192 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
193 | { | |
194 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
195 | struct ath_hw *ah = sc->sc_ah; | |
196 | struct sk_buff *skb; | |
197 | struct ath_buf *bf; | |
198 | int error = 0, i; | |
199 | u32 size; | |
200 | ||
b5c80475 FF |
201 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
202 | ah->caps.rx_status_len); | |
203 | ||
204 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
205 | ah->caps.rx_lp_qdepth); | |
206 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
207 | ah->caps.rx_hp_qdepth); | |
208 | ||
209 | size = sizeof(struct ath_buf) * nbufs; | |
b81950b1 | 210 | bf = devm_kzalloc(sc->dev, size, GFP_KERNEL); |
b5c80475 FF |
211 | if (!bf) |
212 | return -ENOMEM; | |
213 | ||
214 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
b5c80475 FF |
215 | |
216 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 217 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 218 | if (!skb) { |
797fe5cb | 219 | error = -ENOMEM; |
b5c80475 | 220 | goto rx_init_fail; |
f078f209 | 221 | } |
f078f209 | 222 | |
b5c80475 | 223 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 224 | bf->bf_mpdu = skb; |
b5c80475 | 225 | |
797fe5cb | 226 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 227 | common->rx_bufsize, |
b5c80475 | 228 | DMA_BIDIRECTIONAL); |
797fe5cb | 229 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
230 | bf->bf_buf_addr))) { |
231 | dev_kfree_skb_any(skb); | |
232 | bf->bf_mpdu = NULL; | |
6cf9e995 | 233 | bf->bf_buf_addr = 0; |
3800276a | 234 | ath_err(common, |
b5c80475 FF |
235 | "dma_mapping_error() on RX init\n"); |
236 | error = -ENOMEM; | |
237 | goto rx_init_fail; | |
238 | } | |
239 | ||
240 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
241 | } | |
242 | ||
243 | return 0; | |
244 | ||
245 | rx_init_fail: | |
246 | ath_rx_edma_cleanup(sc); | |
247 | return error; | |
248 | } | |
249 | ||
250 | static void ath_edma_start_recv(struct ath_softc *sc) | |
251 | { | |
b5c80475 | 252 | ath9k_hw_rxena(sc->sc_ah); |
7a897203 SM |
253 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP); |
254 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 | 255 | ath_opmode_init(sc); |
4cb54fa3 | 256 | ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
b5c80475 FF |
257 | } |
258 | ||
259 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
260 | { | |
b5c80475 FF |
261 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
262 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
263 | } |
264 | ||
265 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
266 | { | |
267 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
268 | struct sk_buff *skb; | |
269 | struct ath_buf *bf; | |
270 | int error = 0; | |
271 | ||
4bdd1e97 | 272 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 | 273 | |
0d95521e FF |
274 | common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + |
275 | sc->sc_ah->caps.rx_status_len; | |
276 | ||
e87f3d53 | 277 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
b5c80475 | 278 | return ath_rx_edma_init(sc, nbufs); |
b5c80475 | 279 | |
e87f3d53 SM |
280 | ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", |
281 | common->cachelsz, common->rx_bufsize); | |
b5c80475 | 282 | |
e87f3d53 SM |
283 | /* Initialize rx descriptors */ |
284 | ||
285 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
286 | "rx", nbufs, 1, 0); | |
287 | if (error != 0) { | |
288 | ath_err(common, | |
289 | "failed to allocate rx descriptors: %d\n", | |
290 | error); | |
291 | goto err; | |
292 | } | |
293 | ||
294 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
295 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
296 | GFP_KERNEL); | |
297 | if (skb == NULL) { | |
298 | error = -ENOMEM; | |
797fe5cb S |
299 | goto err; |
300 | } | |
b5c80475 | 301 | |
e87f3d53 SM |
302 | bf->bf_mpdu = skb; |
303 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
304 | common->rx_bufsize, | |
305 | DMA_FROM_DEVICE); | |
306 | if (unlikely(dma_mapping_error(sc->dev, | |
307 | bf->bf_buf_addr))) { | |
308 | dev_kfree_skb_any(skb); | |
309 | bf->bf_mpdu = NULL; | |
310 | bf->bf_buf_addr = 0; | |
311 | ath_err(common, | |
312 | "dma_mapping_error() on RX init\n"); | |
313 | error = -ENOMEM; | |
314 | goto err; | |
b5c80475 | 315 | } |
797fe5cb | 316 | } |
e87f3d53 | 317 | sc->rx.rxlink = NULL; |
797fe5cb | 318 | err: |
f078f209 LR |
319 | if (error) |
320 | ath_rx_cleanup(sc); | |
321 | ||
322 | return error; | |
323 | } | |
324 | ||
f078f209 LR |
325 | void ath_rx_cleanup(struct ath_softc *sc) |
326 | { | |
cc861f74 LR |
327 | struct ath_hw *ah = sc->sc_ah; |
328 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
329 | struct sk_buff *skb; |
330 | struct ath_buf *bf; | |
331 | ||
b5c80475 FF |
332 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
333 | ath_rx_edma_cleanup(sc); | |
334 | return; | |
e87f3d53 SM |
335 | } |
336 | ||
337 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
338 | skb = bf->bf_mpdu; | |
339 | if (skb) { | |
340 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
341 | common->rx_bufsize, | |
342 | DMA_FROM_DEVICE); | |
343 | dev_kfree_skb(skb); | |
344 | bf->bf_buf_addr = 0; | |
345 | bf->bf_mpdu = NULL; | |
051b9191 | 346 | } |
b5c80475 | 347 | } |
f078f209 LR |
348 | } |
349 | ||
350 | /* | |
351 | * Calculate the receive filter according to the | |
352 | * operating mode and state: | |
353 | * | |
354 | * o always accept unicast, broadcast, and multicast traffic | |
355 | * o maintain current state of phy error reception (the hal | |
356 | * may enable phy error frames for noise immunity work) | |
357 | * o probe request frames are accepted only when operating in | |
358 | * hostap, adhoc, or monitor modes | |
359 | * o enable promiscuous mode according to the interface state | |
360 | * o accept beacons: | |
361 | * - when operating in adhoc mode so the 802.11 layer creates | |
362 | * node table entries for peers, | |
363 | * - when operating in station mode for collecting rssi data when | |
364 | * the station is otherwise quiet, or | |
365 | * - when operating as a repeater so we see repeater-sta beacons | |
366 | * - when scanning | |
367 | */ | |
368 | ||
369 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
370 | { | |
f078f209 LR |
371 | u32 rfilt; |
372 | ||
ac06697c | 373 | rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST |
f078f209 LR |
374 | | ATH9K_RX_FILTER_MCAST; |
375 | ||
73e4937d ZK |
376 | /* if operating on a DFS channel, enable radar pulse detection */ |
377 | if (sc->hw->conf.radar_enabled) | |
378 | rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR; | |
379 | ||
9c1d8e4a | 380 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
381 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
382 | ||
217ba9da JM |
383 | /* |
384 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
385 | * mode interface or when in monitor mode. AP mode does not need this | |
386 | * since it receives all in-BSS frames anyway. | |
387 | */ | |
2e286947 | 388 | if (sc->sc_ah->is_monitoring) |
f078f209 | 389 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 390 | |
d42c6b71 S |
391 | if (sc->rx.rxfilter & FIF_CONTROL) |
392 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
393 | ||
dbaaa147 | 394 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 395 | (sc->nvifs <= 1) && |
dbaaa147 VT |
396 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
397 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
398 | else | |
f078f209 LR |
399 | rfilt |= ATH9K_RX_FILTER_BEACON; |
400 | ||
264bbec8 | 401 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
66afad01 | 402 | (sc->rx.rxfilter & FIF_PSPOLL)) |
dbaaa147 | 403 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 404 | |
7ea310be S |
405 | if (conf_is_ht(&sc->hw->conf)) |
406 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
407 | ||
7545daf4 | 408 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
a549459c TW |
409 | /* This is needed for older chips */ |
410 | if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160) | |
5eb6ba83 | 411 | rfilt |= ATH9K_RX_FILTER_PROM; |
b93bce2a JM |
412 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
413 | } | |
414 | ||
b3d7aa43 GJ |
415 | if (AR_SREV_9550(sc->sc_ah)) |
416 | rfilt |= ATH9K_RX_FILTER_4ADDRESS; | |
417 | ||
f078f209 | 418 | return rfilt; |
7dcfdcd9 | 419 | |
f078f209 LR |
420 | } |
421 | ||
f078f209 LR |
422 | int ath_startrecv(struct ath_softc *sc) |
423 | { | |
cbe61d8a | 424 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
425 | struct ath_buf *bf, *tbf; |
426 | ||
b5c80475 FF |
427 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
428 | ath_edma_start_recv(sc); | |
429 | return 0; | |
430 | } | |
431 | ||
b77f483f | 432 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
433 | goto start_recv; |
434 | ||
b77f483f S |
435 | sc->rx.rxlink = NULL; |
436 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
437 | ath_rx_buf_link(sc, bf); |
438 | } | |
439 | ||
440 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 441 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
442 | goto start_recv; |
443 | ||
b77f483f | 444 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 445 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 446 | ath9k_hw_rxena(ah); |
f078f209 LR |
447 | |
448 | start_recv: | |
be0418ad | 449 | ath_opmode_init(sc); |
4cb54fa3 | 450 | ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
be0418ad | 451 | |
f078f209 LR |
452 | return 0; |
453 | } | |
454 | ||
4b883f02 FF |
455 | static void ath_flushrecv(struct ath_softc *sc) |
456 | { | |
457 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
458 | ath_rx_tasklet(sc, 1, true); | |
459 | ath_rx_tasklet(sc, 1, false); | |
460 | } | |
461 | ||
f078f209 LR |
462 | bool ath_stoprecv(struct ath_softc *sc) |
463 | { | |
cbe61d8a | 464 | struct ath_hw *ah = sc->sc_ah; |
5882da02 | 465 | bool stopped, reset = false; |
f078f209 | 466 | |
d47844a0 | 467 | ath9k_hw_abortpcurecv(ah); |
be0418ad | 468 | ath9k_hw_setrxfilter(ah, 0); |
5882da02 | 469 | stopped = ath9k_hw_stopdmarecv(ah, &reset); |
b5c80475 | 470 | |
4b883f02 FF |
471 | ath_flushrecv(sc); |
472 | ||
b5c80475 FF |
473 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
474 | ath_edma_stop_recv(sc); | |
475 | else | |
476 | sc->rx.rxlink = NULL; | |
be0418ad | 477 | |
d584747b RM |
478 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
479 | unlikely(!stopped)) { | |
d7fd1b50 BG |
480 | ath_err(ath9k_hw_common(sc->sc_ah), |
481 | "Could not stop RX, we could be " | |
482 | "confusing the DMA engine when we start RX up\n"); | |
483 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
484 | } | |
2232d31b | 485 | return stopped && !reset; |
f078f209 LR |
486 | } |
487 | ||
cc65965c JM |
488 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
489 | { | |
490 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
491 | struct ieee80211_mgmt *mgmt; | |
492 | u8 *pos, *end, id, elen; | |
493 | struct ieee80211_tim_ie *tim; | |
494 | ||
495 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
496 | pos = mgmt->u.beacon.variable; | |
497 | end = skb->data + skb->len; | |
498 | ||
499 | while (pos + 2 < end) { | |
500 | id = *pos++; | |
501 | elen = *pos++; | |
502 | if (pos + elen > end) | |
503 | break; | |
504 | ||
505 | if (id == WLAN_EID_TIM) { | |
506 | if (elen < sizeof(*tim)) | |
507 | break; | |
508 | tim = (struct ieee80211_tim_ie *) pos; | |
509 | if (tim->dtim_count != 0) | |
510 | break; | |
511 | return tim->bitmap_ctrl & 0x01; | |
512 | } | |
513 | ||
514 | pos += elen; | |
515 | } | |
516 | ||
517 | return false; | |
518 | } | |
519 | ||
cc65965c JM |
520 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
521 | { | |
1510718d | 522 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
523 | |
524 | if (skb->len < 24 + 8 + 2 + 2) | |
525 | return; | |
526 | ||
1b04b930 | 527 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 528 | |
1b04b930 S |
529 | if (sc->ps_flags & PS_BEACON_SYNC) { |
530 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
d2182b69 | 531 | ath_dbg(common, PS, |
1a6404a1 | 532 | "Reconfigure beacon timers based on synchronized timestamp\n"); |
ef4ad633 | 533 | ath9k_set_beacon(sc); |
ccdfeab6 JM |
534 | } |
535 | ||
cc65965c JM |
536 | if (ath_beacon_dtim_pending_cab(skb)) { |
537 | /* | |
538 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
539 | * frames. If the last broadcast/multicast frame is not |
540 | * received properly, the next beacon frame will work as | |
541 | * a backup trigger for returning into NETWORK SLEEP state, | |
542 | * so we are waiting for it as well. | |
cc65965c | 543 | */ |
d2182b69 | 544 | ath_dbg(common, PS, |
226afe68 | 545 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); |
1b04b930 | 546 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
547 | return; |
548 | } | |
549 | ||
1b04b930 | 550 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
551 | /* |
552 | * This can happen if a broadcast frame is dropped or the AP | |
553 | * fails to send a frame indicating that all CAB frames have | |
554 | * been delivered. | |
555 | */ | |
1b04b930 | 556 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
d2182b69 | 557 | ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); |
cc65965c | 558 | } |
cc65965c JM |
559 | } |
560 | ||
f73c604c | 561 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) |
cc65965c JM |
562 | { |
563 | struct ieee80211_hdr *hdr; | |
c46917bb | 564 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
565 | |
566 | hdr = (struct ieee80211_hdr *)skb->data; | |
567 | ||
568 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 | 569 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
07c15a3f | 570 | && mybeacon) { |
cc65965c | 571 | ath_rx_ps_beacon(sc, skb); |
07c15a3f SM |
572 | } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
573 | (ieee80211_is_data(hdr->frame_control) || | |
574 | ieee80211_is_action(hdr->frame_control)) && | |
575 | is_multicast_ether_addr(hdr->addr1) && | |
576 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
577 | /* |
578 | * No more broadcast/multicast frames to be received at this | |
579 | * point. | |
580 | */ | |
3fac6dfd | 581 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
d2182b69 | 582 | ath_dbg(common, PS, |
226afe68 | 583 | "All PS CAB frames received, back to sleep\n"); |
1b04b930 | 584 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
585 | !is_multicast_ether_addr(hdr->addr1) && |
586 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 587 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
d2182b69 | 588 | ath_dbg(common, PS, |
226afe68 | 589 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", |
1b04b930 S |
590 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
591 | PS_WAIT_FOR_CAB | | |
592 | PS_WAIT_FOR_PSPOLL_DATA | | |
593 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
594 | } |
595 | } | |
596 | ||
b5c80475 | 597 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
3a2923e8 FF |
598 | enum ath9k_rx_qtype qtype, |
599 | struct ath_rx_status *rs, | |
600 | struct ath_buf **dest) | |
f078f209 | 601 | { |
b5c80475 FF |
602 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
603 | struct ath_hw *ah = sc->sc_ah; | |
604 | struct ath_common *common = ath9k_hw_common(ah); | |
605 | struct sk_buff *skb; | |
606 | struct ath_buf *bf; | |
607 | int ret; | |
608 | ||
609 | skb = skb_peek(&rx_edma->rx_fifo); | |
610 | if (!skb) | |
611 | return false; | |
612 | ||
613 | bf = SKB_CB_ATHBUF(skb); | |
614 | BUG_ON(!bf); | |
615 | ||
ce9426d1 | 616 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
617 | common->rx_bufsize, DMA_FROM_DEVICE); |
618 | ||
3a2923e8 | 619 | ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data); |
ce9426d1 ML |
620 | if (ret == -EINPROGRESS) { |
621 | /*let device gain the buffer again*/ | |
622 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
623 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 624 | return false; |
ce9426d1 | 625 | } |
b5c80475 FF |
626 | |
627 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
628 | if (ret == -EINVAL) { | |
629 | /* corrupt descriptor, skip this one and the following one */ | |
630 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
631 | ath_rx_edma_buf_link(sc, qtype); | |
b5c80475 | 632 | |
3a2923e8 FF |
633 | skb = skb_peek(&rx_edma->rx_fifo); |
634 | if (skb) { | |
635 | bf = SKB_CB_ATHBUF(skb); | |
636 | BUG_ON(!bf); | |
637 | ||
638 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
639 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
640 | ath_rx_edma_buf_link(sc, qtype); | |
3a2923e8 | 641 | } |
6bb51c70 TH |
642 | |
643 | bf = NULL; | |
b5c80475 | 644 | } |
b5c80475 | 645 | |
3a2923e8 | 646 | *dest = bf; |
b5c80475 FF |
647 | return true; |
648 | } | |
f078f209 | 649 | |
b5c80475 FF |
650 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
651 | struct ath_rx_status *rs, | |
652 | enum ath9k_rx_qtype qtype) | |
653 | { | |
3a2923e8 | 654 | struct ath_buf *bf = NULL; |
b5c80475 | 655 | |
3a2923e8 FF |
656 | while (ath_edma_get_buffers(sc, qtype, rs, &bf)) { |
657 | if (!bf) | |
658 | continue; | |
b5c80475 | 659 | |
3a2923e8 FF |
660 | return bf; |
661 | } | |
662 | return NULL; | |
b5c80475 FF |
663 | } |
664 | ||
665 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
666 | struct ath_rx_status *rs) | |
667 | { | |
668 | struct ath_hw *ah = sc->sc_ah; | |
669 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 670 | struct ath_desc *ds; |
b5c80475 FF |
671 | struct ath_buf *bf; |
672 | int ret; | |
673 | ||
674 | if (list_empty(&sc->rx.rxbuf)) { | |
675 | sc->rx.rxlink = NULL; | |
676 | return NULL; | |
677 | } | |
678 | ||
679 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
680 | ds = bf->bf_desc; | |
681 | ||
682 | /* | |
683 | * Must provide the virtual address of the current | |
684 | * descriptor, the physical address, and the virtual | |
685 | * address of the next descriptor in the h/w chain. | |
686 | * This allows the HAL to look ahead to see if the | |
687 | * hardware is done with a descriptor by checking the | |
688 | * done bit in the following descriptor and the address | |
689 | * of the current descriptor the DMA engine is working | |
690 | * on. All this is necessary because of our use of | |
691 | * a self-linked list to avoid rx overruns. | |
692 | */ | |
3de21116 | 693 | ret = ath9k_hw_rxprocdesc(ah, ds, rs); |
b5c80475 FF |
694 | if (ret == -EINPROGRESS) { |
695 | struct ath_rx_status trs; | |
696 | struct ath_buf *tbf; | |
697 | struct ath_desc *tds; | |
698 | ||
699 | memset(&trs, 0, sizeof(trs)); | |
700 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
701 | sc->rx.rxlink = NULL; | |
702 | return NULL; | |
703 | } | |
704 | ||
705 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
706 | ||
707 | /* | |
708 | * On some hardware the descriptor status words could | |
709 | * get corrupted, including the done bit. Because of | |
710 | * this, check if the next descriptor's done bit is | |
711 | * set or not. | |
712 | * | |
713 | * If the next descriptor's done bit is set, the current | |
714 | * descriptor has been corrupted. Force s/w to discard | |
715 | * this descriptor and continue... | |
716 | */ | |
717 | ||
718 | tds = tbf->bf_desc; | |
3de21116 | 719 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs); |
b5c80475 FF |
720 | if (ret == -EINPROGRESS) |
721 | return NULL; | |
723e7113 FF |
722 | |
723 | /* | |
724 | * mark descriptor as zero-length and set the 'more' | |
725 | * flag to ensure that both buffers get discarded | |
726 | */ | |
727 | rs->rs_datalen = 0; | |
728 | rs->rs_more = true; | |
b5c80475 FF |
729 | } |
730 | ||
a3dc48e8 | 731 | list_del(&bf->list); |
b5c80475 FF |
732 | if (!bf->bf_mpdu) |
733 | return bf; | |
734 | ||
735 | /* | |
736 | * Synchronize the DMA transfer with CPU before | |
737 | * 1. accessing the frame | |
738 | * 2. requeueing the same buffer to h/w | |
739 | */ | |
ce9426d1 | 740 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
741 | common->rx_bufsize, |
742 | DMA_FROM_DEVICE); | |
743 | ||
744 | return bf; | |
745 | } | |
746 | ||
d435700f S |
747 | /* Assumes you've already done the endian to CPU conversion */ |
748 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 749 | struct ieee80211_hdr *hdr, |
d435700f S |
750 | struct ieee80211_rx_status *rxs, |
751 | struct ath_rx_status *rx_stats, | |
752 | bool *decrypt_error) | |
753 | { | |
ec205999 | 754 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
66760eac | 755 | bool is_mc, is_valid_tkip, strip_mic, mic_error; |
d435700f | 756 | struct ath_hw *ah = common->ah; |
d435700f | 757 | __le16 fc; |
b7b1b512 | 758 | u8 rx_status_len = ah->caps.rx_status_len; |
d435700f | 759 | |
d435700f S |
760 | fc = hdr->frame_control; |
761 | ||
66760eac FF |
762 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
763 | is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && | |
764 | test_bit(rx_stats->rs_keyix, common->tkip_keymap); | |
152e585d | 765 | strip_mic = is_valid_tkip && ieee80211_is_data(fc) && |
2a5783b8 | 766 | ieee80211_has_protected(fc) && |
152e585d | 767 | !(rx_stats->rs_status & |
846d9363 FF |
768 | (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC | |
769 | ATH9K_RXERR_KEYMISS)); | |
66760eac | 770 | |
f88373fa FF |
771 | /* |
772 | * Key miss events are only relevant for pairwise keys where the | |
773 | * descriptor does contain a valid key index. This has been observed | |
774 | * mostly with CCMP encryption. | |
775 | */ | |
bed3d9c0 FF |
776 | if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID || |
777 | !test_bit(rx_stats->rs_keyix, common->ccmp_keymap)) | |
f88373fa FF |
778 | rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS; |
779 | ||
15072189 BG |
780 | if (!rx_stats->rs_datalen) { |
781 | RX_STAT_INC(rx_len_err); | |
d435700f | 782 | return false; |
15072189 BG |
783 | } |
784 | ||
d435700f S |
785 | /* |
786 | * rs_status follows rs_datalen so if rs_datalen is too large | |
787 | * we can take a hint that hardware corrupted it, so ignore | |
788 | * those frames. | |
789 | */ | |
15072189 BG |
790 | if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) { |
791 | RX_STAT_INC(rx_len_err); | |
d435700f | 792 | return false; |
15072189 | 793 | } |
d435700f | 794 | |
0d95521e | 795 | /* Only use error bits from the last fragment */ |
d435700f | 796 | if (rx_stats->rs_more) |
0d95521e | 797 | return true; |
d435700f | 798 | |
66760eac FF |
799 | mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) && |
800 | !ieee80211_has_morefrags(fc) && | |
801 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
802 | (rx_stats->rs_status & ATH9K_RXERR_MIC); | |
803 | ||
d435700f S |
804 | /* |
805 | * The rx_stats->rs_status will not be set until the end of the | |
806 | * chained descriptors so it can be ignored if rs_more is set. The | |
807 | * rs_more will be false at the last element of the chained | |
808 | * descriptors. | |
809 | */ | |
810 | if (rx_stats->rs_status != 0) { | |
846d9363 FF |
811 | u8 status_mask; |
812 | ||
66760eac | 813 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) { |
d435700f | 814 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; |
66760eac FF |
815 | mic_error = false; |
816 | } | |
d435700f S |
817 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) |
818 | return false; | |
819 | ||
846d9363 FF |
820 | if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) || |
821 | (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) { | |
d435700f | 822 | *decrypt_error = true; |
66760eac | 823 | mic_error = false; |
d435700f | 824 | } |
66760eac | 825 | |
d435700f S |
826 | /* |
827 | * Reject error frames with the exception of | |
828 | * decryption and MIC failures. For monitor mode, | |
829 | * we also ignore the CRC error. | |
830 | */ | |
846d9363 FF |
831 | status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
832 | ATH9K_RXERR_KEYMISS; | |
833 | ||
ec205999 | 834 | if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL)) |
846d9363 FF |
835 | status_mask |= ATH9K_RXERR_CRC; |
836 | ||
837 | if (rx_stats->rs_status & ~status_mask) | |
838 | return false; | |
d435700f | 839 | } |
66760eac FF |
840 | |
841 | /* | |
842 | * For unicast frames the MIC error bit can have false positives, | |
843 | * so all MIC error reports need to be validated in software. | |
844 | * False negatives are not common, so skip software verification | |
845 | * if the hardware considers the MIC valid. | |
846 | */ | |
847 | if (strip_mic) | |
848 | rxs->flag |= RX_FLAG_MMIC_STRIPPED; | |
849 | else if (is_mc && mic_error) | |
850 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
851 | ||
d435700f S |
852 | return true; |
853 | } | |
854 | ||
855 | static int ath9k_process_rate(struct ath_common *common, | |
856 | struct ieee80211_hw *hw, | |
857 | struct ath_rx_status *rx_stats, | |
9f167f64 | 858 | struct ieee80211_rx_status *rxs) |
d435700f S |
859 | { |
860 | struct ieee80211_supported_band *sband; | |
861 | enum ieee80211_band band; | |
862 | unsigned int i = 0; | |
990e08a0 | 863 | struct ath_softc __maybe_unused *sc = common->priv; |
d435700f | 864 | |
675a0b04 | 865 | band = hw->conf.chandef.chan->band; |
d435700f S |
866 | sband = hw->wiphy->bands[band]; |
867 | ||
868 | if (rx_stats->rs_rate & 0x80) { | |
869 | /* HT rate */ | |
870 | rxs->flag |= RX_FLAG_HT; | |
ab276103 | 871 | rxs->flag |= rx_stats->flag; |
d435700f S |
872 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; |
873 | return 0; | |
874 | } | |
875 | ||
876 | for (i = 0; i < sband->n_bitrates; i++) { | |
877 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
878 | rxs->rate_idx = i; | |
879 | return 0; | |
880 | } | |
881 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
882 | rxs->flag |= RX_FLAG_SHORTPRE; | |
883 | rxs->rate_idx = i; | |
884 | return 0; | |
885 | } | |
886 | } | |
887 | ||
888 | /* | |
889 | * No valid hardware bitrate found -- we should not get here | |
890 | * because hardware has already validated this frame as OK. | |
891 | */ | |
d2182b69 | 892 | ath_dbg(common, ANY, |
226afe68 JP |
893 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", |
894 | rx_stats->rs_rate); | |
15072189 | 895 | RX_STAT_INC(rx_rate_err); |
d435700f S |
896 | return -EINVAL; |
897 | } | |
898 | ||
899 | static void ath9k_process_rssi(struct ath_common *common, | |
900 | struct ieee80211_hw *hw, | |
9f167f64 | 901 | struct ieee80211_hdr *hdr, |
d435700f S |
902 | struct ath_rx_status *rx_stats) |
903 | { | |
9ac58615 | 904 | struct ath_softc *sc = hw->priv; |
d435700f | 905 | struct ath_hw *ah = common->ah; |
9fa23e17 | 906 | int last_rssi; |
2ef16755 | 907 | int rssi = rx_stats->rs_rssi; |
d435700f | 908 | |
cf3af748 RM |
909 | if (!rx_stats->is_mybeacon || |
910 | ((ah->opmode != NL80211_IFTYPE_STATION) && | |
911 | (ah->opmode != NL80211_IFTYPE_ADHOC))) | |
9fa23e17 FF |
912 | return; |
913 | ||
9fa23e17 | 914 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
9ac58615 | 915 | ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi); |
d435700f | 916 | |
9ac58615 | 917 | last_rssi = sc->last_rssi; |
d435700f | 918 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
2ef16755 FF |
919 | rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER); |
920 | if (rssi < 0) | |
921 | rssi = 0; | |
d435700f S |
922 | |
923 | /* Update Beacon RSSI, this is used by ANI. */ | |
2ef16755 | 924 | ah->stats.avgbrssi = rssi; |
d435700f S |
925 | } |
926 | ||
927 | /* | |
928 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
929 | * up the frame up to let mac80211 handle the actual error case, be it no | |
930 | * decryption key or real decryption error. This let us keep statistics there. | |
931 | */ | |
723e7113 | 932 | static int ath9k_rx_skb_preprocess(struct ath_softc *sc, |
9f167f64 | 933 | struct ieee80211_hdr *hdr, |
d435700f S |
934 | struct ath_rx_status *rx_stats, |
935 | struct ieee80211_rx_status *rx_status, | |
936 | bool *decrypt_error) | |
937 | { | |
723e7113 FF |
938 | struct ieee80211_hw *hw = sc->hw; |
939 | struct ath_hw *ah = sc->sc_ah; | |
940 | struct ath_common *common = ath9k_hw_common(ah); | |
941 | bool discard_current = sc->rx.discard_next; | |
942 | ||
943 | sc->rx.discard_next = rx_stats->rs_more; | |
944 | if (discard_current) | |
945 | return -EINVAL; | |
f749b946 | 946 | |
d435700f S |
947 | /* |
948 | * everything but the rate is checked here, the rate check is done | |
949 | * separately to avoid doing two lookups for a rate for each frame. | |
950 | */ | |
9f167f64 | 951 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
952 | return -EINVAL; |
953 | ||
0d95521e FF |
954 | /* Only use status info from the last fragment */ |
955 | if (rx_stats->rs_more) | |
956 | return 0; | |
957 | ||
9f167f64 | 958 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
d435700f | 959 | |
9f167f64 | 960 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
961 | return -EINVAL; |
962 | ||
675a0b04 KB |
963 | rx_status->band = hw->conf.chandef.chan->band; |
964 | rx_status->freq = hw->conf.chandef.chan->center_freq; | |
f749b946 | 965 | rx_status->signal = ah->noise + rx_stats->rs_rssi; |
d435700f | 966 | rx_status->antenna = rx_stats->rs_antenna; |
96d21371 | 967 | rx_status->flag |= RX_FLAG_MACTIME_END; |
2ef16755 FF |
968 | if (rx_stats->rs_moreaggr) |
969 | rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; | |
d435700f | 970 | |
723e7113 | 971 | sc->rx.discard_next = false; |
d435700f S |
972 | return 0; |
973 | } | |
974 | ||
975 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
976 | struct sk_buff *skb, | |
977 | struct ath_rx_status *rx_stats, | |
978 | struct ieee80211_rx_status *rxs, | |
979 | bool decrypt_error) | |
980 | { | |
981 | struct ath_hw *ah = common->ah; | |
982 | struct ieee80211_hdr *hdr; | |
983 | int hdrlen, padpos, padsize; | |
984 | u8 keyix; | |
985 | __le16 fc; | |
986 | ||
987 | /* see if any padding is done by the hw and remove it */ | |
988 | hdr = (struct ieee80211_hdr *) skb->data; | |
989 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
990 | fc = hdr->frame_control; | |
c60c9929 | 991 | padpos = ieee80211_hdrlen(fc); |
d435700f S |
992 | |
993 | /* The MAC header is padded to have 32-bit boundary if the | |
994 | * packet payload is non-zero. The general calculation for | |
995 | * padsize would take into account odd header lengths: | |
996 | * padsize = (4 - padpos % 4) % 4; However, since only | |
997 | * even-length headers are used, padding can only be 0 or 2 | |
998 | * bytes and we can optimize this a bit. In addition, we must | |
999 | * not try to remove padding from short control frames that do | |
1000 | * not have payload. */ | |
1001 | padsize = padpos & 3; | |
1002 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1003 | memmove(skb->data + padsize, skb->data, padpos); | |
1004 | skb_pull(skb, padsize); | |
1005 | } | |
1006 | ||
1007 | keyix = rx_stats->rs_keyix; | |
1008 | ||
1009 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1010 | ieee80211_has_protected(fc)) { | |
1011 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1012 | } else if (ieee80211_has_protected(fc) | |
1013 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1014 | keyix = skb->data[hdrlen + 3] >> 6; | |
1015 | ||
1016 | if (test_bit(keyix, common->keymap)) | |
1017 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1018 | } | |
1019 | if (ah->sw_mgmt_crypto && | |
1020 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1021 | ieee80211_is_mgmt(fc)) | |
1022 | /* Use software decrypt for management frames. */ | |
1023 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1024 | } | |
b5c80475 | 1025 | |
ab2e2fc8 | 1026 | #ifdef CONFIG_ATH9K_DEBUGFS |
e93d083f SW |
1027 | static s8 fix_rssi_inv_only(u8 rssi_val) |
1028 | { | |
1029 | if (rssi_val == 128) | |
1030 | rssi_val = 0; | |
1031 | return (s8) rssi_val; | |
1032 | } | |
ab2e2fc8 | 1033 | #endif |
e93d083f | 1034 | |
9b99e665 SW |
1035 | /* returns 1 if this was a spectral frame, even if not handled. */ |
1036 | static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr, | |
1037 | struct ath_rx_status *rs, u64 tsf) | |
e93d083f | 1038 | { |
bd2ffe14 | 1039 | #ifdef CONFIG_ATH9K_DEBUGFS |
e93d083f SW |
1040 | struct ath_hw *ah = sc->sc_ah; |
1041 | u8 bins[SPECTRAL_HT20_NUM_BINS]; | |
1042 | u8 *vdata = (u8 *)hdr; | |
1043 | struct fft_sample_ht20 fft_sample; | |
1044 | struct ath_radar_info *radar_info; | |
1045 | struct ath_ht20_mag_info *mag_info; | |
1046 | int len = rs->rs_datalen; | |
4ab0b0aa | 1047 | int dc_pos; |
12824374 | 1048 | u16 length, max_magnitude; |
e93d083f SW |
1049 | |
1050 | /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer | |
1051 | * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT | |
1052 | * yet, but this is supposed to be possible as well. | |
1053 | */ | |
1054 | if (rs->rs_phyerr != ATH9K_PHYERR_RADAR && | |
1055 | rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT && | |
1056 | rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL) | |
9b99e665 SW |
1057 | return 0; |
1058 | ||
1059 | /* check if spectral scan bit is set. This does not have to be checked | |
1060 | * if received through a SPECTRAL phy error, but shouldn't hurt. | |
1061 | */ | |
1062 | radar_info = ((struct ath_radar_info *)&vdata[len]) - 1; | |
1063 | if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK)) | |
1064 | return 0; | |
e93d083f SW |
1065 | |
1066 | /* Variation in the data length is possible and will be fixed later. | |
1067 | * Note that we only support HT20 for now. | |
1068 | * | |
1069 | * TODO: add HT20_40 support as well. | |
1070 | */ | |
1071 | if ((len > SPECTRAL_HT20_TOTAL_DATA_LEN + 2) || | |
1072 | (len < SPECTRAL_HT20_TOTAL_DATA_LEN - 1)) | |
9b99e665 | 1073 | return 1; |
e93d083f SW |
1074 | |
1075 | fft_sample.tlv.type = ATH_FFT_SAMPLE_HT20; | |
12824374 SE |
1076 | length = sizeof(fft_sample) - sizeof(fft_sample.tlv); |
1077 | fft_sample.tlv.length = __cpu_to_be16(length); | |
e93d083f | 1078 | |
4ab0b0aa | 1079 | fft_sample.freq = __cpu_to_be16(ah->curchan->chan->center_freq); |
e93d083f SW |
1080 | fft_sample.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0); |
1081 | fft_sample.noise = ah->noise; | |
1082 | ||
1083 | switch (len - SPECTRAL_HT20_TOTAL_DATA_LEN) { | |
1084 | case 0: | |
1085 | /* length correct, nothing to do. */ | |
1086 | memcpy(bins, vdata, SPECTRAL_HT20_NUM_BINS); | |
1087 | break; | |
1088 | case -1: | |
1089 | /* first byte missing, duplicate it. */ | |
1090 | memcpy(&bins[1], vdata, SPECTRAL_HT20_NUM_BINS - 1); | |
1091 | bins[0] = vdata[0]; | |
1092 | break; | |
1093 | case 2: | |
1094 | /* MAC added 2 extra bytes at bin 30 and 32, remove them. */ | |
1095 | memcpy(bins, vdata, 30); | |
1096 | bins[30] = vdata[31]; | |
1097 | memcpy(&bins[31], &vdata[33], SPECTRAL_HT20_NUM_BINS - 31); | |
1098 | break; | |
1099 | case 1: | |
1100 | /* MAC added 2 extra bytes AND first byte is missing. */ | |
1101 | bins[0] = vdata[0]; | |
1102 | memcpy(&bins[0], vdata, 30); | |
1103 | bins[31] = vdata[31]; | |
1104 | memcpy(&bins[32], &vdata[33], SPECTRAL_HT20_NUM_BINS - 32); | |
1105 | break; | |
1106 | default: | |
9b99e665 | 1107 | return 1; |
e93d083f SW |
1108 | } |
1109 | ||
1110 | /* DC value (value in the middle) is the blind spot of the spectral | |
1111 | * sample and invalid, interpolate it. | |
1112 | */ | |
1113 | dc_pos = SPECTRAL_HT20_NUM_BINS / 2; | |
1114 | bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2; | |
1115 | ||
1116 | /* mag data is at the end of the frame, in front of radar_info */ | |
1117 | mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1; | |
1118 | ||
4ab0b0aa SE |
1119 | /* copy raw bins without scaling them */ |
1120 | memcpy(fft_sample.data, bins, SPECTRAL_HT20_NUM_BINS); | |
1121 | fft_sample.max_exp = mag_info->max_exp & 0xf; | |
e93d083f | 1122 | |
12824374 SE |
1123 | max_magnitude = spectral_max_magnitude(mag_info->all_bins); |
1124 | fft_sample.max_magnitude = __cpu_to_be16(max_magnitude); | |
e93d083f SW |
1125 | fft_sample.max_index = spectral_max_index(mag_info->all_bins); |
1126 | fft_sample.bitmap_weight = spectral_bitmap_weight(mag_info->all_bins); | |
4ab0b0aa | 1127 | fft_sample.tsf = __cpu_to_be64(tsf); |
e93d083f SW |
1128 | |
1129 | ath_debug_send_fft_sample(sc, &fft_sample.tlv); | |
9b99e665 SW |
1130 | return 1; |
1131 | #else | |
1132 | return 0; | |
e93d083f SW |
1133 | #endif |
1134 | } | |
1135 | ||
21fbbca3 CL |
1136 | static void ath9k_apply_ampdu_details(struct ath_softc *sc, |
1137 | struct ath_rx_status *rs, struct ieee80211_rx_status *rxs) | |
1138 | { | |
1139 | if (rs->rs_isaggr) { | |
1140 | rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN; | |
1141 | ||
1142 | rxs->ampdu_reference = sc->rx.ampdu_ref; | |
1143 | ||
1144 | if (!rs->rs_moreaggr) { | |
1145 | rxs->flag |= RX_FLAG_AMPDU_IS_LAST; | |
1146 | sc->rx.ampdu_ref++; | |
1147 | } | |
1148 | ||
1149 | if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE) | |
1150 | rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR; | |
1151 | } | |
1152 | } | |
1153 | ||
b5c80475 FF |
1154 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) |
1155 | { | |
1156 | struct ath_buf *bf; | |
0d95521e | 1157 | struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; |
5ca42627 | 1158 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1159 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 1160 | struct ath_common *common = ath9k_hw_common(ah); |
7545daf4 | 1161 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1162 | struct ieee80211_hdr *hdr; |
c9b14170 | 1163 | int retval; |
29bffa96 | 1164 | struct ath_rx_status rs; |
b5c80475 FF |
1165 | enum ath9k_rx_qtype qtype; |
1166 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1167 | int dma_type; | |
5c6dd921 | 1168 | u8 rx_status_len = ah->caps.rx_status_len; |
a6d2055b FF |
1169 | u64 tsf = 0; |
1170 | u32 tsf_lower = 0; | |
8ab2cd09 | 1171 | unsigned long flags; |
2e1cd495 | 1172 | dma_addr_t new_buf_addr; |
be0418ad | 1173 | |
b5c80475 | 1174 | if (edma) |
b5c80475 | 1175 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1176 | else |
1177 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1178 | |
1179 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
f078f209 | 1180 | |
a6d2055b FF |
1181 | tsf = ath9k_hw_gettsf64(ah); |
1182 | tsf_lower = tsf & 0xffffffff; | |
1183 | ||
f078f209 | 1184 | do { |
e1352fde | 1185 | bool decrypt_error = false; |
f078f209 | 1186 | |
29bffa96 | 1187 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1188 | if (edma) |
1189 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1190 | else | |
1191 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1192 | |
b5c80475 FF |
1193 | if (!bf) |
1194 | break; | |
f078f209 | 1195 | |
f078f209 | 1196 | skb = bf->bf_mpdu; |
be0418ad | 1197 | if (!skb) |
f078f209 | 1198 | continue; |
f078f209 | 1199 | |
0d95521e FF |
1200 | /* |
1201 | * Take frame header from the first fragment and RX status from | |
1202 | * the last one. | |
1203 | */ | |
1204 | if (sc->rx.frag) | |
1205 | hdr_skb = sc->rx.frag; | |
1206 | else | |
1207 | hdr_skb = skb; | |
1208 | ||
1209 | hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len); | |
1210 | rxs = IEEE80211_SKB_RXCB(hdr_skb); | |
15072189 BG |
1211 | if (ieee80211_is_beacon(hdr->frame_control)) { |
1212 | RX_STAT_INC(rx_beacons); | |
1213 | if (!is_zero_ether_addr(common->curbssid) && | |
2e42e474 | 1214 | ether_addr_equal(hdr->addr3, common->curbssid)) |
15072189 BG |
1215 | rs.is_mybeacon = true; |
1216 | else | |
1217 | rs.is_mybeacon = false; | |
1218 | } | |
cf3af748 RM |
1219 | else |
1220 | rs.is_mybeacon = false; | |
5ca42627 | 1221 | |
be41b052 MSS |
1222 | if (ieee80211_is_data_present(hdr->frame_control) && |
1223 | !ieee80211_is_qos_nullfunc(hdr->frame_control)) | |
1224 | sc->rx.num_pkts++; | |
1225 | ||
29bffa96 | 1226 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1227 | |
ffb1c56a AN |
1228 | memset(rxs, 0, sizeof(struct ieee80211_rx_status)); |
1229 | ||
a6d2055b FF |
1230 | rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; |
1231 | if (rs.rs_tstamp > tsf_lower && | |
1232 | unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) | |
1233 | rxs->mactime -= 0x100000000ULL; | |
1234 | ||
1235 | if (rs.rs_tstamp < tsf_lower && | |
1236 | unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) | |
1237 | rxs->mactime += 0x100000000ULL; | |
1238 | ||
73e4937d ZK |
1239 | if (rs.rs_phyerr == ATH9K_PHYERR_RADAR) |
1240 | ath9k_dfs_process_phyerr(sc, hdr, &rs, rxs->mactime); | |
1241 | ||
9b99e665 SW |
1242 | if (rs.rs_status & ATH9K_RXERR_PHY) { |
1243 | if (ath_process_fft(sc, hdr, &rs, rxs->mactime)) { | |
1244 | RX_STAT_INC(rx_spectral); | |
1245 | goto requeue_drop_frag; | |
1246 | } | |
1247 | } | |
e93d083f | 1248 | |
723e7113 FF |
1249 | retval = ath9k_rx_skb_preprocess(sc, hdr, &rs, rxs, |
1250 | &decrypt_error); | |
83c76570 ZK |
1251 | if (retval) |
1252 | goto requeue_drop_frag; | |
1253 | ||
01e18918 RM |
1254 | if (rs.is_mybeacon) { |
1255 | sc->hw_busy_count = 0; | |
1256 | ath_start_rx_poll(sc, 3); | |
1257 | } | |
cb71d9ba LR |
1258 | /* Ensure we always have an skb to requeue once we are done |
1259 | * processing the current buffer's skb */ | |
cc861f74 | 1260 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1261 | |
1262 | /* If there is no memory we ignore the current RX'd frame, | |
1263 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1264 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba | 1265 | * processing. */ |
15072189 BG |
1266 | if (!requeue_skb) { |
1267 | RX_STAT_INC(rx_oom_err); | |
0d95521e | 1268 | goto requeue_drop_frag; |
15072189 | 1269 | } |
f078f209 | 1270 | |
2e1cd495 FF |
1271 | /* We will now give hardware our shiny new allocated skb */ |
1272 | new_buf_addr = dma_map_single(sc->dev, requeue_skb->data, | |
1273 | common->rx_bufsize, dma_type); | |
1274 | if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) { | |
1275 | dev_kfree_skb_any(requeue_skb); | |
1276 | goto requeue_drop_frag; | |
1277 | } | |
1278 | ||
9bf9fca8 | 1279 | /* Unmap the frame */ |
7da3c55c | 1280 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
2e1cd495 | 1281 | common->rx_bufsize, dma_type); |
f078f209 | 1282 | |
176f0e84 SM |
1283 | bf->bf_mpdu = requeue_skb; |
1284 | bf->bf_buf_addr = new_buf_addr; | |
1285 | ||
b5c80475 FF |
1286 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1287 | if (ah->caps.rx_status_len) | |
1288 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1289 | |
0d95521e FF |
1290 | if (!rs.rs_more) |
1291 | ath9k_rx_skb_postprocess(common, hdr_skb, &rs, | |
1292 | rxs, decrypt_error); | |
be0418ad | 1293 | |
0d95521e | 1294 | if (rs.rs_more) { |
15072189 | 1295 | RX_STAT_INC(rx_frags); |
0d95521e FF |
1296 | /* |
1297 | * rs_more indicates chained descriptors which can be | |
1298 | * used to link buffers together for a sort of | |
1299 | * scatter-gather operation. | |
1300 | */ | |
1301 | if (sc->rx.frag) { | |
1302 | /* too many fragments - cannot handle frame */ | |
1303 | dev_kfree_skb_any(sc->rx.frag); | |
1304 | dev_kfree_skb_any(skb); | |
15072189 | 1305 | RX_STAT_INC(rx_too_many_frags_err); |
0d95521e FF |
1306 | skb = NULL; |
1307 | } | |
1308 | sc->rx.frag = skb; | |
1309 | goto requeue; | |
1310 | } | |
3747c3ee FF |
1311 | if (rs.rs_status & ATH9K_RXERR_CORRUPT_DESC) |
1312 | goto requeue_drop_frag; | |
0d95521e FF |
1313 | |
1314 | if (sc->rx.frag) { | |
1315 | int space = skb->len - skb_tailroom(hdr_skb); | |
1316 | ||
0d95521e FF |
1317 | if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { |
1318 | dev_kfree_skb(skb); | |
15072189 | 1319 | RX_STAT_INC(rx_oom_err); |
0d95521e FF |
1320 | goto requeue_drop_frag; |
1321 | } | |
1322 | ||
b5447ff9 ED |
1323 | sc->rx.frag = NULL; |
1324 | ||
0d95521e FF |
1325 | skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), |
1326 | skb->len); | |
1327 | dev_kfree_skb_any(skb); | |
1328 | skb = hdr_skb; | |
1329 | } | |
1330 | ||
eb840a80 MSS |
1331 | |
1332 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { | |
1333 | ||
1334 | /* | |
1335 | * change the default rx antenna if rx diversity | |
1336 | * chooses the other antenna 3 times in a row. | |
1337 | */ | |
1338 | if (sc->rx.defant != rs.rs_antenna) { | |
1339 | if (++sc->rx.rxotherant >= 3) | |
1340 | ath_setdefantenna(sc, rs.rs_antenna); | |
1341 | } else { | |
1342 | sc->rx.rxotherant = 0; | |
1343 | } | |
1344 | ||
f078f209 | 1345 | } |
3cbb5dd7 | 1346 | |
66760eac FF |
1347 | if (rxs->flag & RX_FLAG_MMIC_STRIPPED) |
1348 | skb_trim(skb, skb->len - 8); | |
1349 | ||
8ab2cd09 | 1350 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
aaef24b4 | 1351 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | |
f73c604c RM |
1352 | PS_WAIT_FOR_CAB | |
1353 | PS_WAIT_FOR_PSPOLL_DATA)) || | |
1354 | ath9k_check_auto_sleep(sc)) | |
1355 | ath_rx_ps(sc, skb, rs.is_mybeacon); | |
8ab2cd09 | 1356 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
cc65965c | 1357 | |
43c35284 | 1358 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3) |
102885a5 VT |
1359 | ath_ant_comb_scan(sc, &rs); |
1360 | ||
21fbbca3 CL |
1361 | ath9k_apply_ampdu_details(sc, &rs, rxs); |
1362 | ||
7545daf4 | 1363 | ieee80211_rx(hw, skb); |
cc65965c | 1364 | |
0d95521e FF |
1365 | requeue_drop_frag: |
1366 | if (sc->rx.frag) { | |
1367 | dev_kfree_skb_any(sc->rx.frag); | |
1368 | sc->rx.frag = NULL; | |
1369 | } | |
cb71d9ba | 1370 | requeue: |
a3dc48e8 FF |
1371 | list_add_tail(&bf->list, &sc->rx.rxbuf); |
1372 | if (flush) | |
1373 | continue; | |
1374 | ||
b5c80475 | 1375 | if (edma) { |
b5c80475 FF |
1376 | ath_rx_edma_buf_link(sc, qtype); |
1377 | } else { | |
b5c80475 | 1378 | ath_rx_buf_link(sc, bf); |
a3dc48e8 | 1379 | ath9k_hw_rxena(ah); |
b5c80475 | 1380 | } |
be0418ad S |
1381 | } while (1); |
1382 | ||
29ab0b36 RM |
1383 | if (!(ah->imask & ATH9K_INT_RXEOL)) { |
1384 | ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 1385 | ath9k_hw_set_interrupts(ah); |
29ab0b36 RM |
1386 | } |
1387 | ||
f078f209 | 1388 | return 0; |
f078f209 | 1389 | } |