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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
51 | struct ath_desc *ds; |
52 | struct sk_buff *skb; | |
53 | ||
54 | ATH_RXBUF_RESET(bf); | |
55 | ||
56 | ds = bf->bf_desc; | |
be0418ad | 57 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
58 | ds->ds_data = bf->bf_buf_addr; |
59 | ||
be0418ad | 60 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
61 | skb = bf->bf_mpdu; |
62 | ASSERT(skb != NULL); | |
63 | ds->ds_vdata = skb->data; | |
64 | ||
b77f483f | 65 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
66 | * how much data it can DMA to us and that we are prepared |
67 | * to process */ | |
b77f483f S |
68 | ath9k_hw_setuprxdesc(ah, ds, |
69 | sc->rx.bufsize, | |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
89 | /* | |
90 | * Extend 15-bit time stamp from rx descriptor to | |
91 | * a full 64-bit TSF using the current h/w TSF. | |
92 | */ | |
93 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
94 | { | |
95 | u64 tsf; | |
96 | ||
97 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
98 | if ((tsf & 0x7fff) < rstamp) | |
99 | tsf -= 0x8000; | |
100 | return (tsf & ~0x7fff) | rstamp; | |
101 | } | |
102 | ||
f078f209 | 103 | /* |
be0418ad S |
104 | * For Decrypt or Demic errors, we only mark packet status here and always push |
105 | * up the frame up to let mac80211 handle the actual error case, be it no | |
106 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 107 | */ |
be0418ad S |
108 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
109 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
110 | struct ath_softc *sc) | |
f078f209 | 111 | { |
be0418ad | 112 | struct ieee80211_hdr *hdr; |
be0418ad S |
113 | u8 ratecode; |
114 | __le16 fc; | |
bce048d7 | 115 | struct ieee80211_hw *hw; |
a59b5a5e SB |
116 | struct ieee80211_sta *sta; |
117 | struct ath_node *an; | |
118 | int last_rssi = ATH_RSSI_DUMMY_MARKER; | |
119 | ||
be0418ad S |
120 | |
121 | hdr = (struct ieee80211_hdr *)skb->data; | |
122 | fc = hdr->frame_control; | |
123 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
bce048d7 | 124 | hw = ath_get_virt_hw(sc, hdr); |
be0418ad S |
125 | |
126 | if (ds->ds_rxstat.rs_more) { | |
127 | /* | |
128 | * Frame spans multiple descriptors; this cannot happen yet | |
129 | * as we don't support jumbograms. If not in monitor mode, | |
130 | * discard the frame. Enable this if you want to see | |
131 | * error frames in Monitor mode. | |
132 | */ | |
2660b81a | 133 | if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR) |
be0418ad S |
134 | goto rx_next; |
135 | } else if (ds->ds_rxstat.rs_status != 0) { | |
136 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
137 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
138 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
139 | goto rx_next; | |
f078f209 | 140 | |
be0418ad S |
141 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
142 | *decrypt_error = true; | |
143 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
144 | if (ieee80211_is_ctl(fc)) | |
145 | /* | |
146 | * Sometimes, we get invalid | |
147 | * MIC failures on valid control frames. | |
148 | * Remove these mic errors. | |
149 | */ | |
150 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
151 | else | |
152 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
153 | } | |
154 | /* | |
155 | * Reject error frames with the exception of | |
156 | * decryption and MIC failures. For monitor mode, | |
157 | * we also ignore the CRC error. | |
158 | */ | |
2660b81a | 159 | if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) { |
be0418ad S |
160 | if (ds->ds_rxstat.rs_status & |
161 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
162 | ATH9K_RXERR_CRC)) | |
163 | goto rx_next; | |
164 | } else { | |
165 | if (ds->ds_rxstat.rs_status & | |
166 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
167 | goto rx_next; | |
168 | } | |
169 | } | |
f078f209 LR |
170 | } |
171 | ||
be0418ad | 172 | ratecode = ds->ds_rxstat.rs_rate; |
be0418ad | 173 | |
be0418ad | 174 | if (ratecode & 0x80) { |
baad1d92 JM |
175 | /* HT rate */ |
176 | rx_status->flag |= RX_FLAG_HT; | |
be0418ad | 177 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) |
baad1d92 | 178 | rx_status->flag |= RX_FLAG_40MHZ; |
be0418ad | 179 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) |
baad1d92 JM |
180 | rx_status->flag |= RX_FLAG_SHORT_GI; |
181 | rx_status->rate_idx = ratecode & 0x7f; | |
182 | } else { | |
183 | int i = 0, cur_band, n_rates; | |
baad1d92 JM |
184 | |
185 | cur_band = hw->conf.channel->band; | |
186 | n_rates = sc->sbands[cur_band].n_bitrates; | |
187 | ||
188 | for (i = 0; i < n_rates; i++) { | |
189 | if (sc->sbands[cur_band].bitrates[i].hw_value == | |
190 | ratecode) { | |
191 | rx_status->rate_idx = i; | |
192 | break; | |
193 | } | |
194 | ||
195 | if (sc->sbands[cur_band].bitrates[i].hw_value_short == | |
196 | ratecode) { | |
197 | rx_status->rate_idx = i; | |
198 | rx_status->flag |= RX_FLAG_SHORTPRE; | |
199 | break; | |
200 | } | |
201 | } | |
be0418ad S |
202 | } |
203 | ||
a59b5a5e SB |
204 | rcu_read_lock(); |
205 | sta = ieee80211_find_sta(sc->hw, hdr->addr2); | |
206 | if (sta) { | |
207 | an = (struct ath_node *) sta->drv_priv; | |
208 | if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD && | |
209 | !ds->ds_rxstat.rs_moreaggr) | |
210 | ATH_RSSI_LPF(an->last_rssi, ds->ds_rxstat.rs_rssi); | |
211 | last_rssi = an->last_rssi; | |
212 | } | |
213 | rcu_read_unlock(); | |
214 | ||
215 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) | |
216 | ds->ds_rxstat.rs_rssi = ATH_EP_RND(last_rssi, | |
217 | ATH_RSSI_EP_MULTIPLIER); | |
218 | if (ds->ds_rxstat.rs_rssi < 0) | |
219 | ds->ds_rxstat.rs_rssi = 0; | |
220 | else if (ds->ds_rxstat.rs_rssi > 127) | |
221 | ds->ds_rxstat.rs_rssi = 127; | |
222 | ||
5e32b1ed S |
223 | /* Update Beacon RSSI, this is used by ANI. */ |
224 | if (ieee80211_is_beacon(fc)) | |
22e66a4c | 225 | sc->sc_ah->stats.avgbrssi = ds->ds_rxstat.rs_rssi; |
5e32b1ed | 226 | |
be0418ad | 227 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); |
bce048d7 JM |
228 | rx_status->band = hw->conf.channel->band; |
229 | rx_status->freq = hw->conf.channel->center_freq; | |
17d7904d | 230 | rx_status->noise = sc->ani.noise_floor; |
a59b5a5e | 231 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + ds->ds_rxstat.rs_rssi; |
be0418ad S |
232 | rx_status->antenna = ds->ds_rxstat.rs_antenna; |
233 | ||
7d5ca3b8 LR |
234 | /* |
235 | * Theory for reporting quality: | |
236 | * | |
237 | * At a hardware RSSI of 45 you will be able to use MCS 7 reliably. | |
238 | * At a hardware RSSI of 45 you will be able to use MCS 15 reliably. | |
239 | * At a hardware RSSI of 35 you should be able use 54 Mbps reliably. | |
240 | * | |
241 | * MCS 7 is the highets MCS index usable by a 1-stream device. | |
242 | * MCS 15 is the highest MCS index usable by a 2-stream device. | |
243 | * | |
244 | * All ath9k devices are either 1-stream or 2-stream. | |
245 | * | |
246 | * How many bars you see is derived from the qual reporting. | |
247 | * | |
248 | * A more elaborate scheme can be used here but it requires tables | |
249 | * of SNR/throughput for each possible mode used. For the MCS table | |
250 | * you can refer to the wireless wiki: | |
251 | * | |
252 | * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n | |
253 | * | |
254 | */ | |
255 | if (conf_is_ht(&hw->conf)) | |
256 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
257 | else | |
258 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 35; | |
be0418ad S |
259 | |
260 | /* rssi can be more than 45 though, anything above that | |
261 | * should be considered at 100% */ | |
262 | if (rx_status->qual > 100) | |
263 | rx_status->qual = 100; | |
264 | ||
265 | rx_status->flag |= RX_FLAG_TSFT; | |
266 | ||
267 | return 1; | |
268 | rx_next: | |
269 | return 0; | |
f078f209 LR |
270 | } |
271 | ||
272 | static void ath_opmode_init(struct ath_softc *sc) | |
273 | { | |
cbe61d8a | 274 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
275 | struct ath_common *common = ath9k_hw_common(ah); |
276 | ||
f078f209 LR |
277 | u32 rfilt, mfilt[2]; |
278 | ||
279 | /* configure rx filter */ | |
280 | rfilt = ath_calcrxfilter(sc); | |
281 | ath9k_hw_setrxfilter(ah, rfilt); | |
282 | ||
283 | /* configure bssid mask */ | |
2660b81a | 284 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
13b81559 | 285 | ath_hw_setbssidmask(common); |
f078f209 LR |
286 | |
287 | /* configure operational mode */ | |
288 | ath9k_hw_setopmode(ah); | |
289 | ||
290 | /* Handle any link-level address change. */ | |
1510718d | 291 | ath9k_hw_setmac(ah, common->macaddr); |
f078f209 LR |
292 | |
293 | /* calculate and install multicast filter */ | |
294 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 295 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
296 | } |
297 | ||
298 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
299 | { | |
27c51f1a | 300 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 LR |
301 | struct sk_buff *skb; |
302 | struct ath_buf *bf; | |
303 | int error = 0; | |
304 | ||
797fe5cb S |
305 | spin_lock_init(&sc->rx.rxflushlock); |
306 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
307 | spin_lock_init(&sc->rx.rxbuflock); | |
f078f209 | 308 | |
797fe5cb | 309 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
27c51f1a | 310 | min(common->cachelsz, (u16)64)); |
f078f209 | 311 | |
c46917bb LR |
312 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
313 | common->cachelsz, sc->rx.bufsize); | |
f078f209 | 314 | |
797fe5cb | 315 | /* Initialize rx descriptors */ |
f078f209 | 316 | |
797fe5cb S |
317 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
318 | "rx", nbufs, 1); | |
319 | if (error != 0) { | |
c46917bb LR |
320 | ath_print(common, ATH_DBG_FATAL, |
321 | "failed to allocate rx descriptors: %d\n", error); | |
797fe5cb S |
322 | goto err; |
323 | } | |
f078f209 | 324 | |
797fe5cb | 325 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
27c51f1a | 326 | skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_KERNEL); |
797fe5cb S |
327 | if (skb == NULL) { |
328 | error = -ENOMEM; | |
329 | goto err; | |
f078f209 | 330 | } |
f078f209 | 331 | |
797fe5cb S |
332 | bf->bf_mpdu = skb; |
333 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
334 | sc->rx.bufsize, | |
335 | DMA_FROM_DEVICE); | |
336 | if (unlikely(dma_mapping_error(sc->dev, | |
337 | bf->bf_buf_addr))) { | |
338 | dev_kfree_skb_any(skb); | |
339 | bf->bf_mpdu = NULL; | |
c46917bb LR |
340 | ath_print(common, ATH_DBG_FATAL, |
341 | "dma_mapping_error() on RX init\n"); | |
797fe5cb S |
342 | error = -ENOMEM; |
343 | goto err; | |
344 | } | |
345 | bf->bf_dmacontext = bf->bf_buf_addr; | |
346 | } | |
347 | sc->rx.rxlink = NULL; | |
f078f209 | 348 | |
797fe5cb | 349 | err: |
f078f209 LR |
350 | if (error) |
351 | ath_rx_cleanup(sc); | |
352 | ||
353 | return error; | |
354 | } | |
355 | ||
f078f209 LR |
356 | void ath_rx_cleanup(struct ath_softc *sc) |
357 | { | |
358 | struct sk_buff *skb; | |
359 | struct ath_buf *bf; | |
360 | ||
b77f483f | 361 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 | 362 | skb = bf->bf_mpdu; |
051b9191 | 363 | if (skb) { |
797fe5cb S |
364 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
365 | sc->rx.bufsize, DMA_FROM_DEVICE); | |
f078f209 | 366 | dev_kfree_skb(skb); |
051b9191 | 367 | } |
f078f209 LR |
368 | } |
369 | ||
b77f483f S |
370 | if (sc->rx.rxdma.dd_desc_len != 0) |
371 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
372 | } |
373 | ||
374 | /* | |
375 | * Calculate the receive filter according to the | |
376 | * operating mode and state: | |
377 | * | |
378 | * o always accept unicast, broadcast, and multicast traffic | |
379 | * o maintain current state of phy error reception (the hal | |
380 | * may enable phy error frames for noise immunity work) | |
381 | * o probe request frames are accepted only when operating in | |
382 | * hostap, adhoc, or monitor modes | |
383 | * o enable promiscuous mode according to the interface state | |
384 | * o accept beacons: | |
385 | * - when operating in adhoc mode so the 802.11 layer creates | |
386 | * node table entries for peers, | |
387 | * - when operating in station mode for collecting rssi data when | |
388 | * the station is otherwise quiet, or | |
389 | * - when operating as a repeater so we see repeater-sta beacons | |
390 | * - when scanning | |
391 | */ | |
392 | ||
393 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
394 | { | |
395 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 396 | |
f078f209 LR |
397 | u32 rfilt; |
398 | ||
399 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
400 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
401 | | ATH9K_RX_FILTER_MCAST; | |
402 | ||
403 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 404 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
405 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
406 | ||
217ba9da JM |
407 | /* |
408 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
409 | * mode interface or when in monitor mode. AP mode does not need this | |
410 | * since it receives all in-BSS frames anyway. | |
411 | */ | |
2660b81a | 412 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 413 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 414 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 415 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 416 | |
d42c6b71 S |
417 | if (sc->rx.rxfilter & FIF_CONTROL) |
418 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
419 | ||
dbaaa147 VT |
420 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
421 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
422 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
423 | else | |
f078f209 LR |
424 | rfilt |= ATH9K_RX_FILTER_BEACON; |
425 | ||
63b08b8d | 426 | if (sc->rx.rxfilter & FIF_PSPOLL) |
dbaaa147 | 427 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 428 | |
7ea310be S |
429 | if (conf_is_ht(&sc->hw->conf)) |
430 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
431 | ||
5eb6ba83 | 432 | if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
b93bce2a JM |
433 | /* TODO: only needed if more than one BSSID is in use in |
434 | * station/adhoc mode */ | |
5eb6ba83 JC |
435 | /* The following may also be needed for other older chips */ |
436 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
437 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
438 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
439 | } | |
440 | ||
f078f209 | 441 | return rfilt; |
7dcfdcd9 | 442 | |
f078f209 LR |
443 | #undef RX_FILTER_PRESERVE |
444 | } | |
445 | ||
f078f209 LR |
446 | int ath_startrecv(struct ath_softc *sc) |
447 | { | |
cbe61d8a | 448 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
449 | struct ath_buf *bf, *tbf; |
450 | ||
b77f483f S |
451 | spin_lock_bh(&sc->rx.rxbuflock); |
452 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
453 | goto start_recv; |
454 | ||
b77f483f S |
455 | sc->rx.rxlink = NULL; |
456 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
457 | ath_rx_buf_link(sc, bf); |
458 | } | |
459 | ||
460 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 461 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
462 | goto start_recv; |
463 | ||
b77f483f | 464 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 465 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 466 | ath9k_hw_rxena(ah); |
f078f209 LR |
467 | |
468 | start_recv: | |
b77f483f | 469 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
470 | ath_opmode_init(sc); |
471 | ath9k_hw_startpcureceive(ah); | |
472 | ||
f078f209 LR |
473 | return 0; |
474 | } | |
475 | ||
f078f209 LR |
476 | bool ath_stoprecv(struct ath_softc *sc) |
477 | { | |
cbe61d8a | 478 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
479 | bool stopped; |
480 | ||
be0418ad S |
481 | ath9k_hw_stoppcurecv(ah); |
482 | ath9k_hw_setrxfilter(ah, 0); | |
483 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 484 | sc->rx.rxlink = NULL; |
be0418ad | 485 | |
f078f209 LR |
486 | return stopped; |
487 | } | |
488 | ||
f078f209 LR |
489 | void ath_flushrecv(struct ath_softc *sc) |
490 | { | |
b77f483f | 491 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 492 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 493 | ath_rx_tasklet(sc, 1); |
98deeea0 | 494 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 495 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
496 | } |
497 | ||
cc65965c JM |
498 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
499 | { | |
500 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
501 | struct ieee80211_mgmt *mgmt; | |
502 | u8 *pos, *end, id, elen; | |
503 | struct ieee80211_tim_ie *tim; | |
504 | ||
505 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
506 | pos = mgmt->u.beacon.variable; | |
507 | end = skb->data + skb->len; | |
508 | ||
509 | while (pos + 2 < end) { | |
510 | id = *pos++; | |
511 | elen = *pos++; | |
512 | if (pos + elen > end) | |
513 | break; | |
514 | ||
515 | if (id == WLAN_EID_TIM) { | |
516 | if (elen < sizeof(*tim)) | |
517 | break; | |
518 | tim = (struct ieee80211_tim_ie *) pos; | |
519 | if (tim->dtim_count != 0) | |
520 | break; | |
521 | return tim->bitmap_ctrl & 0x01; | |
522 | } | |
523 | ||
524 | pos += elen; | |
525 | } | |
526 | ||
527 | return false; | |
528 | } | |
529 | ||
cc65965c JM |
530 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
531 | { | |
532 | struct ieee80211_mgmt *mgmt; | |
1510718d | 533 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
534 | |
535 | if (skb->len < 24 + 8 + 2 + 2) | |
536 | return; | |
537 | ||
538 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
1510718d | 539 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) |
cc65965c JM |
540 | return; /* not from our current AP */ |
541 | ||
293dc5df GJ |
542 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; |
543 | ||
ccdfeab6 JM |
544 | if (sc->sc_flags & SC_OP_BEACON_SYNC) { |
545 | sc->sc_flags &= ~SC_OP_BEACON_SYNC; | |
c46917bb LR |
546 | ath_print(common, ATH_DBG_PS, |
547 | "Reconfigure Beacon timers based on " | |
548 | "timestamp from the AP\n"); | |
ccdfeab6 JM |
549 | ath_beacon_config(sc, NULL); |
550 | } | |
551 | ||
cc65965c JM |
552 | if (ath_beacon_dtim_pending_cab(skb)) { |
553 | /* | |
554 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
555 | * frames. If the last broadcast/multicast frame is not |
556 | * received properly, the next beacon frame will work as | |
557 | * a backup trigger for returning into NETWORK SLEEP state, | |
558 | * so we are waiting for it as well. | |
cc65965c | 559 | */ |
c46917bb LR |
560 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " |
561 | "buffered broadcast/multicast frame(s)\n"); | |
58f5fffd | 562 | sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; |
cc65965c JM |
563 | return; |
564 | } | |
565 | ||
566 | if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) { | |
567 | /* | |
568 | * This can happen if a broadcast frame is dropped or the AP | |
569 | * fails to send a frame indicating that all CAB frames have | |
570 | * been delivered. | |
571 | */ | |
293dc5df | 572 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
573 | ath_print(common, ATH_DBG_PS, |
574 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 575 | } |
cc65965c JM |
576 | } |
577 | ||
578 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
579 | { | |
580 | struct ieee80211_hdr *hdr; | |
c46917bb | 581 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
582 | |
583 | hdr = (struct ieee80211_hdr *)skb->data; | |
584 | ||
585 | /* Process Beacon and CAB receive in PS state */ | |
9a23f9ca JM |
586 | if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) && |
587 | ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c JM |
588 | ath_rx_ps_beacon(sc, skb); |
589 | else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) && | |
590 | (ieee80211_is_data(hdr->frame_control) || | |
591 | ieee80211_is_action(hdr->frame_control)) && | |
592 | is_multicast_ether_addr(hdr->addr1) && | |
593 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
594 | /* |
595 | * No more broadcast/multicast frames to be received at this | |
596 | * point. | |
597 | */ | |
293dc5df | 598 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
599 | ath_print(common, ATH_DBG_PS, |
600 | "All PS CAB frames received, back to sleep\n"); | |
9a23f9ca JM |
601 | } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && |
602 | !is_multicast_ether_addr(hdr->addr1) && | |
603 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
604 | sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; | |
c46917bb LR |
605 | ath_print(common, ATH_DBG_PS, |
606 | "Going back to sleep after having received " | |
607 | "PS-Poll data (0x%x)\n", | |
9a23f9ca JM |
608 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
609 | SC_OP_WAIT_FOR_CAB | | |
610 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
611 | SC_OP_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
612 | } |
613 | } | |
614 | ||
9d64a3cf JM |
615 | static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb, |
616 | struct ieee80211_rx_status *rx_status) | |
617 | { | |
618 | struct ieee80211_hdr *hdr; | |
619 | ||
620 | hdr = (struct ieee80211_hdr *)skb->data; | |
621 | ||
622 | /* Send the frame to mac80211 */ | |
623 | if (is_multicast_ether_addr(hdr->addr1)) { | |
624 | int i; | |
625 | /* | |
626 | * Deliver broadcast/multicast frames to all suitable | |
627 | * virtual wiphys. | |
628 | */ | |
629 | /* TODO: filter based on channel configuration */ | |
630 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
631 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
632 | struct sk_buff *nskb; | |
633 | if (aphy == NULL) | |
634 | continue; | |
635 | nskb = skb_copy(skb, GFP_ATOMIC); | |
f1d58c25 JB |
636 | if (nskb) { |
637 | memcpy(IEEE80211_SKB_RXCB(nskb), rx_status, | |
638 | sizeof(*rx_status)); | |
639 | ieee80211_rx(aphy->hw, nskb); | |
640 | } | |
9d64a3cf | 641 | } |
f1d58c25 JB |
642 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
643 | ieee80211_rx(sc->hw, skb); | |
9d64a3cf JM |
644 | } else { |
645 | /* Deliver unicast frames based on receiver address */ | |
f1d58c25 JB |
646 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
647 | ieee80211_rx(ath_get_virt_hw(sc, hdr), skb); | |
9d64a3cf JM |
648 | } |
649 | } | |
650 | ||
f078f209 LR |
651 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
652 | { | |
653 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
654 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
655 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 656 | |
be0418ad | 657 | struct ath_buf *bf; |
f078f209 | 658 | struct ath_desc *ds; |
cb71d9ba | 659 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 660 | struct ieee80211_rx_status rx_status; |
cbe61d8a | 661 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 662 | struct ath_common *common = ath9k_hw_common(ah); |
be0418ad S |
663 | struct ieee80211_hdr *hdr; |
664 | int hdrlen, padsize, retval; | |
665 | bool decrypt_error = false; | |
666 | u8 keyix; | |
853da11b | 667 | __le16 fc; |
be0418ad | 668 | |
b77f483f | 669 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
670 | |
671 | do { | |
672 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 673 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
674 | break; |
675 | ||
b77f483f S |
676 | if (list_empty(&sc->rx.rxbuf)) { |
677 | sc->rx.rxlink = NULL; | |
f078f209 LR |
678 | break; |
679 | } | |
680 | ||
b77f483f | 681 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 682 | ds = bf->bf_desc; |
f078f209 LR |
683 | |
684 | /* | |
685 | * Must provide the virtual address of the current | |
686 | * descriptor, the physical address, and the virtual | |
687 | * address of the next descriptor in the h/w chain. | |
688 | * This allows the HAL to look ahead to see if the | |
689 | * hardware is done with a descriptor by checking the | |
690 | * done bit in the following descriptor and the address | |
691 | * of the current descriptor the DMA engine is working | |
692 | * on. All this is necessary because of our use of | |
693 | * a self-linked list to avoid rx overruns. | |
694 | */ | |
be0418ad | 695 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
696 | bf->bf_daddr, |
697 | PA2DESC(sc, ds->ds_link), | |
698 | 0); | |
699 | if (retval == -EINPROGRESS) { | |
700 | struct ath_buf *tbf; | |
701 | struct ath_desc *tds; | |
702 | ||
b77f483f S |
703 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
704 | sc->rx.rxlink = NULL; | |
f078f209 LR |
705 | break; |
706 | } | |
707 | ||
708 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
709 | ||
710 | /* | |
711 | * On some hardware the descriptor status words could | |
712 | * get corrupted, including the done bit. Because of | |
713 | * this, check if the next descriptor's done bit is | |
714 | * set or not. | |
715 | * | |
716 | * If the next descriptor's done bit is set, the current | |
717 | * descriptor has been corrupted. Force s/w to discard | |
718 | * this descriptor and continue... | |
719 | */ | |
720 | ||
721 | tds = tbf->bf_desc; | |
be0418ad S |
722 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
723 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 724 | if (retval == -EINPROGRESS) { |
f078f209 LR |
725 | break; |
726 | } | |
727 | } | |
728 | ||
f078f209 | 729 | skb = bf->bf_mpdu; |
be0418ad | 730 | if (!skb) |
f078f209 | 731 | continue; |
f078f209 | 732 | |
9bf9fca8 VT |
733 | /* |
734 | * Synchronize the DMA transfer with CPU before | |
735 | * 1. accessing the frame | |
736 | * 2. requeueing the same buffer to h/w | |
737 | */ | |
7da3c55c | 738 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 739 | sc->rx.bufsize, |
7da3c55c | 740 | DMA_FROM_DEVICE); |
9bf9fca8 | 741 | |
f078f209 | 742 | /* |
be0418ad S |
743 | * If we're asked to flush receive queue, directly |
744 | * chain it back at the queue without processing it. | |
f078f209 | 745 | */ |
be0418ad | 746 | if (flush) |
cb71d9ba | 747 | goto requeue; |
f078f209 | 748 | |
be0418ad | 749 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 750 | goto requeue; |
f078f209 | 751 | |
be0418ad | 752 | /* The status portion of the descriptor could get corrupted. */ |
b77f483f | 753 | if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 754 | goto requeue; |
f078f209 | 755 | |
be0418ad | 756 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
757 | goto requeue; |
758 | ||
759 | /* Ensure we always have an skb to requeue once we are done | |
760 | * processing the current buffer's skb */ | |
27c51f1a | 761 | requeue_skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_ATOMIC); |
cb71d9ba LR |
762 | |
763 | /* If there is no memory we ignore the current RX'd frame, | |
764 | * tell hardware it can give us a new frame using the old | |
b77f483f | 765 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
766 | * processing. */ |
767 | if (!requeue_skb) | |
768 | goto requeue; | |
f078f209 | 769 | |
9bf9fca8 | 770 | /* Unmap the frame */ |
7da3c55c | 771 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 772 | sc->rx.bufsize, |
7da3c55c | 773 | DMA_FROM_DEVICE); |
f078f209 | 774 | |
be0418ad | 775 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
be0418ad S |
776 | |
777 | /* see if any padding is done by the hw and remove it */ | |
778 | hdr = (struct ieee80211_hdr *)skb->data; | |
779 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
853da11b | 780 | fc = hdr->frame_control; |
be0418ad | 781 | |
9c5f89b3 JM |
782 | /* The MAC header is padded to have 32-bit boundary if the |
783 | * packet payload is non-zero. The general calculation for | |
784 | * padsize would take into account odd header lengths: | |
785 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
786 | * even-length headers are used, padding can only be 0 or 2 | |
787 | * bytes and we can optimize this a bit. In addition, we must | |
788 | * not try to remove padding from short control frames that do | |
789 | * not have payload. */ | |
790 | padsize = hdrlen & 3; | |
791 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
792 | memmove(skb->data + padsize, skb->data, hdrlen); |
793 | skb_pull(skb, padsize); | |
f078f209 LR |
794 | } |
795 | ||
be0418ad | 796 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 797 | |
be0418ad S |
798 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
799 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
9d64a3cf | 800 | } else if (ieee80211_has_protected(fc) |
be0418ad S |
801 | && !decrypt_error && skb->len >= hdrlen + 4) { |
802 | keyix = skb->data[hdrlen + 3] >> 6; | |
803 | ||
17d7904d | 804 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
805 | rx_status.flag |= RX_FLAG_DECRYPTED; |
806 | } | |
0ced0e17 JM |
807 | if (ah->sw_mgmt_crypto && |
808 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
9d64a3cf | 809 | ieee80211_is_mgmt(fc)) { |
0ced0e17 JM |
810 | /* Use software decrypt for management frames. */ |
811 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
812 | } | |
be0418ad | 813 | |
cb71d9ba LR |
814 | /* We will now give hardware our shiny new allocated skb */ |
815 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 816 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 817 | sc->rx.bufsize, |
7da3c55c GJ |
818 | DMA_FROM_DEVICE); |
819 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
820 | bf->bf_buf_addr))) { |
821 | dev_kfree_skb_any(requeue_skb); | |
822 | bf->bf_mpdu = NULL; | |
c46917bb LR |
823 | ath_print(common, ATH_DBG_FATAL, |
824 | "dma_mapping_error() on RX\n"); | |
cc65965c | 825 | ath_rx_send_to_mac80211(sc, skb, &rx_status); |
f8316df1 LR |
826 | break; |
827 | } | |
cb71d9ba | 828 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
829 | |
830 | /* | |
831 | * change the default rx antenna if rx diversity chooses the | |
832 | * other antenna 3 times in a row. | |
833 | */ | |
b77f483f S |
834 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
835 | if (++sc->rx.rxotherant >= 3) | |
be0418ad | 836 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 | 837 | } else { |
b77f483f | 838 | sc->rx.rxotherant = 0; |
f078f209 | 839 | } |
3cbb5dd7 | 840 | |
9a23f9ca | 841 | if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
f0e9a860 | 842 | SC_OP_WAIT_FOR_CAB | |
9a23f9ca | 843 | SC_OP_WAIT_FOR_PSPOLL_DATA))) |
cc65965c JM |
844 | ath_rx_ps(sc, skb); |
845 | ||
846 | ath_rx_send_to_mac80211(sc, skb, &rx_status); | |
847 | ||
cb71d9ba | 848 | requeue: |
b77f483f | 849 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 850 | ath_rx_buf_link(sc, bf); |
be0418ad S |
851 | } while (1); |
852 | ||
b77f483f | 853 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
854 | |
855 | return 0; | |
856 | #undef PA2DESC | |
857 | } |