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ath9k: protect tid->sched check
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / xmit.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209
LR		 20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
f078f209
LR		 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
aa5955c3
FF		 32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
f078f209
LR		 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
f078f209 37
c6663876 38static u16 bits_per_symbol[][2] = {
f078f209
LR		 39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
f078f209
LR		 48};
49
82b873af 50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c
FF		 51 struct ath_atx_tid *tid, struct sk_buff *skb);
52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
e8324357 54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 55 struct ath_txq *txq, struct list_head *bf_q,
156369fa 56 struct ath_tx_status *ts, int txok);
102e0572 57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 58 struct list_head *head, bool internal);
0cdd5c60
FF		 59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 61 int txok);
90fa539c
FF		 62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
44f1d26c
FF		 64static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
249ee722 67 struct sk_buff *skb);
c4288390 68
545750d3 69enum {
0e668cde
FF		 70 MCS_HT20,
71 MCS_HT20_SGI,
545750d3
FF		 72 MCS_HT40,
73 MCS_HT40_SGI,
74};
75
e8324357
S		 76/*********************/
77/* Aggregation logic */
78/*********************/
f078f209 79
ef1b6cd9 80void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 81 __acquires(&txq->axq_lock)
23de5dc9
FF		 82{
83 spin_lock_bh(&txq->axq_lock);
84}
85
ef1b6cd9 86void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 87 __releases(&txq->axq_lock)
23de5dc9
FF		 88{
89 spin_unlock_bh(&txq->axq_lock);
90}
91
ef1b6cd9 92void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
1512a486 93 __releases(&txq->axq_lock)
23de5dc9
FF		 94{
95 struct sk_buff_head q;
96 struct sk_buff *skb;
97
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
101
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
104}
105
e8324357 106static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
ff37e337 107{
e8324357 108 struct ath_atx_ac *ac = tid->ac;
ff37e337 109
e8324357
S		 110 if (tid->paused)
111 return;
ff37e337 112
e8324357
S		 113 if (tid->sched)
114 return;
ff37e337 115
e8324357
S		 116 tid->sched = true;
117 list_add_tail(&tid->list, &ac->tid_q);
528f0c6b 118
e8324357
S		 119 if (ac->sched)
120 return;
f078f209 121
e8324357
S		 122 ac->sched = true;
123 list_add_tail(&ac->list, &txq->axq_acq);
124}
f078f209 125
2d42efc4 126static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
76e45221
FF		 127{
128 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4
FF		 129 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
130 sizeof(tx_info->rate_driver_data));
131 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
76e45221
FF		 132}
133
156369fa
FF		 134static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
135{
f89d1bc4
FF		 136 if (!tid->an->sta)
137 return;
138
156369fa
FF		 139 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
140 seqno << IEEE80211_SEQ_SEQ_SHIFT);
141}
142
79acac07
FF		 143static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
144 struct ath_buf *bf)
145{
146 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
147 ARRAY_SIZE(bf->rates));
148}
149
a4943ccb
FF		 150static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
151 struct sk_buff *skb)
152{
153 int q;
154
155 q = skb_get_queue_mapping(skb);
156 if (txq == sc->tx.uapsdq)
157 txq = sc->tx.txq_map[q];
158
159 if (txq != sc->tx.txq_map[q])
160 return;
161
162 if (WARN_ON(--txq->pending_frames < 0))
163 txq->pending_frames = 0;
164
165 if (txq->stopped &&
166 txq->pending_frames < sc->tx.txq_max_pending[q]) {
167 ieee80211_wake_queue(sc->hw, q);
168 txq->stopped = false;
169 }
170}
171
1803d02d
FF		 172static struct ath_atx_tid *
173ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
174{
39731b78 175 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
1803d02d
FF		 176 return ATH_AN_2_TID(an, tidno);
177}
178
a7586ee4
FF		 179static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
180{
bb195ff6 181 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
a7586ee4
FF		 182}
183
184static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
185{
bb195ff6
FF		 186 struct sk_buff *skb;
187
188 skb = __skb_dequeue(&tid->retry_q);
189 if (!skb)
190 skb = __skb_dequeue(&tid->buf_q);
191
192 return skb;
a7586ee4
FF		 193}
194
2800e82b
FF		 195/*
196 * ath_tx_tid_change_state:
197 * - clears a-mpdu flag of previous session
198 * - force sequence number allocation to fix next BlockAck Window
199 */
200static void
201ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
202{
203 struct ath_txq *txq = tid->ac->txq;
204 struct ieee80211_tx_info *tx_info;
205 struct sk_buff *skb, *tskb;
206 struct ath_buf *bf;
207 struct ath_frame_info *fi;
208
209 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
210 fi = get_frame_info(skb);
211 bf = fi->bf;
212
213 tx_info = IEEE80211_SKB_CB(skb);
214 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
215
216 if (bf)
217 continue;
218
219 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
220 if (!bf) {
221 __skb_unlink(skb, &tid->buf_q);
222 ath_txq_skb_done(sc, txq, skb);
223 ieee80211_free_txskb(sc->hw, skb);
224 continue;
225 }
226 }
227
228}
229
08c96abd 230static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
528f0c6b 231{
066dae93 232 struct ath_txq *txq = tid->ac->txq;
56dc6336 233 struct sk_buff *skb;
e8324357
S		 234 struct ath_buf *bf;
235 struct list_head bf_head;
90fa539c 236 struct ath_tx_status ts;
2d42efc4 237 struct ath_frame_info *fi;
156369fa 238 bool sendbar = false;
f078f209 239
90fa539c 240 INIT_LIST_HEAD(&bf_head);
e6a9854b 241
90fa539c 242 memset(&ts, 0, sizeof(ts));
f078f209 243
2800e82b 244 while ((skb = __skb_dequeue(&tid->retry_q))) {
56dc6336
FF		 245 fi = get_frame_info(skb);
246 bf = fi->bf;
249ee722 247 if (!bf) {
2800e82b
FF		 248 ath_txq_skb_done(sc, txq, skb);
249 ieee80211_free_txskb(sc->hw, skb);
250 continue;
249ee722
FF		 251 }
252
8fed1408 253 if (fi->baw_tracked) {
6a0ddaef 254 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
156369fa 255 sendbar = true;
90fa539c 256 }
2800e82b
FF		 257
258 list_add_tail(&bf->list, &bf_head);
259 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
528f0c6b 260 }
f078f209 261
08c96abd 262 if (sendbar) {
23de5dc9 263 ath_txq_unlock(sc, txq);
156369fa 264 ath_send_bar(tid, tid->seq_start);
23de5dc9
FF		 265 ath_txq_lock(sc, txq);
266 }
528f0c6b 267}
f078f209 268
e8324357
S		 269static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
270 int seqno)
528f0c6b 271{
e8324357 272 int index, cindex;
f078f209 273
e8324357
S		 274 index = ATH_BA_INDEX(tid->seq_start, seqno);
275 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
f078f209 276
81ee13ba 277 __clear_bit(cindex, tid->tx_buf);
528f0c6b 278
81ee13ba 279 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
e8324357
S		 280 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
281 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
f9437543
FF		 282 if (tid->bar_index >= 0)
283 tid->bar_index--;
e8324357 284 }
528f0c6b 285}
f078f209 286
e8324357 287static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
8fed1408 288 struct ath_buf *bf)
528f0c6b 289{
8fed1408
FF		 290 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
291 u16 seqno = bf->bf_state.seqno;
e8324357 292 int index, cindex;
528f0c6b 293
2d3bcba0 294 index = ATH_BA_INDEX(tid->seq_start, seqno);
e8324357 295 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
81ee13ba 296 __set_bit(cindex, tid->tx_buf);
8fed1408 297 fi->baw_tracked = 1;
f078f209 298
e8324357
S		 299 if (index >= ((tid->baw_tail - tid->baw_head) &
300 (ATH_TID_MAX_BUFS - 1))) {
301 tid->baw_tail = cindex;
302 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
f078f209 303 }
f078f209
LR		 304}
305
e8324357
S		 306static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
307 struct ath_atx_tid *tid)
f078f209 308
f078f209 309{
56dc6336 310 struct sk_buff *skb;
e8324357
S		 311 struct ath_buf *bf;
312 struct list_head bf_head;
db1a052b 313 struct ath_tx_status ts;
2d42efc4 314 struct ath_frame_info *fi;
db1a052b
FF		 315
316 memset(&ts, 0, sizeof(ts));
e8324357 317 INIT_LIST_HEAD(&bf_head);
f078f209 318
a7586ee4 319 while ((skb = ath_tid_dequeue(tid))) {
56dc6336
FF		 320 fi = get_frame_info(skb);
321 bf = fi->bf;
f078f209 322
44f1d26c 323 if (!bf) {
44f1d26c 324 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
44f1d26c
FF		 325 continue;
326 }
327
56dc6336 328 list_add_tail(&bf->list, &bf_head);
156369fa 329 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
e8324357 330 }
f078f209
LR		 331}
332
fec247c0 333static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
da647626 334 struct sk_buff *skb, int count)
f078f209 335{
8b7f8532 336 struct ath_frame_info *fi = get_frame_info(skb);
f11cc949 337 struct ath_buf *bf = fi->bf;
e8324357 338 struct ieee80211_hdr *hdr;
da647626 339 int prev = fi->retries;
f078f209 340
fec247c0 341 TX_STAT_INC(txq->axq_qnum, a_retries);
da647626
FF		 342 fi->retries += count;
343
344 if (prev > 0)
2d42efc4 345 return;
f078f209 346
e8324357
S		 347 hdr = (struct ieee80211_hdr *)skb->data;
348 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
f11cc949
FF		 349 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
350 sizeof(*hdr), DMA_TO_DEVICE);
f078f209
LR		 351}
352
0a8cea84 353static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
d43f3015 354{
0a8cea84 355 struct ath_buf *bf = NULL;
d43f3015
S		 356
357 spin_lock_bh(&sc->tx.txbuflock);
0a8cea84
FF		 358
359 if (unlikely(list_empty(&sc->tx.txbuf))) {
8a46097a
VT		 360 spin_unlock_bh(&sc->tx.txbuflock);
361 return NULL;
362 }
0a8cea84
FF		 363
364 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
365 list_del(&bf->list);
366
d43f3015
S		 367 spin_unlock_bh(&sc->tx.txbuflock);
368
0a8cea84
FF		 369 return bf;
370}
371
372static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
373{
374 spin_lock_bh(&sc->tx.txbuflock);
375 list_add_tail(&bf->list, &sc->tx.txbuf);
376 spin_unlock_bh(&sc->tx.txbuflock);
377}
378
379static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
380{
381 struct ath_buf *tbf;
382
383 tbf = ath_tx_get_buffer(sc);
384 if (WARN_ON(!tbf))
385 return NULL;
386
d43f3015
S		 387 ATH_TXBUF_RESET(tbf);
388
389 tbf->bf_mpdu = bf->bf_mpdu;
390 tbf->bf_buf_addr = bf->bf_buf_addr;
d826c832 391 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
d43f3015 392 tbf->bf_state = bf->bf_state;
86c7d8d4 393 tbf->bf_state.stale = false;
d43f3015
S		 394
395 return tbf;
396}
397
b572d033
FF		 398static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
399 struct ath_tx_status *ts, int txok,
400 int *nframes, int *nbad)
401{
2d42efc4 402 struct ath_frame_info *fi;
b572d033
FF		 403 u16 seq_st = 0;
404 u32 ba[WME_BA_BMP_SIZE >> 5];
405 int ba_index;
406 int isaggr = 0;
407
408 *nbad = 0;
409 *nframes = 0;
410
b572d033
FF		 411 isaggr = bf_isaggr(bf);
412 if (isaggr) {
413 seq_st = ts->ts_seqnum;
414 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
415 }
416
417 while (bf) {
2d42efc4 418 fi = get_frame_info(bf->bf_mpdu);
6a0ddaef 419 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
b572d033
FF		 420
421 (*nframes)++;
422 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
423 (*nbad)++;
424
425 bf = bf->bf_next;
426 }
427}
428
429
d43f3015
S		 430static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
431 struct ath_buf *bf, struct list_head *bf_q,
1381559b 432 struct ath_tx_status *ts, int txok)
f078f209 433{
e8324357
S		 434 struct ath_node *an = NULL;
435 struct sk_buff *skb;
1286ec6d 436 struct ieee80211_sta *sta;
0cdd5c60 437 struct ieee80211_hw *hw = sc->hw;
1286ec6d 438 struct ieee80211_hdr *hdr;
76d5a9e8 439 struct ieee80211_tx_info *tx_info;
e8324357 440 struct ath_atx_tid *tid = NULL;
d43f3015 441 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
56dc6336
FF		 442 struct list_head bf_head;
443 struct sk_buff_head bf_pending;
156369fa 444 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
f078f209 445 u32 ba[WME_BA_BMP_SIZE >> 5];
0934af23 446 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
6fe7cc71 447 bool rc_update = true, isba;
78c4653a 448 struct ieee80211_tx_rate rates[4];
2d42efc4 449 struct ath_frame_info *fi;
ebd02287 450 int nframes;
daa5c408 451 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
da647626 452 int i, retries;
156369fa 453 int bar_index = -1;
f078f209 454
a22be22a 455 skb = bf->bf_mpdu;
1286ec6d
S		 456 hdr = (struct ieee80211_hdr *)skb->data;
457
76d5a9e8 458 tx_info = IEEE80211_SKB_CB(skb);
76d5a9e8 459
79acac07 460 memcpy(rates, bf->rates, sizeof(rates));
78c4653a 461
da647626
FF		 462 retries = ts->ts_longretry + 1;
463 for (i = 0; i < ts->ts_rateindex; i++)
464 retries += rates[i].count;
465
1286ec6d 466 rcu_read_lock();
f078f209 467
686b9cb9 468 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
1286ec6d
S		 469 if (!sta) {
470 rcu_read_unlock();
73e19463 471
31e79a59
FF		 472 INIT_LIST_HEAD(&bf_head);
473 while (bf) {
474 bf_next = bf->bf_next;
475
50676b81 476 if (!bf->bf_state.stale || bf_next != NULL)
31e79a59
FF		 477 list_move_tail(&bf->list, &bf_head);
478
156369fa 479 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
31e79a59
FF		 480
481 bf = bf_next;
482 }
1286ec6d 483 return;
f078f209
LR		 484 }
485
1286ec6d 486 an = (struct ath_node *)sta->drv_priv;
1803d02d 487 tid = ath_get_skb_tid(sc, an, skb);
156369fa 488 seq_first = tid->seq_start;
6fe7cc71 489 isba = ts->ts_flags & ATH9K_TX_BA;
1286ec6d 490
b11b160d
FF		 491 /*
492 * The hardware occasionally sends a tx status for the wrong TID.
493 * In this case, the BA status cannot be considered valid and all
494 * subframes need to be retransmitted
6fe7cc71
SE		 495 *
496 * Only BlockAcks have a TID and therefore normal Acks cannot be
497 * checked
b11b160d 498 */
1803d02d 499 if (isba && tid->tidno != ts->tid)
b11b160d
FF		 500 txok = false;
501
e8324357 502 isaggr = bf_isaggr(bf);
d43f3015 503 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
f078f209 504
d43f3015 505 if (isaggr && txok) {
db1a052b
FF		 506 if (ts->ts_flags & ATH9K_TX_BA) {
507 seq_st = ts->ts_seqnum;
508 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
e8324357 509 } else {
d43f3015
S		 510 /*
511 * AR5416 can become deaf/mute when BA
512 * issue happens. Chip needs to be reset.
513 * But AP code may have sychronization issues
514 * when perform internal reset in this routine.
515 * Only enable reset in STA mode for now.
516 */
2660b81a 517 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
d43f3015 518 needreset = 1;
e8324357 519 }
f078f209
LR		 520 }
521
56dc6336 522 __skb_queue_head_init(&bf_pending);
f078f209 523
b572d033 524 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
e8324357 525 while (bf) {
6a0ddaef
FF		 526 u16 seqno = bf->bf_state.seqno;
527
f0b8220c 528 txfail = txpending = sendbar = 0;
e8324357 529 bf_next = bf->bf_next;
f078f209 530
78c4653a
FF		 531 skb = bf->bf_mpdu;
532 tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 533 fi = get_frame_info(skb);
78c4653a 534
897d7fd9
FF		 535 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
536 !tid->active) {
08c96abd
FF		 537 /*
538 * Outside of the current BlockAck window,
539 * maybe part of a previous session
540 */
541 txfail = 1;
542 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
e8324357
S		 543 /* transmit completion, subframe is
544 * acked by block ack */
0934af23 545 acked_cnt++;
e8324357
S		 546 } else if (!isaggr && txok) {
547 /* transmit completion */
0934af23 548 acked_cnt++;
b0477013
FF		 549 } else if (flush) {
550 txpending = 1;
551 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
552 if (txok || !an->sleeping)
553 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
554 retries);
555
556 txpending = 1;
e8324357 557 } else {
b0477013
FF		 558 txfail = 1;
559 txfail_cnt++;
560 bar_index = max_t(int, bar_index,
561 ATH_BA_INDEX(seq_first, seqno));
e8324357 562 }
f078f209 563
fce041be
FF		 564 /*
565 * Make sure the last desc is reclaimed if it
566 * not a holding desc.
567 */
56dc6336 568 INIT_LIST_HEAD(&bf_head);
50676b81 569 if (bf_next != NULL || !bf_last->bf_state.stale)
d43f3015 570 list_move_tail(&bf->list, &bf_head);
f078f209 571
08c96abd 572 if (!txpending) {
e8324357
S		 573 /*
574 * complete the acked-ones/xretried ones; update
575 * block-ack window
576 */
6a0ddaef 577 ath_tx_update_baw(sc, tid, seqno);
f078f209 578
8a92e2ee 579 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
78c4653a 580 memcpy(tx_info->control.rates, rates, sizeof(rates));
3afd21e7 581 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
8a92e2ee 582 rc_update = false;
8a92e2ee
VT		 583 }
584
db1a052b 585 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
156369fa 586 !txfail);
e8324357 587 } else {
86a22acf
FF		 588 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
589 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
590 ieee80211_sta_eosp(sta);
591 }
d43f3015 592 /* retry the un-acked ones */
50676b81 593 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
b0477013
FF		 594 struct ath_buf *tbf;
595
596 tbf = ath_clone_txbuf(sc, bf_last);
597 /*
598 * Update tx baw and complete the
599 * frame with failed status if we
600 * run out of tx buf.
601 */
602 if (!tbf) {
b0477013 603 ath_tx_update_baw(sc, tid, seqno);
b0477013
FF		 604
605 ath_tx_complete_buf(sc, bf, txq,
606 &bf_head, ts, 0);
607 bar_index = max_t(int, bar_index,
608 ATH_BA_INDEX(seq_first, seqno));
609 break;
c41d92dc 610 }
b0477013
FF		 611
612 fi->bf = tbf;
e8324357
S		 613 }
614
615 /*
616 * Put this buffer to the temporary pending
617 * queue to retain ordering
618 */
56dc6336 619 __skb_queue_tail(&bf_pending, skb);
e8324357
S		 620 }
621
622 bf = bf_next;
f078f209 623 }
f078f209 624
4cee7861 625 /* prepend un-acked frames to the beginning of the pending frame queue */
56dc6336 626 if (!skb_queue_empty(&bf_pending)) {
5519541d 627 if (an->sleeping)
042ec453 628 ieee80211_sta_set_buffered(sta, tid->tidno, true);
5519541d 629
bb195ff6 630 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
26a64259 631 if (!an->sleeping) {
9af73cf7 632 ath_tx_queue_tid(txq, tid);
26a64259 633
adfbda62 634 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
26a64259
FF		 635 tid->ac->clear_ps_filter = true;
636 }
4cee7861
FF		 637 }
638
23de5dc9
FF		 639 if (bar_index >= 0) {
640 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
641
642 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
643 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
644
645 ath_txq_unlock(sc, txq);
646 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
647 ath_txq_lock(sc, txq);
648 }
649
1286ec6d
S		 650 rcu_read_unlock();
651
124b979b
RM		 652 if (needreset)
653 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
e8324357 654}
f078f209 655
81b51950
FF		 656static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
657{
658 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
659 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
660}
661
662static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
663 struct ath_tx_status *ts, struct ath_buf *bf,
664 struct list_head *bf_head)
665{
0c585dda 666 struct ieee80211_tx_info *info;
81b51950
FF		 667 bool txok, flush;
668
669 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
670 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
671 txq->axq_tx_inprogress = false;
672
673 txq->axq_depth--;
674 if (bf_is_ampdu_not_probing(bf))
675 txq->axq_ampdu_depth--;
676
677 if (!bf_isampdu(bf)) {
0c585dda
FF		 678 if (!flush) {
679 info = IEEE80211_SKB_CB(bf->bf_mpdu);
680 memcpy(info->control.rates, bf->rates,
681 sizeof(info->control.rates));
81b51950 682 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
0c585dda 683 }
81b51950
FF		 684 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
685 } else
686 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
687
73364b0c 688 if (!flush)
81b51950
FF		 689 ath_txq_schedule(sc, txq);
690}
691
1a6e9d0f
RM		 692static bool ath_lookup_legacy(struct ath_buf *bf)
693{
694 struct sk_buff *skb;
695 struct ieee80211_tx_info *tx_info;
696 struct ieee80211_tx_rate *rates;
697 int i;
698
699 skb = bf->bf_mpdu;
700 tx_info = IEEE80211_SKB_CB(skb);
701 rates = tx_info->control.rates;
702
059ee09b
FF		 703 for (i = 0; i < 4; i++) {
704 if (!rates[i].count || rates[i].idx < 0)
705 break;
706
1a6e9d0f
RM		 707 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
708 return true;
709 }
710
711 return false;
712}
713
e8324357
S		 714static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
715 struct ath_atx_tid *tid)
f078f209 716{
528f0c6b
S		 717 struct sk_buff *skb;
718 struct ieee80211_tx_info *tx_info;
a8efee4f 719 struct ieee80211_tx_rate *rates;
d43f3015 720 u32 max_4ms_framelen, frmlen;
c0ac53fa 721 u16 aggr_limit, bt_aggr_limit, legacy = 0;
aa5955c3 722 int q = tid->ac->txq->mac80211_qnum;
e8324357 723 int i;
528f0c6b 724
a22be22a 725 skb = bf->bf_mpdu;
528f0c6b 726 tx_info = IEEE80211_SKB_CB(skb);
0c585dda 727 rates = bf->rates;
528f0c6b 728
e8324357
S		 729 /*
730 * Find the lowest frame length among the rate series that will have a
aa5955c3 731 * 4ms (or TXOP limited) transmit duration.
e8324357
S		 732 */
733 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
e63835b0 734
e8324357 735 for (i = 0; i < 4; i++) {
b0477013 736 int modeidx;
e8324357 737
b0477013
FF		 738 if (!rates[i].count)
739 continue;
545750d3 740
b0477013
FF		 741 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
742 legacy = 1;
743 break;
f078f209 744 }
b0477013
FF		 745
746 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
747 modeidx = MCS_HT40;
748 else
749 modeidx = MCS_HT20;
750
751 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
752 modeidx++;
753
aa5955c3 754 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
b0477013 755 max_4ms_framelen = min(max_4ms_framelen, frmlen);
f078f209 756 }
e63835b0 757
f078f209 758 /*
e8324357
S		 759 * limit aggregate size by the minimum rate if rate selected is
760 * not a probe rate, if rate selected is a probe rate then
761 * avoid aggregation of this packet.
f078f209 762 */
e8324357
S		 763 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
764 return 0;
f078f209 765
c0ac53fa
SM		 766 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
767
768 /*
769 * Override the default aggregation limit for BTCOEX.
770 */
771 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
772 if (bt_aggr_limit)
773 aggr_limit = bt_aggr_limit;
f078f209 774
4ef70841
S		 775 if (tid->an->maxampdu)
776 aggr_limit = min(aggr_limit, tid->an->maxampdu);
f078f209 777
e8324357
S		 778 return aggr_limit;
779}
f078f209 780
e8324357 781/*
d43f3015 782 * Returns the number of delimiters to be added to
e8324357 783 * meet the minimum required mpdudensity.
e8324357
S		 784 */
785static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
7a12dfdb
RM		 786 struct ath_buf *bf, u16 frmlen,
787 bool first_subfrm)
e8324357 788{
7a12dfdb 789#define FIRST_DESC_NDELIMS 60
4ef70841 790 u32 nsymbits, nsymbols;
e8324357 791 u16 minlen;
545750d3 792 u8 flags, rix;
c6663876 793 int width, streams, half_gi, ndelim, mindelim;
2d42efc4 794 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
e8324357
S		 795
796 /* Select standard number of delimiters based on frame length alone */
797 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
f078f209
LR		 798
799 /*
e8324357
S		 800 * If encryption enabled, hardware requires some more padding between
801 * subframes.
802 * TODO - this could be improved to be dependent on the rate.
803 * The hardware can keep up at lower rates, but not higher rates
f078f209 804 */
4f6760b0
RM		 805 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
806 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
e8324357 807 ndelim += ATH_AGGR_ENCRYPTDELIM;
f078f209 808
7a12dfdb
RM		 809 /*
810 * Add delimiter when using RTS/CTS with aggregation
811 * and non enterprise AR9003 card
812 */
3459731a
FF		 813 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
814 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
7a12dfdb
RM		 815 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
816
e8324357
S		 817 /*
818 * Convert desired mpdu density from microeconds to bytes based
819 * on highest rate in rate series (i.e. first rate) to determine
820 * required minimum length for subframe. Take into account
821 * whether high rate is 20 or 40Mhz and half or full GI.
4ef70841 822 *
e8324357
S		 823 * If there is no mpdu density restriction, no further calculation
824 * is needed.
825 */
4ef70841
S		 826
827 if (tid->an->mpdudensity == 0)
e8324357 828 return ndelim;
f078f209 829
79acac07
FF		 830 rix = bf->rates[0].idx;
831 flags = bf->rates[0].flags;
e8324357
S		 832 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
833 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
f078f209 834
e8324357 835 if (half_gi)
4ef70841 836 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
e8324357 837 else
4ef70841 838 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
f078f209 839
e8324357
S		 840 if (nsymbols == 0)
841 nsymbols = 1;
f078f209 842
c6663876
FF		 843 streams = HT_RC_2_STREAMS(rix);
844 nsymbits = bits_per_symbol[rix % 8][width] * streams;
e8324357 845 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
f078f209 846
e8324357 847 if (frmlen < minlen) {
e8324357
S		 848 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
849 ndelim = max(mindelim, ndelim);
f078f209
LR		 850 }
851
e8324357 852 return ndelim;
f078f209
LR		 853}
854
86a22acf
FF		 855static struct ath_buf *
856ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
a7586ee4 857 struct ath_atx_tid *tid, struct sk_buff_head **q)
f078f209 858{
73364b0c 859 struct ieee80211_tx_info *tx_info;
2d42efc4 860 struct ath_frame_info *fi;
56dc6336 861 struct sk_buff *skb;
86a22acf 862 struct ath_buf *bf;
6a0ddaef 863 u16 seqno;
f078f209 864
86a22acf 865 while (1) {
bb195ff6
FF		 866 *q = &tid->retry_q;
867 if (skb_queue_empty(*q))
868 *q = &tid->buf_q;
869
a7586ee4 870 skb = skb_peek(*q);
86a22acf
FF		 871 if (!skb)
872 break;
873
56dc6336
FF		 874 fi = get_frame_info(skb);
875 bf = fi->bf;
44f1d26c 876 if (!fi->bf)
249ee722 877 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
563299d8
FF		 878 else
879 bf->bf_state.stale = false;
56dc6336 880
249ee722 881 if (!bf) {
a7586ee4 882 __skb_unlink(skb, *q);
a4943ccb 883 ath_txq_skb_done(sc, txq, skb);
249ee722 884 ieee80211_free_txskb(sc->hw, skb);
44f1d26c 885 continue;
249ee722 886 }
44f1d26c 887
73364b0c
FF		 888 bf->bf_next = NULL;
889 bf->bf_lastbf = bf;
890
891 tx_info = IEEE80211_SKB_CB(skb);
892 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
893 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
894 bf->bf_state.bf_type = 0;
895 return bf;
896 }
897
399c6489 898 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
44f1d26c 899 seqno = bf->bf_state.seqno;
f078f209 900
d43f3015 901 /* do not step over block-ack window */
86a22acf 902 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
e8324357 903 break;
f078f209 904
f9437543
FF		 905 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
906 struct ath_tx_status ts = {};
907 struct list_head bf_head;
908
909 INIT_LIST_HEAD(&bf_head);
910 list_add(&bf->list, &bf_head);
a7586ee4 911 __skb_unlink(skb, *q);
f9437543
FF		 912 ath_tx_update_baw(sc, tid, seqno);
913 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
914 continue;
915 }
916
86a22acf
FF		 917 return bf;
918 }
919
920 return NULL;
921}
922
2800e82b
FF		 923static bool
924ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
925 struct ath_atx_tid *tid, struct list_head *bf_q,
926 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
927 int *aggr_len)
86a22acf
FF		 928{
929#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
2800e82b 930 struct ath_buf *bf = bf_first, *bf_prev = NULL;
a1cd94d3 931 int nframes = 0, ndelim;
86a22acf 932 u16 aggr_limit = 0, al = 0, bpad = 0,
a1cd94d3 933 al_delta, h_baw = tid->baw_size / 2;
86a22acf
FF		 934 struct ieee80211_tx_info *tx_info;
935 struct ath_frame_info *fi;
936 struct sk_buff *skb;
2800e82b 937 bool closed = false;
86a22acf 938
2800e82b
FF		 939 bf = bf_first;
940 aggr_limit = ath_lookup_rate(sc, bf, tid);
86a22acf 941
2800e82b 942 do {
86a22acf
FF		 943 skb = bf->bf_mpdu;
944 fi = get_frame_info(skb);
945
d43f3015 946 /* do not exceed aggregation limit */
2d42efc4 947 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
a1cd94d3
FF		 948 if (nframes) {
949 if (aggr_limit < al + bpad + al_delta ||
2800e82b 950 ath_lookup_legacy(bf) || nframes >= h_baw)
a1cd94d3 951 break;
f078f209 952
a1cd94d3 953 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
2800e82b
FF		 954 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
955 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
a1cd94d3 956 break;
e8324357 957 }
f078f209 958
d43f3015 959 /* add padding for previous frame to aggregation length */
e8324357 960 al += bpad + al_delta;
f078f209 961
e8324357
S		 962 /*
963 * Get the delimiters needed to meet the MPDU
964 * density for this node.
965 */
7a12dfdb
RM		 966 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
967 !nframes);
e8324357 968 bpad = PADBYTES(al_delta) + (ndelim << 2);
f078f209 969
7a12dfdb 970 nframes++;
e8324357 971 bf->bf_next = NULL;
f078f209 972
d43f3015 973 /* link buffers of this frame to the aggregate */
8fed1408
FF		 974 if (!fi->baw_tracked)
975 ath_tx_addto_baw(sc, tid, bf);
399c6489 976 bf->bf_state.ndelim = ndelim;
56dc6336 977
a7586ee4 978 __skb_unlink(skb, tid_q);
56dc6336 979 list_add_tail(&bf->list, bf_q);
399c6489 980 if (bf_prev)
e8324357 981 bf_prev->bf_next = bf;
399c6489 982
e8324357 983 bf_prev = bf;
fec247c0 984
2800e82b
FF		 985 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
986 if (!bf) {
987 closed = true;
988 break;
989 }
a7586ee4 990 } while (ath_tid_has_buffered(tid));
f078f209 991
2800e82b
FF		 992 bf = bf_first;
993 bf->bf_lastbf = bf_prev;
994
995 if (bf == bf_prev) {
996 al = get_frame_info(bf->bf_mpdu)->framelen;
997 bf->bf_state.bf_type = BUF_AMPDU;
998 } else {
999 TX_STAT_INC(txq->axq_qnum, a_aggr);
1000 }
1001
269c44bc 1002 *aggr_len = al;
d43f3015 1003
2800e82b 1004 return closed;
e8324357
S		 1005#undef PADBYTES
1006}
f078f209 1007
38dad7ba
FF		 1008/*
1009 * rix - rate index
1010 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1011 * width - 0 for 20 MHz, 1 for 40 MHz
1012 * half_gi - to use 4us v/s 3.6 us for symbol time
1013 */
1014static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1015 int width, int half_gi, bool shortPreamble)
1016{
1017 u32 nbits, nsymbits, duration, nsymbols;
1018 int streams;
1019
1020 /* find number of symbols: PLCP + data */
1021 streams = HT_RC_2_STREAMS(rix);
1022 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1023 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1024 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1025
1026 if (!half_gi)
1027 duration = SYMBOL_TIME(nsymbols);
1028 else
1029 duration = SYMBOL_TIME_HALFGI(nsymbols);
1030
1031 /* addup duration for legacy/ht training and signal fields */
1032 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1033
1034 return duration;
1035}
1036
aa5955c3
FF		 1037static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1038{
1039 int streams = HT_RC_2_STREAMS(mcs);
1040 int symbols, bits;
1041 int bytes = 0;
1042
1043 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1044 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1045 bits -= OFDM_PLCP_BITS;
1046 bytes = bits / 8;
1047 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1048 if (bytes > 65532)
1049 bytes = 65532;
1050
1051 return bytes;
1052}
1053
1054void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1055{
1056 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1057 int mcs;
1058
1059 /* 4ms is the default (and maximum) duration */
1060 if (!txop || txop > 4096)
1061 txop = 4096;
1062
1063 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1064 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1065 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1066 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1067 for (mcs = 0; mcs < 32; mcs++) {
1068 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1069 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1070 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1071 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1072 }
1073}
1074
493cf04f 1075static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
a3835e9f 1076 struct ath_tx_info *info, int len, bool rts)
38dad7ba
FF		 1077{
1078 struct ath_hw *ah = sc->sc_ah;
38dad7ba
FF		 1079 struct sk_buff *skb;
1080 struct ieee80211_tx_info *tx_info;
1081 struct ieee80211_tx_rate *rates;
1082 const struct ieee80211_rate *rate;
1083 struct ieee80211_hdr *hdr;
80b08a8d 1084 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
a3835e9f 1085 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
493cf04f
FF		 1086 int i;
1087 u8 rix = 0;
38dad7ba
FF		 1088
1089 skb = bf->bf_mpdu;
1090 tx_info = IEEE80211_SKB_CB(skb);
79acac07 1091 rates = bf->rates;
38dad7ba 1092 hdr = (struct ieee80211_hdr *)skb->data;
493cf04f
FF		 1093
1094 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1095 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
80b08a8d 1096 info->rtscts_rate = fi->rtscts_rate;
38dad7ba 1097
79acac07 1098 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
38dad7ba
FF		 1099 bool is_40, is_sgi, is_sp;
1100 int phy;
1101
1102 if (!rates[i].count || (rates[i].idx < 0))
1103 continue;
1104
1105 rix = rates[i].idx;
493cf04f 1106 info->rates[i].Tries = rates[i].count;
38dad7ba 1107
a3835e9f
SM		 1108 /*
1109 * Handle RTS threshold for unaggregated HT frames.
1110 */
1111 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1112 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1113 unlikely(rts_thresh != (u32) -1)) {
1114 if (!rts_thresh || (len > rts_thresh))
1115 rts = true;
1116 }
1117
1118 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
493cf04f
FF		 1119 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1120 info->flags |= ATH9K_TXDESC_RTSENA;
38dad7ba 1121 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
493cf04f
FF		 1122 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1123 info->flags |= ATH9K_TXDESC_CTSENA;
38dad7ba
FF		 1124 }
1125
1126 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
493cf04f 1127 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
38dad7ba 1128 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
493cf04f 1129 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
38dad7ba
FF		 1130
1131 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1132 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1133 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1134
1135 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1136 /* MCS rates */
493cf04f
FF		 1137 info->rates[i].Rate = rix | 0x80;
1138 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1139 ah->txchainmask, info->rates[i].Rate);
1140 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
38dad7ba
FF		 1141 is_40, is_sgi, is_sp);
1142 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
493cf04f 1143 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
38dad7ba
FF		 1144 continue;
1145 }
1146
1147 /* legacy rates */
76591bea 1148 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
38dad7ba
FF		 1149 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1150 !(rate->flags & IEEE80211_RATE_ERP_G))
1151 phy = WLAN_RC_PHY_CCK;
1152 else
1153 phy = WLAN_RC_PHY_OFDM;
1154
493cf04f 1155 info->rates[i].Rate = rate->hw_value;
38dad7ba
FF		 1156 if (rate->hw_value_short) {
1157 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
493cf04f 1158 info->rates[i].Rate |= rate->hw_value_short;
38dad7ba
FF		 1159 } else {
1160 is_sp = false;
1161 }
1162
1163 if (bf->bf_state.bfs_paprd)
493cf04f 1164 info->rates[i].ChSel = ah->txchainmask;
38dad7ba 1165 else
493cf04f
FF		 1166 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1167 ah->txchainmask, info->rates[i].Rate);
38dad7ba 1168
493cf04f 1169 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
38dad7ba
FF		 1170 phy, rate->bitrate * 100, len, rix, is_sp);
1171 }
1172
1173 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1174 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
493cf04f 1175 info->flags &= ~ATH9K_TXDESC_RTSENA;
38dad7ba
FF		 1176
1177 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
493cf04f
FF		 1178 if (info->flags & ATH9K_TXDESC_RTSENA)
1179 info->flags &= ~ATH9K_TXDESC_CTSENA;
1180}
38dad7ba 1181
493cf04f
FF		 1182static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1183{
1184 struct ieee80211_hdr *hdr;
1185 enum ath9k_pkt_type htype;
1186 __le16 fc;
1187
1188 hdr = (struct ieee80211_hdr *)skb->data;
1189 fc = hdr->frame_control;
38dad7ba 1190
493cf04f
FF		 1191 if (ieee80211_is_beacon(fc))
1192 htype = ATH9K_PKT_TYPE_BEACON;
1193 else if (ieee80211_is_probe_resp(fc))
1194 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1195 else if (ieee80211_is_atim(fc))
1196 htype = ATH9K_PKT_TYPE_ATIM;
1197 else if (ieee80211_is_pspoll(fc))
1198 htype = ATH9K_PKT_TYPE_PSPOLL;
1199 else
1200 htype = ATH9K_PKT_TYPE_NORMAL;
1201
1202 return htype;
38dad7ba
FF		 1203}
1204
493cf04f
FF		 1205static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1206 struct ath_txq *txq, int len)
399c6489
FF		 1207{
1208 struct ath_hw *ah = sc->sc_ah;
86a22acf 1209 struct ath_buf *bf_first = NULL;
493cf04f 1210 struct ath_tx_info info;
a3835e9f
SM		 1211 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1212 bool rts = false;
399c6489 1213
493cf04f
FF		 1214 memset(&info, 0, sizeof(info));
1215 info.is_first = true;
1216 info.is_last = true;
1217 info.txpower = MAX_RATE_POWER;
1218 info.qcu = txq->axq_qnum;
1219
399c6489 1220 while (bf) {
493cf04f 1221 struct sk_buff *skb = bf->bf_mpdu;
86a22acf 1222 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
493cf04f 1223 struct ath_frame_info *fi = get_frame_info(skb);
86a22acf 1224 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
493cf04f
FF		 1225
1226 info.type = get_hw_packet_type(skb);
399c6489 1227 if (bf->bf_next)
493cf04f 1228 info.link = bf->bf_next->bf_daddr;
399c6489 1229 else
89f927af 1230 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
493cf04f 1231
86a22acf
FF		 1232 if (!bf_first) {
1233 bf_first = bf;
1234
89f927af
LR		 1235 if (!sc->tx99_state)
1236 info.flags = ATH9K_TXDESC_INTREQ;
86a22acf
FF		 1237 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1238 txq == sc->tx.uapsdq)
1239 info.flags |= ATH9K_TXDESC_CLRDMASK;
1240
1241 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1242 info.flags |= ATH9K_TXDESC_NOACK;
1243 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1244 info.flags |= ATH9K_TXDESC_LDPC;
1245
1246 if (bf->bf_state.bfs_paprd)
1247 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1248 ATH9K_TXDESC_PAPRD_S;
1249
a3835e9f
SM		 1250 /*
1251 * mac80211 doesn't handle RTS threshold for HT because
1252 * the decision has to be taken based on AMPDU length
1253 * and aggregation is done entirely inside ath9k.
1254 * Set the RTS/CTS flag for the first subframe based
1255 * on the threshold.
1256 */
1257 if (aggr && (bf == bf_first) &&
1258 unlikely(rts_thresh != (u32) -1)) {
1259 /*
1260 * "len" is the size of the entire AMPDU.
1261 */
1262 if (!rts_thresh || (len > rts_thresh))
1263 rts = true;
1264 }
bbf807bc
FF		 1265
1266 if (!aggr)
1267 len = fi->framelen;
1268
a3835e9f 1269 ath_buf_set_rate(sc, bf, &info, len, rts);
86a22acf
FF		 1270 }
1271
42cecc34
JL		 1272 info.buf_addr[0] = bf->bf_buf_addr;
1273 info.buf_len[0] = skb->len;
493cf04f
FF		 1274 info.pkt_len = fi->framelen;
1275 info.keyix = fi->keyix;
1276 info.keytype = fi->keytype;
1277
1278 if (aggr) {
399c6489 1279 if (bf == bf_first)
493cf04f 1280 info.aggr = AGGR_BUF_FIRST;
86a22acf 1281 else if (bf == bf_first->bf_lastbf)
493cf04f
FF		 1282 info.aggr = AGGR_BUF_LAST;
1283 else
1284 info.aggr = AGGR_BUF_MIDDLE;
399c6489 1285
493cf04f
FF		 1286 info.ndelim = bf->bf_state.ndelim;
1287 info.aggr_len = len;
399c6489
FF		 1288 }
1289
86a22acf
FF		 1290 if (bf == bf_first->bf_lastbf)
1291 bf_first = NULL;
1292
493cf04f 1293 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
399c6489
FF		 1294 bf = bf->bf_next;
1295 }
1296}
1297
2800e82b
FF		 1298static void
1299ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1300 struct ath_atx_tid *tid, struct list_head *bf_q,
1301 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1302{
1303 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1304 struct sk_buff *skb;
1305 int nframes = 0;
1306
1307 do {
1308 struct ieee80211_tx_info *tx_info;
1309 skb = bf->bf_mpdu;
1310
1311 nframes++;
1312 __skb_unlink(skb, tid_q);
1313 list_add_tail(&bf->list, bf_q);
1314 if (bf_prev)
1315 bf_prev->bf_next = bf;
1316 bf_prev = bf;
1317
1318 if (nframes >= 2)
1319 break;
1320
1321 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1322 if (!bf)
1323 break;
1324
1325 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1326 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1327 break;
1328
1329 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1330 } while (1);
1331}
1332
020f20f6
FF		 1333static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1334 struct ath_atx_tid *tid, bool *stop)
e8324357 1335{
d43f3015 1336 struct ath_buf *bf;
399c6489 1337 struct ieee80211_tx_info *tx_info;
2800e82b 1338 struct sk_buff_head *tid_q;
e8324357 1339 struct list_head bf_q;
2800e82b
FF		 1340 int aggr_len = 0;
1341 bool aggr, last = true;
f078f209 1342
020f20f6
FF		 1343 if (!ath_tid_has_buffered(tid))
1344 return false;
f078f209 1345
020f20f6 1346 INIT_LIST_HEAD(&bf_q);
e8324357 1347
020f20f6
FF		 1348 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1349 if (!bf)
1350 return false;
f078f209 1351
020f20f6
FF		 1352 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1353 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1354 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1355 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1356 *stop = true;
1357 return false;
1358 }
2800e82b 1359
020f20f6
FF		 1360 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1361 if (aggr)
1362 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1363 tid_q, &aggr_len);
1364 else
1365 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
2800e82b 1366
020f20f6
FF		 1367 if (list_empty(&bf_q))
1368 return false;
f078f209 1369
f89d1bc4 1370 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
020f20f6
FF		 1371 tid->ac->clear_ps_filter = false;
1372 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1373 }
f078f209 1374
020f20f6
FF		 1375 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1376 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1377 return true;
e8324357
S		 1378}
1379
231c3a1f
FF		 1380int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1381 u16 tid, u16 *ssn)
e8324357
S		 1382{
1383 struct ath_atx_tid *txtid;
919123d2 1384 struct ath_txq *txq;
e8324357 1385 struct ath_node *an;
313eb87f 1386 u8 density;
e8324357
S		 1387
1388 an = (struct ath_node *)sta->drv_priv;
f83da965 1389 txtid = ATH_AN_2_TID(an, tid);
919123d2
FF		 1390 txq = txtid->ac->txq;
1391
1392 ath_txq_lock(sc, txq);
231c3a1f 1393
313eb87f
SE		 1394 /* update ampdu factor/density, they may have changed. This may happen
1395 * in HT IBSS when a beacon with HT-info is received after the station
1396 * has already been added.
1397 */
dd5ee59b 1398 if (sta->ht_cap.ht_supported) {
5b502c86
SM		 1399 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1400 sta->ht_cap.ampdu_factor)) - 1;
313eb87f
SE		 1401 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1402 an->mpdudensity = density;
1403 }
1404
2800e82b
FF		 1405 /* force sequence number allocation for pending frames */
1406 ath_tx_tid_change_state(sc, txtid);
1407
08c96abd 1408 txtid->active = true;
75401849 1409 txtid->paused = true;
49447f2f 1410 *ssn = txtid->seq_start = txtid->seq_next;
f9437543 1411 txtid->bar_index = -1;
231c3a1f 1412
2ed72229
FF		 1413 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1414 txtid->baw_head = txtid->baw_tail = 0;
1415
919123d2
FF		 1416 ath_txq_unlock_complete(sc, txq);
1417
231c3a1f 1418 return 0;
e8324357 1419}
f078f209 1420
08c96abd 1421void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
e8324357
S		 1422{
1423 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1424 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
066dae93 1425 struct ath_txq *txq = txtid->ac->txq;
f078f209 1426
23de5dc9 1427 ath_txq_lock(sc, txq);
08c96abd 1428 txtid->active = false;
73364b0c 1429 txtid->paused = false;
08c96abd 1430 ath_tx_flush_tid(sc, txtid);
2800e82b 1431 ath_tx_tid_change_state(sc, txtid);
23de5dc9 1432 ath_txq_unlock_complete(sc, txq);
e8324357 1433}
f078f209 1434
042ec453
JB		 1435void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1436 struct ath_node *an)
5519541d
FF		 1437{
1438 struct ath_atx_tid *tid;
1439 struct ath_atx_ac *ac;
1440 struct ath_txq *txq;
042ec453 1441 bool buffered;
5519541d
FF		 1442 int tidno;
1443
1444 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1445 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d 1446
5519541d
FF		 1447 ac = tid->ac;
1448 txq = ac->txq;
1449
23de5dc9 1450 ath_txq_lock(sc, txq);
5519541d 1451
21f8aaee
SG		 1452 if (!tid->sched) {
1453 ath_txq_unlock(sc, txq);
1454 continue;
1455 }
1456
a7586ee4 1457 buffered = ath_tid_has_buffered(tid);
5519541d
FF		 1458
1459 tid->sched = false;
1460 list_del(&tid->list);
1461
1462 if (ac->sched) {
1463 ac->sched = false;
1464 list_del(&ac->list);
1465 }
1466
23de5dc9 1467 ath_txq_unlock(sc, txq);
5519541d 1468
042ec453
JB		 1469 ieee80211_sta_set_buffered(sta, tidno, buffered);
1470 }
5519541d
FF		 1471}
1472
1473void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1474{
1475 struct ath_atx_tid *tid;
1476 struct ath_atx_ac *ac;
1477 struct ath_txq *txq;
1478 int tidno;
1479
1480 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1481 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d
FF		 1482
1483 ac = tid->ac;
1484 txq = ac->txq;
1485
23de5dc9 1486 ath_txq_lock(sc, txq);
5519541d
FF		 1487 ac->clear_ps_filter = true;
1488
a7586ee4 1489 if (!tid->paused && ath_tid_has_buffered(tid)) {
5519541d
FF		 1490 ath_tx_queue_tid(txq, tid);
1491 ath_txq_schedule(sc, txq);
1492 }
1493
23de5dc9 1494 ath_txq_unlock_complete(sc, txq);
5519541d
FF		 1495 }
1496}
1497
08c96abd
FF		 1498void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1499 u16 tidno)
e8324357 1500{
08c96abd 1501 struct ath_atx_tid *tid;
e8324357 1502 struct ath_node *an;
08c96abd 1503 struct ath_txq *txq;
e8324357
S		 1504
1505 an = (struct ath_node *)sta->drv_priv;
08c96abd
FF		 1506 tid = ATH_AN_2_TID(an, tidno);
1507 txq = tid->ac->txq;
e8324357 1508
08c96abd
FF		 1509 ath_txq_lock(sc, txq);
1510
1511 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1512 tid->paused = false;
1513
a7586ee4 1514 if (ath_tid_has_buffered(tid)) {
08c96abd
FF		 1515 ath_tx_queue_tid(txq, tid);
1516 ath_txq_schedule(sc, txq);
1517 }
1518
1519 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1520}
1521
86a22acf
FF		 1522void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1523 struct ieee80211_sta *sta,
1524 u16 tids, int nframes,
1525 enum ieee80211_frame_release_type reason,
1526 bool more_data)
1527{
1528 struct ath_softc *sc = hw->priv;
1529 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1530 struct ath_txq *txq = sc->tx.uapsdq;
1531 struct ieee80211_tx_info *info;
1532 struct list_head bf_q;
1533 struct ath_buf *bf_tail = NULL, *bf;
a7586ee4 1534 struct sk_buff_head *tid_q;
86a22acf
FF		 1535 int sent = 0;
1536 int i;
1537
1538 INIT_LIST_HEAD(&bf_q);
1539 for (i = 0; tids && nframes; i++, tids >>= 1) {
1540 struct ath_atx_tid *tid;
1541
1542 if (!(tids & 1))
1543 continue;
1544
1545 tid = ATH_AN_2_TID(an, i);
1546 if (tid->paused)
1547 continue;
1548
1549 ath_txq_lock(sc, tid->ac->txq);
a7586ee4
FF		 1550 while (nframes > 0) {
1551 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
86a22acf
FF		 1552 if (!bf)
1553 break;
1554
a7586ee4 1555 __skb_unlink(bf->bf_mpdu, tid_q);
86a22acf
FF		 1556 list_add_tail(&bf->list, &bf_q);
1557 ath_set_rates(tid->an->vif, tid->an->sta, bf);
20e6e55a
FF		 1558 if (bf_isampdu(bf)) {
1559 ath_tx_addto_baw(sc, tid, bf);
1560 bf->bf_state.bf_type &= ~BUF_AGGR;
1561 }
86a22acf
FF		 1562 if (bf_tail)
1563 bf_tail->bf_next = bf;
1564
1565 bf_tail = bf;
1566 nframes--;
1567 sent++;
1568 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1569
f89d1bc4 1570 if (an->sta && !ath_tid_has_buffered(tid))
86a22acf
FF		 1571 ieee80211_sta_set_buffered(an->sta, i, false);
1572 }
1573 ath_txq_unlock_complete(sc, tid->ac->txq);
1574 }
1575
1576 if (list_empty(&bf_q))
1577 return;
1578
1579 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1580 info->flags |= IEEE80211_TX_STATUS_EOSP;
1581
1582 bf = list_first_entry(&bf_q, struct ath_buf, list);
1583 ath_txq_lock(sc, txq);
1584 ath_tx_fill_desc(sc, bf, txq, 0);
1585 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1586 ath_txq_unlock(sc, txq);
1587}
1588
e8324357
S		 1589/********************/
1590/* Queue Management */
1591/********************/
f078f209 1592
e8324357 1593struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
f078f209 1594{
cbe61d8a 1595 struct ath_hw *ah = sc->sc_ah;
e8324357 1596 struct ath9k_tx_queue_info qi;
066dae93 1597 static const int subtype_txq_to_hwq[] = {
bea843c7
SM		 1598 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1599 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1600 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1601 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
066dae93 1602 };
60f2d1d5 1603 int axq_qnum, i;
f078f209 1604
e8324357 1605 memset(&qi, 0, sizeof(qi));
066dae93 1606 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
e8324357
S		 1607 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1608 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1609 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1610 qi.tqi_physCompBuf = 0;
f078f209
LR		 1611
1612 /*
e8324357
S		 1613 * Enable interrupts only for EOL and DESC conditions.
1614 * We mark tx descriptors to receive a DESC interrupt
1615 * when a tx queue gets deep; otherwise waiting for the
1616 * EOL to reap descriptors. Note that this is done to
1617 * reduce interrupt load and this only defers reaping
1618 * descriptors, never transmitting frames. Aside from
1619 * reducing interrupts this also permits more concurrency.
1620 * The only potential downside is if the tx queue backs
1621 * up in which case the top half of the kernel may backup
1622 * due to a lack of tx descriptors.
1623 *
1624 * The UAPSD queue is an exception, since we take a desc-
1625 * based intr on the EOSP frames.
f078f209 1626 */
afe754d6 1627 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
ce8fdf6e 1628 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
afe754d6
VT		 1629 } else {
1630 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1631 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1632 else
1633 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1634 TXQ_FLAG_TXDESCINT_ENABLE;
1635 }
60f2d1d5
BG		 1636 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1637 if (axq_qnum == -1) {
f078f209 1638 /*
e8324357
S		 1639 * NB: don't print a message, this happens
1640 * normally on parts with too few tx queues
f078f209 1641 */
e8324357 1642 return NULL;
f078f209 1643 }
60f2d1d5
BG		 1644 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1645 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
f078f209 1646
60f2d1d5
BG		 1647 txq->axq_qnum = axq_qnum;
1648 txq->mac80211_qnum = -1;
e8324357 1649 txq->axq_link = NULL;
23de5dc9 1650 __skb_queue_head_init(&txq->complete_q);
e8324357
S		 1651 INIT_LIST_HEAD(&txq->axq_q);
1652 INIT_LIST_HEAD(&txq->axq_acq);
1653 spin_lock_init(&txq->axq_lock);
1654 txq->axq_depth = 0;
4b3ba66a 1655 txq->axq_ampdu_depth = 0;
164ace38 1656 txq->axq_tx_inprogress = false;
60f2d1d5 1657 sc->tx.txqsetup |= 1<<axq_qnum;
e5003249
VT		 1658
1659 txq->txq_headidx = txq->txq_tailidx = 0;
1660 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1661 INIT_LIST_HEAD(&txq->txq_fifo[i]);
e8324357 1662 }
60f2d1d5 1663 return &sc->tx.txq[axq_qnum];
f078f209
LR		 1664}
1665
e8324357
S		 1666int ath_txq_update(struct ath_softc *sc, int qnum,
1667 struct ath9k_tx_queue_info *qinfo)
1668{
cbe61d8a 1669 struct ath_hw *ah = sc->sc_ah;
e8324357
S		 1670 int error = 0;
1671 struct ath9k_tx_queue_info qi;
1672
9680e8a3 1673 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
e8324357
S		 1674
1675 ath9k_hw_get_txq_props(ah, qnum, &qi);
1676 qi.tqi_aifs = qinfo->tqi_aifs;
1677 qi.tqi_cwmin = qinfo->tqi_cwmin;
1678 qi.tqi_cwmax = qinfo->tqi_cwmax;
1679 qi.tqi_burstTime = qinfo->tqi_burstTime;
1680 qi.tqi_readyTime = qinfo->tqi_readyTime;
1681
1682 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
3800276a
JP		 1683 ath_err(ath9k_hw_common(sc->sc_ah),
1684 "Unable to update hardware queue %u!\n", qnum);
e8324357
S		 1685 error = -EIO;
1686 } else {
1687 ath9k_hw_resettxqueue(ah, qnum);
1688 }
1689
1690 return error;
1691}
1692
1693int ath_cabq_update(struct ath_softc *sc)
1694{
1695 struct ath9k_tx_queue_info qi;
9814f6b3 1696 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
e8324357 1697 int qnum = sc->beacon.cabq->axq_qnum;
f078f209 1698
e8324357 1699 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
f078f209 1700
9814f6b3 1701 qi.tqi_readyTime = (cur_conf->beacon_interval *
7f329bbb 1702 ATH_CABQ_READY_TIME) / 100;
e8324357
S		 1703 ath_txq_update(sc, qnum, &qi);
1704
1705 return 0;
f078f209
LR		 1706}
1707
fce041be 1708static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1381559b 1709 struct list_head *list)
f078f209 1710{
e8324357
S		 1711 struct ath_buf *bf, *lastbf;
1712 struct list_head bf_head;
db1a052b
FF		 1713 struct ath_tx_status ts;
1714
1715 memset(&ts, 0, sizeof(ts));
daa5c408 1716 ts.ts_status = ATH9K_TX_FLUSH;
e8324357 1717 INIT_LIST_HEAD(&bf_head);
f078f209 1718
fce041be
FF		 1719 while (!list_empty(list)) {
1720 bf = list_first_entry(list, struct ath_buf, list);
f078f209 1721
50676b81 1722 if (bf->bf_state.stale) {
fce041be 1723 list_del(&bf->list);
f078f209 1724
fce041be
FF		 1725 ath_tx_return_buffer(sc, bf);
1726 continue;
e8324357 1727 }
f078f209 1728
e8324357 1729 lastbf = bf->bf_lastbf;
fce041be 1730 list_cut_position(&bf_head, list, &lastbf->list);
81b51950 1731 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
f078f209 1732 }
fce041be 1733}
f078f209 1734
fce041be
FF		 1735/*
1736 * Drain a given TX queue (could be Beacon or Data)
1737 *
1738 * This assumes output has been stopped and
1739 * we do not need to block ath_tx_tasklet.
1740 */
1381559b 1741void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
fce041be 1742{
23de5dc9
FF		 1743 ath_txq_lock(sc, txq);
1744
e5003249 1745 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
fce041be 1746 int idx = txq->txq_tailidx;
e5003249 1747
fce041be 1748 while (!list_empty(&txq->txq_fifo[idx])) {
1381559b 1749 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
fce041be
FF		 1750
1751 INCR(idx, ATH_TXFIFO_DEPTH);
e5003249 1752 }
fce041be 1753 txq->txq_tailidx = idx;
e5003249 1754 }
e609e2ea 1755
fce041be
FF		 1756 txq->axq_link = NULL;
1757 txq->axq_tx_inprogress = false;
1381559b 1758 ath_drain_txq_list(sc, txq, &txq->axq_q);
fce041be 1759
23de5dc9 1760 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1761}
1762
1381559b 1763bool ath_drain_all_txq(struct ath_softc *sc)
f078f209 1764{
cbe61d8a 1765 struct ath_hw *ah = sc->sc_ah;
c46917bb 1766 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
043a0405 1767 struct ath_txq *txq;
34d25810
FF		 1768 int i;
1769 u32 npend = 0;
043a0405 1770
781b14a3 1771 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
080e1a25 1772 return true;
043a0405 1773
0d51cccc 1774 ath9k_hw_abort_tx_dma(ah);
043a0405 1775
0d51cccc 1776 /* Check if any queue remains active */
043a0405 1777 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
0d51cccc
FF		 1778 if (!ATH_TXQ_SETUP(sc, i))
1779 continue;
1780
10ffb6a7
FF		 1781 if (!sc->tx.txq[i].axq_depth)
1782 continue;
1783
34d25810
FF		 1784 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1785 npend |= BIT(i);
043a0405
S		 1786 }
1787
080e1a25 1788 if (npend)
34d25810 1789 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
043a0405
S		 1790
1791 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
92460412
FF		 1792 if (!ATH_TXQ_SETUP(sc, i))
1793 continue;
1794
1795 /*
1796 * The caller will resume queues with ieee80211_wake_queues.
1797 * Mark the queue as not stopped to prevent ath_tx_complete
1798 * from waking the queue too early.
1799 */
1800 txq = &sc->tx.txq[i];
1801 txq->stopped = false;
1381559b 1802 ath_draintxq(sc, txq);
043a0405 1803 }
080e1a25
FF		 1804
1805 return !npend;
e8324357 1806}
f078f209 1807
043a0405 1808void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
e8324357 1809{
043a0405
S		 1810 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1811 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
e8324357 1812}
f078f209 1813
7755bad9
BG		 1814/* For each axq_acq entry, for each tid, try to schedule packets
1815 * for transmit until ampdu_depth has reached min Q depth.
1816 */
e8324357
S		 1817void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1818{
020f20f6 1819 struct ath_atx_ac *ac, *last_ac;
7755bad9 1820 struct ath_atx_tid *tid, *last_tid;
020f20f6 1821 bool sent = false;
f078f209 1822
124b979b 1823 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
020f20f6 1824 list_empty(&txq->axq_acq))
e8324357 1825 return;
f078f209 1826
23bc2021
FF		 1827 rcu_read_lock();
1828
7755bad9 1829 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
020f20f6
FF		 1830 while (!list_empty(&txq->axq_acq)) {
1831 bool stop = false;
f078f209 1832
020f20f6 1833 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
7755bad9
BG		 1834 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1835 list_del(&ac->list);
1836 ac->sched = false;
f078f209 1837
7755bad9 1838 while (!list_empty(&ac->tid_q)) {
020f20f6 1839
7755bad9
BG		 1840 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1841 list);
1842 list_del(&tid->list);
1843 tid->sched = false;
f078f209 1844
7755bad9
BG		 1845 if (tid->paused)
1846 continue;
f078f209 1847
020f20f6
FF		 1848 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1849 sent = true;
f078f209 1850
7755bad9
BG		 1851 /*
1852 * add tid to round-robin queue if more frames
1853 * are pending for the tid
1854 */
a7586ee4 1855 if (ath_tid_has_buffered(tid))
7755bad9 1856 ath_tx_queue_tid(txq, tid);
f078f209 1857
020f20f6 1858 if (stop || tid == last_tid)
7755bad9
BG		 1859 break;
1860 }
f078f209 1861
b0477013
FF		 1862 if (!list_empty(&ac->tid_q) && !ac->sched) {
1863 ac->sched = true;
1864 list_add_tail(&ac->list, &txq->axq_acq);
f078f209 1865 }
7755bad9 1866
020f20f6 1867 if (stop)
23bc2021 1868 break;
020f20f6
FF		 1869
1870 if (ac == last_ac) {
1871 if (!sent)
1872 break;
1873
1874 sent = false;
1875 last_ac = list_entry(txq->axq_acq.prev,
1876 struct ath_atx_ac, list);
1877 }
e8324357 1878 }
23bc2021
FF		 1879
1880 rcu_read_unlock();
e8324357 1881}
f078f209 1882
e8324357
S		 1883/***********/
1884/* TX, DMA */
1885/***********/
1886
f078f209 1887/*
e8324357
S		 1888 * Insert a chain of ath_buf (descriptors) on a txq and
1889 * assume the descriptors are already chained together by caller.
f078f209 1890 */
e8324357 1891static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 1892 struct list_head *head, bool internal)
f078f209 1893{
cbe61d8a 1894 struct ath_hw *ah = sc->sc_ah;
c46917bb 1895 struct ath_common *common = ath9k_hw_common(ah);
fce041be
FF		 1896 struct ath_buf *bf, *bf_last;
1897 bool puttxbuf = false;
1898 bool edma;
f078f209 1899
e8324357
S		 1900 /*
1901 * Insert the frame on the outbound list and
1902 * pass it on to the hardware.
1903 */
f078f209 1904
e8324357
S		 1905 if (list_empty(head))
1906 return;
f078f209 1907
fce041be 1908 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
e8324357 1909 bf = list_first_entry(head, struct ath_buf, list);
fce041be 1910 bf_last = list_entry(head->prev, struct ath_buf, list);
f078f209 1911
d2182b69
JP		 1912 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1913 txq->axq_qnum, txq->axq_depth);
f078f209 1914
fce041be
FF		 1915 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1916 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
e5003249 1917 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
fce041be 1918 puttxbuf = true;
e8324357 1919 } else {
e5003249
VT		 1920 list_splice_tail_init(head, &txq->axq_q);
1921
fce041be
FF		 1922 if (txq->axq_link) {
1923 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
d2182b69 1924 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
226afe68
JP		 1925 txq->axq_qnum, txq->axq_link,
1926 ito64(bf->bf_daddr), bf->bf_desc);
fce041be
FF		 1927 } else if (!edma)
1928 puttxbuf = true;
1929
1930 txq->axq_link = bf_last->bf_desc;
1931 }
1932
1933 if (puttxbuf) {
1934 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1935 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
d2182b69 1936 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
fce041be
FF		 1937 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1938 }
1939
89f927af 1940 if (!edma || sc->tx99_state) {
8d8d3fdc 1941 TX_STAT_INC(txq->axq_qnum, txstart);
e5003249 1942 ath9k_hw_txstart(ah, txq->axq_qnum);
e8324357 1943 }
fce041be
FF		 1944
1945 if (!internal) {
f56e121d
FF		 1946 while (bf) {
1947 txq->axq_depth++;
1948 if (bf_is_ampdu_not_probing(bf))
1949 txq->axq_ampdu_depth++;
1950
440c1c87
FF		 1951 bf_last = bf->bf_lastbf;
1952 bf = bf_last->bf_next;
1953 bf_last->bf_next = NULL;
f56e121d 1954 }
fce041be 1955 }
e8324357 1956}
f078f209 1957
82b873af 1958static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c 1959 struct ath_atx_tid *tid, struct sk_buff *skb)
e8324357 1960{
f69727fd 1961 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
44f1d26c
FF		 1962 struct ath_frame_info *fi = get_frame_info(skb);
1963 struct list_head bf_head;
f69727fd 1964 struct ath_buf *bf = fi->bf;
44f1d26c
FF		 1965
1966 INIT_LIST_HEAD(&bf_head);
1967 list_add_tail(&bf->list, &bf_head);
399c6489 1968 bf->bf_state.bf_type = 0;
f69727fd
FF		 1969 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1970 bf->bf_state.bf_type = BUF_AMPDU;
1971 ath_tx_addto_baw(sc, tid, bf);
1972 }
e8324357 1973
8c6e3093 1974 bf->bf_next = NULL;
d43f3015 1975 bf->bf_lastbf = bf;
493cf04f 1976 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
44f1d26c 1977 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
fec247c0 1978 TX_STAT_INC(txq->axq_qnum, queued);
e8324357
S		 1979}
1980
36323f81
TH		 1981static void setup_frame_info(struct ieee80211_hw *hw,
1982 struct ieee80211_sta *sta,
1983 struct sk_buff *skb,
2d42efc4 1984 int framelen)
e8324357
S		 1985{
1986 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 1987 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
6a0ddaef 1988 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
80b08a8d 1989 const struct ieee80211_rate *rate;
2d42efc4 1990 struct ath_frame_info *fi = get_frame_info(skb);
93ae2dd2 1991 struct ath_node *an = NULL;
2d42efc4 1992 enum ath9k_key_type keytype;
80b08a8d
FF		 1993 bool short_preamble = false;
1994
1995 /*
1996 * We check if Short Preamble is needed for the CTS rate by
1997 * checking the BSS's global flag.
1998 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1999 */
2000 if (tx_info->control.vif &&
2001 tx_info->control.vif->bss_conf.use_short_preamble)
2002 short_preamble = true;
e8324357 2003
80b08a8d 2004 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2d42efc4 2005 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
e8324357 2006
93ae2dd2
FF		 2007 if (sta)
2008 an = (struct ath_node *) sta->drv_priv;
2009
2d42efc4
FF		 2010 memset(fi, 0, sizeof(*fi));
2011 if (hw_key)
2012 fi->keyix = hw_key->hw_key_idx;
93ae2dd2
FF		 2013 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2014 fi->keyix = an->ps_key;
2d42efc4
FF		 2015 else
2016 fi->keyix = ATH9K_TXKEYIX_INVALID;
2017 fi->keytype = keytype;
2018 fi->framelen = framelen;
09b029b6
LR		 2019
2020 if (!rate)
2021 return;
80b08a8d
FF		 2022 fi->rtscts_rate = rate->hw_value;
2023 if (short_preamble)
2024 fi->rtscts_rate |= rate->hw_value_short;
e8324357
S		 2025}
2026
ea066d5a
MSS		 2027u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2028{
2029 struct ath_hw *ah = sc->sc_ah;
2030 struct ath9k_channel *curchan = ah->curchan;
365d2ebc 2031
8896934c 2032 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
d77bf3eb 2033 (chainmask == 0x7) && (rate < 0x90))
ea066d5a 2034 return 0x3;
365d2ebc
SM		 2035 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2036 IS_CCK_RATE(rate))
2037 return 0x2;
ea066d5a
MSS		 2038 else
2039 return chainmask;
2040}
2041
44f1d26c
FF		 2042/*
2043 * Assign a descriptor (and sequence number if necessary,
2044 * and map buffer for DMA. Frees skb on error
2045 */
fa05f87a 2046static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
04caf863 2047 struct ath_txq *txq,
fa05f87a 2048 struct ath_atx_tid *tid,
249ee722 2049 struct sk_buff *skb)
f078f209 2050{
82b873af 2051 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2d42efc4 2052 struct ath_frame_info *fi = get_frame_info(skb);
fa05f87a 2053 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
82b873af 2054 struct ath_buf *bf;
fd09c85f 2055 int fragno;
fa05f87a 2056 u16 seqno;
82b873af
FF		 2057
2058 bf = ath_tx_get_buffer(sc);
2059 if (!bf) {
d2182b69 2060 ath_dbg(common, XMIT, "TX buffers are full\n");
249ee722 2061 return NULL;
82b873af 2062 }
e022edbd 2063
528f0c6b 2064 ATH_TXBUF_RESET(bf);
f078f209 2065
fa05f87a 2066 if (tid) {
fd09c85f 2067 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
fa05f87a
FF		 2068 seqno = tid->seq_next;
2069 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
fd09c85f
SM		 2070
2071 if (fragno)
2072 hdr->seq_ctrl |= cpu_to_le16(fragno);
2073
2074 if (!ieee80211_has_morefrags(hdr->frame_control))
2075 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2076
fa05f87a
FF		 2077 bf->bf_state.seqno = seqno;
2078 }
2079
f078f209 2080 bf->bf_mpdu = skb;
f8316df1 2081
c1739eb3
BG		 2082 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2083 skb->len, DMA_TO_DEVICE);
2084 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
f8316df1 2085 bf->bf_mpdu = NULL;
6cf9e995 2086 bf->bf_buf_addr = 0;
3800276a
JP		 2087 ath_err(ath9k_hw_common(sc->sc_ah),
2088 "dma_mapping_error() on TX\n");
82b873af 2089 ath_tx_return_buffer(sc, bf);
249ee722 2090 return NULL;
f8316df1
LR		 2091 }
2092
56dc6336 2093 fi->bf = bf;
04caf863
FF		 2094
2095 return bf;
2096}
2097
59505c02
FF		 2098static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2099 struct ath_tx_control *txctl)
f078f209 2100{
28d16708
FF		 2101 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2102 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
36323f81 2103 struct ieee80211_sta *sta = txctl->sta;
f59a59fe 2104 struct ieee80211_vif *vif = info->control.vif;
f89d1bc4 2105 struct ath_vif *avp;
9ac58615 2106 struct ath_softc *sc = hw->priv;
04caf863 2107 int frmlen = skb->len + FCS_LEN;
59505c02 2108 int padpos, padsize;
f078f209 2109
a9927ba3
BG		 2110 /* NOTE: sta can be NULL according to net/mac80211.h */
2111 if (sta)
2112 txctl->an = (struct ath_node *)sta->drv_priv;
f89d1bc4
FF		 2113 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2114 avp = (void *)vif->drv_priv;
2115 txctl->an = &avp->mcast_node;
2116 }
a9927ba3 2117
04caf863
FF		 2118 if (info->control.hw_key)
2119 frmlen += info->control.hw_key->icv_len;
2120
f078f209 2121 /*
e8324357
S		 2122 * As a temporary workaround, assign seq# here; this will likely need
2123 * to be cleaned up to work better with Beacon transmission and virtual
2124 * BSSes.
f078f209 2125 */
e8324357 2126 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
e8324357
S		 2127 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2128 sc->tx.seq_no += 0x10;
2129 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2130 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
f078f209 2131 }
f078f209 2132
59505c02
FF		 2133 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2134 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2135 !ieee80211_is_data(hdr->frame_control))
2136 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2137
42cecc34 2138 /* Add the padding after the header if this is not already done */
c60c9929 2139 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2140 padsize = padpos & 3;
2141 if (padsize && skb->len > padpos) {
2142 if (skb_headroom(skb) < padsize)
2143 return -ENOMEM;
28d16708 2144
42cecc34
JL		 2145 skb_push(skb, padsize);
2146 memmove(skb->data, skb->data + padsize, padpos);
f078f209 2147 }
f078f209 2148
36323f81 2149 setup_frame_info(hw, sta, skb, frmlen);
59505c02
FF		 2150 return 0;
2151}
2152
2d42efc4 2153
59505c02
FF		 2154/* Upon failure caller should free skb */
2155int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2156 struct ath_tx_control *txctl)
2157{
2158 struct ieee80211_hdr *hdr;
2159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2160 struct ieee80211_sta *sta = txctl->sta;
2161 struct ieee80211_vif *vif = info->control.vif;
2162 struct ath_softc *sc = hw->priv;
2163 struct ath_txq *txq = txctl->txq;
2164 struct ath_atx_tid *tid = NULL;
2165 struct ath_buf *bf;
59505c02
FF		 2166 int q;
2167 int ret;
2168
2169 ret = ath_tx_prepare(hw, skb, txctl);
2170 if (ret)
2171 return ret;
2172
2173 hdr = (struct ieee80211_hdr *) skb->data;
2d42efc4
FF		 2174 /*
2175 * At this point, the vif, hw_key and sta pointers in the tx control
2176 * info are no longer valid (overwritten by the ath_frame_info data.
2177 */
2178
28d16708 2179 q = skb_get_queue_mapping(skb);
23de5dc9
FF		 2180
2181 ath_txq_lock(sc, txq);
28d16708 2182 if (txq == sc->tx.txq_map[q] &&
7702e788
FF		 2183 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2184 !txq->stopped) {
7545daf4 2185 ieee80211_stop_queue(sc->hw, q);
3db1cd5c 2186 txq->stopped = true;
f078f209 2187 }
f078f209 2188
f2c7a793
FF		 2189 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2190 ath_txq_unlock(sc, txq);
2191 txq = sc->tx.uapsdq;
2192 ath_txq_lock(sc, txq);
2800e82b
FF		 2193 } else if (txctl->an &&
2194 ieee80211_is_data_present(hdr->frame_control)) {
1803d02d 2195 tid = ath_get_skb_tid(sc, txctl->an, skb);
bdc21457
FF		 2196
2197 WARN_ON(tid->ac->txq != txctl->txq);
bdc21457 2198
2800e82b
FF		 2199 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2200 tid->ac->clear_ps_filter = true;
2201
bdc21457 2202 /*
2800e82b
FF		 2203 * Add this frame to software queue for scheduling later
2204 * for aggregation.
bdc21457 2205 */
2800e82b
FF		 2206 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2207 __skb_queue_tail(&tid->buf_q, skb);
2208 if (!txctl->an->sleeping)
2209 ath_tx_queue_tid(txq, tid);
2210
2211 ath_txq_schedule(sc, txq);
bdc21457
FF		 2212 goto out;
2213 }
2214
f2c7a793 2215 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
bdc21457 2216 if (!bf) {
a4943ccb 2217 ath_txq_skb_done(sc, txq, skb);
bdc21457
FF		 2218 if (txctl->paprd)
2219 dev_kfree_skb_any(skb);
2220 else
2221 ieee80211_free_txskb(sc->hw, skb);
2222 goto out;
2223 }
2224
2225 bf->bf_state.bfs_paprd = txctl->paprd;
2226
2227 if (txctl->paprd)
2228 bf->bf_state.bfs_paprd_timestamp = jiffies;
2229
79acac07 2230 ath_set_rates(vif, sta, bf);
f2c7a793 2231 ath_tx_send_normal(sc, txq, tid, skb);
3ad29529 2232
bdc21457 2233out:
23de5dc9 2234 ath_txq_unlock(sc, txq);
3ad29529 2235
44f1d26c 2236 return 0;
f078f209
LR		 2237}
2238
59505c02
FF		 2239void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2240 struct sk_buff *skb)
2241{
2242 struct ath_softc *sc = hw->priv;
2243 struct ath_tx_control txctl = {
2244 .txq = sc->beacon.cabq
2245 };
2246 struct ath_tx_info info = {};
2247 struct ieee80211_hdr *hdr;
2248 struct ath_buf *bf_tail = NULL;
2249 struct ath_buf *bf;
2250 LIST_HEAD(bf_q);
2251 int duration = 0;
2252 int max_duration;
2253
2254 max_duration =
2255 sc->cur_beacon_conf.beacon_interval * 1000 *
2256 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2257
2258 do {
2259 struct ath_frame_info *fi = get_frame_info(skb);
2260
2261 if (ath_tx_prepare(hw, skb, &txctl))
2262 break;
2263
2264 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2265 if (!bf)
2266 break;
2267
2268 bf->bf_lastbf = bf;
2269 ath_set_rates(vif, NULL, bf);
a3835e9f 2270 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
59505c02
FF		 2271 duration += info.rates[0].PktDuration;
2272 if (bf_tail)
2273 bf_tail->bf_next = bf;
2274
2275 list_add_tail(&bf->list, &bf_q);
2276 bf_tail = bf;
2277 skb = NULL;
2278
2279 if (duration > max_duration)
2280 break;
2281
2282 skb = ieee80211_get_buffered_bc(hw, vif);
2283 } while(skb);
2284
2285 if (skb)
2286 ieee80211_free_txskb(hw, skb);
2287
2288 if (list_empty(&bf_q))
2289 return;
2290
2291 bf = list_first_entry(&bf_q, struct ath_buf, list);
2292 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2293
2294 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2295 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2296 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2297 sizeof(*hdr), DMA_TO_DEVICE);
2298 }
2299
2300 ath_txq_lock(sc, txctl.txq);
2301 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2302 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2303 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2304 ath_txq_unlock(sc, txctl.txq);
2305}
2306
e8324357
S		 2307/*****************/
2308/* TX Completion */
2309/*****************/
528f0c6b 2310
e8324357 2311static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
0f9dc298 2312 int tx_flags, struct ath_txq *txq)
528f0c6b 2313{
e8324357 2314 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
c46917bb 2315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4d91f9f3 2316 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
a4943ccb 2317 int padpos, padsize;
07c15a3f 2318 unsigned long flags;
528f0c6b 2319
d2182b69 2320 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
528f0c6b 2321
51dea9be 2322 if (sc->sc_ah->caldata)
4b9b42bf 2323 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
51dea9be 2324
55797b1a 2325 if (!(tx_flags & ATH_TX_ERROR))
e8324357
S		 2326 /* Frame was ACKed */
2327 tx_info->flags |= IEEE80211_TX_STAT_ACK;
528f0c6b 2328
c60c9929 2329 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2330 padsize = padpos & 3;
2331 if (padsize && skb->len>padpos+padsize) {
2332 /*
2333 * Remove MAC header padding before giving the frame back to
2334 * mac80211.
2335 */
2336 memmove(skb->data + padsize, skb->data, padpos);
2337 skb_pull(skb, padsize);
e8324357 2338 }
528f0c6b 2339
07c15a3f 2340 spin_lock_irqsave(&sc->sc_pm_lock, flags);
c8e8868e 2341 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
1b04b930 2342 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
d2182b69 2343 ath_dbg(common, PS,
226afe68 2344 "Going back to sleep after having received TX status (0x%lx)\n",
1b04b930
S		 2345 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2346 PS_WAIT_FOR_CAB |
2347 PS_WAIT_FOR_PSPOLL_DATA |
2348 PS_WAIT_FOR_TX_ACK));
9a23f9ca 2349 }
07c15a3f 2350 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca 2351
f2c7a793 2352 __skb_queue_tail(&txq->complete_q, skb);
a4943ccb 2353 ath_txq_skb_done(sc, txq, skb);
e8324357 2354}
f078f209 2355
e8324357 2356static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 2357 struct ath_txq *txq, struct list_head *bf_q,
156369fa 2358 struct ath_tx_status *ts, int txok)
f078f209 2359{
e8324357 2360 struct sk_buff *skb = bf->bf_mpdu;
3afd21e7 2361 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
e8324357 2362 unsigned long flags;
6b2c4032 2363 int tx_flags = 0;
f078f209 2364
55797b1a 2365 if (!txok)
6b2c4032 2366 tx_flags |= ATH_TX_ERROR;
f078f209 2367
3afd21e7
FF		 2368 if (ts->ts_status & ATH9K_TXERR_FILT)
2369 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2370
c1739eb3 2371 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
6cf9e995 2372 bf->bf_buf_addr = 0;
89f927af
LR		 2373 if (sc->tx99_state)
2374 goto skip_tx_complete;
9f42c2b6
FF		 2375
2376 if (bf->bf_state.bfs_paprd) {
9cf04dcc
MSS		 2377 if (time_after(jiffies,
2378 bf->bf_state.bfs_paprd_timestamp +
2379 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
ca369eb4 2380 dev_kfree_skb_any(skb);
78a18172 2381 else
ca369eb4 2382 complete(&sc->paprd_complete);
9f42c2b6 2383 } else {
55797b1a 2384 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
0f9dc298 2385 ath_tx_complete(sc, skb, tx_flags, txq);
9f42c2b6 2386 }
89f927af 2387skip_tx_complete:
6cf9e995
BG		 2388 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2389 * accidentally reference it later.
2390 */
2391 bf->bf_mpdu = NULL;
e8324357
S		 2392
2393 /*
2394 * Return the list of ath_buf of this mpdu to free queue
2395 */
2396 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2397 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2398 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
f078f209
LR		 2399}
2400
0cdd5c60
FF		 2401static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2402 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 2403 int txok)
f078f209 2404{
a22be22a 2405 struct sk_buff *skb = bf->bf_mpdu;
254ad0ff 2406 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e8324357 2407 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
0cdd5c60 2408 struct ieee80211_hw *hw = sc->hw;
f0c255a0 2409 struct ath_hw *ah = sc->sc_ah;
8a92e2ee 2410 u8 i, tx_rateindex;
f078f209 2411
95e4acb7 2412 if (txok)
db1a052b 2413 tx_info->status.ack_signal = ts->ts_rssi;
95e4acb7 2414
db1a052b 2415 tx_rateindex = ts->ts_rateindex;
8a92e2ee
VT		 2416 WARN_ON(tx_rateindex >= hw->max_rates);
2417
3afd21e7 2418 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
d969847c 2419 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
f078f209 2420
b572d033 2421 BUG_ON(nbad > nframes);
ebd02287 2422 }
185d1589
RM		 2423 tx_info->status.ampdu_len = nframes;
2424 tx_info->status.ampdu_ack_len = nframes - nbad;
ebd02287 2425
db1a052b 2426 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
3afd21e7 2427 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
f0c255a0
FF		 2428 /*
2429 * If an underrun error is seen assume it as an excessive
2430 * retry only if max frame trigger level has been reached
2431 * (2 KB for single stream, and 4 KB for dual stream).
2432 * Adjust the long retry as if the frame was tried
2433 * hw->max_rate_tries times to affect how rate control updates
2434 * PER for the failed rate.
2435 * In case of congestion on the bus penalizing this type of
2436 * underruns should help hardware actually transmit new frames
2437 * successfully by eventually preferring slower rates.
2438 * This itself should also alleviate congestion on the bus.
2439 */
3afd21e7
FF		 2440 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2441 ATH9K_TX_DELIM_UNDERRUN)) &&
2442 ieee80211_is_data(hdr->frame_control) &&
83860c59 2443 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
f0c255a0
FF		 2444 tx_info->status.rates[tx_rateindex].count =
2445 hw->max_rate_tries;
f078f209 2446 }
8a92e2ee 2447
545750d3 2448 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
8a92e2ee 2449 tx_info->status.rates[i].count = 0;
545750d3
FF		 2450 tx_info->status.rates[i].idx = -1;
2451 }
8a92e2ee 2452
78c4653a 2453 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
f078f209
LR		 2454}
2455
e8324357 2456static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
f078f209 2457{
cbe61d8a 2458 struct ath_hw *ah = sc->sc_ah;
c46917bb 2459 struct ath_common *common = ath9k_hw_common(ah);
e8324357 2460 struct ath_buf *bf, *lastbf, *bf_held = NULL;
f078f209 2461 struct list_head bf_head;
e8324357 2462 struct ath_desc *ds;
29bffa96 2463 struct ath_tx_status ts;
e8324357 2464 int status;
f078f209 2465
d2182b69 2466 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
226afe68
JP		 2467 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2468 txq->axq_link);
f078f209 2469
23de5dc9 2470 ath_txq_lock(sc, txq);
f078f209 2471 for (;;) {
124b979b 2472 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2473 break;
2474
f078f209
LR		 2475 if (list_empty(&txq->axq_q)) {
2476 txq->axq_link = NULL;
73364b0c 2477 ath_txq_schedule(sc, txq);
f078f209
LR		 2478 break;
2479 }
f078f209
LR		 2480 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2481
e8324357
S		 2482 /*
2483 * There is a race condition that a BH gets scheduled
2484 * after sw writes TxE and before hw re-load the last
2485 * descriptor to get the newly chained one.
2486 * Software must keep the last DONE descriptor as a
2487 * holding descriptor - software does so by marking
2488 * it with the STALE flag.
2489 */
2490 bf_held = NULL;
50676b81 2491 if (bf->bf_state.stale) {
e8324357 2492 bf_held = bf;
fce041be 2493 if (list_is_last(&bf_held->list, &txq->axq_q))
e8324357 2494 break;
fce041be
FF		 2495
2496 bf = list_entry(bf_held->list.next, struct ath_buf,
2497 list);
f078f209
LR		 2498 }
2499
2500 lastbf = bf->bf_lastbf;
e8324357 2501 ds = lastbf->bf_desc;
f078f209 2502
29bffa96
FF		 2503 memset(&ts, 0, sizeof(ts));
2504 status = ath9k_hw_txprocdesc(ah, ds, &ts);
fce041be 2505 if (status == -EINPROGRESS)
e8324357 2506 break;
fce041be 2507
2dac4fb9 2508 TX_STAT_INC(txq->axq_qnum, txprocdesc);
f078f209 2509
e8324357
S		 2510 /*
2511 * Remove ath_buf's of the same transmit unit from txq,
2512 * however leave the last descriptor back as the holding
2513 * descriptor for hw.
2514 */
50676b81 2515 lastbf->bf_state.stale = true;
e8324357 2516 INIT_LIST_HEAD(&bf_head);
e8324357
S		 2517 if (!list_is_singular(&lastbf->list))
2518 list_cut_position(&bf_head,
2519 &txq->axq_q, lastbf->list.prev);
f078f209 2520
fce041be 2521 if (bf_held) {
0a8cea84 2522 list_del(&bf_held->list);
0a8cea84 2523 ath_tx_return_buffer(sc, bf_held);
e8324357 2524 }
f078f209 2525
fce041be 2526 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
8469cdef 2527 }
23de5dc9 2528 ath_txq_unlock_complete(sc, txq);
8469cdef
S		 2529}
2530
e8324357 2531void ath_tx_tasklet(struct ath_softc *sc)
f078f209 2532{
239c795d
FF		 2533 struct ath_hw *ah = sc->sc_ah;
2534 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
e8324357 2535 int i;
f078f209 2536
e8324357
S		 2537 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2538 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2539 ath_tx_processq(sc, &sc->tx.txq[i]);
f078f209
LR		 2540 }
2541}
2542
e5003249
VT		 2543void ath_tx_edma_tasklet(struct ath_softc *sc)
2544{
fce041be 2545 struct ath_tx_status ts;
e5003249
VT		 2546 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2547 struct ath_hw *ah = sc->sc_ah;
2548 struct ath_txq *txq;
2549 struct ath_buf *bf, *lastbf;
2550 struct list_head bf_head;
99ba6a46 2551 struct list_head *fifo_list;
e5003249 2552 int status;
e5003249
VT		 2553
2554 for (;;) {
124b979b 2555 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2556 break;
2557
fce041be 2558 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
e5003249
VT		 2559 if (status == -EINPROGRESS)
2560 break;
2561 if (status == -EIO) {
d2182b69 2562 ath_dbg(common, XMIT, "Error processing tx status\n");
e5003249
VT		 2563 break;
2564 }
2565
4e0ad259
FF		 2566 /* Process beacon completions separately */
2567 if (ts.qid == sc->beacon.beaconq) {
2568 sc->beacon.tx_processed = true;
2569 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
d074e8d5
SW		 2570
2571 ath9k_csa_is_finished(sc);
e5003249 2572 continue;
4e0ad259 2573 }
e5003249 2574
fce041be 2575 txq = &sc->tx.txq[ts.qid];
e5003249 2576
23de5dc9 2577 ath_txq_lock(sc, txq);
fce041be 2578
78ef731c
SM		 2579 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2580
99ba6a46
FF		 2581 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2582 if (list_empty(fifo_list)) {
23de5dc9 2583 ath_txq_unlock(sc, txq);
e5003249
VT		 2584 return;
2585 }
2586
99ba6a46 2587 bf = list_first_entry(fifo_list, struct ath_buf, list);
50676b81 2588 if (bf->bf_state.stale) {
99ba6a46
FF		 2589 list_del(&bf->list);
2590 ath_tx_return_buffer(sc, bf);
2591 bf = list_first_entry(fifo_list, struct ath_buf, list);
2592 }
2593
e5003249
VT		 2594 lastbf = bf->bf_lastbf;
2595
2596 INIT_LIST_HEAD(&bf_head);
99ba6a46
FF		 2597 if (list_is_last(&lastbf->list, fifo_list)) {
2598 list_splice_tail_init(fifo_list, &bf_head);
fce041be 2599 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
e5003249 2600
fce041be
FF		 2601 if (!list_empty(&txq->axq_q)) {
2602 struct list_head bf_q;
60f2d1d5 2603
fce041be
FF		 2604 INIT_LIST_HEAD(&bf_q);
2605 txq->axq_link = NULL;
2606 list_splice_tail_init(&txq->axq_q, &bf_q);
2607 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2608 }
99ba6a46 2609 } else {
50676b81 2610 lastbf->bf_state.stale = true;
99ba6a46
FF		 2611 if (bf != lastbf)
2612 list_cut_position(&bf_head, fifo_list,
2613 lastbf->list.prev);
fce041be 2614 }
86271e46 2615
fce041be 2616 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
23de5dc9 2617 ath_txq_unlock_complete(sc, txq);
e5003249
VT		 2618 }
2619}
2620
e8324357
S		 2621/*****************/
2622/* Init, Cleanup */
2623/*****************/
f078f209 2624
5088c2f1
VT		 2625static int ath_txstatus_setup(struct ath_softc *sc, int size)
2626{
2627 struct ath_descdma *dd = &sc->txsdma;
2628 u8 txs_len = sc->sc_ah->caps.txs_len;
2629
2630 dd->dd_desc_len = size * txs_len;
b81950b1
FF		 2631 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2632 &dd->dd_desc_paddr, GFP_KERNEL);
5088c2f1
VT		 2633 if (!dd->dd_desc)
2634 return -ENOMEM;
2635
2636 return 0;
2637}
2638
2639static int ath_tx_edma_init(struct ath_softc *sc)
2640{
2641 int err;
2642
2643 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2644 if (!err)
2645 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2646 sc->txsdma.dd_desc_paddr,
2647 ATH_TXSTATUS_RING_SIZE);
2648
2649 return err;
2650}
2651
e8324357 2652int ath_tx_init(struct ath_softc *sc, int nbufs)
f078f209 2653{
c46917bb 2654 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8324357 2655 int error = 0;
f078f209 2656
797fe5cb 2657 spin_lock_init(&sc->tx.txbuflock);
f078f209 2658
797fe5cb 2659 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
4adfcded 2660 "tx", nbufs, 1, 1);
797fe5cb 2661 if (error != 0) {
3800276a
JP		 2662 ath_err(common,
2663 "Failed to allocate tx descriptors: %d\n", error);
b81950b1 2664 return error;
797fe5cb 2665 }
f078f209 2666
797fe5cb 2667 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
5088c2f1 2668 "beacon", ATH_BCBUF, 1, 1);
797fe5cb 2669 if (error != 0) {
3800276a
JP		 2670 ath_err(common,
2671 "Failed to allocate beacon descriptors: %d\n", error);
b81950b1 2672 return error;
797fe5cb 2673 }
f078f209 2674
164ace38
SB		 2675 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2676
b81950b1 2677 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
5088c2f1 2678 error = ath_tx_edma_init(sc);
f078f209 2679
e8324357 2680 return error;
f078f209
LR		 2681}
2682
f078f209
LR		 2683void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2684{
c5170163
S		 2685 struct ath_atx_tid *tid;
2686 struct ath_atx_ac *ac;
2687 int tidno, acno;
f078f209 2688
8ee5afbc 2689 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2690 tidno < IEEE80211_NUM_TIDS;
c5170163
S		 2691 tidno++, tid++) {
2692 tid->an = an;
2693 tid->tidno = tidno;
2694 tid->seq_start = tid->seq_next = 0;
2695 tid->baw_size = WME_MAX_BA;
2696 tid->baw_head = tid->baw_tail = 0;
2697 tid->sched = false;
e8324357 2698 tid->paused = false;
08c96abd 2699 tid->active = false;
56dc6336 2700 __skb_queue_head_init(&tid->buf_q);
bb195ff6 2701 __skb_queue_head_init(&tid->retry_q);
c5170163 2702 acno = TID_TO_WME_AC(tidno);
8ee5afbc 2703 tid->ac = &an->ac[acno];
c5170163 2704 }
f078f209 2705
8ee5afbc 2706 for (acno = 0, ac = &an->ac[acno];
bea843c7 2707 acno < IEEE80211_NUM_ACS; acno++, ac++) {
c5170163 2708 ac->sched = false;
026d5b07 2709 ac->clear_ps_filter = true;
066dae93 2710 ac->txq = sc->tx.txq_map[acno];
c5170163 2711 INIT_LIST_HEAD(&ac->tid_q);
f078f209
LR		 2712 }
2713}
2714
b5aa9bf9 2715void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
f078f209 2716{
2b40994c
FF		 2717 struct ath_atx_ac *ac;
2718 struct ath_atx_tid *tid;
f078f209 2719 struct ath_txq *txq;
066dae93 2720 int tidno;
e8324357 2721
2b40994c 2722 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2723 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
f078f209 2724
2b40994c 2725 ac = tid->ac;
066dae93 2726 txq = ac->txq;
f078f209 2727
23de5dc9 2728 ath_txq_lock(sc, txq);
2b40994c
FF		 2729
2730 if (tid->sched) {
2731 list_del(&tid->list);
2732 tid->sched = false;
2733 }
2734
2735 if (ac->sched) {
2736 list_del(&ac->list);
2737 tid->ac->sched = false;
f078f209 2738 }
2b40994c
FF		 2739
2740 ath_tid_drain(sc, txq, tid);
08c96abd 2741 tid->active = false;
2b40994c 2742
23de5dc9 2743 ath_txq_unlock(sc, txq);
f078f209
LR		 2744 }
2745}
89f927af 2746
ef6b19e4
SM		 2747#ifdef CONFIG_ATH9K_TX99
2748
89f927af
LR		 2749int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2750 struct ath_tx_control *txctl)
2751{
2752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2753 struct ath_frame_info *fi = get_frame_info(skb);
2754 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2755 struct ath_buf *bf;
2756 int padpos, padsize;
2757
2758 padpos = ieee80211_hdrlen(hdr->frame_control);
2759 padsize = padpos & 3;
2760
2761 if (padsize && skb->len > padpos) {
2762 if (skb_headroom(skb) < padsize) {
2763 ath_dbg(common, XMIT,
2764 "tx99 padding failed\n");
2765 return -EINVAL;
2766 }
2767
2768 skb_push(skb, padsize);
2769 memmove(skb->data, skb->data + padsize, padpos);
2770 }
2771
2772 fi->keyix = ATH9K_TXKEYIX_INVALID;
2773 fi->framelen = skb->len + FCS_LEN;
2774 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2775
2776 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2777 if (!bf) {
2778 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2779 return -EINVAL;
2780 }
2781
2782 ath_set_rates(sc->tx99_vif, NULL, bf);
2783
2784 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2785 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2786
2787 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2788
2789 return 0;
2790}
ef6b19e4
SM		 2791
2792#endif /* CONFIG_ATH9K_TX99 */
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