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1 | /* |
2 | * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef _WCN36XX_H_ | |
18 | #define _WCN36XX_H_ | |
19 | ||
20 | #include <linux/completion.h> | |
21 | #include <linux/printk.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <net/mac80211.h> | |
24 | ||
25 | #include "hal.h" | |
26 | #include "smd.h" | |
27 | #include "txrx.h" | |
28 | #include "dxe.h" | |
29 | #include "pmc.h" | |
30 | #include "debug.h" | |
31 | ||
32 | #define WLAN_NV_FILE "wlan/prima/WCNSS_qcom_wlan_nv.bin" | |
33 | #define WCN36XX_AGGR_BUFFER_SIZE 64 | |
34 | ||
35 | extern unsigned int wcn36xx_dbg_mask; | |
36 | ||
37 | enum wcn36xx_debug_mask { | |
38 | WCN36XX_DBG_DXE = 0x00000001, | |
39 | WCN36XX_DBG_DXE_DUMP = 0x00000002, | |
40 | WCN36XX_DBG_SMD = 0x00000004, | |
41 | WCN36XX_DBG_SMD_DUMP = 0x00000008, | |
42 | WCN36XX_DBG_RX = 0x00000010, | |
43 | WCN36XX_DBG_RX_DUMP = 0x00000020, | |
44 | WCN36XX_DBG_TX = 0x00000040, | |
45 | WCN36XX_DBG_TX_DUMP = 0x00000080, | |
46 | WCN36XX_DBG_HAL = 0x00000100, | |
47 | WCN36XX_DBG_HAL_DUMP = 0x00000200, | |
48 | WCN36XX_DBG_MAC = 0x00000400, | |
49 | WCN36XX_DBG_BEACON = 0x00000800, | |
50 | WCN36XX_DBG_BEACON_DUMP = 0x00001000, | |
51 | WCN36XX_DBG_PMC = 0x00002000, | |
52 | WCN36XX_DBG_PMC_DUMP = 0x00004000, | |
53 | WCN36XX_DBG_ANY = 0xffffffff, | |
54 | }; | |
55 | ||
56 | #define wcn36xx_err(fmt, arg...) \ | |
57 | printk(KERN_ERR pr_fmt("ERROR " fmt), ##arg); | |
58 | ||
59 | #define wcn36xx_warn(fmt, arg...) \ | |
60 | printk(KERN_WARNING pr_fmt("WARNING " fmt), ##arg) | |
61 | ||
62 | #define wcn36xx_info(fmt, arg...) \ | |
63 | printk(KERN_INFO pr_fmt(fmt), ##arg) | |
64 | ||
65 | #define wcn36xx_dbg(mask, fmt, arg...) do { \ | |
66 | if (wcn36xx_dbg_mask & mask) \ | |
67 | printk(KERN_DEBUG pr_fmt(fmt), ##arg); \ | |
68 | } while (0) | |
69 | ||
70 | #define wcn36xx_dbg_dump(mask, prefix_str, buf, len) do { \ | |
71 | if (wcn36xx_dbg_mask & mask) \ | |
72 | print_hex_dump(KERN_DEBUG, pr_fmt(prefix_str), \ | |
73 | DUMP_PREFIX_OFFSET, 32, 1, \ | |
74 | buf, len, false); \ | |
75 | } while (0) | |
76 | ||
77 | #define WCN36XX_HW_CHANNEL(__wcn) (__wcn->hw->conf.chandef.chan->hw_value) | |
78 | #define WCN36XX_BAND(__wcn) (__wcn->hw->conf.chandef.chan->band) | |
79 | #define WCN36XX_CENTER_FREQ(__wcn) (__wcn->hw->conf.chandef.chan->center_freq) | |
80 | #define WCN36XX_LISTEN_INTERVAL(__wcn) (__wcn->hw->conf.listen_interval) | |
81 | #define WCN36XX_FLAGS(__wcn) (__wcn->hw->flags) | |
82 | #define WCN36XX_MAX_POWER(__wcn) (__wcn->hw->conf.chandef.chan->max_power) | |
83 | ||
84 | static inline void buff_to_be(u32 *buf, size_t len) | |
85 | { | |
86 | int i; | |
87 | for (i = 0; i < len; i++) | |
88 | buf[i] = cpu_to_be32(buf[i]); | |
89 | } | |
90 | ||
91 | struct nv_data { | |
92 | int is_valid; | |
93 | u8 table; | |
94 | }; | |
95 | ||
96 | /* Interface for platform control path | |
97 | * | |
98 | * @open: hook must be called when wcn36xx wants to open control channel. | |
99 | * @tx: sends a buffer. | |
100 | */ | |
101 | struct wcn36xx_platform_ctrl_ops { | |
102 | int (*open)(void *drv_priv, void *rsp_cb); | |
103 | void (*close)(void); | |
104 | int (*tx)(char *buf, size_t len); | |
105 | int (*get_hw_mac)(u8 *addr); | |
106 | int (*smsm_change_state)(u32 clear_mask, u32 set_mask); | |
107 | }; | |
108 | ||
109 | /** | |
110 | * struct wcn36xx_vif - holds VIF related fields | |
111 | * | |
112 | * @bss_index: bss_index is initially set to 0xFF. bss_index is received from | |
113 | * HW after first config_bss call and must be used in delete_bss and | |
114 | * enter/exit_bmps. | |
115 | */ | |
116 | struct wcn36xx_vif { | |
117 | struct list_head list; | |
118 | struct wcn36xx_sta *sta; | |
119 | u8 dtim_period; | |
120 | enum ani_ed_type encrypt_type; | |
121 | bool is_joining; | |
122 | struct wcn36xx_hal_mac_ssid ssid; | |
123 | ||
124 | /* Power management */ | |
125 | enum wcn36xx_power_state pw_state; | |
126 | ||
127 | u8 bss_index; | |
128 | u8 ucast_dpu_signature; | |
129 | /* Returned from WCN36XX_HAL_ADD_STA_SELF_RSP */ | |
130 | u8 self_sta_index; | |
131 | u8 self_dpu_desc_index; | |
132 | }; | |
133 | ||
134 | /** | |
135 | * struct wcn36xx_sta - holds STA related fields | |
136 | * | |
137 | * @tid: traffic ID that is used during AMPDU and in TX BD. | |
138 | * @sta_index: STA index is returned from HW after config_sta call and is | |
139 | * used in both SMD channel and TX BD. | |
140 | * @dpu_desc_index: DPU descriptor index is returned from HW after config_sta | |
141 | * call and is used in TX BD. | |
142 | * @bss_sta_index: STA index is returned from HW after config_bss call and is | |
143 | * used in both SMD channel and TX BD. See table bellow when it is used. | |
144 | * @bss_dpu_desc_index: DPU descriptor index is returned from HW after | |
145 | * config_bss call and is used in TX BD. | |
146 | * ______________________________________________ | |
147 | * | | STA | AP | | |
148 | * |______________|_____________|_______________| | |
149 | * | TX BD |bss_sta_index| sta_index | | |
150 | * |______________|_____________|_______________| | |
151 | * |all SMD calls |bss_sta_index| sta_index | | |
152 | * |______________|_____________|_______________| | |
153 | * |smd_delete_sta| sta_index | sta_index | | |
154 | * |______________|_____________|_______________| | |
155 | */ | |
156 | struct wcn36xx_sta { | |
157 | struct wcn36xx_vif *vif; | |
158 | u16 aid; | |
159 | u16 tid; | |
160 | u8 sta_index; | |
161 | u8 dpu_desc_index; | |
162 | u8 bss_sta_index; | |
163 | u8 bss_dpu_desc_index; | |
164 | bool is_data_encrypted; | |
165 | /* Rates */ | |
166 | struct wcn36xx_hal_supported_rates supported_rates; | |
167 | }; | |
168 | struct wcn36xx_dxe_ch; | |
169 | struct wcn36xx { | |
170 | struct ieee80211_hw *hw; | |
171 | struct device *dev; | |
172 | struct list_head vif_list; | |
173 | ||
174 | u8 fw_revision; | |
175 | u8 fw_version; | |
176 | u8 fw_minor; | |
177 | u8 fw_major; | |
178 | ||
179 | /* extra byte for the NULL termination */ | |
180 | u8 crm_version[WCN36XX_HAL_VERSION_LENGTH + 1]; | |
181 | u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH + 1]; | |
182 | ||
183 | /* IRQs */ | |
184 | int tx_irq; | |
185 | int rx_irq; | |
186 | void __iomem *mmio; | |
187 | ||
188 | struct wcn36xx_platform_ctrl_ops *ctrl_ops; | |
189 | /* | |
190 | * smd_buf must be protected with smd_mutex to garantee | |
191 | * that all messages are sent one after another | |
192 | */ | |
193 | u8 *hal_buf; | |
194 | size_t hal_rsp_len; | |
195 | struct mutex hal_mutex; | |
196 | struct completion hal_rsp_compl; | |
197 | struct workqueue_struct *hal_ind_wq; | |
198 | struct work_struct hal_ind_work; | |
199 | struct mutex hal_ind_mutex; | |
200 | struct list_head hal_ind_queue; | |
201 | ||
202 | /* DXE channels */ | |
203 | struct wcn36xx_dxe_ch dxe_tx_l_ch; /* TX low */ | |
204 | struct wcn36xx_dxe_ch dxe_tx_h_ch; /* TX high */ | |
205 | struct wcn36xx_dxe_ch dxe_rx_l_ch; /* RX low */ | |
206 | struct wcn36xx_dxe_ch dxe_rx_h_ch; /* RX high */ | |
207 | ||
208 | /* For synchronization of DXE resources from BH, IRQ and WQ contexts */ | |
209 | spinlock_t dxe_lock; | |
210 | bool queues_stopped; | |
211 | ||
212 | /* Memory pools */ | |
213 | struct wcn36xx_dxe_mem_pool mgmt_mem_pool; | |
214 | struct wcn36xx_dxe_mem_pool data_mem_pool; | |
215 | ||
216 | struct sk_buff *tx_ack_skb; | |
217 | ||
218 | #ifdef CONFIG_WCN36XX_DEBUGFS | |
219 | /* Debug file system entry */ | |
220 | struct wcn36xx_dfs_entry dfs; | |
221 | #endif /* CONFIG_WCN36XX_DEBUGFS */ | |
222 | ||
223 | }; | |
224 | ||
225 | static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn, | |
226 | u8 major, | |
227 | u8 minor, | |
228 | u8 version, | |
229 | u8 revision) | |
230 | { | |
231 | return (wcn->fw_major == major && | |
232 | wcn->fw_minor == minor && | |
233 | wcn->fw_version == version && | |
234 | wcn->fw_revision == revision); | |
235 | } | |
236 | void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates); | |
237 | ||
238 | #endif /* _WCN36XX_H_ */ |