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wil6210: correctly report locally generated disconnect in STA mode
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / wil6210 / wil6210.h
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2be7d22f 1/*
9953a782 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
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3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef __WIL6210_H__
18#define __WIL6210_H__
19
13cd9f75 20#include <linux/etherdevice.h>
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21#include <linux/netdevice.h>
22#include <linux/wireless.h>
23#include <net/cfg80211.h>
7c0acf86 24#include <linux/timex.h>
dc16427b 25#include <linux/types.h>
b874ddec 26#include "wmi.h"
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27#include "wil_platform.h"
28
c33407a8 29extern bool no_fw_recovery;
9a06bec9 30extern unsigned int mtu_max;
ab954628 31extern unsigned short rx_ring_overflow_thrsh;
3a3def8d 32extern int agg_wsize;
0436fd9a 33extern u32 vring_idle_trsh;
c406ea7c 34extern bool rx_align_2;
bfc2dc7a 35extern bool debug_fw;
849a564b 36extern bool disable_ap_sme;
2be7d22f 37
2be7d22f 38#define WIL_NAME "wil6210"
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39#define WIL_FW_NAME_DEFAULT "wil6210.fw" /* code Sparrow B0 */
40#define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" /* code Sparrow D0 */
41#define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */
2be7d22f 42
9953a782 43#define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */
f772ebfb 44#define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
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45
46/**
47 * extract bits [@b0:@b1] (inclusive) from the value @x
48 * it should be @b0 <= @b1, or result is incorrect
49 */
50static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
51{
52 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
53}
54
55#define WIL6210_MEM_SIZE (2*1024*1024UL)
56
f1871cd9 57#define WIL_TX_Q_LEN_DEFAULT (4000)
3baedd91 58#define WIL_RX_RING_SIZE_ORDER_DEFAULT (10)
ee5dfe0d 59#define WIL_TX_RING_SIZE_ORDER_DEFAULT (12)
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60#define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7)
61#define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */
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62/* limit ring size in range [32..32k] */
63#define WIL_RING_SIZE_ORDER_MIN (5)
64#define WIL_RING_SIZE_ORDER_MAX (15)
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65#define WIL6210_MAX_TX_RINGS (24) /* HW limit */
66#define WIL6210_MAX_CID (8) /* HW limit */
67#define WIL6210_NAPI_BUDGET (16) /* arbitrary */
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68#define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */
69#define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */
70/* Hardware offload block adds the following:
71 * 26 bytes - 3-address QoS data header
c44690a1 72 * 8 bytes - IV + EIV (for GCMP)
3277213f 73 * 8 bytes - SNAP
c44690a1 74 * 16 bytes - MIC (for GCMP)
3277213f 75 * 4 bytes - CRC
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76 */
77#define WIL_MAX_MPDU_OVERHEAD (62)
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78
79/* Calculate MAC buffer size for the firmware. It includes all overhead,
80 * as it will go over the air, and need to be 8 byte aligned
81 */
82static inline u32 wil_mtu2macbuf(u32 mtu)
83{
84 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
85}
86
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87/* MTU for Ethernet need to take into account 8-byte SNAP header
88 * to be added when encapsulating Ethernet frame into 802.11
89 */
90#define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8)
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91/* Max supported by wil6210 value for interrupt threshold is 5sec. */
92#define WIL6210_ITR_TRSH_MAX (5000000)
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93#define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
94#define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
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95#define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
96#define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
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97#define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */
98#define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000)
047e5d74 99#define WIL6210_SCAN_TO msecs_to_jiffies(10000)
78771d76 100#define WIL6210_DISCONNECT_TO_MS (2000)
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101#define WIL6210_RX_HIGH_TRSH_INIT (0)
102#define WIL6210_RX_HIGH_TRSH_DEFAULT \
103 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
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104#define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see
105 * 802.11REVmc/D5.0, section 9.4.1.8)
106 */
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107/* Hardware definitions begin */
108
109/*
110 * Mapping
111 * RGF File | Host addr | FW addr
112 * | |
113 * user_rgf | 0x000000 | 0x880000
114 * dma_rgf | 0x001000 | 0x881000
115 * pcie_rgf | 0x002000 | 0x882000
116 * | |
117 */
118
119/* Where various structures placed in host address space */
120#define WIL6210_FW_HOST_OFF (0x880000UL)
121
122#define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF)
123
124/*
125 * Interrupt control registers block
126 *
127 * each interrupt controlled by the same bit in all registers
128 */
129struct RGF_ICR {
130 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
131 u32 ICR; /* Cause, W1C/COR depending on ICC */
132 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
133 u32 ICS; /* Cause Set, WO */
134 u32 IMV; /* Mask, RW+S/C */
135 u32 IMS; /* Mask Set, write 1 to set */
136 u32 IMC; /* Mask Clear, write 1 to clear */
137} __packed;
138
139/* registers - FW addresses */
b373de72 140#define RGF_USER_USAGE_1 (0x880004)
151a9706 141#define RGF_USER_USAGE_6 (0x880018)
1f1a361a 142 #define BIT_USER_OOB_MODE BIT(31)
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143#define RGF_USER_HW_MACHINE_STATE (0x8801dc)
144 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
2be7d22f 145#define RGF_USER_USER_CPU_0 (0x8801e0)
151a9706 146 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
17123991 147#define RGF_USER_MAC_CPU_0 (0x8801fc)
151a9706 148 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
17123991 149#define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
2cd0f021 150#define RGF_USER_BL (0x880A3C) /* Boot Loader */
17123991 151#define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
972072aa 152#define RGF_USER_CLKS_CTL_0 (0x880abc)
151a9706 153 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
972072aa 154 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
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155#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
156#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
157#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
158#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
17123991 159#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
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160 #define BIT_HPAL_PERST_FROM_PAD BIT(6)
161 #define BIT_CAR_PERST_RST BIT(7)
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162#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
163 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
6508281b 164#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18)
151a9706 165#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c)
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166#define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */
167 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2)
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168
169#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
170 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
171 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */
172#define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */
173 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0)
40e391b4 174 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1)
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175#define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
176 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
177 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
349214c1 178 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27)
7269494e 179 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */
2be7d22f 180
78366f69 181/* Legacy interrupt moderation control (before Sparrow v2)*/
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182#define RGF_DMA_ITR_CNT_TRSH (0x881c5c)
183#define RGF_DMA_ITR_CNT_DATA (0x881c60)
17123991 184#define RGF_DMA_ITR_CNT_CRL (0x881c64)
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185 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0)
186 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1)
187 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2)
188 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3)
189 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4)
190
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191/* Offload control (Sparrow B0+) */
192#define RGF_DMA_OFUL_NID_0 (0x881cd4)
193 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0)
194 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1)
195 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2)
196 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3)
197
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198/* New (sparrow v2+) interrupt moderation control */
199#define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40)
200#define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34)
201#define RGF_DMA_ITR_TX_CNT_DATA (0x881d38)
202#define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c)
203 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0)
204 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1)
205 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2)
206 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3)
207 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4)
208 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5)
209 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6)
210#define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60)
211#define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64)
212#define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68)
213 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0)
214 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
215 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2)
216 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3)
217 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
218#define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50)
219#define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44)
220#define RGF_DMA_ITR_RX_CNT_DATA (0x881d48)
221#define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c)
222 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0)
223 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1)
224 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2)
225 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3)
226 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4)
227 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5)
228 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6)
229#define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54)
230#define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58)
231#define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c)
232 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0)
233 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
234 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2)
235 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3)
236 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
237
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238#define RGF_DMA_PSEUDO_CAUSE (0x881c68)
239#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
240#define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70)
241 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0)
242 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
243 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
244
6508281b 245#define RGF_HP_CTRL (0x88265c)
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246#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
247
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248/* MAC timer, usec, for packet lifetime */
249#define RGF_MAC_MTRL_COUNTER_0 (0x886aa8)
250
151a9706 251#define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */
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252#define RGF_CAF_OSC_CONTROL (0x88afa4)
253 #define BIT_CAF_OSC_XTAL_EN BIT(0)
254#define RGF_CAF_PLL_LOCK_STATUS (0x88afec)
255 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0)
151a9706 256
d8cfb80c 257#define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */
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258 #define JTAG_DEV_ID_SPARROW (0x2632072f)
259
260#define RGF_USER_REVISION_ID (0x88afe4)
261#define RGF_USER_REVISION_ID_MASK (3)
262 #define REVISION_ID_SPARROW_B0 (0x0)
263 #define REVISION_ID_SPARROW_D0 (0x3)
d8cfb80c 264
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265/* crash codes for FW/Ucode stored here */
266#define RGF_FW_ASSERT_CODE (0x91f020)
267#define RGF_UCODE_ASSERT_CODE (0x91f028)
268
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269enum {
270 HW_VER_UNKNOWN,
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271 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */
272 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */
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273};
274
2be7d22f 275/* popular locations */
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276#define RGF_MBOX RGF_USER_USER_SCRATCH_PAD
277#define HOST_MBOX HOSTADDR(RGF_MBOX)
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278#define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
279
280/* ISR register bits */
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281#define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0)
282#define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1)
283#define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3)
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284
285/* Hardware definitions end */
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286struct fw_map {
287 u32 from; /* linker address - from, inclusive */
288 u32 to; /* linker address - to, exclusive */
289 u32 host; /* PCI/Host address - BAR0 + 0x880000 */
290 const char *name; /* for debugfs */
61578820 291 bool fw; /* true if FW mapping, false if UCODE mapping */
b541d0a0 292};
8fe59627 293
b541d0a0 294/* array size should be in sync with actual definition in the wmi.c */
61578820 295extern const struct fw_map fw_mapping[10];
2be7d22f 296
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297/**
298 * mk_cidxtid - construct @cidxtid field
299 * @cid: CID value
300 * @tid: TID value
301 *
302 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
303 */
304static inline u8 mk_cidxtid(u8 cid, u8 tid)
305{
306 return ((tid & 0xf) << 4) | (cid & 0xf);
307}
308
309/**
310 * parse_cidxtid - parse @cidxtid field
311 * @cid: store CID value here
312 * @tid: store TID value here
313 *
314 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
315 */
316static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
317{
318 *cid = cidxtid & 0xf;
319 *tid = (cidxtid >> 4) & 0xf;
320}
321
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322struct wil6210_mbox_ring {
323 u32 base;
324 u16 entry_size; /* max. size of mbox entry, incl. all headers */
325 u16 size;
326 u32 tail;
327 u32 head;
328} __packed;
329
330struct wil6210_mbox_ring_desc {
331 __le32 sync;
332 __le32 addr;
333} __packed;
334
335/* at HOST_OFF_WIL6210_MBOX_CTL */
336struct wil6210_mbox_ctl {
337 struct wil6210_mbox_ring tx;
338 struct wil6210_mbox_ring rx;
339} __packed;
340
341struct wil6210_mbox_hdr {
342 __le16 seq;
343 __le16 len; /* payload, bytes after this header */
344 __le16 type;
345 u8 flags;
346 u8 reserved;
347} __packed;
348
349#define WIL_MBOX_HDR_TYPE_WMI (0)
350
351/* max. value for wil6210_mbox_hdr.len */
352#define MAX_MBOXITEM_SIZE (240)
353
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354struct pending_wmi_event {
355 struct list_head list;
356 struct {
357 struct wil6210_mbox_hdr hdr;
b874ddec 358 struct wmi_cmd_hdr wmi;
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359 u8 data[0];
360 } __packed event;
361};
362
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363enum { /* for wil_ctx.mapped_as */
364 wil_mapped_as_none = 0,
365 wil_mapped_as_single = 1,
366 wil_mapped_as_page = 2,
367};
368
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369/**
370 * struct wil_ctx - software context for Vring descriptor
371 */
372struct wil_ctx {
373 struct sk_buff *skb;
c236658f 374 u8 nr_frags;
2232abd5 375 u8 mapped_as;
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376};
377
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378union vring_desc;
379
380struct vring {
381 dma_addr_t pa;
382 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
383 u16 size; /* number of vring_desc elements */
384 u32 swtail;
385 u32 swhead;
386 u32 hwtail; /* write here to inform hw */
f88f113a 387 struct wil_ctx *ctx; /* ctx[size] - software context */
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388};
389
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390/**
391 * Additional data for Tx Vring
392 */
393struct vring_tx_data {
230d8442 394 bool dot1x_open;
097638a0 395 int enabled;
7c0acf86 396 cycles_t idle, last_idle, begin;
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397 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
398 u16 agg_timeout;
cbcf5866 399 u8 agg_amsdu;
3a124ed6 400 bool addba_in_progress; /* if set, agg_xxx is for request in progress */
5933a06d 401 spinlock_t lock;
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402};
403
2be7d22f 404enum { /* for wil6210_priv.status */
817f1853 405 wil_status_fwready = 0, /* FW operational */
b338f74e 406 wil_status_fwconnecting,
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407 wil_status_fwconnected,
408 wil_status_dontscan,
817f1853 409 wil_status_mbox_ready, /* MBOX structures ready */
2be7d22f 410 wil_status_irqen, /* FIXME: interrupts enabled - for debug */
0fef1818 411 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
f13e0630 412 wil_status_resetting, /* reset in progress */
9419b6a2 413 wil_status_last /* keep last */
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414};
415
416struct pci_dev;
417
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418/**
419 * struct tid_ampdu_rx - TID aggregation information (Rx).
420 *
421 * @reorder_buf: buffer to reorder incoming aggregated MPDUs
422 * @reorder_time: jiffies when skb was added
423 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
424 * @reorder_timer: releases expired frames from the reorder buffer.
425 * @last_rx: jiffies of last rx activity
426 * @head_seq_num: head sequence number in reordering buffer.
427 * @stored_mpdu_num: number of MPDUs in reordering buffer
428 * @ssn: Starting Sequence Number expected to be aggregated.
429 * @buf_size: buffer size for incoming A-MPDUs
430 * @timeout: reset timer value (in TUs).
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431 * @ssn_last_drop: SSN of the last dropped frame
432 * @total: total number of processed incoming frames
433 * @drop_dup: duplicate frames dropped for this reorder buffer
434 * @drop_old: old frames dropped for this reorder buffer
b4490f42 435 * @dialog_token: dialog token for aggregation session
91a8edcc 436 * @first_time: true when this buffer used 1-st time
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437 */
438struct wil_tid_ampdu_rx {
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439 struct sk_buff **reorder_buf;
440 unsigned long *reorder_time;
441 struct timer_list session_timer;
442 struct timer_list reorder_timer;
443 unsigned long last_rx;
444 u16 head_seq_num;
445 u16 stored_mpdu_num;
446 u16 ssn;
447 u16 buf_size;
448 u16 timeout;
d5b1c32f 449 u16 ssn_last_drop;
91a8edcc
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450 unsigned long long total; /* frames processed */
451 unsigned long long drop_dup;
452 unsigned long long drop_old;
b4490f42 453 u8 dialog_token;
c888cdd4 454 bool first_time; /* is it 1-st time this buffer used? */
b4490f42
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455};
456
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457/**
458 * struct wil_tid_crypto_rx_single - TID crypto information (Rx).
459 *
460 * @pn: GCMP PN for the session
461 * @key_set: valid key present
462 */
463struct wil_tid_crypto_rx_single {
464 u8 pn[IEEE80211_GCMP_PN_LEN];
465 bool key_set;
466};
467
468struct wil_tid_crypto_rx {
469 struct wil_tid_crypto_rx_single key_id[4];
470};
471
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472struct wil_p2p_info {
473 struct ieee80211_channel listen_chan;
474 u8 discovery_started;
eb57a5b3 475 u8 p2p_dev_started;
e6d68341 476 u64 cookie;
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477 struct wireless_dev *pending_listen_wdev;
478 unsigned int listen_duration;
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479 struct timer_list discovery_timer; /* listen/search duration */
480 struct work_struct discovery_expired_work; /* listen/search expire */
bb6743f7 481 struct work_struct delayed_listen_work; /* listen after scan done */
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482};
483
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484enum wil_sta_status {
485 wil_sta_unused = 0,
486 wil_sta_conn_pending = 1,
487 wil_sta_connected = 2,
488};
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489
490#define WIL_STA_TID_NUM (16)
c4a110d8 491#define WIL_MCS_MAX (12) /* Maximum MCS supported */
b4490f42 492
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493struct wil_net_stats {
494 unsigned long rx_packets;
495 unsigned long tx_packets;
496 unsigned long rx_bytes;
497 unsigned long tx_bytes;
498 unsigned long tx_errors;
499 unsigned long rx_dropped;
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500 unsigned long rx_non_data_frame;
501 unsigned long rx_short_frame;
502 unsigned long rx_large_frame;
58527421 503 unsigned long rx_replay;
c8b78b5f 504 u16 last_mcs_rx;
c4a110d8 505 u64 rx_per_mcs[WIL_MCS_MAX + 1];
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506};
507
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508/**
509 * struct wil_sta_info - data for peer
510 *
511 * Peer identified by its CID (connection ID)
512 * NIC performs beam forming for each peer;
513 * if no beam forming done, frame exchange is not
514 * possible.
515 */
516struct wil_sta_info {
517 u8 addr[ETH_ALEN];
518 enum wil_sta_status status;
c8b78b5f 519 struct wil_net_stats stats;
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520 /* Rx BACK */
521 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
ec81b5ad 522 spinlock_t tid_rx_lock; /* guarding tid_rx array */
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523 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
524 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
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525 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM];
526 struct wil_tid_crypto_rx group_crypto_rx;
9d865ee2 527 u8 aid; /* 1-254; 0 if unknown/not reported */
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528};
529
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530enum {
531 fw_recovery_idle = 0,
532 fw_recovery_pending = 1,
533 fw_recovery_running = 2,
534};
535
d8cfb80c 536enum {
d8cfb80c
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537 hw_capability_last
538};
539
40822a90
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540struct wil_probe_client_req {
541 struct list_head list;
542 u64 cookie;
543 u8 cid;
544};
545
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546struct pmc_ctx {
547 /* alloc, free, and read operations must own the lock */
548 struct mutex lock;
549 struct vring_tx_desc *pring_va;
550 dma_addr_t pring_pa;
551 struct desc_alloc_info *descriptors;
552 int last_cmd_status;
553 int num_descriptors;
554 int descriptor_size;
555};
556
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557struct wil_halp {
558 struct mutex lock; /* protect halp ref_cnt */
559 unsigned int ref_cnt;
560 struct completion comp;
561};
562
563struct wil_blob_wrapper {
564 struct wil6210_priv *wil;
565 struct debugfs_blob_wrapper blob;
566};
567
10d599ad
ME
568#define WIL_LED_MAX_ID (2)
569#define WIL_LED_INVALID_ID (0xF)
570#define WIL_LED_BLINK_ON_SLOW_MS (300)
571#define WIL_LED_BLINK_OFF_SLOW_MS (300)
572#define WIL_LED_BLINK_ON_MED_MS (200)
573#define WIL_LED_BLINK_OFF_MED_MS (200)
574#define WIL_LED_BLINK_ON_FAST_MS (100)
575#define WIL_LED_BLINK_OFF_FAST_MS (100)
576enum {
577 WIL_LED_TIME_SLOW = 0,
578 WIL_LED_TIME_MED,
579 WIL_LED_TIME_FAST,
580 WIL_LED_TIME_LAST,
581};
582
583struct blink_on_off_time {
584 u32 on_ms;
585 u32 off_ms;
586};
587
588extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST];
589extern u8 led_id;
590extern u8 led_polarity;
591
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592struct wil6210_priv {
593 struct pci_dev *pdev;
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594 struct wireless_dev *wdev;
595 void __iomem *csr;
9419b6a2 596 DECLARE_BITMAP(status, wil_status_last);
13cd9f75 597 u8 fw_version[ETHTOOL_FWVERS_LEN];
36b10a72 598 u32 hw_version;
a351f2f5 599 u8 chip_revision;
1aeda13b 600 const char *hw_name;
a351f2f5 601 const char *wil_fw_name;
d8cfb80c 602 DECLARE_BITMAP(hw_capabilities, hw_capability_last);
12bace75 603 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX);
b8023177 604 u8 n_mids; /* number of additional MIDs as reported by FW */
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605 u32 recovery_count; /* num of FW recovery attempts in a short time */
606 u32 recovery_state; /* FW recovery state machine */
fc219eed 607 unsigned long last_fw_recovery; /* jiffies of last fw recovery */
c33407a8 608 wait_queue_head_t wq; /* for all wait_event() use */
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609 /* profile */
610 u32 monitor_flags;
774974e5 611 u32 privacy; /* secure connection? */
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612 u8 hidden_ssid; /* relevant in AP mode */
613 u16 channel; /* relevant in AP mode */
2be7d22f 614 int sinfo_gen;
02beaf1a 615 u32 ap_isolate; /* no intra-BSS communication */
bcdd49b0 616 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */
3b56c15f 617 int locally_generated_disc; /* relevant in STA mode */
78366f69
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618 /* interrupt moderation */
619 u32 tx_max_burst_duration;
620 u32 tx_interframe_timeout;
621 u32 rx_max_burst_duration;
622 u32 rx_interframe_timeout;
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623 /* cached ISR registers */
624 u32 isr_misc;
625 /* mailbox related */
626 struct mutex wmi_mutex;
627 struct wil6210_mbox_ctl mbox_ctl;
628 struct completion wmi_ready;
59502647 629 struct completion wmi_call;
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630 u16 wmi_seq;
631 u16 reply_id; /**< wait for this WMI event */
632 void *reply_buf;
633 u16 reply_size;
634 struct workqueue_struct *wmi_wq; /* for deferred calls */
635 struct work_struct wmi_event_worker;
3277213f 636 struct workqueue_struct *wq_service;
2be7d22f 637 struct work_struct disconnect_worker;
ed6f9dc6 638 struct work_struct fw_error_worker; /* for FW error recovery */
2be7d22f 639 struct timer_list connect_timer;
047e5d74 640 struct timer_list scan_timer; /* detect scan timeout */
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641 struct list_head pending_wmi_ev;
642 /*
643 * protect pending_wmi_ev
644 * - fill in IRQ from wil6210_irq_misc,
645 * - consumed in thread by wmi_event_worker
646 */
647 spinlock_t wmi_ev_lock;
f9e3033f
DL
648 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */
649 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */
e0287c4a
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650 struct napi_struct napi_rx;
651 struct napi_struct napi_tx;
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652 /* keep alive */
653 struct list_head probe_client_pending;
654 struct mutex probe_client_mutex; /* protect @probe_client_pending */
655 struct work_struct probe_client_worker;
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656 /* DMA related */
657 struct vring vring_rx;
658 struct vring vring_tx[WIL6210_MAX_TX_RINGS];
097638a0 659 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
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660 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
661 struct wil_sta_info sta[WIL6210_MAX_CID];
41d6b093 662 int bcast_vring;
f2de576d 663 bool use_extended_dma_addr; /* indicates whether we are using 48 bits */
2be7d22f
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664 /* scan */
665 struct cfg80211_scan_request *scan_request;
666
667 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
668 /* statistics */
be299858 669 atomic_t isr_count_rx, isr_count_tx;
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670 /* debugfs */
671 struct dentry *debug;
349214c1 672 struct wil_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
74997a53 673 u8 discovery_mode;
c3bfea05 674 u8 abft_len;
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675
676 void *platform_handle;
677 struct wil_platform_ops platform_ops;
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678
679 struct pmc_ctx pmc;
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680
681 bool pbss;
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682
683 struct wil_p2p_info p2p;
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684
685 /* P2P_DEVICE vif */
686 struct wireless_dev *p2p_wdev;
5ffae432 687 struct mutex p2p_wdev_mutex; /* protect @p2p_wdev and @scan_request */
4332cac1 688 struct wireless_dev *radio_wdev;
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ME
689
690 /* High Access Latency Policy voting */
691 struct wil_halp halp;
692
e34dc647
ME
693#ifdef CONFIG_PM
694#ifdef CONFIG_PM_SLEEP
695 struct notifier_block pm_notify;
696#endif /* CONFIG_PM_SLEEP */
697#endif /* CONFIG_PM */
2be7d22f
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698};
699
700#define wil_to_wiphy(i) (i->wdev->wiphy)
701#define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
702#define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
703#define wil_to_wdev(i) (i->wdev)
704#define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
705#define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
706#define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
707
babcb3ed 708__printf(2, 3)
57219dc7 709void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
babcb3ed 710__printf(2, 3)
290206fa 711void __wil_err(struct wil6210_priv *wil, const char *fmt, ...);
babcb3ed 712__printf(2, 3)
290206fa 713void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
40e391b4 714__printf(2, 3)
290206fa 715void __wil_info(struct wil6210_priv *wil, const char *fmt, ...);
d8ed043a
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716__printf(2, 3)
717void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...);
98658095
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718#define wil_dbg(wil, fmt, arg...) do { \
719 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
720 wil_dbg_trace(wil, fmt, ##arg); \
721} while (0)
2be7d22f 722
7743882d
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723#define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
724#define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
725#define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
726#define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
93cb679a 727#define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg)
290206fa
ME
728#define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg)
729#define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg)
730#define wil_err_ratelimited(wil, fmt, arg...) \
731 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg)
2be7d22f 732
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733/* target operations */
734/* register read */
735static inline u32 wil_r(struct wil6210_priv *wil, u32 reg)
736{
737 return readl(wil->csr + HOSTADDR(reg));
738}
739
740/* register write. wmb() to make sure it is completed */
741static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val)
742{
743 writel(val, wil->csr + HOSTADDR(reg));
744 wmb(); /* wait for write to propagate to the HW */
745}
746
747/* register set = read, OR, write */
748static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val)
749{
750 wil_w(wil, reg, wil_r(wil, reg) | val);
751}
752
753/* register clear = read, AND with inverted, write */
754static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val)
755{
756 wil_w(wil, reg, wil_r(wil, reg) & ~val);
757}
758
871d8c4b 759#if defined(CONFIG_DYNAMIC_DEBUG)
7743882d 760#define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \
2be7d22f 761 groupsize, buf, len, ascii) \
3b0378a8 762 print_hex_dump_debug("DBG[TXRX]" prefix_str,\
2be7d22f
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763 prefix_type, rowsize, \
764 groupsize, buf, len, ascii)
765
7743882d 766#define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \
2be7d22f 767 groupsize, buf, len, ascii) \
3b0378a8 768 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
2be7d22f
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769 prefix_type, rowsize, \
770 groupsize, buf, len, ascii)
5eb443e9
DL
771
772#define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \
773 groupsize, buf, len, ascii) \
774 print_hex_dump_debug("DBG[MISC]" prefix_str,\
775 prefix_type, rowsize, \
776 groupsize, buf, len, ascii)
a43b5142
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777#else /* defined(CONFIG_DYNAMIC_DEBUG) */
778static inline
779void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
780 int groupsize, const void *buf, size_t len, bool ascii)
781{
782}
783
784static inline
785void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
786 int groupsize, const void *buf, size_t len, bool ascii)
787{
788}
5eb443e9
DL
789
790static inline
791void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize,
792 int groupsize, const void *buf, size_t len, bool ascii)
793{
794}
a43b5142 795#endif /* defined(CONFIG_DYNAMIC_DEBUG) */
2be7d22f
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796
797void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
798 size_t count);
799void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
800 size_t count);
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801void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst,
802 const volatile void __iomem *src,
803 size_t count);
804void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil,
805 volatile void __iomem *dst,
806 const void *src, size_t count);
2be7d22f 807
3e2d8e1b 808void *wil_if_alloc(struct device *dev);
2be7d22f
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809void wil_if_free(struct wil6210_priv *wil);
810int wil_if_add(struct wil6210_priv *wil);
811void wil_if_remove(struct wil6210_priv *wil);
812int wil_priv_init(struct wil6210_priv *wil);
813void wil_priv_deinit(struct wil6210_priv *wil);
2cd0f021 814int wil_reset(struct wil6210_priv *wil, bool no_fw);
ed6f9dc6 815void wil_fw_error_recovery(struct wil6210_priv *wil);
c33407a8 816void wil_set_recovery_state(struct wil6210_priv *wil, int state);
375a173f 817bool wil_is_recovery_blocked(struct wil6210_priv *wil);
2be7d22f 818int wil_up(struct wil6210_priv *wil);
73d839ae 819int __wil_up(struct wil6210_priv *wil);
2be7d22f 820int wil_down(struct wil6210_priv *wil);
73d839ae 821int __wil_down(struct wil6210_priv *wil);
2be7d22f 822void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
3df2cd36 823int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
b6b1b0ec 824void wil_set_ethtoolops(struct net_device *ndev);
2be7d22f
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825
826void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
827void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
828int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
829 struct wil6210_mbox_hdr *hdr);
830int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
831void wmi_recv_cmd(struct wil6210_priv *wil);
832int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
833 u16 reply_id, void *reply, u8 reply_size, int to_msec);
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834void wmi_event_worker(struct work_struct *work);
835void wmi_event_flush(struct wil6210_priv *wil);
836int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
837int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
838int wmi_set_channel(struct wil6210_priv *wil, int channel);
839int wmi_get_channel(struct wil6210_priv *wil, int *channel);
2be7d22f 840int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
230d8442 841 const void *mac_addr, int key_usage);
2be7d22f 842int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
230d8442
VK
843 const void *mac_addr, int key_len, const void *key,
844 int key_usage);
2be7d22f
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845int wmi_echo(struct wil6210_priv *wil);
846int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
47e19af9 847int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
1647f12f 848int wmi_rxon(struct wil6210_priv *wil, bool on);
1a2780e0 849int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
849a564b
DL
850int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac,
851 u16 reason, bool full_disconnect, bool del_sta);
3277213f 852int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout);
26a359d9
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853int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason);
854int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason);
3277213f
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855int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token,
856 u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
2c207eb8
ME
857int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil,
858 enum wmi_ps_profile_type ps_profile);
3fea18d0
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859int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short);
860int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short);
849a564b 861int wmi_new_sta(struct wil6210_priv *wil, const u8 *mac, u8 aid);
3277213f
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862int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid,
863 u8 dialog_token, __le16 ba_param_set,
864 __le16 ba_timeout, __le16 ba_seq_ctrl);
3a3def8d 865int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
2be7d22f 866
f4b5a803 867void wil6210_clear_irq(struct wil6210_priv *wil);
bd2d18b5 868int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi);
2be7d22f 869void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
e4dbb093
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870void wil_mask_irq(struct wil6210_priv *wil);
871void wil_unmask_irq(struct wil6210_priv *wil);
78366f69 872void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
73d839ae
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873void wil_disable_irq(struct wil6210_priv *wil);
874void wil_enable_irq(struct wil6210_priv *wil);
f1b7764f 875void wil6210_mask_halp(struct wil6210_priv *wil);
e6d68341
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876
877/* P2P */
321a000b 878bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request);
e6d68341
DL
879void wil_p2p_discovery_timer_fn(ulong x);
880int wil_p2p_search(struct wil6210_priv *wil,
881 struct cfg80211_scan_request *request);
bb6743f7
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882int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev,
883 unsigned int duration, struct ieee80211_channel *chan,
884 u64 *cookie);
280ab987
LD
885u8 wil_p2p_stop_discovery(struct wil6210_priv *wil);
886int wil_p2p_cancel_listen(struct wil6210_priv *wil, u64 cookie);
e6d68341
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887void wil_p2p_listen_expired(struct work_struct *work);
888void wil_p2p_search_expired(struct work_struct *work);
d35c2b6f 889void wil_p2p_stop_radio_operations(struct wil6210_priv *wil);
bb6743f7 890void wil_p2p_delayed_listen_work(struct work_struct *work);
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DL
891
892/* WMI for P2P */
893int wmi_p2p_cfg(struct wil6210_priv *wil, int channel, int bi);
894int wmi_start_listen(struct wil6210_priv *wil);
895int wmi_start_search(struct wil6210_priv *wil);
896int wmi_stop_discovery(struct wil6210_priv *wil);
897
0b39aaf2
VK
898int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
899 struct cfg80211_mgmt_tx_params *params,
900 u64 *cookie);
2be7d22f
VK
901
902int wil6210_debugfs_init(struct wil6210_priv *wil);
903void wil6210_debugfs_remove(struct wil6210_priv *wil);
9eb82d43
VK
904int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
905 struct station_info *sinfo);
2be7d22f
VK
906
907struct wireless_dev *wil_cfg80211_init(struct device *dev);
908void wil_wdev_free(struct wil6210_priv *wil);
4332cac1 909void wil_p2p_wdev_free(struct wil6210_priv *wil);
2be7d22f
VK
910
911int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
8e52fe30 912int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype,
b4944f2c 913 u8 chan, u8 hidden_ssid, u8 is_go);
b8023177 914int wmi_pcp_stop(struct wil6210_priv *wil);
10d599ad 915int wmi_led_cfg(struct wil6210_priv *wil, bool enable);
035859a5
ME
916int wmi_abort_scan(struct wil6210_priv *wil);
917void wil_abort_scan(struct wil6210_priv *wil, bool sync);
9953a782 918void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps);
b516fcc5 919void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
4821e6d8 920 u16 reason_code, bool from_event);
40822a90
VK
921void wil_probe_client_flush(struct wil6210_priv *wil);
922void wil_probe_client_worker(struct work_struct *work);
2be7d22f 923
d3762b40 924int wil_rx_init(struct wil6210_priv *wil, u16 size);
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VK
925void wil_rx_fini(struct wil6210_priv *wil);
926
927/* TX API */
928int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
929 int cid, int tid);
930void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
0916d9f2 931int wil_tx_init(struct wil6210_priv *wil, int cid);
41d6b093
VK
932int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size);
933int wil_bcast_init(struct wil6210_priv *wil);
934void wil_bcast_fini(struct wil6210_priv *wil);
2be7d22f 935
f9e3033f
DL
936void wil_update_net_queues(struct wil6210_priv *wil, struct vring *vring,
937 bool should_stop);
938void wil_update_net_queues_bh(struct wil6210_priv *wil, struct vring *vring,
939 bool check_stop);
2be7d22f 940netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
e0287c4a
VK
941int wil_tx_complete(struct wil6210_priv *wil, int ringid);
942void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
2be7d22f
VK
943
944/* RX API */
e0287c4a
VK
945void wil_rx_handle(struct wil6210_priv *wil, int *quota);
946void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
2be7d22f
VK
947
948int wil_iftype_nl2wmi(enum nl80211_iftype type);
949
dba4b74d 950int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
12bace75
LD
951int wil_request_firmware(struct wil6210_priv *wil, const char *name,
952 bool load);
a351f2f5 953bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name);
dba4b74d 954
93cb679a
VK
955int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime);
956int wil_suspend(struct wil6210_priv *wil, bool is_runtime);
957int wil_resume(struct wil6210_priv *wil, bool is_runtime);
958
ea3ade75 959int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size);
7dc47258
VK
960void wil_fw_core_dump(struct wil6210_priv *wil);
961
349214c1
ME
962void wil_halp_vote(struct wil6210_priv *wil);
963void wil_halp_unvote(struct wil6210_priv *wil);
964void wil6210_set_halp(struct wil6210_priv *wil);
965void wil6210_clear_halp(struct wil6210_priv *wil);
966
2be7d22f 967#endif /* __WIL6210_H__ */