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mac80211: fix initialisation error path
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
61/* unaligned little endian access */
62#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68};
69
70static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
83MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
84
85
86/* Known PCI ids */
87static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
112static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
141/*
142 * Prototypes - PCI stack related functions
143 */
144static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
147#ifdef CONFIG_PM
148static int ath5k_pci_suspend(struct pci_dev *pdev,
149 pm_message_t state);
150static int ath5k_pci_resume(struct pci_dev *pdev);
151#else
152#define ath5k_pci_suspend NULL
153#define ath5k_pci_resume NULL
154#endif /* CONFIG_PM */
155
156static struct pci_driver ath5k_pci_drv_id = {
157 .name = "ath5k_pci",
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
163};
164
165
166
167/*
168 * Prototypes - MAC 802.11 stack related functions
169 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw);
175static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
32bfd35d
JB		 181static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
fa1c114f
JS		 183 struct ieee80211_if_conf *conf);
184static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ieee80211_tx_control *ctl);
201
202static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx,
204 .start = ath5k_start,
205 .stop = ath5k_stop,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
213 .conf_tx = NULL,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218};
219
220/*
221 * Prototypes - Internal functions
222 */
223/* Attach detach */
224static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228/* Channel/mode setup */
229static inline short ath5k_ieee2mhz(short chan);
230static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
232 unsigned int max);
233static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
235 unsigned int mode,
236 unsigned int max);
237static int ath5k_getchannels(struct ieee80211_hw *hw);
238static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240static void ath5k_setcurmode(struct ath5k_softc *sc,
241 unsigned int mode);
242static void ath5k_mode_setup(struct ath5k_softc *sc);
243/* Descriptor setup */
244static int ath5k_desc_alloc(struct ath5k_softc *sc,
245 struct pci_dev *pdev);
246static void ath5k_desc_free(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248/* Buffers setup */
249static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
250 struct ath5k_buf *bf);
251static int ath5k_txbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf,
253 struct ieee80211_tx_control *ctl);
254
255static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
256 struct ath5k_buf *bf)
257{
258 BUG_ON(!bf);
259 if (!bf->skb)
260 return;
261 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
262 PCI_DMA_TODEVICE);
263 dev_kfree_skb(bf->skb);
264 bf->skb = NULL;
265}
266
267/* Queues setup */
268static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
269 int qtype, int subtype);
270static int ath5k_beaconq_setup(struct ath5k_hw *ah);
271static int ath5k_beaconq_config(struct ath5k_softc *sc);
272static void ath5k_txq_drainq(struct ath5k_softc *sc,
273 struct ath5k_txq *txq);
274static void ath5k_txq_cleanup(struct ath5k_softc *sc);
275static void ath5k_txq_release(struct ath5k_softc *sc);
276/* Rx handling */
277static int ath5k_rx_start(struct ath5k_softc *sc);
278static void ath5k_rx_stop(struct ath5k_softc *sc);
279static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
280 struct ath5k_desc *ds,
281 struct sk_buff *skb);
282static void ath5k_tasklet_rx(unsigned long data);
283/* Tx handling */
284static void ath5k_tx_processq(struct ath5k_softc *sc,
285 struct ath5k_txq *txq);
286static void ath5k_tasklet_tx(unsigned long data);
287/* Beacon handling */
288static int ath5k_beacon_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf,
290 struct ieee80211_tx_control *ctl);
291static void ath5k_beacon_send(struct ath5k_softc *sc);
292static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 293static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 294
295static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
296{
297 u64 tsf = ath5k_hw_get_tsf64(ah);
298
299 if ((tsf & 0x7fff) < rstamp)
300 tsf -= 0x8000;
301
302 return (tsf & ~0x7fff) | rstamp;
303}
304
305/* Interrupt handling */
306static int ath5k_init(struct ath5k_softc *sc);
307static int ath5k_stop_locked(struct ath5k_softc *sc);
308static int ath5k_stop_hw(struct ath5k_softc *sc);
309static irqreturn_t ath5k_intr(int irq, void *dev_id);
310static void ath5k_tasklet_reset(unsigned long data);
311
312static void ath5k_calibrate(unsigned long data);
313/* LED functions */
314static void ath5k_led_off(unsigned long data);
315static void ath5k_led_blink(struct ath5k_softc *sc,
316 unsigned int on,
317 unsigned int off);
318static void ath5k_led_event(struct ath5k_softc *sc,
319 int event);
320
321
322/*
323 * Module init/exit functions
324 */
325static int __init
326init_ath5k_pci(void)
327{
328 int ret;
329
330 ath5k_debug_init();
331
332 ret = pci_register_driver(&ath5k_pci_drv_id);
333 if (ret) {
334 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
335 return ret;
336 }
337
338 return 0;
339}
340
341static void __exit
342exit_ath5k_pci(void)
343{
344 pci_unregister_driver(&ath5k_pci_drv_id);
345
346 ath5k_debug_finish();
347}
348
349module_init(init_ath5k_pci);
350module_exit(exit_ath5k_pci);
351
352
353/********************\
354* PCI Initialization *
355\********************/
356
357static const char *
358ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
359{
360 const char *name = "xxxxx";
361 unsigned int i;
362
363 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
364 if (srev_names[i].sr_type != type)
365 continue;
366 if ((val & 0xff) < srev_names[i + 1].sr_val) {
367 name = srev_names[i].sr_name;
368 break;
369 }
370 }
371
372 return name;
373}
374
375static int __devinit
376ath5k_pci_probe(struct pci_dev *pdev,
377 const struct pci_device_id *id)
378{
379 void __iomem *mem;
380 struct ath5k_softc *sc;
381 struct ieee80211_hw *hw;
382 int ret;
383 u8 csz;
384
385 ret = pci_enable_device(pdev);
386 if (ret) {
387 dev_err(&pdev->dev, "can't enable device\n");
388 goto err;
389 }
390
391 /* XXX 32-bit addressing only */
392 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
393 if (ret) {
394 dev_err(&pdev->dev, "32-bit DMA not available\n");
395 goto err_dis;
396 }
397
398 /*
399 * Cache line size is used to size and align various
400 * structures used to communicate with the hardware.
401 */
402 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
403 if (csz == 0) {
404 /*
405 * Linux 2.4.18 (at least) writes the cache line size
406 * register as a 16-bit wide register which is wrong.
407 * We must have this setup properly for rx buffer
408 * DMA to work so force a reasonable value here if it
409 * comes up zero.
410 */
411 csz = L1_CACHE_BYTES / sizeof(u32);
412 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
413 }
414 /*
415 * The default setting of latency timer yields poor results,
416 * set it to the value used by other systems. It may be worth
417 * tweaking this setting more.
418 */
419 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
420
421 /* Enable bus mastering */
422 pci_set_master(pdev);
423
424 /*
425 * Disable the RETRY_TIMEOUT register (0x41) to keep
426 * PCI Tx retries from interfering with C3 CPU state.
427 */
428 pci_write_config_byte(pdev, 0x41, 0);
429
430 ret = pci_request_region(pdev, 0, "ath5k");
431 if (ret) {
432 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
433 goto err_dis;
434 }
435
436 mem = pci_iomap(pdev, 0, 0);
437 if (!mem) {
438 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
439 ret = -EIO;
440 goto err_reg;
441 }
442
443 /*
444 * Allocate hw (mac80211 main struct)
445 * and hw->priv (driver private data)
446 */
447 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
448 if (hw == NULL) {
449 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
450 ret = -ENOMEM;
451 goto err_map;
452 }
453
454 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
455
456 /* Initialize driver private data */
457 SET_IEEE80211_DEV(hw, &pdev->dev);
458 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
459 hw->extra_tx_headroom = 2;
460 hw->channel_change_time = 5000;
461 /* these names are misleading */
462 hw->max_rssi = -110; /* signal in dBm */
463 hw->max_noise = -110; /* noise in dBm */
464 hw->max_signal = 100; /* we will provide a percentage based on rssi */
465 sc = hw->priv;
466 sc->hw = hw;
467 sc->pdev = pdev;
468
469 ath5k_debug_init_device(sc);
470
471 /*
472 * Mark the device as detached to avoid processing
473 * interrupts until setup is complete.
474 */
475 __set_bit(ATH_STAT_INVALID, sc->status);
476
477 sc->iobase = mem; /* So we can unmap it on detach */
478 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
479 sc->opmode = IEEE80211_IF_TYPE_STA;
480 mutex_init(&sc->lock);
481 spin_lock_init(&sc->rxbuflock);
482 spin_lock_init(&sc->txbuflock);
483
484 /* Set private data */
485 pci_set_drvdata(pdev, hw);
486
487 /* Enable msi for devices that support it */
488 pci_enable_msi(pdev);
489
490 /* Setup interrupt handler */
491 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
492 if (ret) {
493 ATH5K_ERR(sc, "request_irq failed\n");
494 goto err_free;
495 }
496
497 /* Initialize device */
498 sc->ah = ath5k_hw_attach(sc, id->driver_data);
499 if (IS_ERR(sc->ah)) {
500 ret = PTR_ERR(sc->ah);
501 goto err_irq;
502 }
503
504 /* Finish private driver data initialization */
505 ret = ath5k_attach(pdev, hw);
506 if (ret)
507 goto err_ah;
508
509 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
510 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
511 sc->ah->ah_mac_srev,
512 sc->ah->ah_phy_revision);
513
514 if(!sc->ah->ah_single_chip){
515 /* Single chip radio (!RF5111) */
516 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
517 /* No 5GHz support -> report 2GHz radio */
518 if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){
519 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
520 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
521 sc->ah->ah_radio_5ghz_revision);
522 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
523 } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){
524 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
525 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
527 /* Multiband radio */
528 } else {
529 ATH5K_INFO(sc, "RF%s multiband radio found"
530 " (0x%x)\n",
531 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
532 sc->ah->ah_radio_5ghz_revision);
533 }
534 }
535 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
536 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
537 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
538 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
539 sc->ah->ah_radio_5ghz_revision);
540 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
541 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
542 sc->ah->ah_radio_2ghz_revision);
543 }
544 }
545
546
547 /* ready to process interrupts */
548 __clear_bit(ATH_STAT_INVALID, sc->status);
549
550 return 0;
551err_ah:
552 ath5k_hw_detach(sc->ah);
553err_irq:
554 free_irq(pdev->irq, sc);
555err_free:
556 pci_disable_msi(pdev);
557 ieee80211_free_hw(hw);
558err_map:
559 pci_iounmap(pdev, mem);
560err_reg:
561 pci_release_region(pdev, 0);
562err_dis:
563 pci_disable_device(pdev);
564err:
565 return ret;
566}
567
568static void __devexit
569ath5k_pci_remove(struct pci_dev *pdev)
570{
571 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
572 struct ath5k_softc *sc = hw->priv;
573
574 ath5k_debug_finish_device(sc);
575 ath5k_detach(pdev, hw);
576 ath5k_hw_detach(sc->ah);
577 free_irq(pdev->irq, sc);
578 pci_disable_msi(pdev);
579 pci_iounmap(pdev, sc->iobase);
580 pci_release_region(pdev, 0);
581 pci_disable_device(pdev);
582 ieee80211_free_hw(hw);
583}
584
585#ifdef CONFIG_PM
586static int
587ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
588{
589 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
590 struct ath5k_softc *sc = hw->priv;
591
592 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
593 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
594
595 ath5k_stop_hw(sc);
596 pci_save_state(pdev);
597 pci_disable_device(pdev);
598 pci_set_power_state(pdev, PCI_D3hot);
599
600 return 0;
601}
602
603static int
604ath5k_pci_resume(struct pci_dev *pdev)
605{
606 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
607 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 608 struct ath5k_hw *ah = sc->ah;
609 int i, err;
fa1c114f
JS		 610
611 err = pci_set_power_state(pdev, PCI_D0);
612 if (err)
613 return err;
614
615 err = pci_enable_device(pdev);
616 if (err)
617 return err;
618
619 pci_restore_state(pdev);
620 /*
621 * Suspend/Resume resets the PCI configuration space, so we have to
622 * re-disable the RETRY_TIMEOUT register (0x41) to keep
623 * PCI Tx retries from interfering with C3 CPU state
624 */
625 pci_write_config_byte(pdev, 0x41, 0);
626
627 ath5k_init(sc);
628 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
247ae449
JL		 629 ath5k_hw_set_gpio_output(ah, sc->led_pin);
630 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
fa1c114f
JS		 631 }
632
247ae449
JL		 633 /*
634 * Reset the key cache since some parts do not
635 * reset the contents on initial power up or resume.
636 *
637 * FIXME: This may need to be revisited when mac80211 becomes
638 * aware of suspend/resume.
639 */
640 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
641 ath5k_hw_reset_key(ah, i);
642
fa1c114f
JS		 643 return 0;
644}
645#endif /* CONFIG_PM */
646
647
648
649/***********************\
650* Driver Initialization *
651\***********************/
652
653static int
654ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
655{
656 struct ath5k_softc *sc = hw->priv;
657 struct ath5k_hw *ah = sc->ah;
658 u8 mac[ETH_ALEN];
659 unsigned int i;
660 int ret;
661
662 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
663
664 /*
665 * Check if the MAC has multi-rate retry support.
666 * We do this by trying to setup a fake extended
667 * descriptor. MAC's that don't have support will
668 * return false w/o doing anything. MAC's that do
669 * support it will return true w/o doing anything.
670 */
671 if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0))
672 __set_bit(ATH_STAT_MRRETRY, sc->status);
673
674 /*
675 * Reset the key cache since some parts do not
676 * reset the contents on initial power up.
677 */
c65638a7 678 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 679 ath5k_hw_reset_key(ah, i);
680
681 /*
682 * Collect the channel list. The 802.11 layer
683 * is resposible for filtering this list based
684 * on settings like the phy mode and regulatory
685 * domain restrictions.
686 */
687 ret = ath5k_getchannels(hw);
688 if (ret) {
689 ATH5K_ERR(sc, "can't get channels\n");
690 goto err;
691 }
692
693 /* NB: setup here so ath5k_rate_update is happy */
694 if (test_bit(MODE_IEEE80211A, ah->ah_modes))
695 ath5k_setcurmode(sc, MODE_IEEE80211A);
696 else
697 ath5k_setcurmode(sc, MODE_IEEE80211B);
698
699 /*
700 * Allocate tx+rx descriptors and populate the lists.
701 */
702 ret = ath5k_desc_alloc(sc, pdev);
703 if (ret) {
704 ATH5K_ERR(sc, "can't allocate descriptors\n");
705 goto err;
706 }
707
708 /*
709 * Allocate hardware transmit queues: one queue for
710 * beacon frames and one data queue for each QoS
711 * priority. Note that hw functions handle reseting
712 * these queues at the needed time.
713 */
714 ret = ath5k_beaconq_setup(ah);
715 if (ret < 0) {
716 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
717 goto err_desc;
718 }
719 sc->bhalq = ret;
720
721 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
722 if (IS_ERR(sc->txq)) {
723 ATH5K_ERR(sc, "can't setup xmit queue\n");
724 ret = PTR_ERR(sc->txq);
725 goto err_bhal;
726 }
727
728 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
729 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
730 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
731 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
732 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
733
734 sc->led_on = 0; /* low true */
735 /*
736 * Auto-enable soft led processing for IBM cards and for
737 * 5211 minipci cards.
738 */
739 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
740 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
741 __set_bit(ATH_STAT_LEDSOFT, sc->status);
742 sc->led_pin = 0;
743 }
744 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
745 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
746 __set_bit(ATH_STAT_LEDSOFT, sc->status);
747 sc->led_pin = 0;
748 }
749 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
750 ath5k_hw_set_gpio_output(ah, sc->led_pin);
751 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
752 }
753
754 ath5k_hw_get_lladdr(ah, mac);
755 SET_IEEE80211_PERM_ADDR(hw, mac);
756 /* All MAC address bits matter for ACKs */
757 memset(sc->bssidmask, 0xff, ETH_ALEN);
758 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
759
760 ret = ieee80211_register_hw(hw);
761 if (ret) {
762 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
763 goto err_queues;
764 }
765
766 return 0;
767err_queues:
768 ath5k_txq_release(sc);
769err_bhal:
770 ath5k_hw_release_tx_queue(ah, sc->bhalq);
771err_desc:
772 ath5k_desc_free(sc, pdev);
773err:
774 return ret;
775}
776
777static void
778ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
779{
780 struct ath5k_softc *sc = hw->priv;
781
782 /*
783 * NB: the order of these is important:
784 * o call the 802.11 layer before detaching ath5k_hw to
785 * insure callbacks into the driver to delete global
786 * key cache entries can be handled
787 * o reclaim the tx queue data structures after calling
788 * the 802.11 layer as we'll get called back to reclaim
789 * node state and potentially want to use them
790 * o to cleanup the tx queues the hal is called, so detach
791 * it last
792 * XXX: ??? detach ath5k_hw ???
793 * Other than that, it's straightforward...
794 */
795 ieee80211_unregister_hw(hw);
796 ath5k_desc_free(sc, pdev);
797 ath5k_txq_release(sc);
798 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
799
800 /*
801 * NB: can't reclaim these until after ieee80211_ifdetach
802 * returns because we'll get called back to reclaim node
803 * state and potentially want to use them.
804 */
805}
806
807
808
809
810/********************\
811* Channel/mode setup *
812\********************/
813
814/*
815 * Convert IEEE channel number to MHz frequency.
816 */
817static inline short
818ath5k_ieee2mhz(short chan)
819{
820 if (chan <= 14 || chan >= 27)
821 return ieee80211chan2mhz(chan);
822 else
823 return 2212 + chan * 20;
824}
825
826static unsigned int
827ath5k_copy_rates(struct ieee80211_rate *rates,
828 const struct ath5k_rate_table *rt,
829 unsigned int max)
830{
831 unsigned int i, count;
832
833 if (rt == NULL)
834 return 0;
835
836 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
837 if (!rt->rates[i].valid)
838 continue;
839 rates->rate = rt->rates[i].rate_kbps / 100;
840 rates->val = rt->rates[i].rate_code;
841 rates->flags = rt->rates[i].modulation;
842 rates++;
843 count++;
844 max--;
845 }
846
847 return count;
848}
849
850static unsigned int
851ath5k_copy_channels(struct ath5k_hw *ah,
852 struct ieee80211_channel *channels,
853 unsigned int mode,
854 unsigned int max)
855{
856 static const struct { unsigned int mode, mask, chan; } map[] = {
857 [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A },
858 [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T },
859 [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B },
860 [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G },
861 [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG },
862 };
863 static const struct ath5k_regchannel chans_2ghz[] =
864 IEEE80211_CHANNELS_2GHZ;
865 static const struct ath5k_regchannel chans_5ghz[] =
866 IEEE80211_CHANNELS_5GHZ;
867 const struct ath5k_regchannel *chans;
868 enum ath5k_regdom dmn;
869 unsigned int i, count, size, chfreq, all, f, ch;
870
871 if (!test_bit(mode, ah->ah_modes))
872 return 0;
873
874 all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1;
875
876 switch (mode) {
877 case MODE_IEEE80211A:
878 case MODE_ATHEROS_TURBO:
879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
880 size = all ? 220 : ARRAY_SIZE(chans_5ghz);
881 chans = chans_5ghz;
882 dmn = ath5k_regdom2flag(ah->ah_regdomain,
883 IEEE80211_CHANNELS_5GHZ_MIN);
884 chfreq = CHANNEL_5GHZ;
885 break;
886 case MODE_IEEE80211B:
887 case MODE_IEEE80211G:
888 case MODE_ATHEROS_TURBOG:
889 size = all ? 26 : ARRAY_SIZE(chans_2ghz);
890 chans = chans_2ghz;
891 dmn = ath5k_regdom2flag(ah->ah_regdomain,
892 IEEE80211_CHANNELS_2GHZ_MIN);
893 chfreq = CHANNEL_2GHZ;
894 break;
895 default:
896 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
897 return 0;
898 }
899
900 for (i = 0, count = 0; i < size && max > 0; i++) {
901 ch = all ? i + 1 : chans[i].chan;
902 f = ath5k_ieee2mhz(ch);
903 /* Check if channel is supported by the chipset */
904 if (!ath5k_channel_ok(ah, f, chfreq))
905 continue;
906
907 /* Match regulation domain */
908 if (!all && !(IEEE80211_DMN(chans[i].domain) &
909 IEEE80211_DMN(dmn)))
910 continue;
911
912 if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode)
913 continue;
914
915 /* Write channel and increment counter */
916 channels->chan = ch;
917 channels->freq = f;
918 channels->val = map[mode].chan;
919 channels++;
920 count++;
921 max--;
922 }
923
924 return count;
925}
926
927/* Only tries to register modes our EEPROM says it can support */
928#define REGISTER_MODE(m) do { \
929 ret = ath5k_register_mode(hw, m); \
930 if (ret) \
931 return ret; \
932} while (0) \
933
934static inline int
935ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
936{
937 struct ath5k_softc *sc = hw->priv;
938 struct ieee80211_hw_mode *modes = sc->modes;
939 unsigned int i;
940 int ret;
941
942 if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
943 return 0;
944
945 for (i = 0; i < NUM_DRIVER_MODES; i++) {
946 if (modes[i].mode != m || !modes[i].num_channels)
947 continue;
948 ret = ieee80211_register_hwmode(hw, &modes[i]);
949 if (ret) {
950 ATH5K_ERR(sc, "can't register hwmode %u\n", m);
951 return ret;
952 }
953 return 0;
954 }
955 BUG();
956}
957
958static int
959ath5k_getchannels(struct ieee80211_hw *hw)
960{
961 struct ath5k_softc *sc = hw->priv;
962 struct ath5k_hw *ah = sc->ah;
963 struct ieee80211_hw_mode *modes = sc->modes;
964 unsigned int i, max_r, max_c;
965 int ret;
966
967 BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3);
968
969 /* The order here does not matter */
970 modes[0].mode = MODE_IEEE80211G;
971 modes[1].mode = MODE_IEEE80211B;
972 modes[2].mode = MODE_IEEE80211A;
973
974 max_r = ARRAY_SIZE(sc->rates);
975 max_c = ARRAY_SIZE(sc->channels);
976
977 for (i = 0; i < NUM_DRIVER_MODES; i++) {
978 struct ieee80211_hw_mode *mode = &modes[i];
979 const struct ath5k_rate_table *hw_rates;
980
981 if (i == 0) {
982 modes[0].rates = sc->rates;
983 modes->channels = sc->channels;
984 } else {
985 struct ieee80211_hw_mode *prev_mode = &modes[i-1];
986 int prev_num_r = prev_mode->num_rates;
987 int prev_num_c = prev_mode->num_channels;
988 mode->rates = &prev_mode->rates[prev_num_r];
989 mode->channels = &prev_mode->channels[prev_num_c];
990 }
991
992 hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
993 mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
994 max_r);
995 mode->num_channels = ath5k_copy_channels(ah, mode->channels,
996 mode->mode, max_c);
997 max_r -= mode->num_rates;
998 max_c -= mode->num_channels;
999 }
1000
1001 /* We try to register all modes this driver supports. We don't bother
1002 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
1003 * for that as per mac80211. Then, REGISTER_MODE() will will actually
1004 * check the eeprom reading for more reliable capability information.
1005 * Order matters here as per mac80211's latest preference. This will
1006 * all hopefullly soon go away. */
1007
1008 REGISTER_MODE(MODE_IEEE80211G);
1009 if (ah->ah_version != AR5K_AR5212)
1010 REGISTER_MODE(MODE_IEEE80211B);
1011 REGISTER_MODE(MODE_IEEE80211A);
1012
1013 ath5k_debug_dump_modes(sc, modes);
1014
1015 return ret;
1016}
1017
1018/*
1019 * Set/change channels. If the channel is really being changed,
1020 * it's done by reseting the chip. To accomplish this we must
1021 * first cleanup any pending DMA, then restart stuff after a la
1022 * ath5k_init.
1023 */
1024static int
1025ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1026{
1027 struct ath5k_hw *ah = sc->ah;
1028 int ret;
1029
1030 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n",
1031 sc->curchan->chan, sc->curchan->freq,
1032 chan->chan, chan->freq);
1033
1034 if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) {
1035 /*
1036 * To switch channels clear any pending DMA operations;
1037 * wait long enough for the RX fifo to drain, reset the
1038 * hardware at the new frequency, and then re-enable
1039 * the relevant bits of the h/w.
1040 */
1041 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1042 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1043 ath5k_rx_stop(sc); /* turn off frame recv */
1044 ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
1045 if (ret) {
1046 ATH5K_ERR(sc, "%s: unable to reset channel %u "
1047 "(%u Mhz)\n", __func__, chan->chan, chan->freq);
1048 return ret;
1049 }
1050 sc->curchan = chan;
1051 ath5k_hw_set_txpower_limit(sc->ah, 0);
1052
1053 /*
1054 * Re-enable rx framework.
1055 */
1056 ret = ath5k_rx_start(sc);
1057 if (ret) {
1058 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1059 __func__);
1060 return ret;
1061 }
1062
1063 /*
1064 * Change channels and update the h/w rate map
1065 * if we're switching; e.g. 11a to 11b/g.
1066 *
1067 * XXX needed?
1068 */
1069/* ath5k_chan_change(sc, chan); */
1070
1071 ath5k_beacon_config(sc);
1072 /*
1073 * Re-enable interrupts.
1074 */
1075 ath5k_hw_set_intr(ah, sc->imask);
1076 }
1077
1078 return 0;
1079}
1080
1081static void
1082ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1083{
1084 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1085 /* from Atheros NDIS driver, w/ permission */
1086 static const struct {
1087 u16 rate; /* tx/rx 802.11 rate */
1088 u16 timeOn; /* LED on time (ms) */
1089 u16 timeOff; /* LED off time (ms) */
1090 } blinkrates[] = {
1091 { 108, 40, 10 },
1092 { 96, 44, 11 },
1093 { 72, 50, 13 },
1094 { 48, 57, 14 },
1095 { 36, 67, 16 },
1096 { 24, 80, 20 },
1097 { 22, 100, 25 },
1098 { 18, 133, 34 },
1099 { 12, 160, 40 },
1100 { 10, 200, 50 },
1101 { 6, 240, 58 },
1102 { 4, 267, 66 },
1103 { 2, 400, 100 },
1104 { 0, 500, 130 }
1105 };
1106 const struct ath5k_rate_table *rt =
1107 ath5k_hw_get_rate_table(sc->ah, mode);
1108 unsigned int i, j;
1109
1110 BUG_ON(rt == NULL);
1111
1112 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1113 for (i = 0; i < 32; i++) {
1114 u8 ix = rt->rate_code_to_index[i];
1115 if (ix == 0xff) {
1116 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1117 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1118 continue;
1119 }
1120 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1121 if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation ==
1122 IEEE80211_RATE_OFDM)
1123 sc->hwmap[i].txflags |=
1124 IEEE80211_RADIOTAP_F_SHORTPRE;
1125 /* receive frames include FCS */
1126 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1127 IEEE80211_RADIOTAP_F_FCS;
1128 /* setup blink rate table to avoid per-packet lookup */
1129 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1130 if (blinkrates[j].rate == /* XXX why 7f? */
1131 (rt->rates[ix].dot11_rate&0x7f))
1132 break;
1133
1134 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1135 timeOn);
1136 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1137 timeOff);
1138 }
1139 }
1140
1141 sc->curmode = mode;
1142}
1143
1144static void
1145ath5k_mode_setup(struct ath5k_softc *sc)
1146{
1147 struct ath5k_hw *ah = sc->ah;
1148 u32 rfilt;
1149
1150 /* configure rx filter */
1151 rfilt = sc->filter_flags;
1152 ath5k_hw_set_rx_filter(ah, rfilt);
1153
1154 if (ath5k_hw_hasbssidmask(ah))
1155 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1156
1157 /* configure operational mode */
1158 ath5k_hw_set_opmode(ah);
1159
1160 ath5k_hw_set_mcast_filter(ah, 0, 0);
1161 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1162}
1163
1164
1165
1166
1167/***************\
1168* Buffers setup *
1169\***************/
1170
1171static int
1172ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1173{
1174 struct ath5k_hw *ah = sc->ah;
1175 struct sk_buff *skb = bf->skb;
1176 struct ath5k_desc *ds;
1177
1178 if (likely(skb == NULL)) {
1179 unsigned int off;
1180
1181 /*
1182 * Allocate buffer with headroom_needed space for the
1183 * fake physical layer header at the start.
1184 */
1185 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1186 if (unlikely(skb == NULL)) {
1187 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1188 sc->rxbufsize + sc->cachelsz - 1);
1189 return -ENOMEM;
1190 }
1191 /*
1192 * Cache-line-align. This is important (for the
1193 * 5210 at least) as not doing so causes bogus data
1194 * in rx'd frames.
1195 */
1196 off = ((unsigned long)skb->data) % sc->cachelsz;
1197 if (off != 0)
1198 skb_reserve(skb, sc->cachelsz - off);
1199
1200 bf->skb = skb;
1201 bf->skbaddr = pci_map_single(sc->pdev,
1202 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1203 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1204 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1205 dev_kfree_skb(skb);
1206 bf->skb = NULL;
1207 return -ENOMEM;
1208 }
1209 }
1210
1211 /*
1212 * Setup descriptors. For receive we always terminate
1213 * the descriptor list with a self-linked entry so we'll
1214 * not get overrun under high load (as can happen with a
1215 * 5212 when ANI processing enables PHY error frames).
1216 *
1217 * To insure the last descriptor is self-linked we create
1218 * each descriptor as self-linked and add it to the end. As
1219 * each additional descriptor is added the previous self-linked
1220 * entry is ``fixed'' naturally. This should be safe even
1221 * if DMA is happening. When processing RX interrupts we
1222 * never remove/process the last, self-linked, entry on the
1223 * descriptor list. This insures the hardware always has
1224 * someplace to write a new frame.
1225 */
1226 ds = bf->desc;
1227 ds->ds_link = bf->daddr; /* link to self */
1228 ds->ds_data = bf->skbaddr;
1229 ath5k_hw_setup_rx_desc(ah, ds,
1230 skb_tailroom(skb), /* buffer size */
1231 0);
1232
1233 if (sc->rxlink != NULL)
1234 *sc->rxlink = bf->daddr;
1235 sc->rxlink = &ds->ds_link;
1236 return 0;
1237}
1238
1239static int
1240ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1241 struct ieee80211_tx_control *ctl)
1242{
1243 struct ath5k_hw *ah = sc->ah;
1244 struct ath5k_txq *txq = sc->txq;
1245 struct ath5k_desc *ds = bf->desc;
1246 struct sk_buff *skb = bf->skb;
1247 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1248 int ret;
1249
1250 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1251 bf->ctl = *ctl;
1252 /* XXX endianness */
1253 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1254 PCI_DMA_TODEVICE);
1255
1256 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1257 flags |= AR5K_TXDESC_NOACK;
1258
1259 pktlen = skb->len + FCS_LEN;
1260
1261 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1262 keyidx = ctl->key_idx;
1263 pktlen += ctl->icv_len;
1264 }
1265
1266 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1267 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1268 (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0);
1269 if (ret)
1270 goto err_unmap;
1271
1272 ds->ds_link = 0;
1273 ds->ds_data = bf->skbaddr;
1274
1275 spin_lock_bh(&txq->lock);
1276 list_add_tail(&bf->list, &txq->q);
1277 sc->tx_stats.data[txq->qnum].len++;
1278 if (txq->link == NULL) /* is this first packet? */
1279 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1280 else /* no, so only link it */
1281 *txq->link = bf->daddr;
1282
1283 txq->link = &ds->ds_link;
1284 ath5k_hw_tx_start(ah, txq->qnum);
1285 spin_unlock_bh(&txq->lock);
1286
1287 return 0;
1288err_unmap:
1289 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1290 return ret;
1291}
1292
1293/*******************\
1294* Descriptors setup *
1295\*******************/
1296
1297static int
1298ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1299{
1300 struct ath5k_desc *ds;
1301 struct ath5k_buf *bf;
1302 dma_addr_t da;
1303 unsigned int i;
1304 int ret;
1305
1306 /* allocate descriptors */
1307 sc->desc_len = sizeof(struct ath5k_desc) *
1308 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1309 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1310 if (sc->desc == NULL) {
1311 ATH5K_ERR(sc, "can't allocate descriptors\n");
1312 ret = -ENOMEM;
1313 goto err;
1314 }
1315 ds = sc->desc;
1316 da = sc->desc_daddr;
1317 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1318 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1319
1320 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1321 sizeof(struct ath5k_buf), GFP_KERNEL);
1322 if (bf == NULL) {
1323 ATH5K_ERR(sc, "can't allocate bufptr\n");
1324 ret = -ENOMEM;
1325 goto err_free;
1326 }
1327 sc->bufptr = bf;
1328
1329 INIT_LIST_HEAD(&sc->rxbuf);
1330 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1331 bf->desc = ds;
1332 bf->daddr = da;
1333 list_add_tail(&bf->list, &sc->rxbuf);
1334 }
1335
1336 INIT_LIST_HEAD(&sc->txbuf);
1337 sc->txbuf_len = ATH_TXBUF;
1338 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1339 da += sizeof(*ds)) {
1340 bf->desc = ds;
1341 bf->daddr = da;
1342 list_add_tail(&bf->list, &sc->txbuf);
1343 }
1344
1345 /* beacon buffer */
1346 bf->desc = ds;
1347 bf->daddr = da;
1348 sc->bbuf = bf;
1349
1350 return 0;
1351err_free:
1352 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1353err:
1354 sc->desc = NULL;
1355 return ret;
1356}
1357
1358static void
1359ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1360{
1361 struct ath5k_buf *bf;
1362
1363 ath5k_txbuf_free(sc, sc->bbuf);
1364 list_for_each_entry(bf, &sc->txbuf, list)
1365 ath5k_txbuf_free(sc, bf);
1366 list_for_each_entry(bf, &sc->rxbuf, list)
1367 ath5k_txbuf_free(sc, bf);
1368
1369 /* Free memory associated with all descriptors */
1370 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1371
1372 kfree(sc->bufptr);
1373 sc->bufptr = NULL;
1374}
1375
1376
1377
1378
1379
1380/**************\
1381* Queues setup *
1382\**************/
1383
1384static struct ath5k_txq *
1385ath5k_txq_setup(struct ath5k_softc *sc,
1386 int qtype, int subtype)
1387{
1388 struct ath5k_hw *ah = sc->ah;
1389 struct ath5k_txq *txq;
1390 struct ath5k_txq_info qi = {
1391 .tqi_subtype = subtype,
1392 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1393 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1394 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1395 };
1396 int qnum;
1397
1398 /*
1399 * Enable interrupts only for EOL and DESC conditions.
1400 * We mark tx descriptors to receive a DESC interrupt
1401 * when a tx queue gets deep; otherwise waiting for the
1402 * EOL to reap descriptors. Note that this is done to
1403 * reduce interrupt load and this only defers reaping
1404 * descriptors, never transmitting frames. Aside from
1405 * reducing interrupts this also permits more concurrency.
1406 * The only potential downside is if the tx queue backs
1407 * up in which case the top half of the kernel may backup
1408 * due to a lack of tx descriptors.
1409 */
1410 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1411 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1412 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1413 if (qnum < 0) {
1414 /*
1415 * NB: don't print a message, this happens
1416 * normally on parts with too few tx queues
1417 */
1418 return ERR_PTR(qnum);
1419 }
1420 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1421 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1422 qnum, ARRAY_SIZE(sc->txqs));
1423 ath5k_hw_release_tx_queue(ah, qnum);
1424 return ERR_PTR(-EINVAL);
1425 }
1426 txq = &sc->txqs[qnum];
1427 if (!txq->setup) {
1428 txq->qnum = qnum;
1429 txq->link = NULL;
1430 INIT_LIST_HEAD(&txq->q);
1431 spin_lock_init(&txq->lock);
1432 txq->setup = true;
1433 }
1434 return &sc->txqs[qnum];
1435}
1436
1437static int
1438ath5k_beaconq_setup(struct ath5k_hw *ah)
1439{
1440 struct ath5k_txq_info qi = {
1441 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1442 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1443 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1444 /* NB: for dynamic turbo, don't enable any other interrupts */
1445 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1446 };
1447
1448 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1449}
1450
1451static int
1452ath5k_beaconq_config(struct ath5k_softc *sc)
1453{
1454 struct ath5k_hw *ah = sc->ah;
1455 struct ath5k_txq_info qi;
1456 int ret;
1457
1458 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1459 if (ret)
1460 return ret;
6d91e1d8 1461 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1462 /*
1463 * Always burst out beacon and CAB traffic
1464 * (aifs = cwmin = cwmax = 0)
1465 */
1466 qi.tqi_aifs = 0;
1467 qi.tqi_cw_min = 0;
1468 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1469 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1470 /*
1471 * Adhoc mode; backoff between 0 and (2 * cw_min).
1472 */
1473 qi.tqi_aifs = 0;
1474 qi.tqi_cw_min = 0;
1475 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1476 }
1477
6d91e1d8
BR		 1478 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1479 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1480 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1481
fa1c114f
JS		 1482 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1483 if (ret) {
1484 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1485 "hardware queue!\n", __func__);
1486 return ret;
1487 }
1488
1489 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1490}
1491
1492static void
1493ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1494{
1495 struct ath5k_buf *bf, *bf0;
1496
1497 /*
1498 * NB: this assumes output has been stopped and
1499 * we do not need to block ath5k_tx_tasklet
1500 */
1501 spin_lock_bh(&txq->lock);
1502 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1503 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1504 bf->desc));
1505
1506 ath5k_txbuf_free(sc, bf);
1507
1508 spin_lock_bh(&sc->txbuflock);
1509 sc->tx_stats.data[txq->qnum].len--;
1510 list_move_tail(&bf->list, &sc->txbuf);
1511 sc->txbuf_len++;
1512 spin_unlock_bh(&sc->txbuflock);
1513 }
1514 txq->link = NULL;
1515 spin_unlock_bh(&txq->lock);
1516}
1517
1518/*
1519 * Drain the transmit queues and reclaim resources.
1520 */
1521static void
1522ath5k_txq_cleanup(struct ath5k_softc *sc)
1523{
1524 struct ath5k_hw *ah = sc->ah;
1525 unsigned int i;
1526
1527 /* XXX return value */
1528 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1529 /* don't touch the hardware if marked invalid */
1530 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1531 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1532 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1533 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1534 if (sc->txqs[i].setup) {
1535 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1536 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1537 "link %p\n",
1538 sc->txqs[i].qnum,
1539 ath5k_hw_get_tx_buf(ah,
1540 sc->txqs[i].qnum),
1541 sc->txqs[i].link);
1542 }
1543 }
1544 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1545
1546 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1547 if (sc->txqs[i].setup)
1548 ath5k_txq_drainq(sc, &sc->txqs[i]);
1549}
1550
1551static void
1552ath5k_txq_release(struct ath5k_softc *sc)
1553{
1554 struct ath5k_txq *txq = sc->txqs;
1555 unsigned int i;
1556
1557 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1558 if (txq->setup) {
1559 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1560 txq->setup = false;
1561 }
1562}
1563
1564
1565
1566
1567/*************\
1568* RX Handling *
1569\*************/
1570
1571/*
1572 * Enable the receive h/w following a reset.
1573 */
1574static int
1575ath5k_rx_start(struct ath5k_softc *sc)
1576{
1577 struct ath5k_hw *ah = sc->ah;
1578 struct ath5k_buf *bf;
1579 int ret;
1580
1581 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1582
1583 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1584 sc->cachelsz, sc->rxbufsize);
1585
1586 sc->rxlink = NULL;
1587
1588 spin_lock_bh(&sc->rxbuflock);
1589 list_for_each_entry(bf, &sc->rxbuf, list) {
1590 ret = ath5k_rxbuf_setup(sc, bf);
1591 if (ret != 0) {
1592 spin_unlock_bh(&sc->rxbuflock);
1593 goto err;
1594 }
1595 }
1596 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1597 spin_unlock_bh(&sc->rxbuflock);
1598
1599 ath5k_hw_put_rx_buf(ah, bf->daddr);
1600 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1601 ath5k_mode_setup(sc); /* set filters, etc. */
1602 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1603
1604 return 0;
1605err:
1606 return ret;
1607}
1608
1609/*
1610 * Disable the receive h/w in preparation for a reset.
1611 */
1612static void
1613ath5k_rx_stop(struct ath5k_softc *sc)
1614{
1615 struct ath5k_hw *ah = sc->ah;
1616
1617 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1618 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1619 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1620 mdelay(3); /* 3ms is long enough for 1 frame */
1621
1622 ath5k_debug_printrxbuffs(sc, ah);
1623
1624 sc->rxlink = NULL; /* just in case */
1625}
1626
1627static unsigned int
1628ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1629 struct sk_buff *skb)
1630{
1631 struct ieee80211_hdr *hdr = (void *)skb->data;
1632 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1633
1634 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1635 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1636 return RX_FLAG_DECRYPTED;
1637
1638 /* Apparently when a default key is used to decrypt the packet
1639 the hw does not set the index used to decrypt. In such cases
1640 get the index from the packet. */
1641 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1642 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1643 skb->len >= hlen + 4) {
1644 keyix = skb->data[hlen + 3] >> 6;
1645
1646 if (test_bit(keyix, sc->keymap))
1647 return RX_FLAG_DECRYPTED;
1648 }
1649
1650 return 0;
1651}
1652
036cd1ec
BR		 1653
1654static void
1655ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1656{
1657 u32 hw_tu;
1658 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1659
1660 if ((mgmt->frame_control & IEEE80211_FCTL_FTYPE) ==
1661 IEEE80211_FTYPE_MGMT &&
1662 (mgmt->frame_control & IEEE80211_FCTL_STYPE) ==
1663 IEEE80211_STYPE_BEACON &&
1664 mgmt->u.beacon.capab_info & WLAN_CAPABILITY_IBSS &&
1665 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1666 /*
1667 * Received an IBSS beacon with the same BSSID. Hardware might
1668 * have updated the TSF, check if we need to update timers.
1669 */
1670 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1671 if (hw_tu >= sc->nexttbtt) {
1672 ath5k_beacon_update_timers(sc,
1673 mgmt->u.beacon.timestamp);
1674 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1675 "detected HW merge from received beacon\n");
1676 }
1677 }
1678}
1679
1680
fa1c114f
JS		 1681static void
1682ath5k_tasklet_rx(unsigned long data)
1683{
1684 struct ieee80211_rx_status rxs = {};
1685 struct sk_buff *skb;
1686 struct ath5k_softc *sc = (void *)data;
1687 struct ath5k_buf *bf;
1688 struct ath5k_desc *ds;
1689 u16 len;
1690 u8 stat;
1691 int ret;
1692 int hdrlen;
1693 int pad;
1694
1695 spin_lock(&sc->rxbuflock);
1696 do {
1697 if (unlikely(list_empty(&sc->rxbuf))) {
1698 ATH5K_WARN(sc, "empty rx buf pool\n");
1699 break;
1700 }
1701 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1702 BUG_ON(bf->skb == NULL);
1703 skb = bf->skb;
1704 ds = bf->desc;
1705
1706 /* TODO only one segment */
1707 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1708 sc->desc_len, PCI_DMA_FROMDEVICE);
1709
1710 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1711 break;
1712
1713 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1714 if (unlikely(ret == -EINPROGRESS))
1715 break;
1716 else if (unlikely(ret)) {
1717 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1718 return;
1719 }
1720
1721 if (unlikely(ds->ds_rxstat.rs_more)) {
1722 ATH5K_WARN(sc, "unsupported jumbo\n");
1723 goto next;
1724 }
1725
1726 stat = ds->ds_rxstat.rs_status;
1727 if (unlikely(stat)) {
1728 if (stat & AR5K_RXERR_PHY)
1729 goto next;
1730 if (stat & AR5K_RXERR_DECRYPT) {
1731 /*
1732 * Decrypt error. If the error occurred
1733 * because there was no hardware key, then
1734 * let the frame through so the upper layers
1735 * can process it. This is necessary for 5210
1736 * parts which have no way to setup a ``clear''
1737 * key cache entry.
1738 *
1739 * XXX do key cache faulting
1740 */
1741 if (ds->ds_rxstat.rs_keyix ==
1742 AR5K_RXKEYIX_INVALID &&
1743 !(stat & AR5K_RXERR_CRC))
1744 goto accept;
1745 }
1746 if (stat & AR5K_RXERR_MIC) {
1747 rxs.flag |= RX_FLAG_MMIC_ERROR;
1748 goto accept;
1749 }
1750
1751 /* let crypto-error packets fall through in MNTR */
1752 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1753 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1754 goto next;
1755 }
1756accept:
1757 len = ds->ds_rxstat.rs_datalen;
1758 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1759 PCI_DMA_FROMDEVICE);
1760 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1761 PCI_DMA_FROMDEVICE);
1762 bf->skb = NULL;
1763
1764 skb_put(skb, len);
1765
1766 /*
1767 * the hardware adds a padding to 4 byte boundaries between
1768 * the header and the payload data if the header length is
1769 * not multiples of 4 - remove it
1770 */
1771 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1772 if (hdrlen & 3) {
1773 pad = hdrlen % 4;
1774 memmove(skb->data + pad, skb->data, hdrlen);
1775 skb_pull(skb, pad);
1776 }
1777
c0e1899b
BR		 1778 /*
1779 * always extend the mac timestamp, since this information is
1780 * also needed for proper IBSS merging.
1781 *
1782 * XXX: it might be too late to do it here, since rs_tstamp is
1783 * 15bit only. that means TSF extension has to be done within
1784 * 32768usec (about 32ms). it might be necessary to move this to
1785 * the interrupt handler, like it is done in madwifi.
1786 */
1787 rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp);
1788 rxs.flag |= RX_FLAG_TSFT;
1789
fa1c114f
JS		 1790 rxs.freq = sc->curchan->freq;
1791 rxs.channel = sc->curchan->chan;
1792 rxs.phymode = sc->curmode;
1793
1794 /*
1795 * signal quality:
1796 * the names here are misleading and the usage of these
1797 * values by iwconfig makes it even worse
1798 */
1799 /* noise floor in dBm, from the last noise calibration */
1800 rxs.noise = sc->ah->ah_noise_floor;
1801 /* signal level in dBm */
1802 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1803 /*
1804 * "signal" is actually displayed as Link Quality by iwconfig
1805 * we provide a percentage based on rssi (assuming max rssi 64)
1806 */
1807 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1808
1809 rxs.antenna = ds->ds_rxstat.rs_antenna;
1810 rxs.rate = ds->ds_rxstat.rs_rate;
1811 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1812
1813 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1814
036cd1ec
BR		 1815 /* check beacons in IBSS mode */
1816 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1817 ath5k_check_ibss_hw_merge(sc, skb);
1818
fa1c114f
JS		 1819 __ieee80211_rx(sc->hw, skb, &rxs);
1820 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1821 ath5k_led_event(sc, ATH_LED_RX);
1822next:
1823 list_move_tail(&bf->list, &sc->rxbuf);
1824 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1825 spin_unlock(&sc->rxbuflock);
1826}
1827
1828
1829
1830
1831/*************\
1832* TX Handling *
1833\*************/
1834
1835static void
1836ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1837{
1838 struct ieee80211_tx_status txs = {};
1839 struct ath5k_buf *bf, *bf0;
1840 struct ath5k_desc *ds;
1841 struct sk_buff *skb;
1842 int ret;
1843
1844 spin_lock(&txq->lock);
1845 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1846 ds = bf->desc;
1847
1848 /* TODO only one segment */
1849 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1850 sc->desc_len, PCI_DMA_FROMDEVICE);
1851 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1852 if (unlikely(ret == -EINPROGRESS))
1853 break;
1854 else if (unlikely(ret)) {
1855 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1856 ret, txq->qnum);
1857 break;
1858 }
1859
1860 skb = bf->skb;
1861 bf->skb = NULL;
1862 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1863 PCI_DMA_TODEVICE);
1864
1865 txs.control = bf->ctl;
1866 txs.retry_count = ds->ds_txstat.ts_shortretry +
1867 ds->ds_txstat.ts_longretry / 6;
1868 if (unlikely(ds->ds_txstat.ts_status)) {
1869 sc->ll_stats.dot11ACKFailureCount++;
1870 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1871 txs.excessive_retries = 1;
1872 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1873 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1874 } else {
1875 txs.flags |= IEEE80211_TX_STATUS_ACK;
1876 txs.ack_signal = ds->ds_txstat.ts_rssi;
1877 }
1878
1879 ieee80211_tx_status(sc->hw, skb, &txs);
1880 sc->tx_stats.data[txq->qnum].count++;
1881
1882 spin_lock(&sc->txbuflock);
1883 sc->tx_stats.data[txq->qnum].len--;
1884 list_move_tail(&bf->list, &sc->txbuf);
1885 sc->txbuf_len++;
1886 spin_unlock(&sc->txbuflock);
1887 }
1888 if (likely(list_empty(&txq->q)))
1889 txq->link = NULL;
1890 spin_unlock(&txq->lock);
1891 if (sc->txbuf_len > ATH_TXBUF / 5)
1892 ieee80211_wake_queues(sc->hw);
1893}
1894
1895static void
1896ath5k_tasklet_tx(unsigned long data)
1897{
1898 struct ath5k_softc *sc = (void *)data;
1899
1900 ath5k_tx_processq(sc, sc->txq);
1901
1902 ath5k_led_event(sc, ATH_LED_TX);
1903}
1904
1905
1906
1907
1908/*****************\
1909* Beacon handling *
1910\*****************/
1911
1912/*
1913 * Setup the beacon frame for transmit.
1914 */
1915static int
1916ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1917 struct ieee80211_tx_control *ctl)
1918{
1919 struct sk_buff *skb = bf->skb;
1920 struct ath5k_hw *ah = sc->ah;
1921 struct ath5k_desc *ds;
1922 int ret, antenna = 0;
1923 u32 flags;
1924
1925 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1926 PCI_DMA_TODEVICE);
1927 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1928 "skbaddr %llx\n", skb, skb->data, skb->len,
1929 (unsigned long long)bf->skbaddr);
1930 if (pci_dma_mapping_error(bf->skbaddr)) {
1931 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1932 return -EIO;
1933 }
1934
1935 ds = bf->desc;
1936
1937 flags = AR5K_TXDESC_NOACK;
1938 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1939 ds->ds_link = bf->daddr; /* self-linked */
1940 flags |= AR5K_TXDESC_VEOL;
1941 /*
1942 * Let hardware handle antenna switching if txantenna is not set
1943 */
1944 } else {
1945 ds->ds_link = 0;
1946 /*
1947 * Switch antenna every 4 beacons if txantenna is not set
1948 * XXX assumes two antennas
1949 */
1950 if (antenna == 0)
1951 antenna = sc->bsent & 4 ? 2 : 1;
1952 }
1953
1954 ds->ds_data = bf->skbaddr;
1955 ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN,
1956 ieee80211_get_hdrlen_from_skb(skb),
1957 AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1,
1958 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
1959 if (ret)
1960 goto err_unmap;
1961
1962 return 0;
1963err_unmap:
1964 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1965 return ret;
1966}
1967
1968/*
1969 * Transmit a beacon frame at SWBA. Dynamic updates to the
1970 * frame contents are done as needed and the slot time is
1971 * also adjusted based on current state.
1972 *
1973 * this is usually called from interrupt context (ath5k_intr())
1974 * but also from ath5k_beacon_config() in IBSS mode which in turn
1975 * can be called from a tasklet and user context
1976 */
1977static void
1978ath5k_beacon_send(struct ath5k_softc *sc)
1979{
1980 struct ath5k_buf *bf = sc->bbuf;
1981 struct ath5k_hw *ah = sc->ah;
1982
be9b7259 1983 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1984
1985 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1986 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1987 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1988 return;
1989 }
1990 /*
1991 * Check if the previous beacon has gone out. If
1992 * not don't don't try to post another, skip this
1993 * period and wait for the next. Missed beacons
1994 * indicate a problem and should not occur. If we
1995 * miss too many consecutive beacons reset the device.
1996 */
1997 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1998 sc->bmisscount++;
be9b7259 1999 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2000 "missed %u consecutive beacons\n", sc->bmisscount);
2001 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2002 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2003 "stuck beacon time (%u missed)\n",
2004 sc->bmisscount);
2005 tasklet_schedule(&sc->restq);
2006 }
2007 return;
2008 }
2009 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2010 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2011 "resume beacon xmit after %u misses\n",
2012 sc->bmisscount);
2013 sc->bmisscount = 0;
2014 }
2015
2016 /*
2017 * Stop any current dma and put the new frame on the queue.
2018 * This should never fail since we check above that no frames
2019 * are still pending on the queue.
2020 */
2021 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2022 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2023 /* NB: hw still stops DMA, so proceed */
2024 }
2025 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2026 PCI_DMA_TODEVICE);
2027
2028 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2029 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2030 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2031 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2032
2033 sc->bsent++;
2034}
2035
2036
9804b98d
BR		 2037/**
2038 * ath5k_beacon_update_timers - update beacon timers
2039 *
2040 * @sc: struct ath5k_softc pointer we are operating on
2041 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2042 * beacon timer update based on the current HW TSF.
2043 *
2044 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2045 * of a received beacon or the current local hardware TSF and write it to the
2046 * beacon timer registers.
2047 *
2048 * This is called in a variety of situations, e.g. when a beacon is received,
2049 * when a HW merge has been detected, but also when an new IBSS is created or
2050 * when we otherwise know we have to update the timers, but we keep it in this
2051 * function to have it all together in one place.
2052 */
fa1c114f 2053static void
9804b98d 2054ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2055{
2056 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2057 u32 nexttbtt, intval, hw_tu, bc_tu;
2058 u64 hw_tsf;
fa1c114f
JS		 2059
2060 intval = sc->bintval & AR5K_BEACON_PERIOD;
2061 if (WARN_ON(!intval))
2062 return;
2063
9804b98d
BR		 2064 /* beacon TSF converted to TU */
2065 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2066
9804b98d
BR		 2067 /* current TSF converted to TU */
2068 hw_tsf = ath5k_hw_get_tsf64(ah);
2069 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2070
9804b98d
BR		 2071#define FUDGE 3
2072 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2073 if (bc_tsf == -1) {
2074 /*
2075 * no beacons received, called internally.
2076 * just need to refresh timers based on HW TSF.
2077 */
2078 nexttbtt = roundup(hw_tu + FUDGE, intval);
2079 } else if (bc_tsf == 0) {
2080 /*
2081 * no beacon received, probably called by ath5k_reset_tsf().
2082 * reset TSF to start with 0.
2083 */
2084 nexttbtt = intval;
2085 intval |= AR5K_BEACON_RESET_TSF;
2086 } else if (bc_tsf > hw_tsf) {
2087 /*
2088 * beacon received, SW merge happend but HW TSF not yet updated.
2089 * not possible to reconfigure timers yet, but next time we
2090 * receive a beacon with the same BSSID, the hardware will
2091 * automatically update the TSF and then we need to reconfigure
2092 * the timers.
2093 */
2094 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2095 "need to wait for HW TSF sync\n");
2096 return;
2097 } else {
2098 /*
2099 * most important case for beacon synchronization between STA.
2100 *
2101 * beacon received and HW TSF has been already updated by HW.
2102 * update next TBTT based on the TSF of the beacon, but make
2103 * sure it is ahead of our local TSF timer.
2104 */
2105 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2106 }
2107#undef FUDGE
fa1c114f 2108
036cd1ec
BR		 2109 sc->nexttbtt = nexttbtt;
2110
fa1c114f 2111 intval |= AR5K_BEACON_ENA;
fa1c114f 2112 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2113
2114 /*
2115 * debugging output last in order to preserve the time critical aspect
2116 * of this function
2117 */
2118 if (bc_tsf == -1)
2119 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2120 "reconfigured timers based on HW TSF\n");
2121 else if (bc_tsf == 0)
2122 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2123 "reset HW TSF and timers\n");
2124 else
2125 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2126 "updated timers based on beacon TSF\n");
2127
2128 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2129 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2130 bc_tsf, hw_tsf, bc_tu, hw_tu, nexttbtt);
2131 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2132 intval & AR5K_BEACON_PERIOD,
2133 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2134 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2135}
2136
2137
036cd1ec
BR		 2138/**
2139 * ath5k_beacon_config - Configure the beacon queues and interrupts
2140 *
2141 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2142 *
2143 * When operating in station mode we want to receive a BMISS interrupt when we
2144 * stop seeing beacons from the AP we've associated with so we can look for
2145 * another AP to associate with.
2146 *
036cd1ec
BR		 2147 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2148 * interrupts to detect HW merges only.
2149 *
2150 * AP mode is missing.
fa1c114f
JS		 2151 */
2152static void
2153ath5k_beacon_config(struct ath5k_softc *sc)
2154{
2155 struct ath5k_hw *ah = sc->ah;
2156
2157 ath5k_hw_set_intr(ah, 0);
2158 sc->bmisscount = 0;
2159
2160 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2161 sc->imask |= AR5K_INT_BMISS;
2162 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2163 /*
036cd1ec
BR		 2164 * In IBSS mode we use a self-linked tx descriptor and let the
2165 * hardware send the beacons automatically. We have to load it
fa1c114f 2166 * only once here.
036cd1ec
BR		 2167 * We use the SWBA interrupt only to keep track of the beacon
2168 * timers in order to detect HW merges (automatic TSF updates).
fa1c114f
JS		 2169 */
2170 ath5k_beaconq_config(sc);
fa1c114f 2171
036cd1ec
BR		 2172 sc->imask |= AR5K_INT_SWBA;
2173
2174 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2175 ath5k_beacon_send(sc);
2176 }
2177 /* TODO else AP */
2178
2179 ath5k_hw_set_intr(ah, sc->imask);
2180}
2181
2182
2183/********************\
2184* Interrupt handling *
2185\********************/
2186
2187static int
2188ath5k_init(struct ath5k_softc *sc)
2189{
2190 int ret;
2191
2192 mutex_lock(&sc->lock);
2193
2194 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2195
2196 /*
2197 * Stop anything previously setup. This is safe
2198 * no matter this is the first time through or not.
2199 */
2200 ath5k_stop_locked(sc);
2201
2202 /*
2203 * The basic interface to setting the hardware in a good
2204 * state is ``reset''. On return the hardware is known to
2205 * be powered up and with interrupts disabled. This must
2206 * be followed by initialization of the appropriate bits
2207 * and then setup of the interrupt mask.
2208 */
2209 sc->curchan = sc->hw->conf.chan;
2210 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2211 if (ret) {
2212 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2213 goto done;
2214 }
2215 /*
2216 * This is needed only to setup initial state
2217 * but it's best done after a reset.
2218 */
2219 ath5k_hw_set_txpower_limit(sc->ah, 0);
2220
2221 /*
2222 * Setup the hardware after reset: the key cache
2223 * is filled as needed and the receive engine is
2224 * set going. Frame transmit is handled entirely
2225 * in the frame output path; there's nothing to do
2226 * here except setup the interrupt mask.
2227 */
2228 ret = ath5k_rx_start(sc);
2229 if (ret)
2230 goto done;
2231
2232 /*
2233 * Enable interrupts.
2234 */
2235 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2236 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2237
2238 ath5k_hw_set_intr(sc->ah, sc->imask);
2239 /* Set ack to be sent at low bit-rates */
2240 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2241
2242 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2243 msecs_to_jiffies(ath5k_calinterval * 1000)));
2244
2245 ret = 0;
2246done:
2247 mutex_unlock(&sc->lock);
2248 return ret;
2249}
2250
2251static int
2252ath5k_stop_locked(struct ath5k_softc *sc)
2253{
2254 struct ath5k_hw *ah = sc->ah;
2255
2256 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2257 test_bit(ATH_STAT_INVALID, sc->status));
2258
2259 /*
2260 * Shutdown the hardware and driver:
2261 * stop output from above
2262 * disable interrupts
2263 * turn off timers
2264 * turn off the radio
2265 * clear transmit machinery
2266 * clear receive machinery
2267 * drain and release tx queues
2268 * reclaim beacon resources
2269 * power down hardware
2270 *
2271 * Note that some of this work is not possible if the
2272 * hardware is gone (invalid).
2273 */
2274 ieee80211_stop_queues(sc->hw);
2275
2276 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2277 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2278 del_timer_sync(&sc->led_tim);
2279 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2280 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2281 }
2282 ath5k_hw_set_intr(ah, 0);
2283 }
2284 ath5k_txq_cleanup(sc);
2285 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2286 ath5k_rx_stop(sc);
2287 ath5k_hw_phy_disable(ah);
2288 } else
2289 sc->rxlink = NULL;
2290
2291 return 0;
2292}
2293
2294/*
2295 * Stop the device, grabbing the top-level lock to protect
2296 * against concurrent entry through ath5k_init (which can happen
2297 * if another thread does a system call and the thread doing the
2298 * stop is preempted).
2299 */
2300static int
2301ath5k_stop_hw(struct ath5k_softc *sc)
2302{
2303 int ret;
2304
2305 mutex_lock(&sc->lock);
2306 ret = ath5k_stop_locked(sc);
2307 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2308 /*
2309 * Set the chip in full sleep mode. Note that we are
2310 * careful to do this only when bringing the interface
2311 * completely to a stop. When the chip is in this state
2312 * it must be carefully woken up or references to
2313 * registers in the PCI clock domain may freeze the bus
2314 * (and system). This varies by chip and is mostly an
2315 * issue with newer parts that go to sleep more quickly.
2316 */
2317 if (sc->ah->ah_mac_srev >= 0x78) {
2318 /*
2319 * XXX
2320 * don't put newer MAC revisions > 7.8 to sleep because
2321 * of the above mentioned problems
2322 */
2323 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2324 "not putting device to sleep\n");
2325 } else {
2326 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2327 "putting device to full sleep\n");
2328 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2329 }
2330 }
2331 ath5k_txbuf_free(sc, sc->bbuf);
2332 mutex_unlock(&sc->lock);
2333
2334 del_timer_sync(&sc->calib_tim);
2335
2336 return ret;
2337}
2338
2339static irqreturn_t
2340ath5k_intr(int irq, void *dev_id)
2341{
2342 struct ath5k_softc *sc = dev_id;
2343 struct ath5k_hw *ah = sc->ah;
2344 enum ath5k_int status;
2345 unsigned int counter = 1000;
2346
2347 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2348 !ath5k_hw_is_intr_pending(ah)))
2349 return IRQ_NONE;
2350
2351 do {
2352 /*
2353 * Figure out the reason(s) for the interrupt. Note
2354 * that get_isr returns a pseudo-ISR that may include
2355 * bits we haven't explicitly enabled so we mask the
2356 * value to insure we only process bits we requested.
2357 */
2358 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2359 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2360 status, sc->imask);
2361 status &= sc->imask; /* discard unasked for bits */
2362 if (unlikely(status & AR5K_INT_FATAL)) {
2363 /*
2364 * Fatal errors are unrecoverable.
2365 * Typically these are caused by DMA errors.
2366 */
2367 tasklet_schedule(&sc->restq);
2368 } else if (unlikely(status & AR5K_INT_RXORN)) {
2369 tasklet_schedule(&sc->restq);
2370 } else {
2371 if (status & AR5K_INT_SWBA) {
2372 /*
2373 * Software beacon alert--time to send a beacon.
2374 * Handle beacon transmission directly; deferring
2375 * this is too slow to meet timing constraints
2376 * under load.
036cd1ec
BR		 2377 *
2378 * In IBSS mode we use this interrupt just to
2379 * keep track of the next TBTT (target beacon
2380 * transmission time) in order to detect hardware
2381 * merges (TSF updates).
fa1c114f 2382 */
036cd1ec
BR		 2383 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2384 /* XXX: only if VEOL suppported */
2385 u64 tsf = ath5k_hw_get_tsf64(ah);
2386 sc->nexttbtt += sc->bintval;
2387 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2388 "SWBA nexttbtt: %x hw_tu: %x "
2389 "TSF: %llx\n",
2390 sc->nexttbtt,
2391 TSF_TO_TU(tsf), tsf);
2392 } else {
2393 ath5k_beacon_send(sc);
2394 }
fa1c114f
JS		 2395 }
2396 if (status & AR5K_INT_RXEOL) {
2397 /*
2398 * NB: the hardware should re-read the link when
2399 * RXE bit is written, but it doesn't work at
2400 * least on older hardware revs.
2401 */
2402 sc->rxlink = NULL;
2403 }
2404 if (status & AR5K_INT_TXURN) {
2405 /* bump tx trigger level */
2406 ath5k_hw_update_tx_triglevel(ah, true);
2407 }
2408 if (status & AR5K_INT_RX)
2409 tasklet_schedule(&sc->rxtq);
2410 if (status & AR5K_INT_TX)
2411 tasklet_schedule(&sc->txtq);
2412 if (status & AR5K_INT_BMISS) {
2413 }
2414 if (status & AR5K_INT_MIB) {
2415 /* TODO */
2416 }
2417 }
2418 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2419
2420 if (unlikely(!counter))
2421 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2422
2423 return IRQ_HANDLED;
2424}
2425
2426static void
2427ath5k_tasklet_reset(unsigned long data)
2428{
2429 struct ath5k_softc *sc = (void *)data;
2430
2431 ath5k_reset(sc->hw);
2432}
2433
2434/*
2435 * Periodically recalibrate the PHY to account
2436 * for temperature/environment changes.
2437 */
2438static void
2439ath5k_calibrate(unsigned long data)
2440{
2441 struct ath5k_softc *sc = (void *)data;
2442 struct ath5k_hw *ah = sc->ah;
2443
2444 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2445 sc->curchan->chan, sc->curchan->val);
2446
2447 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2448 /*
2449 * Rfgain is out of bounds, reset the chip
2450 * to load new gain values.
2451 */
2452 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2453 ath5k_reset(sc->hw);
2454 }
2455 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2456 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2457 sc->curchan->chan);
2458
2459 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2460 msecs_to_jiffies(ath5k_calinterval * 1000)));
2461}
2462
2463
2464
2465/***************\
2466* LED functions *
2467\***************/
2468
2469static void
2470ath5k_led_off(unsigned long data)
2471{
2472 struct ath5k_softc *sc = (void *)data;
2473
2474 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2475 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2476 else {
2477 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2478 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2479 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2480 }
2481}
2482
2483/*
2484 * Blink the LED according to the specified on/off times.
2485 */
2486static void
2487ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2488 unsigned int off)
2489{
2490 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2491 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2492 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2493 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2494 sc->led_off = off;
2495 mod_timer(&sc->led_tim, jiffies + on);
2496}
2497
2498static void
2499ath5k_led_event(struct ath5k_softc *sc, int event)
2500{
2501 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2502 return;
2503 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2504 return; /* don't interrupt active blink */
2505 switch (event) {
2506 case ATH_LED_TX:
2507 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2508 sc->hwmap[sc->led_txrate].ledoff);
2509 break;
2510 case ATH_LED_RX:
2511 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2512 sc->hwmap[sc->led_rxrate].ledoff);
2513 break;
2514 }
2515}
2516
2517
2518
2519
2520/********************\
2521* Mac80211 functions *
2522\********************/
2523
2524static int
2525ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2526 struct ieee80211_tx_control *ctl)
2527{
2528 struct ath5k_softc *sc = hw->priv;
2529 struct ath5k_buf *bf;
2530 unsigned long flags;
2531 int hdrlen;
2532 int pad;
2533
2534 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2535
2536 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2537 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2538
2539 /*
2540 * the hardware expects the header padded to 4 byte boundaries
2541 * if this is not the case we add the padding after the header
2542 */
2543 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2544 if (hdrlen & 3) {
2545 pad = hdrlen % 4;
2546 if (skb_headroom(skb) < pad) {
2547 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2548 " headroom to pad %d\n", hdrlen, pad);
2549 return -1;
2550 }
2551 skb_push(skb, pad);
2552 memmove(skb->data, skb->data+pad, hdrlen);
2553 }
2554
2555 sc->led_txrate = ctl->tx_rate;
2556
2557 spin_lock_irqsave(&sc->txbuflock, flags);
2558 if (list_empty(&sc->txbuf)) {
2559 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2560 spin_unlock_irqrestore(&sc->txbuflock, flags);
2561 ieee80211_stop_queue(hw, ctl->queue);
2562 return -1;
2563 }
2564 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2565 list_del(&bf->list);
2566 sc->txbuf_len--;
2567 if (list_empty(&sc->txbuf))
2568 ieee80211_stop_queues(hw);
2569 spin_unlock_irqrestore(&sc->txbuflock, flags);
2570
2571 bf->skb = skb;
2572
2573 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2574 bf->skb = NULL;
2575 spin_lock_irqsave(&sc->txbuflock, flags);
2576 list_add_tail(&bf->list, &sc->txbuf);
2577 sc->txbuf_len++;
2578 spin_unlock_irqrestore(&sc->txbuflock, flags);
2579 dev_kfree_skb_any(skb);
2580 return 0;
2581 }
2582
2583 return 0;
2584}
2585
2586static int
2587ath5k_reset(struct ieee80211_hw *hw)
2588{
2589 struct ath5k_softc *sc = hw->priv;
2590 struct ath5k_hw *ah = sc->ah;
2591 int ret;
2592
2593 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2594 /*
2595 * Convert to a hw channel description with the flags
2596 * constrained to reflect the current operating mode.
2597 */
2598 sc->curchan = hw->conf.chan;
2599
2600 ath5k_hw_set_intr(ah, 0);
2601 ath5k_txq_cleanup(sc);
2602 ath5k_rx_stop(sc);
2603
2604 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2605 if (unlikely(ret)) {
2606 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2607 goto err;
2608 }
2609 ath5k_hw_set_txpower_limit(sc->ah, 0);
2610
2611 ret = ath5k_rx_start(sc);
2612 if (unlikely(ret)) {
2613 ATH5K_ERR(sc, "can't start recv logic\n");
2614 goto err;
2615 }
2616 /*
2617 * We may be doing a reset in response to an ioctl
2618 * that changes the channel so update any state that
2619 * might change as a result.
2620 *
2621 * XXX needed?
2622 */
2623/* ath5k_chan_change(sc, c); */
2624 ath5k_beacon_config(sc);
2625 /* intrs are started by ath5k_beacon_config */
2626
2627 ieee80211_wake_queues(hw);
2628
2629 return 0;
2630err:
2631 return ret;
2632}
2633
2634static int ath5k_start(struct ieee80211_hw *hw)
2635{
2636 return ath5k_init(hw->priv);
2637}
2638
2639static void ath5k_stop(struct ieee80211_hw *hw)
2640{
2641 ath5k_stop_hw(hw->priv);
2642}
2643
2644static int ath5k_add_interface(struct ieee80211_hw *hw,
2645 struct ieee80211_if_init_conf *conf)
2646{
2647 struct ath5k_softc *sc = hw->priv;
2648 int ret;
2649
2650 mutex_lock(&sc->lock);
32bfd35d 2651 if (sc->vif) {
fa1c114f
JS		 2652 ret = 0;
2653 goto end;
2654 }
2655
32bfd35d 2656 sc->vif = conf->vif;
fa1c114f
JS		 2657
2658 switch (conf->type) {
2659 case IEEE80211_IF_TYPE_STA:
2660 case IEEE80211_IF_TYPE_IBSS:
2661 case IEEE80211_IF_TYPE_MNTR:
2662 sc->opmode = conf->type;
2663 break;
2664 default:
2665 ret = -EOPNOTSUPP;
2666 goto end;
2667 }
2668 ret = 0;
2669end:
2670 mutex_unlock(&sc->lock);
2671 return ret;
2672}
2673
2674static void
2675ath5k_remove_interface(struct ieee80211_hw *hw,
2676 struct ieee80211_if_init_conf *conf)
2677{
2678 struct ath5k_softc *sc = hw->priv;
2679
2680 mutex_lock(&sc->lock);
32bfd35d 2681 if (sc->vif != conf->vif)
fa1c114f
JS		 2682 goto end;
2683
32bfd35d 2684 sc->vif = NULL;
fa1c114f
JS		 2685end:
2686 mutex_unlock(&sc->lock);
2687}
2688
2689static int
2690ath5k_config(struct ieee80211_hw *hw,
2691 struct ieee80211_conf *conf)
2692{
2693 struct ath5k_softc *sc = hw->priv;
2694
e535c1ac 2695 sc->bintval = conf->beacon_int;
fa1c114f
JS		 2696 ath5k_setcurmode(sc, conf->phymode);
2697
2698 return ath5k_chan_set(sc, conf->chan);
2699}
2700
2701static int
32bfd35d 2702ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2703 struct ieee80211_if_conf *conf)
2704{
2705 struct ath5k_softc *sc = hw->priv;
2706 struct ath5k_hw *ah = sc->ah;
2707 int ret;
2708
2709 /* Set to a reasonable value. Note that this will
2710 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2711 sc->bintval = 1000;
fa1c114f 2712 mutex_lock(&sc->lock);
32bfd35d 2713 if (sc->vif != vif) {
fa1c114f
JS		 2714 ret = -EIO;
2715 goto unlock;
2716 }
2717 if (conf->bssid) {
2718 /* Cache for later use during resets */
2719 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2720 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2721 * a clean way of letting us retrieve this yet. */
2722 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2723 }
2724 mutex_unlock(&sc->lock);
2725
2726 return ath5k_reset(hw);
2727unlock:
2728 mutex_unlock(&sc->lock);
2729 return ret;
2730}
2731
2732#define SUPPORTED_FIF_FLAGS \
2733 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2734 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2735 FIF_BCN_PRBRESP_PROMISC
2736/*
2737 * o always accept unicast, broadcast, and multicast traffic
2738 * o multicast traffic for all BSSIDs will be enabled if mac80211
2739 * says it should be
2740 * o maintain current state of phy ofdm or phy cck error reception.
2741 * If the hardware detects any of these type of errors then
2742 * ath5k_hw_get_rx_filter() will pass to us the respective
2743 * hardware filters to be able to receive these type of frames.
2744 * o probe request frames are accepted only when operating in
2745 * hostap, adhoc, or monitor modes
2746 * o enable promiscuous mode according to the interface state
2747 * o accept beacons:
2748 * - when operating in adhoc mode so the 802.11 layer creates
2749 * node table entries for peers,
2750 * - when operating in station mode for collecting rssi data when
2751 * the station is otherwise quiet, or
2752 * - when scanning
2753 */
2754static void ath5k_configure_filter(struct ieee80211_hw *hw,
2755 unsigned int changed_flags,
2756 unsigned int *new_flags,
2757 int mc_count, struct dev_mc_list *mclist)
2758{
2759 struct ath5k_softc *sc = hw->priv;
2760 struct ath5k_hw *ah = sc->ah;
2761 u32 mfilt[2], val, rfilt;
2762 u8 pos;
2763 int i;
2764
2765 mfilt[0] = 0;
2766 mfilt[1] = 0;
2767
2768 /* Only deal with supported flags */
2769 changed_flags &= SUPPORTED_FIF_FLAGS;
2770 *new_flags &= SUPPORTED_FIF_FLAGS;
2771
2772 /* If HW detects any phy or radar errors, leave those filters on.
2773 * Also, always enable Unicast, Broadcasts and Multicast
2774 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2775 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2776 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2777 AR5K_RX_FILTER_MCAST);
2778
2779 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2780 if (*new_flags & FIF_PROMISC_IN_BSS) {
2781 rfilt |= AR5K_RX_FILTER_PROM;
2782 __set_bit(ATH_STAT_PROMISC, sc->status);
2783 }
2784 else
2785 __clear_bit(ATH_STAT_PROMISC, sc->status);
2786 }
2787
2788 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2789 if (*new_flags & FIF_ALLMULTI) {
2790 mfilt[0] = ~0;
2791 mfilt[1] = ~0;
2792 } else {
2793 for (i = 0; i < mc_count; i++) {
2794 if (!mclist)
2795 break;
2796 /* calculate XOR of eight 6-bit values */
2797 val = LE_READ_4(mclist->dmi_addr + 0);
2798 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2799 val = LE_READ_4(mclist->dmi_addr + 3);
2800 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2801 pos &= 0x3f;
2802 mfilt[pos / 32] |= (1 << (pos % 32));
2803 /* XXX: we might be able to just do this instead,
2804 * but not sure, needs testing, if we do use this we'd
2805 * neet to inform below to not reset the mcast */
2806 /* ath5k_hw_set_mcast_filterindex(ah,
2807 * mclist->dmi_addr[5]); */
2808 mclist = mclist->next;
2809 }
2810 }
2811
2812 /* This is the best we can do */
2813 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2814 rfilt |= AR5K_RX_FILTER_PHYERR;
2815
2816 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2817 * and probes for any BSSID, this needs testing */
2818 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2819 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2820
2821 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2822 * set we should only pass on control frames for this
2823 * station. This needs testing. I believe right now this
2824 * enables *all* control frames, which is OK.. but
2825 * but we should see if we can improve on granularity */
2826 if (*new_flags & FIF_CONTROL)
2827 rfilt |= AR5K_RX_FILTER_CONTROL;
2828
2829 /* Additional settings per mode -- this is per ath5k */
2830
2831 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2832
2833 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2834 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2835 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2836 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2837 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2838 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2839 test_bit(ATH_STAT_PROMISC, sc->status))
2840 rfilt |= AR5K_RX_FILTER_PROM;
2841 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2842 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2843 rfilt |= AR5K_RX_FILTER_BEACON;
2844 }
2845
2846 /* Set filters */
2847 ath5k_hw_set_rx_filter(ah,rfilt);
2848
2849 /* Set multicast bits */
2850 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2851 /* Set the cached hw filter flags, this will alter actually
2852 * be set in HW */
2853 sc->filter_flags = rfilt;
2854}
2855
2856static int
2857ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2858 const u8 *local_addr, const u8 *addr,
2859 struct ieee80211_key_conf *key)
2860{
2861 struct ath5k_softc *sc = hw->priv;
2862 int ret = 0;
2863
2864 switch(key->alg) {
2865 case ALG_WEP:
2866 break;
2867 case ALG_TKIP:
2868 case ALG_CCMP:
2869 return -EOPNOTSUPP;
2870 default:
2871 WARN_ON(1);
2872 return -EINVAL;
2873 }
2874
2875 mutex_lock(&sc->lock);
2876
2877 switch (cmd) {
2878 case SET_KEY:
2879 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2880 if (ret) {
2881 ATH5K_ERR(sc, "can't set the key\n");
2882 goto unlock;
2883 }
2884 __set_bit(key->keyidx, sc->keymap);
2885 key->hw_key_idx = key->keyidx;
2886 break;
2887 case DISABLE_KEY:
2888 ath5k_hw_reset_key(sc->ah, key->keyidx);
2889 __clear_bit(key->keyidx, sc->keymap);
2890 break;
2891 default:
2892 ret = -EINVAL;
2893 goto unlock;
2894 }
2895
2896unlock:
2897 mutex_unlock(&sc->lock);
2898 return ret;
2899}
2900
2901static int
2902ath5k_get_stats(struct ieee80211_hw *hw,
2903 struct ieee80211_low_level_stats *stats)
2904{
2905 struct ath5k_softc *sc = hw->priv;
2906
2907 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2908
2909 return 0;
2910}
2911
2912static int
2913ath5k_get_tx_stats(struct ieee80211_hw *hw,
2914 struct ieee80211_tx_queue_stats *stats)
2915{
2916 struct ath5k_softc *sc = hw->priv;
2917
2918 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2919
2920 return 0;
2921}
2922
2923static u64
2924ath5k_get_tsf(struct ieee80211_hw *hw)
2925{
2926 struct ath5k_softc *sc = hw->priv;
2927
2928 return ath5k_hw_get_tsf64(sc->ah);
2929}
2930
2931static void
2932ath5k_reset_tsf(struct ieee80211_hw *hw)
2933{
2934 struct ath5k_softc *sc = hw->priv;
2935
9804b98d
BR		 2936 /*
2937 * in IBSS mode we need to update the beacon timers too.
2938 * this will also reset the TSF if we call it with 0
2939 */
2940 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2941 ath5k_beacon_update_timers(sc, 0);
2942 else
2943 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 2944}
2945
2946static int
2947ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2948 struct ieee80211_tx_control *ctl)
2949{
2950 struct ath5k_softc *sc = hw->priv;
2951 int ret;
2952
2953 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2954
2955 mutex_lock(&sc->lock);
2956
2957 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
2958 ret = -EIO;
2959 goto end;
2960 }
2961
2962 ath5k_txbuf_free(sc, sc->bbuf);
2963 sc->bbuf->skb = skb;
2964 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
2965 if (ret)
2966 sc->bbuf->skb = NULL;
2967 else
2968 ath5k_beacon_config(sc);
2969
2970end:
2971 mutex_unlock(&sc->lock);
2972 return ret;
2973}
2974
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