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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
2c91108c 82static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
2c91108c 106static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
2c91108c 145static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
209d889b 217static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 242static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 243static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 244static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 245 struct sk_buff *skb);
02969b38
MX		 246static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
fa1c114f 250
2c91108c 251static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 353static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 354
355static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356{
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363}
364
365/* Interrupt handling */
bb2becac 366static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 367static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 368static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 369static irqreturn_t ath5k_intr(int irq, void *dev_id);
370static void ath5k_tasklet_reset(unsigned long data);
371
372static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 373
374/*
375 * Module init/exit functions
376 */
377static int __init
378init_ath5k_pci(void)
379{
380 int ret;
381
382 ath5k_debug_init();
383
04a9e451 384 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391}
392
393static void __exit
394exit_ath5k_pci(void)
395{
04a9e451 396 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 397
398 ath5k_debug_finish();
399}
400
401module_init(init_ath5k_pci);
402module_exit(exit_ath5k_pci);
403
404
405/********************\
406* PCI Initialization *
407\********************/
408
409static const char *
410ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411{
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
75d0edb8
NK		 418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429}
430
431static int __devinit
432ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434{
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
284901a9 448 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 517
518 hw->wiphy->interface_modes =
519 BIT(NL80211_IFTYPE_STATION) |
520 BIT(NL80211_IFTYPE_ADHOC) |
521 BIT(NL80211_IFTYPE_MESH_POINT);
522
fa1c114f
JS		 523 hw->extra_tx_headroom = 2;
524 hw->channel_change_time = 5000;
fa1c114f
JS		 525 sc = hw->priv;
526 sc->hw = hw;
527 sc->pdev = pdev;
528
529 ath5k_debug_init_device(sc);
530
531 /*
532 * Mark the device as detached to avoid processing
533 * interrupts until setup is complete.
534 */
535 __set_bit(ATH_STAT_INVALID, sc->status);
536
537 sc->iobase = mem; /* So we can unmap it on detach */
538 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 539 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 540 mutex_init(&sc->lock);
541 spin_lock_init(&sc->rxbuflock);
542 spin_lock_init(&sc->txbuflock);
00482973 543 spin_lock_init(&sc->block);
fa1c114f
JS		 544
545 /* Set private data */
546 pci_set_drvdata(pdev, hw);
547
fa1c114f
JS		 548 /* Setup interrupt handler */
549 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
550 if (ret) {
551 ATH5K_ERR(sc, "request_irq failed\n");
552 goto err_free;
553 }
554
555 /* Initialize device */
556 sc->ah = ath5k_hw_attach(sc, id->driver_data);
557 if (IS_ERR(sc->ah)) {
558 ret = PTR_ERR(sc->ah);
559 goto err_irq;
560 }
561
2f7fe870
FF		 562 /* set up multi-rate retry capabilities */
563 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 564 hw->max_rates = 4;
565 hw->max_rate_tries = 11;
2f7fe870
FF		 566 }
567
fa1c114f
JS		 568 /* Finish private driver data initialization */
569 ret = ath5k_attach(pdev, hw);
570 if (ret)
571 goto err_ah;
572
573 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 574 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 575 sc->ah->ah_mac_srev,
576 sc->ah->ah_phy_revision);
577
400ec45a 578 if (!sc->ah->ah_single_chip) {
fa1c114f 579 /* Single chip radio (!RF5111) */
400ec45a
LR		 580 if (sc->ah->ah_radio_5ghz_revision &&
581 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 582 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 583 if (!test_bit(AR5K_MODE_11A,
584 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_5ghz_revision),
588 sc->ah->ah_radio_5ghz_revision);
589 /* No 2GHz support (5110 and some
590 * 5Ghz only cards) -> report 5Ghz radio */
591 } else if (!test_bit(AR5K_MODE_11B,
592 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 593 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 594 ath5k_chip_name(AR5K_VERSION_RAD,
595 sc->ah->ah_radio_5ghz_revision),
596 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 597 /* Multiband radio */
598 } else {
599 ATH5K_INFO(sc, "RF%s multiband radio found"
600 " (0x%x)\n",
400ec45a
LR		 601 ath5k_chip_name(AR5K_VERSION_RAD,
602 sc->ah->ah_radio_5ghz_revision),
603 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 604 }
605 }
400ec45a
LR		 606 /* Multi chip radio (RF5111 - RF2111) ->
607 * report both 2GHz/5GHz radios */
608 else if (sc->ah->ah_radio_5ghz_revision &&
609 sc->ah->ah_radio_2ghz_revision){
fa1c114f 610 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
fa1c114f 614 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_2ghz_revision),
617 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 618 }
619 }
620
621
622 /* ready to process interrupts */
623 __clear_bit(ATH_STAT_INVALID, sc->status);
624
625 return 0;
626err_ah:
627 ath5k_hw_detach(sc->ah);
628err_irq:
629 free_irq(pdev->irq, sc);
630err_free:
fa1c114f
JS		 631 ieee80211_free_hw(hw);
632err_map:
633 pci_iounmap(pdev, mem);
634err_reg:
635 pci_release_region(pdev, 0);
636err_dis:
637 pci_disable_device(pdev);
638err:
639 return ret;
640}
641
642static void __devexit
643ath5k_pci_remove(struct pci_dev *pdev)
644{
645 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
646 struct ath5k_softc *sc = hw->priv;
647
648 ath5k_debug_finish_device(sc);
649 ath5k_detach(pdev, hw);
650 ath5k_hw_detach(sc->ah);
651 free_irq(pdev->irq, sc);
fa1c114f
JS		 652 pci_iounmap(pdev, sc->iobase);
653 pci_release_region(pdev, 0);
654 pci_disable_device(pdev);
655 ieee80211_free_hw(hw);
656}
657
658#ifdef CONFIG_PM
659static int
660ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
661{
662 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
663 struct ath5k_softc *sc = hw->priv;
664
3a078876 665 ath5k_led_off(sc);
fa1c114f 666
3e4242b9 667 free_irq(pdev->irq, sc);
fa1c114f
JS		 668 pci_save_state(pdev);
669 pci_disable_device(pdev);
670 pci_set_power_state(pdev, PCI_D3hot);
671
672 return 0;
673}
674
675static int
676ath5k_pci_resume(struct pci_dev *pdev)
677{
678 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
679 struct ath5k_softc *sc = hw->priv;
bc1b32d6 680 int err;
fa1c114f 681
3e4242b9 682 pci_restore_state(pdev);
fa1c114f
JS		 683
684 err = pci_enable_device(pdev);
685 if (err)
686 return err;
687
3e4242b9
JS		 688 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
689 if (err) {
690 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 691 goto err_no_irq;
3e4242b9
JS		 692 }
693
3a078876 694 ath5k_led_enable(sc);
fa1c114f 695 return 0;
bb2becac 696
37465c8a 697err_no_irq:
3e4242b9
JS		 698 pci_disable_device(pdev);
699 return err;
fa1c114f
JS		 700}
701#endif /* CONFIG_PM */
702
703
fa1c114f
JS		 704/***********************\
705* Driver Initialization *
706\***********************/
707
708static int
709ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
710{
711 struct ath5k_softc *sc = hw->priv;
712 struct ath5k_hw *ah = sc->ah;
0e149cf5 713 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 714 int ret;
715
716 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
717
718 /*
719 * Check if the MAC has multi-rate retry support.
720 * We do this by trying to setup a fake extended
721 * descriptor. MAC's that don't have support will
722 * return false w/o doing anything. MAC's that do
723 * support it will return true w/o doing anything.
724 */
c6e387a2 725 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 726 if (ret < 0)
727 goto err;
728 if (ret > 0)
fa1c114f
JS		 729 __set_bit(ATH_STAT_MRRETRY, sc->status);
730
fa1c114f
JS		 731 /*
732 * Collect the channel list. The 802.11 layer
733 * is resposible for filtering this list based
734 * on settings like the phy mode and regulatory
735 * domain restrictions.
736 */
63266a65 737 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 738 if (ret) {
739 ATH5K_ERR(sc, "can't get channels\n");
740 goto err;
741 }
742
743 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 744 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
745 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 746 else
d8ee398d 747 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 748
749 /*
750 * Allocate tx+rx descriptors and populate the lists.
751 */
752 ret = ath5k_desc_alloc(sc, pdev);
753 if (ret) {
754 ATH5K_ERR(sc, "can't allocate descriptors\n");
755 goto err;
756 }
757
758 /*
759 * Allocate hardware transmit queues: one queue for
760 * beacon frames and one data queue for each QoS
761 * priority. Note that hw functions handle reseting
762 * these queues at the needed time.
763 */
764 ret = ath5k_beaconq_setup(ah);
765 if (ret < 0) {
766 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
767 goto err_desc;
768 }
769 sc->bhalq = ret;
770
771 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
772 if (IS_ERR(sc->txq)) {
773 ATH5K_ERR(sc, "can't setup xmit queue\n");
774 ret = PTR_ERR(sc->txq);
775 goto err_bhal;
776 }
777
778 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
779 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
780 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 781 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 782 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 783
0e149cf5
BC		 784 ret = ath5k_eeprom_read_mac(ah, mac);
785 if (ret) {
786 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
787 sc->pdev->device);
788 goto err_queues;
789 }
790
fa1c114f
JS		 791 SET_IEEE80211_PERM_ADDR(hw, mac);
792 /* All MAC address bits matter for ACKs */
793 memset(sc->bssidmask, 0xff, ETH_ALEN);
794 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
795
796 ret = ieee80211_register_hw(hw);
797 if (ret) {
798 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
799 goto err_queues;
800 }
801
3a078876
BC		 802 ath5k_init_leds(sc);
803
fa1c114f
JS		 804 return 0;
805err_queues:
806 ath5k_txq_release(sc);
807err_bhal:
808 ath5k_hw_release_tx_queue(ah, sc->bhalq);
809err_desc:
810 ath5k_desc_free(sc, pdev);
811err:
812 return ret;
813}
814
815static void
816ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
817{
818 struct ath5k_softc *sc = hw->priv;
819
820 /*
821 * NB: the order of these is important:
822 * o call the 802.11 layer before detaching ath5k_hw to
823 * insure callbacks into the driver to delete global
824 * key cache entries can be handled
825 * o reclaim the tx queue data structures after calling
826 * the 802.11 layer as we'll get called back to reclaim
827 * node state and potentially want to use them
828 * o to cleanup the tx queues the hal is called, so detach
829 * it last
830 * XXX: ??? detach ath5k_hw ???
831 * Other than that, it's straightforward...
832 */
833 ieee80211_unregister_hw(hw);
834 ath5k_desc_free(sc, pdev);
835 ath5k_txq_release(sc);
836 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 837 ath5k_unregister_leds(sc);
fa1c114f
JS		 838
839 /*
840 * NB: can't reclaim these until after ieee80211_ifdetach
841 * returns because we'll get called back to reclaim node
842 * state and potentially want to use them.
843 */
844}
845
846
847
848
849/********************\
850* Channel/mode setup *
851\********************/
852
853/*
854 * Convert IEEE channel number to MHz frequency.
855 */
856static inline short
857ath5k_ieee2mhz(short chan)
858{
859 if (chan <= 14 || chan >= 27)
860 return ieee80211chan2mhz(chan);
861 else
862 return 2212 + chan * 20;
863}
864
fa1c114f
JS		 865static unsigned int
866ath5k_copy_channels(struct ath5k_hw *ah,
867 struct ieee80211_channel *channels,
868 unsigned int mode,
869 unsigned int max)
870{
d8ee398d 871 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 872
873 if (!test_bit(mode, ah->ah_modes))
874 return 0;
875
fa1c114f 876 switch (mode) {
d8ee398d
LR		 877 case AR5K_MODE_11A:
878 case AR5K_MODE_11A_TURBO:
fa1c114f 879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 880 size = 220 ;
fa1c114f
JS		 881 chfreq = CHANNEL_5GHZ;
882 break;
d8ee398d
LR		 883 case AR5K_MODE_11B:
884 case AR5K_MODE_11G:
885 case AR5K_MODE_11G_TURBO:
886 size = 26;
fa1c114f
JS		 887 chfreq = CHANNEL_2GHZ;
888 break;
889 default:
890 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 return 0;
892 }
893
894 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 895 ch = i + 1 ;
896 freq = ath5k_ieee2mhz(ch);
fa1c114f 897
d8ee398d
LR		 898 /* Check if channel is supported by the chipset */
899 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 900 continue;
901
d8ee398d
LR		 902 /* Write channel info and increment counter */
903 channels[count].center_freq = freq;
a3f4b914
LR		 904 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
905 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 906 switch (mode) {
907 case AR5K_MODE_11A:
908 case AR5K_MODE_11G:
909 channels[count].hw_value = chfreq | CHANNEL_OFDM;
910 break;
911 case AR5K_MODE_11A_TURBO:
912 case AR5K_MODE_11G_TURBO:
913 channels[count].hw_value = chfreq |
914 CHANNEL_OFDM | CHANNEL_TURBO;
915 break;
916 case AR5K_MODE_11B:
d8ee398d
LR		 917 channels[count].hw_value = CHANNEL_B;
918 }
fa1c114f 919
fa1c114f
JS		 920 count++;
921 max--;
922 }
923
924 return count;
925}
926
63266a65
BR		 927static void
928ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
929{
930 u8 i;
931
932 for (i = 0; i < AR5K_MAX_RATES; i++)
933 sc->rate_idx[b->band][i] = -1;
934
935 for (i = 0; i < b->n_bitrates; i++) {
936 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
937 if (b->bitrates[i].hw_value_short)
938 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
939 }
940}
941
d8ee398d 942static int
63266a65 943ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 944{
945 struct ath5k_softc *sc = hw->priv;
d8ee398d 946 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 947 struct ieee80211_supported_band *sband;
948 int max_c, count_c = 0;
949 int i;
fa1c114f 950
d8ee398d 951 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 952 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 953
954 /* 2GHz band */
63266a65
BR		 955 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
956 sband->band = IEEE80211_BAND_2GHZ;
957 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 958
63266a65
BR		 959 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
960 /* G mode */
961 memcpy(sband->bitrates, &ath5k_rates[0],
962 sizeof(struct ieee80211_rate) * 12);
963 sband->n_bitrates = 12;
fa1c114f 964
d8ee398d 965 sband->channels = sc->channels;
d8ee398d 966 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 967 AR5K_MODE_11G, max_c);
fa1c114f 968
63266a65 969 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 970 count_c = sband->n_channels;
63266a65
BR		 971 max_c -= count_c;
972 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
973 /* B mode */
974 memcpy(sband->bitrates, &ath5k_rates[0],
975 sizeof(struct ieee80211_rate) * 4);
976 sband->n_bitrates = 4;
977
978 /* 5211 only supports B rates and uses 4bit rate codes
979 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
980 * fix them up here:
981 */
982 if (ah->ah_version == AR5K_AR5211) {
983 for (i = 0; i < 4; i++) {
984 sband->bitrates[i].hw_value =
985 sband->bitrates[i].hw_value & 0xF;
986 sband->bitrates[i].hw_value_short =
987 sband->bitrates[i].hw_value_short & 0xF;
988 }
989 }
fa1c114f 990
63266a65
BR		 991 sband->channels = sc->channels;
992 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
993 AR5K_MODE_11B, max_c);
d8ee398d 994
63266a65
BR		 995 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
996 count_c = sband->n_channels;
d8ee398d 997 max_c -= count_c;
fa1c114f 998 }
63266a65 999 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1000
63266a65 1001 /* 5GHz band, A mode */
400ec45a 1002 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1003 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1004 sband->band = IEEE80211_BAND_5GHZ;
1005 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1006
63266a65
BR		 1007 memcpy(sband->bitrates, &ath5k_rates[4],
1008 sizeof(struct ieee80211_rate) * 8);
1009 sband->n_bitrates = 8;
fa1c114f 1010
63266a65 1011 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1012 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1013 AR5K_MODE_11A, max_c);
1014
d8ee398d
LR		 1015 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1016 }
63266a65 1017 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1018
b446197c 1019 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1020
1021 return 0;
fa1c114f
JS		 1022}
1023
1024/*
1025 * Set/change channels. If the channel is really being changed,
1026 * it's done by reseting the chip. To accomplish this we must
1027 * first cleanup any pending DMA, then restart stuff after a la
1028 * ath5k_init.
be009370
BC		 1029 *
1030 * Called with sc->lock.
fa1c114f
JS		 1031 */
1032static int
1033ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034{
d8ee398d
LR		 1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1037
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1040
fa1c114f
JS		 1041 /*
1042 * To switch channels clear any pending DMA operations;
1043 * wait long enough for the RX fifo to drain, reset the
1044 * hardware at the new frequency, and then re-enable
1045 * the relevant bits of the h/w.
1046 */
209d889b 1047 return ath5k_reset(sc, chan);
fa1c114f
JS		 1048 }
1049
1050 return 0;
1051}
1052
1053static void
1054ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1055{
fa1c114f 1056 sc->curmode = mode;
d8ee398d 1057
400ec45a 1058 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1059 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1060 } else {
1061 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1062 }
fa1c114f
JS		 1063}
1064
1065static void
1066ath5k_mode_setup(struct ath5k_softc *sc)
1067{
1068 struct ath5k_hw *ah = sc->ah;
1069 u32 rfilt;
1070
1071 /* configure rx filter */
1072 rfilt = sc->filter_flags;
1073 ath5k_hw_set_rx_filter(ah, rfilt);
1074
1075 if (ath5k_hw_hasbssidmask(ah))
1076 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1077
1078 /* configure operational mode */
1079 ath5k_hw_set_opmode(ah);
1080
1081 ath5k_hw_set_mcast_filter(ah, 0, 0);
1082 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1083}
1084
d8ee398d 1085static inline int
63266a65
BR		 1086ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1087{
b7266047
BC		 1088 int rix;
1089
1090 /* return base rate on errors */
1091 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1092 "hw_rix out of bounds: %x\n", hw_rix))
1093 return 0;
1094
1095 rix = sc->rate_idx[sc->curband->band][hw_rix];
1096 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1097 rix = 0;
1098
1099 return rix;
d8ee398d
LR		 1100}
1101
fa1c114f
JS		 1102/***************\
1103* Buffers setup *
1104\***************/
1105
b6ea0356
BC		 1106static
1107struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1108{
1109 struct sk_buff *skb;
1110 unsigned int off;
1111
1112 /*
1113 * Allocate buffer with headroom_needed space for the
1114 * fake physical layer header at the start.
1115 */
1116 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1117
1118 if (!skb) {
1119 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1120 sc->rxbufsize + sc->cachelsz - 1);
1121 return NULL;
1122 }
1123 /*
1124 * Cache-line-align. This is important (for the
1125 * 5210 at least) as not doing so causes bogus data
1126 * in rx'd frames.
1127 */
1128 off = ((unsigned long)skb->data) % sc->cachelsz;
1129 if (off != 0)
1130 skb_reserve(skb, sc->cachelsz - off);
1131
1132 *skb_addr = pci_map_single(sc->pdev,
1133 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1134 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1135 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1136 dev_kfree_skb(skb);
1137 return NULL;
1138 }
1139 return skb;
1140}
1141
fa1c114f
JS		 1142static int
1143ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1144{
1145 struct ath5k_hw *ah = sc->ah;
1146 struct sk_buff *skb = bf->skb;
1147 struct ath5k_desc *ds;
1148
b6ea0356
BC		 1149 if (!skb) {
1150 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1151 if (!skb)
fa1c114f 1152 return -ENOMEM;
fa1c114f 1153 bf->skb = skb;
fa1c114f
JS		 1154 }
1155
1156 /*
1157 * Setup descriptors. For receive we always terminate
1158 * the descriptor list with a self-linked entry so we'll
1159 * not get overrun under high load (as can happen with a
1160 * 5212 when ANI processing enables PHY error frames).
1161 *
1162 * To insure the last descriptor is self-linked we create
1163 * each descriptor as self-linked and add it to the end. As
1164 * each additional descriptor is added the previous self-linked
1165 * entry is ``fixed'' naturally. This should be safe even
1166 * if DMA is happening. When processing RX interrupts we
1167 * never remove/process the last, self-linked, entry on the
1168 * descriptor list. This insures the hardware always has
1169 * someplace to write a new frame.
1170 */
1171 ds = bf->desc;
1172 ds->ds_link = bf->daddr; /* link to self */
1173 ds->ds_data = bf->skbaddr;
c6e387a2 1174 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1175 skb_tailroom(skb), /* buffer size */
1176 0);
1177
1178 if (sc->rxlink != NULL)
1179 *sc->rxlink = bf->daddr;
1180 sc->rxlink = &ds->ds_link;
1181 return 0;
1182}
1183
1184static int
e039fa4a 1185ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1186{
1187 struct ath5k_hw *ah = sc->ah;
1188 struct ath5k_txq *txq = sc->txq;
1189 struct ath5k_desc *ds = bf->desc;
1190 struct sk_buff *skb = bf->skb;
a888d52d 1191 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1192 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1193 struct ieee80211_rate *rate;
1194 unsigned int mrr_rate[3], mrr_tries[3];
1195 int i, ret;
8902ff4e 1196 u16 hw_rate;
07c1e852
BC		 1197 u16 cts_rate = 0;
1198 u16 duration = 0;
8902ff4e 1199 u8 rc_flags;
fa1c114f
JS		 1200
1201 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1202
fa1c114f
JS		 1203 /* XXX endianness */
1204 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1205 PCI_DMA_TODEVICE);
1206
8902ff4e
BC		 1207 rate = ieee80211_get_tx_rate(sc->hw, info);
1208
e039fa4a 1209 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1210 flags |= AR5K_TXDESC_NOACK;
1211
8902ff4e
BC		 1212 rc_flags = info->control.rates[0].flags;
1213 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1214 rate->hw_value_short : rate->hw_value;
1215
281c56dd 1216 pktlen = skb->len;
fa1c114f 1217
8f655dde
NK		 1218 /* FIXME: If we are in g mode and rate is a CCK rate
1219 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1220 * from tx power (value is in dB units already) */
362695e1
BC		 1221 if (info->control.hw_key) {
1222 keyidx = info->control.hw_key->hw_key_idx;
1223 pktlen += info->control.hw_key->icv_len;
1224 }
07c1e852
BC		 1225 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1226 flags |= AR5K_TXDESC_RTSENA;
1227 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1228 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1229 sc->vif, pktlen, info));
1230 }
1231 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1232 flags |= AR5K_TXDESC_CTSENA;
1233 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1234 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1235 sc->vif, pktlen, info));
1236 }
fa1c114f
JS		 1237 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1238 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1239 (sc->power_level * 2),
8902ff4e 1240 hw_rate,
07c1e852
BC		 1241 info->control.rates[0].count, keyidx, 0, flags,
1242 cts_rate, duration);
fa1c114f
JS		 1243 if (ret)
1244 goto err_unmap;
1245
2f7fe870
FF		 1246 memset(mrr_rate, 0, sizeof(mrr_rate));
1247 memset(mrr_tries, 0, sizeof(mrr_tries));
1248 for (i = 0; i < 3; i++) {
1249 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1250 if (!rate)
1251 break;
1252
1253 mrr_rate[i] = rate->hw_value;
e6a9854b 1254 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1255 }
1256
1257 ah->ah_setup_mrr_tx_desc(ah, ds,
1258 mrr_rate[0], mrr_tries[0],
1259 mrr_rate[1], mrr_tries[1],
1260 mrr_rate[2], mrr_tries[2]);
1261
fa1c114f
JS		 1262 ds->ds_link = 0;
1263 ds->ds_data = bf->skbaddr;
1264
1265 spin_lock_bh(&txq->lock);
1266 list_add_tail(&bf->list, &txq->q);
57ffc589 1267 sc->tx_stats[txq->qnum].len++;
fa1c114f 1268 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1269 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1270 else /* no, so only link it */
1271 *txq->link = bf->daddr;
1272
1273 txq->link = &ds->ds_link;
c6e387a2 1274 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1275 mmiowb();
fa1c114f
JS		 1276 spin_unlock_bh(&txq->lock);
1277
1278 return 0;
1279err_unmap:
1280 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1281 return ret;
1282}
1283
1284/*******************\
1285* Descriptors setup *
1286\*******************/
1287
1288static int
1289ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1290{
1291 struct ath5k_desc *ds;
1292 struct ath5k_buf *bf;
1293 dma_addr_t da;
1294 unsigned int i;
1295 int ret;
1296
1297 /* allocate descriptors */
1298 sc->desc_len = sizeof(struct ath5k_desc) *
1299 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1300 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1301 if (sc->desc == NULL) {
1302 ATH5K_ERR(sc, "can't allocate descriptors\n");
1303 ret = -ENOMEM;
1304 goto err;
1305 }
1306 ds = sc->desc;
1307 da = sc->desc_daddr;
1308 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1309 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1310
1311 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1312 sizeof(struct ath5k_buf), GFP_KERNEL);
1313 if (bf == NULL) {
1314 ATH5K_ERR(sc, "can't allocate bufptr\n");
1315 ret = -ENOMEM;
1316 goto err_free;
1317 }
1318 sc->bufptr = bf;
1319
1320 INIT_LIST_HEAD(&sc->rxbuf);
1321 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1322 bf->desc = ds;
1323 bf->daddr = da;
1324 list_add_tail(&bf->list, &sc->rxbuf);
1325 }
1326
1327 INIT_LIST_HEAD(&sc->txbuf);
1328 sc->txbuf_len = ATH_TXBUF;
1329 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1330 da += sizeof(*ds)) {
1331 bf->desc = ds;
1332 bf->daddr = da;
1333 list_add_tail(&bf->list, &sc->txbuf);
1334 }
1335
1336 /* beacon buffer */
1337 bf->desc = ds;
1338 bf->daddr = da;
1339 sc->bbuf = bf;
1340
1341 return 0;
1342err_free:
1343 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1344err:
1345 sc->desc = NULL;
1346 return ret;
1347}
1348
1349static void
1350ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1351{
1352 struct ath5k_buf *bf;
1353
1354 ath5k_txbuf_free(sc, sc->bbuf);
1355 list_for_each_entry(bf, &sc->txbuf, list)
1356 ath5k_txbuf_free(sc, bf);
1357 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1358 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1359
1360 /* Free memory associated with all descriptors */
1361 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1362
1363 kfree(sc->bufptr);
1364 sc->bufptr = NULL;
1365}
1366
1367
1368
1369
1370
1371/**************\
1372* Queues setup *
1373\**************/
1374
1375static struct ath5k_txq *
1376ath5k_txq_setup(struct ath5k_softc *sc,
1377 int qtype, int subtype)
1378{
1379 struct ath5k_hw *ah = sc->ah;
1380 struct ath5k_txq *txq;
1381 struct ath5k_txq_info qi = {
1382 .tqi_subtype = subtype,
1383 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1384 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1385 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1386 };
1387 int qnum;
1388
1389 /*
1390 * Enable interrupts only for EOL and DESC conditions.
1391 * We mark tx descriptors to receive a DESC interrupt
1392 * when a tx queue gets deep; otherwise waiting for the
1393 * EOL to reap descriptors. Note that this is done to
1394 * reduce interrupt load and this only defers reaping
1395 * descriptors, never transmitting frames. Aside from
1396 * reducing interrupts this also permits more concurrency.
1397 * The only potential downside is if the tx queue backs
1398 * up in which case the top half of the kernel may backup
1399 * due to a lack of tx descriptors.
1400 */
1401 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1402 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1403 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1404 if (qnum < 0) {
1405 /*
1406 * NB: don't print a message, this happens
1407 * normally on parts with too few tx queues
1408 */
1409 return ERR_PTR(qnum);
1410 }
1411 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1412 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1413 qnum, ARRAY_SIZE(sc->txqs));
1414 ath5k_hw_release_tx_queue(ah, qnum);
1415 return ERR_PTR(-EINVAL);
1416 }
1417 txq = &sc->txqs[qnum];
1418 if (!txq->setup) {
1419 txq->qnum = qnum;
1420 txq->link = NULL;
1421 INIT_LIST_HEAD(&txq->q);
1422 spin_lock_init(&txq->lock);
1423 txq->setup = true;
1424 }
1425 return &sc->txqs[qnum];
1426}
1427
1428static int
1429ath5k_beaconq_setup(struct ath5k_hw *ah)
1430{
1431 struct ath5k_txq_info qi = {
1432 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1433 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1435 /* NB: for dynamic turbo, don't enable any other interrupts */
1436 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1437 };
1438
1439 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1440}
1441
1442static int
1443ath5k_beaconq_config(struct ath5k_softc *sc)
1444{
1445 struct ath5k_hw *ah = sc->ah;
1446 struct ath5k_txq_info qi;
1447 int ret;
1448
1449 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1450 if (ret)
1451 return ret;
05c914fe
JB		 1452 if (sc->opmode == NL80211_IFTYPE_AP ||
1453 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1454 /*
1455 * Always burst out beacon and CAB traffic
1456 * (aifs = cwmin = cwmax = 0)
1457 */
1458 qi.tqi_aifs = 0;
1459 qi.tqi_cw_min = 0;
1460 qi.tqi_cw_max = 0;
05c914fe 1461 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1462 /*
1463 * Adhoc mode; backoff between 0 and (2 * cw_min).
1464 */
1465 qi.tqi_aifs = 0;
1466 qi.tqi_cw_min = 0;
1467 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1468 }
1469
6d91e1d8
BR		 1470 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1471 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1472 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1473
c6e387a2 1474 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1475 if (ret) {
1476 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1477 "hardware queue!\n", __func__);
1478 return ret;
1479 }
1480
1481 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1482}
1483
1484static void
1485ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1486{
1487 struct ath5k_buf *bf, *bf0;
1488
1489 /*
1490 * NB: this assumes output has been stopped and
1491 * we do not need to block ath5k_tx_tasklet
1492 */
1493 spin_lock_bh(&txq->lock);
1494 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1495 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1496
1497 ath5k_txbuf_free(sc, bf);
1498
1499 spin_lock_bh(&sc->txbuflock);
57ffc589 1500 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1501 list_move_tail(&bf->list, &sc->txbuf);
1502 sc->txbuf_len++;
1503 spin_unlock_bh(&sc->txbuflock);
1504 }
1505 txq->link = NULL;
1506 spin_unlock_bh(&txq->lock);
1507}
1508
1509/*
1510 * Drain the transmit queues and reclaim resources.
1511 */
1512static void
1513ath5k_txq_cleanup(struct ath5k_softc *sc)
1514{
1515 struct ath5k_hw *ah = sc->ah;
1516 unsigned int i;
1517
1518 /* XXX return value */
1519 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1520 /* don't touch the hardware if marked invalid */
1521 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1522 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1523 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1524 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1525 if (sc->txqs[i].setup) {
1526 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1527 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1528 "link %p\n",
1529 sc->txqs[i].qnum,
c6e387a2 1530 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1531 sc->txqs[i].qnum),
1532 sc->txqs[i].link);
1533 }
1534 }
36d6825b 1535 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1536
1537 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1538 if (sc->txqs[i].setup)
1539 ath5k_txq_drainq(sc, &sc->txqs[i]);
1540}
1541
1542static void
1543ath5k_txq_release(struct ath5k_softc *sc)
1544{
1545 struct ath5k_txq *txq = sc->txqs;
1546 unsigned int i;
1547
1548 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1549 if (txq->setup) {
1550 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1551 txq->setup = false;
1552 }
1553}
1554
1555
1556
1557
1558/*************\
1559* RX Handling *
1560\*************/
1561
1562/*
1563 * Enable the receive h/w following a reset.
1564 */
1565static int
1566ath5k_rx_start(struct ath5k_softc *sc)
1567{
1568 struct ath5k_hw *ah = sc->ah;
1569 struct ath5k_buf *bf;
1570 int ret;
1571
1572 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1573
1574 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1575 sc->cachelsz, sc->rxbufsize);
1576
1577 sc->rxlink = NULL;
1578
1579 spin_lock_bh(&sc->rxbuflock);
1580 list_for_each_entry(bf, &sc->rxbuf, list) {
1581 ret = ath5k_rxbuf_setup(sc, bf);
1582 if (ret != 0) {
1583 spin_unlock_bh(&sc->rxbuflock);
1584 goto err;
1585 }
1586 }
1587 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1588 spin_unlock_bh(&sc->rxbuflock);
1589
c6e387a2
NK		 1590 ath5k_hw_set_rxdp(ah, bf->daddr);
1591 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1592 ath5k_mode_setup(sc); /* set filters, etc. */
1593 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1594
1595 return 0;
1596err:
1597 return ret;
1598}
1599
1600/*
1601 * Disable the receive h/w in preparation for a reset.
1602 */
1603static void
1604ath5k_rx_stop(struct ath5k_softc *sc)
1605{
1606 struct ath5k_hw *ah = sc->ah;
1607
c6e387a2 1608 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1609 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1610 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1611
1612 ath5k_debug_printrxbuffs(sc, ah);
1613
1614 sc->rxlink = NULL; /* just in case */
1615}
1616
1617static unsigned int
1618ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1619 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1620{
1621 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1622 unsigned int keyix, hlen;
fa1c114f 1623
b47f407b
BR		 1624 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1625 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1626 return RX_FLAG_DECRYPTED;
1627
1628 /* Apparently when a default key is used to decrypt the packet
1629 the hw does not set the index used to decrypt. In such cases
1630 get the index from the packet. */
798ee985 1631 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1632 if (ieee80211_has_protected(hdr->frame_control) &&
1633 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1634 skb->len >= hlen + 4) {
fa1c114f
JS		 1635 keyix = skb->data[hlen + 3] >> 6;
1636
1637 if (test_bit(keyix, sc->keymap))
1638 return RX_FLAG_DECRYPTED;
1639 }
1640
1641 return 0;
1642}
1643
036cd1ec
BR		 1644
1645static void
6ba81c2c
BR		 1646ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1647 struct ieee80211_rx_status *rxs)
036cd1ec 1648{
6ba81c2c 1649 u64 tsf, bc_tstamp;
036cd1ec
BR		 1650 u32 hw_tu;
1651 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1652
24b56e70 1653 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1654 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1655 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1656 /*
6ba81c2c
BR		 1657 * Received an IBSS beacon with the same BSSID. Hardware *must*
1658 * have updated the local TSF. We have to work around various
1659 * hardware bugs, though...
036cd1ec 1660 */
6ba81c2c
BR		 1661 tsf = ath5k_hw_get_tsf64(sc->ah);
1662 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1663 hw_tu = TSF_TO_TU(tsf);
1664
1665 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1666 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1667 (unsigned long long)bc_tstamp,
1668 (unsigned long long)rxs->mactime,
1669 (unsigned long long)(rxs->mactime - bc_tstamp),
1670 (unsigned long long)tsf);
6ba81c2c
BR		 1671
1672 /*
1673 * Sometimes the HW will give us a wrong tstamp in the rx
1674 * status, causing the timestamp extension to go wrong.
1675 * (This seems to happen especially with beacon frames bigger
1676 * than 78 byte (incl. FCS))
1677 * But we know that the receive timestamp must be later than the
1678 * timestamp of the beacon since HW must have synced to that.
1679 *
1680 * NOTE: here we assume mactime to be after the frame was
1681 * received, not like mac80211 which defines it at the start.
1682 */
1683 if (bc_tstamp > rxs->mactime) {
036cd1ec 1684 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1685 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1686 (unsigned long long)rxs->mactime,
1687 (unsigned long long)tsf);
6ba81c2c 1688 rxs->mactime = tsf;
036cd1ec 1689 }
6ba81c2c
BR		 1690
1691 /*
1692 * Local TSF might have moved higher than our beacon timers,
1693 * in that case we have to update them to continue sending
1694 * beacons. This also takes care of synchronizing beacon sending
1695 * times with other stations.
1696 */
1697 if (hw_tu >= sc->nexttbtt)
1698 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1699 }
1700}
1701
acf3c1a5
BC		 1702static void ath5k_tasklet_beacon(unsigned long data)
1703{
1704 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1705
1706 /*
1707 * Software beacon alert--time to send a beacon.
1708 *
1709 * In IBSS mode we use this interrupt just to
1710 * keep track of the next TBTT (target beacon
1711 * transmission time) in order to detect wether
1712 * automatic TSF updates happened.
1713 */
1714 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1715 /* XXX: only if VEOL suppported */
1716 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1717 sc->nexttbtt += sc->bintval;
1718 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1719 "SWBA nexttbtt: %x hw_tu: %x "
1720 "TSF: %llx\n",
1721 sc->nexttbtt,
1722 TSF_TO_TU(tsf),
1723 (unsigned long long) tsf);
1724 } else {
1725 spin_lock(&sc->block);
1726 ath5k_beacon_send(sc);
1727 spin_unlock(&sc->block);
1728 }
1729}
1730
fa1c114f
JS		 1731static void
1732ath5k_tasklet_rx(unsigned long data)
1733{
1734 struct ieee80211_rx_status rxs = {};
b47f407b 1735 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1736 struct sk_buff *skb, *next_skb;
1737 dma_addr_t next_skb_addr;
fa1c114f 1738 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1739 struct ath5k_buf *bf, *bf_last;
fa1c114f 1740 struct ath5k_desc *ds;
fa1c114f
JS		 1741 int ret;
1742 int hdrlen;
0fe45b1d 1743 int padsize;
fa1c114f
JS		 1744
1745 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1746 if (list_empty(&sc->rxbuf)) {
1747 ATH5K_WARN(sc, "empty rx buf pool\n");
1748 goto unlock;
1749 }
1750 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1751 do {
d6894b5b
BC		 1752 rxs.flag = 0;
1753
fa1c114f
JS		 1754 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1755 BUG_ON(bf->skb == NULL);
1756 skb = bf->skb;
1757 ds = bf->desc;
1758
3a0f2c87
JS		 1759 /*
1760 * last buffer must not be freed to ensure proper hardware
1761 * function. When the hardware finishes also a packet next to
1762 * it, we are sure, it doesn't use it anymore and we can go on.
1763 */
1764 if (bf_last == bf)
1765 bf->flags |= 1;
1766 if (bf->flags) {
1767 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1768 struct ath5k_buf, list);
1769 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1770 &rs);
1771 if (ret)
1772 break;
1773 bf->flags &= ~1;
1774 /* skip the overwritten one (even status is martian) */
1775 goto next;
1776 }
fa1c114f 1777
b47f407b 1778 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1779 if (unlikely(ret == -EINPROGRESS))
1780 break;
1781 else if (unlikely(ret)) {
1782 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1783 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1784 return;
1785 }
1786
b47f407b 1787 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1788 ATH5K_WARN(sc, "unsupported jumbo\n");
1789 goto next;
1790 }
1791
b47f407b
BR		 1792 if (unlikely(rs.rs_status)) {
1793 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1794 goto next;
b47f407b 1795 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1796 /*
1797 * Decrypt error. If the error occurred
1798 * because there was no hardware key, then
1799 * let the frame through so the upper layers
1800 * can process it. This is necessary for 5210
1801 * parts which have no way to setup a ``clear''
1802 * key cache entry.
1803 *
1804 * XXX do key cache faulting
1805 */
b47f407b
BR		 1806 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1807 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1808 goto accept;
1809 }
b47f407b 1810 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1811 rxs.flag |= RX_FLAG_MMIC_ERROR;
1812 goto accept;
1813 }
1814
1815 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1816 if ((rs.rs_status &
1817 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1818 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1819 goto next;
1820 }
1821accept:
b6ea0356
BC		 1822 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1823
1824 /*
1825 * If we can't replace bf->skb with a new skb under memory
1826 * pressure, just skip this packet
1827 */
1828 if (!next_skb)
1829 goto next;
1830
fa1c114f
JS		 1831 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1832 PCI_DMA_FROMDEVICE);
b47f407b 1833 skb_put(skb, rs.rs_datalen);
fa1c114f 1834
0fe45b1d
BP		 1835 /* The MAC header is padded to have 32-bit boundary if the
1836 * packet payload is non-zero. The general calculation for
1837 * padsize would take into account odd header lengths:
1838 * padsize = (4 - hdrlen % 4) % 4; However, since only
1839 * even-length headers are used, padding can only be 0 or 2
1840 * bytes and we can optimize this a bit. In addition, we must
1841 * not try to remove padding from short control frames that do
1842 * not have payload. */
fa1c114f 1843 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1844 padsize = ath5k_pad_size(hdrlen);
1845 if (padsize) {
0fe45b1d
BP		 1846 memmove(skb->data + padsize, skb->data, hdrlen);
1847 skb_pull(skb, padsize);
fa1c114f
JS		 1848 }
1849
c0e1899b
BR		 1850 /*
1851 * always extend the mac timestamp, since this information is
1852 * also needed for proper IBSS merging.
1853 *
1854 * XXX: it might be too late to do it here, since rs_tstamp is
1855 * 15bit only. that means TSF extension has to be done within
1856 * 32768usec (about 32ms). it might be necessary to move this to
1857 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1858 *
1859 * Unfortunately we don't know when the hardware takes the rx
1860 * timestamp (beginning of phy frame, data frame, end of rx?).
1861 * The only thing we know is that it is hardware specific...
1862 * On AR5213 it seems the rx timestamp is at the end of the
1863 * frame, but i'm not sure.
1864 *
1865 * NOTE: mac80211 defines mactime at the beginning of the first
1866 * data symbol. Since we don't have any time references it's
1867 * impossible to comply to that. This affects IBSS merge only
1868 * right now, so it's not too bad...
c0e1899b 1869 */
b47f407b 1870 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1871 rxs.flag |= RX_FLAG_TSFT;
1872
d8ee398d
LR		 1873 rxs.freq = sc->curchan->center_freq;
1874 rxs.band = sc->curband->band;
fa1c114f 1875
fa1c114f 1876 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1877 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1878
1879 /* An rssi of 35 indicates you should be able use
1880 * 54 Mbps reliably. A more elaborate scheme can be used
1881 * here but it requires a map of SNR/throughput for each
1882 * possible mode used */
1883 rxs.qual = rs.rs_rssi * 100 / 35;
1884
1885 /* rssi can be more than 35 though, anything above that
1886 * should be considered at 100% */
1887 if (rxs.qual > 100)
1888 rxs.qual = 100;
fa1c114f 1889
b47f407b
BR		 1890 rxs.antenna = rs.rs_antenna;
1891 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1892 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1893
06303352
BR		 1894 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1895 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1896 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1897
fa1c114f
JS		 1898 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1899
036cd1ec 1900 /* check beacons in IBSS mode */
05c914fe 1901 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1902 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1903
fa1c114f 1904 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1905
1906 bf->skb = next_skb;
1907 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1908next:
1909 list_move_tail(&bf->list, &sc->rxbuf);
1910 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1911unlock:
fa1c114f
JS		 1912 spin_unlock(&sc->rxbuflock);
1913}
1914
1915
1916
1917
1918/*************\
1919* TX Handling *
1920\*************/
1921
1922static void
1923ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1924{
b47f407b 1925 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1926 struct ath5k_buf *bf, *bf0;
1927 struct ath5k_desc *ds;
1928 struct sk_buff *skb;
e039fa4a 1929 struct ieee80211_tx_info *info;
2f7fe870 1930 int i, ret;
fa1c114f
JS		 1931
1932 spin_lock(&txq->lock);
1933 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1934 ds = bf->desc;
1935
b47f407b 1936 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1937 if (unlikely(ret == -EINPROGRESS))
1938 break;
1939 else if (unlikely(ret)) {
1940 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1941 ret, txq->qnum);
1942 break;
1943 }
1944
1945 skb = bf->skb;
a888d52d 1946 info = IEEE80211_SKB_CB(skb);
fa1c114f 1947 bf->skb = NULL;
e039fa4a 1948
fa1c114f
JS		 1949 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1950 PCI_DMA_TODEVICE);
1951
e6a9854b 1952 ieee80211_tx_info_clear_status(info);
2f7fe870 1953 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1954 struct ieee80211_tx_rate *r =
1955 &info->status.rates[i];
2f7fe870
FF		 1956
1957 if (ts.ts_rate[i]) {
e6a9854b
JB		 1958 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1959 r->count = ts.ts_retry[i];
2f7fe870 1960 } else {
e6a9854b
JB		 1961 r->idx = -1;
1962 r->count = 0;
2f7fe870
FF		 1963 }
1964 }
1965
e6a9854b
JB		 1966 /* count the successful attempt as well */
1967 info->status.rates[ts.ts_final_idx].count++;
1968
b47f407b 1969 if (unlikely(ts.ts_status)) {
fa1c114f 1970 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1971 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1972 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1973 } else {
e039fa4a
JB		 1974 info->flags |= IEEE80211_TX_STAT_ACK;
1975 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1976 }
1977
e039fa4a 1978 ieee80211_tx_status(sc->hw, skb);
57ffc589 1979 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1980
1981 spin_lock(&sc->txbuflock);
57ffc589 1982 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1983 list_move_tail(&bf->list, &sc->txbuf);
1984 sc->txbuf_len++;
1985 spin_unlock(&sc->txbuflock);
1986 }
1987 if (likely(list_empty(&txq->q)))
1988 txq->link = NULL;
1989 spin_unlock(&txq->lock);
1990 if (sc->txbuf_len > ATH_TXBUF / 5)
1991 ieee80211_wake_queues(sc->hw);
1992}
1993
1994static void
1995ath5k_tasklet_tx(unsigned long data)
1996{
1997 struct ath5k_softc *sc = (void *)data;
1998
1999 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 2000}
2001
2002
fa1c114f
JS		 2003/*****************\
2004* Beacon handling *
2005\*****************/
2006
2007/*
2008 * Setup the beacon frame for transmit.
2009 */
2010static int
e039fa4a 2011ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2012{
2013 struct sk_buff *skb = bf->skb;
a888d52d 2014 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2015 struct ath5k_hw *ah = sc->ah;
2016 struct ath5k_desc *ds;
2017 int ret, antenna = 0;
2018 u32 flags;
2019
2020 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2021 PCI_DMA_TODEVICE);
2022 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2023 "skbaddr %llx\n", skb, skb->data, skb->len,
2024 (unsigned long long)bf->skbaddr);
8d8bb39b 2025 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2026 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2027 return -EIO;
2028 }
2029
2030 ds = bf->desc;
2031
2032 flags = AR5K_TXDESC_NOACK;
05c914fe 2033 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2034 ds->ds_link = bf->daddr; /* self-linked */
2035 flags |= AR5K_TXDESC_VEOL;
2036 /*
2037 * Let hardware handle antenna switching if txantenna is not set
2038 */
2039 } else {
2040 ds->ds_link = 0;
2041 /*
2042 * Switch antenna every 4 beacons if txantenna is not set
2043 * XXX assumes two antennas
2044 */
2045 if (antenna == 0)
2046 antenna = sc->bsent & 4 ? 2 : 1;
2047 }
2048
8f655dde
NK		 2049 /* FIXME: If we are in g mode and rate is a CCK rate
2050 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2051 * from tx power (value is in dB units already) */
fa1c114f 2052 ds->ds_data = bf->skbaddr;
281c56dd 2053 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2054 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2055 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2056 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2057 1, AR5K_TXKEYIX_INVALID,
400ec45a 2058 antenna, flags, 0, 0);
fa1c114f
JS		 2059 if (ret)
2060 goto err_unmap;
2061
2062 return 0;
2063err_unmap:
2064 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2065 return ret;
2066}
2067
2068/*
2069 * Transmit a beacon frame at SWBA. Dynamic updates to the
2070 * frame contents are done as needed and the slot time is
2071 * also adjusted based on current state.
2072 *
acf3c1a5
BC		 2073 * This is called from software irq context (beacontq or restq
2074 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2075 */
2076static void
2077ath5k_beacon_send(struct ath5k_softc *sc)
2078{
2079 struct ath5k_buf *bf = sc->bbuf;
2080 struct ath5k_hw *ah = sc->ah;
2081
be9b7259 2082 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2083
05c914fe
JB		 2084 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2085 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2086 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2087 return;
2088 }
2089 /*
2090 * Check if the previous beacon has gone out. If
2091 * not don't don't try to post another, skip this
2092 * period and wait for the next. Missed beacons
2093 * indicate a problem and should not occur. If we
2094 * miss too many consecutive beacons reset the device.
2095 */
2096 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2097 sc->bmisscount++;
be9b7259 2098 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2099 "missed %u consecutive beacons\n", sc->bmisscount);
2100 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2101 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2102 "stuck beacon time (%u missed)\n",
2103 sc->bmisscount);
2104 tasklet_schedule(&sc->restq);
2105 }
2106 return;
2107 }
2108 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2109 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2110 "resume beacon xmit after %u misses\n",
2111 sc->bmisscount);
2112 sc->bmisscount = 0;
2113 }
2114
2115 /*
2116 * Stop any current dma and put the new frame on the queue.
2117 * This should never fail since we check above that no frames
2118 * are still pending on the queue.
2119 */
2120 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2121 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2122 /* NB: hw still stops DMA, so proceed */
2123 }
fa1c114f 2124
c6e387a2
NK		 2125 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2126 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2127 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2128 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2129
2130 sc->bsent++;
2131}
2132
2133
9804b98d
BR		 2134/**
2135 * ath5k_beacon_update_timers - update beacon timers
2136 *
2137 * @sc: struct ath5k_softc pointer we are operating on
2138 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2139 * beacon timer update based on the current HW TSF.
2140 *
2141 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2142 * of a received beacon or the current local hardware TSF and write it to the
2143 * beacon timer registers.
2144 *
2145 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2146 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2147 * when we otherwise know we have to update the timers, but we keep it in this
2148 * function to have it all together in one place.
2149 */
fa1c114f 2150static void
9804b98d 2151ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2152{
2153 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2154 u32 nexttbtt, intval, hw_tu, bc_tu;
2155 u64 hw_tsf;
fa1c114f
JS		 2156
2157 intval = sc->bintval & AR5K_BEACON_PERIOD;
2158 if (WARN_ON(!intval))
2159 return;
2160
9804b98d
BR		 2161 /* beacon TSF converted to TU */
2162 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2163
9804b98d
BR		 2164 /* current TSF converted to TU */
2165 hw_tsf = ath5k_hw_get_tsf64(ah);
2166 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2167
9804b98d
BR		 2168#define FUDGE 3
2169 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2170 if (bc_tsf == -1) {
2171 /*
2172 * no beacons received, called internally.
2173 * just need to refresh timers based on HW TSF.
2174 */
2175 nexttbtt = roundup(hw_tu + FUDGE, intval);
2176 } else if (bc_tsf == 0) {
2177 /*
2178 * no beacon received, probably called by ath5k_reset_tsf().
2179 * reset TSF to start with 0.
2180 */
2181 nexttbtt = intval;
2182 intval |= AR5K_BEACON_RESET_TSF;
2183 } else if (bc_tsf > hw_tsf) {
2184 /*
2185 * beacon received, SW merge happend but HW TSF not yet updated.
2186 * not possible to reconfigure timers yet, but next time we
2187 * receive a beacon with the same BSSID, the hardware will
2188 * automatically update the TSF and then we need to reconfigure
2189 * the timers.
2190 */
2191 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2192 "need to wait for HW TSF sync\n");
2193 return;
2194 } else {
2195 /*
2196 * most important case for beacon synchronization between STA.
2197 *
2198 * beacon received and HW TSF has been already updated by HW.
2199 * update next TBTT based on the TSF of the beacon, but make
2200 * sure it is ahead of our local TSF timer.
2201 */
2202 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2203 }
2204#undef FUDGE
fa1c114f 2205
036cd1ec
BR		 2206 sc->nexttbtt = nexttbtt;
2207
fa1c114f 2208 intval |= AR5K_BEACON_ENA;
fa1c114f 2209 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2210
2211 /*
2212 * debugging output last in order to preserve the time critical aspect
2213 * of this function
2214 */
2215 if (bc_tsf == -1)
2216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2217 "reconfigured timers based on HW TSF\n");
2218 else if (bc_tsf == 0)
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "reset HW TSF and timers\n");
2221 else
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2223 "updated timers based on beacon TSF\n");
2224
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2226 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2227 (unsigned long long) bc_tsf,
2228 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2229 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2230 intval & AR5K_BEACON_PERIOD,
2231 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2232 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2233}
2234
2235
036cd1ec
BR		 2236/**
2237 * ath5k_beacon_config - Configure the beacon queues and interrupts
2238 *
2239 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2240 *
036cd1ec 2241 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2242 * interrupts to detect TSF updates only.
fa1c114f
JS		 2243 */
2244static void
2245ath5k_beacon_config(struct ath5k_softc *sc)
2246{
2247 struct ath5k_hw *ah = sc->ah;
b5f03956 2248 unsigned long flags;
fa1c114f 2249
c6e387a2 2250 ath5k_hw_set_imr(ah, 0);
fa1c114f 2251 sc->bmisscount = 0;
dc1968e7 2252 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2253
1e3e6e8f 2254 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2255 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2256 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2257 /*
036cd1ec
BR		 2258 * In IBSS mode we use a self-linked tx descriptor and let the
2259 * hardware send the beacons automatically. We have to load it
fa1c114f 2260 * only once here.
036cd1ec 2261 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2262 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2263 */
2264 ath5k_beaconq_config(sc);
fa1c114f 2265
036cd1ec
BR		 2266 sc->imask |= AR5K_INT_SWBA;
2267
da966bca
JS		 2268 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2269 if (ath5k_hw_hasveol(ah)) {
b5f03956 2270 spin_lock_irqsave(&sc->block, flags);
da966bca 2271 ath5k_beacon_send(sc);
b5f03956 2272 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2273 }
2274 } else
2275 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2276 }
fa1c114f 2277
c6e387a2 2278 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2279}
2280
2281
2282/********************\
2283* Interrupt handling *
2284\********************/
2285
2286static int
bb2becac 2287ath5k_init(struct ath5k_softc *sc)
fa1c114f 2288{
bc1b32d6
EO		 2289 struct ath5k_hw *ah = sc->ah;
2290 int ret, i;
fa1c114f
JS		 2291
2292 mutex_lock(&sc->lock);
2293
2294 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2295
2296 /*
2297 * Stop anything previously setup. This is safe
2298 * no matter this is the first time through or not.
2299 */
2300 ath5k_stop_locked(sc);
2301
2302 /*
2303 * The basic interface to setting the hardware in a good
2304 * state is ``reset''. On return the hardware is known to
2305 * be powered up and with interrupts disabled. This must
2306 * be followed by initialization of the appropriate bits
2307 * and then setup of the interrupt mask.
2308 */
d8ee398d
LR		 2309 sc->curchan = sc->hw->conf.channel;
2310 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2311 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2312 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2313 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
209d889b 2314 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2315 if (ret)
2316 goto done;
fa1c114f 2317
bc1b32d6
EO		 2318 /*
2319 * Reset the key cache since some parts do not reset the
2320 * contents on initial power up or resume from suspend.
2321 */
2322 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2323 ath5k_hw_reset_key(ah, i);
2324
fa1c114f 2325 /* Set ack to be sent at low bit-rates */
bc1b32d6 2326 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2327
2328 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2329 msecs_to_jiffies(ath5k_calinterval * 1000)));
2330
2331 ret = 0;
2332done:
274c7c36 2333 mmiowb();
fa1c114f
JS		 2334 mutex_unlock(&sc->lock);
2335 return ret;
2336}
2337
2338static int
2339ath5k_stop_locked(struct ath5k_softc *sc)
2340{
2341 struct ath5k_hw *ah = sc->ah;
2342
2343 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2344 test_bit(ATH_STAT_INVALID, sc->status));
2345
2346 /*
2347 * Shutdown the hardware and driver:
2348 * stop output from above
2349 * disable interrupts
2350 * turn off timers
2351 * turn off the radio
2352 * clear transmit machinery
2353 * clear receive machinery
2354 * drain and release tx queues
2355 * reclaim beacon resources
2356 * power down hardware
2357 *
2358 * Note that some of this work is not possible if the
2359 * hardware is gone (invalid).
2360 */
2361 ieee80211_stop_queues(sc->hw);
2362
2363 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2364 ath5k_led_off(sc);
c6e387a2 2365 ath5k_hw_set_imr(ah, 0);
274c7c36 2366 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2367 }
2368 ath5k_txq_cleanup(sc);
2369 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2370 ath5k_rx_stop(sc);
2371 ath5k_hw_phy_disable(ah);
2372 } else
2373 sc->rxlink = NULL;
2374
2375 return 0;
2376}
2377
2378/*
2379 * Stop the device, grabbing the top-level lock to protect
2380 * against concurrent entry through ath5k_init (which can happen
2381 * if another thread does a system call and the thread doing the
2382 * stop is preempted).
2383 */
2384static int
bb2becac 2385ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2386{
2387 int ret;
2388
2389 mutex_lock(&sc->lock);
2390 ret = ath5k_stop_locked(sc);
2391 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2392 /*
2393 * Set the chip in full sleep mode. Note that we are
2394 * careful to do this only when bringing the interface
2395 * completely to a stop. When the chip is in this state
2396 * it must be carefully woken up or references to
2397 * registers in the PCI clock domain may freeze the bus
2398 * (and system). This varies by chip and is mostly an
2399 * issue with newer parts that go to sleep more quickly.
2400 */
2401 if (sc->ah->ah_mac_srev >= 0x78) {
2402 /*
2403 * XXX
2404 * don't put newer MAC revisions > 7.8 to sleep because
2405 * of the above mentioned problems
2406 */
2407 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2408 "not putting device to sleep\n");
2409 } else {
2410 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2411 "putting device to full sleep\n");
2412 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2413 }
2414 }
2415 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2416
274c7c36 2417 mmiowb();
fa1c114f
JS		 2418 mutex_unlock(&sc->lock);
2419
2420 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2421 tasklet_kill(&sc->rxtq);
2422 tasklet_kill(&sc->txtq);
2423 tasklet_kill(&sc->restq);
acf3c1a5 2424 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2425
2426 return ret;
2427}
2428
2429static irqreturn_t
2430ath5k_intr(int irq, void *dev_id)
2431{
2432 struct ath5k_softc *sc = dev_id;
2433 struct ath5k_hw *ah = sc->ah;
2434 enum ath5k_int status;
2435 unsigned int counter = 1000;
2436
2437 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2438 !ath5k_hw_is_intr_pending(ah)))
2439 return IRQ_NONE;
2440
2441 do {
fa1c114f
JS		 2442 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2443 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2444 status, sc->imask);
fa1c114f
JS		 2445 if (unlikely(status & AR5K_INT_FATAL)) {
2446 /*
2447 * Fatal errors are unrecoverable.
2448 * Typically these are caused by DMA errors.
2449 */
2450 tasklet_schedule(&sc->restq);
2451 } else if (unlikely(status & AR5K_INT_RXORN)) {
2452 tasklet_schedule(&sc->restq);
2453 } else {
2454 if (status & AR5K_INT_SWBA) {
acf3c1a5 2455 tasklet_schedule(&sc->beacontq);
fa1c114f
JS		 2456 }
2457 if (status & AR5K_INT_RXEOL) {
2458 /*
2459 * NB: the hardware should re-read the link when
2460 * RXE bit is written, but it doesn't work at
2461 * least on older hardware revs.
2462 */
2463 sc->rxlink = NULL;
2464 }
2465 if (status & AR5K_INT_TXURN) {
2466 /* bump tx trigger level */
2467 ath5k_hw_update_tx_triglevel(ah, true);
2468 }
4c674c60 2469 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2470 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2471 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2472 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2473 tasklet_schedule(&sc->txtq);
2474 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2475 /* TODO */
fa1c114f
JS		 2476 }
2477 if (status & AR5K_INT_MIB) {
194828a2
NK		 2478 /*
2479 * These stats are also used for ANI i think
2480 * so how about updating them more often ?
2481 */
2482 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2483 }
2484 }
2485 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2486
2487 if (unlikely(!counter))
2488 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2489
2490 return IRQ_HANDLED;
2491}
2492
2493static void
2494ath5k_tasklet_reset(unsigned long data)
2495{
2496 struct ath5k_softc *sc = (void *)data;
2497
d7dc1003 2498 ath5k_reset_wake(sc);
fa1c114f
JS		 2499}
2500
2501/*
2502 * Periodically recalibrate the PHY to account
2503 * for temperature/environment changes.
2504 */
2505static void
2506ath5k_calibrate(unsigned long data)
2507{
2508 struct ath5k_softc *sc = (void *)data;
2509 struct ath5k_hw *ah = sc->ah;
2510
2511 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2512 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2513 sc->curchan->hw_value);
fa1c114f 2514
6f3b414a 2515 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2516 /*
2517 * Rfgain is out of bounds, reset the chip
2518 * to load new gain values.
2519 */
2520 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2521 ath5k_reset_wake(sc);
fa1c114f
JS		 2522 }
2523 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2524 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2525 ieee80211_frequency_to_channel(
2526 sc->curchan->center_freq));
fa1c114f
JS		 2527
2528 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2529 msecs_to_jiffies(ath5k_calinterval * 1000)));
2530}
2531
2532
fa1c114f
JS		 2533/********************\
2534* Mac80211 functions *
2535\********************/
2536
2537static int
e039fa4a 2538ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2539{
2540 struct ath5k_softc *sc = hw->priv;
2541 struct ath5k_buf *bf;
2542 unsigned long flags;
2543 int hdrlen;
0fe45b1d 2544 int padsize;
fa1c114f
JS		 2545
2546 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2547
05c914fe 2548 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2549 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2550
2551 /*
2552 * the hardware expects the header padded to 4 byte boundaries
2553 * if this is not the case we add the padding after the header
2554 */
2555 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2556 padsize = ath5k_pad_size(hdrlen);
2557 if (padsize) {
0fe45b1d
BP		 2558
2559 if (skb_headroom(skb) < padsize) {
fa1c114f 2560 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2561 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2562 goto drop_packet;
fa1c114f 2563 }
0fe45b1d
BP		 2564 skb_push(skb, padsize);
2565 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2566 }
2567
fa1c114f
JS		 2568 spin_lock_irqsave(&sc->txbuflock, flags);
2569 if (list_empty(&sc->txbuf)) {
2570 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2571 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2572 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2573 goto drop_packet;
fa1c114f
JS		 2574 }
2575 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2576 list_del(&bf->list);
2577 sc->txbuf_len--;
2578 if (list_empty(&sc->txbuf))
2579 ieee80211_stop_queues(hw);
2580 spin_unlock_irqrestore(&sc->txbuflock, flags);
2581
2582 bf->skb = skb;
2583
e039fa4a 2584 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2585 bf->skb = NULL;
2586 spin_lock_irqsave(&sc->txbuflock, flags);
2587 list_add_tail(&bf->list, &sc->txbuf);
2588 sc->txbuf_len++;
2589 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2590 goto drop_packet;
fa1c114f 2591 }
5a0fe8ac 2592 return NETDEV_TX_OK;
fa1c114f 2593
5a0fe8ac
BC		 2594drop_packet:
2595 dev_kfree_skb_any(skb);
71ef99c8 2596 return NETDEV_TX_OK;
fa1c114f
JS		 2597}
2598
209d889b
BC		 2599/*
2600 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2601 * and change to the given channel.
2602 */
fa1c114f 2603static int
209d889b 2604ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2605{
fa1c114f
JS		 2606 struct ath5k_hw *ah = sc->ah;
2607 int ret;
2608
2609 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2610
209d889b 2611 if (chan) {
c6e387a2 2612 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2613 ath5k_txq_cleanup(sc);
2614 ath5k_rx_stop(sc);
209d889b
BC		 2615
2616 sc->curchan = chan;
2617 sc->curband = &sc->sbands[chan->band];
d7dc1003 2618 }
fa1c114f 2619 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2620 if (ret) {
fa1c114f
JS		 2621 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2622 goto err;
2623 }
d7dc1003 2624
fa1c114f 2625 ret = ath5k_rx_start(sc);
d7dc1003 2626 if (ret) {
fa1c114f
JS		 2627 ATH5K_ERR(sc, "can't start recv logic\n");
2628 goto err;
2629 }
d7dc1003 2630
fa1c114f 2631 /*
d7dc1003
JS		 2632 * Change channels and update the h/w rate map if we're switching;
2633 * e.g. 11a to 11b/g.
2634 *
2635 * We may be doing a reset in response to an ioctl that changes the
2636 * channel so update any state that might change as a result.
fa1c114f
JS		 2637 *
2638 * XXX needed?
2639 */
2640/* ath5k_chan_change(sc, c); */
fa1c114f 2641
d7dc1003
JS		 2642 ath5k_beacon_config(sc);
2643 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2644
2645 return 0;
2646err:
2647 return ret;
2648}
2649
d7dc1003
JS		 2650static int
2651ath5k_reset_wake(struct ath5k_softc *sc)
2652{
2653 int ret;
2654
209d889b 2655 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2656 if (!ret)
2657 ieee80211_wake_queues(sc->hw);
2658
2659 return ret;
2660}
2661
fa1c114f
JS		 2662static int ath5k_start(struct ieee80211_hw *hw)
2663{
bb2becac 2664 return ath5k_init(hw->priv);
fa1c114f
JS		 2665}
2666
2667static void ath5k_stop(struct ieee80211_hw *hw)
2668{
bb2becac 2669 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2670}
2671
2672static int ath5k_add_interface(struct ieee80211_hw *hw,
2673 struct ieee80211_if_init_conf *conf)
2674{
2675 struct ath5k_softc *sc = hw->priv;
2676 int ret;
2677
2678 mutex_lock(&sc->lock);
32bfd35d 2679 if (sc->vif) {
fa1c114f
JS		 2680 ret = 0;
2681 goto end;
2682 }
2683
32bfd35d 2684 sc->vif = conf->vif;
fa1c114f
JS		 2685
2686 switch (conf->type) {
da966bca 2687 case NL80211_IFTYPE_AP:
05c914fe
JB		 2688 case NL80211_IFTYPE_STATION:
2689 case NL80211_IFTYPE_ADHOC:
b706e65b 2690 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2691 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2692 sc->opmode = conf->type;
2693 break;
2694 default:
2695 ret = -EOPNOTSUPP;
2696 goto end;
2697 }
67d2e2df
JS		 2698
2699 /* Set to a reasonable value. Note that this will
2700 * be set to mac80211's value at ath5k_config(). */
2701 sc->bintval = 1000;
0e149cf5 2702 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2703
fa1c114f
JS		 2704 ret = 0;
2705end:
2706 mutex_unlock(&sc->lock);
2707 return ret;
2708}
2709
2710static void
2711ath5k_remove_interface(struct ieee80211_hw *hw,
2712 struct ieee80211_if_init_conf *conf)
2713{
2714 struct ath5k_softc *sc = hw->priv;
0e149cf5 2715 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2716
2717 mutex_lock(&sc->lock);
32bfd35d 2718 if (sc->vif != conf->vif)
fa1c114f
JS		 2719 goto end;
2720
0e149cf5 2721 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2722 sc->vif = NULL;
fa1c114f
JS		 2723end:
2724 mutex_unlock(&sc->lock);
2725}
2726
d8ee398d
LR		 2727/*
2728 * TODO: Phy disable/diversity etc
2729 */
fa1c114f 2730static int
e8975581 2731ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2732{
2733 struct ath5k_softc *sc = hw->priv;
e8975581 2734 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2735 int ret;
2736
2737 mutex_lock(&sc->lock);
fa1c114f 2738
e535c1ac 2739 sc->bintval = conf->beacon_int;
d8ee398d 2740 sc->power_level = conf->power_level;
fa1c114f 2741
be009370
BC		 2742 ret = ath5k_chan_set(sc, conf->channel);
2743
2744 mutex_unlock(&sc->lock);
2745 return ret;
fa1c114f
JS		 2746}
2747
2748static int
32bfd35d 2749ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2750 struct ieee80211_if_conf *conf)
2751{
2752 struct ath5k_softc *sc = hw->priv;
2753 struct ath5k_hw *ah = sc->ah;
fa8419d0 2754 int ret = 0;
fa1c114f 2755
fa1c114f 2756 mutex_lock(&sc->lock);
32bfd35d 2757 if (sc->vif != vif) {
fa1c114f
JS		 2758 ret = -EIO;
2759 goto unlock;
2760 }
da966bca 2761 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2762 /* Cache for later use during resets */
2763 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2764 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2765 * a clean way of letting us retrieve this yet. */
2766 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2767 mmiowb();
fa1c114f 2768 }
9d139c81 2769 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2770 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2771 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2772 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2773 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2774 if (!beacon) {
2775 ret = -ENOMEM;
2776 goto unlock;
2777 }
da966bca 2778 ath5k_beacon_update(sc, beacon);
9d139c81 2779 }
fa1c114f 2780
fa1c114f
JS		 2781unlock:
2782 mutex_unlock(&sc->lock);
2783 return ret;
2784}
2785
2786#define SUPPORTED_FIF_FLAGS \
2787 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2788 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2789 FIF_BCN_PRBRESP_PROMISC
2790/*
2791 * o always accept unicast, broadcast, and multicast traffic
2792 * o multicast traffic for all BSSIDs will be enabled if mac80211
2793 * says it should be
2794 * o maintain current state of phy ofdm or phy cck error reception.
2795 * If the hardware detects any of these type of errors then
2796 * ath5k_hw_get_rx_filter() will pass to us the respective
2797 * hardware filters to be able to receive these type of frames.
2798 * o probe request frames are accepted only when operating in
2799 * hostap, adhoc, or monitor modes
2800 * o enable promiscuous mode according to the interface state
2801 * o accept beacons:
2802 * - when operating in adhoc mode so the 802.11 layer creates
2803 * node table entries for peers,
2804 * - when operating in station mode for collecting rssi data when
2805 * the station is otherwise quiet, or
2806 * - when scanning
2807 */
2808static void ath5k_configure_filter(struct ieee80211_hw *hw,
2809 unsigned int changed_flags,
2810 unsigned int *new_flags,
2811 int mc_count, struct dev_mc_list *mclist)
2812{
2813 struct ath5k_softc *sc = hw->priv;
2814 struct ath5k_hw *ah = sc->ah;
2815 u32 mfilt[2], val, rfilt;
2816 u8 pos;
2817 int i;
2818
2819 mfilt[0] = 0;
2820 mfilt[1] = 0;
2821
2822 /* Only deal with supported flags */
2823 changed_flags &= SUPPORTED_FIF_FLAGS;
2824 *new_flags &= SUPPORTED_FIF_FLAGS;
2825
2826 /* If HW detects any phy or radar errors, leave those filters on.
2827 * Also, always enable Unicast, Broadcasts and Multicast
2828 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2829 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2830 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2831 AR5K_RX_FILTER_MCAST);
2832
2833 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2834 if (*new_flags & FIF_PROMISC_IN_BSS) {
2835 rfilt |= AR5K_RX_FILTER_PROM;
2836 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2837 } else {
fa1c114f 2838 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2839 }
fa1c114f
JS		 2840 }
2841
2842 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2843 if (*new_flags & FIF_ALLMULTI) {
2844 mfilt[0] = ~0;
2845 mfilt[1] = ~0;
2846 } else {
2847 for (i = 0; i < mc_count; i++) {
2848 if (!mclist)
2849 break;
2850 /* calculate XOR of eight 6-bit values */
533dd1b0 2851 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2852 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2853 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2854 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2855 pos &= 0x3f;
2856 mfilt[pos / 32] |= (1 << (pos % 32));
2857 /* XXX: we might be able to just do this instead,
2858 * but not sure, needs testing, if we do use this we'd
2859 * neet to inform below to not reset the mcast */
2860 /* ath5k_hw_set_mcast_filterindex(ah,
2861 * mclist->dmi_addr[5]); */
2862 mclist = mclist->next;
2863 }
2864 }
2865
2866 /* This is the best we can do */
2867 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2868 rfilt |= AR5K_RX_FILTER_PHYERR;
2869
2870 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2871 * and probes for any BSSID, this needs testing */
2872 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2873 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2874
2875 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2876 * set we should only pass on control frames for this
2877 * station. This needs testing. I believe right now this
2878 * enables *all* control frames, which is OK.. but
2879 * but we should see if we can improve on granularity */
2880 if (*new_flags & FIF_CONTROL)
2881 rfilt |= AR5K_RX_FILTER_CONTROL;
2882
2883 /* Additional settings per mode -- this is per ath5k */
2884
2885 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2886
05c914fe 2887 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2888 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2889 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2890 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2891 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2892 if (sc->opmode != NL80211_IFTYPE_AP &&
2893 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2894 test_bit(ATH_STAT_PROMISC, sc->status))
2895 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2896 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2897 sc->opmode == NL80211_IFTYPE_ADHOC ||
2898 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2899 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2900 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2901 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2902 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2903
2904 /* Set filters */
0bbac08f 2905 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2906
2907 /* Set multicast bits */
2908 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2909 /* Set the cached hw filter flags, this will alter actually
2910 * be set in HW */
2911 sc->filter_flags = rfilt;
2912}
2913
2914static int
2915ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2916 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2917 struct ieee80211_key_conf *key)
fa1c114f
JS		 2918{
2919 struct ath5k_softc *sc = hw->priv;
2920 int ret = 0;
2921
9ad9a26e
BC		 2922 if (modparam_nohwcrypt)
2923 return -EOPNOTSUPP;
2924
0bbac08f 2925 switch (key->alg) {
fa1c114f 2926 case ALG_WEP:
fa1c114f 2927 case ALG_TKIP:
3f64b435 2928 break;
fa1c114f
JS		 2929 case ALG_CCMP:
2930 return -EOPNOTSUPP;
2931 default:
2932 WARN_ON(1);
2933 return -EINVAL;
2934 }
2935
2936 mutex_lock(&sc->lock);
2937
2938 switch (cmd) {
2939 case SET_KEY:
dc822b5d
JB		 2940 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2941 sta ? sta->addr : NULL);
fa1c114f
JS		 2942 if (ret) {
2943 ATH5K_ERR(sc, "can't set the key\n");
2944 goto unlock;
2945 }
2946 __set_bit(key->keyidx, sc->keymap);
2947 key->hw_key_idx = key->keyidx;
3f64b435
BC		 2948 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2949 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 2950 break;
2951 case DISABLE_KEY:
2952 ath5k_hw_reset_key(sc->ah, key->keyidx);
2953 __clear_bit(key->keyidx, sc->keymap);
2954 break;
2955 default:
2956 ret = -EINVAL;
2957 goto unlock;
2958 }
2959
2960unlock:
274c7c36 2961 mmiowb();
fa1c114f
JS		 2962 mutex_unlock(&sc->lock);
2963 return ret;
2964}
2965
2966static int
2967ath5k_get_stats(struct ieee80211_hw *hw,
2968 struct ieee80211_low_level_stats *stats)
2969{
2970 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2971 struct ath5k_hw *ah = sc->ah;
2972
2973 /* Force update */
2974 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2975
2976 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2977
2978 return 0;
2979}
2980
2981static int
2982ath5k_get_tx_stats(struct ieee80211_hw *hw,
2983 struct ieee80211_tx_queue_stats *stats)
2984{
2985 struct ath5k_softc *sc = hw->priv;
2986
2987 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2988
2989 return 0;
2990}
2991
2992static u64
2993ath5k_get_tsf(struct ieee80211_hw *hw)
2994{
2995 struct ath5k_softc *sc = hw->priv;
2996
2997 return ath5k_hw_get_tsf64(sc->ah);
2998}
2999
3b5d665b
AF		 3000static void
3001ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3002{
3003 struct ath5k_softc *sc = hw->priv;
3004
3005 ath5k_hw_set_tsf64(sc->ah, tsf);
3006}
3007
fa1c114f
JS		 3008static void
3009ath5k_reset_tsf(struct ieee80211_hw *hw)
3010{
3011 struct ath5k_softc *sc = hw->priv;
3012
9804b98d
BR		 3013 /*
3014 * in IBSS mode we need to update the beacon timers too.
3015 * this will also reset the TSF if we call it with 0
3016 */
05c914fe 3017 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3018 ath5k_beacon_update_timers(sc, 0);
3019 else
3020 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3021}
3022
3023static int
da966bca 3024ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3025{
00482973 3026 unsigned long flags;
fa1c114f
JS		 3027 int ret;
3028
3029 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3030
00482973 3031 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3032 ath5k_txbuf_free(sc, sc->bbuf);
3033 sc->bbuf->skb = skb;
e039fa4a 3034 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3035 if (ret)
3036 sc->bbuf->skb = NULL;
00482973
JS		 3037 spin_unlock_irqrestore(&sc->block, flags);
3038 if (!ret) {
fa1c114f 3039 ath5k_beacon_config(sc);
274c7c36
JS		 3040 mmiowb();
3041 }
fa1c114f 3042
fa1c114f
JS		 3043 return ret;
3044}
02969b38
MX		 3045static void
3046set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3047{
3048 struct ath5k_softc *sc = hw->priv;
3049 struct ath5k_hw *ah = sc->ah;
3050 u32 rfilt;
3051 rfilt = ath5k_hw_get_rx_filter(ah);
3052 if (enable)
3053 rfilt |= AR5K_RX_FILTER_BEACON;
3054 else
3055 rfilt &= ~AR5K_RX_FILTER_BEACON;
3056 ath5k_hw_set_rx_filter(ah, rfilt);
3057 sc->filter_flags = rfilt;
3058}
fa1c114f 3059
02969b38
MX		 3060static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3061 struct ieee80211_vif *vif,
3062 struct ieee80211_bss_conf *bss_conf,
3063 u32 changes)
3064{
3065 struct ath5k_softc *sc = hw->priv;
3066 if (changes & BSS_CHANGED_ASSOC) {
3067 mutex_lock(&sc->lock);
3068 sc->assoc = bss_conf->assoc;
3069 if (sc->opmode == NL80211_IFTYPE_STATION)
3070 set_beacon_filter(hw, sc->assoc);
3071 mutex_unlock(&sc->lock);
3072 }
3073}
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