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ath5k: remove unused led_off parameter
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 243static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 244 struct sk_buff *skb);
02969b38
MX		 245static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif,
247 struct ieee80211_bss_conf *bss_conf,
248 u32 changes);
fa1c114f
JS		 249
250static struct ieee80211_ops ath5k_hw_ops = {
251 .tx = ath5k_tx,
252 .start = ath5k_start,
253 .stop = ath5k_stop,
254 .add_interface = ath5k_add_interface,
255 .remove_interface = ath5k_remove_interface,
256 .config = ath5k_config,
257 .config_interface = ath5k_config_interface,
258 .configure_filter = ath5k_configure_filter,
259 .set_key = ath5k_set_key,
260 .get_stats = ath5k_get_stats,
261 .conf_tx = NULL,
262 .get_tx_stats = ath5k_get_tx_stats,
263 .get_tsf = ath5k_get_tsf,
264 .reset_tsf = ath5k_reset_tsf,
02969b38 265 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 266};
267
268/*
269 * Prototypes - Internal functions
270 */
271/* Attach detach */
272static int ath5k_attach(struct pci_dev *pdev,
273 struct ieee80211_hw *hw);
274static void ath5k_detach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276/* Channel/mode setup */
277static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 278static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
279 struct ieee80211_channel *channels,
280 unsigned int mode,
281 unsigned int max);
63266a65 282static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 283static int ath5k_chan_set(struct ath5k_softc *sc,
284 struct ieee80211_channel *chan);
285static void ath5k_setcurmode(struct ath5k_softc *sc,
286 unsigned int mode);
287static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 288
fa1c114f
JS		 289/* Descriptor setup */
290static int ath5k_desc_alloc(struct ath5k_softc *sc,
291 struct pci_dev *pdev);
292static void ath5k_desc_free(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294/* Buffers setup */
295static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
296 struct ath5k_buf *bf);
297static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 298 struct ath5k_buf *bf);
fa1c114f
JS		 299static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
300 struct ath5k_buf *bf)
301{
302 BUG_ON(!bf);
303 if (!bf->skb)
304 return;
305 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
306 PCI_DMA_TODEVICE);
00482973 307 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 308 bf->skb = NULL;
309}
310
311/* Queues setup */
312static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
313 int qtype, int subtype);
314static int ath5k_beaconq_setup(struct ath5k_hw *ah);
315static int ath5k_beaconq_config(struct ath5k_softc *sc);
316static void ath5k_txq_drainq(struct ath5k_softc *sc,
317 struct ath5k_txq *txq);
318static void ath5k_txq_cleanup(struct ath5k_softc *sc);
319static void ath5k_txq_release(struct ath5k_softc *sc);
320/* Rx handling */
321static int ath5k_rx_start(struct ath5k_softc *sc);
322static void ath5k_rx_stop(struct ath5k_softc *sc);
323static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
324 struct ath5k_desc *ds,
b47f407b
BR		 325 struct sk_buff *skb,
326 struct ath5k_rx_status *rs);
fa1c114f
JS		 327static void ath5k_tasklet_rx(unsigned long data);
328/* Tx handling */
329static void ath5k_tx_processq(struct ath5k_softc *sc,
330 struct ath5k_txq *txq);
331static void ath5k_tasklet_tx(unsigned long data);
332/* Beacon handling */
333static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 334 struct ath5k_buf *bf);
fa1c114f
JS		 335static void ath5k_beacon_send(struct ath5k_softc *sc);
336static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 337static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 338
339static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
340{
341 u64 tsf = ath5k_hw_get_tsf64(ah);
342
343 if ((tsf & 0x7fff) < rstamp)
344 tsf -= 0x8000;
345
346 return (tsf & ~0x7fff) | rstamp;
347}
348
349/* Interrupt handling */
bb2becac 350static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 351static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 352static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 353static irqreturn_t ath5k_intr(int irq, void *dev_id);
354static void ath5k_tasklet_reset(unsigned long data);
355
356static void ath5k_calibrate(unsigned long data);
357/* LED functions */
3a078876
BC		 358static int ath5k_init_leds(struct ath5k_softc *sc);
359static void ath5k_led_enable(struct ath5k_softc *sc);
360static void ath5k_led_off(struct ath5k_softc *sc);
361static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 362
363/*
364 * Module init/exit functions
365 */
366static int __init
367init_ath5k_pci(void)
368{
369 int ret;
370
371 ath5k_debug_init();
372
04a9e451 373 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 374 if (ret) {
375 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
376 return ret;
377 }
378
379 return 0;
380}
381
382static void __exit
383exit_ath5k_pci(void)
384{
04a9e451 385 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 386
387 ath5k_debug_finish();
388}
389
390module_init(init_ath5k_pci);
391module_exit(exit_ath5k_pci);
392
393
394/********************\
395* PCI Initialization *
396\********************/
397
398static const char *
399ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
400{
401 const char *name = "xxxxx";
402 unsigned int i;
403
404 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
405 if (srev_names[i].sr_type != type)
406 continue;
75d0edb8
NK		 407
408 if ((val & 0xf0) == srev_names[i].sr_val)
409 name = srev_names[i].sr_name;
410
411 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 412 name = srev_names[i].sr_name;
413 break;
414 }
415 }
416
417 return name;
418}
419
420static int __devinit
421ath5k_pci_probe(struct pci_dev *pdev,
422 const struct pci_device_id *id)
423{
424 void __iomem *mem;
425 struct ath5k_softc *sc;
426 struct ieee80211_hw *hw;
427 int ret;
428 u8 csz;
429
430 ret = pci_enable_device(pdev);
431 if (ret) {
432 dev_err(&pdev->dev, "can't enable device\n");
433 goto err;
434 }
435
436 /* XXX 32-bit addressing only */
437 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
438 if (ret) {
439 dev_err(&pdev->dev, "32-bit DMA not available\n");
440 goto err_dis;
441 }
442
443 /*
444 * Cache line size is used to size and align various
445 * structures used to communicate with the hardware.
446 */
447 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
448 if (csz == 0) {
449 /*
450 * Linux 2.4.18 (at least) writes the cache line size
451 * register as a 16-bit wide register which is wrong.
452 * We must have this setup properly for rx buffer
453 * DMA to work so force a reasonable value here if it
454 * comes up zero.
455 */
456 csz = L1_CACHE_BYTES / sizeof(u32);
457 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
458 }
459 /*
460 * The default setting of latency timer yields poor results,
461 * set it to the value used by other systems. It may be worth
462 * tweaking this setting more.
463 */
464 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
465
466 /* Enable bus mastering */
467 pci_set_master(pdev);
468
469 /*
470 * Disable the RETRY_TIMEOUT register (0x41) to keep
471 * PCI Tx retries from interfering with C3 CPU state.
472 */
473 pci_write_config_byte(pdev, 0x41, 0);
474
475 ret = pci_request_region(pdev, 0, "ath5k");
476 if (ret) {
477 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
478 goto err_dis;
479 }
480
481 mem = pci_iomap(pdev, 0, 0);
482 if (!mem) {
483 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
484 ret = -EIO;
485 goto err_reg;
486 }
487
488 /*
489 * Allocate hw (mac80211 main struct)
490 * and hw->priv (driver private data)
491 */
492 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
493 if (hw == NULL) {
494 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
495 ret = -ENOMEM;
496 goto err_map;
497 }
498
499 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
500
501 /* Initialize driver private data */
502 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 503 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
504 IEEE80211_HW_SIGNAL_DBM |
505 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 506
507 hw->wiphy->interface_modes =
508 BIT(NL80211_IFTYPE_STATION) |
509 BIT(NL80211_IFTYPE_ADHOC) |
510 BIT(NL80211_IFTYPE_MESH_POINT);
511
fa1c114f
JS		 512 hw->extra_tx_headroom = 2;
513 hw->channel_change_time = 5000;
fa1c114f
JS		 514 sc = hw->priv;
515 sc->hw = hw;
516 sc->pdev = pdev;
517
518 ath5k_debug_init_device(sc);
519
520 /*
521 * Mark the device as detached to avoid processing
522 * interrupts until setup is complete.
523 */
524 __set_bit(ATH_STAT_INVALID, sc->status);
525
526 sc->iobase = mem; /* So we can unmap it on detach */
527 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 528 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 529 mutex_init(&sc->lock);
530 spin_lock_init(&sc->rxbuflock);
531 spin_lock_init(&sc->txbuflock);
00482973 532 spin_lock_init(&sc->block);
fa1c114f
JS		 533
534 /* Set private data */
535 pci_set_drvdata(pdev, hw);
536
fa1c114f
JS		 537 /* Setup interrupt handler */
538 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
539 if (ret) {
540 ATH5K_ERR(sc, "request_irq failed\n");
541 goto err_free;
542 }
543
544 /* Initialize device */
545 sc->ah = ath5k_hw_attach(sc, id->driver_data);
546 if (IS_ERR(sc->ah)) {
547 ret = PTR_ERR(sc->ah);
548 goto err_irq;
549 }
550
2f7fe870
FF		 551 /* set up multi-rate retry capabilities */
552 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 553 hw->max_rates = 4;
554 hw->max_rate_tries = 11;
2f7fe870
FF		 555 }
556
fa1c114f
JS		 557 /* Finish private driver data initialization */
558 ret = ath5k_attach(pdev, hw);
559 if (ret)
560 goto err_ah;
561
562 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 563 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 564 sc->ah->ah_mac_srev,
565 sc->ah->ah_phy_revision);
566
400ec45a 567 if (!sc->ah->ah_single_chip) {
fa1c114f 568 /* Single chip radio (!RF5111) */
400ec45a
LR		 569 if (sc->ah->ah_radio_5ghz_revision &&
570 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 571 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 572 if (!test_bit(AR5K_MODE_11A,
573 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 574 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 575 ath5k_chip_name(AR5K_VERSION_RAD,
576 sc->ah->ah_radio_5ghz_revision),
577 sc->ah->ah_radio_5ghz_revision);
578 /* No 2GHz support (5110 and some
579 * 5Ghz only cards) -> report 5Ghz radio */
580 } else if (!test_bit(AR5K_MODE_11B,
581 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 582 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 583 ath5k_chip_name(AR5K_VERSION_RAD,
584 sc->ah->ah_radio_5ghz_revision),
585 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 586 /* Multiband radio */
587 } else {
588 ATH5K_INFO(sc, "RF%s multiband radio found"
589 " (0x%x)\n",
400ec45a
LR		 590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 593 }
594 }
400ec45a
LR		 595 /* Multi chip radio (RF5111 - RF2111) ->
596 * report both 2GHz/5GHz radios */
597 else if (sc->ah->ah_radio_5ghz_revision &&
598 sc->ah->ah_radio_2ghz_revision){
fa1c114f 599 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 600 ath5k_chip_name(AR5K_VERSION_RAD,
601 sc->ah->ah_radio_5ghz_revision),
602 sc->ah->ah_radio_5ghz_revision);
fa1c114f 603 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_2ghz_revision),
606 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 607 }
608 }
609
610
611 /* ready to process interrupts */
612 __clear_bit(ATH_STAT_INVALID, sc->status);
613
614 return 0;
615err_ah:
616 ath5k_hw_detach(sc->ah);
617err_irq:
618 free_irq(pdev->irq, sc);
619err_free:
fa1c114f
JS		 620 ieee80211_free_hw(hw);
621err_map:
622 pci_iounmap(pdev, mem);
623err_reg:
624 pci_release_region(pdev, 0);
625err_dis:
626 pci_disable_device(pdev);
627err:
628 return ret;
629}
630
631static void __devexit
632ath5k_pci_remove(struct pci_dev *pdev)
633{
634 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
635 struct ath5k_softc *sc = hw->priv;
636
637 ath5k_debug_finish_device(sc);
638 ath5k_detach(pdev, hw);
639 ath5k_hw_detach(sc->ah);
640 free_irq(pdev->irq, sc);
fa1c114f
JS		 641 pci_iounmap(pdev, sc->iobase);
642 pci_release_region(pdev, 0);
643 pci_disable_device(pdev);
644 ieee80211_free_hw(hw);
645}
646
647#ifdef CONFIG_PM
648static int
649ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
650{
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
653
3a078876 654 ath5k_led_off(sc);
fa1c114f 655
3e4242b9 656 free_irq(pdev->irq, sc);
fa1c114f
JS		 657 pci_save_state(pdev);
658 pci_disable_device(pdev);
659 pci_set_power_state(pdev, PCI_D3hot);
660
661 return 0;
662}
663
664static int
665ath5k_pci_resume(struct pci_dev *pdev)
666{
667 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
668 struct ath5k_softc *sc = hw->priv;
bc1b32d6 669 int err;
fa1c114f 670
3e4242b9 671 pci_restore_state(pdev);
fa1c114f
JS		 672
673 err = pci_enable_device(pdev);
674 if (err)
675 return err;
676
fa1c114f
JS		 677 /*
678 * Suspend/Resume resets the PCI configuration space, so we have to
679 * re-disable the RETRY_TIMEOUT register (0x41) to keep
680 * PCI Tx retries from interfering with C3 CPU state
681 */
682 pci_write_config_byte(pdev, 0x41, 0);
683
3e4242b9
JS		 684 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
685 if (err) {
686 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 687 goto err_no_irq;
3e4242b9
JS		 688 }
689
3a078876 690 ath5k_led_enable(sc);
fa1c114f 691 return 0;
bb2becac 692
37465c8a 693err_no_irq:
3e4242b9
JS		 694 pci_disable_device(pdev);
695 return err;
fa1c114f
JS		 696}
697#endif /* CONFIG_PM */
698
699
fa1c114f
JS		 700/***********************\
701* Driver Initialization *
702\***********************/
703
704static int
705ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
706{
707 struct ath5k_softc *sc = hw->priv;
708 struct ath5k_hw *ah = sc->ah;
0e149cf5 709 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 710 int ret;
711
712 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
713
714 /*
715 * Check if the MAC has multi-rate retry support.
716 * We do this by trying to setup a fake extended
717 * descriptor. MAC's that don't have support will
718 * return false w/o doing anything. MAC's that do
719 * support it will return true w/o doing anything.
720 */
c6e387a2 721 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 722 if (ret < 0)
723 goto err;
724 if (ret > 0)
fa1c114f
JS		 725 __set_bit(ATH_STAT_MRRETRY, sc->status);
726
fa1c114f
JS		 727 /*
728 * Collect the channel list. The 802.11 layer
729 * is resposible for filtering this list based
730 * on settings like the phy mode and regulatory
731 * domain restrictions.
732 */
63266a65 733 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 734 if (ret) {
735 ATH5K_ERR(sc, "can't get channels\n");
736 goto err;
737 }
738
739 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 740 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
741 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 742 else
d8ee398d 743 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 744
745 /*
746 * Allocate tx+rx descriptors and populate the lists.
747 */
748 ret = ath5k_desc_alloc(sc, pdev);
749 if (ret) {
750 ATH5K_ERR(sc, "can't allocate descriptors\n");
751 goto err;
752 }
753
754 /*
755 * Allocate hardware transmit queues: one queue for
756 * beacon frames and one data queue for each QoS
757 * priority. Note that hw functions handle reseting
758 * these queues at the needed time.
759 */
760 ret = ath5k_beaconq_setup(ah);
761 if (ret < 0) {
762 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
763 goto err_desc;
764 }
765 sc->bhalq = ret;
766
767 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
768 if (IS_ERR(sc->txq)) {
769 ATH5K_ERR(sc, "can't setup xmit queue\n");
770 ret = PTR_ERR(sc->txq);
771 goto err_bhal;
772 }
773
774 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
775 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
776 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
777 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 778
0e149cf5
BC		 779 ret = ath5k_eeprom_read_mac(ah, mac);
780 if (ret) {
781 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
782 sc->pdev->device);
783 goto err_queues;
784 }
785
fa1c114f
JS		 786 SET_IEEE80211_PERM_ADDR(hw, mac);
787 /* All MAC address bits matter for ACKs */
788 memset(sc->bssidmask, 0xff, ETH_ALEN);
789 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
790
791 ret = ieee80211_register_hw(hw);
792 if (ret) {
793 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
794 goto err_queues;
795 }
796
3a078876
BC		 797 ath5k_init_leds(sc);
798
fa1c114f
JS		 799 return 0;
800err_queues:
801 ath5k_txq_release(sc);
802err_bhal:
803 ath5k_hw_release_tx_queue(ah, sc->bhalq);
804err_desc:
805 ath5k_desc_free(sc, pdev);
806err:
807 return ret;
808}
809
810static void
811ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
812{
813 struct ath5k_softc *sc = hw->priv;
814
815 /*
816 * NB: the order of these is important:
817 * o call the 802.11 layer before detaching ath5k_hw to
818 * insure callbacks into the driver to delete global
819 * key cache entries can be handled
820 * o reclaim the tx queue data structures after calling
821 * the 802.11 layer as we'll get called back to reclaim
822 * node state and potentially want to use them
823 * o to cleanup the tx queues the hal is called, so detach
824 * it last
825 * XXX: ??? detach ath5k_hw ???
826 * Other than that, it's straightforward...
827 */
828 ieee80211_unregister_hw(hw);
829 ath5k_desc_free(sc, pdev);
830 ath5k_txq_release(sc);
831 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 832 ath5k_unregister_leds(sc);
fa1c114f
JS		 833
834 /*
835 * NB: can't reclaim these until after ieee80211_ifdetach
836 * returns because we'll get called back to reclaim node
837 * state and potentially want to use them.
838 */
839}
840
841
842
843
844/********************\
845* Channel/mode setup *
846\********************/
847
848/*
849 * Convert IEEE channel number to MHz frequency.
850 */
851static inline short
852ath5k_ieee2mhz(short chan)
853{
854 if (chan <= 14 || chan >= 27)
855 return ieee80211chan2mhz(chan);
856 else
857 return 2212 + chan * 20;
858}
859
fa1c114f
JS		 860static unsigned int
861ath5k_copy_channels(struct ath5k_hw *ah,
862 struct ieee80211_channel *channels,
863 unsigned int mode,
864 unsigned int max)
865{
d8ee398d 866 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 867
868 if (!test_bit(mode, ah->ah_modes))
869 return 0;
870
fa1c114f 871 switch (mode) {
d8ee398d
LR		 872 case AR5K_MODE_11A:
873 case AR5K_MODE_11A_TURBO:
fa1c114f 874 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 875 size = 220 ;
fa1c114f
JS		 876 chfreq = CHANNEL_5GHZ;
877 break;
d8ee398d
LR		 878 case AR5K_MODE_11B:
879 case AR5K_MODE_11G:
880 case AR5K_MODE_11G_TURBO:
881 size = 26;
fa1c114f
JS		 882 chfreq = CHANNEL_2GHZ;
883 break;
884 default:
885 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
886 return 0;
887 }
888
889 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 890 ch = i + 1 ;
891 freq = ath5k_ieee2mhz(ch);
fa1c114f 892
d8ee398d
LR		 893 /* Check if channel is supported by the chipset */
894 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 895 continue;
896
d8ee398d
LR		 897 /* Write channel info and increment counter */
898 channels[count].center_freq = freq;
a3f4b914
LR		 899 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
900 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 901 switch (mode) {
902 case AR5K_MODE_11A:
903 case AR5K_MODE_11G:
904 channels[count].hw_value = chfreq | CHANNEL_OFDM;
905 break;
906 case AR5K_MODE_11A_TURBO:
907 case AR5K_MODE_11G_TURBO:
908 channels[count].hw_value = chfreq |
909 CHANNEL_OFDM | CHANNEL_TURBO;
910 break;
911 case AR5K_MODE_11B:
d8ee398d
LR		 912 channels[count].hw_value = CHANNEL_B;
913 }
fa1c114f 914
fa1c114f
JS		 915 count++;
916 max--;
917 }
918
919 return count;
920}
921
63266a65
BR		 922static void
923ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
924{
925 u8 i;
926
927 for (i = 0; i < AR5K_MAX_RATES; i++)
928 sc->rate_idx[b->band][i] = -1;
929
930 for (i = 0; i < b->n_bitrates; i++) {
931 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
932 if (b->bitrates[i].hw_value_short)
933 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
934 }
935}
936
d8ee398d 937static int
63266a65 938ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 939{
940 struct ath5k_softc *sc = hw->priv;
d8ee398d 941 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 942 struct ieee80211_supported_band *sband;
943 int max_c, count_c = 0;
944 int i;
fa1c114f 945
d8ee398d 946 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 947 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 948
949 /* 2GHz band */
63266a65
BR		 950 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
951 sband->band = IEEE80211_BAND_2GHZ;
952 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 953
63266a65
BR		 954 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
955 /* G mode */
956 memcpy(sband->bitrates, &ath5k_rates[0],
957 sizeof(struct ieee80211_rate) * 12);
958 sband->n_bitrates = 12;
fa1c114f 959
d8ee398d 960 sband->channels = sc->channels;
d8ee398d 961 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 962 AR5K_MODE_11G, max_c);
fa1c114f 963
63266a65 964 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 965 count_c = sband->n_channels;
63266a65
BR		 966 max_c -= count_c;
967 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
968 /* B mode */
969 memcpy(sband->bitrates, &ath5k_rates[0],
970 sizeof(struct ieee80211_rate) * 4);
971 sband->n_bitrates = 4;
972
973 /* 5211 only supports B rates and uses 4bit rate codes
974 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
975 * fix them up here:
976 */
977 if (ah->ah_version == AR5K_AR5211) {
978 for (i = 0; i < 4; i++) {
979 sband->bitrates[i].hw_value =
980 sband->bitrates[i].hw_value & 0xF;
981 sband->bitrates[i].hw_value_short =
982 sband->bitrates[i].hw_value_short & 0xF;
983 }
984 }
fa1c114f 985
63266a65
BR		 986 sband->channels = sc->channels;
987 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
988 AR5K_MODE_11B, max_c);
d8ee398d 989
63266a65
BR		 990 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
991 count_c = sband->n_channels;
d8ee398d 992 max_c -= count_c;
fa1c114f 993 }
63266a65 994 ath5k_setup_rate_idx(sc, sband);
fa1c114f 995
63266a65 996 /* 5GHz band, A mode */
400ec45a 997 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 998 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
999 sband->band = IEEE80211_BAND_5GHZ;
1000 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1001
63266a65
BR		 1002 memcpy(sband->bitrates, &ath5k_rates[4],
1003 sizeof(struct ieee80211_rate) * 8);
1004 sband->n_bitrates = 8;
fa1c114f 1005
63266a65 1006 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1007 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1008 AR5K_MODE_11A, max_c);
1009
d8ee398d
LR		 1010 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1011 }
63266a65 1012 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1013
b446197c 1014 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1015
1016 return 0;
fa1c114f
JS		 1017}
1018
1019/*
1020 * Set/change channels. If the channel is really being changed,
1021 * it's done by reseting the chip. To accomplish this we must
1022 * first cleanup any pending DMA, then restart stuff after a la
1023 * ath5k_init.
1024 */
1025static int
1026ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1027{
d8ee398d
LR		 1028 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1029 sc->curchan->center_freq, chan->center_freq);
1030
1031 if (chan->center_freq != sc->curchan->center_freq ||
1032 chan->hw_value != sc->curchan->hw_value) {
1033
1034 sc->curchan = chan;
1035 sc->curband = &sc->sbands[chan->band];
fa1c114f 1036
fa1c114f
JS		 1037 /*
1038 * To switch channels clear any pending DMA operations;
1039 * wait long enough for the RX fifo to drain, reset the
1040 * hardware at the new frequency, and then re-enable
1041 * the relevant bits of the h/w.
1042 */
d7dc1003 1043 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1044 }
1045
1046 return 0;
1047}
1048
1049static void
1050ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1051{
fa1c114f 1052 sc->curmode = mode;
d8ee398d 1053
400ec45a 1054 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1055 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1056 } else {
1057 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1058 }
fa1c114f
JS		 1059}
1060
1061static void
1062ath5k_mode_setup(struct ath5k_softc *sc)
1063{
1064 struct ath5k_hw *ah = sc->ah;
1065 u32 rfilt;
1066
1067 /* configure rx filter */
1068 rfilt = sc->filter_flags;
1069 ath5k_hw_set_rx_filter(ah, rfilt);
1070
1071 if (ath5k_hw_hasbssidmask(ah))
1072 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1073
1074 /* configure operational mode */
1075 ath5k_hw_set_opmode(ah);
1076
1077 ath5k_hw_set_mcast_filter(ah, 0, 0);
1078 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1079}
1080
d8ee398d 1081static inline int
63266a65
BR		 1082ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1083{
1084 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1085 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1086}
1087
fa1c114f
JS		 1088/***************\
1089* Buffers setup *
1090\***************/
1091
b6ea0356
BC		 1092static
1093struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1094{
1095 struct sk_buff *skb;
1096 unsigned int off;
1097
1098 /*
1099 * Allocate buffer with headroom_needed space for the
1100 * fake physical layer header at the start.
1101 */
1102 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1103
1104 if (!skb) {
1105 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1106 sc->rxbufsize + sc->cachelsz - 1);
1107 return NULL;
1108 }
1109 /*
1110 * Cache-line-align. This is important (for the
1111 * 5210 at least) as not doing so causes bogus data
1112 * in rx'd frames.
1113 */
1114 off = ((unsigned long)skb->data) % sc->cachelsz;
1115 if (off != 0)
1116 skb_reserve(skb, sc->cachelsz - off);
1117
1118 *skb_addr = pci_map_single(sc->pdev,
1119 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1120 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1121 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1122 dev_kfree_skb(skb);
1123 return NULL;
1124 }
1125 return skb;
1126}
1127
fa1c114f
JS		 1128static int
1129ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1130{
1131 struct ath5k_hw *ah = sc->ah;
1132 struct sk_buff *skb = bf->skb;
1133 struct ath5k_desc *ds;
1134
b6ea0356
BC		 1135 if (!skb) {
1136 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1137 if (!skb)
fa1c114f 1138 return -ENOMEM;
fa1c114f 1139 bf->skb = skb;
fa1c114f
JS		 1140 }
1141
1142 /*
1143 * Setup descriptors. For receive we always terminate
1144 * the descriptor list with a self-linked entry so we'll
1145 * not get overrun under high load (as can happen with a
1146 * 5212 when ANI processing enables PHY error frames).
1147 *
1148 * To insure the last descriptor is self-linked we create
1149 * each descriptor as self-linked and add it to the end. As
1150 * each additional descriptor is added the previous self-linked
1151 * entry is ``fixed'' naturally. This should be safe even
1152 * if DMA is happening. When processing RX interrupts we
1153 * never remove/process the last, self-linked, entry on the
1154 * descriptor list. This insures the hardware always has
1155 * someplace to write a new frame.
1156 */
1157 ds = bf->desc;
1158 ds->ds_link = bf->daddr; /* link to self */
1159 ds->ds_data = bf->skbaddr;
c6e387a2 1160 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1161 skb_tailroom(skb), /* buffer size */
1162 0);
1163
1164 if (sc->rxlink != NULL)
1165 *sc->rxlink = bf->daddr;
1166 sc->rxlink = &ds->ds_link;
1167 return 0;
1168}
1169
1170static int
e039fa4a 1171ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1172{
1173 struct ath5k_hw *ah = sc->ah;
1174 struct ath5k_txq *txq = sc->txq;
1175 struct ath5k_desc *ds = bf->desc;
1176 struct sk_buff *skb = bf->skb;
a888d52d 1177 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1178 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1179 struct ieee80211_rate *rate;
1180 unsigned int mrr_rate[3], mrr_tries[3];
1181 int i, ret;
fa1c114f
JS		 1182
1183 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1184
fa1c114f
JS		 1185 /* XXX endianness */
1186 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1187 PCI_DMA_TODEVICE);
1188
e039fa4a 1189 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1190 flags |= AR5K_TXDESC_NOACK;
1191
281c56dd 1192 pktlen = skb->len;
fa1c114f 1193
d0f09804 1194 if (info->control.hw_key) {
e039fa4a 1195 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1196 pktlen += info->control.hw_key->icv_len;
fa1c114f 1197 }
fa1c114f
JS		 1198 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1199 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1200 (sc->power_level * 2),
e039fa4a 1201 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
e6a9854b 1202 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1203 if (ret)
1204 goto err_unmap;
1205
2f7fe870
FF		 1206 memset(mrr_rate, 0, sizeof(mrr_rate));
1207 memset(mrr_tries, 0, sizeof(mrr_tries));
1208 for (i = 0; i < 3; i++) {
1209 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1210 if (!rate)
1211 break;
1212
1213 mrr_rate[i] = rate->hw_value;
e6a9854b 1214 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1215 }
1216
1217 ah->ah_setup_mrr_tx_desc(ah, ds,
1218 mrr_rate[0], mrr_tries[0],
1219 mrr_rate[1], mrr_tries[1],
1220 mrr_rate[2], mrr_tries[2]);
1221
fa1c114f
JS		 1222 ds->ds_link = 0;
1223 ds->ds_data = bf->skbaddr;
1224
1225 spin_lock_bh(&txq->lock);
1226 list_add_tail(&bf->list, &txq->q);
57ffc589 1227 sc->tx_stats[txq->qnum].len++;
fa1c114f 1228 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1229 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1230 else /* no, so only link it */
1231 *txq->link = bf->daddr;
1232
1233 txq->link = &ds->ds_link;
c6e387a2 1234 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1235 mmiowb();
fa1c114f
JS		 1236 spin_unlock_bh(&txq->lock);
1237
1238 return 0;
1239err_unmap:
1240 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1241 return ret;
1242}
1243
1244/*******************\
1245* Descriptors setup *
1246\*******************/
1247
1248static int
1249ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1250{
1251 struct ath5k_desc *ds;
1252 struct ath5k_buf *bf;
1253 dma_addr_t da;
1254 unsigned int i;
1255 int ret;
1256
1257 /* allocate descriptors */
1258 sc->desc_len = sizeof(struct ath5k_desc) *
1259 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1260 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1261 if (sc->desc == NULL) {
1262 ATH5K_ERR(sc, "can't allocate descriptors\n");
1263 ret = -ENOMEM;
1264 goto err;
1265 }
1266 ds = sc->desc;
1267 da = sc->desc_daddr;
1268 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1269 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1270
1271 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1272 sizeof(struct ath5k_buf), GFP_KERNEL);
1273 if (bf == NULL) {
1274 ATH5K_ERR(sc, "can't allocate bufptr\n");
1275 ret = -ENOMEM;
1276 goto err_free;
1277 }
1278 sc->bufptr = bf;
1279
1280 INIT_LIST_HEAD(&sc->rxbuf);
1281 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1282 bf->desc = ds;
1283 bf->daddr = da;
1284 list_add_tail(&bf->list, &sc->rxbuf);
1285 }
1286
1287 INIT_LIST_HEAD(&sc->txbuf);
1288 sc->txbuf_len = ATH_TXBUF;
1289 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1290 da += sizeof(*ds)) {
1291 bf->desc = ds;
1292 bf->daddr = da;
1293 list_add_tail(&bf->list, &sc->txbuf);
1294 }
1295
1296 /* beacon buffer */
1297 bf->desc = ds;
1298 bf->daddr = da;
1299 sc->bbuf = bf;
1300
1301 return 0;
1302err_free:
1303 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1304err:
1305 sc->desc = NULL;
1306 return ret;
1307}
1308
1309static void
1310ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1311{
1312 struct ath5k_buf *bf;
1313
1314 ath5k_txbuf_free(sc, sc->bbuf);
1315 list_for_each_entry(bf, &sc->txbuf, list)
1316 ath5k_txbuf_free(sc, bf);
1317 list_for_each_entry(bf, &sc->rxbuf, list)
1318 ath5k_txbuf_free(sc, bf);
1319
1320 /* Free memory associated with all descriptors */
1321 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1322
1323 kfree(sc->bufptr);
1324 sc->bufptr = NULL;
1325}
1326
1327
1328
1329
1330
1331/**************\
1332* Queues setup *
1333\**************/
1334
1335static struct ath5k_txq *
1336ath5k_txq_setup(struct ath5k_softc *sc,
1337 int qtype, int subtype)
1338{
1339 struct ath5k_hw *ah = sc->ah;
1340 struct ath5k_txq *txq;
1341 struct ath5k_txq_info qi = {
1342 .tqi_subtype = subtype,
1343 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1344 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1345 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1346 };
1347 int qnum;
1348
1349 /*
1350 * Enable interrupts only for EOL and DESC conditions.
1351 * We mark tx descriptors to receive a DESC interrupt
1352 * when a tx queue gets deep; otherwise waiting for the
1353 * EOL to reap descriptors. Note that this is done to
1354 * reduce interrupt load and this only defers reaping
1355 * descriptors, never transmitting frames. Aside from
1356 * reducing interrupts this also permits more concurrency.
1357 * The only potential downside is if the tx queue backs
1358 * up in which case the top half of the kernel may backup
1359 * due to a lack of tx descriptors.
1360 */
1361 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1362 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1363 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1364 if (qnum < 0) {
1365 /*
1366 * NB: don't print a message, this happens
1367 * normally on parts with too few tx queues
1368 */
1369 return ERR_PTR(qnum);
1370 }
1371 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1372 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1373 qnum, ARRAY_SIZE(sc->txqs));
1374 ath5k_hw_release_tx_queue(ah, qnum);
1375 return ERR_PTR(-EINVAL);
1376 }
1377 txq = &sc->txqs[qnum];
1378 if (!txq->setup) {
1379 txq->qnum = qnum;
1380 txq->link = NULL;
1381 INIT_LIST_HEAD(&txq->q);
1382 spin_lock_init(&txq->lock);
1383 txq->setup = true;
1384 }
1385 return &sc->txqs[qnum];
1386}
1387
1388static int
1389ath5k_beaconq_setup(struct ath5k_hw *ah)
1390{
1391 struct ath5k_txq_info qi = {
1392 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1393 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1394 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1395 /* NB: for dynamic turbo, don't enable any other interrupts */
1396 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1397 };
1398
1399 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1400}
1401
1402static int
1403ath5k_beaconq_config(struct ath5k_softc *sc)
1404{
1405 struct ath5k_hw *ah = sc->ah;
1406 struct ath5k_txq_info qi;
1407 int ret;
1408
1409 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1410 if (ret)
1411 return ret;
05c914fe
JB		 1412 if (sc->opmode == NL80211_IFTYPE_AP ||
1413 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1414 /*
1415 * Always burst out beacon and CAB traffic
1416 * (aifs = cwmin = cwmax = 0)
1417 */
1418 qi.tqi_aifs = 0;
1419 qi.tqi_cw_min = 0;
1420 qi.tqi_cw_max = 0;
05c914fe 1421 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1422 /*
1423 * Adhoc mode; backoff between 0 and (2 * cw_min).
1424 */
1425 qi.tqi_aifs = 0;
1426 qi.tqi_cw_min = 0;
1427 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1428 }
1429
6d91e1d8
BR		 1430 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1431 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1432 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1433
c6e387a2 1434 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1435 if (ret) {
1436 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1437 "hardware queue!\n", __func__);
1438 return ret;
1439 }
1440
1441 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1442}
1443
1444static void
1445ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1446{
1447 struct ath5k_buf *bf, *bf0;
1448
1449 /*
1450 * NB: this assumes output has been stopped and
1451 * we do not need to block ath5k_tx_tasklet
1452 */
1453 spin_lock_bh(&txq->lock);
1454 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1455 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1456
1457 ath5k_txbuf_free(sc, bf);
1458
1459 spin_lock_bh(&sc->txbuflock);
57ffc589 1460 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1461 list_move_tail(&bf->list, &sc->txbuf);
1462 sc->txbuf_len++;
1463 spin_unlock_bh(&sc->txbuflock);
1464 }
1465 txq->link = NULL;
1466 spin_unlock_bh(&txq->lock);
1467}
1468
1469/*
1470 * Drain the transmit queues and reclaim resources.
1471 */
1472static void
1473ath5k_txq_cleanup(struct ath5k_softc *sc)
1474{
1475 struct ath5k_hw *ah = sc->ah;
1476 unsigned int i;
1477
1478 /* XXX return value */
1479 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1480 /* don't touch the hardware if marked invalid */
1481 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1482 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1483 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1484 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1485 if (sc->txqs[i].setup) {
1486 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1488 "link %p\n",
1489 sc->txqs[i].qnum,
c6e387a2 1490 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1491 sc->txqs[i].qnum),
1492 sc->txqs[i].link);
1493 }
1494 }
36d6825b 1495 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1496
1497 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1498 if (sc->txqs[i].setup)
1499 ath5k_txq_drainq(sc, &sc->txqs[i]);
1500}
1501
1502static void
1503ath5k_txq_release(struct ath5k_softc *sc)
1504{
1505 struct ath5k_txq *txq = sc->txqs;
1506 unsigned int i;
1507
1508 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1509 if (txq->setup) {
1510 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1511 txq->setup = false;
1512 }
1513}
1514
1515
1516
1517
1518/*************\
1519* RX Handling *
1520\*************/
1521
1522/*
1523 * Enable the receive h/w following a reset.
1524 */
1525static int
1526ath5k_rx_start(struct ath5k_softc *sc)
1527{
1528 struct ath5k_hw *ah = sc->ah;
1529 struct ath5k_buf *bf;
1530 int ret;
1531
1532 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1533
1534 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1535 sc->cachelsz, sc->rxbufsize);
1536
1537 sc->rxlink = NULL;
1538
1539 spin_lock_bh(&sc->rxbuflock);
1540 list_for_each_entry(bf, &sc->rxbuf, list) {
1541 ret = ath5k_rxbuf_setup(sc, bf);
1542 if (ret != 0) {
1543 spin_unlock_bh(&sc->rxbuflock);
1544 goto err;
1545 }
1546 }
1547 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1548 spin_unlock_bh(&sc->rxbuflock);
1549
c6e387a2
NK		 1550 ath5k_hw_set_rxdp(ah, bf->daddr);
1551 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1552 ath5k_mode_setup(sc); /* set filters, etc. */
1553 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1554
1555 return 0;
1556err:
1557 return ret;
1558}
1559
1560/*
1561 * Disable the receive h/w in preparation for a reset.
1562 */
1563static void
1564ath5k_rx_stop(struct ath5k_softc *sc)
1565{
1566 struct ath5k_hw *ah = sc->ah;
1567
c6e387a2 1568 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1569 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1570 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1571
1572 ath5k_debug_printrxbuffs(sc, ah);
1573
1574 sc->rxlink = NULL; /* just in case */
1575}
1576
1577static unsigned int
1578ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1579 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1580{
1581 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1582 unsigned int keyix, hlen;
fa1c114f 1583
b47f407b
BR		 1584 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1585 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1586 return RX_FLAG_DECRYPTED;
1587
1588 /* Apparently when a default key is used to decrypt the packet
1589 the hw does not set the index used to decrypt. In such cases
1590 get the index from the packet. */
798ee985 1591 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1592 if (ieee80211_has_protected(hdr->frame_control) &&
1593 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1594 skb->len >= hlen + 4) {
fa1c114f
JS		 1595 keyix = skb->data[hlen + 3] >> 6;
1596
1597 if (test_bit(keyix, sc->keymap))
1598 return RX_FLAG_DECRYPTED;
1599 }
1600
1601 return 0;
1602}
1603
036cd1ec
BR		 1604
1605static void
6ba81c2c
BR		 1606ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1607 struct ieee80211_rx_status *rxs)
036cd1ec 1608{
6ba81c2c 1609 u64 tsf, bc_tstamp;
036cd1ec
BR		 1610 u32 hw_tu;
1611 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1612
24b56e70 1613 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1614 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1615 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1616 /*
6ba81c2c
BR		 1617 * Received an IBSS beacon with the same BSSID. Hardware *must*
1618 * have updated the local TSF. We have to work around various
1619 * hardware bugs, though...
036cd1ec 1620 */
6ba81c2c
BR		 1621 tsf = ath5k_hw_get_tsf64(sc->ah);
1622 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1623 hw_tu = TSF_TO_TU(tsf);
1624
1625 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1626 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1627 (unsigned long long)bc_tstamp,
1628 (unsigned long long)rxs->mactime,
1629 (unsigned long long)(rxs->mactime - bc_tstamp),
1630 (unsigned long long)tsf);
6ba81c2c
BR		 1631
1632 /*
1633 * Sometimes the HW will give us a wrong tstamp in the rx
1634 * status, causing the timestamp extension to go wrong.
1635 * (This seems to happen especially with beacon frames bigger
1636 * than 78 byte (incl. FCS))
1637 * But we know that the receive timestamp must be later than the
1638 * timestamp of the beacon since HW must have synced to that.
1639 *
1640 * NOTE: here we assume mactime to be after the frame was
1641 * received, not like mac80211 which defines it at the start.
1642 */
1643 if (bc_tstamp > rxs->mactime) {
036cd1ec 1644 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1645 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1646 (unsigned long long)rxs->mactime,
1647 (unsigned long long)tsf);
6ba81c2c 1648 rxs->mactime = tsf;
036cd1ec 1649 }
6ba81c2c
BR		 1650
1651 /*
1652 * Local TSF might have moved higher than our beacon timers,
1653 * in that case we have to update them to continue sending
1654 * beacons. This also takes care of synchronizing beacon sending
1655 * times with other stations.
1656 */
1657 if (hw_tu >= sc->nexttbtt)
1658 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1659 }
1660}
1661
1662
fa1c114f
JS		 1663static void
1664ath5k_tasklet_rx(unsigned long data)
1665{
1666 struct ieee80211_rx_status rxs = {};
b47f407b 1667 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1668 struct sk_buff *skb, *next_skb;
1669 dma_addr_t next_skb_addr;
fa1c114f 1670 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1671 struct ath5k_buf *bf, *bf_last;
fa1c114f 1672 struct ath5k_desc *ds;
fa1c114f
JS		 1673 int ret;
1674 int hdrlen;
0fe45b1d 1675 int padsize;
fa1c114f
JS		 1676
1677 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1678 if (list_empty(&sc->rxbuf)) {
1679 ATH5K_WARN(sc, "empty rx buf pool\n");
1680 goto unlock;
1681 }
1682 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1683 do {
d6894b5b
BC		 1684 rxs.flag = 0;
1685
fa1c114f
JS		 1686 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1687 BUG_ON(bf->skb == NULL);
1688 skb = bf->skb;
1689 ds = bf->desc;
1690
3a0f2c87
JS		 1691 /*
1692 * last buffer must not be freed to ensure proper hardware
1693 * function. When the hardware finishes also a packet next to
1694 * it, we are sure, it doesn't use it anymore and we can go on.
1695 */
1696 if (bf_last == bf)
1697 bf->flags |= 1;
1698 if (bf->flags) {
1699 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1700 struct ath5k_buf, list);
1701 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1702 &rs);
1703 if (ret)
1704 break;
1705 bf->flags &= ~1;
1706 /* skip the overwritten one (even status is martian) */
1707 goto next;
1708 }
fa1c114f 1709
b47f407b 1710 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1711 if (unlikely(ret == -EINPROGRESS))
1712 break;
1713 else if (unlikely(ret)) {
1714 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1715 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1716 return;
1717 }
1718
b47f407b 1719 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1720 ATH5K_WARN(sc, "unsupported jumbo\n");
1721 goto next;
1722 }
1723
b47f407b
BR		 1724 if (unlikely(rs.rs_status)) {
1725 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1726 goto next;
b47f407b 1727 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1728 /*
1729 * Decrypt error. If the error occurred
1730 * because there was no hardware key, then
1731 * let the frame through so the upper layers
1732 * can process it. This is necessary for 5210
1733 * parts which have no way to setup a ``clear''
1734 * key cache entry.
1735 *
1736 * XXX do key cache faulting
1737 */
b47f407b
BR		 1738 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1739 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1740 goto accept;
1741 }
b47f407b 1742 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1743 rxs.flag |= RX_FLAG_MMIC_ERROR;
1744 goto accept;
1745 }
1746
1747 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1748 if ((rs.rs_status &
1749 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1750 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1751 goto next;
1752 }
1753accept:
b6ea0356
BC		 1754 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1755
1756 /*
1757 * If we can't replace bf->skb with a new skb under memory
1758 * pressure, just skip this packet
1759 */
1760 if (!next_skb)
1761 goto next;
1762
fa1c114f
JS		 1763 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1764 PCI_DMA_FROMDEVICE);
b47f407b 1765 skb_put(skb, rs.rs_datalen);
fa1c114f 1766
0fe45b1d
BP		 1767 /* The MAC header is padded to have 32-bit boundary if the
1768 * packet payload is non-zero. The general calculation for
1769 * padsize would take into account odd header lengths:
1770 * padsize = (4 - hdrlen % 4) % 4; However, since only
1771 * even-length headers are used, padding can only be 0 or 2
1772 * bytes and we can optimize this a bit. In addition, we must
1773 * not try to remove padding from short control frames that do
1774 * not have payload. */
fa1c114f 1775 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1776 padsize = ath5k_pad_size(hdrlen);
1777 if (padsize) {
0fe45b1d
BP		 1778 memmove(skb->data + padsize, skb->data, hdrlen);
1779 skb_pull(skb, padsize);
fa1c114f
JS		 1780 }
1781
c0e1899b
BR		 1782 /*
1783 * always extend the mac timestamp, since this information is
1784 * also needed for proper IBSS merging.
1785 *
1786 * XXX: it might be too late to do it here, since rs_tstamp is
1787 * 15bit only. that means TSF extension has to be done within
1788 * 32768usec (about 32ms). it might be necessary to move this to
1789 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1790 *
1791 * Unfortunately we don't know when the hardware takes the rx
1792 * timestamp (beginning of phy frame, data frame, end of rx?).
1793 * The only thing we know is that it is hardware specific...
1794 * On AR5213 it seems the rx timestamp is at the end of the
1795 * frame, but i'm not sure.
1796 *
1797 * NOTE: mac80211 defines mactime at the beginning of the first
1798 * data symbol. Since we don't have any time references it's
1799 * impossible to comply to that. This affects IBSS merge only
1800 * right now, so it's not too bad...
c0e1899b 1801 */
b47f407b 1802 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1803 rxs.flag |= RX_FLAG_TSFT;
1804
d8ee398d
LR		 1805 rxs.freq = sc->curchan->center_freq;
1806 rxs.band = sc->curband->band;
fa1c114f 1807
fa1c114f 1808 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1809 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1810
1811 /* An rssi of 35 indicates you should be able use
1812 * 54 Mbps reliably. A more elaborate scheme can be used
1813 * here but it requires a map of SNR/throughput for each
1814 * possible mode used */
1815 rxs.qual = rs.rs_rssi * 100 / 35;
1816
1817 /* rssi can be more than 35 though, anything above that
1818 * should be considered at 100% */
1819 if (rxs.qual > 100)
1820 rxs.qual = 100;
fa1c114f 1821
b47f407b
BR		 1822 rxs.antenna = rs.rs_antenna;
1823 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1824 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1825
06303352
BR		 1826 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1827 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1828 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1829
fa1c114f
JS		 1830 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1831
036cd1ec 1832 /* check beacons in IBSS mode */
05c914fe 1833 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1834 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1835
fa1c114f 1836 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1837
1838 bf->skb = next_skb;
1839 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1840next:
1841 list_move_tail(&bf->list, &sc->rxbuf);
1842 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1843unlock:
fa1c114f
JS		 1844 spin_unlock(&sc->rxbuflock);
1845}
1846
1847
1848
1849
1850/*************\
1851* TX Handling *
1852\*************/
1853
1854static void
1855ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1856{
b47f407b 1857 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1858 struct ath5k_buf *bf, *bf0;
1859 struct ath5k_desc *ds;
1860 struct sk_buff *skb;
e039fa4a 1861 struct ieee80211_tx_info *info;
2f7fe870 1862 int i, ret;
fa1c114f
JS		 1863
1864 spin_lock(&txq->lock);
1865 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1866 ds = bf->desc;
1867
b47f407b 1868 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1869 if (unlikely(ret == -EINPROGRESS))
1870 break;
1871 else if (unlikely(ret)) {
1872 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1873 ret, txq->qnum);
1874 break;
1875 }
1876
1877 skb = bf->skb;
a888d52d 1878 info = IEEE80211_SKB_CB(skb);
fa1c114f 1879 bf->skb = NULL;
e039fa4a 1880
fa1c114f
JS		 1881 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1882 PCI_DMA_TODEVICE);
1883
e6a9854b 1884 ieee80211_tx_info_clear_status(info);
2f7fe870 1885 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1886 struct ieee80211_tx_rate *r =
1887 &info->status.rates[i];
2f7fe870
FF		 1888
1889 if (ts.ts_rate[i]) {
e6a9854b
JB		 1890 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1891 r->count = ts.ts_retry[i];
2f7fe870 1892 } else {
e6a9854b
JB		 1893 r->idx = -1;
1894 r->count = 0;
2f7fe870
FF		 1895 }
1896 }
1897
e6a9854b
JB		 1898 /* count the successful attempt as well */
1899 info->status.rates[ts.ts_final_idx].count++;
1900
b47f407b 1901 if (unlikely(ts.ts_status)) {
fa1c114f 1902 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1903 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1904 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1905 } else {
e039fa4a
JB		 1906 info->flags |= IEEE80211_TX_STAT_ACK;
1907 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1908 }
1909
e039fa4a 1910 ieee80211_tx_status(sc->hw, skb);
57ffc589 1911 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1912
1913 spin_lock(&sc->txbuflock);
57ffc589 1914 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1915 list_move_tail(&bf->list, &sc->txbuf);
1916 sc->txbuf_len++;
1917 spin_unlock(&sc->txbuflock);
1918 }
1919 if (likely(list_empty(&txq->q)))
1920 txq->link = NULL;
1921 spin_unlock(&txq->lock);
1922 if (sc->txbuf_len > ATH_TXBUF / 5)
1923 ieee80211_wake_queues(sc->hw);
1924}
1925
1926static void
1927ath5k_tasklet_tx(unsigned long data)
1928{
1929 struct ath5k_softc *sc = (void *)data;
1930
1931 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1932}
1933
1934
fa1c114f
JS		 1935/*****************\
1936* Beacon handling *
1937\*****************/
1938
1939/*
1940 * Setup the beacon frame for transmit.
1941 */
1942static int
e039fa4a 1943ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1944{
1945 struct sk_buff *skb = bf->skb;
a888d52d 1946 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1947 struct ath5k_hw *ah = sc->ah;
1948 struct ath5k_desc *ds;
1949 int ret, antenna = 0;
1950 u32 flags;
1951
1952 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1953 PCI_DMA_TODEVICE);
1954 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1955 "skbaddr %llx\n", skb, skb->data, skb->len,
1956 (unsigned long long)bf->skbaddr);
8d8bb39b 1957 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1958 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1959 return -EIO;
1960 }
1961
1962 ds = bf->desc;
1963
1964 flags = AR5K_TXDESC_NOACK;
05c914fe 1965 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1966 ds->ds_link = bf->daddr; /* self-linked */
1967 flags |= AR5K_TXDESC_VEOL;
1968 /*
1969 * Let hardware handle antenna switching if txantenna is not set
1970 */
1971 } else {
1972 ds->ds_link = 0;
1973 /*
1974 * Switch antenna every 4 beacons if txantenna is not set
1975 * XXX assumes two antennas
1976 */
1977 if (antenna == 0)
1978 antenna = sc->bsent & 4 ? 2 : 1;
1979 }
1980
1981 ds->ds_data = bf->skbaddr;
281c56dd 1982 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1983 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1984 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1985 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1986 1, AR5K_TXKEYIX_INVALID,
400ec45a 1987 antenna, flags, 0, 0);
fa1c114f
JS		 1988 if (ret)
1989 goto err_unmap;
1990
1991 return 0;
1992err_unmap:
1993 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1994 return ret;
1995}
1996
1997/*
1998 * Transmit a beacon frame at SWBA. Dynamic updates to the
1999 * frame contents are done as needed and the slot time is
2000 * also adjusted based on current state.
2001 *
2002 * this is usually called from interrupt context (ath5k_intr())
2003 * but also from ath5k_beacon_config() in IBSS mode which in turn
2004 * can be called from a tasklet and user context
2005 */
2006static void
2007ath5k_beacon_send(struct ath5k_softc *sc)
2008{
2009 struct ath5k_buf *bf = sc->bbuf;
2010 struct ath5k_hw *ah = sc->ah;
2011
be9b7259 2012 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2013
05c914fe
JB		 2014 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2015 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2016 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2017 return;
2018 }
2019 /*
2020 * Check if the previous beacon has gone out. If
2021 * not don't don't try to post another, skip this
2022 * period and wait for the next. Missed beacons
2023 * indicate a problem and should not occur. If we
2024 * miss too many consecutive beacons reset the device.
2025 */
2026 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2027 sc->bmisscount++;
be9b7259 2028 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2029 "missed %u consecutive beacons\n", sc->bmisscount);
2030 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2031 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2032 "stuck beacon time (%u missed)\n",
2033 sc->bmisscount);
2034 tasklet_schedule(&sc->restq);
2035 }
2036 return;
2037 }
2038 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2039 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2040 "resume beacon xmit after %u misses\n",
2041 sc->bmisscount);
2042 sc->bmisscount = 0;
2043 }
2044
2045 /*
2046 * Stop any current dma and put the new frame on the queue.
2047 * This should never fail since we check above that no frames
2048 * are still pending on the queue.
2049 */
2050 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2051 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2052 /* NB: hw still stops DMA, so proceed */
2053 }
fa1c114f 2054
c6e387a2
NK		 2055 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2056 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2057 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2058 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2059
2060 sc->bsent++;
2061}
2062
2063
9804b98d
BR		 2064/**
2065 * ath5k_beacon_update_timers - update beacon timers
2066 *
2067 * @sc: struct ath5k_softc pointer we are operating on
2068 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2069 * beacon timer update based on the current HW TSF.
2070 *
2071 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2072 * of a received beacon or the current local hardware TSF and write it to the
2073 * beacon timer registers.
2074 *
2075 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2076 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2077 * when we otherwise know we have to update the timers, but we keep it in this
2078 * function to have it all together in one place.
2079 */
fa1c114f 2080static void
9804b98d 2081ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2082{
2083 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2084 u32 nexttbtt, intval, hw_tu, bc_tu;
2085 u64 hw_tsf;
fa1c114f
JS		 2086
2087 intval = sc->bintval & AR5K_BEACON_PERIOD;
2088 if (WARN_ON(!intval))
2089 return;
2090
9804b98d
BR		 2091 /* beacon TSF converted to TU */
2092 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2093
9804b98d
BR		 2094 /* current TSF converted to TU */
2095 hw_tsf = ath5k_hw_get_tsf64(ah);
2096 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2097
9804b98d
BR		 2098#define FUDGE 3
2099 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2100 if (bc_tsf == -1) {
2101 /*
2102 * no beacons received, called internally.
2103 * just need to refresh timers based on HW TSF.
2104 */
2105 nexttbtt = roundup(hw_tu + FUDGE, intval);
2106 } else if (bc_tsf == 0) {
2107 /*
2108 * no beacon received, probably called by ath5k_reset_tsf().
2109 * reset TSF to start with 0.
2110 */
2111 nexttbtt = intval;
2112 intval |= AR5K_BEACON_RESET_TSF;
2113 } else if (bc_tsf > hw_tsf) {
2114 /*
2115 * beacon received, SW merge happend but HW TSF not yet updated.
2116 * not possible to reconfigure timers yet, but next time we
2117 * receive a beacon with the same BSSID, the hardware will
2118 * automatically update the TSF and then we need to reconfigure
2119 * the timers.
2120 */
2121 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2122 "need to wait for HW TSF sync\n");
2123 return;
2124 } else {
2125 /*
2126 * most important case for beacon synchronization between STA.
2127 *
2128 * beacon received and HW TSF has been already updated by HW.
2129 * update next TBTT based on the TSF of the beacon, but make
2130 * sure it is ahead of our local TSF timer.
2131 */
2132 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2133 }
2134#undef FUDGE
fa1c114f 2135
036cd1ec
BR		 2136 sc->nexttbtt = nexttbtt;
2137
fa1c114f 2138 intval |= AR5K_BEACON_ENA;
fa1c114f 2139 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2140
2141 /*
2142 * debugging output last in order to preserve the time critical aspect
2143 * of this function
2144 */
2145 if (bc_tsf == -1)
2146 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2147 "reconfigured timers based on HW TSF\n");
2148 else if (bc_tsf == 0)
2149 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2150 "reset HW TSF and timers\n");
2151 else
2152 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2153 "updated timers based on beacon TSF\n");
2154
2155 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2156 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2157 (unsigned long long) bc_tsf,
2158 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2159 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2160 intval & AR5K_BEACON_PERIOD,
2161 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2162 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2163}
2164
2165
036cd1ec
BR		 2166/**
2167 * ath5k_beacon_config - Configure the beacon queues and interrupts
2168 *
2169 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2170 *
2171 * When operating in station mode we want to receive a BMISS interrupt when we
2172 * stop seeing beacons from the AP we've associated with so we can look for
2173 * another AP to associate with.
2174 *
036cd1ec 2175 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2176 * interrupts to detect TSF updates only.
fa1c114f
JS		 2177 */
2178static void
2179ath5k_beacon_config(struct ath5k_softc *sc)
2180{
2181 struct ath5k_hw *ah = sc->ah;
2182
c6e387a2 2183 ath5k_hw_set_imr(ah, 0);
fa1c114f 2184 sc->bmisscount = 0;
dc1968e7 2185 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2186
05c914fe 2187 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2188 sc->imask |= AR5K_INT_BMISS;
da966bca 2189 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2190 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2191 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2192 /*
036cd1ec
BR		 2193 * In IBSS mode we use a self-linked tx descriptor and let the
2194 * hardware send the beacons automatically. We have to load it
fa1c114f 2195 * only once here.
036cd1ec 2196 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2197 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2198 */
2199 ath5k_beaconq_config(sc);
fa1c114f 2200
036cd1ec
BR		 2201 sc->imask |= AR5K_INT_SWBA;
2202
da966bca
JS		 2203 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2204 if (ath5k_hw_hasveol(ah)) {
2205 spin_lock(&sc->block);
2206 ath5k_beacon_send(sc);
2207 spin_unlock(&sc->block);
2208 }
2209 } else
2210 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2211 }
fa1c114f 2212
c6e387a2 2213 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2214}
2215
2216
2217/********************\
2218* Interrupt handling *
2219\********************/
2220
2221static int
bb2becac 2222ath5k_init(struct ath5k_softc *sc)
fa1c114f 2223{
bc1b32d6
EO		 2224 struct ath5k_hw *ah = sc->ah;
2225 int ret, i;
fa1c114f
JS		 2226
2227 mutex_lock(&sc->lock);
2228
2229 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2230
2231 /*
2232 * Stop anything previously setup. This is safe
2233 * no matter this is the first time through or not.
2234 */
2235 ath5k_stop_locked(sc);
2236
2237 /*
2238 * The basic interface to setting the hardware in a good
2239 * state is ``reset''. On return the hardware is known to
2240 * be powered up and with interrupts disabled. This must
2241 * be followed by initialization of the appropriate bits
2242 * and then setup of the interrupt mask.
2243 */
d8ee398d
LR		 2244 sc->curchan = sc->hw->conf.channel;
2245 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2246 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2247 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2248 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
d7dc1003
JS		 2249 ret = ath5k_reset(sc, false, false);
2250 if (ret)
2251 goto done;
fa1c114f 2252
bc1b32d6
EO		 2253 /*
2254 * Reset the key cache since some parts do not reset the
2255 * contents on initial power up or resume from suspend.
2256 */
2257 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2258 ath5k_hw_reset_key(ah, i);
2259
fa1c114f 2260 /* Set ack to be sent at low bit-rates */
bc1b32d6 2261 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2262
2263 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2264 msecs_to_jiffies(ath5k_calinterval * 1000)));
2265
2266 ret = 0;
2267done:
274c7c36 2268 mmiowb();
fa1c114f
JS		 2269 mutex_unlock(&sc->lock);
2270 return ret;
2271}
2272
2273static int
2274ath5k_stop_locked(struct ath5k_softc *sc)
2275{
2276 struct ath5k_hw *ah = sc->ah;
2277
2278 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2279 test_bit(ATH_STAT_INVALID, sc->status));
2280
2281 /*
2282 * Shutdown the hardware and driver:
2283 * stop output from above
2284 * disable interrupts
2285 * turn off timers
2286 * turn off the radio
2287 * clear transmit machinery
2288 * clear receive machinery
2289 * drain and release tx queues
2290 * reclaim beacon resources
2291 * power down hardware
2292 *
2293 * Note that some of this work is not possible if the
2294 * hardware is gone (invalid).
2295 */
2296 ieee80211_stop_queues(sc->hw);
2297
2298 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2299 ath5k_led_off(sc);
c6e387a2 2300 ath5k_hw_set_imr(ah, 0);
274c7c36 2301 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2302 }
2303 ath5k_txq_cleanup(sc);
2304 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2305 ath5k_rx_stop(sc);
2306 ath5k_hw_phy_disable(ah);
2307 } else
2308 sc->rxlink = NULL;
2309
2310 return 0;
2311}
2312
2313/*
2314 * Stop the device, grabbing the top-level lock to protect
2315 * against concurrent entry through ath5k_init (which can happen
2316 * if another thread does a system call and the thread doing the
2317 * stop is preempted).
2318 */
2319static int
bb2becac 2320ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2321{
2322 int ret;
2323
2324 mutex_lock(&sc->lock);
2325 ret = ath5k_stop_locked(sc);
2326 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2327 /*
2328 * Set the chip in full sleep mode. Note that we are
2329 * careful to do this only when bringing the interface
2330 * completely to a stop. When the chip is in this state
2331 * it must be carefully woken up or references to
2332 * registers in the PCI clock domain may freeze the bus
2333 * (and system). This varies by chip and is mostly an
2334 * issue with newer parts that go to sleep more quickly.
2335 */
2336 if (sc->ah->ah_mac_srev >= 0x78) {
2337 /*
2338 * XXX
2339 * don't put newer MAC revisions > 7.8 to sleep because
2340 * of the above mentioned problems
2341 */
2342 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2343 "not putting device to sleep\n");
2344 } else {
2345 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2346 "putting device to full sleep\n");
2347 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2348 }
2349 }
2350 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2351
274c7c36 2352 mmiowb();
fa1c114f
JS		 2353 mutex_unlock(&sc->lock);
2354
2355 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2356 tasklet_kill(&sc->rxtq);
2357 tasklet_kill(&sc->txtq);
2358 tasklet_kill(&sc->restq);
fa1c114f
JS		 2359
2360 return ret;
2361}
2362
2363static irqreturn_t
2364ath5k_intr(int irq, void *dev_id)
2365{
2366 struct ath5k_softc *sc = dev_id;
2367 struct ath5k_hw *ah = sc->ah;
2368 enum ath5k_int status;
2369 unsigned int counter = 1000;
2370
2371 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2372 !ath5k_hw_is_intr_pending(ah)))
2373 return IRQ_NONE;
2374
2375 do {
2376 /*
2377 * Figure out the reason(s) for the interrupt. Note
2378 * that get_isr returns a pseudo-ISR that may include
2379 * bits we haven't explicitly enabled so we mask the
2380 * value to insure we only process bits we requested.
2381 */
2382 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2383 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2384 status, sc->imask);
2385 status &= sc->imask; /* discard unasked for bits */
2386 if (unlikely(status & AR5K_INT_FATAL)) {
2387 /*
2388 * Fatal errors are unrecoverable.
2389 * Typically these are caused by DMA errors.
2390 */
2391 tasklet_schedule(&sc->restq);
2392 } else if (unlikely(status & AR5K_INT_RXORN)) {
2393 tasklet_schedule(&sc->restq);
2394 } else {
2395 if (status & AR5K_INT_SWBA) {
2396 /*
2397 * Software beacon alert--time to send a beacon.
2398 * Handle beacon transmission directly; deferring
2399 * this is too slow to meet timing constraints
2400 * under load.
036cd1ec
BR		 2401 *
2402 * In IBSS mode we use this interrupt just to
2403 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2404 * transmission time) in order to detect wether
2405 * automatic TSF updates happened.
fa1c114f 2406 */
05c914fe 2407 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2408 /* XXX: only if VEOL suppported */
2409 u64 tsf = ath5k_hw_get_tsf64(ah);
2410 sc->nexttbtt += sc->bintval;
2411 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2412 "SWBA nexttbtt: %x hw_tu: %x "
2413 "TSF: %llx\n",
2414 sc->nexttbtt,
2415 TSF_TO_TU(tsf),
2416 (unsigned long long) tsf);
036cd1ec 2417 } else {
00482973 2418 spin_lock(&sc->block);
036cd1ec 2419 ath5k_beacon_send(sc);
00482973 2420 spin_unlock(&sc->block);
036cd1ec 2421 }
fa1c114f
JS		 2422 }
2423 if (status & AR5K_INT_RXEOL) {
2424 /*
2425 * NB: the hardware should re-read the link when
2426 * RXE bit is written, but it doesn't work at
2427 * least on older hardware revs.
2428 */
2429 sc->rxlink = NULL;
2430 }
2431 if (status & AR5K_INT_TXURN) {
2432 /* bump tx trigger level */
2433 ath5k_hw_update_tx_triglevel(ah, true);
2434 }
4c674c60 2435 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2436 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2437 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2438 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2439 tasklet_schedule(&sc->txtq);
2440 if (status & AR5K_INT_BMISS) {
2441 }
2442 if (status & AR5K_INT_MIB) {
194828a2
NK		 2443 /*
2444 * These stats are also used for ANI i think
2445 * so how about updating them more often ?
2446 */
2447 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2448 }
2449 }
2450 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2451
2452 if (unlikely(!counter))
2453 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2454
2455 return IRQ_HANDLED;
2456}
2457
2458static void
2459ath5k_tasklet_reset(unsigned long data)
2460{
2461 struct ath5k_softc *sc = (void *)data;
2462
d7dc1003 2463 ath5k_reset_wake(sc);
fa1c114f
JS		 2464}
2465
2466/*
2467 * Periodically recalibrate the PHY to account
2468 * for temperature/environment changes.
2469 */
2470static void
2471ath5k_calibrate(unsigned long data)
2472{
2473 struct ath5k_softc *sc = (void *)data;
2474 struct ath5k_hw *ah = sc->ah;
2475
2476 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2477 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2478 sc->curchan->hw_value);
fa1c114f
JS		 2479
2480 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2481 /*
2482 * Rfgain is out of bounds, reset the chip
2483 * to load new gain values.
2484 */
2485 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2486 ath5k_reset_wake(sc);
fa1c114f
JS		 2487 }
2488 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2489 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2490 ieee80211_frequency_to_channel(
2491 sc->curchan->center_freq));
fa1c114f
JS		 2492
2493 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2494 msecs_to_jiffies(ath5k_calinterval * 1000)));
2495}
2496
2497
2498
2499/***************\
2500* LED functions *
2501\***************/
2502
2503static void
3a078876 2504ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2505{
3a078876
BC		 2506 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2507 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2508 ath5k_led_off(sc);
fa1c114f
JS		 2509 }
2510}
2511
fa1c114f 2512static void
3a078876 2513ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2514{
3a078876
BC		 2515 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2516 return;
fa1c114f 2517 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2518}
2519
2520static void
3a078876 2521ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2522{
3a078876 2523 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2524 return;
3a078876
BC		 2525 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2526}
2527
2528static void
2529ath5k_led_brightness_set(struct led_classdev *led_dev,
2530 enum led_brightness brightness)
2531{
2532 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2533 led_dev);
2534
2535 if (brightness == LED_OFF)
2536 ath5k_led_off(led->sc);
2537 else
2538 ath5k_led_on(led->sc);
2539}
2540
2541static int
2542ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2543 const char *name, char *trigger)
2544{
2545 int err;
2546
2547 led->sc = sc;
2548 strncpy(led->name, name, sizeof(led->name));
2549 led->led_dev.name = led->name;
2550 led->led_dev.default_trigger = trigger;
2551 led->led_dev.brightness_set = ath5k_led_brightness_set;
2552
2553 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2554 if (err) {
3a078876
BC		 2555 ATH5K_WARN(sc, "could not register LED %s\n", name);
2556 led->sc = NULL;
fa1c114f 2557 }
3a078876 2558 return err;
fa1c114f
JS		 2559}
2560
3a078876
BC		 2561static void
2562ath5k_unregister_led(struct ath5k_led *led)
2563{
2564 if (!led->sc)
2565 return;
2566 led_classdev_unregister(&led->led_dev);
2567 ath5k_led_off(led->sc);
2568 led->sc = NULL;
2569}
2570
2571static void
2572ath5k_unregister_leds(struct ath5k_softc *sc)
2573{
2574 ath5k_unregister_led(&sc->rx_led);
2575 ath5k_unregister_led(&sc->tx_led);
2576}
2577
2578
2579static int
2580ath5k_init_leds(struct ath5k_softc *sc)
2581{
2582 int ret = 0;
2583 struct ieee80211_hw *hw = sc->hw;
2584 struct pci_dev *pdev = sc->pdev;
2585 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2586
3a078876
BC		 2587 /*
2588 * Auto-enable soft led processing for IBM cards and for
2589 * 5211 minipci cards.
2590 */
2591 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2592 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2593 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2594 sc->led_pin = 0;
734b5aa9 2595 sc->led_on = 0; /* active low */
3a078876
BC		 2596 }
2597 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2598 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2599 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2600 sc->led_pin = 1;
734b5aa9 2601 sc->led_on = 1; /* active high */
3a078876 2602 }
63649b6c
BC		 2603 /* Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) */
2604 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN) {
2605 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2606 sc->led_pin = 3;
2607 sc->led_on = 0; /* active low */
2608 }
2609
3a078876
BC		 2610 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2611 goto out;
2612
2613 ath5k_led_enable(sc);
2614
2615 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2616 ret = ath5k_register_led(sc, &sc->rx_led, name,
2617 ieee80211_get_rx_led_name(hw));
2618 if (ret)
2619 goto out;
2620
2621 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2622 ret = ath5k_register_led(sc, &sc->tx_led, name,
2623 ieee80211_get_tx_led_name(hw));
2624out:
2625 return ret;
2626}
fa1c114f
JS		 2627
2628
2629/********************\
2630* Mac80211 functions *
2631\********************/
2632
2633static int
e039fa4a 2634ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2635{
2636 struct ath5k_softc *sc = hw->priv;
2637 struct ath5k_buf *bf;
2638 unsigned long flags;
2639 int hdrlen;
0fe45b1d 2640 int padsize;
fa1c114f
JS		 2641
2642 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2643
05c914fe 2644 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2645 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2646
2647 /*
2648 * the hardware expects the header padded to 4 byte boundaries
2649 * if this is not the case we add the padding after the header
2650 */
2651 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2652 padsize = ath5k_pad_size(hdrlen);
2653 if (padsize) {
0fe45b1d
BP		 2654
2655 if (skb_headroom(skb) < padsize) {
fa1c114f 2656 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2657 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2658 return NETDEV_TX_BUSY;
fa1c114f 2659 }
0fe45b1d
BP		 2660 skb_push(skb, padsize);
2661 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2662 }
2663
fa1c114f
JS		 2664 spin_lock_irqsave(&sc->txbuflock, flags);
2665 if (list_empty(&sc->txbuf)) {
2666 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2667 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2668 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2669 return NETDEV_TX_BUSY;
fa1c114f
JS		 2670 }
2671 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2672 list_del(&bf->list);
2673 sc->txbuf_len--;
2674 if (list_empty(&sc->txbuf))
2675 ieee80211_stop_queues(hw);
2676 spin_unlock_irqrestore(&sc->txbuflock, flags);
2677
2678 bf->skb = skb;
2679
e039fa4a 2680 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2681 bf->skb = NULL;
2682 spin_lock_irqsave(&sc->txbuflock, flags);
2683 list_add_tail(&bf->list, &sc->txbuf);
2684 sc->txbuf_len++;
2685 spin_unlock_irqrestore(&sc->txbuflock, flags);
2686 dev_kfree_skb_any(skb);
71ef99c8 2687 return NETDEV_TX_OK;
fa1c114f
JS		 2688 }
2689
71ef99c8 2690 return NETDEV_TX_OK;
fa1c114f
JS		 2691}
2692
2693static int
d7dc1003 2694ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2695{
fa1c114f
JS		 2696 struct ath5k_hw *ah = sc->ah;
2697 int ret;
2698
2699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2700
d7dc1003 2701 if (stop) {
c6e387a2 2702 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2703 ath5k_txq_cleanup(sc);
2704 ath5k_rx_stop(sc);
2705 }
fa1c114f 2706 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2707 if (ret) {
fa1c114f
JS		 2708 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2709 goto err;
2710 }
d7dc1003
JS		 2711
2712 /*
2713 * This is needed only to setup initial state
2714 * but it's best done after a reset.
2715 */
fa1c114f
JS		 2716 ath5k_hw_set_txpower_limit(sc->ah, 0);
2717
2718 ret = ath5k_rx_start(sc);
d7dc1003 2719 if (ret) {
fa1c114f
JS		 2720 ATH5K_ERR(sc, "can't start recv logic\n");
2721 goto err;
2722 }
d7dc1003 2723
fa1c114f 2724 /*
d7dc1003
JS		 2725 * Change channels and update the h/w rate map if we're switching;
2726 * e.g. 11a to 11b/g.
2727 *
2728 * We may be doing a reset in response to an ioctl that changes the
2729 * channel so update any state that might change as a result.
fa1c114f
JS		 2730 *
2731 * XXX needed?
2732 */
2733/* ath5k_chan_change(sc, c); */
fa1c114f 2734
d7dc1003
JS		 2735 ath5k_beacon_config(sc);
2736 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2737
2738 return 0;
2739err:
2740 return ret;
2741}
2742
d7dc1003
JS		 2743static int
2744ath5k_reset_wake(struct ath5k_softc *sc)
2745{
2746 int ret;
2747
2748 ret = ath5k_reset(sc, true, true);
2749 if (!ret)
2750 ieee80211_wake_queues(sc->hw);
2751
2752 return ret;
2753}
2754
fa1c114f
JS		 2755static int ath5k_start(struct ieee80211_hw *hw)
2756{
bb2becac 2757 return ath5k_init(hw->priv);
fa1c114f
JS		 2758}
2759
2760static void ath5k_stop(struct ieee80211_hw *hw)
2761{
bb2becac 2762 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2763}
2764
2765static int ath5k_add_interface(struct ieee80211_hw *hw,
2766 struct ieee80211_if_init_conf *conf)
2767{
2768 struct ath5k_softc *sc = hw->priv;
2769 int ret;
2770
2771 mutex_lock(&sc->lock);
32bfd35d 2772 if (sc->vif) {
fa1c114f
JS		 2773 ret = 0;
2774 goto end;
2775 }
2776
32bfd35d 2777 sc->vif = conf->vif;
fa1c114f
JS		 2778
2779 switch (conf->type) {
da966bca 2780 case NL80211_IFTYPE_AP:
05c914fe
JB		 2781 case NL80211_IFTYPE_STATION:
2782 case NL80211_IFTYPE_ADHOC:
b706e65b 2783 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2784 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2785 sc->opmode = conf->type;
2786 break;
2787 default:
2788 ret = -EOPNOTSUPP;
2789 goto end;
2790 }
67d2e2df
JS		 2791
2792 /* Set to a reasonable value. Note that this will
2793 * be set to mac80211's value at ath5k_config(). */
2794 sc->bintval = 1000;
0e149cf5 2795 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2796
fa1c114f
JS		 2797 ret = 0;
2798end:
2799 mutex_unlock(&sc->lock);
2800 return ret;
2801}
2802
2803static void
2804ath5k_remove_interface(struct ieee80211_hw *hw,
2805 struct ieee80211_if_init_conf *conf)
2806{
2807 struct ath5k_softc *sc = hw->priv;
0e149cf5 2808 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2809
2810 mutex_lock(&sc->lock);
32bfd35d 2811 if (sc->vif != conf->vif)
fa1c114f
JS		 2812 goto end;
2813
0e149cf5 2814 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2815 sc->vif = NULL;
fa1c114f
JS		 2816end:
2817 mutex_unlock(&sc->lock);
2818}
2819
d8ee398d
LR		 2820/*
2821 * TODO: Phy disable/diversity etc
2822 */
fa1c114f 2823static int
e8975581 2824ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2825{
2826 struct ath5k_softc *sc = hw->priv;
e8975581 2827 struct ieee80211_conf *conf = &hw->conf;
fa1c114f 2828
e535c1ac 2829 sc->bintval = conf->beacon_int;
d8ee398d 2830 sc->power_level = conf->power_level;
fa1c114f 2831
d8ee398d 2832 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2833}
2834
2835static int
32bfd35d 2836ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2837 struct ieee80211_if_conf *conf)
2838{
2839 struct ath5k_softc *sc = hw->priv;
2840 struct ath5k_hw *ah = sc->ah;
2841 int ret;
2842
fa1c114f 2843 mutex_lock(&sc->lock);
32bfd35d 2844 if (sc->vif != vif) {
fa1c114f
JS		 2845 ret = -EIO;
2846 goto unlock;
2847 }
da966bca 2848 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2849 /* Cache for later use during resets */
2850 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2851 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2852 * a clean way of letting us retrieve this yet. */
2853 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2854 mmiowb();
fa1c114f 2855 }
9d139c81 2856 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2857 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2858 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2859 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2860 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2861 if (!beacon) {
2862 ret = -ENOMEM;
2863 goto unlock;
2864 }
da966bca 2865 ath5k_beacon_update(sc, beacon);
9d139c81 2866 }
fa1c114f
JS		 2867 mutex_unlock(&sc->lock);
2868
d7dc1003 2869 return ath5k_reset_wake(sc);
fa1c114f
JS		 2870unlock:
2871 mutex_unlock(&sc->lock);
2872 return ret;
2873}
2874
2875#define SUPPORTED_FIF_FLAGS \
2876 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2877 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2878 FIF_BCN_PRBRESP_PROMISC
2879/*
2880 * o always accept unicast, broadcast, and multicast traffic
2881 * o multicast traffic for all BSSIDs will be enabled if mac80211
2882 * says it should be
2883 * o maintain current state of phy ofdm or phy cck error reception.
2884 * If the hardware detects any of these type of errors then
2885 * ath5k_hw_get_rx_filter() will pass to us the respective
2886 * hardware filters to be able to receive these type of frames.
2887 * o probe request frames are accepted only when operating in
2888 * hostap, adhoc, or monitor modes
2889 * o enable promiscuous mode according to the interface state
2890 * o accept beacons:
2891 * - when operating in adhoc mode so the 802.11 layer creates
2892 * node table entries for peers,
2893 * - when operating in station mode for collecting rssi data when
2894 * the station is otherwise quiet, or
2895 * - when scanning
2896 */
2897static void ath5k_configure_filter(struct ieee80211_hw *hw,
2898 unsigned int changed_flags,
2899 unsigned int *new_flags,
2900 int mc_count, struct dev_mc_list *mclist)
2901{
2902 struct ath5k_softc *sc = hw->priv;
2903 struct ath5k_hw *ah = sc->ah;
2904 u32 mfilt[2], val, rfilt;
2905 u8 pos;
2906 int i;
2907
2908 mfilt[0] = 0;
2909 mfilt[1] = 0;
2910
2911 /* Only deal with supported flags */
2912 changed_flags &= SUPPORTED_FIF_FLAGS;
2913 *new_flags &= SUPPORTED_FIF_FLAGS;
2914
2915 /* If HW detects any phy or radar errors, leave those filters on.
2916 * Also, always enable Unicast, Broadcasts and Multicast
2917 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2918 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2919 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2920 AR5K_RX_FILTER_MCAST);
2921
2922 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2923 if (*new_flags & FIF_PROMISC_IN_BSS) {
2924 rfilt |= AR5K_RX_FILTER_PROM;
2925 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2926 } else {
fa1c114f 2927 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2928 }
fa1c114f
JS		 2929 }
2930
2931 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2932 if (*new_flags & FIF_ALLMULTI) {
2933 mfilt[0] = ~0;
2934 mfilt[1] = ~0;
2935 } else {
2936 for (i = 0; i < mc_count; i++) {
2937 if (!mclist)
2938 break;
2939 /* calculate XOR of eight 6-bit values */
533dd1b0 2940 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2941 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2942 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2943 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2944 pos &= 0x3f;
2945 mfilt[pos / 32] |= (1 << (pos % 32));
2946 /* XXX: we might be able to just do this instead,
2947 * but not sure, needs testing, if we do use this we'd
2948 * neet to inform below to not reset the mcast */
2949 /* ath5k_hw_set_mcast_filterindex(ah,
2950 * mclist->dmi_addr[5]); */
2951 mclist = mclist->next;
2952 }
2953 }
2954
2955 /* This is the best we can do */
2956 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2957 rfilt |= AR5K_RX_FILTER_PHYERR;
2958
2959 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2960 * and probes for any BSSID, this needs testing */
2961 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2962 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2963
2964 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2965 * set we should only pass on control frames for this
2966 * station. This needs testing. I believe right now this
2967 * enables *all* control frames, which is OK.. but
2968 * but we should see if we can improve on granularity */
2969 if (*new_flags & FIF_CONTROL)
2970 rfilt |= AR5K_RX_FILTER_CONTROL;
2971
2972 /* Additional settings per mode -- this is per ath5k */
2973
2974 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2975
05c914fe 2976 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2977 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2978 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2979 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2980 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2981 if (sc->opmode != NL80211_IFTYPE_AP &&
2982 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2983 test_bit(ATH_STAT_PROMISC, sc->status))
2984 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2985 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2986 sc->opmode == NL80211_IFTYPE_ADHOC ||
2987 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2988 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2989 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2990 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2991 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2992
2993 /* Set filters */
0bbac08f 2994 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2995
2996 /* Set multicast bits */
2997 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2998 /* Set the cached hw filter flags, this will alter actually
2999 * be set in HW */
3000 sc->filter_flags = rfilt;
3001}
3002
3003static int
3004ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3005 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3006 struct ieee80211_key_conf *key)
fa1c114f
JS		 3007{
3008 struct ath5k_softc *sc = hw->priv;
3009 int ret = 0;
3010
9ad9a26e
BC		 3011 if (modparam_nohwcrypt)
3012 return -EOPNOTSUPP;
3013
0bbac08f 3014 switch (key->alg) {
fa1c114f 3015 case ALG_WEP:
fa1c114f 3016 case ALG_TKIP:
3f64b435 3017 break;
fa1c114f
JS		 3018 case ALG_CCMP:
3019 return -EOPNOTSUPP;
3020 default:
3021 WARN_ON(1);
3022 return -EINVAL;
3023 }
3024
3025 mutex_lock(&sc->lock);
3026
3027 switch (cmd) {
3028 case SET_KEY:
dc822b5d
JB		 3029 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3030 sta ? sta->addr : NULL);
fa1c114f
JS		 3031 if (ret) {
3032 ATH5K_ERR(sc, "can't set the key\n");
3033 goto unlock;
3034 }
3035 __set_bit(key->keyidx, sc->keymap);
3036 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3037 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3038 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3039 break;
3040 case DISABLE_KEY:
3041 ath5k_hw_reset_key(sc->ah, key->keyidx);
3042 __clear_bit(key->keyidx, sc->keymap);
3043 break;
3044 default:
3045 ret = -EINVAL;
3046 goto unlock;
3047 }
3048
3049unlock:
274c7c36 3050 mmiowb();
fa1c114f
JS		 3051 mutex_unlock(&sc->lock);
3052 return ret;
3053}
3054
3055static int
3056ath5k_get_stats(struct ieee80211_hw *hw,
3057 struct ieee80211_low_level_stats *stats)
3058{
3059 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3060 struct ath5k_hw *ah = sc->ah;
3061
3062 /* Force update */
3063 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3064
3065 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3066
3067 return 0;
3068}
3069
3070static int
3071ath5k_get_tx_stats(struct ieee80211_hw *hw,
3072 struct ieee80211_tx_queue_stats *stats)
3073{
3074 struct ath5k_softc *sc = hw->priv;
3075
3076 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3077
3078 return 0;
3079}
3080
3081static u64
3082ath5k_get_tsf(struct ieee80211_hw *hw)
3083{
3084 struct ath5k_softc *sc = hw->priv;
3085
3086 return ath5k_hw_get_tsf64(sc->ah);
3087}
3088
3089static void
3090ath5k_reset_tsf(struct ieee80211_hw *hw)
3091{
3092 struct ath5k_softc *sc = hw->priv;
3093
9804b98d
BR		 3094 /*
3095 * in IBSS mode we need to update the beacon timers too.
3096 * this will also reset the TSF if we call it with 0
3097 */
05c914fe 3098 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3099 ath5k_beacon_update_timers(sc, 0);
3100 else
3101 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3102}
3103
3104static int
da966bca 3105ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3106{
00482973 3107 unsigned long flags;
fa1c114f
JS		 3108 int ret;
3109
3110 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3111
00482973 3112 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3113 ath5k_txbuf_free(sc, sc->bbuf);
3114 sc->bbuf->skb = skb;
e039fa4a 3115 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3116 if (ret)
3117 sc->bbuf->skb = NULL;
00482973
JS		 3118 spin_unlock_irqrestore(&sc->block, flags);
3119 if (!ret) {
fa1c114f 3120 ath5k_beacon_config(sc);
274c7c36
JS		 3121 mmiowb();
3122 }
fa1c114f 3123
fa1c114f
JS		 3124 return ret;
3125}
02969b38
MX		 3126static void
3127set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3128{
3129 struct ath5k_softc *sc = hw->priv;
3130 struct ath5k_hw *ah = sc->ah;
3131 u32 rfilt;
3132 rfilt = ath5k_hw_get_rx_filter(ah);
3133 if (enable)
3134 rfilt |= AR5K_RX_FILTER_BEACON;
3135 else
3136 rfilt &= ~AR5K_RX_FILTER_BEACON;
3137 ath5k_hw_set_rx_filter(ah, rfilt);
3138 sc->filter_flags = rfilt;
3139}
fa1c114f 3140
02969b38
MX		 3141static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3142 struct ieee80211_vif *vif,
3143 struct ieee80211_bss_conf *bss_conf,
3144 u32 changes)
3145{
3146 struct ath5k_softc *sc = hw->priv;
3147 if (changes & BSS_CHANGED_ASSOC) {
3148 mutex_lock(&sc->lock);
3149 sc->assoc = bss_conf->assoc;
3150 if (sc->opmode == NL80211_IFTYPE_STATION)
3151 set_beacon_filter(hw, sc->assoc);
3152 mutex_unlock(&sc->lock);
3153 }
3154}
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