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iwlwifi: use le16 frame control directly, use QOS symbolic constant mask
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
133};
134
63266a65
BR		 135static struct ieee80211_rate ath5k_rates[] = {
136 { .bitrate = 10,
137 .hw_value = ATH5K_RATE_CODE_1M, },
138 { .bitrate = 20,
139 .hw_value = ATH5K_RATE_CODE_2M,
140 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
141 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
142 { .bitrate = 55,
143 .hw_value = ATH5K_RATE_CODE_5_5M,
144 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
145 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
146 { .bitrate = 110,
147 .hw_value = ATH5K_RATE_CODE_11M,
148 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 60,
151 .hw_value = ATH5K_RATE_CODE_6M,
152 .flags = 0 },
153 { .bitrate = 90,
154 .hw_value = ATH5K_RATE_CODE_9M,
155 .flags = 0 },
156 { .bitrate = 120,
157 .hw_value = ATH5K_RATE_CODE_12M,
158 .flags = 0 },
159 { .bitrate = 180,
160 .hw_value = ATH5K_RATE_CODE_18M,
161 .flags = 0 },
162 { .bitrate = 240,
163 .hw_value = ATH5K_RATE_CODE_24M,
164 .flags = 0 },
165 { .bitrate = 360,
166 .hw_value = ATH5K_RATE_CODE_36M,
167 .flags = 0 },
168 { .bitrate = 480,
169 .hw_value = ATH5K_RATE_CODE_48M,
170 .flags = 0 },
171 { .bitrate = 540,
172 .hw_value = ATH5K_RATE_CODE_54M,
173 .flags = 0 },
174 /* XR missing */
175};
176
fa1c114f
JS		 177/*
178 * Prototypes - PCI stack related functions
179 */
180static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
181 const struct pci_device_id *id);
182static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
183#ifdef CONFIG_PM
184static int ath5k_pci_suspend(struct pci_dev *pdev,
185 pm_message_t state);
186static int ath5k_pci_resume(struct pci_dev *pdev);
187#else
188#define ath5k_pci_suspend NULL
189#define ath5k_pci_resume NULL
190#endif /* CONFIG_PM */
191
04a9e451 192static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 193 .name = "ath5k_pci",
194 .id_table = ath5k_pci_id_table,
195 .probe = ath5k_pci_probe,
196 .remove = __devexit_p(ath5k_pci_remove),
197 .suspend = ath5k_pci_suspend,
198 .resume = ath5k_pci_resume,
199};
200
201
202
203/*
204 * Prototypes - MAC 802.11 stack related functions
205 */
e039fa4a 206static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 207static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
208static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 209static int ath5k_start(struct ieee80211_hw *hw);
210static void ath5k_stop(struct ieee80211_hw *hw);
211static int ath5k_add_interface(struct ieee80211_hw *hw,
212 struct ieee80211_if_init_conf *conf);
213static void ath5k_remove_interface(struct ieee80211_hw *hw,
214 struct ieee80211_if_init_conf *conf);
215static int ath5k_config(struct ieee80211_hw *hw,
216 struct ieee80211_conf *conf);
32bfd35d
JB		 217static int ath5k_config_interface(struct ieee80211_hw *hw,
218 struct ieee80211_vif *vif,
fa1c114f
JS		 219 struct ieee80211_if_conf *conf);
220static void ath5k_configure_filter(struct ieee80211_hw *hw,
221 unsigned int changed_flags,
222 unsigned int *new_flags,
223 int mc_count, struct dev_mc_list *mclist);
224static int ath5k_set_key(struct ieee80211_hw *hw,
225 enum set_key_cmd cmd,
226 const u8 *local_addr, const u8 *addr,
227 struct ieee80211_key_conf *key);
228static int ath5k_get_stats(struct ieee80211_hw *hw,
229 struct ieee80211_low_level_stats *stats);
230static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
231 struct ieee80211_tx_queue_stats *stats);
232static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
233static void ath5k_reset_tsf(struct ieee80211_hw *hw);
234static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 235 struct sk_buff *skb);
fa1c114f
JS		 236
237static struct ieee80211_ops ath5k_hw_ops = {
238 .tx = ath5k_tx,
239 .start = ath5k_start,
240 .stop = ath5k_stop,
241 .add_interface = ath5k_add_interface,
242 .remove_interface = ath5k_remove_interface,
243 .config = ath5k_config,
244 .config_interface = ath5k_config_interface,
245 .configure_filter = ath5k_configure_filter,
246 .set_key = ath5k_set_key,
247 .get_stats = ath5k_get_stats,
248 .conf_tx = NULL,
249 .get_tx_stats = ath5k_get_tx_stats,
250 .get_tsf = ath5k_get_tsf,
251 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 252};
253
254/*
255 * Prototypes - Internal functions
256 */
257/* Attach detach */
258static int ath5k_attach(struct pci_dev *pdev,
259 struct ieee80211_hw *hw);
260static void ath5k_detach(struct pci_dev *pdev,
261 struct ieee80211_hw *hw);
262/* Channel/mode setup */
263static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 264static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
265 struct ieee80211_channel *channels,
266 unsigned int mode,
267 unsigned int max);
63266a65 268static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 269static int ath5k_chan_set(struct ath5k_softc *sc,
270 struct ieee80211_channel *chan);
271static void ath5k_setcurmode(struct ath5k_softc *sc,
272 unsigned int mode);
273static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 274
fa1c114f
JS		 275/* Descriptor setup */
276static int ath5k_desc_alloc(struct ath5k_softc *sc,
277 struct pci_dev *pdev);
278static void ath5k_desc_free(struct ath5k_softc *sc,
279 struct pci_dev *pdev);
280/* Buffers setup */
281static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
282 struct ath5k_buf *bf);
283static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 284 struct ath5k_buf *bf);
fa1c114f
JS		 285static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
286 struct ath5k_buf *bf)
287{
288 BUG_ON(!bf);
289 if (!bf->skb)
290 return;
291 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
292 PCI_DMA_TODEVICE);
293 dev_kfree_skb(bf->skb);
294 bf->skb = NULL;
295}
296
297/* Queues setup */
298static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
299 int qtype, int subtype);
300static int ath5k_beaconq_setup(struct ath5k_hw *ah);
301static int ath5k_beaconq_config(struct ath5k_softc *sc);
302static void ath5k_txq_drainq(struct ath5k_softc *sc,
303 struct ath5k_txq *txq);
304static void ath5k_txq_cleanup(struct ath5k_softc *sc);
305static void ath5k_txq_release(struct ath5k_softc *sc);
306/* Rx handling */
307static int ath5k_rx_start(struct ath5k_softc *sc);
308static void ath5k_rx_stop(struct ath5k_softc *sc);
309static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
310 struct ath5k_desc *ds,
b47f407b
BR		 311 struct sk_buff *skb,
312 struct ath5k_rx_status *rs);
fa1c114f
JS		 313static void ath5k_tasklet_rx(unsigned long data);
314/* Tx handling */
315static void ath5k_tx_processq(struct ath5k_softc *sc,
316 struct ath5k_txq *txq);
317static void ath5k_tasklet_tx(unsigned long data);
318/* Beacon handling */
319static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 320 struct ath5k_buf *bf);
fa1c114f
JS		 321static void ath5k_beacon_send(struct ath5k_softc *sc);
322static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 323static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 324
325static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
326{
327 u64 tsf = ath5k_hw_get_tsf64(ah);
328
329 if ((tsf & 0x7fff) < rstamp)
330 tsf -= 0x8000;
331
332 return (tsf & ~0x7fff) | rstamp;
333}
334
335/* Interrupt handling */
336static int ath5k_init(struct ath5k_softc *sc);
337static int ath5k_stop_locked(struct ath5k_softc *sc);
338static int ath5k_stop_hw(struct ath5k_softc *sc);
339static irqreturn_t ath5k_intr(int irq, void *dev_id);
340static void ath5k_tasklet_reset(unsigned long data);
341
342static void ath5k_calibrate(unsigned long data);
343/* LED functions */
3a078876
BC		 344static int ath5k_init_leds(struct ath5k_softc *sc);
345static void ath5k_led_enable(struct ath5k_softc *sc);
346static void ath5k_led_off(struct ath5k_softc *sc);
347static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 348
349/*
350 * Module init/exit functions
351 */
352static int __init
353init_ath5k_pci(void)
354{
355 int ret;
356
357 ath5k_debug_init();
358
04a9e451 359 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 360 if (ret) {
361 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
362 return ret;
363 }
364
365 return 0;
366}
367
368static void __exit
369exit_ath5k_pci(void)
370{
04a9e451 371 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 372
373 ath5k_debug_finish();
374}
375
376module_init(init_ath5k_pci);
377module_exit(exit_ath5k_pci);
378
379
380/********************\
381* PCI Initialization *
382\********************/
383
384static const char *
385ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
386{
387 const char *name = "xxxxx";
388 unsigned int i;
389
390 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
391 if (srev_names[i].sr_type != type)
392 continue;
393 if ((val & 0xff) < srev_names[i + 1].sr_val) {
394 name = srev_names[i].sr_name;
395 break;
396 }
397 }
398
399 return name;
400}
401
402static int __devinit
403ath5k_pci_probe(struct pci_dev *pdev,
404 const struct pci_device_id *id)
405{
406 void __iomem *mem;
407 struct ath5k_softc *sc;
408 struct ieee80211_hw *hw;
409 int ret;
410 u8 csz;
411
412 ret = pci_enable_device(pdev);
413 if (ret) {
414 dev_err(&pdev->dev, "can't enable device\n");
415 goto err;
416 }
417
418 /* XXX 32-bit addressing only */
419 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
420 if (ret) {
421 dev_err(&pdev->dev, "32-bit DMA not available\n");
422 goto err_dis;
423 }
424
425 /*
426 * Cache line size is used to size and align various
427 * structures used to communicate with the hardware.
428 */
429 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
430 if (csz == 0) {
431 /*
432 * Linux 2.4.18 (at least) writes the cache line size
433 * register as a 16-bit wide register which is wrong.
434 * We must have this setup properly for rx buffer
435 * DMA to work so force a reasonable value here if it
436 * comes up zero.
437 */
438 csz = L1_CACHE_BYTES / sizeof(u32);
439 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
440 }
441 /*
442 * The default setting of latency timer yields poor results,
443 * set it to the value used by other systems. It may be worth
444 * tweaking this setting more.
445 */
446 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
447
448 /* Enable bus mastering */
449 pci_set_master(pdev);
450
451 /*
452 * Disable the RETRY_TIMEOUT register (0x41) to keep
453 * PCI Tx retries from interfering with C3 CPU state.
454 */
455 pci_write_config_byte(pdev, 0x41, 0);
456
457 ret = pci_request_region(pdev, 0, "ath5k");
458 if (ret) {
459 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
460 goto err_dis;
461 }
462
463 mem = pci_iomap(pdev, 0, 0);
464 if (!mem) {
465 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
466 ret = -EIO;
467 goto err_reg;
468 }
469
470 /*
471 * Allocate hw (mac80211 main struct)
472 * and hw->priv (driver private data)
473 */
474 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
475 if (hw == NULL) {
476 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
477 ret = -ENOMEM;
478 goto err_map;
479 }
480
481 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
482
483 /* Initialize driver private data */
484 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 485 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
486 IEEE80211_HW_SIGNAL_DBM |
487 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 488 hw->extra_tx_headroom = 2;
489 hw->channel_change_time = 5000;
fa1c114f
JS		 490 sc = hw->priv;
491 sc->hw = hw;
492 sc->pdev = pdev;
493
494 ath5k_debug_init_device(sc);
495
496 /*
497 * Mark the device as detached to avoid processing
498 * interrupts until setup is complete.
499 */
500 __set_bit(ATH_STAT_INVALID, sc->status);
501
502 sc->iobase = mem; /* So we can unmap it on detach */
503 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
504 sc->opmode = IEEE80211_IF_TYPE_STA;
505 mutex_init(&sc->lock);
506 spin_lock_init(&sc->rxbuflock);
507 spin_lock_init(&sc->txbuflock);
508
509 /* Set private data */
510 pci_set_drvdata(pdev, hw);
511
fa1c114f
JS		 512 /* Setup interrupt handler */
513 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
514 if (ret) {
515 ATH5K_ERR(sc, "request_irq failed\n");
516 goto err_free;
517 }
518
519 /* Initialize device */
520 sc->ah = ath5k_hw_attach(sc, id->driver_data);
521 if (IS_ERR(sc->ah)) {
522 ret = PTR_ERR(sc->ah);
523 goto err_irq;
524 }
525
526 /* Finish private driver data initialization */
527 ret = ath5k_attach(pdev, hw);
528 if (ret)
529 goto err_ah;
530
531 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
532 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
533 sc->ah->ah_mac_srev,
534 sc->ah->ah_phy_revision);
535
400ec45a 536 if (!sc->ah->ah_single_chip) {
fa1c114f 537 /* Single chip radio (!RF5111) */
400ec45a
LR		 538 if (sc->ah->ah_radio_5ghz_revision &&
539 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 540 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 541 if (!test_bit(AR5K_MODE_11A,
542 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 543 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 544 ath5k_chip_name(AR5K_VERSION_RAD,
545 sc->ah->ah_radio_5ghz_revision),
546 sc->ah->ah_radio_5ghz_revision);
547 /* No 2GHz support (5110 and some
548 * 5Ghz only cards) -> report 5Ghz radio */
549 } else if (!test_bit(AR5K_MODE_11B,
550 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 551 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 552 ath5k_chip_name(AR5K_VERSION_RAD,
553 sc->ah->ah_radio_5ghz_revision),
554 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 555 /* Multiband radio */
556 } else {
557 ATH5K_INFO(sc, "RF%s multiband radio found"
558 " (0x%x)\n",
400ec45a
LR		 559 ath5k_chip_name(AR5K_VERSION_RAD,
560 sc->ah->ah_radio_5ghz_revision),
561 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 562 }
563 }
400ec45a
LR		 564 /* Multi chip radio (RF5111 - RF2111) ->
565 * report both 2GHz/5GHz radios */
566 else if (sc->ah->ah_radio_5ghz_revision &&
567 sc->ah->ah_radio_2ghz_revision){
fa1c114f 568 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 569 ath5k_chip_name(AR5K_VERSION_RAD,
570 sc->ah->ah_radio_5ghz_revision),
571 sc->ah->ah_radio_5ghz_revision);
fa1c114f 572 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 573 ath5k_chip_name(AR5K_VERSION_RAD,
574 sc->ah->ah_radio_2ghz_revision),
575 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 576 }
577 }
578
579
580 /* ready to process interrupts */
581 __clear_bit(ATH_STAT_INVALID, sc->status);
582
583 return 0;
584err_ah:
585 ath5k_hw_detach(sc->ah);
586err_irq:
587 free_irq(pdev->irq, sc);
588err_free:
fa1c114f
JS		 589 ieee80211_free_hw(hw);
590err_map:
591 pci_iounmap(pdev, mem);
592err_reg:
593 pci_release_region(pdev, 0);
594err_dis:
595 pci_disable_device(pdev);
596err:
597 return ret;
598}
599
600static void __devexit
601ath5k_pci_remove(struct pci_dev *pdev)
602{
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv;
605
606 ath5k_debug_finish_device(sc);
607 ath5k_detach(pdev, hw);
608 ath5k_hw_detach(sc->ah);
609 free_irq(pdev->irq, sc);
fa1c114f
JS		 610 pci_iounmap(pdev, sc->iobase);
611 pci_release_region(pdev, 0);
612 pci_disable_device(pdev);
613 ieee80211_free_hw(hw);
614}
615
616#ifdef CONFIG_PM
617static int
618ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
619{
620 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
621 struct ath5k_softc *sc = hw->priv;
622
3a078876 623 ath5k_led_off(sc);
fa1c114f
JS		 624
625 ath5k_stop_hw(sc);
3e4242b9
JS		 626
627 free_irq(pdev->irq, sc);
fa1c114f
JS		 628 pci_save_state(pdev);
629 pci_disable_device(pdev);
630 pci_set_power_state(pdev, PCI_D3hot);
631
632 return 0;
633}
634
635static int
636ath5k_pci_resume(struct pci_dev *pdev)
637{
638 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
639 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 640 struct ath5k_hw *ah = sc->ah;
641 int i, err;
fa1c114f 642
3e4242b9 643 pci_restore_state(pdev);
fa1c114f
JS		 644
645 err = pci_enable_device(pdev);
646 if (err)
647 return err;
648
fa1c114f
JS		 649 /*
650 * Suspend/Resume resets the PCI configuration space, so we have to
651 * re-disable the RETRY_TIMEOUT register (0x41) to keep
652 * PCI Tx retries from interfering with C3 CPU state
653 */
654 pci_write_config_byte(pdev, 0x41, 0);
655
3e4242b9
JS		 656 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
657 if (err) {
658 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 659 goto err_no_irq;
3e4242b9
JS		 660 }
661
662 err = ath5k_init(sc);
663 if (err)
664 goto err_irq;
3a078876 665 ath5k_led_enable(sc);
fa1c114f 666
247ae449
JL		 667 /*
668 * Reset the key cache since some parts do not
669 * reset the contents on initial power up or resume.
670 *
671 * FIXME: This may need to be revisited when mac80211 becomes
672 * aware of suspend/resume.
673 */
674 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
675 ath5k_hw_reset_key(ah, i);
676
fa1c114f 677 return 0;
3e4242b9
JS		 678err_irq:
679 free_irq(pdev->irq, sc);
37465c8a 680err_no_irq:
3e4242b9
JS		 681 pci_disable_device(pdev);
682 return err;
fa1c114f
JS		 683}
684#endif /* CONFIG_PM */
685
686
fa1c114f
JS		 687/***********************\
688* Driver Initialization *
689\***********************/
690
691static int
692ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
693{
694 struct ath5k_softc *sc = hw->priv;
695 struct ath5k_hw *ah = sc->ah;
696 u8 mac[ETH_ALEN];
697 unsigned int i;
698 int ret;
699
700 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
701
702 /*
703 * Check if the MAC has multi-rate retry support.
704 * We do this by trying to setup a fake extended
705 * descriptor. MAC's that don't have support will
706 * return false w/o doing anything. MAC's that do
707 * support it will return true w/o doing anything.
708 */
b9887638
JS		 709 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
710 if (ret < 0)
711 goto err;
712 if (ret > 0)
fa1c114f
JS		 713 __set_bit(ATH_STAT_MRRETRY, sc->status);
714
715 /*
716 * Reset the key cache since some parts do not
717 * reset the contents on initial power up.
718 */
c65638a7 719 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 720 ath5k_hw_reset_key(ah, i);
721
722 /*
723 * Collect the channel list. The 802.11 layer
724 * is resposible for filtering this list based
725 * on settings like the phy mode and regulatory
726 * domain restrictions.
727 */
63266a65 728 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 729 if (ret) {
730 ATH5K_ERR(sc, "can't get channels\n");
731 goto err;
732 }
733
734 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 735 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
736 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 737 else
d8ee398d 738 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 739
740 /*
741 * Allocate tx+rx descriptors and populate the lists.
742 */
743 ret = ath5k_desc_alloc(sc, pdev);
744 if (ret) {
745 ATH5K_ERR(sc, "can't allocate descriptors\n");
746 goto err;
747 }
748
749 /*
750 * Allocate hardware transmit queues: one queue for
751 * beacon frames and one data queue for each QoS
752 * priority. Note that hw functions handle reseting
753 * these queues at the needed time.
754 */
755 ret = ath5k_beaconq_setup(ah);
756 if (ret < 0) {
757 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
758 goto err_desc;
759 }
760 sc->bhalq = ret;
761
762 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
763 if (IS_ERR(sc->txq)) {
764 ATH5K_ERR(sc, "can't setup xmit queue\n");
765 ret = PTR_ERR(sc->txq);
766 goto err_bhal;
767 }
768
769 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
770 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
771 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
772 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 773
774 ath5k_hw_get_lladdr(ah, mac);
775 SET_IEEE80211_PERM_ADDR(hw, mac);
776 /* All MAC address bits matter for ACKs */
777 memset(sc->bssidmask, 0xff, ETH_ALEN);
778 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
779
780 ret = ieee80211_register_hw(hw);
781 if (ret) {
782 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
783 goto err_queues;
784 }
785
3a078876
BC		 786 ath5k_init_leds(sc);
787
fa1c114f
JS		 788 return 0;
789err_queues:
790 ath5k_txq_release(sc);
791err_bhal:
792 ath5k_hw_release_tx_queue(ah, sc->bhalq);
793err_desc:
794 ath5k_desc_free(sc, pdev);
795err:
796 return ret;
797}
798
799static void
800ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
801{
802 struct ath5k_softc *sc = hw->priv;
803
804 /*
805 * NB: the order of these is important:
806 * o call the 802.11 layer before detaching ath5k_hw to
807 * insure callbacks into the driver to delete global
808 * key cache entries can be handled
809 * o reclaim the tx queue data structures after calling
810 * the 802.11 layer as we'll get called back to reclaim
811 * node state and potentially want to use them
812 * o to cleanup the tx queues the hal is called, so detach
813 * it last
814 * XXX: ??? detach ath5k_hw ???
815 * Other than that, it's straightforward...
816 */
817 ieee80211_unregister_hw(hw);
818 ath5k_desc_free(sc, pdev);
819 ath5k_txq_release(sc);
820 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 821 ath5k_unregister_leds(sc);
fa1c114f
JS		 822
823 /*
824 * NB: can't reclaim these until after ieee80211_ifdetach
825 * returns because we'll get called back to reclaim node
826 * state and potentially want to use them.
827 */
828}
829
830
831
832
833/********************\
834* Channel/mode setup *
835\********************/
836
837/*
838 * Convert IEEE channel number to MHz frequency.
839 */
840static inline short
841ath5k_ieee2mhz(short chan)
842{
843 if (chan <= 14 || chan >= 27)
844 return ieee80211chan2mhz(chan);
845 else
846 return 2212 + chan * 20;
847}
848
fa1c114f
JS		 849static unsigned int
850ath5k_copy_channels(struct ath5k_hw *ah,
851 struct ieee80211_channel *channels,
852 unsigned int mode,
853 unsigned int max)
854{
d8ee398d 855 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 856
857 if (!test_bit(mode, ah->ah_modes))
858 return 0;
859
fa1c114f 860 switch (mode) {
d8ee398d
LR		 861 case AR5K_MODE_11A:
862 case AR5K_MODE_11A_TURBO:
fa1c114f 863 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 864 size = 220 ;
fa1c114f
JS		 865 chfreq = CHANNEL_5GHZ;
866 break;
d8ee398d
LR		 867 case AR5K_MODE_11B:
868 case AR5K_MODE_11G:
869 case AR5K_MODE_11G_TURBO:
870 size = 26;
fa1c114f
JS		 871 chfreq = CHANNEL_2GHZ;
872 break;
873 default:
874 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
875 return 0;
876 }
877
878 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 879 ch = i + 1 ;
880 freq = ath5k_ieee2mhz(ch);
fa1c114f 881
d8ee398d
LR		 882 /* Check if channel is supported by the chipset */
883 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 884 continue;
885
d8ee398d
LR		 886 /* Write channel info and increment counter */
887 channels[count].center_freq = freq;
a3f4b914
LR		 888 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
889 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 890 switch (mode) {
891 case AR5K_MODE_11A:
892 case AR5K_MODE_11G:
893 channels[count].hw_value = chfreq | CHANNEL_OFDM;
894 break;
895 case AR5K_MODE_11A_TURBO:
896 case AR5K_MODE_11G_TURBO:
897 channels[count].hw_value = chfreq |
898 CHANNEL_OFDM | CHANNEL_TURBO;
899 break;
900 case AR5K_MODE_11B:
d8ee398d
LR		 901 channels[count].hw_value = CHANNEL_B;
902 }
fa1c114f 903
fa1c114f
JS		 904 count++;
905 max--;
906 }
907
908 return count;
909}
910
63266a65
BR		 911static void
912ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
913{
914 u8 i;
915
916 for (i = 0; i < AR5K_MAX_RATES; i++)
917 sc->rate_idx[b->band][i] = -1;
918
919 for (i = 0; i < b->n_bitrates; i++) {
920 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
921 if (b->bitrates[i].hw_value_short)
922 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
923 }
924}
925
d8ee398d 926static int
63266a65 927ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 928{
929 struct ath5k_softc *sc = hw->priv;
d8ee398d 930 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 931 struct ieee80211_supported_band *sband;
932 int max_c, count_c = 0;
933 int i;
fa1c114f 934
d8ee398d 935 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 936 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 937
938 /* 2GHz band */
63266a65
BR		 939 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
940 sband->band = IEEE80211_BAND_2GHZ;
941 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 942
63266a65
BR		 943 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
944 /* G mode */
945 memcpy(sband->bitrates, &ath5k_rates[0],
946 sizeof(struct ieee80211_rate) * 12);
947 sband->n_bitrates = 12;
fa1c114f 948
d8ee398d 949 sband->channels = sc->channels;
d8ee398d 950 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 951 AR5K_MODE_11G, max_c);
fa1c114f 952
63266a65 953 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 954 count_c = sband->n_channels;
63266a65
BR		 955 max_c -= count_c;
956 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
957 /* B mode */
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 4);
960 sband->n_bitrates = 4;
961
962 /* 5211 only supports B rates and uses 4bit rate codes
963 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
964 * fix them up here:
965 */
966 if (ah->ah_version == AR5K_AR5211) {
967 for (i = 0; i < 4; i++) {
968 sband->bitrates[i].hw_value =
969 sband->bitrates[i].hw_value & 0xF;
970 sband->bitrates[i].hw_value_short =
971 sband->bitrates[i].hw_value_short & 0xF;
972 }
973 }
fa1c114f 974
63266a65
BR		 975 sband->channels = sc->channels;
976 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
977 AR5K_MODE_11B, max_c);
d8ee398d 978
63266a65
BR		 979 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
980 count_c = sband->n_channels;
d8ee398d 981 max_c -= count_c;
fa1c114f 982 }
63266a65 983 ath5k_setup_rate_idx(sc, sband);
fa1c114f 984
63266a65 985 /* 5GHz band, A mode */
400ec45a 986 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 987 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
988 sband->band = IEEE80211_BAND_5GHZ;
989 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 990
63266a65
BR		 991 memcpy(sband->bitrates, &ath5k_rates[4],
992 sizeof(struct ieee80211_rate) * 8);
993 sband->n_bitrates = 8;
fa1c114f 994
63266a65 995 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 996 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
997 AR5K_MODE_11A, max_c);
998
d8ee398d
LR		 999 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1000 }
63266a65 1001 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1002
b446197c 1003 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1004
1005 return 0;
fa1c114f
JS		 1006}
1007
1008/*
1009 * Set/change channels. If the channel is really being changed,
1010 * it's done by reseting the chip. To accomplish this we must
1011 * first cleanup any pending DMA, then restart stuff after a la
1012 * ath5k_init.
1013 */
1014static int
1015ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1016{
d8ee398d
LR		 1017 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1018 sc->curchan->center_freq, chan->center_freq);
1019
1020 if (chan->center_freq != sc->curchan->center_freq ||
1021 chan->hw_value != sc->curchan->hw_value) {
1022
1023 sc->curchan = chan;
1024 sc->curband = &sc->sbands[chan->band];
fa1c114f 1025
fa1c114f
JS		 1026 /*
1027 * To switch channels clear any pending DMA operations;
1028 * wait long enough for the RX fifo to drain, reset the
1029 * hardware at the new frequency, and then re-enable
1030 * the relevant bits of the h/w.
1031 */
d7dc1003 1032 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1033 }
1034
1035 return 0;
1036}
1037
1038static void
1039ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1040{
fa1c114f 1041 sc->curmode = mode;
d8ee398d 1042
400ec45a 1043 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1044 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1045 } else {
1046 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1047 }
fa1c114f
JS		 1048}
1049
1050static void
1051ath5k_mode_setup(struct ath5k_softc *sc)
1052{
1053 struct ath5k_hw *ah = sc->ah;
1054 u32 rfilt;
1055
1056 /* configure rx filter */
1057 rfilt = sc->filter_flags;
1058 ath5k_hw_set_rx_filter(ah, rfilt);
1059
1060 if (ath5k_hw_hasbssidmask(ah))
1061 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1062
1063 /* configure operational mode */
1064 ath5k_hw_set_opmode(ah);
1065
1066 ath5k_hw_set_mcast_filter(ah, 0, 0);
1067 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1068}
1069
d8ee398d 1070static inline int
63266a65
BR		 1071ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1072{
1073 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1074 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1075}
1076
fa1c114f
JS		 1077/***************\
1078* Buffers setup *
1079\***************/
1080
1081static int
1082ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1083{
1084 struct ath5k_hw *ah = sc->ah;
1085 struct sk_buff *skb = bf->skb;
1086 struct ath5k_desc *ds;
1087
1088 if (likely(skb == NULL)) {
1089 unsigned int off;
1090
1091 /*
1092 * Allocate buffer with headroom_needed space for the
1093 * fake physical layer header at the start.
1094 */
1095 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1096 if (unlikely(skb == NULL)) {
1097 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1098 sc->rxbufsize + sc->cachelsz - 1);
1099 return -ENOMEM;
1100 }
1101 /*
1102 * Cache-line-align. This is important (for the
1103 * 5210 at least) as not doing so causes bogus data
1104 * in rx'd frames.
1105 */
1106 off = ((unsigned long)skb->data) % sc->cachelsz;
1107 if (off != 0)
1108 skb_reserve(skb, sc->cachelsz - off);
1109
1110 bf->skb = skb;
1111 bf->skbaddr = pci_map_single(sc->pdev,
1112 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1113 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1114 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1115 dev_kfree_skb(skb);
1116 bf->skb = NULL;
1117 return -ENOMEM;
1118 }
1119 }
1120
1121 /*
1122 * Setup descriptors. For receive we always terminate
1123 * the descriptor list with a self-linked entry so we'll
1124 * not get overrun under high load (as can happen with a
1125 * 5212 when ANI processing enables PHY error frames).
1126 *
1127 * To insure the last descriptor is self-linked we create
1128 * each descriptor as self-linked and add it to the end. As
1129 * each additional descriptor is added the previous self-linked
1130 * entry is ``fixed'' naturally. This should be safe even
1131 * if DMA is happening. When processing RX interrupts we
1132 * never remove/process the last, self-linked, entry on the
1133 * descriptor list. This insures the hardware always has
1134 * someplace to write a new frame.
1135 */
1136 ds = bf->desc;
1137 ds->ds_link = bf->daddr; /* link to self */
1138 ds->ds_data = bf->skbaddr;
1139 ath5k_hw_setup_rx_desc(ah, ds,
1140 skb_tailroom(skb), /* buffer size */
1141 0);
1142
1143 if (sc->rxlink != NULL)
1144 *sc->rxlink = bf->daddr;
1145 sc->rxlink = &ds->ds_link;
1146 return 0;
1147}
1148
1149static int
e039fa4a 1150ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1151{
1152 struct ath5k_hw *ah = sc->ah;
1153 struct ath5k_txq *txq = sc->txq;
1154 struct ath5k_desc *ds = bf->desc;
1155 struct sk_buff *skb = bf->skb;
a888d52d 1156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1157 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1158 int ret;
1159
1160 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1161
fa1c114f
JS		 1162 /* XXX endianness */
1163 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1164 PCI_DMA_TODEVICE);
1165
e039fa4a 1166 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1167 flags |= AR5K_TXDESC_NOACK;
1168
281c56dd 1169 pktlen = skb->len;
fa1c114f 1170
d0f09804 1171 if (info->control.hw_key) {
e039fa4a
JB		 1172 keyidx = info->control.hw_key->hw_key_idx;
1173 pktlen += info->control.icv_len;
fa1c114f 1174 }
fa1c114f
JS		 1175 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1176 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1177 (sc->power_level * 2),
e039fa4a
JB		 1178 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1179 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1180 if (ret)
1181 goto err_unmap;
1182
1183 ds->ds_link = 0;
1184 ds->ds_data = bf->skbaddr;
1185
1186 spin_lock_bh(&txq->lock);
1187 list_add_tail(&bf->list, &txq->q);
57ffc589 1188 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1189 if (txq->link == NULL) /* is this first packet? */
1190 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1191 else /* no, so only link it */
1192 *txq->link = bf->daddr;
1193
1194 txq->link = &ds->ds_link;
1195 ath5k_hw_tx_start(ah, txq->qnum);
274c7c36 1196 mmiowb();
fa1c114f
JS		 1197 spin_unlock_bh(&txq->lock);
1198
1199 return 0;
1200err_unmap:
1201 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1202 return ret;
1203}
1204
1205/*******************\
1206* Descriptors setup *
1207\*******************/
1208
1209static int
1210ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1211{
1212 struct ath5k_desc *ds;
1213 struct ath5k_buf *bf;
1214 dma_addr_t da;
1215 unsigned int i;
1216 int ret;
1217
1218 /* allocate descriptors */
1219 sc->desc_len = sizeof(struct ath5k_desc) *
1220 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1221 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1222 if (sc->desc == NULL) {
1223 ATH5K_ERR(sc, "can't allocate descriptors\n");
1224 ret = -ENOMEM;
1225 goto err;
1226 }
1227 ds = sc->desc;
1228 da = sc->desc_daddr;
1229 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1230 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1231
1232 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1233 sizeof(struct ath5k_buf), GFP_KERNEL);
1234 if (bf == NULL) {
1235 ATH5K_ERR(sc, "can't allocate bufptr\n");
1236 ret = -ENOMEM;
1237 goto err_free;
1238 }
1239 sc->bufptr = bf;
1240
1241 INIT_LIST_HEAD(&sc->rxbuf);
1242 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1243 bf->desc = ds;
1244 bf->daddr = da;
1245 list_add_tail(&bf->list, &sc->rxbuf);
1246 }
1247
1248 INIT_LIST_HEAD(&sc->txbuf);
1249 sc->txbuf_len = ATH_TXBUF;
1250 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1251 da += sizeof(*ds)) {
1252 bf->desc = ds;
1253 bf->daddr = da;
1254 list_add_tail(&bf->list, &sc->txbuf);
1255 }
1256
1257 /* beacon buffer */
1258 bf->desc = ds;
1259 bf->daddr = da;
1260 sc->bbuf = bf;
1261
1262 return 0;
1263err_free:
1264 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1265err:
1266 sc->desc = NULL;
1267 return ret;
1268}
1269
1270static void
1271ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1272{
1273 struct ath5k_buf *bf;
1274
1275 ath5k_txbuf_free(sc, sc->bbuf);
1276 list_for_each_entry(bf, &sc->txbuf, list)
1277 ath5k_txbuf_free(sc, bf);
1278 list_for_each_entry(bf, &sc->rxbuf, list)
1279 ath5k_txbuf_free(sc, bf);
1280
1281 /* Free memory associated with all descriptors */
1282 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1283
1284 kfree(sc->bufptr);
1285 sc->bufptr = NULL;
1286}
1287
1288
1289
1290
1291
1292/**************\
1293* Queues setup *
1294\**************/
1295
1296static struct ath5k_txq *
1297ath5k_txq_setup(struct ath5k_softc *sc,
1298 int qtype, int subtype)
1299{
1300 struct ath5k_hw *ah = sc->ah;
1301 struct ath5k_txq *txq;
1302 struct ath5k_txq_info qi = {
1303 .tqi_subtype = subtype,
1304 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1305 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1306 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1307 };
1308 int qnum;
1309
1310 /*
1311 * Enable interrupts only for EOL and DESC conditions.
1312 * We mark tx descriptors to receive a DESC interrupt
1313 * when a tx queue gets deep; otherwise waiting for the
1314 * EOL to reap descriptors. Note that this is done to
1315 * reduce interrupt load and this only defers reaping
1316 * descriptors, never transmitting frames. Aside from
1317 * reducing interrupts this also permits more concurrency.
1318 * The only potential downside is if the tx queue backs
1319 * up in which case the top half of the kernel may backup
1320 * due to a lack of tx descriptors.
1321 */
1322 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1323 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1324 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1325 if (qnum < 0) {
1326 /*
1327 * NB: don't print a message, this happens
1328 * normally on parts with too few tx queues
1329 */
1330 return ERR_PTR(qnum);
1331 }
1332 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1333 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1334 qnum, ARRAY_SIZE(sc->txqs));
1335 ath5k_hw_release_tx_queue(ah, qnum);
1336 return ERR_PTR(-EINVAL);
1337 }
1338 txq = &sc->txqs[qnum];
1339 if (!txq->setup) {
1340 txq->qnum = qnum;
1341 txq->link = NULL;
1342 INIT_LIST_HEAD(&txq->q);
1343 spin_lock_init(&txq->lock);
1344 txq->setup = true;
1345 }
1346 return &sc->txqs[qnum];
1347}
1348
1349static int
1350ath5k_beaconq_setup(struct ath5k_hw *ah)
1351{
1352 struct ath5k_txq_info qi = {
1353 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1354 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1355 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1356 /* NB: for dynamic turbo, don't enable any other interrupts */
1357 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1358 };
1359
1360 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1361}
1362
1363static int
1364ath5k_beaconq_config(struct ath5k_softc *sc)
1365{
1366 struct ath5k_hw *ah = sc->ah;
1367 struct ath5k_txq_info qi;
1368 int ret;
1369
1370 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1371 if (ret)
1372 return ret;
8e5f3d0a
AY		 1373 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1374 sc->opmode == IEEE80211_IF_TYPE_MESH_POINT) {
fa1c114f
JS		 1375 /*
1376 * Always burst out beacon and CAB traffic
1377 * (aifs = cwmin = cwmax = 0)
1378 */
1379 qi.tqi_aifs = 0;
1380 qi.tqi_cw_min = 0;
1381 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1382 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1383 /*
1384 * Adhoc mode; backoff between 0 and (2 * cw_min).
1385 */
1386 qi.tqi_aifs = 0;
1387 qi.tqi_cw_min = 0;
1388 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1389 }
1390
6d91e1d8
BR		 1391 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1392 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1393 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1394
fa1c114f
JS		 1395 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1396 if (ret) {
1397 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1398 "hardware queue!\n", __func__);
1399 return ret;
1400 }
1401
1402 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1403}
1404
1405static void
1406ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1407{
1408 struct ath5k_buf *bf, *bf0;
1409
1410 /*
1411 * NB: this assumes output has been stopped and
1412 * we do not need to block ath5k_tx_tasklet
1413 */
1414 spin_lock_bh(&txq->lock);
1415 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1416 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1417
1418 ath5k_txbuf_free(sc, bf);
1419
1420 spin_lock_bh(&sc->txbuflock);
57ffc589 1421 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1422 list_move_tail(&bf->list, &sc->txbuf);
1423 sc->txbuf_len++;
1424 spin_unlock_bh(&sc->txbuflock);
1425 }
1426 txq->link = NULL;
1427 spin_unlock_bh(&txq->lock);
1428}
1429
1430/*
1431 * Drain the transmit queues and reclaim resources.
1432 */
1433static void
1434ath5k_txq_cleanup(struct ath5k_softc *sc)
1435{
1436 struct ath5k_hw *ah = sc->ah;
1437 unsigned int i;
1438
1439 /* XXX return value */
1440 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1441 /* don't touch the hardware if marked invalid */
1442 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1443 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1444 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1445 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1446 if (sc->txqs[i].setup) {
1447 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1448 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1449 "link %p\n",
1450 sc->txqs[i].qnum,
1451 ath5k_hw_get_tx_buf(ah,
1452 sc->txqs[i].qnum),
1453 sc->txqs[i].link);
1454 }
1455 }
36d6825b 1456 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1457
1458 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1459 if (sc->txqs[i].setup)
1460 ath5k_txq_drainq(sc, &sc->txqs[i]);
1461}
1462
1463static void
1464ath5k_txq_release(struct ath5k_softc *sc)
1465{
1466 struct ath5k_txq *txq = sc->txqs;
1467 unsigned int i;
1468
1469 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1470 if (txq->setup) {
1471 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1472 txq->setup = false;
1473 }
1474}
1475
1476
1477
1478
1479/*************\
1480* RX Handling *
1481\*************/
1482
1483/*
1484 * Enable the receive h/w following a reset.
1485 */
1486static int
1487ath5k_rx_start(struct ath5k_softc *sc)
1488{
1489 struct ath5k_hw *ah = sc->ah;
1490 struct ath5k_buf *bf;
1491 int ret;
1492
1493 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1494
1495 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1496 sc->cachelsz, sc->rxbufsize);
1497
1498 sc->rxlink = NULL;
1499
1500 spin_lock_bh(&sc->rxbuflock);
1501 list_for_each_entry(bf, &sc->rxbuf, list) {
1502 ret = ath5k_rxbuf_setup(sc, bf);
1503 if (ret != 0) {
1504 spin_unlock_bh(&sc->rxbuflock);
1505 goto err;
1506 }
1507 }
1508 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1509 spin_unlock_bh(&sc->rxbuflock);
1510
1511 ath5k_hw_put_rx_buf(ah, bf->daddr);
1512 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1513 ath5k_mode_setup(sc); /* set filters, etc. */
1514 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1515
1516 return 0;
1517err:
1518 return ret;
1519}
1520
1521/*
1522 * Disable the receive h/w in preparation for a reset.
1523 */
1524static void
1525ath5k_rx_stop(struct ath5k_softc *sc)
1526{
1527 struct ath5k_hw *ah = sc->ah;
1528
1529 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1530 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1531 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1532
1533 ath5k_debug_printrxbuffs(sc, ah);
1534
1535 sc->rxlink = NULL; /* just in case */
1536}
1537
1538static unsigned int
1539ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1540 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1541{
1542 struct ieee80211_hdr *hdr = (void *)skb->data;
1543 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1544
b47f407b
BR		 1545 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1546 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1547 return RX_FLAG_DECRYPTED;
1548
1549 /* Apparently when a default key is used to decrypt the packet
1550 the hw does not set the index used to decrypt. In such cases
1551 get the index from the packet. */
24b56e70
HH		 1552 if (ieee80211_has_protected(hdr->frame_control) &&
1553 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1554 skb->len >= hlen + 4) {
fa1c114f
JS		 1555 keyix = skb->data[hlen + 3] >> 6;
1556
1557 if (test_bit(keyix, sc->keymap))
1558 return RX_FLAG_DECRYPTED;
1559 }
1560
1561 return 0;
1562}
1563
036cd1ec
BR		 1564
1565static void
6ba81c2c
BR		 1566ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1567 struct ieee80211_rx_status *rxs)
036cd1ec 1568{
6ba81c2c 1569 u64 tsf, bc_tstamp;
036cd1ec
BR		 1570 u32 hw_tu;
1571 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1572
24b56e70 1573 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1574 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1575 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1576 /*
6ba81c2c
BR		 1577 * Received an IBSS beacon with the same BSSID. Hardware *must*
1578 * have updated the local TSF. We have to work around various
1579 * hardware bugs, though...
036cd1ec 1580 */
6ba81c2c
BR		 1581 tsf = ath5k_hw_get_tsf64(sc->ah);
1582 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1583 hw_tu = TSF_TO_TU(tsf);
1584
1585 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1586 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1587 (unsigned long long)bc_tstamp,
1588 (unsigned long long)rxs->mactime,
1589 (unsigned long long)(rxs->mactime - bc_tstamp),
1590 (unsigned long long)tsf);
6ba81c2c
BR		 1591
1592 /*
1593 * Sometimes the HW will give us a wrong tstamp in the rx
1594 * status, causing the timestamp extension to go wrong.
1595 * (This seems to happen especially with beacon frames bigger
1596 * than 78 byte (incl. FCS))
1597 * But we know that the receive timestamp must be later than the
1598 * timestamp of the beacon since HW must have synced to that.
1599 *
1600 * NOTE: here we assume mactime to be after the frame was
1601 * received, not like mac80211 which defines it at the start.
1602 */
1603 if (bc_tstamp > rxs->mactime) {
036cd1ec 1604 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1605 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1606 (unsigned long long)rxs->mactime,
1607 (unsigned long long)tsf);
6ba81c2c 1608 rxs->mactime = tsf;
036cd1ec 1609 }
6ba81c2c
BR		 1610
1611 /*
1612 * Local TSF might have moved higher than our beacon timers,
1613 * in that case we have to update them to continue sending
1614 * beacons. This also takes care of synchronizing beacon sending
1615 * times with other stations.
1616 */
1617 if (hw_tu >= sc->nexttbtt)
1618 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1619 }
1620}
1621
1622
fa1c114f
JS		 1623static void
1624ath5k_tasklet_rx(unsigned long data)
1625{
1626 struct ieee80211_rx_status rxs = {};
b47f407b 1627 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1628 struct sk_buff *skb;
1629 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1630 struct ath5k_buf *bf, *bf_last;
fa1c114f 1631 struct ath5k_desc *ds;
fa1c114f
JS		 1632 int ret;
1633 int hdrlen;
1634 int pad;
1635
1636 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1637 if (list_empty(&sc->rxbuf)) {
1638 ATH5K_WARN(sc, "empty rx buf pool\n");
1639 goto unlock;
1640 }
1641 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1642 do {
d6894b5b
BC		 1643 rxs.flag = 0;
1644
fa1c114f
JS		 1645 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1646 BUG_ON(bf->skb == NULL);
1647 skb = bf->skb;
1648 ds = bf->desc;
1649
3a0f2c87
JS		 1650 /*
1651 * last buffer must not be freed to ensure proper hardware
1652 * function. When the hardware finishes also a packet next to
1653 * it, we are sure, it doesn't use it anymore and we can go on.
1654 */
1655 if (bf_last == bf)
1656 bf->flags |= 1;
1657 if (bf->flags) {
1658 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1659 struct ath5k_buf, list);
1660 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1661 &rs);
1662 if (ret)
1663 break;
1664 bf->flags &= ~1;
1665 /* skip the overwritten one (even status is martian) */
1666 goto next;
1667 }
fa1c114f 1668
b47f407b 1669 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1670 if (unlikely(ret == -EINPROGRESS))
1671 break;
1672 else if (unlikely(ret)) {
1673 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1674 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1675 return;
1676 }
1677
b47f407b 1678 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1679 ATH5K_WARN(sc, "unsupported jumbo\n");
1680 goto next;
1681 }
1682
b47f407b
BR		 1683 if (unlikely(rs.rs_status)) {
1684 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1685 goto next;
b47f407b 1686 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1687 /*
1688 * Decrypt error. If the error occurred
1689 * because there was no hardware key, then
1690 * let the frame through so the upper layers
1691 * can process it. This is necessary for 5210
1692 * parts which have no way to setup a ``clear''
1693 * key cache entry.
1694 *
1695 * XXX do key cache faulting
1696 */
b47f407b
BR		 1697 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1698 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1699 goto accept;
1700 }
b47f407b 1701 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1702 rxs.flag |= RX_FLAG_MMIC_ERROR;
1703 goto accept;
1704 }
1705
1706 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1707 if ((rs.rs_status &
1708 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1709 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1710 goto next;
1711 }
1712accept:
fa1c114f
JS		 1713 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1714 PCI_DMA_FROMDEVICE);
1715 bf->skb = NULL;
1716
b47f407b 1717 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1718
1719 /*
1720 * the hardware adds a padding to 4 byte boundaries between
1721 * the header and the payload data if the header length is
1722 * not multiples of 4 - remove it
1723 */
1724 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1725 if (hdrlen & 3) {
1726 pad = hdrlen % 4;
1727 memmove(skb->data + pad, skb->data, hdrlen);
1728 skb_pull(skb, pad);
1729 }
1730
c0e1899b
BR		 1731 /*
1732 * always extend the mac timestamp, since this information is
1733 * also needed for proper IBSS merging.
1734 *
1735 * XXX: it might be too late to do it here, since rs_tstamp is
1736 * 15bit only. that means TSF extension has to be done within
1737 * 32768usec (about 32ms). it might be necessary to move this to
1738 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1739 *
1740 * Unfortunately we don't know when the hardware takes the rx
1741 * timestamp (beginning of phy frame, data frame, end of rx?).
1742 * The only thing we know is that it is hardware specific...
1743 * On AR5213 it seems the rx timestamp is at the end of the
1744 * frame, but i'm not sure.
1745 *
1746 * NOTE: mac80211 defines mactime at the beginning of the first
1747 * data symbol. Since we don't have any time references it's
1748 * impossible to comply to that. This affects IBSS merge only
1749 * right now, so it's not too bad...
c0e1899b 1750 */
b47f407b 1751 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1752 rxs.flag |= RX_FLAG_TSFT;
1753
d8ee398d
LR		 1754 rxs.freq = sc->curchan->center_freq;
1755 rxs.band = sc->curband->band;
fa1c114f 1756
fa1c114f 1757 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1758 rxs.signal = rxs.noise + rs.rs_rssi;
1759 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1760
b47f407b
BR		 1761 rxs.antenna = rs.rs_antenna;
1762 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1763 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1764
63266a65
BR		 1765#if 0 /* add rxs.flag SHORTPRE once it is in mac80211 */
1766 if (rs.rs_rate >= ATH5K_RATE_CODE_2M &&
1767 rs.rs_rate <= ATH5K_RATE_CODE_11M &&
1768 rs.rs_rate & AR5K_SET_SHORT_PREAMBLE)
1769 rxs.flag |= RX_FLAG_SHORTPRE;
1770#endif
fa1c114f
JS		 1771 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1772
036cd1ec
BR		 1773 /* check beacons in IBSS mode */
1774 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1775 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1776
fa1c114f 1777 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1778next:
1779 list_move_tail(&bf->list, &sc->rxbuf);
1780 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1781unlock:
fa1c114f
JS		 1782 spin_unlock(&sc->rxbuflock);
1783}
1784
1785
1786
1787
1788/*************\
1789* TX Handling *
1790\*************/
1791
1792static void
1793ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1794{
b47f407b 1795 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1796 struct ath5k_buf *bf, *bf0;
1797 struct ath5k_desc *ds;
1798 struct sk_buff *skb;
e039fa4a 1799 struct ieee80211_tx_info *info;
fa1c114f
JS		 1800 int ret;
1801
1802 spin_lock(&txq->lock);
1803 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1804 ds = bf->desc;
1805
b47f407b 1806 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1807 if (unlikely(ret == -EINPROGRESS))
1808 break;
1809 else if (unlikely(ret)) {
1810 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1811 ret, txq->qnum);
1812 break;
1813 }
1814
1815 skb = bf->skb;
a888d52d 1816 info = IEEE80211_SKB_CB(skb);
fa1c114f 1817 bf->skb = NULL;
e039fa4a 1818
fa1c114f
JS		 1819 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1820 PCI_DMA_TODEVICE);
1821
e039fa4a 1822 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1823 if (unlikely(ts.ts_status)) {
fa1c114f 1824 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1825 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1826 info->status.excessive_retries = 1;
b47f407b 1827 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1828 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1829 } else {
e039fa4a
JB		 1830 info->flags |= IEEE80211_TX_STAT_ACK;
1831 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1832 }
1833
e039fa4a 1834 ieee80211_tx_status(sc->hw, skb);
57ffc589 1835 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1836
1837 spin_lock(&sc->txbuflock);
57ffc589 1838 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1839 list_move_tail(&bf->list, &sc->txbuf);
1840 sc->txbuf_len++;
1841 spin_unlock(&sc->txbuflock);
1842 }
1843 if (likely(list_empty(&txq->q)))
1844 txq->link = NULL;
1845 spin_unlock(&txq->lock);
1846 if (sc->txbuf_len > ATH_TXBUF / 5)
1847 ieee80211_wake_queues(sc->hw);
1848}
1849
1850static void
1851ath5k_tasklet_tx(unsigned long data)
1852{
1853 struct ath5k_softc *sc = (void *)data;
1854
1855 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1856}
1857
1858
fa1c114f
JS		 1859/*****************\
1860* Beacon handling *
1861\*****************/
1862
1863/*
1864 * Setup the beacon frame for transmit.
1865 */
1866static int
e039fa4a 1867ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1868{
1869 struct sk_buff *skb = bf->skb;
a888d52d 1870 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1871 struct ath5k_hw *ah = sc->ah;
1872 struct ath5k_desc *ds;
1873 int ret, antenna = 0;
1874 u32 flags;
1875
1876 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1877 PCI_DMA_TODEVICE);
1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1879 "skbaddr %llx\n", skb, skb->data, skb->len,
1880 (unsigned long long)bf->skbaddr);
8d8bb39b 1881 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1882 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1883 return -EIO;
1884 }
1885
1886 ds = bf->desc;
1887
1888 flags = AR5K_TXDESC_NOACK;
1889 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1890 ds->ds_link = bf->daddr; /* self-linked */
1891 flags |= AR5K_TXDESC_VEOL;
1892 /*
1893 * Let hardware handle antenna switching if txantenna is not set
1894 */
1895 } else {
1896 ds->ds_link = 0;
1897 /*
1898 * Switch antenna every 4 beacons if txantenna is not set
1899 * XXX assumes two antennas
1900 */
1901 if (antenna == 0)
1902 antenna = sc->bsent & 4 ? 2 : 1;
1903 }
1904
1905 ds->ds_data = bf->skbaddr;
281c56dd 1906 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1907 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1908 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1909 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1910 1, AR5K_TXKEYIX_INVALID,
400ec45a 1911 antenna, flags, 0, 0);
fa1c114f
JS		 1912 if (ret)
1913 goto err_unmap;
1914
1915 return 0;
1916err_unmap:
1917 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1918 return ret;
1919}
1920
1921/*
1922 * Transmit a beacon frame at SWBA. Dynamic updates to the
1923 * frame contents are done as needed and the slot time is
1924 * also adjusted based on current state.
1925 *
1926 * this is usually called from interrupt context (ath5k_intr())
1927 * but also from ath5k_beacon_config() in IBSS mode which in turn
1928 * can be called from a tasklet and user context
1929 */
1930static void
1931ath5k_beacon_send(struct ath5k_softc *sc)
1932{
1933 struct ath5k_buf *bf = sc->bbuf;
1934 struct ath5k_hw *ah = sc->ah;
1935
be9b7259 1936 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1937
1938 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1939 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1940 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1941 return;
1942 }
1943 /*
1944 * Check if the previous beacon has gone out. If
1945 * not don't don't try to post another, skip this
1946 * period and wait for the next. Missed beacons
1947 * indicate a problem and should not occur. If we
1948 * miss too many consecutive beacons reset the device.
1949 */
1950 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1951 sc->bmisscount++;
be9b7259 1952 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1953 "missed %u consecutive beacons\n", sc->bmisscount);
1954 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1955 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1956 "stuck beacon time (%u missed)\n",
1957 sc->bmisscount);
1958 tasklet_schedule(&sc->restq);
1959 }
1960 return;
1961 }
1962 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1963 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1964 "resume beacon xmit after %u misses\n",
1965 sc->bmisscount);
1966 sc->bmisscount = 0;
1967 }
1968
1969 /*
1970 * Stop any current dma and put the new frame on the queue.
1971 * This should never fail since we check above that no frames
1972 * are still pending on the queue.
1973 */
1974 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1975 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1976 /* NB: hw still stops DMA, so proceed */
1977 }
fa1c114f
JS		 1978
1979 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1980 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 1981 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1982 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1983
1984 sc->bsent++;
1985}
1986
1987
9804b98d
BR		 1988/**
1989 * ath5k_beacon_update_timers - update beacon timers
1990 *
1991 * @sc: struct ath5k_softc pointer we are operating on
1992 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1993 * beacon timer update based on the current HW TSF.
1994 *
1995 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1996 * of a received beacon or the current local hardware TSF and write it to the
1997 * beacon timer registers.
1998 *
1999 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2000 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2001 * when we otherwise know we have to update the timers, but we keep it in this
2002 * function to have it all together in one place.
2003 */
fa1c114f 2004static void
9804b98d 2005ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2006{
2007 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2008 u32 nexttbtt, intval, hw_tu, bc_tu;
2009 u64 hw_tsf;
fa1c114f
JS		 2010
2011 intval = sc->bintval & AR5K_BEACON_PERIOD;
2012 if (WARN_ON(!intval))
2013 return;
2014
9804b98d
BR		 2015 /* beacon TSF converted to TU */
2016 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2017
9804b98d
BR		 2018 /* current TSF converted to TU */
2019 hw_tsf = ath5k_hw_get_tsf64(ah);
2020 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2021
9804b98d
BR		 2022#define FUDGE 3
2023 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2024 if (bc_tsf == -1) {
2025 /*
2026 * no beacons received, called internally.
2027 * just need to refresh timers based on HW TSF.
2028 */
2029 nexttbtt = roundup(hw_tu + FUDGE, intval);
2030 } else if (bc_tsf == 0) {
2031 /*
2032 * no beacon received, probably called by ath5k_reset_tsf().
2033 * reset TSF to start with 0.
2034 */
2035 nexttbtt = intval;
2036 intval |= AR5K_BEACON_RESET_TSF;
2037 } else if (bc_tsf > hw_tsf) {
2038 /*
2039 * beacon received, SW merge happend but HW TSF not yet updated.
2040 * not possible to reconfigure timers yet, but next time we
2041 * receive a beacon with the same BSSID, the hardware will
2042 * automatically update the TSF and then we need to reconfigure
2043 * the timers.
2044 */
2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2046 "need to wait for HW TSF sync\n");
2047 return;
2048 } else {
2049 /*
2050 * most important case for beacon synchronization between STA.
2051 *
2052 * beacon received and HW TSF has been already updated by HW.
2053 * update next TBTT based on the TSF of the beacon, but make
2054 * sure it is ahead of our local TSF timer.
2055 */
2056 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2057 }
2058#undef FUDGE
fa1c114f 2059
036cd1ec
BR		 2060 sc->nexttbtt = nexttbtt;
2061
fa1c114f 2062 intval |= AR5K_BEACON_ENA;
fa1c114f 2063 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2064
2065 /*
2066 * debugging output last in order to preserve the time critical aspect
2067 * of this function
2068 */
2069 if (bc_tsf == -1)
2070 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2071 "reconfigured timers based on HW TSF\n");
2072 else if (bc_tsf == 0)
2073 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2074 "reset HW TSF and timers\n");
2075 else
2076 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2077 "updated timers based on beacon TSF\n");
2078
2079 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2080 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2081 (unsigned long long) bc_tsf,
2082 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2083 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2084 intval & AR5K_BEACON_PERIOD,
2085 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2086 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2087}
2088
2089
036cd1ec
BR		 2090/**
2091 * ath5k_beacon_config - Configure the beacon queues and interrupts
2092 *
2093 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2094 *
2095 * When operating in station mode we want to receive a BMISS interrupt when we
2096 * stop seeing beacons from the AP we've associated with so we can look for
2097 * another AP to associate with.
2098 *
036cd1ec 2099 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2100 * interrupts to detect TSF updates only.
036cd1ec
BR		 2101 *
2102 * AP mode is missing.
fa1c114f
JS		 2103 */
2104static void
2105ath5k_beacon_config(struct ath5k_softc *sc)
2106{
2107 struct ath5k_hw *ah = sc->ah;
2108
2109 ath5k_hw_set_intr(ah, 0);
2110 sc->bmisscount = 0;
dc1968e7 2111 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f
JS		 2112
2113 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2114 sc->imask |= AR5K_INT_BMISS;
2115 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2116 /*
036cd1ec
BR		 2117 * In IBSS mode we use a self-linked tx descriptor and let the
2118 * hardware send the beacons automatically. We have to load it
fa1c114f 2119 * only once here.
036cd1ec 2120 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2121 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2122 */
2123 ath5k_beaconq_config(sc);
fa1c114f 2124
036cd1ec
BR		 2125 sc->imask |= AR5K_INT_SWBA;
2126
2127 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2128 ath5k_beacon_send(sc);
2129 }
2130 /* TODO else AP */
2131
2132 ath5k_hw_set_intr(ah, sc->imask);
2133}
2134
2135
2136/********************\
2137* Interrupt handling *
2138\********************/
2139
2140static int
2141ath5k_init(struct ath5k_softc *sc)
2142{
2143 int ret;
2144
2145 mutex_lock(&sc->lock);
2146
2147 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2148
2149 /*
2150 * Stop anything previously setup. This is safe
2151 * no matter this is the first time through or not.
2152 */
2153 ath5k_stop_locked(sc);
2154
2155 /*
2156 * The basic interface to setting the hardware in a good
2157 * state is ``reset''. On return the hardware is known to
2158 * be powered up and with interrupts disabled. This must
2159 * be followed by initialization of the appropriate bits
2160 * and then setup of the interrupt mask.
2161 */
d8ee398d
LR		 2162 sc->curchan = sc->hw->conf.channel;
2163 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2164 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2165 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2166 AR5K_INT_MIB;
d7dc1003
JS		 2167 ret = ath5k_reset(sc, false, false);
2168 if (ret)
2169 goto done;
fa1c114f 2170
fa1c114f
JS		 2171 /* Set ack to be sent at low bit-rates */
2172 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2173
2174 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2175 msecs_to_jiffies(ath5k_calinterval * 1000)));
2176
2177 ret = 0;
2178done:
274c7c36 2179 mmiowb();
fa1c114f
JS		 2180 mutex_unlock(&sc->lock);
2181 return ret;
2182}
2183
2184static int
2185ath5k_stop_locked(struct ath5k_softc *sc)
2186{
2187 struct ath5k_hw *ah = sc->ah;
2188
2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2190 test_bit(ATH_STAT_INVALID, sc->status));
2191
2192 /*
2193 * Shutdown the hardware and driver:
2194 * stop output from above
2195 * disable interrupts
2196 * turn off timers
2197 * turn off the radio
2198 * clear transmit machinery
2199 * clear receive machinery
2200 * drain and release tx queues
2201 * reclaim beacon resources
2202 * power down hardware
2203 *
2204 * Note that some of this work is not possible if the
2205 * hardware is gone (invalid).
2206 */
2207 ieee80211_stop_queues(sc->hw);
2208
2209 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2210 ath5k_led_off(sc);
fa1c114f 2211 ath5k_hw_set_intr(ah, 0);
274c7c36 2212 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2213 }
2214 ath5k_txq_cleanup(sc);
2215 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2216 ath5k_rx_stop(sc);
2217 ath5k_hw_phy_disable(ah);
2218 } else
2219 sc->rxlink = NULL;
2220
2221 return 0;
2222}
2223
2224/*
2225 * Stop the device, grabbing the top-level lock to protect
2226 * against concurrent entry through ath5k_init (which can happen
2227 * if another thread does a system call and the thread doing the
2228 * stop is preempted).
2229 */
2230static int
2231ath5k_stop_hw(struct ath5k_softc *sc)
2232{
2233 int ret;
2234
2235 mutex_lock(&sc->lock);
2236 ret = ath5k_stop_locked(sc);
2237 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2238 /*
2239 * Set the chip in full sleep mode. Note that we are
2240 * careful to do this only when bringing the interface
2241 * completely to a stop. When the chip is in this state
2242 * it must be carefully woken up or references to
2243 * registers in the PCI clock domain may freeze the bus
2244 * (and system). This varies by chip and is mostly an
2245 * issue with newer parts that go to sleep more quickly.
2246 */
2247 if (sc->ah->ah_mac_srev >= 0x78) {
2248 /*
2249 * XXX
2250 * don't put newer MAC revisions > 7.8 to sleep because
2251 * of the above mentioned problems
2252 */
2253 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2254 "not putting device to sleep\n");
2255 } else {
2256 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2257 "putting device to full sleep\n");
2258 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2259 }
2260 }
2261 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2262 mmiowb();
fa1c114f
JS		 2263 mutex_unlock(&sc->lock);
2264
2265 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2266 tasklet_kill(&sc->rxtq);
2267 tasklet_kill(&sc->txtq);
2268 tasklet_kill(&sc->restq);
fa1c114f
JS		 2269
2270 return ret;
2271}
2272
2273static irqreturn_t
2274ath5k_intr(int irq, void *dev_id)
2275{
2276 struct ath5k_softc *sc = dev_id;
2277 struct ath5k_hw *ah = sc->ah;
2278 enum ath5k_int status;
2279 unsigned int counter = 1000;
2280
2281 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2282 !ath5k_hw_is_intr_pending(ah)))
2283 return IRQ_NONE;
2284
2285 do {
2286 /*
2287 * Figure out the reason(s) for the interrupt. Note
2288 * that get_isr returns a pseudo-ISR that may include
2289 * bits we haven't explicitly enabled so we mask the
2290 * value to insure we only process bits we requested.
2291 */
2292 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2293 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2294 status, sc->imask);
2295 status &= sc->imask; /* discard unasked for bits */
2296 if (unlikely(status & AR5K_INT_FATAL)) {
2297 /*
2298 * Fatal errors are unrecoverable.
2299 * Typically these are caused by DMA errors.
2300 */
2301 tasklet_schedule(&sc->restq);
2302 } else if (unlikely(status & AR5K_INT_RXORN)) {
2303 tasklet_schedule(&sc->restq);
2304 } else {
2305 if (status & AR5K_INT_SWBA) {
2306 /*
2307 * Software beacon alert--time to send a beacon.
2308 * Handle beacon transmission directly; deferring
2309 * this is too slow to meet timing constraints
2310 * under load.
036cd1ec
BR		 2311 *
2312 * In IBSS mode we use this interrupt just to
2313 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2314 * transmission time) in order to detect wether
2315 * automatic TSF updates happened.
fa1c114f 2316 */
036cd1ec
BR		 2317 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2318 /* XXX: only if VEOL suppported */
2319 u64 tsf = ath5k_hw_get_tsf64(ah);
2320 sc->nexttbtt += sc->bintval;
2321 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2322 "SWBA nexttbtt: %x hw_tu: %x "
2323 "TSF: %llx\n",
2324 sc->nexttbtt,
2325 TSF_TO_TU(tsf),
2326 (unsigned long long) tsf);
036cd1ec
BR		 2327 } else {
2328 ath5k_beacon_send(sc);
2329 }
fa1c114f
JS		 2330 }
2331 if (status & AR5K_INT_RXEOL) {
2332 /*
2333 * NB: the hardware should re-read the link when
2334 * RXE bit is written, but it doesn't work at
2335 * least on older hardware revs.
2336 */
2337 sc->rxlink = NULL;
2338 }
2339 if (status & AR5K_INT_TXURN) {
2340 /* bump tx trigger level */
2341 ath5k_hw_update_tx_triglevel(ah, true);
2342 }
2343 if (status & AR5K_INT_RX)
2344 tasklet_schedule(&sc->rxtq);
2345 if (status & AR5K_INT_TX)
2346 tasklet_schedule(&sc->txtq);
2347 if (status & AR5K_INT_BMISS) {
2348 }
2349 if (status & AR5K_INT_MIB) {
194828a2
NK		 2350 /*
2351 * These stats are also used for ANI i think
2352 * so how about updating them more often ?
2353 */
2354 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2355 }
2356 }
2357 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2358
2359 if (unlikely(!counter))
2360 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2361
2362 return IRQ_HANDLED;
2363}
2364
2365static void
2366ath5k_tasklet_reset(unsigned long data)
2367{
2368 struct ath5k_softc *sc = (void *)data;
2369
d7dc1003 2370 ath5k_reset_wake(sc);
fa1c114f
JS		 2371}
2372
2373/*
2374 * Periodically recalibrate the PHY to account
2375 * for temperature/environment changes.
2376 */
2377static void
2378ath5k_calibrate(unsigned long data)
2379{
2380 struct ath5k_softc *sc = (void *)data;
2381 struct ath5k_hw *ah = sc->ah;
2382
2383 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2384 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2385 sc->curchan->hw_value);
fa1c114f
JS		 2386
2387 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2388 /*
2389 * Rfgain is out of bounds, reset the chip
2390 * to load new gain values.
2391 */
2392 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2393 ath5k_reset_wake(sc);
fa1c114f
JS		 2394 }
2395 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2396 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2397 ieee80211_frequency_to_channel(
2398 sc->curchan->center_freq));
fa1c114f
JS		 2399
2400 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2401 msecs_to_jiffies(ath5k_calinterval * 1000)));
2402}
2403
2404
2405
2406/***************\
2407* LED functions *
2408\***************/
2409
2410static void
3a078876 2411ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2412{
3a078876
BC		 2413 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2414 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2415 ath5k_led_off(sc);
fa1c114f
JS		 2416 }
2417}
2418
fa1c114f 2419static void
3a078876 2420ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2421{
3a078876
BC		 2422 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2423 return;
fa1c114f 2424 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2425}
2426
2427static void
3a078876 2428ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2429{
3a078876 2430 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2431 return;
3a078876
BC		 2432 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2433}
2434
2435static void
2436ath5k_led_brightness_set(struct led_classdev *led_dev,
2437 enum led_brightness brightness)
2438{
2439 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2440 led_dev);
2441
2442 if (brightness == LED_OFF)
2443 ath5k_led_off(led->sc);
2444 else
2445 ath5k_led_on(led->sc);
2446}
2447
2448static int
2449ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2450 const char *name, char *trigger)
2451{
2452 int err;
2453
2454 led->sc = sc;
2455 strncpy(led->name, name, sizeof(led->name));
2456 led->led_dev.name = led->name;
2457 led->led_dev.default_trigger = trigger;
2458 led->led_dev.brightness_set = ath5k_led_brightness_set;
2459
2460 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2461 if (err)
2462 {
2463 ATH5K_WARN(sc, "could not register LED %s\n", name);
2464 led->sc = NULL;
fa1c114f 2465 }
3a078876 2466 return err;
fa1c114f
JS		 2467}
2468
3a078876
BC		 2469static void
2470ath5k_unregister_led(struct ath5k_led *led)
2471{
2472 if (!led->sc)
2473 return;
2474 led_classdev_unregister(&led->led_dev);
2475 ath5k_led_off(led->sc);
2476 led->sc = NULL;
2477}
2478
2479static void
2480ath5k_unregister_leds(struct ath5k_softc *sc)
2481{
2482 ath5k_unregister_led(&sc->rx_led);
2483 ath5k_unregister_led(&sc->tx_led);
2484}
2485
2486
2487static int
2488ath5k_init_leds(struct ath5k_softc *sc)
2489{
2490 int ret = 0;
2491 struct ieee80211_hw *hw = sc->hw;
2492 struct pci_dev *pdev = sc->pdev;
2493 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2494
3a078876
BC		 2495 /*
2496 * Auto-enable soft led processing for IBM cards and for
2497 * 5211 minipci cards.
2498 */
2499 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2500 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2501 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2502 sc->led_pin = 0;
734b5aa9 2503 sc->led_on = 0; /* active low */
3a078876
BC		 2504 }
2505 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2506 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2507 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2508 sc->led_pin = 1;
734b5aa9 2509 sc->led_on = 1; /* active high */
3a078876
BC		 2510 }
2511 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2512 goto out;
2513
2514 ath5k_led_enable(sc);
2515
2516 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2517 ret = ath5k_register_led(sc, &sc->rx_led, name,
2518 ieee80211_get_rx_led_name(hw));
2519 if (ret)
2520 goto out;
2521
2522 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2523 ret = ath5k_register_led(sc, &sc->tx_led, name,
2524 ieee80211_get_tx_led_name(hw));
2525out:
2526 return ret;
2527}
fa1c114f
JS		 2528
2529
2530/********************\
2531* Mac80211 functions *
2532\********************/
2533
2534static int
e039fa4a 2535ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2536{
2537 struct ath5k_softc *sc = hw->priv;
2538 struct ath5k_buf *bf;
2539 unsigned long flags;
2540 int hdrlen;
2541 int pad;
2542
2543 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2544
2545 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2546 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2547
2548 /*
2549 * the hardware expects the header padded to 4 byte boundaries
2550 * if this is not the case we add the padding after the header
2551 */
2552 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2553 if (hdrlen & 3) {
2554 pad = hdrlen % 4;
2555 if (skb_headroom(skb) < pad) {
2556 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2557 " headroom to pad %d\n", hdrlen, pad);
2558 return -1;
2559 }
2560 skb_push(skb, pad);
2561 memmove(skb->data, skb->data+pad, hdrlen);
2562 }
2563
fa1c114f
JS		 2564 spin_lock_irqsave(&sc->txbuflock, flags);
2565 if (list_empty(&sc->txbuf)) {
2566 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2567 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2568 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2569 return -1;
2570 }
2571 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2572 list_del(&bf->list);
2573 sc->txbuf_len--;
2574 if (list_empty(&sc->txbuf))
2575 ieee80211_stop_queues(hw);
2576 spin_unlock_irqrestore(&sc->txbuflock, flags);
2577
2578 bf->skb = skb;
2579
e039fa4a 2580 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2581 bf->skb = NULL;
2582 spin_lock_irqsave(&sc->txbuflock, flags);
2583 list_add_tail(&bf->list, &sc->txbuf);
2584 sc->txbuf_len++;
2585 spin_unlock_irqrestore(&sc->txbuflock, flags);
2586 dev_kfree_skb_any(skb);
2587 return 0;
2588 }
2589
2590 return 0;
2591}
2592
2593static int
d7dc1003 2594ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2595{
fa1c114f
JS		 2596 struct ath5k_hw *ah = sc->ah;
2597 int ret;
2598
2599 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2600
d7dc1003
JS		 2601 if (stop) {
2602 ath5k_hw_set_intr(ah, 0);
2603 ath5k_txq_cleanup(sc);
2604 ath5k_rx_stop(sc);
2605 }
fa1c114f 2606 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2607 if (ret) {
fa1c114f
JS		 2608 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2609 goto err;
2610 }
d7dc1003
JS		 2611
2612 /*
2613 * This is needed only to setup initial state
2614 * but it's best done after a reset.
2615 */
fa1c114f
JS		 2616 ath5k_hw_set_txpower_limit(sc->ah, 0);
2617
2618 ret = ath5k_rx_start(sc);
d7dc1003 2619 if (ret) {
fa1c114f
JS		 2620 ATH5K_ERR(sc, "can't start recv logic\n");
2621 goto err;
2622 }
d7dc1003 2623
fa1c114f 2624 /*
d7dc1003
JS		 2625 * Change channels and update the h/w rate map if we're switching;
2626 * e.g. 11a to 11b/g.
2627 *
2628 * We may be doing a reset in response to an ioctl that changes the
2629 * channel so update any state that might change as a result.
fa1c114f
JS		 2630 *
2631 * XXX needed?
2632 */
2633/* ath5k_chan_change(sc, c); */
fa1c114f 2634
d7dc1003
JS		 2635 ath5k_beacon_config(sc);
2636 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2637
2638 return 0;
2639err:
2640 return ret;
2641}
2642
d7dc1003
JS		 2643static int
2644ath5k_reset_wake(struct ath5k_softc *sc)
2645{
2646 int ret;
2647
2648 ret = ath5k_reset(sc, true, true);
2649 if (!ret)
2650 ieee80211_wake_queues(sc->hw);
2651
2652 return ret;
2653}
2654
fa1c114f
JS		 2655static int ath5k_start(struct ieee80211_hw *hw)
2656{
2657 return ath5k_init(hw->priv);
2658}
2659
2660static void ath5k_stop(struct ieee80211_hw *hw)
2661{
2662 ath5k_stop_hw(hw->priv);
2663}
2664
2665static int ath5k_add_interface(struct ieee80211_hw *hw,
2666 struct ieee80211_if_init_conf *conf)
2667{
2668 struct ath5k_softc *sc = hw->priv;
2669 int ret;
2670
2671 mutex_lock(&sc->lock);
32bfd35d 2672 if (sc->vif) {
fa1c114f
JS		 2673 ret = 0;
2674 goto end;
2675 }
2676
32bfd35d 2677 sc->vif = conf->vif;
fa1c114f
JS		 2678
2679 switch (conf->type) {
2680 case IEEE80211_IF_TYPE_STA:
2681 case IEEE80211_IF_TYPE_IBSS:
2682 case IEEE80211_IF_TYPE_MNTR:
2683 sc->opmode = conf->type;
2684 break;
2685 default:
2686 ret = -EOPNOTSUPP;
2687 goto end;
2688 }
2689 ret = 0;
2690end:
2691 mutex_unlock(&sc->lock);
2692 return ret;
2693}
2694
2695static void
2696ath5k_remove_interface(struct ieee80211_hw *hw,
2697 struct ieee80211_if_init_conf *conf)
2698{
2699 struct ath5k_softc *sc = hw->priv;
2700
2701 mutex_lock(&sc->lock);
32bfd35d 2702 if (sc->vif != conf->vif)
fa1c114f
JS		 2703 goto end;
2704
32bfd35d 2705 sc->vif = NULL;
fa1c114f
JS		 2706end:
2707 mutex_unlock(&sc->lock);
2708}
2709
d8ee398d
LR		 2710/*
2711 * TODO: Phy disable/diversity etc
2712 */
fa1c114f
JS		 2713static int
2714ath5k_config(struct ieee80211_hw *hw,
2715 struct ieee80211_conf *conf)
2716{
2717 struct ath5k_softc *sc = hw->priv;
2718
e535c1ac 2719 sc->bintval = conf->beacon_int;
d8ee398d 2720 sc->power_level = conf->power_level;
fa1c114f 2721
d8ee398d 2722 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2723}
2724
2725static int
32bfd35d 2726ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2727 struct ieee80211_if_conf *conf)
2728{
2729 struct ath5k_softc *sc = hw->priv;
2730 struct ath5k_hw *ah = sc->ah;
2731 int ret;
2732
2733 /* Set to a reasonable value. Note that this will
2734 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2735 sc->bintval = 1000;
fa1c114f 2736 mutex_lock(&sc->lock);
32bfd35d 2737 if (sc->vif != vif) {
fa1c114f
JS		 2738 ret = -EIO;
2739 goto unlock;
2740 }
2741 if (conf->bssid) {
2742 /* Cache for later use during resets */
2743 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2744 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2745 * a clean way of letting us retrieve this yet. */
2746 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2747 mmiowb();
fa1c114f 2748 }
9d139c81
JB		 2749
2750 if (conf->changed & IEEE80211_IFCC_BEACON &&
2751 vif->type == IEEE80211_IF_TYPE_IBSS) {
2752 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2753 if (!beacon) {
2754 ret = -ENOMEM;
2755 goto unlock;
2756 }
2757 /* call old handler for now */
2758 ath5k_beacon_update(hw, beacon);
2759 }
2760
fa1c114f
JS		 2761 mutex_unlock(&sc->lock);
2762
d7dc1003 2763 return ath5k_reset_wake(sc);
fa1c114f
JS		 2764unlock:
2765 mutex_unlock(&sc->lock);
2766 return ret;
2767}
2768
2769#define SUPPORTED_FIF_FLAGS \
2770 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2771 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2772 FIF_BCN_PRBRESP_PROMISC
2773/*
2774 * o always accept unicast, broadcast, and multicast traffic
2775 * o multicast traffic for all BSSIDs will be enabled if mac80211
2776 * says it should be
2777 * o maintain current state of phy ofdm or phy cck error reception.
2778 * If the hardware detects any of these type of errors then
2779 * ath5k_hw_get_rx_filter() will pass to us the respective
2780 * hardware filters to be able to receive these type of frames.
2781 * o probe request frames are accepted only when operating in
2782 * hostap, adhoc, or monitor modes
2783 * o enable promiscuous mode according to the interface state
2784 * o accept beacons:
2785 * - when operating in adhoc mode so the 802.11 layer creates
2786 * node table entries for peers,
2787 * - when operating in station mode for collecting rssi data when
2788 * the station is otherwise quiet, or
2789 * - when scanning
2790 */
2791static void ath5k_configure_filter(struct ieee80211_hw *hw,
2792 unsigned int changed_flags,
2793 unsigned int *new_flags,
2794 int mc_count, struct dev_mc_list *mclist)
2795{
2796 struct ath5k_softc *sc = hw->priv;
2797 struct ath5k_hw *ah = sc->ah;
2798 u32 mfilt[2], val, rfilt;
2799 u8 pos;
2800 int i;
2801
2802 mfilt[0] = 0;
2803 mfilt[1] = 0;
2804
2805 /* Only deal with supported flags */
2806 changed_flags &= SUPPORTED_FIF_FLAGS;
2807 *new_flags &= SUPPORTED_FIF_FLAGS;
2808
2809 /* If HW detects any phy or radar errors, leave those filters on.
2810 * Also, always enable Unicast, Broadcasts and Multicast
2811 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2812 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2813 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2814 AR5K_RX_FILTER_MCAST);
2815
2816 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2817 if (*new_flags & FIF_PROMISC_IN_BSS) {
2818 rfilt |= AR5K_RX_FILTER_PROM;
2819 __set_bit(ATH_STAT_PROMISC, sc->status);
2820 }
2821 else
2822 __clear_bit(ATH_STAT_PROMISC, sc->status);
2823 }
2824
2825 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2826 if (*new_flags & FIF_ALLMULTI) {
2827 mfilt[0] = ~0;
2828 mfilt[1] = ~0;
2829 } else {
2830 for (i = 0; i < mc_count; i++) {
2831 if (!mclist)
2832 break;
2833 /* calculate XOR of eight 6-bit values */
533dd1b0 2834 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2835 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2836 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2837 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2838 pos &= 0x3f;
2839 mfilt[pos / 32] |= (1 << (pos % 32));
2840 /* XXX: we might be able to just do this instead,
2841 * but not sure, needs testing, if we do use this we'd
2842 * neet to inform below to not reset the mcast */
2843 /* ath5k_hw_set_mcast_filterindex(ah,
2844 * mclist->dmi_addr[5]); */
2845 mclist = mclist->next;
2846 }
2847 }
2848
2849 /* This is the best we can do */
2850 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2851 rfilt |= AR5K_RX_FILTER_PHYERR;
2852
2853 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2854 * and probes for any BSSID, this needs testing */
2855 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2856 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2857
2858 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2859 * set we should only pass on control frames for this
2860 * station. This needs testing. I believe right now this
2861 * enables *all* control frames, which is OK.. but
2862 * but we should see if we can improve on granularity */
2863 if (*new_flags & FIF_CONTROL)
2864 rfilt |= AR5K_RX_FILTER_CONTROL;
2865
2866 /* Additional settings per mode -- this is per ath5k */
2867
2868 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2869
2870 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2871 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2872 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2873 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2874 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2875 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
8e5f3d0a 2876 sc->opmode != IEEE80211_IF_TYPE_MESH_POINT &&
fa1c114f
JS		 2877 test_bit(ATH_STAT_PROMISC, sc->status))
2878 rfilt |= AR5K_RX_FILTER_PROM;
2879 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2880 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2881 rfilt |= AR5K_RX_FILTER_BEACON;
2882 }
2883
2884 /* Set filters */
2885 ath5k_hw_set_rx_filter(ah,rfilt);
2886
2887 /* Set multicast bits */
2888 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2889 /* Set the cached hw filter flags, this will alter actually
2890 * be set in HW */
2891 sc->filter_flags = rfilt;
2892}
2893
2894static int
2895ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2896 const u8 *local_addr, const u8 *addr,
2897 struct ieee80211_key_conf *key)
2898{
2899 struct ath5k_softc *sc = hw->priv;
2900 int ret = 0;
2901
2902 switch(key->alg) {
2903 case ALG_WEP:
6844e63a
LR		 2904 /* XXX: fix hardware encryption, its not working. For now
2905 * allow software encryption */
2906 /* break; */
fa1c114f
JS		 2907 case ALG_TKIP:
2908 case ALG_CCMP:
2909 return -EOPNOTSUPP;
2910 default:
2911 WARN_ON(1);
2912 return -EINVAL;
2913 }
2914
2915 mutex_lock(&sc->lock);
2916
2917 switch (cmd) {
2918 case SET_KEY:
2919 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2920 if (ret) {
2921 ATH5K_ERR(sc, "can't set the key\n");
2922 goto unlock;
2923 }
2924 __set_bit(key->keyidx, sc->keymap);
2925 key->hw_key_idx = key->keyidx;
2926 break;
2927 case DISABLE_KEY:
2928 ath5k_hw_reset_key(sc->ah, key->keyidx);
2929 __clear_bit(key->keyidx, sc->keymap);
2930 break;
2931 default:
2932 ret = -EINVAL;
2933 goto unlock;
2934 }
2935
2936unlock:
274c7c36 2937 mmiowb();
fa1c114f
JS		 2938 mutex_unlock(&sc->lock);
2939 return ret;
2940}
2941
2942static int
2943ath5k_get_stats(struct ieee80211_hw *hw,
2944 struct ieee80211_low_level_stats *stats)
2945{
2946 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2947 struct ath5k_hw *ah = sc->ah;
2948
2949 /* Force update */
2950 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2951
2952 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2953
2954 return 0;
2955}
2956
2957static int
2958ath5k_get_tx_stats(struct ieee80211_hw *hw,
2959 struct ieee80211_tx_queue_stats *stats)
2960{
2961 struct ath5k_softc *sc = hw->priv;
2962
2963 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2964
2965 return 0;
2966}
2967
2968static u64
2969ath5k_get_tsf(struct ieee80211_hw *hw)
2970{
2971 struct ath5k_softc *sc = hw->priv;
2972
2973 return ath5k_hw_get_tsf64(sc->ah);
2974}
2975
2976static void
2977ath5k_reset_tsf(struct ieee80211_hw *hw)
2978{
2979 struct ath5k_softc *sc = hw->priv;
2980
9804b98d
BR		 2981 /*
2982 * in IBSS mode we need to update the beacon timers too.
2983 * this will also reset the TSF if we call it with 0
2984 */
2985 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2986 ath5k_beacon_update_timers(sc, 0);
2987 else
2988 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 2989}
2990
2991static int
e039fa4a 2992ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2993{
2994 struct ath5k_softc *sc = hw->priv;
2995 int ret;
2996
2997 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2998
fa1c114f
JS		 2999 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3000 ret = -EIO;
3001 goto end;
3002 }
3003
3004 ath5k_txbuf_free(sc, sc->bbuf);
3005 sc->bbuf->skb = skb;
e039fa4a 3006 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3007 if (ret)
3008 sc->bbuf->skb = NULL;
274c7c36 3009 else {
fa1c114f 3010 ath5k_beacon_config(sc);
274c7c36
JS		 3011 mmiowb();
3012 }
fa1c114f
JS		 3013
3014end:
fa1c114f
JS		 3015 return ret;
3016}
3017
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