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ath5k: Fix SREV reporting after SREV updates
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
63266a65
BR		 141static struct ieee80211_rate ath5k_rates[] = {
142 { .bitrate = 10,
143 .hw_value = ATH5K_RATE_CODE_1M, },
144 { .bitrate = 20,
145 .hw_value = ATH5K_RATE_CODE_2M,
146 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 55,
149 .hw_value = ATH5K_RATE_CODE_5_5M,
150 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 110,
153 .hw_value = ATH5K_RATE_CODE_11M,
154 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 60,
157 .hw_value = ATH5K_RATE_CODE_6M,
158 .flags = 0 },
159 { .bitrate = 90,
160 .hw_value = ATH5K_RATE_CODE_9M,
161 .flags = 0 },
162 { .bitrate = 120,
163 .hw_value = ATH5K_RATE_CODE_12M,
164 .flags = 0 },
165 { .bitrate = 180,
166 .hw_value = ATH5K_RATE_CODE_18M,
167 .flags = 0 },
168 { .bitrate = 240,
169 .hw_value = ATH5K_RATE_CODE_24M,
170 .flags = 0 },
171 { .bitrate = 360,
172 .hw_value = ATH5K_RATE_CODE_36M,
173 .flags = 0 },
174 { .bitrate = 480,
175 .hw_value = ATH5K_RATE_CODE_48M,
176 .flags = 0 },
177 { .bitrate = 540,
178 .hw_value = ATH5K_RATE_CODE_54M,
179 .flags = 0 },
180 /* XR missing */
181};
182
fa1c114f
JS		 183/*
184 * Prototypes - PCI stack related functions
185 */
186static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
187 const struct pci_device_id *id);
188static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
189#ifdef CONFIG_PM
190static int ath5k_pci_suspend(struct pci_dev *pdev,
191 pm_message_t state);
192static int ath5k_pci_resume(struct pci_dev *pdev);
193#else
194#define ath5k_pci_suspend NULL
195#define ath5k_pci_resume NULL
196#endif /* CONFIG_PM */
197
04a9e451 198static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 199 .name = "ath5k_pci",
200 .id_table = ath5k_pci_id_table,
201 .probe = ath5k_pci_probe,
202 .remove = __devexit_p(ath5k_pci_remove),
203 .suspend = ath5k_pci_suspend,
204 .resume = ath5k_pci_resume,
205};
206
207
208
209/*
210 * Prototypes - MAC 802.11 stack related functions
211 */
e039fa4a 212static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 213static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
214static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 215static int ath5k_start(struct ieee80211_hw *hw);
216static void ath5k_stop(struct ieee80211_hw *hw);
217static int ath5k_add_interface(struct ieee80211_hw *hw,
218 struct ieee80211_if_init_conf *conf);
219static void ath5k_remove_interface(struct ieee80211_hw *hw,
220 struct ieee80211_if_init_conf *conf);
221static int ath5k_config(struct ieee80211_hw *hw,
222 struct ieee80211_conf *conf);
32bfd35d
JB		 223static int ath5k_config_interface(struct ieee80211_hw *hw,
224 struct ieee80211_vif *vif,
fa1c114f
JS		 225 struct ieee80211_if_conf *conf);
226static void ath5k_configure_filter(struct ieee80211_hw *hw,
227 unsigned int changed_flags,
228 unsigned int *new_flags,
229 int mc_count, struct dev_mc_list *mclist);
230static int ath5k_set_key(struct ieee80211_hw *hw,
231 enum set_key_cmd cmd,
232 const u8 *local_addr, const u8 *addr,
233 struct ieee80211_key_conf *key);
234static int ath5k_get_stats(struct ieee80211_hw *hw,
235 struct ieee80211_low_level_stats *stats);
236static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
237 struct ieee80211_tx_queue_stats *stats);
238static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
239static void ath5k_reset_tsf(struct ieee80211_hw *hw);
240static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 241 struct sk_buff *skb);
fa1c114f
JS		 242
243static struct ieee80211_ops ath5k_hw_ops = {
244 .tx = ath5k_tx,
245 .start = ath5k_start,
246 .stop = ath5k_stop,
247 .add_interface = ath5k_add_interface,
248 .remove_interface = ath5k_remove_interface,
249 .config = ath5k_config,
250 .config_interface = ath5k_config_interface,
251 .configure_filter = ath5k_configure_filter,
252 .set_key = ath5k_set_key,
253 .get_stats = ath5k_get_stats,
254 .conf_tx = NULL,
255 .get_tx_stats = ath5k_get_tx_stats,
256 .get_tsf = ath5k_get_tsf,
257 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 258};
259
260/*
261 * Prototypes - Internal functions
262 */
263/* Attach detach */
264static int ath5k_attach(struct pci_dev *pdev,
265 struct ieee80211_hw *hw);
266static void ath5k_detach(struct pci_dev *pdev,
267 struct ieee80211_hw *hw);
268/* Channel/mode setup */
269static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 270static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
271 struct ieee80211_channel *channels,
272 unsigned int mode,
273 unsigned int max);
63266a65 274static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 275static int ath5k_chan_set(struct ath5k_softc *sc,
276 struct ieee80211_channel *chan);
277static void ath5k_setcurmode(struct ath5k_softc *sc,
278 unsigned int mode);
279static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 280
fa1c114f
JS		 281/* Descriptor setup */
282static int ath5k_desc_alloc(struct ath5k_softc *sc,
283 struct pci_dev *pdev);
284static void ath5k_desc_free(struct ath5k_softc *sc,
285 struct pci_dev *pdev);
286/* Buffers setup */
287static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
288 struct ath5k_buf *bf);
289static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 290 struct ath5k_buf *bf);
fa1c114f
JS		 291static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
292 struct ath5k_buf *bf)
293{
294 BUG_ON(!bf);
295 if (!bf->skb)
296 return;
297 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
298 PCI_DMA_TODEVICE);
00482973 299 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 300 bf->skb = NULL;
301}
302
303/* Queues setup */
304static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
305 int qtype, int subtype);
306static int ath5k_beaconq_setup(struct ath5k_hw *ah);
307static int ath5k_beaconq_config(struct ath5k_softc *sc);
308static void ath5k_txq_drainq(struct ath5k_softc *sc,
309 struct ath5k_txq *txq);
310static void ath5k_txq_cleanup(struct ath5k_softc *sc);
311static void ath5k_txq_release(struct ath5k_softc *sc);
312/* Rx handling */
313static int ath5k_rx_start(struct ath5k_softc *sc);
314static void ath5k_rx_stop(struct ath5k_softc *sc);
315static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
316 struct ath5k_desc *ds,
b47f407b
BR		 317 struct sk_buff *skb,
318 struct ath5k_rx_status *rs);
fa1c114f
JS		 319static void ath5k_tasklet_rx(unsigned long data);
320/* Tx handling */
321static void ath5k_tx_processq(struct ath5k_softc *sc,
322 struct ath5k_txq *txq);
323static void ath5k_tasklet_tx(unsigned long data);
324/* Beacon handling */
325static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 326 struct ath5k_buf *bf);
fa1c114f
JS		 327static void ath5k_beacon_send(struct ath5k_softc *sc);
328static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 329static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 330
331static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
332{
333 u64 tsf = ath5k_hw_get_tsf64(ah);
334
335 if ((tsf & 0x7fff) < rstamp)
336 tsf -= 0x8000;
337
338 return (tsf & ~0x7fff) | rstamp;
339}
340
341/* Interrupt handling */
342static int ath5k_init(struct ath5k_softc *sc);
343static int ath5k_stop_locked(struct ath5k_softc *sc);
344static int ath5k_stop_hw(struct ath5k_softc *sc);
345static irqreturn_t ath5k_intr(int irq, void *dev_id);
346static void ath5k_tasklet_reset(unsigned long data);
347
348static void ath5k_calibrate(unsigned long data);
349/* LED functions */
3a078876
BC		 350static int ath5k_init_leds(struct ath5k_softc *sc);
351static void ath5k_led_enable(struct ath5k_softc *sc);
352static void ath5k_led_off(struct ath5k_softc *sc);
353static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 354
355/*
356 * Module init/exit functions
357 */
358static int __init
359init_ath5k_pci(void)
360{
361 int ret;
362
363 ath5k_debug_init();
364
04a9e451 365 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 366 if (ret) {
367 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
368 return ret;
369 }
370
371 return 0;
372}
373
374static void __exit
375exit_ath5k_pci(void)
376{
04a9e451 377 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 378
379 ath5k_debug_finish();
380}
381
382module_init(init_ath5k_pci);
383module_exit(exit_ath5k_pci);
384
385
386/********************\
387* PCI Initialization *
388\********************/
389
390static const char *
391ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
392{
393 const char *name = "xxxxx";
394 unsigned int i;
395
396 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
397 if (srev_names[i].sr_type != type)
398 continue;
75d0edb8
NK		 399
400 if ((val & 0xf0) == srev_names[i].sr_val)
401 name = srev_names[i].sr_name;
402
403 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 404 name = srev_names[i].sr_name;
405 break;
406 }
407 }
408
409 return name;
410}
411
412static int __devinit
413ath5k_pci_probe(struct pci_dev *pdev,
414 const struct pci_device_id *id)
415{
416 void __iomem *mem;
417 struct ath5k_softc *sc;
418 struct ieee80211_hw *hw;
419 int ret;
420 u8 csz;
421
422 ret = pci_enable_device(pdev);
423 if (ret) {
424 dev_err(&pdev->dev, "can't enable device\n");
425 goto err;
426 }
427
428 /* XXX 32-bit addressing only */
429 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
430 if (ret) {
431 dev_err(&pdev->dev, "32-bit DMA not available\n");
432 goto err_dis;
433 }
434
435 /*
436 * Cache line size is used to size and align various
437 * structures used to communicate with the hardware.
438 */
439 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
440 if (csz == 0) {
441 /*
442 * Linux 2.4.18 (at least) writes the cache line size
443 * register as a 16-bit wide register which is wrong.
444 * We must have this setup properly for rx buffer
445 * DMA to work so force a reasonable value here if it
446 * comes up zero.
447 */
448 csz = L1_CACHE_BYTES / sizeof(u32);
449 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
450 }
451 /*
452 * The default setting of latency timer yields poor results,
453 * set it to the value used by other systems. It may be worth
454 * tweaking this setting more.
455 */
456 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
457
458 /* Enable bus mastering */
459 pci_set_master(pdev);
460
461 /*
462 * Disable the RETRY_TIMEOUT register (0x41) to keep
463 * PCI Tx retries from interfering with C3 CPU state.
464 */
465 pci_write_config_byte(pdev, 0x41, 0);
466
467 ret = pci_request_region(pdev, 0, "ath5k");
468 if (ret) {
469 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
470 goto err_dis;
471 }
472
473 mem = pci_iomap(pdev, 0, 0);
474 if (!mem) {
475 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
476 ret = -EIO;
477 goto err_reg;
478 }
479
480 /*
481 * Allocate hw (mac80211 main struct)
482 * and hw->priv (driver private data)
483 */
484 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
485 if (hw == NULL) {
486 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
487 ret = -ENOMEM;
488 goto err_map;
489 }
490
491 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
492
493 /* Initialize driver private data */
494 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 495 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
496 IEEE80211_HW_SIGNAL_DBM |
497 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 498
499 hw->wiphy->interface_modes =
500 BIT(NL80211_IFTYPE_STATION) |
501 BIT(NL80211_IFTYPE_ADHOC) |
502 BIT(NL80211_IFTYPE_MESH_POINT);
503
fa1c114f
JS		 504 hw->extra_tx_headroom = 2;
505 hw->channel_change_time = 5000;
fa1c114f
JS		 506 sc = hw->priv;
507 sc->hw = hw;
508 sc->pdev = pdev;
509
510 ath5k_debug_init_device(sc);
511
512 /*
513 * Mark the device as detached to avoid processing
514 * interrupts until setup is complete.
515 */
516 __set_bit(ATH_STAT_INVALID, sc->status);
517
518 sc->iobase = mem; /* So we can unmap it on detach */
519 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 520 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 521 mutex_init(&sc->lock);
522 spin_lock_init(&sc->rxbuflock);
523 spin_lock_init(&sc->txbuflock);
00482973 524 spin_lock_init(&sc->block);
fa1c114f
JS		 525
526 /* Set private data */
527 pci_set_drvdata(pdev, hw);
528
fa1c114f
JS		 529 /* Setup interrupt handler */
530 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
531 if (ret) {
532 ATH5K_ERR(sc, "request_irq failed\n");
533 goto err_free;
534 }
535
536 /* Initialize device */
537 sc->ah = ath5k_hw_attach(sc, id->driver_data);
538 if (IS_ERR(sc->ah)) {
539 ret = PTR_ERR(sc->ah);
540 goto err_irq;
541 }
542
543 /* Finish private driver data initialization */
544 ret = ath5k_attach(pdev, hw);
545 if (ret)
546 goto err_ah;
547
548 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 549 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 550 sc->ah->ah_mac_srev,
551 sc->ah->ah_phy_revision);
552
400ec45a 553 if (!sc->ah->ah_single_chip) {
fa1c114f 554 /* Single chip radio (!RF5111) */
400ec45a
LR		 555 if (sc->ah->ah_radio_5ghz_revision &&
556 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 557 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 558 if (!test_bit(AR5K_MODE_11A,
559 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 560 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 561 ath5k_chip_name(AR5K_VERSION_RAD,
562 sc->ah->ah_radio_5ghz_revision),
563 sc->ah->ah_radio_5ghz_revision);
564 /* No 2GHz support (5110 and some
565 * 5Ghz only cards) -> report 5Ghz radio */
566 } else if (!test_bit(AR5K_MODE_11B,
567 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 568 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 569 ath5k_chip_name(AR5K_VERSION_RAD,
570 sc->ah->ah_radio_5ghz_revision),
571 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 572 /* Multiband radio */
573 } else {
574 ATH5K_INFO(sc, "RF%s multiband radio found"
575 " (0x%x)\n",
400ec45a
LR		 576 ath5k_chip_name(AR5K_VERSION_RAD,
577 sc->ah->ah_radio_5ghz_revision),
578 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 579 }
580 }
400ec45a
LR		 581 /* Multi chip radio (RF5111 - RF2111) ->
582 * report both 2GHz/5GHz radios */
583 else if (sc->ah->ah_radio_5ghz_revision &&
584 sc->ah->ah_radio_2ghz_revision){
fa1c114f 585 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_5ghz_revision),
588 sc->ah->ah_radio_5ghz_revision);
fa1c114f 589 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_2ghz_revision),
592 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 593 }
594 }
595
596
597 /* ready to process interrupts */
598 __clear_bit(ATH_STAT_INVALID, sc->status);
599
600 return 0;
601err_ah:
602 ath5k_hw_detach(sc->ah);
603err_irq:
604 free_irq(pdev->irq, sc);
605err_free:
fa1c114f
JS		 606 ieee80211_free_hw(hw);
607err_map:
608 pci_iounmap(pdev, mem);
609err_reg:
610 pci_release_region(pdev, 0);
611err_dis:
612 pci_disable_device(pdev);
613err:
614 return ret;
615}
616
617static void __devexit
618ath5k_pci_remove(struct pci_dev *pdev)
619{
620 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
621 struct ath5k_softc *sc = hw->priv;
622
623 ath5k_debug_finish_device(sc);
624 ath5k_detach(pdev, hw);
625 ath5k_hw_detach(sc->ah);
626 free_irq(pdev->irq, sc);
fa1c114f
JS		 627 pci_iounmap(pdev, sc->iobase);
628 pci_release_region(pdev, 0);
629 pci_disable_device(pdev);
630 ieee80211_free_hw(hw);
631}
632
633#ifdef CONFIG_PM
634static int
635ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
636{
637 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
638 struct ath5k_softc *sc = hw->priv;
639
3a078876 640 ath5k_led_off(sc);
fa1c114f
JS		 641
642 ath5k_stop_hw(sc);
3e4242b9
JS		 643
644 free_irq(pdev->irq, sc);
fa1c114f
JS		 645 pci_save_state(pdev);
646 pci_disable_device(pdev);
647 pci_set_power_state(pdev, PCI_D3hot);
648
649 return 0;
650}
651
652static int
653ath5k_pci_resume(struct pci_dev *pdev)
654{
655 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
656 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 657 struct ath5k_hw *ah = sc->ah;
658 int i, err;
fa1c114f 659
3e4242b9 660 pci_restore_state(pdev);
fa1c114f
JS		 661
662 err = pci_enable_device(pdev);
663 if (err)
664 return err;
665
fa1c114f
JS		 666 /*
667 * Suspend/Resume resets the PCI configuration space, so we have to
668 * re-disable the RETRY_TIMEOUT register (0x41) to keep
669 * PCI Tx retries from interfering with C3 CPU state
670 */
671 pci_write_config_byte(pdev, 0x41, 0);
672
3e4242b9
JS		 673 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
674 if (err) {
675 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 676 goto err_no_irq;
3e4242b9
JS		 677 }
678
679 err = ath5k_init(sc);
680 if (err)
681 goto err_irq;
3a078876 682 ath5k_led_enable(sc);
fa1c114f 683
247ae449
JL		 684 /*
685 * Reset the key cache since some parts do not
686 * reset the contents on initial power up or resume.
687 *
688 * FIXME: This may need to be revisited when mac80211 becomes
689 * aware of suspend/resume.
690 */
691 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
692 ath5k_hw_reset_key(ah, i);
693
fa1c114f 694 return 0;
3e4242b9
JS		 695err_irq:
696 free_irq(pdev->irq, sc);
37465c8a 697err_no_irq:
3e4242b9
JS		 698 pci_disable_device(pdev);
699 return err;
fa1c114f
JS		 700}
701#endif /* CONFIG_PM */
702
703
fa1c114f
JS		 704/***********************\
705* Driver Initialization *
706\***********************/
707
708static int
709ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
710{
711 struct ath5k_softc *sc = hw->priv;
712 struct ath5k_hw *ah = sc->ah;
713 u8 mac[ETH_ALEN];
714 unsigned int i;
715 int ret;
716
717 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
718
719 /*
720 * Check if the MAC has multi-rate retry support.
721 * We do this by trying to setup a fake extended
722 * descriptor. MAC's that don't have support will
723 * return false w/o doing anything. MAC's that do
724 * support it will return true w/o doing anything.
725 */
c6e387a2 726 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 727 if (ret < 0)
728 goto err;
729 if (ret > 0)
fa1c114f
JS		 730 __set_bit(ATH_STAT_MRRETRY, sc->status);
731
732 /*
733 * Reset the key cache since some parts do not
734 * reset the contents on initial power up.
735 */
c65638a7 736 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 737 ath5k_hw_reset_key(ah, i);
738
739 /*
740 * Collect the channel list. The 802.11 layer
741 * is resposible for filtering this list based
742 * on settings like the phy mode and regulatory
743 * domain restrictions.
744 */
63266a65 745 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 746 if (ret) {
747 ATH5K_ERR(sc, "can't get channels\n");
748 goto err;
749 }
750
751 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 752 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
753 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 754 else
d8ee398d 755 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 756
757 /*
758 * Allocate tx+rx descriptors and populate the lists.
759 */
760 ret = ath5k_desc_alloc(sc, pdev);
761 if (ret) {
762 ATH5K_ERR(sc, "can't allocate descriptors\n");
763 goto err;
764 }
765
766 /*
767 * Allocate hardware transmit queues: one queue for
768 * beacon frames and one data queue for each QoS
769 * priority. Note that hw functions handle reseting
770 * these queues at the needed time.
771 */
772 ret = ath5k_beaconq_setup(ah);
773 if (ret < 0) {
774 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
775 goto err_desc;
776 }
777 sc->bhalq = ret;
778
779 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
780 if (IS_ERR(sc->txq)) {
781 ATH5K_ERR(sc, "can't setup xmit queue\n");
782 ret = PTR_ERR(sc->txq);
783 goto err_bhal;
784 }
785
786 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
787 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
788 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
789 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 790
791 ath5k_hw_get_lladdr(ah, mac);
792 SET_IEEE80211_PERM_ADDR(hw, mac);
793 /* All MAC address bits matter for ACKs */
794 memset(sc->bssidmask, 0xff, ETH_ALEN);
795 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
796
797 ret = ieee80211_register_hw(hw);
798 if (ret) {
799 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
800 goto err_queues;
801 }
802
3a078876
BC		 803 ath5k_init_leds(sc);
804
fa1c114f
JS		 805 return 0;
806err_queues:
807 ath5k_txq_release(sc);
808err_bhal:
809 ath5k_hw_release_tx_queue(ah, sc->bhalq);
810err_desc:
811 ath5k_desc_free(sc, pdev);
812err:
813 return ret;
814}
815
816static void
817ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
818{
819 struct ath5k_softc *sc = hw->priv;
820
821 /*
822 * NB: the order of these is important:
823 * o call the 802.11 layer before detaching ath5k_hw to
824 * insure callbacks into the driver to delete global
825 * key cache entries can be handled
826 * o reclaim the tx queue data structures after calling
827 * the 802.11 layer as we'll get called back to reclaim
828 * node state and potentially want to use them
829 * o to cleanup the tx queues the hal is called, so detach
830 * it last
831 * XXX: ??? detach ath5k_hw ???
832 * Other than that, it's straightforward...
833 */
834 ieee80211_unregister_hw(hw);
835 ath5k_desc_free(sc, pdev);
836 ath5k_txq_release(sc);
837 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 838 ath5k_unregister_leds(sc);
fa1c114f
JS		 839
840 /*
841 * NB: can't reclaim these until after ieee80211_ifdetach
842 * returns because we'll get called back to reclaim node
843 * state and potentially want to use them.
844 */
845}
846
847
848
849
850/********************\
851* Channel/mode setup *
852\********************/
853
854/*
855 * Convert IEEE channel number to MHz frequency.
856 */
857static inline short
858ath5k_ieee2mhz(short chan)
859{
860 if (chan <= 14 || chan >= 27)
861 return ieee80211chan2mhz(chan);
862 else
863 return 2212 + chan * 20;
864}
865
fa1c114f
JS		 866static unsigned int
867ath5k_copy_channels(struct ath5k_hw *ah,
868 struct ieee80211_channel *channels,
869 unsigned int mode,
870 unsigned int max)
871{
d8ee398d 872 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 873
874 if (!test_bit(mode, ah->ah_modes))
875 return 0;
876
fa1c114f 877 switch (mode) {
d8ee398d
LR		 878 case AR5K_MODE_11A:
879 case AR5K_MODE_11A_TURBO:
fa1c114f 880 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 881 size = 220 ;
fa1c114f
JS		 882 chfreq = CHANNEL_5GHZ;
883 break;
d8ee398d
LR		 884 case AR5K_MODE_11B:
885 case AR5K_MODE_11G:
886 case AR5K_MODE_11G_TURBO:
887 size = 26;
fa1c114f
JS		 888 chfreq = CHANNEL_2GHZ;
889 break;
890 default:
891 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
892 return 0;
893 }
894
895 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 896 ch = i + 1 ;
897 freq = ath5k_ieee2mhz(ch);
fa1c114f 898
d8ee398d
LR		 899 /* Check if channel is supported by the chipset */
900 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 901 continue;
902
d8ee398d
LR		 903 /* Write channel info and increment counter */
904 channels[count].center_freq = freq;
a3f4b914
LR		 905 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
906 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 907 switch (mode) {
908 case AR5K_MODE_11A:
909 case AR5K_MODE_11G:
910 channels[count].hw_value = chfreq | CHANNEL_OFDM;
911 break;
912 case AR5K_MODE_11A_TURBO:
913 case AR5K_MODE_11G_TURBO:
914 channels[count].hw_value = chfreq |
915 CHANNEL_OFDM | CHANNEL_TURBO;
916 break;
917 case AR5K_MODE_11B:
d8ee398d
LR		 918 channels[count].hw_value = CHANNEL_B;
919 }
fa1c114f 920
fa1c114f
JS		 921 count++;
922 max--;
923 }
924
925 return count;
926}
927
63266a65
BR		 928static void
929ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
930{
931 u8 i;
932
933 for (i = 0; i < AR5K_MAX_RATES; i++)
934 sc->rate_idx[b->band][i] = -1;
935
936 for (i = 0; i < b->n_bitrates; i++) {
937 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
938 if (b->bitrates[i].hw_value_short)
939 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
940 }
941}
942
d8ee398d 943static int
63266a65 944ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 945{
946 struct ath5k_softc *sc = hw->priv;
d8ee398d 947 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 948 struct ieee80211_supported_band *sband;
949 int max_c, count_c = 0;
950 int i;
fa1c114f 951
d8ee398d 952 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 953 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 954
955 /* 2GHz band */
63266a65
BR		 956 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
957 sband->band = IEEE80211_BAND_2GHZ;
958 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 959
63266a65
BR		 960 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
961 /* G mode */
962 memcpy(sband->bitrates, &ath5k_rates[0],
963 sizeof(struct ieee80211_rate) * 12);
964 sband->n_bitrates = 12;
fa1c114f 965
d8ee398d 966 sband->channels = sc->channels;
d8ee398d 967 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 968 AR5K_MODE_11G, max_c);
fa1c114f 969
63266a65 970 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 971 count_c = sband->n_channels;
63266a65
BR		 972 max_c -= count_c;
973 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
974 /* B mode */
975 memcpy(sband->bitrates, &ath5k_rates[0],
976 sizeof(struct ieee80211_rate) * 4);
977 sband->n_bitrates = 4;
978
979 /* 5211 only supports B rates and uses 4bit rate codes
980 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
981 * fix them up here:
982 */
983 if (ah->ah_version == AR5K_AR5211) {
984 for (i = 0; i < 4; i++) {
985 sband->bitrates[i].hw_value =
986 sband->bitrates[i].hw_value & 0xF;
987 sband->bitrates[i].hw_value_short =
988 sband->bitrates[i].hw_value_short & 0xF;
989 }
990 }
fa1c114f 991
63266a65
BR		 992 sband->channels = sc->channels;
993 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
994 AR5K_MODE_11B, max_c);
d8ee398d 995
63266a65
BR		 996 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
997 count_c = sband->n_channels;
d8ee398d 998 max_c -= count_c;
fa1c114f 999 }
63266a65 1000 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1001
63266a65 1002 /* 5GHz band, A mode */
400ec45a 1003 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1004 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1005 sband->band = IEEE80211_BAND_5GHZ;
1006 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1007
63266a65
BR		 1008 memcpy(sband->bitrates, &ath5k_rates[4],
1009 sizeof(struct ieee80211_rate) * 8);
1010 sband->n_bitrates = 8;
fa1c114f 1011
63266a65 1012 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1013 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1014 AR5K_MODE_11A, max_c);
1015
d8ee398d
LR		 1016 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1017 }
63266a65 1018 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1019
b446197c 1020 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1021
1022 return 0;
fa1c114f
JS		 1023}
1024
1025/*
1026 * Set/change channels. If the channel is really being changed,
1027 * it's done by reseting the chip. To accomplish this we must
1028 * first cleanup any pending DMA, then restart stuff after a la
1029 * ath5k_init.
1030 */
1031static int
1032ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1033{
d8ee398d
LR		 1034 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1035 sc->curchan->center_freq, chan->center_freq);
1036
1037 if (chan->center_freq != sc->curchan->center_freq ||
1038 chan->hw_value != sc->curchan->hw_value) {
1039
1040 sc->curchan = chan;
1041 sc->curband = &sc->sbands[chan->band];
fa1c114f 1042
fa1c114f
JS		 1043 /*
1044 * To switch channels clear any pending DMA operations;
1045 * wait long enough for the RX fifo to drain, reset the
1046 * hardware at the new frequency, and then re-enable
1047 * the relevant bits of the h/w.
1048 */
d7dc1003 1049 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1050 }
1051
1052 return 0;
1053}
1054
1055static void
1056ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1057{
fa1c114f 1058 sc->curmode = mode;
d8ee398d 1059
400ec45a 1060 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1061 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1062 } else {
1063 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1064 }
fa1c114f
JS		 1065}
1066
1067static void
1068ath5k_mode_setup(struct ath5k_softc *sc)
1069{
1070 struct ath5k_hw *ah = sc->ah;
1071 u32 rfilt;
1072
1073 /* configure rx filter */
1074 rfilt = sc->filter_flags;
1075 ath5k_hw_set_rx_filter(ah, rfilt);
1076
1077 if (ath5k_hw_hasbssidmask(ah))
1078 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1079
1080 /* configure operational mode */
1081 ath5k_hw_set_opmode(ah);
1082
1083 ath5k_hw_set_mcast_filter(ah, 0, 0);
1084 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1085}
1086
d8ee398d 1087static inline int
63266a65
BR		 1088ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1089{
1090 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1091 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1092}
1093
fa1c114f
JS		 1094/***************\
1095* Buffers setup *
1096\***************/
1097
1098static int
1099ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1100{
1101 struct ath5k_hw *ah = sc->ah;
1102 struct sk_buff *skb = bf->skb;
1103 struct ath5k_desc *ds;
1104
1105 if (likely(skb == NULL)) {
1106 unsigned int off;
1107
1108 /*
1109 * Allocate buffer with headroom_needed space for the
1110 * fake physical layer header at the start.
1111 */
1112 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1113 if (unlikely(skb == NULL)) {
1114 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1115 sc->rxbufsize + sc->cachelsz - 1);
1116 return -ENOMEM;
1117 }
1118 /*
1119 * Cache-line-align. This is important (for the
1120 * 5210 at least) as not doing so causes bogus data
1121 * in rx'd frames.
1122 */
1123 off = ((unsigned long)skb->data) % sc->cachelsz;
1124 if (off != 0)
1125 skb_reserve(skb, sc->cachelsz - off);
1126
1127 bf->skb = skb;
1128 bf->skbaddr = pci_map_single(sc->pdev,
1129 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1130 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1131 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1132 dev_kfree_skb(skb);
1133 bf->skb = NULL;
1134 return -ENOMEM;
1135 }
1136 }
1137
1138 /*
1139 * Setup descriptors. For receive we always terminate
1140 * the descriptor list with a self-linked entry so we'll
1141 * not get overrun under high load (as can happen with a
1142 * 5212 when ANI processing enables PHY error frames).
1143 *
1144 * To insure the last descriptor is self-linked we create
1145 * each descriptor as self-linked and add it to the end. As
1146 * each additional descriptor is added the previous self-linked
1147 * entry is ``fixed'' naturally. This should be safe even
1148 * if DMA is happening. When processing RX interrupts we
1149 * never remove/process the last, self-linked, entry on the
1150 * descriptor list. This insures the hardware always has
1151 * someplace to write a new frame.
1152 */
1153 ds = bf->desc;
1154 ds->ds_link = bf->daddr; /* link to self */
1155 ds->ds_data = bf->skbaddr;
c6e387a2 1156 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1157 skb_tailroom(skb), /* buffer size */
1158 0);
1159
1160 if (sc->rxlink != NULL)
1161 *sc->rxlink = bf->daddr;
1162 sc->rxlink = &ds->ds_link;
1163 return 0;
1164}
1165
1166static int
e039fa4a 1167ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1168{
1169 struct ath5k_hw *ah = sc->ah;
1170 struct ath5k_txq *txq = sc->txq;
1171 struct ath5k_desc *ds = bf->desc;
1172 struct sk_buff *skb = bf->skb;
a888d52d 1173 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1174 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1175 int ret;
1176
1177 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1178
fa1c114f
JS		 1179 /* XXX endianness */
1180 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1181 PCI_DMA_TODEVICE);
1182
e039fa4a 1183 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1184 flags |= AR5K_TXDESC_NOACK;
1185
281c56dd 1186 pktlen = skb->len;
fa1c114f 1187
d0f09804 1188 if (info->control.hw_key) {
e039fa4a
JB		 1189 keyidx = info->control.hw_key->hw_key_idx;
1190 pktlen += info->control.icv_len;
fa1c114f 1191 }
fa1c114f
JS		 1192 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1193 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1194 (sc->power_level * 2),
e039fa4a
JB		 1195 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1196 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1197 if (ret)
1198 goto err_unmap;
1199
1200 ds->ds_link = 0;
1201 ds->ds_data = bf->skbaddr;
1202
1203 spin_lock_bh(&txq->lock);
1204 list_add_tail(&bf->list, &txq->q);
57ffc589 1205 sc->tx_stats[txq->qnum].len++;
fa1c114f 1206 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1207 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1208 else /* no, so only link it */
1209 *txq->link = bf->daddr;
1210
1211 txq->link = &ds->ds_link;
c6e387a2 1212 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1213 mmiowb();
fa1c114f
JS		 1214 spin_unlock_bh(&txq->lock);
1215
1216 return 0;
1217err_unmap:
1218 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1219 return ret;
1220}
1221
1222/*******************\
1223* Descriptors setup *
1224\*******************/
1225
1226static int
1227ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1228{
1229 struct ath5k_desc *ds;
1230 struct ath5k_buf *bf;
1231 dma_addr_t da;
1232 unsigned int i;
1233 int ret;
1234
1235 /* allocate descriptors */
1236 sc->desc_len = sizeof(struct ath5k_desc) *
1237 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1238 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1239 if (sc->desc == NULL) {
1240 ATH5K_ERR(sc, "can't allocate descriptors\n");
1241 ret = -ENOMEM;
1242 goto err;
1243 }
1244 ds = sc->desc;
1245 da = sc->desc_daddr;
1246 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1247 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1248
1249 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1250 sizeof(struct ath5k_buf), GFP_KERNEL);
1251 if (bf == NULL) {
1252 ATH5K_ERR(sc, "can't allocate bufptr\n");
1253 ret = -ENOMEM;
1254 goto err_free;
1255 }
1256 sc->bufptr = bf;
1257
1258 INIT_LIST_HEAD(&sc->rxbuf);
1259 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1260 bf->desc = ds;
1261 bf->daddr = da;
1262 list_add_tail(&bf->list, &sc->rxbuf);
1263 }
1264
1265 INIT_LIST_HEAD(&sc->txbuf);
1266 sc->txbuf_len = ATH_TXBUF;
1267 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1268 da += sizeof(*ds)) {
1269 bf->desc = ds;
1270 bf->daddr = da;
1271 list_add_tail(&bf->list, &sc->txbuf);
1272 }
1273
1274 /* beacon buffer */
1275 bf->desc = ds;
1276 bf->daddr = da;
1277 sc->bbuf = bf;
1278
1279 return 0;
1280err_free:
1281 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1282err:
1283 sc->desc = NULL;
1284 return ret;
1285}
1286
1287static void
1288ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1289{
1290 struct ath5k_buf *bf;
1291
1292 ath5k_txbuf_free(sc, sc->bbuf);
1293 list_for_each_entry(bf, &sc->txbuf, list)
1294 ath5k_txbuf_free(sc, bf);
1295 list_for_each_entry(bf, &sc->rxbuf, list)
1296 ath5k_txbuf_free(sc, bf);
1297
1298 /* Free memory associated with all descriptors */
1299 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1300
1301 kfree(sc->bufptr);
1302 sc->bufptr = NULL;
1303}
1304
1305
1306
1307
1308
1309/**************\
1310* Queues setup *
1311\**************/
1312
1313static struct ath5k_txq *
1314ath5k_txq_setup(struct ath5k_softc *sc,
1315 int qtype, int subtype)
1316{
1317 struct ath5k_hw *ah = sc->ah;
1318 struct ath5k_txq *txq;
1319 struct ath5k_txq_info qi = {
1320 .tqi_subtype = subtype,
1321 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1322 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1323 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1324 };
1325 int qnum;
1326
1327 /*
1328 * Enable interrupts only for EOL and DESC conditions.
1329 * We mark tx descriptors to receive a DESC interrupt
1330 * when a tx queue gets deep; otherwise waiting for the
1331 * EOL to reap descriptors. Note that this is done to
1332 * reduce interrupt load and this only defers reaping
1333 * descriptors, never transmitting frames. Aside from
1334 * reducing interrupts this also permits more concurrency.
1335 * The only potential downside is if the tx queue backs
1336 * up in which case the top half of the kernel may backup
1337 * due to a lack of tx descriptors.
1338 */
1339 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1340 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1341 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1342 if (qnum < 0) {
1343 /*
1344 * NB: don't print a message, this happens
1345 * normally on parts with too few tx queues
1346 */
1347 return ERR_PTR(qnum);
1348 }
1349 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1350 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1351 qnum, ARRAY_SIZE(sc->txqs));
1352 ath5k_hw_release_tx_queue(ah, qnum);
1353 return ERR_PTR(-EINVAL);
1354 }
1355 txq = &sc->txqs[qnum];
1356 if (!txq->setup) {
1357 txq->qnum = qnum;
1358 txq->link = NULL;
1359 INIT_LIST_HEAD(&txq->q);
1360 spin_lock_init(&txq->lock);
1361 txq->setup = true;
1362 }
1363 return &sc->txqs[qnum];
1364}
1365
1366static int
1367ath5k_beaconq_setup(struct ath5k_hw *ah)
1368{
1369 struct ath5k_txq_info qi = {
1370 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1371 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1372 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1373 /* NB: for dynamic turbo, don't enable any other interrupts */
1374 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1375 };
1376
1377 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1378}
1379
1380static int
1381ath5k_beaconq_config(struct ath5k_softc *sc)
1382{
1383 struct ath5k_hw *ah = sc->ah;
1384 struct ath5k_txq_info qi;
1385 int ret;
1386
1387 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1388 if (ret)
1389 return ret;
05c914fe
JB		 1390 if (sc->opmode == NL80211_IFTYPE_AP ||
1391 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1392 /*
1393 * Always burst out beacon and CAB traffic
1394 * (aifs = cwmin = cwmax = 0)
1395 */
1396 qi.tqi_aifs = 0;
1397 qi.tqi_cw_min = 0;
1398 qi.tqi_cw_max = 0;
05c914fe 1399 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1400 /*
1401 * Adhoc mode; backoff between 0 and (2 * cw_min).
1402 */
1403 qi.tqi_aifs = 0;
1404 qi.tqi_cw_min = 0;
1405 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1406 }
1407
6d91e1d8
BR		 1408 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1409 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1410 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1411
c6e387a2 1412 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1413 if (ret) {
1414 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1415 "hardware queue!\n", __func__);
1416 return ret;
1417 }
1418
1419 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1420}
1421
1422static void
1423ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1424{
1425 struct ath5k_buf *bf, *bf0;
1426
1427 /*
1428 * NB: this assumes output has been stopped and
1429 * we do not need to block ath5k_tx_tasklet
1430 */
1431 spin_lock_bh(&txq->lock);
1432 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1433 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1434
1435 ath5k_txbuf_free(sc, bf);
1436
1437 spin_lock_bh(&sc->txbuflock);
57ffc589 1438 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1439 list_move_tail(&bf->list, &sc->txbuf);
1440 sc->txbuf_len++;
1441 spin_unlock_bh(&sc->txbuflock);
1442 }
1443 txq->link = NULL;
1444 spin_unlock_bh(&txq->lock);
1445}
1446
1447/*
1448 * Drain the transmit queues and reclaim resources.
1449 */
1450static void
1451ath5k_txq_cleanup(struct ath5k_softc *sc)
1452{
1453 struct ath5k_hw *ah = sc->ah;
1454 unsigned int i;
1455
1456 /* XXX return value */
1457 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1458 /* don't touch the hardware if marked invalid */
1459 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1460 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1461 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1462 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1463 if (sc->txqs[i].setup) {
1464 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1465 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1466 "link %p\n",
1467 sc->txqs[i].qnum,
c6e387a2 1468 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1469 sc->txqs[i].qnum),
1470 sc->txqs[i].link);
1471 }
1472 }
36d6825b 1473 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1474
1475 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1476 if (sc->txqs[i].setup)
1477 ath5k_txq_drainq(sc, &sc->txqs[i]);
1478}
1479
1480static void
1481ath5k_txq_release(struct ath5k_softc *sc)
1482{
1483 struct ath5k_txq *txq = sc->txqs;
1484 unsigned int i;
1485
1486 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1487 if (txq->setup) {
1488 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1489 txq->setup = false;
1490 }
1491}
1492
1493
1494
1495
1496/*************\
1497* RX Handling *
1498\*************/
1499
1500/*
1501 * Enable the receive h/w following a reset.
1502 */
1503static int
1504ath5k_rx_start(struct ath5k_softc *sc)
1505{
1506 struct ath5k_hw *ah = sc->ah;
1507 struct ath5k_buf *bf;
1508 int ret;
1509
1510 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1511
1512 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1513 sc->cachelsz, sc->rxbufsize);
1514
1515 sc->rxlink = NULL;
1516
1517 spin_lock_bh(&sc->rxbuflock);
1518 list_for_each_entry(bf, &sc->rxbuf, list) {
1519 ret = ath5k_rxbuf_setup(sc, bf);
1520 if (ret != 0) {
1521 spin_unlock_bh(&sc->rxbuflock);
1522 goto err;
1523 }
1524 }
1525 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1526 spin_unlock_bh(&sc->rxbuflock);
1527
c6e387a2
NK		 1528 ath5k_hw_set_rxdp(ah, bf->daddr);
1529 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1530 ath5k_mode_setup(sc); /* set filters, etc. */
1531 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1532
1533 return 0;
1534err:
1535 return ret;
1536}
1537
1538/*
1539 * Disable the receive h/w in preparation for a reset.
1540 */
1541static void
1542ath5k_rx_stop(struct ath5k_softc *sc)
1543{
1544 struct ath5k_hw *ah = sc->ah;
1545
c6e387a2 1546 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1547 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1548 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1549
1550 ath5k_debug_printrxbuffs(sc, ah);
1551
1552 sc->rxlink = NULL; /* just in case */
1553}
1554
1555static unsigned int
1556ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1557 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1558{
1559 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1560 unsigned int keyix, hlen;
fa1c114f 1561
b47f407b
BR		 1562 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1563 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1564 return RX_FLAG_DECRYPTED;
1565
1566 /* Apparently when a default key is used to decrypt the packet
1567 the hw does not set the index used to decrypt. In such cases
1568 get the index from the packet. */
798ee985 1569 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1570 if (ieee80211_has_protected(hdr->frame_control) &&
1571 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1572 skb->len >= hlen + 4) {
fa1c114f
JS		 1573 keyix = skb->data[hlen + 3] >> 6;
1574
1575 if (test_bit(keyix, sc->keymap))
1576 return RX_FLAG_DECRYPTED;
1577 }
1578
1579 return 0;
1580}
1581
036cd1ec
BR		 1582
1583static void
6ba81c2c
BR		 1584ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1585 struct ieee80211_rx_status *rxs)
036cd1ec 1586{
6ba81c2c 1587 u64 tsf, bc_tstamp;
036cd1ec
BR		 1588 u32 hw_tu;
1589 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1590
24b56e70 1591 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1592 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1593 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1594 /*
6ba81c2c
BR		 1595 * Received an IBSS beacon with the same BSSID. Hardware *must*
1596 * have updated the local TSF. We have to work around various
1597 * hardware bugs, though...
036cd1ec 1598 */
6ba81c2c
BR		 1599 tsf = ath5k_hw_get_tsf64(sc->ah);
1600 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1601 hw_tu = TSF_TO_TU(tsf);
1602
1603 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1604 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1605 (unsigned long long)bc_tstamp,
1606 (unsigned long long)rxs->mactime,
1607 (unsigned long long)(rxs->mactime - bc_tstamp),
1608 (unsigned long long)tsf);
6ba81c2c
BR		 1609
1610 /*
1611 * Sometimes the HW will give us a wrong tstamp in the rx
1612 * status, causing the timestamp extension to go wrong.
1613 * (This seems to happen especially with beacon frames bigger
1614 * than 78 byte (incl. FCS))
1615 * But we know that the receive timestamp must be later than the
1616 * timestamp of the beacon since HW must have synced to that.
1617 *
1618 * NOTE: here we assume mactime to be after the frame was
1619 * received, not like mac80211 which defines it at the start.
1620 */
1621 if (bc_tstamp > rxs->mactime) {
036cd1ec 1622 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1623 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1624 (unsigned long long)rxs->mactime,
1625 (unsigned long long)tsf);
6ba81c2c 1626 rxs->mactime = tsf;
036cd1ec 1627 }
6ba81c2c
BR		 1628
1629 /*
1630 * Local TSF might have moved higher than our beacon timers,
1631 * in that case we have to update them to continue sending
1632 * beacons. This also takes care of synchronizing beacon sending
1633 * times with other stations.
1634 */
1635 if (hw_tu >= sc->nexttbtt)
1636 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1637 }
1638}
1639
1640
fa1c114f
JS		 1641static void
1642ath5k_tasklet_rx(unsigned long data)
1643{
1644 struct ieee80211_rx_status rxs = {};
b47f407b 1645 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1646 struct sk_buff *skb;
1647 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1648 struct ath5k_buf *bf, *bf_last;
fa1c114f 1649 struct ath5k_desc *ds;
fa1c114f
JS		 1650 int ret;
1651 int hdrlen;
1652 int pad;
1653
1654 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1655 if (list_empty(&sc->rxbuf)) {
1656 ATH5K_WARN(sc, "empty rx buf pool\n");
1657 goto unlock;
1658 }
1659 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1660 do {
d6894b5b
BC		 1661 rxs.flag = 0;
1662
fa1c114f
JS		 1663 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1664 BUG_ON(bf->skb == NULL);
1665 skb = bf->skb;
1666 ds = bf->desc;
1667
3a0f2c87
JS		 1668 /*
1669 * last buffer must not be freed to ensure proper hardware
1670 * function. When the hardware finishes also a packet next to
1671 * it, we are sure, it doesn't use it anymore and we can go on.
1672 */
1673 if (bf_last == bf)
1674 bf->flags |= 1;
1675 if (bf->flags) {
1676 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1677 struct ath5k_buf, list);
1678 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1679 &rs);
1680 if (ret)
1681 break;
1682 bf->flags &= ~1;
1683 /* skip the overwritten one (even status is martian) */
1684 goto next;
1685 }
fa1c114f 1686
b47f407b 1687 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1688 if (unlikely(ret == -EINPROGRESS))
1689 break;
1690 else if (unlikely(ret)) {
1691 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1692 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1693 return;
1694 }
1695
b47f407b 1696 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1697 ATH5K_WARN(sc, "unsupported jumbo\n");
1698 goto next;
1699 }
1700
b47f407b
BR		 1701 if (unlikely(rs.rs_status)) {
1702 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1703 goto next;
b47f407b 1704 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1705 /*
1706 * Decrypt error. If the error occurred
1707 * because there was no hardware key, then
1708 * let the frame through so the upper layers
1709 * can process it. This is necessary for 5210
1710 * parts which have no way to setup a ``clear''
1711 * key cache entry.
1712 *
1713 * XXX do key cache faulting
1714 */
b47f407b
BR		 1715 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1716 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1717 goto accept;
1718 }
b47f407b 1719 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1720 rxs.flag |= RX_FLAG_MMIC_ERROR;
1721 goto accept;
1722 }
1723
1724 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1725 if ((rs.rs_status &
1726 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1727 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1728 goto next;
1729 }
1730accept:
fa1c114f
JS		 1731 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1732 PCI_DMA_FROMDEVICE);
1733 bf->skb = NULL;
1734
b47f407b 1735 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1736
1737 /*
1738 * the hardware adds a padding to 4 byte boundaries between
1739 * the header and the payload data if the header length is
1740 * not multiples of 4 - remove it
1741 */
1742 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1743 if (hdrlen & 3) {
1744 pad = hdrlen % 4;
1745 memmove(skb->data + pad, skb->data, hdrlen);
1746 skb_pull(skb, pad);
1747 }
1748
c0e1899b
BR		 1749 /*
1750 * always extend the mac timestamp, since this information is
1751 * also needed for proper IBSS merging.
1752 *
1753 * XXX: it might be too late to do it here, since rs_tstamp is
1754 * 15bit only. that means TSF extension has to be done within
1755 * 32768usec (about 32ms). it might be necessary to move this to
1756 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1757 *
1758 * Unfortunately we don't know when the hardware takes the rx
1759 * timestamp (beginning of phy frame, data frame, end of rx?).
1760 * The only thing we know is that it is hardware specific...
1761 * On AR5213 it seems the rx timestamp is at the end of the
1762 * frame, but i'm not sure.
1763 *
1764 * NOTE: mac80211 defines mactime at the beginning of the first
1765 * data symbol. Since we don't have any time references it's
1766 * impossible to comply to that. This affects IBSS merge only
1767 * right now, so it's not too bad...
c0e1899b 1768 */
b47f407b 1769 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1770 rxs.flag |= RX_FLAG_TSFT;
1771
d8ee398d
LR		 1772 rxs.freq = sc->curchan->center_freq;
1773 rxs.band = sc->curband->band;
fa1c114f 1774
fa1c114f 1775 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1776 rxs.signal = rxs.noise + rs.rs_rssi;
1777 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1778
b47f407b
BR		 1779 rxs.antenna = rs.rs_antenna;
1780 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1781 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1782
06303352
BR		 1783 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1784 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1785 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1786
fa1c114f
JS		 1787 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1788
036cd1ec 1789 /* check beacons in IBSS mode */
05c914fe 1790 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1791 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1792
fa1c114f 1793 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1794next:
1795 list_move_tail(&bf->list, &sc->rxbuf);
1796 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1797unlock:
fa1c114f
JS		 1798 spin_unlock(&sc->rxbuflock);
1799}
1800
1801
1802
1803
1804/*************\
1805* TX Handling *
1806\*************/
1807
1808static void
1809ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1810{
b47f407b 1811 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1812 struct ath5k_buf *bf, *bf0;
1813 struct ath5k_desc *ds;
1814 struct sk_buff *skb;
e039fa4a 1815 struct ieee80211_tx_info *info;
fa1c114f
JS		 1816 int ret;
1817
1818 spin_lock(&txq->lock);
1819 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1820 ds = bf->desc;
1821
b47f407b 1822 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1823 if (unlikely(ret == -EINPROGRESS))
1824 break;
1825 else if (unlikely(ret)) {
1826 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1827 ret, txq->qnum);
1828 break;
1829 }
1830
1831 skb = bf->skb;
a888d52d 1832 info = IEEE80211_SKB_CB(skb);
fa1c114f 1833 bf->skb = NULL;
e039fa4a 1834
fa1c114f
JS		 1835 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1836 PCI_DMA_TODEVICE);
1837
e039fa4a 1838 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1839 if (unlikely(ts.ts_status)) {
fa1c114f 1840 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1841 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1842 info->status.excessive_retries = 1;
b47f407b 1843 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1844 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1845 } else {
e039fa4a
JB		 1846 info->flags |= IEEE80211_TX_STAT_ACK;
1847 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1848 }
1849
e039fa4a 1850 ieee80211_tx_status(sc->hw, skb);
57ffc589 1851 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1852
1853 spin_lock(&sc->txbuflock);
57ffc589 1854 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1855 list_move_tail(&bf->list, &sc->txbuf);
1856 sc->txbuf_len++;
1857 spin_unlock(&sc->txbuflock);
1858 }
1859 if (likely(list_empty(&txq->q)))
1860 txq->link = NULL;
1861 spin_unlock(&txq->lock);
1862 if (sc->txbuf_len > ATH_TXBUF / 5)
1863 ieee80211_wake_queues(sc->hw);
1864}
1865
1866static void
1867ath5k_tasklet_tx(unsigned long data)
1868{
1869 struct ath5k_softc *sc = (void *)data;
1870
1871 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1872}
1873
1874
fa1c114f
JS		 1875/*****************\
1876* Beacon handling *
1877\*****************/
1878
1879/*
1880 * Setup the beacon frame for transmit.
1881 */
1882static int
e039fa4a 1883ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1884{
1885 struct sk_buff *skb = bf->skb;
a888d52d 1886 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1887 struct ath5k_hw *ah = sc->ah;
1888 struct ath5k_desc *ds;
1889 int ret, antenna = 0;
1890 u32 flags;
1891
1892 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1893 PCI_DMA_TODEVICE);
1894 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1895 "skbaddr %llx\n", skb, skb->data, skb->len,
1896 (unsigned long long)bf->skbaddr);
8d8bb39b 1897 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1898 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1899 return -EIO;
1900 }
1901
1902 ds = bf->desc;
1903
1904 flags = AR5K_TXDESC_NOACK;
05c914fe 1905 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1906 ds->ds_link = bf->daddr; /* self-linked */
1907 flags |= AR5K_TXDESC_VEOL;
1908 /*
1909 * Let hardware handle antenna switching if txantenna is not set
1910 */
1911 } else {
1912 ds->ds_link = 0;
1913 /*
1914 * Switch antenna every 4 beacons if txantenna is not set
1915 * XXX assumes two antennas
1916 */
1917 if (antenna == 0)
1918 antenna = sc->bsent & 4 ? 2 : 1;
1919 }
1920
1921 ds->ds_data = bf->skbaddr;
281c56dd 1922 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1923 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1924 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1925 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1926 1, AR5K_TXKEYIX_INVALID,
400ec45a 1927 antenna, flags, 0, 0);
fa1c114f
JS		 1928 if (ret)
1929 goto err_unmap;
1930
1931 return 0;
1932err_unmap:
1933 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1934 return ret;
1935}
1936
1937/*
1938 * Transmit a beacon frame at SWBA. Dynamic updates to the
1939 * frame contents are done as needed and the slot time is
1940 * also adjusted based on current state.
1941 *
1942 * this is usually called from interrupt context (ath5k_intr())
1943 * but also from ath5k_beacon_config() in IBSS mode which in turn
1944 * can be called from a tasklet and user context
1945 */
1946static void
1947ath5k_beacon_send(struct ath5k_softc *sc)
1948{
1949 struct ath5k_buf *bf = sc->bbuf;
1950 struct ath5k_hw *ah = sc->ah;
1951
be9b7259 1952 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1953
05c914fe
JB		 1954 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1955 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 1956 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1957 return;
1958 }
1959 /*
1960 * Check if the previous beacon has gone out. If
1961 * not don't don't try to post another, skip this
1962 * period and wait for the next. Missed beacons
1963 * indicate a problem and should not occur. If we
1964 * miss too many consecutive beacons reset the device.
1965 */
1966 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1967 sc->bmisscount++;
be9b7259 1968 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1969 "missed %u consecutive beacons\n", sc->bmisscount);
1970 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1971 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1972 "stuck beacon time (%u missed)\n",
1973 sc->bmisscount);
1974 tasklet_schedule(&sc->restq);
1975 }
1976 return;
1977 }
1978 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1979 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1980 "resume beacon xmit after %u misses\n",
1981 sc->bmisscount);
1982 sc->bmisscount = 0;
1983 }
1984
1985 /*
1986 * Stop any current dma and put the new frame on the queue.
1987 * This should never fail since we check above that no frames
1988 * are still pending on the queue.
1989 */
1990 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1991 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1992 /* NB: hw still stops DMA, so proceed */
1993 }
fa1c114f 1994
c6e387a2
NK		 1995 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1996 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1997 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1998 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1999
2000 sc->bsent++;
2001}
2002
2003
9804b98d
BR		 2004/**
2005 * ath5k_beacon_update_timers - update beacon timers
2006 *
2007 * @sc: struct ath5k_softc pointer we are operating on
2008 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2009 * beacon timer update based on the current HW TSF.
2010 *
2011 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2012 * of a received beacon or the current local hardware TSF and write it to the
2013 * beacon timer registers.
2014 *
2015 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2016 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2017 * when we otherwise know we have to update the timers, but we keep it in this
2018 * function to have it all together in one place.
2019 */
fa1c114f 2020static void
9804b98d 2021ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2022{
2023 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2024 u32 nexttbtt, intval, hw_tu, bc_tu;
2025 u64 hw_tsf;
fa1c114f
JS		 2026
2027 intval = sc->bintval & AR5K_BEACON_PERIOD;
2028 if (WARN_ON(!intval))
2029 return;
2030
9804b98d
BR		 2031 /* beacon TSF converted to TU */
2032 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2033
9804b98d
BR		 2034 /* current TSF converted to TU */
2035 hw_tsf = ath5k_hw_get_tsf64(ah);
2036 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2037
9804b98d
BR		 2038#define FUDGE 3
2039 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2040 if (bc_tsf == -1) {
2041 /*
2042 * no beacons received, called internally.
2043 * just need to refresh timers based on HW TSF.
2044 */
2045 nexttbtt = roundup(hw_tu + FUDGE, intval);
2046 } else if (bc_tsf == 0) {
2047 /*
2048 * no beacon received, probably called by ath5k_reset_tsf().
2049 * reset TSF to start with 0.
2050 */
2051 nexttbtt = intval;
2052 intval |= AR5K_BEACON_RESET_TSF;
2053 } else if (bc_tsf > hw_tsf) {
2054 /*
2055 * beacon received, SW merge happend but HW TSF not yet updated.
2056 * not possible to reconfigure timers yet, but next time we
2057 * receive a beacon with the same BSSID, the hardware will
2058 * automatically update the TSF and then we need to reconfigure
2059 * the timers.
2060 */
2061 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2062 "need to wait for HW TSF sync\n");
2063 return;
2064 } else {
2065 /*
2066 * most important case for beacon synchronization between STA.
2067 *
2068 * beacon received and HW TSF has been already updated by HW.
2069 * update next TBTT based on the TSF of the beacon, but make
2070 * sure it is ahead of our local TSF timer.
2071 */
2072 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2073 }
2074#undef FUDGE
fa1c114f 2075
036cd1ec
BR		 2076 sc->nexttbtt = nexttbtt;
2077
fa1c114f 2078 intval |= AR5K_BEACON_ENA;
fa1c114f 2079 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2080
2081 /*
2082 * debugging output last in order to preserve the time critical aspect
2083 * of this function
2084 */
2085 if (bc_tsf == -1)
2086 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2087 "reconfigured timers based on HW TSF\n");
2088 else if (bc_tsf == 0)
2089 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2090 "reset HW TSF and timers\n");
2091 else
2092 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2093 "updated timers based on beacon TSF\n");
2094
2095 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2096 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2097 (unsigned long long) bc_tsf,
2098 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2099 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2100 intval & AR5K_BEACON_PERIOD,
2101 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2102 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2103}
2104
2105
036cd1ec
BR		 2106/**
2107 * ath5k_beacon_config - Configure the beacon queues and interrupts
2108 *
2109 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2110 *
2111 * When operating in station mode we want to receive a BMISS interrupt when we
2112 * stop seeing beacons from the AP we've associated with so we can look for
2113 * another AP to associate with.
2114 *
036cd1ec 2115 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2116 * interrupts to detect TSF updates only.
036cd1ec
BR		 2117 *
2118 * AP mode is missing.
fa1c114f
JS		 2119 */
2120static void
2121ath5k_beacon_config(struct ath5k_softc *sc)
2122{
2123 struct ath5k_hw *ah = sc->ah;
2124
c6e387a2 2125 ath5k_hw_set_imr(ah, 0);
fa1c114f 2126 sc->bmisscount = 0;
dc1968e7 2127 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2128
05c914fe 2129 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2130 sc->imask |= AR5K_INT_BMISS;
05c914fe 2131 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2132 /*
036cd1ec
BR		 2133 * In IBSS mode we use a self-linked tx descriptor and let the
2134 * hardware send the beacons automatically. We have to load it
fa1c114f 2135 * only once here.
036cd1ec 2136 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2137 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2138 */
2139 ath5k_beaconq_config(sc);
fa1c114f 2140
036cd1ec
BR		 2141 sc->imask |= AR5K_INT_SWBA;
2142
00482973
JS		 2143 if (ath5k_hw_hasveol(ah)) {
2144 spin_lock(&sc->block);
fa1c114f 2145 ath5k_beacon_send(sc);
00482973
JS		 2146 spin_unlock(&sc->block);
2147 }
fa1c114f
JS		 2148 }
2149 /* TODO else AP */
2150
c6e387a2 2151 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2152}
2153
2154
2155/********************\
2156* Interrupt handling *
2157\********************/
2158
2159static int
2160ath5k_init(struct ath5k_softc *sc)
2161{
2162 int ret;
2163
2164 mutex_lock(&sc->lock);
2165
2166 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2167
2168 /*
2169 * Stop anything previously setup. This is safe
2170 * no matter this is the first time through or not.
2171 */
2172 ath5k_stop_locked(sc);
2173
2174 /*
2175 * The basic interface to setting the hardware in a good
2176 * state is ``reset''. On return the hardware is known to
2177 * be powered up and with interrupts disabled. This must
2178 * be followed by initialization of the appropriate bits
2179 * and then setup of the interrupt mask.
2180 */
d8ee398d
LR		 2181 sc->curchan = sc->hw->conf.channel;
2182 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2183 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2184 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2185 AR5K_INT_MIB;
d7dc1003
JS		 2186 ret = ath5k_reset(sc, false, false);
2187 if (ret)
2188 goto done;
fa1c114f 2189
fa1c114f
JS		 2190 /* Set ack to be sent at low bit-rates */
2191 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2192
2193 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2194 msecs_to_jiffies(ath5k_calinterval * 1000)));
2195
2196 ret = 0;
2197done:
274c7c36 2198 mmiowb();
fa1c114f
JS		 2199 mutex_unlock(&sc->lock);
2200 return ret;
2201}
2202
2203static int
2204ath5k_stop_locked(struct ath5k_softc *sc)
2205{
2206 struct ath5k_hw *ah = sc->ah;
2207
2208 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2209 test_bit(ATH_STAT_INVALID, sc->status));
2210
2211 /*
2212 * Shutdown the hardware and driver:
2213 * stop output from above
2214 * disable interrupts
2215 * turn off timers
2216 * turn off the radio
2217 * clear transmit machinery
2218 * clear receive machinery
2219 * drain and release tx queues
2220 * reclaim beacon resources
2221 * power down hardware
2222 *
2223 * Note that some of this work is not possible if the
2224 * hardware is gone (invalid).
2225 */
2226 ieee80211_stop_queues(sc->hw);
2227
2228 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2229 ath5k_led_off(sc);
c6e387a2 2230 ath5k_hw_set_imr(ah, 0);
274c7c36 2231 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2232 }
2233 ath5k_txq_cleanup(sc);
2234 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2235 ath5k_rx_stop(sc);
2236 ath5k_hw_phy_disable(ah);
2237 } else
2238 sc->rxlink = NULL;
2239
2240 return 0;
2241}
2242
2243/*
2244 * Stop the device, grabbing the top-level lock to protect
2245 * against concurrent entry through ath5k_init (which can happen
2246 * if another thread does a system call and the thread doing the
2247 * stop is preempted).
2248 */
2249static int
2250ath5k_stop_hw(struct ath5k_softc *sc)
2251{
2252 int ret;
2253
2254 mutex_lock(&sc->lock);
2255 ret = ath5k_stop_locked(sc);
2256 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2257 /*
2258 * Set the chip in full sleep mode. Note that we are
2259 * careful to do this only when bringing the interface
2260 * completely to a stop. When the chip is in this state
2261 * it must be carefully woken up or references to
2262 * registers in the PCI clock domain may freeze the bus
2263 * (and system). This varies by chip and is mostly an
2264 * issue with newer parts that go to sleep more quickly.
2265 */
2266 if (sc->ah->ah_mac_srev >= 0x78) {
2267 /*
2268 * XXX
2269 * don't put newer MAC revisions > 7.8 to sleep because
2270 * of the above mentioned problems
2271 */
2272 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2273 "not putting device to sleep\n");
2274 } else {
2275 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2276 "putting device to full sleep\n");
2277 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2278 }
2279 }
2280 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2281 mmiowb();
fa1c114f
JS		 2282 mutex_unlock(&sc->lock);
2283
2284 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2285 tasklet_kill(&sc->rxtq);
2286 tasklet_kill(&sc->txtq);
2287 tasklet_kill(&sc->restq);
fa1c114f
JS		 2288
2289 return ret;
2290}
2291
2292static irqreturn_t
2293ath5k_intr(int irq, void *dev_id)
2294{
2295 struct ath5k_softc *sc = dev_id;
2296 struct ath5k_hw *ah = sc->ah;
2297 enum ath5k_int status;
2298 unsigned int counter = 1000;
2299
2300 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2301 !ath5k_hw_is_intr_pending(ah)))
2302 return IRQ_NONE;
2303
2304 do {
2305 /*
2306 * Figure out the reason(s) for the interrupt. Note
2307 * that get_isr returns a pseudo-ISR that may include
2308 * bits we haven't explicitly enabled so we mask the
2309 * value to insure we only process bits we requested.
2310 */
2311 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2312 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2313 status, sc->imask);
2314 status &= sc->imask; /* discard unasked for bits */
2315 if (unlikely(status & AR5K_INT_FATAL)) {
2316 /*
2317 * Fatal errors are unrecoverable.
2318 * Typically these are caused by DMA errors.
2319 */
2320 tasklet_schedule(&sc->restq);
2321 } else if (unlikely(status & AR5K_INT_RXORN)) {
2322 tasklet_schedule(&sc->restq);
2323 } else {
2324 if (status & AR5K_INT_SWBA) {
2325 /*
2326 * Software beacon alert--time to send a beacon.
2327 * Handle beacon transmission directly; deferring
2328 * this is too slow to meet timing constraints
2329 * under load.
036cd1ec
BR		 2330 *
2331 * In IBSS mode we use this interrupt just to
2332 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2333 * transmission time) in order to detect wether
2334 * automatic TSF updates happened.
fa1c114f 2335 */
05c914fe 2336 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2337 /* XXX: only if VEOL suppported */
2338 u64 tsf = ath5k_hw_get_tsf64(ah);
2339 sc->nexttbtt += sc->bintval;
2340 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2341 "SWBA nexttbtt: %x hw_tu: %x "
2342 "TSF: %llx\n",
2343 sc->nexttbtt,
2344 TSF_TO_TU(tsf),
2345 (unsigned long long) tsf);
036cd1ec 2346 } else {
00482973 2347 spin_lock(&sc->block);
036cd1ec 2348 ath5k_beacon_send(sc);
00482973 2349 spin_unlock(&sc->block);
036cd1ec 2350 }
fa1c114f
JS		 2351 }
2352 if (status & AR5K_INT_RXEOL) {
2353 /*
2354 * NB: the hardware should re-read the link when
2355 * RXE bit is written, but it doesn't work at
2356 * least on older hardware revs.
2357 */
2358 sc->rxlink = NULL;
2359 }
2360 if (status & AR5K_INT_TXURN) {
2361 /* bump tx trigger level */
2362 ath5k_hw_update_tx_triglevel(ah, true);
2363 }
2364 if (status & AR5K_INT_RX)
2365 tasklet_schedule(&sc->rxtq);
2366 if (status & AR5K_INT_TX)
2367 tasklet_schedule(&sc->txtq);
2368 if (status & AR5K_INT_BMISS) {
2369 }
2370 if (status & AR5K_INT_MIB) {
194828a2
NK		 2371 /*
2372 * These stats are also used for ANI i think
2373 * so how about updating them more often ?
2374 */
2375 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2376 }
2377 }
2378 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2379
2380 if (unlikely(!counter))
2381 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2382
2383 return IRQ_HANDLED;
2384}
2385
2386static void
2387ath5k_tasklet_reset(unsigned long data)
2388{
2389 struct ath5k_softc *sc = (void *)data;
2390
d7dc1003 2391 ath5k_reset_wake(sc);
fa1c114f
JS		 2392}
2393
2394/*
2395 * Periodically recalibrate the PHY to account
2396 * for temperature/environment changes.
2397 */
2398static void
2399ath5k_calibrate(unsigned long data)
2400{
2401 struct ath5k_softc *sc = (void *)data;
2402 struct ath5k_hw *ah = sc->ah;
2403
2404 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2405 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2406 sc->curchan->hw_value);
fa1c114f
JS		 2407
2408 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2409 /*
2410 * Rfgain is out of bounds, reset the chip
2411 * to load new gain values.
2412 */
2413 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2414 ath5k_reset_wake(sc);
fa1c114f
JS		 2415 }
2416 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2417 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2418 ieee80211_frequency_to_channel(
2419 sc->curchan->center_freq));
fa1c114f
JS		 2420
2421 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2422 msecs_to_jiffies(ath5k_calinterval * 1000)));
2423}
2424
2425
2426
2427/***************\
2428* LED functions *
2429\***************/
2430
2431static void
3a078876 2432ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2433{
3a078876
BC		 2434 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2435 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2436 ath5k_led_off(sc);
fa1c114f
JS		 2437 }
2438}
2439
fa1c114f 2440static void
3a078876 2441ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2442{
3a078876
BC		 2443 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2444 return;
fa1c114f 2445 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2446}
2447
2448static void
3a078876 2449ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2450{
3a078876 2451 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2452 return;
3a078876
BC		 2453 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2454}
2455
2456static void
2457ath5k_led_brightness_set(struct led_classdev *led_dev,
2458 enum led_brightness brightness)
2459{
2460 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2461 led_dev);
2462
2463 if (brightness == LED_OFF)
2464 ath5k_led_off(led->sc);
2465 else
2466 ath5k_led_on(led->sc);
2467}
2468
2469static int
2470ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2471 const char *name, char *trigger)
2472{
2473 int err;
2474
2475 led->sc = sc;
2476 strncpy(led->name, name, sizeof(led->name));
2477 led->led_dev.name = led->name;
2478 led->led_dev.default_trigger = trigger;
2479 led->led_dev.brightness_set = ath5k_led_brightness_set;
2480
2481 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2482 if (err)
2483 {
2484 ATH5K_WARN(sc, "could not register LED %s\n", name);
2485 led->sc = NULL;
fa1c114f 2486 }
3a078876 2487 return err;
fa1c114f
JS		 2488}
2489
3a078876
BC		 2490static void
2491ath5k_unregister_led(struct ath5k_led *led)
2492{
2493 if (!led->sc)
2494 return;
2495 led_classdev_unregister(&led->led_dev);
2496 ath5k_led_off(led->sc);
2497 led->sc = NULL;
2498}
2499
2500static void
2501ath5k_unregister_leds(struct ath5k_softc *sc)
2502{
2503 ath5k_unregister_led(&sc->rx_led);
2504 ath5k_unregister_led(&sc->tx_led);
2505}
2506
2507
2508static int
2509ath5k_init_leds(struct ath5k_softc *sc)
2510{
2511 int ret = 0;
2512 struct ieee80211_hw *hw = sc->hw;
2513 struct pci_dev *pdev = sc->pdev;
2514 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2515
3a078876
BC		 2516 /*
2517 * Auto-enable soft led processing for IBM cards and for
2518 * 5211 minipci cards.
2519 */
2520 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2521 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2522 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2523 sc->led_pin = 0;
734b5aa9 2524 sc->led_on = 0; /* active low */
3a078876
BC		 2525 }
2526 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2527 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2528 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2529 sc->led_pin = 1;
734b5aa9 2530 sc->led_on = 1; /* active high */
3a078876
BC		 2531 }
2532 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2533 goto out;
2534
2535 ath5k_led_enable(sc);
2536
2537 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2538 ret = ath5k_register_led(sc, &sc->rx_led, name,
2539 ieee80211_get_rx_led_name(hw));
2540 if (ret)
2541 goto out;
2542
2543 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2544 ret = ath5k_register_led(sc, &sc->tx_led, name,
2545 ieee80211_get_tx_led_name(hw));
2546out:
2547 return ret;
2548}
fa1c114f
JS		 2549
2550
2551/********************\
2552* Mac80211 functions *
2553\********************/
2554
2555static int
e039fa4a 2556ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2557{
2558 struct ath5k_softc *sc = hw->priv;
2559 struct ath5k_buf *bf;
2560 unsigned long flags;
2561 int hdrlen;
2562 int pad;
2563
2564 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2565
05c914fe 2566 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2567 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2568
2569 /*
2570 * the hardware expects the header padded to 4 byte boundaries
2571 * if this is not the case we add the padding after the header
2572 */
2573 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2574 if (hdrlen & 3) {
2575 pad = hdrlen % 4;
2576 if (skb_headroom(skb) < pad) {
2577 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2578 " headroom to pad %d\n", hdrlen, pad);
2579 return -1;
2580 }
2581 skb_push(skb, pad);
2582 memmove(skb->data, skb->data+pad, hdrlen);
2583 }
2584
fa1c114f
JS		 2585 spin_lock_irqsave(&sc->txbuflock, flags);
2586 if (list_empty(&sc->txbuf)) {
2587 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2588 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2589 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2590 return -1;
2591 }
2592 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2593 list_del(&bf->list);
2594 sc->txbuf_len--;
2595 if (list_empty(&sc->txbuf))
2596 ieee80211_stop_queues(hw);
2597 spin_unlock_irqrestore(&sc->txbuflock, flags);
2598
2599 bf->skb = skb;
2600
e039fa4a 2601 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2602 bf->skb = NULL;
2603 spin_lock_irqsave(&sc->txbuflock, flags);
2604 list_add_tail(&bf->list, &sc->txbuf);
2605 sc->txbuf_len++;
2606 spin_unlock_irqrestore(&sc->txbuflock, flags);
2607 dev_kfree_skb_any(skb);
2608 return 0;
2609 }
2610
2611 return 0;
2612}
2613
2614static int
d7dc1003 2615ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2616{
fa1c114f
JS		 2617 struct ath5k_hw *ah = sc->ah;
2618 int ret;
2619
2620 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2621
d7dc1003 2622 if (stop) {
c6e387a2 2623 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2624 ath5k_txq_cleanup(sc);
2625 ath5k_rx_stop(sc);
2626 }
fa1c114f 2627 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2628 if (ret) {
fa1c114f
JS		 2629 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2630 goto err;
2631 }
d7dc1003
JS		 2632
2633 /*
2634 * This is needed only to setup initial state
2635 * but it's best done after a reset.
2636 */
fa1c114f
JS		 2637 ath5k_hw_set_txpower_limit(sc->ah, 0);
2638
2639 ret = ath5k_rx_start(sc);
d7dc1003 2640 if (ret) {
fa1c114f
JS		 2641 ATH5K_ERR(sc, "can't start recv logic\n");
2642 goto err;
2643 }
d7dc1003 2644
fa1c114f 2645 /*
d7dc1003
JS		 2646 * Change channels and update the h/w rate map if we're switching;
2647 * e.g. 11a to 11b/g.
2648 *
2649 * We may be doing a reset in response to an ioctl that changes the
2650 * channel so update any state that might change as a result.
fa1c114f
JS		 2651 *
2652 * XXX needed?
2653 */
2654/* ath5k_chan_change(sc, c); */
fa1c114f 2655
d7dc1003
JS		 2656 ath5k_beacon_config(sc);
2657 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2658
2659 return 0;
2660err:
2661 return ret;
2662}
2663
d7dc1003
JS		 2664static int
2665ath5k_reset_wake(struct ath5k_softc *sc)
2666{
2667 int ret;
2668
2669 ret = ath5k_reset(sc, true, true);
2670 if (!ret)
2671 ieee80211_wake_queues(sc->hw);
2672
2673 return ret;
2674}
2675
fa1c114f
JS		 2676static int ath5k_start(struct ieee80211_hw *hw)
2677{
2678 return ath5k_init(hw->priv);
2679}
2680
2681static void ath5k_stop(struct ieee80211_hw *hw)
2682{
2683 ath5k_stop_hw(hw->priv);
2684}
2685
2686static int ath5k_add_interface(struct ieee80211_hw *hw,
2687 struct ieee80211_if_init_conf *conf)
2688{
2689 struct ath5k_softc *sc = hw->priv;
2690 int ret;
2691
2692 mutex_lock(&sc->lock);
32bfd35d 2693 if (sc->vif) {
fa1c114f
JS		 2694 ret = 0;
2695 goto end;
2696 }
2697
32bfd35d 2698 sc->vif = conf->vif;
fa1c114f
JS		 2699
2700 switch (conf->type) {
05c914fe
JB		 2701 case NL80211_IFTYPE_STATION:
2702 case NL80211_IFTYPE_ADHOC:
2703 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2704 sc->opmode = conf->type;
2705 break;
2706 default:
2707 ret = -EOPNOTSUPP;
2708 goto end;
2709 }
67d2e2df
JS		 2710
2711 /* Set to a reasonable value. Note that this will
2712 * be set to mac80211's value at ath5k_config(). */
2713 sc->bintval = 1000;
2714
fa1c114f
JS		 2715 ret = 0;
2716end:
2717 mutex_unlock(&sc->lock);
2718 return ret;
2719}
2720
2721static void
2722ath5k_remove_interface(struct ieee80211_hw *hw,
2723 struct ieee80211_if_init_conf *conf)
2724{
2725 struct ath5k_softc *sc = hw->priv;
2726
2727 mutex_lock(&sc->lock);
32bfd35d 2728 if (sc->vif != conf->vif)
fa1c114f
JS		 2729 goto end;
2730
32bfd35d 2731 sc->vif = NULL;
fa1c114f
JS		 2732end:
2733 mutex_unlock(&sc->lock);
2734}
2735
d8ee398d
LR		 2736/*
2737 * TODO: Phy disable/diversity etc
2738 */
fa1c114f
JS		 2739static int
2740ath5k_config(struct ieee80211_hw *hw,
2741 struct ieee80211_conf *conf)
2742{
2743 struct ath5k_softc *sc = hw->priv;
2744
e535c1ac 2745 sc->bintval = conf->beacon_int;
d8ee398d 2746 sc->power_level = conf->power_level;
fa1c114f 2747
d8ee398d 2748 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2749}
2750
2751static int
32bfd35d 2752ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2753 struct ieee80211_if_conf *conf)
2754{
2755 struct ath5k_softc *sc = hw->priv;
2756 struct ath5k_hw *ah = sc->ah;
2757 int ret;
2758
fa1c114f 2759 mutex_lock(&sc->lock);
32bfd35d 2760 if (sc->vif != vif) {
fa1c114f
JS		 2761 ret = -EIO;
2762 goto unlock;
2763 }
2764 if (conf->bssid) {
2765 /* Cache for later use during resets */
2766 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2767 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2768 * a clean way of letting us retrieve this yet. */
2769 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2770 mmiowb();
fa1c114f 2771 }
9d139c81
JB		 2772
2773 if (conf->changed & IEEE80211_IFCC_BEACON &&
05c914fe 2774 vif->type == NL80211_IFTYPE_ADHOC) {
9d139c81
JB		 2775 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2776 if (!beacon) {
2777 ret = -ENOMEM;
2778 goto unlock;
2779 }
2780 /* call old handler for now */
2781 ath5k_beacon_update(hw, beacon);
2782 }
2783
fa1c114f
JS		 2784 mutex_unlock(&sc->lock);
2785
d7dc1003 2786 return ath5k_reset_wake(sc);
fa1c114f
JS		 2787unlock:
2788 mutex_unlock(&sc->lock);
2789 return ret;
2790}
2791
2792#define SUPPORTED_FIF_FLAGS \
2793 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2794 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2795 FIF_BCN_PRBRESP_PROMISC
2796/*
2797 * o always accept unicast, broadcast, and multicast traffic
2798 * o multicast traffic for all BSSIDs will be enabled if mac80211
2799 * says it should be
2800 * o maintain current state of phy ofdm or phy cck error reception.
2801 * If the hardware detects any of these type of errors then
2802 * ath5k_hw_get_rx_filter() will pass to us the respective
2803 * hardware filters to be able to receive these type of frames.
2804 * o probe request frames are accepted only when operating in
2805 * hostap, adhoc, or monitor modes
2806 * o enable promiscuous mode according to the interface state
2807 * o accept beacons:
2808 * - when operating in adhoc mode so the 802.11 layer creates
2809 * node table entries for peers,
2810 * - when operating in station mode for collecting rssi data when
2811 * the station is otherwise quiet, or
2812 * - when scanning
2813 */
2814static void ath5k_configure_filter(struct ieee80211_hw *hw,
2815 unsigned int changed_flags,
2816 unsigned int *new_flags,
2817 int mc_count, struct dev_mc_list *mclist)
2818{
2819 struct ath5k_softc *sc = hw->priv;
2820 struct ath5k_hw *ah = sc->ah;
2821 u32 mfilt[2], val, rfilt;
2822 u8 pos;
2823 int i;
2824
2825 mfilt[0] = 0;
2826 mfilt[1] = 0;
2827
2828 /* Only deal with supported flags */
2829 changed_flags &= SUPPORTED_FIF_FLAGS;
2830 *new_flags &= SUPPORTED_FIF_FLAGS;
2831
2832 /* If HW detects any phy or radar errors, leave those filters on.
2833 * Also, always enable Unicast, Broadcasts and Multicast
2834 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2835 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2836 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2837 AR5K_RX_FILTER_MCAST);
2838
2839 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2840 if (*new_flags & FIF_PROMISC_IN_BSS) {
2841 rfilt |= AR5K_RX_FILTER_PROM;
2842 __set_bit(ATH_STAT_PROMISC, sc->status);
2843 }
2844 else
2845 __clear_bit(ATH_STAT_PROMISC, sc->status);
2846 }
2847
2848 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2849 if (*new_flags & FIF_ALLMULTI) {
2850 mfilt[0] = ~0;
2851 mfilt[1] = ~0;
2852 } else {
2853 for (i = 0; i < mc_count; i++) {
2854 if (!mclist)
2855 break;
2856 /* calculate XOR of eight 6-bit values */
533dd1b0 2857 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2858 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2859 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2860 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2861 pos &= 0x3f;
2862 mfilt[pos / 32] |= (1 << (pos % 32));
2863 /* XXX: we might be able to just do this instead,
2864 * but not sure, needs testing, if we do use this we'd
2865 * neet to inform below to not reset the mcast */
2866 /* ath5k_hw_set_mcast_filterindex(ah,
2867 * mclist->dmi_addr[5]); */
2868 mclist = mclist->next;
2869 }
2870 }
2871
2872 /* This is the best we can do */
2873 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2874 rfilt |= AR5K_RX_FILTER_PHYERR;
2875
2876 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2877 * and probes for any BSSID, this needs testing */
2878 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2879 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2880
2881 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2882 * set we should only pass on control frames for this
2883 * station. This needs testing. I believe right now this
2884 * enables *all* control frames, which is OK.. but
2885 * but we should see if we can improve on granularity */
2886 if (*new_flags & FIF_CONTROL)
2887 rfilt |= AR5K_RX_FILTER_CONTROL;
2888
2889 /* Additional settings per mode -- this is per ath5k */
2890
2891 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2892
05c914fe 2893 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2894 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2895 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2896 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2897 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2898 if (sc->opmode != NL80211_IFTYPE_AP &&
2899 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2900 test_bit(ATH_STAT_PROMISC, sc->status))
2901 rfilt |= AR5K_RX_FILTER_PROM;
05c914fe
JB		 2902 if (sc->opmode == NL80211_IFTYPE_STATION ||
2903 sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 2904 rfilt |= AR5K_RX_FILTER_BEACON;
2905 }
2906
2907 /* Set filters */
2908 ath5k_hw_set_rx_filter(ah,rfilt);
2909
2910 /* Set multicast bits */
2911 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2912 /* Set the cached hw filter flags, this will alter actually
2913 * be set in HW */
2914 sc->filter_flags = rfilt;
2915}
2916
2917static int
2918ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2919 const u8 *local_addr, const u8 *addr,
2920 struct ieee80211_key_conf *key)
2921{
2922 struct ath5k_softc *sc = hw->priv;
2923 int ret = 0;
2924
2925 switch(key->alg) {
2926 case ALG_WEP:
6844e63a
LR		 2927 /* XXX: fix hardware encryption, its not working. For now
2928 * allow software encryption */
2929 /* break; */
fa1c114f
JS		 2930 case ALG_TKIP:
2931 case ALG_CCMP:
2932 return -EOPNOTSUPP;
2933 default:
2934 WARN_ON(1);
2935 return -EINVAL;
2936 }
2937
2938 mutex_lock(&sc->lock);
2939
2940 switch (cmd) {
2941 case SET_KEY:
2942 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2943 if (ret) {
2944 ATH5K_ERR(sc, "can't set the key\n");
2945 goto unlock;
2946 }
2947 __set_bit(key->keyidx, sc->keymap);
2948 key->hw_key_idx = key->keyidx;
2949 break;
2950 case DISABLE_KEY:
2951 ath5k_hw_reset_key(sc->ah, key->keyidx);
2952 __clear_bit(key->keyidx, sc->keymap);
2953 break;
2954 default:
2955 ret = -EINVAL;
2956 goto unlock;
2957 }
2958
2959unlock:
274c7c36 2960 mmiowb();
fa1c114f
JS		 2961 mutex_unlock(&sc->lock);
2962 return ret;
2963}
2964
2965static int
2966ath5k_get_stats(struct ieee80211_hw *hw,
2967 struct ieee80211_low_level_stats *stats)
2968{
2969 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2970 struct ath5k_hw *ah = sc->ah;
2971
2972 /* Force update */
2973 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2974
2975 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2976
2977 return 0;
2978}
2979
2980static int
2981ath5k_get_tx_stats(struct ieee80211_hw *hw,
2982 struct ieee80211_tx_queue_stats *stats)
2983{
2984 struct ath5k_softc *sc = hw->priv;
2985
2986 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2987
2988 return 0;
2989}
2990
2991static u64
2992ath5k_get_tsf(struct ieee80211_hw *hw)
2993{
2994 struct ath5k_softc *sc = hw->priv;
2995
2996 return ath5k_hw_get_tsf64(sc->ah);
2997}
2998
2999static void
3000ath5k_reset_tsf(struct ieee80211_hw *hw)
3001{
3002 struct ath5k_softc *sc = hw->priv;
3003
9804b98d
BR		 3004 /*
3005 * in IBSS mode we need to update the beacon timers too.
3006 * this will also reset the TSF if we call it with 0
3007 */
05c914fe 3008 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3009 ath5k_beacon_update_timers(sc, 0);
3010 else
3011 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3012}
3013
3014static int
e039fa4a 3015ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3016{
3017 struct ath5k_softc *sc = hw->priv;
00482973 3018 unsigned long flags;
fa1c114f
JS		 3019 int ret;
3020
3021 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3022
05c914fe 3023 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 3024 ret = -EIO;
3025 goto end;
3026 }
3027
00482973 3028 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3029 ath5k_txbuf_free(sc, sc->bbuf);
3030 sc->bbuf->skb = skb;
e039fa4a 3031 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3032 if (ret)
3033 sc->bbuf->skb = NULL;
00482973
JS		 3034 spin_unlock_irqrestore(&sc->block, flags);
3035 if (!ret) {
fa1c114f 3036 ath5k_beacon_config(sc);
274c7c36
JS		 3037 mmiowb();
3038 }
fa1c114f
JS		 3039
3040end:
fa1c114f
JS		 3041 return ret;
3042}
3043
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