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mac80211: add multi-rate retry support
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 75MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 98 { 0 }
99};
100MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102/* Known SREVs */
103static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 104 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
105 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
106 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
107 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
108 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
109 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
110 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
111 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
112 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
113 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
114 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
115 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
116 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
117 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
118 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
119 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
120 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
121 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
135 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
136 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
137 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 138 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
139 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
140};
141
63266a65
BR		 142static struct ieee80211_rate ath5k_rates[] = {
143 { .bitrate = 10,
144 .hw_value = ATH5K_RATE_CODE_1M, },
145 { .bitrate = 20,
146 .hw_value = ATH5K_RATE_CODE_2M,
147 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 { .bitrate = 55,
150 .hw_value = ATH5K_RATE_CODE_5_5M,
151 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 { .bitrate = 110,
154 .hw_value = ATH5K_RATE_CODE_11M,
155 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 60,
158 .hw_value = ATH5K_RATE_CODE_6M,
159 .flags = 0 },
160 { .bitrate = 90,
161 .hw_value = ATH5K_RATE_CODE_9M,
162 .flags = 0 },
163 { .bitrate = 120,
164 .hw_value = ATH5K_RATE_CODE_12M,
165 .flags = 0 },
166 { .bitrate = 180,
167 .hw_value = ATH5K_RATE_CODE_18M,
168 .flags = 0 },
169 { .bitrate = 240,
170 .hw_value = ATH5K_RATE_CODE_24M,
171 .flags = 0 },
172 { .bitrate = 360,
173 .hw_value = ATH5K_RATE_CODE_36M,
174 .flags = 0 },
175 { .bitrate = 480,
176 .hw_value = ATH5K_RATE_CODE_48M,
177 .flags = 0 },
178 { .bitrate = 540,
179 .hw_value = ATH5K_RATE_CODE_54M,
180 .flags = 0 },
181 /* XR missing */
182};
183
fa1c114f
JS		 184/*
185 * Prototypes - PCI stack related functions
186 */
187static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
188 const struct pci_device_id *id);
189static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
190#ifdef CONFIG_PM
191static int ath5k_pci_suspend(struct pci_dev *pdev,
192 pm_message_t state);
193static int ath5k_pci_resume(struct pci_dev *pdev);
194#else
195#define ath5k_pci_suspend NULL
196#define ath5k_pci_resume NULL
197#endif /* CONFIG_PM */
198
04a9e451 199static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 200 .name = "ath5k_pci",
201 .id_table = ath5k_pci_id_table,
202 .probe = ath5k_pci_probe,
203 .remove = __devexit_p(ath5k_pci_remove),
204 .suspend = ath5k_pci_suspend,
205 .resume = ath5k_pci_resume,
206};
207
208
209
210/*
211 * Prototypes - MAC 802.11 stack related functions
212 */
e039fa4a 213static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 214static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
215static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 216static int ath5k_start(struct ieee80211_hw *hw);
217static void ath5k_stop(struct ieee80211_hw *hw);
218static int ath5k_add_interface(struct ieee80211_hw *hw,
219 struct ieee80211_if_init_conf *conf);
220static void ath5k_remove_interface(struct ieee80211_hw *hw,
221 struct ieee80211_if_init_conf *conf);
222static int ath5k_config(struct ieee80211_hw *hw,
223 struct ieee80211_conf *conf);
32bfd35d
JB		 224static int ath5k_config_interface(struct ieee80211_hw *hw,
225 struct ieee80211_vif *vif,
fa1c114f
JS		 226 struct ieee80211_if_conf *conf);
227static void ath5k_configure_filter(struct ieee80211_hw *hw,
228 unsigned int changed_flags,
229 unsigned int *new_flags,
230 int mc_count, struct dev_mc_list *mclist);
231static int ath5k_set_key(struct ieee80211_hw *hw,
232 enum set_key_cmd cmd,
233 const u8 *local_addr, const u8 *addr,
234 struct ieee80211_key_conf *key);
235static int ath5k_get_stats(struct ieee80211_hw *hw,
236 struct ieee80211_low_level_stats *stats);
237static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
238 struct ieee80211_tx_queue_stats *stats);
239static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
240static void ath5k_reset_tsf(struct ieee80211_hw *hw);
241static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 242 struct sk_buff *skb);
fa1c114f
JS		 243
244static struct ieee80211_ops ath5k_hw_ops = {
245 .tx = ath5k_tx,
246 .start = ath5k_start,
247 .stop = ath5k_stop,
248 .add_interface = ath5k_add_interface,
249 .remove_interface = ath5k_remove_interface,
250 .config = ath5k_config,
251 .config_interface = ath5k_config_interface,
252 .configure_filter = ath5k_configure_filter,
253 .set_key = ath5k_set_key,
254 .get_stats = ath5k_get_stats,
255 .conf_tx = NULL,
256 .get_tx_stats = ath5k_get_tx_stats,
257 .get_tsf = ath5k_get_tsf,
258 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 259};
260
261/*
262 * Prototypes - Internal functions
263 */
264/* Attach detach */
265static int ath5k_attach(struct pci_dev *pdev,
266 struct ieee80211_hw *hw);
267static void ath5k_detach(struct pci_dev *pdev,
268 struct ieee80211_hw *hw);
269/* Channel/mode setup */
270static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 271static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
272 struct ieee80211_channel *channels,
273 unsigned int mode,
274 unsigned int max);
63266a65 275static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 276static int ath5k_chan_set(struct ath5k_softc *sc,
277 struct ieee80211_channel *chan);
278static void ath5k_setcurmode(struct ath5k_softc *sc,
279 unsigned int mode);
280static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 281
fa1c114f
JS		 282/* Descriptor setup */
283static int ath5k_desc_alloc(struct ath5k_softc *sc,
284 struct pci_dev *pdev);
285static void ath5k_desc_free(struct ath5k_softc *sc,
286 struct pci_dev *pdev);
287/* Buffers setup */
288static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf);
290static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 291 struct ath5k_buf *bf);
fa1c114f
JS		 292static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
293 struct ath5k_buf *bf)
294{
295 BUG_ON(!bf);
296 if (!bf->skb)
297 return;
298 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
299 PCI_DMA_TODEVICE);
00482973 300 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 301 bf->skb = NULL;
302}
303
304/* Queues setup */
305static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
306 int qtype, int subtype);
307static int ath5k_beaconq_setup(struct ath5k_hw *ah);
308static int ath5k_beaconq_config(struct ath5k_softc *sc);
309static void ath5k_txq_drainq(struct ath5k_softc *sc,
310 struct ath5k_txq *txq);
311static void ath5k_txq_cleanup(struct ath5k_softc *sc);
312static void ath5k_txq_release(struct ath5k_softc *sc);
313/* Rx handling */
314static int ath5k_rx_start(struct ath5k_softc *sc);
315static void ath5k_rx_stop(struct ath5k_softc *sc);
316static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
317 struct ath5k_desc *ds,
b47f407b
BR		 318 struct sk_buff *skb,
319 struct ath5k_rx_status *rs);
fa1c114f
JS		 320static void ath5k_tasklet_rx(unsigned long data);
321/* Tx handling */
322static void ath5k_tx_processq(struct ath5k_softc *sc,
323 struct ath5k_txq *txq);
324static void ath5k_tasklet_tx(unsigned long data);
325/* Beacon handling */
326static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 327 struct ath5k_buf *bf);
fa1c114f
JS		 328static void ath5k_beacon_send(struct ath5k_softc *sc);
329static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 330static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 331
332static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
333{
334 u64 tsf = ath5k_hw_get_tsf64(ah);
335
336 if ((tsf & 0x7fff) < rstamp)
337 tsf -= 0x8000;
338
339 return (tsf & ~0x7fff) | rstamp;
340}
341
342/* Interrupt handling */
343static int ath5k_init(struct ath5k_softc *sc);
344static int ath5k_stop_locked(struct ath5k_softc *sc);
345static int ath5k_stop_hw(struct ath5k_softc *sc);
346static irqreturn_t ath5k_intr(int irq, void *dev_id);
347static void ath5k_tasklet_reset(unsigned long data);
348
349static void ath5k_calibrate(unsigned long data);
350/* LED functions */
3a078876
BC		 351static int ath5k_init_leds(struct ath5k_softc *sc);
352static void ath5k_led_enable(struct ath5k_softc *sc);
353static void ath5k_led_off(struct ath5k_softc *sc);
354static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 355
356/*
357 * Module init/exit functions
358 */
359static int __init
360init_ath5k_pci(void)
361{
362 int ret;
363
364 ath5k_debug_init();
365
04a9e451 366 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 367 if (ret) {
368 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
369 return ret;
370 }
371
372 return 0;
373}
374
375static void __exit
376exit_ath5k_pci(void)
377{
04a9e451 378 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 379
380 ath5k_debug_finish();
381}
382
383module_init(init_ath5k_pci);
384module_exit(exit_ath5k_pci);
385
386
387/********************\
388* PCI Initialization *
389\********************/
390
391static const char *
392ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
393{
394 const char *name = "xxxxx";
395 unsigned int i;
396
397 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
398 if (srev_names[i].sr_type != type)
399 continue;
75d0edb8
NK		 400
401 if ((val & 0xf0) == srev_names[i].sr_val)
402 name = srev_names[i].sr_name;
403
404 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 405 name = srev_names[i].sr_name;
406 break;
407 }
408 }
409
410 return name;
411}
412
413static int __devinit
414ath5k_pci_probe(struct pci_dev *pdev,
415 const struct pci_device_id *id)
416{
417 void __iomem *mem;
418 struct ath5k_softc *sc;
419 struct ieee80211_hw *hw;
420 int ret;
421 u8 csz;
422
423 ret = pci_enable_device(pdev);
424 if (ret) {
425 dev_err(&pdev->dev, "can't enable device\n");
426 goto err;
427 }
428
429 /* XXX 32-bit addressing only */
430 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
431 if (ret) {
432 dev_err(&pdev->dev, "32-bit DMA not available\n");
433 goto err_dis;
434 }
435
436 /*
437 * Cache line size is used to size and align various
438 * structures used to communicate with the hardware.
439 */
440 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
441 if (csz == 0) {
442 /*
443 * Linux 2.4.18 (at least) writes the cache line size
444 * register as a 16-bit wide register which is wrong.
445 * We must have this setup properly for rx buffer
446 * DMA to work so force a reasonable value here if it
447 * comes up zero.
448 */
449 csz = L1_CACHE_BYTES / sizeof(u32);
450 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
451 }
452 /*
453 * The default setting of latency timer yields poor results,
454 * set it to the value used by other systems. It may be worth
455 * tweaking this setting more.
456 */
457 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
458
459 /* Enable bus mastering */
460 pci_set_master(pdev);
461
462 /*
463 * Disable the RETRY_TIMEOUT register (0x41) to keep
464 * PCI Tx retries from interfering with C3 CPU state.
465 */
466 pci_write_config_byte(pdev, 0x41, 0);
467
468 ret = pci_request_region(pdev, 0, "ath5k");
469 if (ret) {
470 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
471 goto err_dis;
472 }
473
474 mem = pci_iomap(pdev, 0, 0);
475 if (!mem) {
476 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
477 ret = -EIO;
478 goto err_reg;
479 }
480
481 /*
482 * Allocate hw (mac80211 main struct)
483 * and hw->priv (driver private data)
484 */
485 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
486 if (hw == NULL) {
487 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
488 ret = -ENOMEM;
489 goto err_map;
490 }
491
492 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
493
494 /* Initialize driver private data */
495 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 496 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
497 IEEE80211_HW_SIGNAL_DBM |
498 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 499
500 hw->wiphy->interface_modes =
501 BIT(NL80211_IFTYPE_STATION) |
502 BIT(NL80211_IFTYPE_ADHOC) |
503 BIT(NL80211_IFTYPE_MESH_POINT);
504
fa1c114f
JS		 505 hw->extra_tx_headroom = 2;
506 hw->channel_change_time = 5000;
fa1c114f
JS		 507 sc = hw->priv;
508 sc->hw = hw;
509 sc->pdev = pdev;
510
511 ath5k_debug_init_device(sc);
512
513 /*
514 * Mark the device as detached to avoid processing
515 * interrupts until setup is complete.
516 */
517 __set_bit(ATH_STAT_INVALID, sc->status);
518
519 sc->iobase = mem; /* So we can unmap it on detach */
520 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 521 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 522 mutex_init(&sc->lock);
523 spin_lock_init(&sc->rxbuflock);
524 spin_lock_init(&sc->txbuflock);
00482973 525 spin_lock_init(&sc->block);
fa1c114f
JS		 526
527 /* Set private data */
528 pci_set_drvdata(pdev, hw);
529
fa1c114f
JS		 530 /* Setup interrupt handler */
531 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
532 if (ret) {
533 ATH5K_ERR(sc, "request_irq failed\n");
534 goto err_free;
535 }
536
537 /* Initialize device */
538 sc->ah = ath5k_hw_attach(sc, id->driver_data);
539 if (IS_ERR(sc->ah)) {
540 ret = PTR_ERR(sc->ah);
541 goto err_irq;
542 }
543
544 /* Finish private driver data initialization */
545 ret = ath5k_attach(pdev, hw);
546 if (ret)
547 goto err_ah;
548
549 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 550 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 551 sc->ah->ah_mac_srev,
552 sc->ah->ah_phy_revision);
553
400ec45a 554 if (!sc->ah->ah_single_chip) {
fa1c114f 555 /* Single chip radio (!RF5111) */
400ec45a
LR		 556 if (sc->ah->ah_radio_5ghz_revision &&
557 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 558 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 559 if (!test_bit(AR5K_MODE_11A,
560 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 561 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 562 ath5k_chip_name(AR5K_VERSION_RAD,
563 sc->ah->ah_radio_5ghz_revision),
564 sc->ah->ah_radio_5ghz_revision);
565 /* No 2GHz support (5110 and some
566 * 5Ghz only cards) -> report 5Ghz radio */
567 } else if (!test_bit(AR5K_MODE_11B,
568 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 569 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 570 ath5k_chip_name(AR5K_VERSION_RAD,
571 sc->ah->ah_radio_5ghz_revision),
572 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 573 /* Multiband radio */
574 } else {
575 ATH5K_INFO(sc, "RF%s multiband radio found"
576 " (0x%x)\n",
400ec45a
LR		 577 ath5k_chip_name(AR5K_VERSION_RAD,
578 sc->ah->ah_radio_5ghz_revision),
579 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 580 }
581 }
400ec45a
LR		 582 /* Multi chip radio (RF5111 - RF2111) ->
583 * report both 2GHz/5GHz radios */
584 else if (sc->ah->ah_radio_5ghz_revision &&
585 sc->ah->ah_radio_2ghz_revision){
fa1c114f 586 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 587 ath5k_chip_name(AR5K_VERSION_RAD,
588 sc->ah->ah_radio_5ghz_revision),
589 sc->ah->ah_radio_5ghz_revision);
fa1c114f 590 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 591 ath5k_chip_name(AR5K_VERSION_RAD,
592 sc->ah->ah_radio_2ghz_revision),
593 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 594 }
595 }
596
597
598 /* ready to process interrupts */
599 __clear_bit(ATH_STAT_INVALID, sc->status);
600
601 return 0;
602err_ah:
603 ath5k_hw_detach(sc->ah);
604err_irq:
605 free_irq(pdev->irq, sc);
606err_free:
fa1c114f
JS		 607 ieee80211_free_hw(hw);
608err_map:
609 pci_iounmap(pdev, mem);
610err_reg:
611 pci_release_region(pdev, 0);
612err_dis:
613 pci_disable_device(pdev);
614err:
615 return ret;
616}
617
618static void __devexit
619ath5k_pci_remove(struct pci_dev *pdev)
620{
621 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
622 struct ath5k_softc *sc = hw->priv;
623
624 ath5k_debug_finish_device(sc);
625 ath5k_detach(pdev, hw);
626 ath5k_hw_detach(sc->ah);
627 free_irq(pdev->irq, sc);
fa1c114f
JS		 628 pci_iounmap(pdev, sc->iobase);
629 pci_release_region(pdev, 0);
630 pci_disable_device(pdev);
631 ieee80211_free_hw(hw);
632}
633
634#ifdef CONFIG_PM
635static int
636ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
637{
638 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
639 struct ath5k_softc *sc = hw->priv;
640
3a078876 641 ath5k_led_off(sc);
fa1c114f
JS		 642
643 ath5k_stop_hw(sc);
3e4242b9
JS		 644
645 free_irq(pdev->irq, sc);
fa1c114f
JS		 646 pci_save_state(pdev);
647 pci_disable_device(pdev);
648 pci_set_power_state(pdev, PCI_D3hot);
649
650 return 0;
651}
652
653static int
654ath5k_pci_resume(struct pci_dev *pdev)
655{
656 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
657 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 658 struct ath5k_hw *ah = sc->ah;
659 int i, err;
fa1c114f 660
3e4242b9 661 pci_restore_state(pdev);
fa1c114f
JS		 662
663 err = pci_enable_device(pdev);
664 if (err)
665 return err;
666
fa1c114f
JS		 667 /*
668 * Suspend/Resume resets the PCI configuration space, so we have to
669 * re-disable the RETRY_TIMEOUT register (0x41) to keep
670 * PCI Tx retries from interfering with C3 CPU state
671 */
672 pci_write_config_byte(pdev, 0x41, 0);
673
3e4242b9
JS		 674 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
675 if (err) {
676 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 677 goto err_no_irq;
3e4242b9
JS		 678 }
679
680 err = ath5k_init(sc);
681 if (err)
682 goto err_irq;
3a078876 683 ath5k_led_enable(sc);
fa1c114f 684
247ae449
JL		 685 /*
686 * Reset the key cache since some parts do not
687 * reset the contents on initial power up or resume.
688 *
689 * FIXME: This may need to be revisited when mac80211 becomes
690 * aware of suspend/resume.
691 */
692 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
693 ath5k_hw_reset_key(ah, i);
694
fa1c114f 695 return 0;
3e4242b9
JS		 696err_irq:
697 free_irq(pdev->irq, sc);
37465c8a 698err_no_irq:
3e4242b9
JS		 699 pci_disable_device(pdev);
700 return err;
fa1c114f
JS		 701}
702#endif /* CONFIG_PM */
703
704
fa1c114f
JS		 705/***********************\
706* Driver Initialization *
707\***********************/
708
709static int
710ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
711{
712 struct ath5k_softc *sc = hw->priv;
713 struct ath5k_hw *ah = sc->ah;
714 u8 mac[ETH_ALEN];
715 unsigned int i;
716 int ret;
717
718 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
719
720 /*
721 * Check if the MAC has multi-rate retry support.
722 * We do this by trying to setup a fake extended
723 * descriptor. MAC's that don't have support will
724 * return false w/o doing anything. MAC's that do
725 * support it will return true w/o doing anything.
726 */
c6e387a2 727 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 728 if (ret < 0)
729 goto err;
730 if (ret > 0)
fa1c114f
JS		 731 __set_bit(ATH_STAT_MRRETRY, sc->status);
732
733 /*
734 * Reset the key cache since some parts do not
735 * reset the contents on initial power up.
736 */
c65638a7 737 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 738 ath5k_hw_reset_key(ah, i);
739
740 /*
741 * Collect the channel list. The 802.11 layer
742 * is resposible for filtering this list based
743 * on settings like the phy mode and regulatory
744 * domain restrictions.
745 */
63266a65 746 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 747 if (ret) {
748 ATH5K_ERR(sc, "can't get channels\n");
749 goto err;
750 }
751
752 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 753 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
754 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 755 else
d8ee398d 756 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 757
758 /*
759 * Allocate tx+rx descriptors and populate the lists.
760 */
761 ret = ath5k_desc_alloc(sc, pdev);
762 if (ret) {
763 ATH5K_ERR(sc, "can't allocate descriptors\n");
764 goto err;
765 }
766
767 /*
768 * Allocate hardware transmit queues: one queue for
769 * beacon frames and one data queue for each QoS
770 * priority. Note that hw functions handle reseting
771 * these queues at the needed time.
772 */
773 ret = ath5k_beaconq_setup(ah);
774 if (ret < 0) {
775 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
776 goto err_desc;
777 }
778 sc->bhalq = ret;
779
780 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
781 if (IS_ERR(sc->txq)) {
782 ATH5K_ERR(sc, "can't setup xmit queue\n");
783 ret = PTR_ERR(sc->txq);
784 goto err_bhal;
785 }
786
787 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
788 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
789 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
790 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 791
792 ath5k_hw_get_lladdr(ah, mac);
793 SET_IEEE80211_PERM_ADDR(hw, mac);
794 /* All MAC address bits matter for ACKs */
795 memset(sc->bssidmask, 0xff, ETH_ALEN);
796 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
797
798 ret = ieee80211_register_hw(hw);
799 if (ret) {
800 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
801 goto err_queues;
802 }
803
3a078876
BC		 804 ath5k_init_leds(sc);
805
fa1c114f
JS		 806 return 0;
807err_queues:
808 ath5k_txq_release(sc);
809err_bhal:
810 ath5k_hw_release_tx_queue(ah, sc->bhalq);
811err_desc:
812 ath5k_desc_free(sc, pdev);
813err:
814 return ret;
815}
816
817static void
818ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
819{
820 struct ath5k_softc *sc = hw->priv;
821
822 /*
823 * NB: the order of these is important:
824 * o call the 802.11 layer before detaching ath5k_hw to
825 * insure callbacks into the driver to delete global
826 * key cache entries can be handled
827 * o reclaim the tx queue data structures after calling
828 * the 802.11 layer as we'll get called back to reclaim
829 * node state and potentially want to use them
830 * o to cleanup the tx queues the hal is called, so detach
831 * it last
832 * XXX: ??? detach ath5k_hw ???
833 * Other than that, it's straightforward...
834 */
835 ieee80211_unregister_hw(hw);
836 ath5k_desc_free(sc, pdev);
837 ath5k_txq_release(sc);
838 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 839 ath5k_unregister_leds(sc);
fa1c114f
JS		 840
841 /*
842 * NB: can't reclaim these until after ieee80211_ifdetach
843 * returns because we'll get called back to reclaim node
844 * state and potentially want to use them.
845 */
846}
847
848
849
850
851/********************\
852* Channel/mode setup *
853\********************/
854
855/*
856 * Convert IEEE channel number to MHz frequency.
857 */
858static inline short
859ath5k_ieee2mhz(short chan)
860{
861 if (chan <= 14 || chan >= 27)
862 return ieee80211chan2mhz(chan);
863 else
864 return 2212 + chan * 20;
865}
866
fa1c114f
JS		 867static unsigned int
868ath5k_copy_channels(struct ath5k_hw *ah,
869 struct ieee80211_channel *channels,
870 unsigned int mode,
871 unsigned int max)
872{
d8ee398d 873 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 874
875 if (!test_bit(mode, ah->ah_modes))
876 return 0;
877
fa1c114f 878 switch (mode) {
d8ee398d
LR		 879 case AR5K_MODE_11A:
880 case AR5K_MODE_11A_TURBO:
fa1c114f 881 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 882 size = 220 ;
fa1c114f
JS		 883 chfreq = CHANNEL_5GHZ;
884 break;
d8ee398d
LR		 885 case AR5K_MODE_11B:
886 case AR5K_MODE_11G:
887 case AR5K_MODE_11G_TURBO:
888 size = 26;
fa1c114f
JS		 889 chfreq = CHANNEL_2GHZ;
890 break;
891 default:
892 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
893 return 0;
894 }
895
896 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 897 ch = i + 1 ;
898 freq = ath5k_ieee2mhz(ch);
fa1c114f 899
d8ee398d
LR		 900 /* Check if channel is supported by the chipset */
901 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 902 continue;
903
d8ee398d
LR		 904 /* Write channel info and increment counter */
905 channels[count].center_freq = freq;
a3f4b914
LR		 906 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
907 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 908 switch (mode) {
909 case AR5K_MODE_11A:
910 case AR5K_MODE_11G:
911 channels[count].hw_value = chfreq | CHANNEL_OFDM;
912 break;
913 case AR5K_MODE_11A_TURBO:
914 case AR5K_MODE_11G_TURBO:
915 channels[count].hw_value = chfreq |
916 CHANNEL_OFDM | CHANNEL_TURBO;
917 break;
918 case AR5K_MODE_11B:
d8ee398d
LR		 919 channels[count].hw_value = CHANNEL_B;
920 }
fa1c114f 921
fa1c114f
JS		 922 count++;
923 max--;
924 }
925
926 return count;
927}
928
63266a65
BR		 929static void
930ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
931{
932 u8 i;
933
934 for (i = 0; i < AR5K_MAX_RATES; i++)
935 sc->rate_idx[b->band][i] = -1;
936
937 for (i = 0; i < b->n_bitrates; i++) {
938 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
939 if (b->bitrates[i].hw_value_short)
940 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
941 }
942}
943
d8ee398d 944static int
63266a65 945ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 946{
947 struct ath5k_softc *sc = hw->priv;
d8ee398d 948 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 949 struct ieee80211_supported_band *sband;
950 int max_c, count_c = 0;
951 int i;
fa1c114f 952
d8ee398d 953 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 954 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 955
956 /* 2GHz band */
63266a65
BR		 957 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
958 sband->band = IEEE80211_BAND_2GHZ;
959 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 960
63266a65
BR		 961 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
962 /* G mode */
963 memcpy(sband->bitrates, &ath5k_rates[0],
964 sizeof(struct ieee80211_rate) * 12);
965 sband->n_bitrates = 12;
fa1c114f 966
d8ee398d 967 sband->channels = sc->channels;
d8ee398d 968 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 969 AR5K_MODE_11G, max_c);
fa1c114f 970
63266a65 971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 972 count_c = sband->n_channels;
63266a65
BR		 973 max_c -= count_c;
974 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
975 /* B mode */
976 memcpy(sband->bitrates, &ath5k_rates[0],
977 sizeof(struct ieee80211_rate) * 4);
978 sband->n_bitrates = 4;
979
980 /* 5211 only supports B rates and uses 4bit rate codes
981 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
982 * fix them up here:
983 */
984 if (ah->ah_version == AR5K_AR5211) {
985 for (i = 0; i < 4; i++) {
986 sband->bitrates[i].hw_value =
987 sband->bitrates[i].hw_value & 0xF;
988 sband->bitrates[i].hw_value_short =
989 sband->bitrates[i].hw_value_short & 0xF;
990 }
991 }
fa1c114f 992
63266a65
BR		 993 sband->channels = sc->channels;
994 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
995 AR5K_MODE_11B, max_c);
d8ee398d 996
63266a65
BR		 997 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
998 count_c = sband->n_channels;
d8ee398d 999 max_c -= count_c;
fa1c114f 1000 }
63266a65 1001 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1002
63266a65 1003 /* 5GHz band, A mode */
400ec45a 1004 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1005 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1006 sband->band = IEEE80211_BAND_5GHZ;
1007 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1008
63266a65
BR		 1009 memcpy(sband->bitrates, &ath5k_rates[4],
1010 sizeof(struct ieee80211_rate) * 8);
1011 sband->n_bitrates = 8;
fa1c114f 1012
63266a65 1013 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1014 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1015 AR5K_MODE_11A, max_c);
1016
d8ee398d
LR		 1017 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1018 }
63266a65 1019 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1020
b446197c 1021 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1022
1023 return 0;
fa1c114f
JS		 1024}
1025
1026/*
1027 * Set/change channels. If the channel is really being changed,
1028 * it's done by reseting the chip. To accomplish this we must
1029 * first cleanup any pending DMA, then restart stuff after a la
1030 * ath5k_init.
1031 */
1032static int
1033ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034{
d8ee398d
LR		 1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1037
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1040
1041 sc->curchan = chan;
1042 sc->curband = &sc->sbands[chan->band];
fa1c114f 1043
fa1c114f
JS		 1044 /*
1045 * To switch channels clear any pending DMA operations;
1046 * wait long enough for the RX fifo to drain, reset the
1047 * hardware at the new frequency, and then re-enable
1048 * the relevant bits of the h/w.
1049 */
d7dc1003 1050 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1051 }
1052
1053 return 0;
1054}
1055
1056static void
1057ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1058{
fa1c114f 1059 sc->curmode = mode;
d8ee398d 1060
400ec45a 1061 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1062 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1063 } else {
1064 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1065 }
fa1c114f
JS		 1066}
1067
1068static void
1069ath5k_mode_setup(struct ath5k_softc *sc)
1070{
1071 struct ath5k_hw *ah = sc->ah;
1072 u32 rfilt;
1073
1074 /* configure rx filter */
1075 rfilt = sc->filter_flags;
1076 ath5k_hw_set_rx_filter(ah, rfilt);
1077
1078 if (ath5k_hw_hasbssidmask(ah))
1079 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1080
1081 /* configure operational mode */
1082 ath5k_hw_set_opmode(ah);
1083
1084 ath5k_hw_set_mcast_filter(ah, 0, 0);
1085 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1086}
1087
d8ee398d 1088static inline int
63266a65
BR		 1089ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1090{
1091 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1092 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1093}
1094
fa1c114f
JS		 1095/***************\
1096* Buffers setup *
1097\***************/
1098
1099static int
1100ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1101{
1102 struct ath5k_hw *ah = sc->ah;
1103 struct sk_buff *skb = bf->skb;
1104 struct ath5k_desc *ds;
1105
1106 if (likely(skb == NULL)) {
1107 unsigned int off;
1108
1109 /*
1110 * Allocate buffer with headroom_needed space for the
1111 * fake physical layer header at the start.
1112 */
1113 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1114 if (unlikely(skb == NULL)) {
1115 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1116 sc->rxbufsize + sc->cachelsz - 1);
1117 return -ENOMEM;
1118 }
1119 /*
1120 * Cache-line-align. This is important (for the
1121 * 5210 at least) as not doing so causes bogus data
1122 * in rx'd frames.
1123 */
1124 off = ((unsigned long)skb->data) % sc->cachelsz;
1125 if (off != 0)
1126 skb_reserve(skb, sc->cachelsz - off);
1127
1128 bf->skb = skb;
1129 bf->skbaddr = pci_map_single(sc->pdev,
1130 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1131 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1132 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1133 dev_kfree_skb(skb);
1134 bf->skb = NULL;
1135 return -ENOMEM;
1136 }
1137 }
1138
1139 /*
1140 * Setup descriptors. For receive we always terminate
1141 * the descriptor list with a self-linked entry so we'll
1142 * not get overrun under high load (as can happen with a
1143 * 5212 when ANI processing enables PHY error frames).
1144 *
1145 * To insure the last descriptor is self-linked we create
1146 * each descriptor as self-linked and add it to the end. As
1147 * each additional descriptor is added the previous self-linked
1148 * entry is ``fixed'' naturally. This should be safe even
1149 * if DMA is happening. When processing RX interrupts we
1150 * never remove/process the last, self-linked, entry on the
1151 * descriptor list. This insures the hardware always has
1152 * someplace to write a new frame.
1153 */
1154 ds = bf->desc;
1155 ds->ds_link = bf->daddr; /* link to self */
1156 ds->ds_data = bf->skbaddr;
c6e387a2 1157 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1158 skb_tailroom(skb), /* buffer size */
1159 0);
1160
1161 if (sc->rxlink != NULL)
1162 *sc->rxlink = bf->daddr;
1163 sc->rxlink = &ds->ds_link;
1164 return 0;
1165}
1166
1167static int
e039fa4a 1168ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1169{
1170 struct ath5k_hw *ah = sc->ah;
1171 struct ath5k_txq *txq = sc->txq;
1172 struct ath5k_desc *ds = bf->desc;
1173 struct sk_buff *skb = bf->skb;
a888d52d 1174 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1175 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1176 int ret;
1177
1178 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1179
fa1c114f
JS		 1180 /* XXX endianness */
1181 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1182 PCI_DMA_TODEVICE);
1183
e039fa4a 1184 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1185 flags |= AR5K_TXDESC_NOACK;
1186
281c56dd 1187 pktlen = skb->len;
fa1c114f 1188
d0f09804 1189 if (info->control.hw_key) {
e039fa4a 1190 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1191 pktlen += info->control.hw_key->icv_len;
fa1c114f 1192 }
fa1c114f
JS		 1193 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1194 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1195 (sc->power_level * 2),
e039fa4a
JB		 1196 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1197 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1198 if (ret)
1199 goto err_unmap;
1200
1201 ds->ds_link = 0;
1202 ds->ds_data = bf->skbaddr;
1203
1204 spin_lock_bh(&txq->lock);
1205 list_add_tail(&bf->list, &txq->q);
57ffc589 1206 sc->tx_stats[txq->qnum].len++;
fa1c114f 1207 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1208 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1209 else /* no, so only link it */
1210 *txq->link = bf->daddr;
1211
1212 txq->link = &ds->ds_link;
c6e387a2 1213 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1214 mmiowb();
fa1c114f
JS		 1215 spin_unlock_bh(&txq->lock);
1216
1217 return 0;
1218err_unmap:
1219 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1220 return ret;
1221}
1222
1223/*******************\
1224* Descriptors setup *
1225\*******************/
1226
1227static int
1228ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1229{
1230 struct ath5k_desc *ds;
1231 struct ath5k_buf *bf;
1232 dma_addr_t da;
1233 unsigned int i;
1234 int ret;
1235
1236 /* allocate descriptors */
1237 sc->desc_len = sizeof(struct ath5k_desc) *
1238 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1239 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1240 if (sc->desc == NULL) {
1241 ATH5K_ERR(sc, "can't allocate descriptors\n");
1242 ret = -ENOMEM;
1243 goto err;
1244 }
1245 ds = sc->desc;
1246 da = sc->desc_daddr;
1247 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1248 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1249
1250 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1251 sizeof(struct ath5k_buf), GFP_KERNEL);
1252 if (bf == NULL) {
1253 ATH5K_ERR(sc, "can't allocate bufptr\n");
1254 ret = -ENOMEM;
1255 goto err_free;
1256 }
1257 sc->bufptr = bf;
1258
1259 INIT_LIST_HEAD(&sc->rxbuf);
1260 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1261 bf->desc = ds;
1262 bf->daddr = da;
1263 list_add_tail(&bf->list, &sc->rxbuf);
1264 }
1265
1266 INIT_LIST_HEAD(&sc->txbuf);
1267 sc->txbuf_len = ATH_TXBUF;
1268 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1269 da += sizeof(*ds)) {
1270 bf->desc = ds;
1271 bf->daddr = da;
1272 list_add_tail(&bf->list, &sc->txbuf);
1273 }
1274
1275 /* beacon buffer */
1276 bf->desc = ds;
1277 bf->daddr = da;
1278 sc->bbuf = bf;
1279
1280 return 0;
1281err_free:
1282 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1283err:
1284 sc->desc = NULL;
1285 return ret;
1286}
1287
1288static void
1289ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1290{
1291 struct ath5k_buf *bf;
1292
1293 ath5k_txbuf_free(sc, sc->bbuf);
1294 list_for_each_entry(bf, &sc->txbuf, list)
1295 ath5k_txbuf_free(sc, bf);
1296 list_for_each_entry(bf, &sc->rxbuf, list)
1297 ath5k_txbuf_free(sc, bf);
1298
1299 /* Free memory associated with all descriptors */
1300 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1301
1302 kfree(sc->bufptr);
1303 sc->bufptr = NULL;
1304}
1305
1306
1307
1308
1309
1310/**************\
1311* Queues setup *
1312\**************/
1313
1314static struct ath5k_txq *
1315ath5k_txq_setup(struct ath5k_softc *sc,
1316 int qtype, int subtype)
1317{
1318 struct ath5k_hw *ah = sc->ah;
1319 struct ath5k_txq *txq;
1320 struct ath5k_txq_info qi = {
1321 .tqi_subtype = subtype,
1322 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1323 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1324 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1325 };
1326 int qnum;
1327
1328 /*
1329 * Enable interrupts only for EOL and DESC conditions.
1330 * We mark tx descriptors to receive a DESC interrupt
1331 * when a tx queue gets deep; otherwise waiting for the
1332 * EOL to reap descriptors. Note that this is done to
1333 * reduce interrupt load and this only defers reaping
1334 * descriptors, never transmitting frames. Aside from
1335 * reducing interrupts this also permits more concurrency.
1336 * The only potential downside is if the tx queue backs
1337 * up in which case the top half of the kernel may backup
1338 * due to a lack of tx descriptors.
1339 */
1340 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1341 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1342 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1343 if (qnum < 0) {
1344 /*
1345 * NB: don't print a message, this happens
1346 * normally on parts with too few tx queues
1347 */
1348 return ERR_PTR(qnum);
1349 }
1350 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1351 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1352 qnum, ARRAY_SIZE(sc->txqs));
1353 ath5k_hw_release_tx_queue(ah, qnum);
1354 return ERR_PTR(-EINVAL);
1355 }
1356 txq = &sc->txqs[qnum];
1357 if (!txq->setup) {
1358 txq->qnum = qnum;
1359 txq->link = NULL;
1360 INIT_LIST_HEAD(&txq->q);
1361 spin_lock_init(&txq->lock);
1362 txq->setup = true;
1363 }
1364 return &sc->txqs[qnum];
1365}
1366
1367static int
1368ath5k_beaconq_setup(struct ath5k_hw *ah)
1369{
1370 struct ath5k_txq_info qi = {
1371 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1372 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1373 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1374 /* NB: for dynamic turbo, don't enable any other interrupts */
1375 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1376 };
1377
1378 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1379}
1380
1381static int
1382ath5k_beaconq_config(struct ath5k_softc *sc)
1383{
1384 struct ath5k_hw *ah = sc->ah;
1385 struct ath5k_txq_info qi;
1386 int ret;
1387
1388 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1389 if (ret)
1390 return ret;
05c914fe
JB		 1391 if (sc->opmode == NL80211_IFTYPE_AP ||
1392 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1393 /*
1394 * Always burst out beacon and CAB traffic
1395 * (aifs = cwmin = cwmax = 0)
1396 */
1397 qi.tqi_aifs = 0;
1398 qi.tqi_cw_min = 0;
1399 qi.tqi_cw_max = 0;
05c914fe 1400 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1401 /*
1402 * Adhoc mode; backoff between 0 and (2 * cw_min).
1403 */
1404 qi.tqi_aifs = 0;
1405 qi.tqi_cw_min = 0;
1406 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1407 }
1408
6d91e1d8
BR		 1409 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1410 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1411 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1412
c6e387a2 1413 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1414 if (ret) {
1415 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1416 "hardware queue!\n", __func__);
1417 return ret;
1418 }
1419
1420 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1421}
1422
1423static void
1424ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1425{
1426 struct ath5k_buf *bf, *bf0;
1427
1428 /*
1429 * NB: this assumes output has been stopped and
1430 * we do not need to block ath5k_tx_tasklet
1431 */
1432 spin_lock_bh(&txq->lock);
1433 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1434 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1435
1436 ath5k_txbuf_free(sc, bf);
1437
1438 spin_lock_bh(&sc->txbuflock);
57ffc589 1439 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1440 list_move_tail(&bf->list, &sc->txbuf);
1441 sc->txbuf_len++;
1442 spin_unlock_bh(&sc->txbuflock);
1443 }
1444 txq->link = NULL;
1445 spin_unlock_bh(&txq->lock);
1446}
1447
1448/*
1449 * Drain the transmit queues and reclaim resources.
1450 */
1451static void
1452ath5k_txq_cleanup(struct ath5k_softc *sc)
1453{
1454 struct ath5k_hw *ah = sc->ah;
1455 unsigned int i;
1456
1457 /* XXX return value */
1458 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1459 /* don't touch the hardware if marked invalid */
1460 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1461 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1462 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1463 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1464 if (sc->txqs[i].setup) {
1465 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1466 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1467 "link %p\n",
1468 sc->txqs[i].qnum,
c6e387a2 1469 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1470 sc->txqs[i].qnum),
1471 sc->txqs[i].link);
1472 }
1473 }
36d6825b 1474 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1475
1476 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1477 if (sc->txqs[i].setup)
1478 ath5k_txq_drainq(sc, &sc->txqs[i]);
1479}
1480
1481static void
1482ath5k_txq_release(struct ath5k_softc *sc)
1483{
1484 struct ath5k_txq *txq = sc->txqs;
1485 unsigned int i;
1486
1487 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1488 if (txq->setup) {
1489 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1490 txq->setup = false;
1491 }
1492}
1493
1494
1495
1496
1497/*************\
1498* RX Handling *
1499\*************/
1500
1501/*
1502 * Enable the receive h/w following a reset.
1503 */
1504static int
1505ath5k_rx_start(struct ath5k_softc *sc)
1506{
1507 struct ath5k_hw *ah = sc->ah;
1508 struct ath5k_buf *bf;
1509 int ret;
1510
1511 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1512
1513 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1514 sc->cachelsz, sc->rxbufsize);
1515
1516 sc->rxlink = NULL;
1517
1518 spin_lock_bh(&sc->rxbuflock);
1519 list_for_each_entry(bf, &sc->rxbuf, list) {
1520 ret = ath5k_rxbuf_setup(sc, bf);
1521 if (ret != 0) {
1522 spin_unlock_bh(&sc->rxbuflock);
1523 goto err;
1524 }
1525 }
1526 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1527 spin_unlock_bh(&sc->rxbuflock);
1528
c6e387a2
NK		 1529 ath5k_hw_set_rxdp(ah, bf->daddr);
1530 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1531 ath5k_mode_setup(sc); /* set filters, etc. */
1532 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1533
1534 return 0;
1535err:
1536 return ret;
1537}
1538
1539/*
1540 * Disable the receive h/w in preparation for a reset.
1541 */
1542static void
1543ath5k_rx_stop(struct ath5k_softc *sc)
1544{
1545 struct ath5k_hw *ah = sc->ah;
1546
c6e387a2 1547 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1548 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1549 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1550
1551 ath5k_debug_printrxbuffs(sc, ah);
1552
1553 sc->rxlink = NULL; /* just in case */
1554}
1555
1556static unsigned int
1557ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1558 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1559{
1560 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1561 unsigned int keyix, hlen;
fa1c114f 1562
b47f407b
BR		 1563 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1564 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1565 return RX_FLAG_DECRYPTED;
1566
1567 /* Apparently when a default key is used to decrypt the packet
1568 the hw does not set the index used to decrypt. In such cases
1569 get the index from the packet. */
798ee985 1570 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1571 if (ieee80211_has_protected(hdr->frame_control) &&
1572 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1573 skb->len >= hlen + 4) {
fa1c114f
JS		 1574 keyix = skb->data[hlen + 3] >> 6;
1575
1576 if (test_bit(keyix, sc->keymap))
1577 return RX_FLAG_DECRYPTED;
1578 }
1579
1580 return 0;
1581}
1582
036cd1ec
BR		 1583
1584static void
6ba81c2c
BR		 1585ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1586 struct ieee80211_rx_status *rxs)
036cd1ec 1587{
6ba81c2c 1588 u64 tsf, bc_tstamp;
036cd1ec
BR		 1589 u32 hw_tu;
1590 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1591
24b56e70 1592 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1593 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1594 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1595 /*
6ba81c2c
BR		 1596 * Received an IBSS beacon with the same BSSID. Hardware *must*
1597 * have updated the local TSF. We have to work around various
1598 * hardware bugs, though...
036cd1ec 1599 */
6ba81c2c
BR		 1600 tsf = ath5k_hw_get_tsf64(sc->ah);
1601 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1602 hw_tu = TSF_TO_TU(tsf);
1603
1604 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1605 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1606 (unsigned long long)bc_tstamp,
1607 (unsigned long long)rxs->mactime,
1608 (unsigned long long)(rxs->mactime - bc_tstamp),
1609 (unsigned long long)tsf);
6ba81c2c
BR		 1610
1611 /*
1612 * Sometimes the HW will give us a wrong tstamp in the rx
1613 * status, causing the timestamp extension to go wrong.
1614 * (This seems to happen especially with beacon frames bigger
1615 * than 78 byte (incl. FCS))
1616 * But we know that the receive timestamp must be later than the
1617 * timestamp of the beacon since HW must have synced to that.
1618 *
1619 * NOTE: here we assume mactime to be after the frame was
1620 * received, not like mac80211 which defines it at the start.
1621 */
1622 if (bc_tstamp > rxs->mactime) {
036cd1ec 1623 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1624 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1625 (unsigned long long)rxs->mactime,
1626 (unsigned long long)tsf);
6ba81c2c 1627 rxs->mactime = tsf;
036cd1ec 1628 }
6ba81c2c
BR		 1629
1630 /*
1631 * Local TSF might have moved higher than our beacon timers,
1632 * in that case we have to update them to continue sending
1633 * beacons. This also takes care of synchronizing beacon sending
1634 * times with other stations.
1635 */
1636 if (hw_tu >= sc->nexttbtt)
1637 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1638 }
1639}
1640
1641
fa1c114f
JS		 1642static void
1643ath5k_tasklet_rx(unsigned long data)
1644{
1645 struct ieee80211_rx_status rxs = {};
b47f407b 1646 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1647 struct sk_buff *skb;
1648 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1649 struct ath5k_buf *bf, *bf_last;
fa1c114f 1650 struct ath5k_desc *ds;
fa1c114f
JS		 1651 int ret;
1652 int hdrlen;
1653 int pad;
1654
1655 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1656 if (list_empty(&sc->rxbuf)) {
1657 ATH5K_WARN(sc, "empty rx buf pool\n");
1658 goto unlock;
1659 }
1660 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1661 do {
d6894b5b
BC		 1662 rxs.flag = 0;
1663
fa1c114f
JS		 1664 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1665 BUG_ON(bf->skb == NULL);
1666 skb = bf->skb;
1667 ds = bf->desc;
1668
3a0f2c87
JS		 1669 /*
1670 * last buffer must not be freed to ensure proper hardware
1671 * function. When the hardware finishes also a packet next to
1672 * it, we are sure, it doesn't use it anymore and we can go on.
1673 */
1674 if (bf_last == bf)
1675 bf->flags |= 1;
1676 if (bf->flags) {
1677 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1678 struct ath5k_buf, list);
1679 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1680 &rs);
1681 if (ret)
1682 break;
1683 bf->flags &= ~1;
1684 /* skip the overwritten one (even status is martian) */
1685 goto next;
1686 }
fa1c114f 1687
b47f407b 1688 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1689 if (unlikely(ret == -EINPROGRESS))
1690 break;
1691 else if (unlikely(ret)) {
1692 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1693 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1694 return;
1695 }
1696
b47f407b 1697 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1698 ATH5K_WARN(sc, "unsupported jumbo\n");
1699 goto next;
1700 }
1701
b47f407b
BR		 1702 if (unlikely(rs.rs_status)) {
1703 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1704 goto next;
b47f407b 1705 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1706 /*
1707 * Decrypt error. If the error occurred
1708 * because there was no hardware key, then
1709 * let the frame through so the upper layers
1710 * can process it. This is necessary for 5210
1711 * parts which have no way to setup a ``clear''
1712 * key cache entry.
1713 *
1714 * XXX do key cache faulting
1715 */
b47f407b
BR		 1716 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1717 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1718 goto accept;
1719 }
b47f407b 1720 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1721 rxs.flag |= RX_FLAG_MMIC_ERROR;
1722 goto accept;
1723 }
1724
1725 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1726 if ((rs.rs_status &
1727 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1728 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1729 goto next;
1730 }
1731accept:
fa1c114f
JS		 1732 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1733 PCI_DMA_FROMDEVICE);
1734 bf->skb = NULL;
1735
b47f407b 1736 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1737
1738 /*
1739 * the hardware adds a padding to 4 byte boundaries between
1740 * the header and the payload data if the header length is
1741 * not multiples of 4 - remove it
1742 */
1743 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1744 if (hdrlen & 3) {
1745 pad = hdrlen % 4;
1746 memmove(skb->data + pad, skb->data, hdrlen);
1747 skb_pull(skb, pad);
1748 }
1749
c0e1899b
BR		 1750 /*
1751 * always extend the mac timestamp, since this information is
1752 * also needed for proper IBSS merging.
1753 *
1754 * XXX: it might be too late to do it here, since rs_tstamp is
1755 * 15bit only. that means TSF extension has to be done within
1756 * 32768usec (about 32ms). it might be necessary to move this to
1757 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1758 *
1759 * Unfortunately we don't know when the hardware takes the rx
1760 * timestamp (beginning of phy frame, data frame, end of rx?).
1761 * The only thing we know is that it is hardware specific...
1762 * On AR5213 it seems the rx timestamp is at the end of the
1763 * frame, but i'm not sure.
1764 *
1765 * NOTE: mac80211 defines mactime at the beginning of the first
1766 * data symbol. Since we don't have any time references it's
1767 * impossible to comply to that. This affects IBSS merge only
1768 * right now, so it's not too bad...
c0e1899b 1769 */
b47f407b 1770 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1771 rxs.flag |= RX_FLAG_TSFT;
1772
d8ee398d
LR		 1773 rxs.freq = sc->curchan->center_freq;
1774 rxs.band = sc->curband->band;
fa1c114f 1775
fa1c114f 1776 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1777 rxs.signal = rxs.noise + rs.rs_rssi;
1778 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1779
b47f407b
BR		 1780 rxs.antenna = rs.rs_antenna;
1781 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1782 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1783
06303352
BR		 1784 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1785 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1786 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1787
fa1c114f
JS		 1788 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1789
036cd1ec 1790 /* check beacons in IBSS mode */
05c914fe 1791 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1792 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1793
fa1c114f 1794 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1795next:
1796 list_move_tail(&bf->list, &sc->rxbuf);
1797 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1798unlock:
fa1c114f
JS		 1799 spin_unlock(&sc->rxbuflock);
1800}
1801
1802
1803
1804
1805/*************\
1806* TX Handling *
1807\*************/
1808
1809static void
1810ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1811{
b47f407b 1812 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1813 struct ath5k_buf *bf, *bf0;
1814 struct ath5k_desc *ds;
1815 struct sk_buff *skb;
e039fa4a 1816 struct ieee80211_tx_info *info;
fa1c114f
JS		 1817 int ret;
1818
1819 spin_lock(&txq->lock);
1820 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1821 ds = bf->desc;
1822
b47f407b 1823 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1824 if (unlikely(ret == -EINPROGRESS))
1825 break;
1826 else if (unlikely(ret)) {
1827 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1828 ret, txq->qnum);
1829 break;
1830 }
1831
1832 skb = bf->skb;
a888d52d 1833 info = IEEE80211_SKB_CB(skb);
fa1c114f 1834 bf->skb = NULL;
e039fa4a 1835
fa1c114f
JS		 1836 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1837 PCI_DMA_TODEVICE);
1838
e039fa4a 1839 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1840 if (unlikely(ts.ts_status)) {
fa1c114f 1841 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1842 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1843 info->status.excessive_retries = 1;
b47f407b 1844 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1845 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1846 } else {
e039fa4a
JB		 1847 info->flags |= IEEE80211_TX_STAT_ACK;
1848 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1849 }
1850
e039fa4a 1851 ieee80211_tx_status(sc->hw, skb);
57ffc589 1852 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1853
1854 spin_lock(&sc->txbuflock);
57ffc589 1855 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1856 list_move_tail(&bf->list, &sc->txbuf);
1857 sc->txbuf_len++;
1858 spin_unlock(&sc->txbuflock);
1859 }
1860 if (likely(list_empty(&txq->q)))
1861 txq->link = NULL;
1862 spin_unlock(&txq->lock);
1863 if (sc->txbuf_len > ATH_TXBUF / 5)
1864 ieee80211_wake_queues(sc->hw);
1865}
1866
1867static void
1868ath5k_tasklet_tx(unsigned long data)
1869{
1870 struct ath5k_softc *sc = (void *)data;
1871
1872 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1873}
1874
1875
fa1c114f
JS		 1876/*****************\
1877* Beacon handling *
1878\*****************/
1879
1880/*
1881 * Setup the beacon frame for transmit.
1882 */
1883static int
e039fa4a 1884ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1885{
1886 struct sk_buff *skb = bf->skb;
a888d52d 1887 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1888 struct ath5k_hw *ah = sc->ah;
1889 struct ath5k_desc *ds;
1890 int ret, antenna = 0;
1891 u32 flags;
1892
1893 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1894 PCI_DMA_TODEVICE);
1895 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1896 "skbaddr %llx\n", skb, skb->data, skb->len,
1897 (unsigned long long)bf->skbaddr);
8d8bb39b 1898 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1899 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1900 return -EIO;
1901 }
1902
1903 ds = bf->desc;
1904
1905 flags = AR5K_TXDESC_NOACK;
05c914fe 1906 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1907 ds->ds_link = bf->daddr; /* self-linked */
1908 flags |= AR5K_TXDESC_VEOL;
1909 /*
1910 * Let hardware handle antenna switching if txantenna is not set
1911 */
1912 } else {
1913 ds->ds_link = 0;
1914 /*
1915 * Switch antenna every 4 beacons if txantenna is not set
1916 * XXX assumes two antennas
1917 */
1918 if (antenna == 0)
1919 antenna = sc->bsent & 4 ? 2 : 1;
1920 }
1921
1922 ds->ds_data = bf->skbaddr;
281c56dd 1923 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1924 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1925 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1926 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1927 1, AR5K_TXKEYIX_INVALID,
400ec45a 1928 antenna, flags, 0, 0);
fa1c114f
JS		 1929 if (ret)
1930 goto err_unmap;
1931
1932 return 0;
1933err_unmap:
1934 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1935 return ret;
1936}
1937
1938/*
1939 * Transmit a beacon frame at SWBA. Dynamic updates to the
1940 * frame contents are done as needed and the slot time is
1941 * also adjusted based on current state.
1942 *
1943 * this is usually called from interrupt context (ath5k_intr())
1944 * but also from ath5k_beacon_config() in IBSS mode which in turn
1945 * can be called from a tasklet and user context
1946 */
1947static void
1948ath5k_beacon_send(struct ath5k_softc *sc)
1949{
1950 struct ath5k_buf *bf = sc->bbuf;
1951 struct ath5k_hw *ah = sc->ah;
1952
be9b7259 1953 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1954
05c914fe
JB		 1955 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1956 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 1957 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1958 return;
1959 }
1960 /*
1961 * Check if the previous beacon has gone out. If
1962 * not don't don't try to post another, skip this
1963 * period and wait for the next. Missed beacons
1964 * indicate a problem and should not occur. If we
1965 * miss too many consecutive beacons reset the device.
1966 */
1967 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1968 sc->bmisscount++;
be9b7259 1969 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1970 "missed %u consecutive beacons\n", sc->bmisscount);
1971 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1972 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1973 "stuck beacon time (%u missed)\n",
1974 sc->bmisscount);
1975 tasklet_schedule(&sc->restq);
1976 }
1977 return;
1978 }
1979 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1980 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1981 "resume beacon xmit after %u misses\n",
1982 sc->bmisscount);
1983 sc->bmisscount = 0;
1984 }
1985
1986 /*
1987 * Stop any current dma and put the new frame on the queue.
1988 * This should never fail since we check above that no frames
1989 * are still pending on the queue.
1990 */
1991 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1992 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1993 /* NB: hw still stops DMA, so proceed */
1994 }
fa1c114f 1995
c6e387a2
NK		 1996 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1997 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1998 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1999 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2000
2001 sc->bsent++;
2002}
2003
2004
9804b98d
BR		 2005/**
2006 * ath5k_beacon_update_timers - update beacon timers
2007 *
2008 * @sc: struct ath5k_softc pointer we are operating on
2009 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2010 * beacon timer update based on the current HW TSF.
2011 *
2012 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2013 * of a received beacon or the current local hardware TSF and write it to the
2014 * beacon timer registers.
2015 *
2016 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2017 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2018 * when we otherwise know we have to update the timers, but we keep it in this
2019 * function to have it all together in one place.
2020 */
fa1c114f 2021static void
9804b98d 2022ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2023{
2024 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2025 u32 nexttbtt, intval, hw_tu, bc_tu;
2026 u64 hw_tsf;
fa1c114f
JS		 2027
2028 intval = sc->bintval & AR5K_BEACON_PERIOD;
2029 if (WARN_ON(!intval))
2030 return;
2031
9804b98d
BR		 2032 /* beacon TSF converted to TU */
2033 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2034
9804b98d
BR		 2035 /* current TSF converted to TU */
2036 hw_tsf = ath5k_hw_get_tsf64(ah);
2037 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2038
9804b98d
BR		 2039#define FUDGE 3
2040 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2041 if (bc_tsf == -1) {
2042 /*
2043 * no beacons received, called internally.
2044 * just need to refresh timers based on HW TSF.
2045 */
2046 nexttbtt = roundup(hw_tu + FUDGE, intval);
2047 } else if (bc_tsf == 0) {
2048 /*
2049 * no beacon received, probably called by ath5k_reset_tsf().
2050 * reset TSF to start with 0.
2051 */
2052 nexttbtt = intval;
2053 intval |= AR5K_BEACON_RESET_TSF;
2054 } else if (bc_tsf > hw_tsf) {
2055 /*
2056 * beacon received, SW merge happend but HW TSF not yet updated.
2057 * not possible to reconfigure timers yet, but next time we
2058 * receive a beacon with the same BSSID, the hardware will
2059 * automatically update the TSF and then we need to reconfigure
2060 * the timers.
2061 */
2062 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2063 "need to wait for HW TSF sync\n");
2064 return;
2065 } else {
2066 /*
2067 * most important case for beacon synchronization between STA.
2068 *
2069 * beacon received and HW TSF has been already updated by HW.
2070 * update next TBTT based on the TSF of the beacon, but make
2071 * sure it is ahead of our local TSF timer.
2072 */
2073 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2074 }
2075#undef FUDGE
fa1c114f 2076
036cd1ec
BR		 2077 sc->nexttbtt = nexttbtt;
2078
fa1c114f 2079 intval |= AR5K_BEACON_ENA;
fa1c114f 2080 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2081
2082 /*
2083 * debugging output last in order to preserve the time critical aspect
2084 * of this function
2085 */
2086 if (bc_tsf == -1)
2087 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2088 "reconfigured timers based on HW TSF\n");
2089 else if (bc_tsf == 0)
2090 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2091 "reset HW TSF and timers\n");
2092 else
2093 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2094 "updated timers based on beacon TSF\n");
2095
2096 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2097 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2098 (unsigned long long) bc_tsf,
2099 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2100 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2101 intval & AR5K_BEACON_PERIOD,
2102 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2103 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2104}
2105
2106
036cd1ec
BR		 2107/**
2108 * ath5k_beacon_config - Configure the beacon queues and interrupts
2109 *
2110 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2111 *
2112 * When operating in station mode we want to receive a BMISS interrupt when we
2113 * stop seeing beacons from the AP we've associated with so we can look for
2114 * another AP to associate with.
2115 *
036cd1ec 2116 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2117 * interrupts to detect TSF updates only.
036cd1ec
BR		 2118 *
2119 * AP mode is missing.
fa1c114f
JS		 2120 */
2121static void
2122ath5k_beacon_config(struct ath5k_softc *sc)
2123{
2124 struct ath5k_hw *ah = sc->ah;
2125
c6e387a2 2126 ath5k_hw_set_imr(ah, 0);
fa1c114f 2127 sc->bmisscount = 0;
dc1968e7 2128 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2129
05c914fe 2130 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2131 sc->imask |= AR5K_INT_BMISS;
05c914fe 2132 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2133 /*
036cd1ec
BR		 2134 * In IBSS mode we use a self-linked tx descriptor and let the
2135 * hardware send the beacons automatically. We have to load it
fa1c114f 2136 * only once here.
036cd1ec 2137 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2138 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2139 */
2140 ath5k_beaconq_config(sc);
fa1c114f 2141
036cd1ec
BR		 2142 sc->imask |= AR5K_INT_SWBA;
2143
00482973
JS		 2144 if (ath5k_hw_hasveol(ah)) {
2145 spin_lock(&sc->block);
fa1c114f 2146 ath5k_beacon_send(sc);
00482973
JS		 2147 spin_unlock(&sc->block);
2148 }
fa1c114f
JS		 2149 }
2150 /* TODO else AP */
2151
c6e387a2 2152 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2153}
2154
2155
2156/********************\
2157* Interrupt handling *
2158\********************/
2159
2160static int
2161ath5k_init(struct ath5k_softc *sc)
2162{
2163 int ret;
2164
2165 mutex_lock(&sc->lock);
2166
2167 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2168
2169 /*
2170 * Stop anything previously setup. This is safe
2171 * no matter this is the first time through or not.
2172 */
2173 ath5k_stop_locked(sc);
2174
2175 /*
2176 * The basic interface to setting the hardware in a good
2177 * state is ``reset''. On return the hardware is known to
2178 * be powered up and with interrupts disabled. This must
2179 * be followed by initialization of the appropriate bits
2180 * and then setup of the interrupt mask.
2181 */
d8ee398d
LR		 2182 sc->curchan = sc->hw->conf.channel;
2183 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2184 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2185 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2186 AR5K_INT_MIB;
d7dc1003
JS		 2187 ret = ath5k_reset(sc, false, false);
2188 if (ret)
2189 goto done;
fa1c114f 2190
fa1c114f
JS		 2191 /* Set ack to be sent at low bit-rates */
2192 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2193
2194 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2195 msecs_to_jiffies(ath5k_calinterval * 1000)));
2196
2197 ret = 0;
2198done:
274c7c36 2199 mmiowb();
fa1c114f
JS		 2200 mutex_unlock(&sc->lock);
2201 return ret;
2202}
2203
2204static int
2205ath5k_stop_locked(struct ath5k_softc *sc)
2206{
2207 struct ath5k_hw *ah = sc->ah;
2208
2209 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2210 test_bit(ATH_STAT_INVALID, sc->status));
2211
2212 /*
2213 * Shutdown the hardware and driver:
2214 * stop output from above
2215 * disable interrupts
2216 * turn off timers
2217 * turn off the radio
2218 * clear transmit machinery
2219 * clear receive machinery
2220 * drain and release tx queues
2221 * reclaim beacon resources
2222 * power down hardware
2223 *
2224 * Note that some of this work is not possible if the
2225 * hardware is gone (invalid).
2226 */
2227 ieee80211_stop_queues(sc->hw);
2228
2229 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2230 ath5k_led_off(sc);
c6e387a2 2231 ath5k_hw_set_imr(ah, 0);
274c7c36 2232 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2233 }
2234 ath5k_txq_cleanup(sc);
2235 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2236 ath5k_rx_stop(sc);
2237 ath5k_hw_phy_disable(ah);
2238 } else
2239 sc->rxlink = NULL;
2240
2241 return 0;
2242}
2243
2244/*
2245 * Stop the device, grabbing the top-level lock to protect
2246 * against concurrent entry through ath5k_init (which can happen
2247 * if another thread does a system call and the thread doing the
2248 * stop is preempted).
2249 */
2250static int
2251ath5k_stop_hw(struct ath5k_softc *sc)
2252{
2253 int ret;
2254
2255 mutex_lock(&sc->lock);
2256 ret = ath5k_stop_locked(sc);
2257 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2258 /*
2259 * Set the chip in full sleep mode. Note that we are
2260 * careful to do this only when bringing the interface
2261 * completely to a stop. When the chip is in this state
2262 * it must be carefully woken up or references to
2263 * registers in the PCI clock domain may freeze the bus
2264 * (and system). This varies by chip and is mostly an
2265 * issue with newer parts that go to sleep more quickly.
2266 */
2267 if (sc->ah->ah_mac_srev >= 0x78) {
2268 /*
2269 * XXX
2270 * don't put newer MAC revisions > 7.8 to sleep because
2271 * of the above mentioned problems
2272 */
2273 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2274 "not putting device to sleep\n");
2275 } else {
2276 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2277 "putting device to full sleep\n");
2278 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2279 }
2280 }
2281 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2282 mmiowb();
fa1c114f
JS		 2283 mutex_unlock(&sc->lock);
2284
2285 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2286 tasklet_kill(&sc->rxtq);
2287 tasklet_kill(&sc->txtq);
2288 tasklet_kill(&sc->restq);
fa1c114f
JS		 2289
2290 return ret;
2291}
2292
2293static irqreturn_t
2294ath5k_intr(int irq, void *dev_id)
2295{
2296 struct ath5k_softc *sc = dev_id;
2297 struct ath5k_hw *ah = sc->ah;
2298 enum ath5k_int status;
2299 unsigned int counter = 1000;
2300
2301 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2302 !ath5k_hw_is_intr_pending(ah)))
2303 return IRQ_NONE;
2304
2305 do {
2306 /*
2307 * Figure out the reason(s) for the interrupt. Note
2308 * that get_isr returns a pseudo-ISR that may include
2309 * bits we haven't explicitly enabled so we mask the
2310 * value to insure we only process bits we requested.
2311 */
2312 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2313 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2314 status, sc->imask);
2315 status &= sc->imask; /* discard unasked for bits */
2316 if (unlikely(status & AR5K_INT_FATAL)) {
2317 /*
2318 * Fatal errors are unrecoverable.
2319 * Typically these are caused by DMA errors.
2320 */
2321 tasklet_schedule(&sc->restq);
2322 } else if (unlikely(status & AR5K_INT_RXORN)) {
2323 tasklet_schedule(&sc->restq);
2324 } else {
2325 if (status & AR5K_INT_SWBA) {
2326 /*
2327 * Software beacon alert--time to send a beacon.
2328 * Handle beacon transmission directly; deferring
2329 * this is too slow to meet timing constraints
2330 * under load.
036cd1ec
BR		 2331 *
2332 * In IBSS mode we use this interrupt just to
2333 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2334 * transmission time) in order to detect wether
2335 * automatic TSF updates happened.
fa1c114f 2336 */
05c914fe 2337 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2338 /* XXX: only if VEOL suppported */
2339 u64 tsf = ath5k_hw_get_tsf64(ah);
2340 sc->nexttbtt += sc->bintval;
2341 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2342 "SWBA nexttbtt: %x hw_tu: %x "
2343 "TSF: %llx\n",
2344 sc->nexttbtt,
2345 TSF_TO_TU(tsf),
2346 (unsigned long long) tsf);
036cd1ec 2347 } else {
00482973 2348 spin_lock(&sc->block);
036cd1ec 2349 ath5k_beacon_send(sc);
00482973 2350 spin_unlock(&sc->block);
036cd1ec 2351 }
fa1c114f
JS		 2352 }
2353 if (status & AR5K_INT_RXEOL) {
2354 /*
2355 * NB: the hardware should re-read the link when
2356 * RXE bit is written, but it doesn't work at
2357 * least on older hardware revs.
2358 */
2359 sc->rxlink = NULL;
2360 }
2361 if (status & AR5K_INT_TXURN) {
2362 /* bump tx trigger level */
2363 ath5k_hw_update_tx_triglevel(ah, true);
2364 }
2365 if (status & AR5K_INT_RX)
2366 tasklet_schedule(&sc->rxtq);
2367 if (status & AR5K_INT_TX)
2368 tasklet_schedule(&sc->txtq);
2369 if (status & AR5K_INT_BMISS) {
2370 }
2371 if (status & AR5K_INT_MIB) {
194828a2
NK		 2372 /*
2373 * These stats are also used for ANI i think
2374 * so how about updating them more often ?
2375 */
2376 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2377 }
2378 }
2379 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2380
2381 if (unlikely(!counter))
2382 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2383
2384 return IRQ_HANDLED;
2385}
2386
2387static void
2388ath5k_tasklet_reset(unsigned long data)
2389{
2390 struct ath5k_softc *sc = (void *)data;
2391
d7dc1003 2392 ath5k_reset_wake(sc);
fa1c114f
JS		 2393}
2394
2395/*
2396 * Periodically recalibrate the PHY to account
2397 * for temperature/environment changes.
2398 */
2399static void
2400ath5k_calibrate(unsigned long data)
2401{
2402 struct ath5k_softc *sc = (void *)data;
2403 struct ath5k_hw *ah = sc->ah;
2404
2405 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2406 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2407 sc->curchan->hw_value);
fa1c114f
JS		 2408
2409 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2410 /*
2411 * Rfgain is out of bounds, reset the chip
2412 * to load new gain values.
2413 */
2414 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2415 ath5k_reset_wake(sc);
fa1c114f
JS		 2416 }
2417 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2418 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2419 ieee80211_frequency_to_channel(
2420 sc->curchan->center_freq));
fa1c114f
JS		 2421
2422 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2423 msecs_to_jiffies(ath5k_calinterval * 1000)));
2424}
2425
2426
2427
2428/***************\
2429* LED functions *
2430\***************/
2431
2432static void
3a078876 2433ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2434{
3a078876
BC		 2435 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2436 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2437 ath5k_led_off(sc);
fa1c114f
JS		 2438 }
2439}
2440
fa1c114f 2441static void
3a078876 2442ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2443{
3a078876
BC		 2444 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2445 return;
fa1c114f 2446 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2447}
2448
2449static void
3a078876 2450ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2451{
3a078876 2452 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2453 return;
3a078876
BC		 2454 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2455}
2456
2457static void
2458ath5k_led_brightness_set(struct led_classdev *led_dev,
2459 enum led_brightness brightness)
2460{
2461 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2462 led_dev);
2463
2464 if (brightness == LED_OFF)
2465 ath5k_led_off(led->sc);
2466 else
2467 ath5k_led_on(led->sc);
2468}
2469
2470static int
2471ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2472 const char *name, char *trigger)
2473{
2474 int err;
2475
2476 led->sc = sc;
2477 strncpy(led->name, name, sizeof(led->name));
2478 led->led_dev.name = led->name;
2479 led->led_dev.default_trigger = trigger;
2480 led->led_dev.brightness_set = ath5k_led_brightness_set;
2481
2482 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2483 if (err)
2484 {
2485 ATH5K_WARN(sc, "could not register LED %s\n", name);
2486 led->sc = NULL;
fa1c114f 2487 }
3a078876 2488 return err;
fa1c114f
JS		 2489}
2490
3a078876
BC		 2491static void
2492ath5k_unregister_led(struct ath5k_led *led)
2493{
2494 if (!led->sc)
2495 return;
2496 led_classdev_unregister(&led->led_dev);
2497 ath5k_led_off(led->sc);
2498 led->sc = NULL;
2499}
2500
2501static void
2502ath5k_unregister_leds(struct ath5k_softc *sc)
2503{
2504 ath5k_unregister_led(&sc->rx_led);
2505 ath5k_unregister_led(&sc->tx_led);
2506}
2507
2508
2509static int
2510ath5k_init_leds(struct ath5k_softc *sc)
2511{
2512 int ret = 0;
2513 struct ieee80211_hw *hw = sc->hw;
2514 struct pci_dev *pdev = sc->pdev;
2515 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2516
3a078876
BC		 2517 /*
2518 * Auto-enable soft led processing for IBM cards and for
2519 * 5211 minipci cards.
2520 */
2521 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2522 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2523 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2524 sc->led_pin = 0;
734b5aa9 2525 sc->led_on = 0; /* active low */
3a078876
BC		 2526 }
2527 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2528 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2529 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2530 sc->led_pin = 1;
734b5aa9 2531 sc->led_on = 1; /* active high */
3a078876
BC		 2532 }
2533 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2534 goto out;
2535
2536 ath5k_led_enable(sc);
2537
2538 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2539 ret = ath5k_register_led(sc, &sc->rx_led, name,
2540 ieee80211_get_rx_led_name(hw));
2541 if (ret)
2542 goto out;
2543
2544 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2545 ret = ath5k_register_led(sc, &sc->tx_led, name,
2546 ieee80211_get_tx_led_name(hw));
2547out:
2548 return ret;
2549}
fa1c114f
JS		 2550
2551
2552/********************\
2553* Mac80211 functions *
2554\********************/
2555
2556static int
e039fa4a 2557ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2558{
2559 struct ath5k_softc *sc = hw->priv;
2560 struct ath5k_buf *bf;
2561 unsigned long flags;
2562 int hdrlen;
2563 int pad;
2564
2565 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2566
05c914fe 2567 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2568 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2569
2570 /*
2571 * the hardware expects the header padded to 4 byte boundaries
2572 * if this is not the case we add the padding after the header
2573 */
2574 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2575 if (hdrlen & 3) {
2576 pad = hdrlen % 4;
2577 if (skb_headroom(skb) < pad) {
2578 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2579 " headroom to pad %d\n", hdrlen, pad);
2580 return -1;
2581 }
2582 skb_push(skb, pad);
2583 memmove(skb->data, skb->data+pad, hdrlen);
2584 }
2585
fa1c114f
JS		 2586 spin_lock_irqsave(&sc->txbuflock, flags);
2587 if (list_empty(&sc->txbuf)) {
2588 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2589 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2590 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2591 return -1;
2592 }
2593 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2594 list_del(&bf->list);
2595 sc->txbuf_len--;
2596 if (list_empty(&sc->txbuf))
2597 ieee80211_stop_queues(hw);
2598 spin_unlock_irqrestore(&sc->txbuflock, flags);
2599
2600 bf->skb = skb;
2601
e039fa4a 2602 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2603 bf->skb = NULL;
2604 spin_lock_irqsave(&sc->txbuflock, flags);
2605 list_add_tail(&bf->list, &sc->txbuf);
2606 sc->txbuf_len++;
2607 spin_unlock_irqrestore(&sc->txbuflock, flags);
2608 dev_kfree_skb_any(skb);
2609 return 0;
2610 }
2611
2612 return 0;
2613}
2614
2615static int
d7dc1003 2616ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2617{
fa1c114f
JS		 2618 struct ath5k_hw *ah = sc->ah;
2619 int ret;
2620
2621 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2622
d7dc1003 2623 if (stop) {
c6e387a2 2624 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2625 ath5k_txq_cleanup(sc);
2626 ath5k_rx_stop(sc);
2627 }
fa1c114f 2628 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2629 if (ret) {
fa1c114f
JS		 2630 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2631 goto err;
2632 }
d7dc1003
JS		 2633
2634 /*
2635 * This is needed only to setup initial state
2636 * but it's best done after a reset.
2637 */
fa1c114f
JS		 2638 ath5k_hw_set_txpower_limit(sc->ah, 0);
2639
2640 ret = ath5k_rx_start(sc);
d7dc1003 2641 if (ret) {
fa1c114f
JS		 2642 ATH5K_ERR(sc, "can't start recv logic\n");
2643 goto err;
2644 }
d7dc1003 2645
fa1c114f 2646 /*
d7dc1003
JS		 2647 * Change channels and update the h/w rate map if we're switching;
2648 * e.g. 11a to 11b/g.
2649 *
2650 * We may be doing a reset in response to an ioctl that changes the
2651 * channel so update any state that might change as a result.
fa1c114f
JS		 2652 *
2653 * XXX needed?
2654 */
2655/* ath5k_chan_change(sc, c); */
fa1c114f 2656
d7dc1003
JS		 2657 ath5k_beacon_config(sc);
2658 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2659
2660 return 0;
2661err:
2662 return ret;
2663}
2664
d7dc1003
JS		 2665static int
2666ath5k_reset_wake(struct ath5k_softc *sc)
2667{
2668 int ret;
2669
2670 ret = ath5k_reset(sc, true, true);
2671 if (!ret)
2672 ieee80211_wake_queues(sc->hw);
2673
2674 return ret;
2675}
2676
fa1c114f
JS		 2677static int ath5k_start(struct ieee80211_hw *hw)
2678{
2679 return ath5k_init(hw->priv);
2680}
2681
2682static void ath5k_stop(struct ieee80211_hw *hw)
2683{
2684 ath5k_stop_hw(hw->priv);
2685}
2686
2687static int ath5k_add_interface(struct ieee80211_hw *hw,
2688 struct ieee80211_if_init_conf *conf)
2689{
2690 struct ath5k_softc *sc = hw->priv;
2691 int ret;
2692
2693 mutex_lock(&sc->lock);
32bfd35d 2694 if (sc->vif) {
fa1c114f
JS		 2695 ret = 0;
2696 goto end;
2697 }
2698
32bfd35d 2699 sc->vif = conf->vif;
fa1c114f
JS		 2700
2701 switch (conf->type) {
05c914fe
JB		 2702 case NL80211_IFTYPE_STATION:
2703 case NL80211_IFTYPE_ADHOC:
2704 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2705 sc->opmode = conf->type;
2706 break;
2707 default:
2708 ret = -EOPNOTSUPP;
2709 goto end;
2710 }
67d2e2df
JS		 2711
2712 /* Set to a reasonable value. Note that this will
2713 * be set to mac80211's value at ath5k_config(). */
2714 sc->bintval = 1000;
2715
fa1c114f
JS		 2716 ret = 0;
2717end:
2718 mutex_unlock(&sc->lock);
2719 return ret;
2720}
2721
2722static void
2723ath5k_remove_interface(struct ieee80211_hw *hw,
2724 struct ieee80211_if_init_conf *conf)
2725{
2726 struct ath5k_softc *sc = hw->priv;
2727
2728 mutex_lock(&sc->lock);
32bfd35d 2729 if (sc->vif != conf->vif)
fa1c114f
JS		 2730 goto end;
2731
32bfd35d 2732 sc->vif = NULL;
fa1c114f
JS		 2733end:
2734 mutex_unlock(&sc->lock);
2735}
2736
d8ee398d
LR		 2737/*
2738 * TODO: Phy disable/diversity etc
2739 */
fa1c114f
JS		 2740static int
2741ath5k_config(struct ieee80211_hw *hw,
2742 struct ieee80211_conf *conf)
2743{
2744 struct ath5k_softc *sc = hw->priv;
2745
e535c1ac 2746 sc->bintval = conf->beacon_int;
d8ee398d 2747 sc->power_level = conf->power_level;
fa1c114f 2748
d8ee398d 2749 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2750}
2751
2752static int
32bfd35d 2753ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2754 struct ieee80211_if_conf *conf)
2755{
2756 struct ath5k_softc *sc = hw->priv;
2757 struct ath5k_hw *ah = sc->ah;
2758 int ret;
2759
fa1c114f 2760 mutex_lock(&sc->lock);
32bfd35d 2761 if (sc->vif != vif) {
fa1c114f
JS		 2762 ret = -EIO;
2763 goto unlock;
2764 }
2765 if (conf->bssid) {
2766 /* Cache for later use during resets */
2767 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2768 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2769 * a clean way of letting us retrieve this yet. */
2770 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2771 mmiowb();
fa1c114f 2772 }
9d139c81
JB		 2773
2774 if (conf->changed & IEEE80211_IFCC_BEACON &&
05c914fe 2775 vif->type == NL80211_IFTYPE_ADHOC) {
9d139c81
JB		 2776 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2777 if (!beacon) {
2778 ret = -ENOMEM;
2779 goto unlock;
2780 }
2781 /* call old handler for now */
2782 ath5k_beacon_update(hw, beacon);
2783 }
2784
fa1c114f
JS		 2785 mutex_unlock(&sc->lock);
2786
d7dc1003 2787 return ath5k_reset_wake(sc);
fa1c114f
JS		 2788unlock:
2789 mutex_unlock(&sc->lock);
2790 return ret;
2791}
2792
2793#define SUPPORTED_FIF_FLAGS \
2794 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2795 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2796 FIF_BCN_PRBRESP_PROMISC
2797/*
2798 * o always accept unicast, broadcast, and multicast traffic
2799 * o multicast traffic for all BSSIDs will be enabled if mac80211
2800 * says it should be
2801 * o maintain current state of phy ofdm or phy cck error reception.
2802 * If the hardware detects any of these type of errors then
2803 * ath5k_hw_get_rx_filter() will pass to us the respective
2804 * hardware filters to be able to receive these type of frames.
2805 * o probe request frames are accepted only when operating in
2806 * hostap, adhoc, or monitor modes
2807 * o enable promiscuous mode according to the interface state
2808 * o accept beacons:
2809 * - when operating in adhoc mode so the 802.11 layer creates
2810 * node table entries for peers,
2811 * - when operating in station mode for collecting rssi data when
2812 * the station is otherwise quiet, or
2813 * - when scanning
2814 */
2815static void ath5k_configure_filter(struct ieee80211_hw *hw,
2816 unsigned int changed_flags,
2817 unsigned int *new_flags,
2818 int mc_count, struct dev_mc_list *mclist)
2819{
2820 struct ath5k_softc *sc = hw->priv;
2821 struct ath5k_hw *ah = sc->ah;
2822 u32 mfilt[2], val, rfilt;
2823 u8 pos;
2824 int i;
2825
2826 mfilt[0] = 0;
2827 mfilt[1] = 0;
2828
2829 /* Only deal with supported flags */
2830 changed_flags &= SUPPORTED_FIF_FLAGS;
2831 *new_flags &= SUPPORTED_FIF_FLAGS;
2832
2833 /* If HW detects any phy or radar errors, leave those filters on.
2834 * Also, always enable Unicast, Broadcasts and Multicast
2835 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2836 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2837 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2838 AR5K_RX_FILTER_MCAST);
2839
2840 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2841 if (*new_flags & FIF_PROMISC_IN_BSS) {
2842 rfilt |= AR5K_RX_FILTER_PROM;
2843 __set_bit(ATH_STAT_PROMISC, sc->status);
2844 }
2845 else
2846 __clear_bit(ATH_STAT_PROMISC, sc->status);
2847 }
2848
2849 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2850 if (*new_flags & FIF_ALLMULTI) {
2851 mfilt[0] = ~0;
2852 mfilt[1] = ~0;
2853 } else {
2854 for (i = 0; i < mc_count; i++) {
2855 if (!mclist)
2856 break;
2857 /* calculate XOR of eight 6-bit values */
533dd1b0 2858 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2859 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2860 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2861 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2862 pos &= 0x3f;
2863 mfilt[pos / 32] |= (1 << (pos % 32));
2864 /* XXX: we might be able to just do this instead,
2865 * but not sure, needs testing, if we do use this we'd
2866 * neet to inform below to not reset the mcast */
2867 /* ath5k_hw_set_mcast_filterindex(ah,
2868 * mclist->dmi_addr[5]); */
2869 mclist = mclist->next;
2870 }
2871 }
2872
2873 /* This is the best we can do */
2874 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2875 rfilt |= AR5K_RX_FILTER_PHYERR;
2876
2877 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2878 * and probes for any BSSID, this needs testing */
2879 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2880 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2881
2882 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2883 * set we should only pass on control frames for this
2884 * station. This needs testing. I believe right now this
2885 * enables *all* control frames, which is OK.. but
2886 * but we should see if we can improve on granularity */
2887 if (*new_flags & FIF_CONTROL)
2888 rfilt |= AR5K_RX_FILTER_CONTROL;
2889
2890 /* Additional settings per mode -- this is per ath5k */
2891
2892 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2893
05c914fe 2894 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2895 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2896 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2897 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2898 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2899 if (sc->opmode != NL80211_IFTYPE_AP &&
2900 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2901 test_bit(ATH_STAT_PROMISC, sc->status))
2902 rfilt |= AR5K_RX_FILTER_PROM;
05c914fe
JB		 2903 if (sc->opmode == NL80211_IFTYPE_STATION ||
2904 sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 2905 rfilt |= AR5K_RX_FILTER_BEACON;
2906 }
2907
2908 /* Set filters */
2909 ath5k_hw_set_rx_filter(ah,rfilt);
2910
2911 /* Set multicast bits */
2912 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2913 /* Set the cached hw filter flags, this will alter actually
2914 * be set in HW */
2915 sc->filter_flags = rfilt;
2916}
2917
2918static int
2919ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2920 const u8 *local_addr, const u8 *addr,
2921 struct ieee80211_key_conf *key)
2922{
2923 struct ath5k_softc *sc = hw->priv;
2924 int ret = 0;
2925
2926 switch(key->alg) {
2927 case ALG_WEP:
6844e63a
LR		 2928 /* XXX: fix hardware encryption, its not working. For now
2929 * allow software encryption */
2930 /* break; */
fa1c114f
JS		 2931 case ALG_TKIP:
2932 case ALG_CCMP:
2933 return -EOPNOTSUPP;
2934 default:
2935 WARN_ON(1);
2936 return -EINVAL;
2937 }
2938
2939 mutex_lock(&sc->lock);
2940
2941 switch (cmd) {
2942 case SET_KEY:
2943 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2944 if (ret) {
2945 ATH5K_ERR(sc, "can't set the key\n");
2946 goto unlock;
2947 }
2948 __set_bit(key->keyidx, sc->keymap);
2949 key->hw_key_idx = key->keyidx;
2950 break;
2951 case DISABLE_KEY:
2952 ath5k_hw_reset_key(sc->ah, key->keyidx);
2953 __clear_bit(key->keyidx, sc->keymap);
2954 break;
2955 default:
2956 ret = -EINVAL;
2957 goto unlock;
2958 }
2959
2960unlock:
274c7c36 2961 mmiowb();
fa1c114f
JS		 2962 mutex_unlock(&sc->lock);
2963 return ret;
2964}
2965
2966static int
2967ath5k_get_stats(struct ieee80211_hw *hw,
2968 struct ieee80211_low_level_stats *stats)
2969{
2970 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2971 struct ath5k_hw *ah = sc->ah;
2972
2973 /* Force update */
2974 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2975
2976 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2977
2978 return 0;
2979}
2980
2981static int
2982ath5k_get_tx_stats(struct ieee80211_hw *hw,
2983 struct ieee80211_tx_queue_stats *stats)
2984{
2985 struct ath5k_softc *sc = hw->priv;
2986
2987 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2988
2989 return 0;
2990}
2991
2992static u64
2993ath5k_get_tsf(struct ieee80211_hw *hw)
2994{
2995 struct ath5k_softc *sc = hw->priv;
2996
2997 return ath5k_hw_get_tsf64(sc->ah);
2998}
2999
3000static void
3001ath5k_reset_tsf(struct ieee80211_hw *hw)
3002{
3003 struct ath5k_softc *sc = hw->priv;
3004
9804b98d
BR		 3005 /*
3006 * in IBSS mode we need to update the beacon timers too.
3007 * this will also reset the TSF if we call it with 0
3008 */
05c914fe 3009 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3010 ath5k_beacon_update_timers(sc, 0);
3011 else
3012 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3013}
3014
3015static int
e039fa4a 3016ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3017{
3018 struct ath5k_softc *sc = hw->priv;
00482973 3019 unsigned long flags;
fa1c114f
JS		 3020 int ret;
3021
3022 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3023
05c914fe 3024 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 3025 ret = -EIO;
3026 goto end;
3027 }
3028
00482973 3029 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3030 ath5k_txbuf_free(sc, sc->bbuf);
3031 sc->bbuf->skb = skb;
e039fa4a 3032 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3033 if (ret)
3034 sc->bbuf->skb = NULL;
00482973
JS		 3035 spin_unlock_irqrestore(&sc->block, flags);
3036 if (!ret) {
fa1c114f 3037 ath5k_beacon_config(sc);
274c7c36
JS		 3038 mmiowb();
3039 }
fa1c114f
JS		 3040
3041end:
fa1c114f
JS		 3042 return ret;
3043}
3044
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