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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
133};
134
135/*
136 * Prototypes - PCI stack related functions
137 */
138static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
139 const struct pci_device_id *id);
140static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
141#ifdef CONFIG_PM
142static int ath5k_pci_suspend(struct pci_dev *pdev,
143 pm_message_t state);
144static int ath5k_pci_resume(struct pci_dev *pdev);
145#else
146#define ath5k_pci_suspend NULL
147#define ath5k_pci_resume NULL
148#endif /* CONFIG_PM */
149
04a9e451 150static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 151 .name = "ath5k_pci",
152 .id_table = ath5k_pci_id_table,
153 .probe = ath5k_pci_probe,
154 .remove = __devexit_p(ath5k_pci_remove),
155 .suspend = ath5k_pci_suspend,
156 .resume = ath5k_pci_resume,
157};
158
159
160
161/*
162 * Prototypes - MAC 802.11 stack related functions
163 */
e039fa4a 164static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 165static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
166static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 167static int ath5k_start(struct ieee80211_hw *hw);
168static void ath5k_stop(struct ieee80211_hw *hw);
169static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
32bfd35d
JB		 175static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
fa1c114f
JS		 177 struct ieee80211_if_conf *conf);
178static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 193 struct sk_buff *skb);
fa1c114f
JS		 194
195static struct ieee80211_ops ath5k_hw_ops = {
196 .tx = ath5k_tx,
197 .start = ath5k_start,
198 .stop = ath5k_stop,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
206 .conf_tx = NULL,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 210};
211
212/*
213 * Prototypes - Internal functions
214 */
215/* Attach detach */
216static int ath5k_attach(struct pci_dev *pdev,
217 struct ieee80211_hw *hw);
218static void ath5k_detach(struct pci_dev *pdev,
219 struct ieee80211_hw *hw);
220/* Channel/mode setup */
221static inline short ath5k_ieee2mhz(short chan);
222static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
223 const struct ath5k_rate_table *rt,
224 unsigned int max);
225static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
226 struct ieee80211_channel *channels,
227 unsigned int mode,
228 unsigned int max);
229static int ath5k_getchannels(struct ieee80211_hw *hw);
230static int ath5k_chan_set(struct ath5k_softc *sc,
231 struct ieee80211_channel *chan);
232static void ath5k_setcurmode(struct ath5k_softc *sc,
233 unsigned int mode);
234static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 235static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
236
fa1c114f
JS		 237/* Descriptor setup */
238static int ath5k_desc_alloc(struct ath5k_softc *sc,
239 struct pci_dev *pdev);
240static void ath5k_desc_free(struct ath5k_softc *sc,
241 struct pci_dev *pdev);
242/* Buffers setup */
243static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
244 struct ath5k_buf *bf);
245static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 246 struct ath5k_buf *bf);
fa1c114f
JS		 247static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
248 struct ath5k_buf *bf)
249{
250 BUG_ON(!bf);
251 if (!bf->skb)
252 return;
253 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
254 PCI_DMA_TODEVICE);
255 dev_kfree_skb(bf->skb);
256 bf->skb = NULL;
257}
258
259/* Queues setup */
260static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
261 int qtype, int subtype);
262static int ath5k_beaconq_setup(struct ath5k_hw *ah);
263static int ath5k_beaconq_config(struct ath5k_softc *sc);
264static void ath5k_txq_drainq(struct ath5k_softc *sc,
265 struct ath5k_txq *txq);
266static void ath5k_txq_cleanup(struct ath5k_softc *sc);
267static void ath5k_txq_release(struct ath5k_softc *sc);
268/* Rx handling */
269static int ath5k_rx_start(struct ath5k_softc *sc);
270static void ath5k_rx_stop(struct ath5k_softc *sc);
271static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
272 struct ath5k_desc *ds,
b47f407b
BR		 273 struct sk_buff *skb,
274 struct ath5k_rx_status *rs);
fa1c114f
JS		 275static void ath5k_tasklet_rx(unsigned long data);
276/* Tx handling */
277static void ath5k_tx_processq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279static void ath5k_tasklet_tx(unsigned long data);
280/* Beacon handling */
281static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 282 struct ath5k_buf *bf);
fa1c114f
JS		 283static void ath5k_beacon_send(struct ath5k_softc *sc);
284static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 285static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 286
287static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
288{
289 u64 tsf = ath5k_hw_get_tsf64(ah);
290
291 if ((tsf & 0x7fff) < rstamp)
292 tsf -= 0x8000;
293
294 return (tsf & ~0x7fff) | rstamp;
295}
296
297/* Interrupt handling */
298static int ath5k_init(struct ath5k_softc *sc);
299static int ath5k_stop_locked(struct ath5k_softc *sc);
300static int ath5k_stop_hw(struct ath5k_softc *sc);
301static irqreturn_t ath5k_intr(int irq, void *dev_id);
302static void ath5k_tasklet_reset(unsigned long data);
303
304static void ath5k_calibrate(unsigned long data);
305/* LED functions */
3a078876
BC		 306static int ath5k_init_leds(struct ath5k_softc *sc);
307static void ath5k_led_enable(struct ath5k_softc *sc);
308static void ath5k_led_off(struct ath5k_softc *sc);
309static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 310
311/*
312 * Module init/exit functions
313 */
314static int __init
315init_ath5k_pci(void)
316{
317 int ret;
318
319 ath5k_debug_init();
320
04a9e451 321 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 322 if (ret) {
323 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
324 return ret;
325 }
326
327 return 0;
328}
329
330static void __exit
331exit_ath5k_pci(void)
332{
04a9e451 333 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 334
335 ath5k_debug_finish();
336}
337
338module_init(init_ath5k_pci);
339module_exit(exit_ath5k_pci);
340
341
342/********************\
343* PCI Initialization *
344\********************/
345
346static const char *
347ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
348{
349 const char *name = "xxxxx";
350 unsigned int i;
351
352 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
353 if (srev_names[i].sr_type != type)
354 continue;
355 if ((val & 0xff) < srev_names[i + 1].sr_val) {
356 name = srev_names[i].sr_name;
357 break;
358 }
359 }
360
361 return name;
362}
363
364static int __devinit
365ath5k_pci_probe(struct pci_dev *pdev,
366 const struct pci_device_id *id)
367{
368 void __iomem *mem;
369 struct ath5k_softc *sc;
370 struct ieee80211_hw *hw;
371 int ret;
372 u8 csz;
373
374 ret = pci_enable_device(pdev);
375 if (ret) {
376 dev_err(&pdev->dev, "can't enable device\n");
377 goto err;
378 }
379
380 /* XXX 32-bit addressing only */
381 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
382 if (ret) {
383 dev_err(&pdev->dev, "32-bit DMA not available\n");
384 goto err_dis;
385 }
386
387 /*
388 * Cache line size is used to size and align various
389 * structures used to communicate with the hardware.
390 */
391 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
392 if (csz == 0) {
393 /*
394 * Linux 2.4.18 (at least) writes the cache line size
395 * register as a 16-bit wide register which is wrong.
396 * We must have this setup properly for rx buffer
397 * DMA to work so force a reasonable value here if it
398 * comes up zero.
399 */
400 csz = L1_CACHE_BYTES / sizeof(u32);
401 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
402 }
403 /*
404 * The default setting of latency timer yields poor results,
405 * set it to the value used by other systems. It may be worth
406 * tweaking this setting more.
407 */
408 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
409
410 /* Enable bus mastering */
411 pci_set_master(pdev);
412
413 /*
414 * Disable the RETRY_TIMEOUT register (0x41) to keep
415 * PCI Tx retries from interfering with C3 CPU state.
416 */
417 pci_write_config_byte(pdev, 0x41, 0);
418
419 ret = pci_request_region(pdev, 0, "ath5k");
420 if (ret) {
421 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
422 goto err_dis;
423 }
424
425 mem = pci_iomap(pdev, 0, 0);
426 if (!mem) {
427 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
428 ret = -EIO;
429 goto err_reg;
430 }
431
432 /*
433 * Allocate hw (mac80211 main struct)
434 * and hw->priv (driver private data)
435 */
436 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
437 if (hw == NULL) {
438 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
439 ret = -ENOMEM;
440 goto err_map;
441 }
442
443 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
444
445 /* Initialize driver private data */
446 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
448 IEEE80211_HW_SIGNAL_DBM |
449 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 450 hw->extra_tx_headroom = 2;
451 hw->channel_change_time = 5000;
fa1c114f
JS		 452 sc = hw->priv;
453 sc->hw = hw;
454 sc->pdev = pdev;
455
456 ath5k_debug_init_device(sc);
457
458 /*
459 * Mark the device as detached to avoid processing
460 * interrupts until setup is complete.
461 */
462 __set_bit(ATH_STAT_INVALID, sc->status);
463
464 sc->iobase = mem; /* So we can unmap it on detach */
465 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
466 sc->opmode = IEEE80211_IF_TYPE_STA;
467 mutex_init(&sc->lock);
468 spin_lock_init(&sc->rxbuflock);
469 spin_lock_init(&sc->txbuflock);
470
471 /* Set private data */
472 pci_set_drvdata(pdev, hw);
473
fa1c114f
JS		 474 /* Setup interrupt handler */
475 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
476 if (ret) {
477 ATH5K_ERR(sc, "request_irq failed\n");
478 goto err_free;
479 }
480
481 /* Initialize device */
482 sc->ah = ath5k_hw_attach(sc, id->driver_data);
483 if (IS_ERR(sc->ah)) {
484 ret = PTR_ERR(sc->ah);
485 goto err_irq;
486 }
487
488 /* Finish private driver data initialization */
489 ret = ath5k_attach(pdev, hw);
490 if (ret)
491 goto err_ah;
492
493 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
494 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
495 sc->ah->ah_mac_srev,
496 sc->ah->ah_phy_revision);
497
400ec45a 498 if (!sc->ah->ah_single_chip) {
fa1c114f 499 /* Single chip radio (!RF5111) */
400ec45a
LR		 500 if (sc->ah->ah_radio_5ghz_revision &&
501 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 502 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 503 if (!test_bit(AR5K_MODE_11A,
504 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 505 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 506 ath5k_chip_name(AR5K_VERSION_RAD,
507 sc->ah->ah_radio_5ghz_revision),
508 sc->ah->ah_radio_5ghz_revision);
509 /* No 2GHz support (5110 and some
510 * 5Ghz only cards) -> report 5Ghz radio */
511 } else if (!test_bit(AR5K_MODE_11B,
512 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 513 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 514 ath5k_chip_name(AR5K_VERSION_RAD,
515 sc->ah->ah_radio_5ghz_revision),
516 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 517 /* Multiband radio */
518 } else {
519 ATH5K_INFO(sc, "RF%s multiband radio found"
520 " (0x%x)\n",
400ec45a
LR		 521 ath5k_chip_name(AR5K_VERSION_RAD,
522 sc->ah->ah_radio_5ghz_revision),
523 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 524 }
525 }
400ec45a
LR		 526 /* Multi chip radio (RF5111 - RF2111) ->
527 * report both 2GHz/5GHz radios */
528 else if (sc->ah->ah_radio_5ghz_revision &&
529 sc->ah->ah_radio_2ghz_revision){
fa1c114f 530 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 531 ath5k_chip_name(AR5K_VERSION_RAD,
532 sc->ah->ah_radio_5ghz_revision),
533 sc->ah->ah_radio_5ghz_revision);
fa1c114f 534 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_2ghz_revision),
537 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 538 }
539 }
540
541
542 /* ready to process interrupts */
543 __clear_bit(ATH_STAT_INVALID, sc->status);
544
545 return 0;
546err_ah:
547 ath5k_hw_detach(sc->ah);
548err_irq:
549 free_irq(pdev->irq, sc);
550err_free:
fa1c114f
JS		 551 ieee80211_free_hw(hw);
552err_map:
553 pci_iounmap(pdev, mem);
554err_reg:
555 pci_release_region(pdev, 0);
556err_dis:
557 pci_disable_device(pdev);
558err:
559 return ret;
560}
561
562static void __devexit
563ath5k_pci_remove(struct pci_dev *pdev)
564{
565 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
566 struct ath5k_softc *sc = hw->priv;
567
568 ath5k_debug_finish_device(sc);
569 ath5k_detach(pdev, hw);
570 ath5k_hw_detach(sc->ah);
571 free_irq(pdev->irq, sc);
fa1c114f
JS		 572 pci_iounmap(pdev, sc->iobase);
573 pci_release_region(pdev, 0);
574 pci_disable_device(pdev);
575 ieee80211_free_hw(hw);
576}
577
578#ifdef CONFIG_PM
579static int
580ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
581{
582 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
583 struct ath5k_softc *sc = hw->priv;
584
3a078876 585 ath5k_led_off(sc);
fa1c114f
JS		 586
587 ath5k_stop_hw(sc);
3e4242b9
JS		 588
589 free_irq(pdev->irq, sc);
fa1c114f
JS		 590 pci_save_state(pdev);
591 pci_disable_device(pdev);
592 pci_set_power_state(pdev, PCI_D3hot);
593
594 return 0;
595}
596
597static int
598ath5k_pci_resume(struct pci_dev *pdev)
599{
600 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
601 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 602 struct ath5k_hw *ah = sc->ah;
603 int i, err;
fa1c114f 604
3e4242b9 605 pci_restore_state(pdev);
fa1c114f
JS		 606
607 err = pci_enable_device(pdev);
608 if (err)
609 return err;
610
fa1c114f
JS		 611 /*
612 * Suspend/Resume resets the PCI configuration space, so we have to
613 * re-disable the RETRY_TIMEOUT register (0x41) to keep
614 * PCI Tx retries from interfering with C3 CPU state
615 */
616 pci_write_config_byte(pdev, 0x41, 0);
617
3e4242b9
JS		 618 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
619 if (err) {
620 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 621 goto err_no_irq;
3e4242b9
JS		 622 }
623
624 err = ath5k_init(sc);
625 if (err)
626 goto err_irq;
3a078876 627 ath5k_led_enable(sc);
fa1c114f 628
247ae449
JL		 629 /*
630 * Reset the key cache since some parts do not
631 * reset the contents on initial power up or resume.
632 *
633 * FIXME: This may need to be revisited when mac80211 becomes
634 * aware of suspend/resume.
635 */
636 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
637 ath5k_hw_reset_key(ah, i);
638
fa1c114f 639 return 0;
3e4242b9
JS		 640err_irq:
641 free_irq(pdev->irq, sc);
37465c8a 642err_no_irq:
3e4242b9
JS		 643 pci_disable_device(pdev);
644 return err;
fa1c114f
JS		 645}
646#endif /* CONFIG_PM */
647
648
649
650/***********************\
651* Driver Initialization *
652\***********************/
653
654static int
655ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
656{
657 struct ath5k_softc *sc = hw->priv;
658 struct ath5k_hw *ah = sc->ah;
659 u8 mac[ETH_ALEN];
660 unsigned int i;
661 int ret;
662
663 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
664
665 /*
666 * Check if the MAC has multi-rate retry support.
667 * We do this by trying to setup a fake extended
668 * descriptor. MAC's that don't have support will
669 * return false w/o doing anything. MAC's that do
670 * support it will return true w/o doing anything.
671 */
b9887638
JS		 672 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
673 if (ret < 0)
674 goto err;
675 if (ret > 0)
fa1c114f
JS		 676 __set_bit(ATH_STAT_MRRETRY, sc->status);
677
678 /*
679 * Reset the key cache since some parts do not
680 * reset the contents on initial power up.
681 */
c65638a7 682 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 683 ath5k_hw_reset_key(ah, i);
684
685 /*
686 * Collect the channel list. The 802.11 layer
687 * is resposible for filtering this list based
688 * on settings like the phy mode and regulatory
689 * domain restrictions.
690 */
691 ret = ath5k_getchannels(hw);
692 if (ret) {
693 ATH5K_ERR(sc, "can't get channels\n");
694 goto err;
695 }
696
d8ee398d
LR		 697 /* Set *_rates so we can map hw rate index */
698 ath5k_set_total_hw_rates(sc);
699
fa1c114f 700 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 701 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
702 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 703 else
d8ee398d 704 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 705
706 /*
707 * Allocate tx+rx descriptors and populate the lists.
708 */
709 ret = ath5k_desc_alloc(sc, pdev);
710 if (ret) {
711 ATH5K_ERR(sc, "can't allocate descriptors\n");
712 goto err;
713 }
714
715 /*
716 * Allocate hardware transmit queues: one queue for
717 * beacon frames and one data queue for each QoS
718 * priority. Note that hw functions handle reseting
719 * these queues at the needed time.
720 */
721 ret = ath5k_beaconq_setup(ah);
722 if (ret < 0) {
723 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
724 goto err_desc;
725 }
726 sc->bhalq = ret;
727
728 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
729 if (IS_ERR(sc->txq)) {
730 ATH5K_ERR(sc, "can't setup xmit queue\n");
731 ret = PTR_ERR(sc->txq);
732 goto err_bhal;
733 }
734
735 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
736 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
737 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
738 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 739
740 ath5k_hw_get_lladdr(ah, mac);
741 SET_IEEE80211_PERM_ADDR(hw, mac);
742 /* All MAC address bits matter for ACKs */
743 memset(sc->bssidmask, 0xff, ETH_ALEN);
744 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
745
746 ret = ieee80211_register_hw(hw);
747 if (ret) {
748 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
749 goto err_queues;
750 }
751
3a078876
BC		 752 ath5k_init_leds(sc);
753
fa1c114f
JS		 754 return 0;
755err_queues:
756 ath5k_txq_release(sc);
757err_bhal:
758 ath5k_hw_release_tx_queue(ah, sc->bhalq);
759err_desc:
760 ath5k_desc_free(sc, pdev);
761err:
762 return ret;
763}
764
765static void
766ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
767{
768 struct ath5k_softc *sc = hw->priv;
769
770 /*
771 * NB: the order of these is important:
772 * o call the 802.11 layer before detaching ath5k_hw to
773 * insure callbacks into the driver to delete global
774 * key cache entries can be handled
775 * o reclaim the tx queue data structures after calling
776 * the 802.11 layer as we'll get called back to reclaim
777 * node state and potentially want to use them
778 * o to cleanup the tx queues the hal is called, so detach
779 * it last
780 * XXX: ??? detach ath5k_hw ???
781 * Other than that, it's straightforward...
782 */
783 ieee80211_unregister_hw(hw);
784 ath5k_desc_free(sc, pdev);
785 ath5k_txq_release(sc);
786 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 787 ath5k_unregister_leds(sc);
fa1c114f
JS		 788
789 /*
790 * NB: can't reclaim these until after ieee80211_ifdetach
791 * returns because we'll get called back to reclaim node
792 * state and potentially want to use them.
793 */
794}
795
796
797
798
799/********************\
800* Channel/mode setup *
801\********************/
802
803/*
804 * Convert IEEE channel number to MHz frequency.
805 */
806static inline short
807ath5k_ieee2mhz(short chan)
808{
809 if (chan <= 14 || chan >= 27)
810 return ieee80211chan2mhz(chan);
811 else
812 return 2212 + chan * 20;
813}
814
815static unsigned int
816ath5k_copy_rates(struct ieee80211_rate *rates,
817 const struct ath5k_rate_table *rt,
818 unsigned int max)
819{
820 unsigned int i, count;
821
822 if (rt == NULL)
823 return 0;
824
825 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 826 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
827 rates[count].hw_value = rt->rates[i].rate_code;
828 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 829 count++;
830 max--;
831 }
832
833 return count;
834}
835
836static unsigned int
837ath5k_copy_channels(struct ath5k_hw *ah,
838 struct ieee80211_channel *channels,
839 unsigned int mode,
840 unsigned int max)
841{
d8ee398d 842 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 843
844 if (!test_bit(mode, ah->ah_modes))
845 return 0;
846
fa1c114f 847 switch (mode) {
d8ee398d
LR		 848 case AR5K_MODE_11A:
849 case AR5K_MODE_11A_TURBO:
fa1c114f 850 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 851 size = 220 ;
fa1c114f
JS		 852 chfreq = CHANNEL_5GHZ;
853 break;
d8ee398d
LR		 854 case AR5K_MODE_11B:
855 case AR5K_MODE_11G:
856 case AR5K_MODE_11G_TURBO:
857 size = 26;
fa1c114f
JS		 858 chfreq = CHANNEL_2GHZ;
859 break;
860 default:
861 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
862 return 0;
863 }
864
865 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 866 ch = i + 1 ;
867 freq = ath5k_ieee2mhz(ch);
fa1c114f 868
d8ee398d
LR		 869 /* Check if channel is supported by the chipset */
870 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 871 continue;
872
d8ee398d
LR		 873 /* Write channel info and increment counter */
874 channels[count].center_freq = freq;
a3f4b914
LR		 875 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
876 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 877 switch (mode) {
878 case AR5K_MODE_11A:
879 case AR5K_MODE_11G:
880 channels[count].hw_value = chfreq | CHANNEL_OFDM;
881 break;
882 case AR5K_MODE_11A_TURBO:
883 case AR5K_MODE_11G_TURBO:
884 channels[count].hw_value = chfreq |
885 CHANNEL_OFDM | CHANNEL_TURBO;
886 break;
887 case AR5K_MODE_11B:
d8ee398d
LR		 888 channels[count].hw_value = CHANNEL_B;
889 }
fa1c114f 890
fa1c114f
JS		 891 count++;
892 max--;
893 }
894
895 return count;
896}
897
d8ee398d
LR		 898static int
899ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 900{
901 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 902 struct ath5k_hw *ah = sc->ah;
903 struct ieee80211_supported_band *sbands = sc->sbands;
904 const struct ath5k_rate_table *hw_rates;
905 unsigned int max_r, max_c, count_r, count_c;
906 int mode2g = AR5K_MODE_11G;
fa1c114f 907
d8ee398d 908 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 909
d8ee398d
LR		 910 max_r = ARRAY_SIZE(sc->rates);
911 max_c = ARRAY_SIZE(sc->channels);
912 count_r = count_c = 0;
913
914 /* 2GHz band */
400ec45a 915 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 916 mode2g = AR5K_MODE_11B;
400ec45a
LR		 917 if (!test_bit(AR5K_MODE_11B,
918 sc->ah->ah_capabilities.cap_mode))
d8ee398d 919 mode2g = -1;
fa1c114f 920 }
fa1c114f 921
400ec45a
LR		 922 if (mode2g > 0) {
923 struct ieee80211_supported_band *sband =
924 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 925
d8ee398d
LR		 926 sband->bitrates = sc->rates;
927 sband->channels = sc->channels;
fa1c114f 928
d8ee398d
LR		 929 sband->band = IEEE80211_BAND_2GHZ;
930 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
931 mode2g, max_c);
fa1c114f 932
d8ee398d
LR		 933 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
934 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 935 hw_rates, max_r);
fa1c114f 936
d8ee398d
LR		 937 count_c = sband->n_channels;
938 count_r = sband->n_bitrates;
fa1c114f 939
d8ee398d
LR		 940 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
941
942 max_r -= count_r;
943 max_c -= count_c;
fa1c114f 944
fa1c114f
JS		 945 }
946
d8ee398d 947 /* 5GHz band */
fa1c114f 948
400ec45a
LR		 949 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
950 struct ieee80211_supported_band *sband =
951 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 952
d8ee398d
LR		 953 sband->bitrates = &sc->rates[count_r];
954 sband->channels = &sc->channels[count_c];
fa1c114f 955
d8ee398d
LR		 956 sband->band = IEEE80211_BAND_5GHZ;
957 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
958 AR5K_MODE_11A, max_c);
959
960 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
961 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 962 hw_rates, max_r);
d8ee398d
LR		 963
964 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
965 }
966
b446197c 967 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 968
969 return 0;
fa1c114f
JS		 970}
971
972/*
973 * Set/change channels. If the channel is really being changed,
974 * it's done by reseting the chip. To accomplish this we must
975 * first cleanup any pending DMA, then restart stuff after a la
976 * ath5k_init.
977 */
978static int
979ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
980{
d8ee398d
LR		 981 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
982 sc->curchan->center_freq, chan->center_freq);
983
984 if (chan->center_freq != sc->curchan->center_freq ||
985 chan->hw_value != sc->curchan->hw_value) {
986
987 sc->curchan = chan;
988 sc->curband = &sc->sbands[chan->band];
fa1c114f 989
fa1c114f
JS		 990 /*
991 * To switch channels clear any pending DMA operations;
992 * wait long enough for the RX fifo to drain, reset the
993 * hardware at the new frequency, and then re-enable
994 * the relevant bits of the h/w.
995 */
d7dc1003 996 return ath5k_reset(sc, true, true);
fa1c114f
JS		 997 }
998
999 return 0;
1000}
1001
1002static void
1003ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1004{
fa1c114f 1005 sc->curmode = mode;
d8ee398d 1006
400ec45a 1007 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1008 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1009 } else {
1010 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1011 }
fa1c114f
JS		 1012}
1013
1014static void
1015ath5k_mode_setup(struct ath5k_softc *sc)
1016{
1017 struct ath5k_hw *ah = sc->ah;
1018 u32 rfilt;
1019
1020 /* configure rx filter */
1021 rfilt = sc->filter_flags;
1022 ath5k_hw_set_rx_filter(ah, rfilt);
1023
1024 if (ath5k_hw_hasbssidmask(ah))
1025 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1026
1027 /* configure operational mode */
1028 ath5k_hw_set_opmode(ah);
1029
1030 ath5k_hw_set_mcast_filter(ah, 0, 0);
1031 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1032}
1033
d8ee398d
LR		 1034/*
1035 * Match the hw provided rate index (through descriptors)
1036 * to an index for sc->curband->bitrates, so it can be used
1037 * by the stack.
1038 *
1039 * This one is a little bit tricky but i think i'm right
1040 * about this...
1041 *
1042 * We have 4 rate tables in the following order:
1043 * XR (4 rates)
1044 * 802.11a (8 rates)
1045 * 802.11b (4 rates)
1046 * 802.11g (12 rates)
1047 * that make the hw rate table.
1048 *
1049 * Lets take a 5211 for example that supports a and b modes only.
1050 * First comes the 802.11a table and then 802.11b (total 12 rates).
1051 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1052 * if it returns 2 it points to the second 802.11a rate etc.
1053 *
1054 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1055 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1056 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1057 */
1058static void
400ec45a 1059ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1060
1061 struct ath5k_hw *ah = sc->ah;
1062
400ec45a 1063 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1064 sc->a_rates = 8;
1065
400ec45a 1066 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1067 sc->b_rates = 4;
1068
400ec45a 1069 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1070 sc->g_rates = 12;
1071
1072 /* XXX: Need to see what what happens when
1073 xr disable bits in eeprom are set */
400ec45a 1074 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1075 sc->xr_rates = 4;
1076
1077}
1078
1079static inline int
400ec45a 1080ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1081
1082 int mac80211_rix;
1083
400ec45a 1084 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1085 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1086 mac80211_rix =
1087 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1088 } else {
1089 mac80211_rix = hw_rix - sc->xr_rates;
1090 }
1091
1092 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1093 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1094 (mac80211_rix <= 0 ))
d8ee398d 1095 mac80211_rix = 1;
d8ee398d
LR		 1096
1097 return mac80211_rix;
1098}
1099
fa1c114f
JS		 1100
1101
1102
1103/***************\
1104* Buffers setup *
1105\***************/
1106
1107static int
1108ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1109{
1110 struct ath5k_hw *ah = sc->ah;
1111 struct sk_buff *skb = bf->skb;
1112 struct ath5k_desc *ds;
1113
1114 if (likely(skb == NULL)) {
1115 unsigned int off;
1116
1117 /*
1118 * Allocate buffer with headroom_needed space for the
1119 * fake physical layer header at the start.
1120 */
1121 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1122 if (unlikely(skb == NULL)) {
1123 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1124 sc->rxbufsize + sc->cachelsz - 1);
1125 return -ENOMEM;
1126 }
1127 /*
1128 * Cache-line-align. This is important (for the
1129 * 5210 at least) as not doing so causes bogus data
1130 * in rx'd frames.
1131 */
1132 off = ((unsigned long)skb->data) % sc->cachelsz;
1133 if (off != 0)
1134 skb_reserve(skb, sc->cachelsz - off);
1135
1136 bf->skb = skb;
1137 bf->skbaddr = pci_map_single(sc->pdev,
1138 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1139 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1140 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1141 dev_kfree_skb(skb);
1142 bf->skb = NULL;
1143 return -ENOMEM;
1144 }
1145 }
1146
1147 /*
1148 * Setup descriptors. For receive we always terminate
1149 * the descriptor list with a self-linked entry so we'll
1150 * not get overrun under high load (as can happen with a
1151 * 5212 when ANI processing enables PHY error frames).
1152 *
1153 * To insure the last descriptor is self-linked we create
1154 * each descriptor as self-linked and add it to the end. As
1155 * each additional descriptor is added the previous self-linked
1156 * entry is ``fixed'' naturally. This should be safe even
1157 * if DMA is happening. When processing RX interrupts we
1158 * never remove/process the last, self-linked, entry on the
1159 * descriptor list. This insures the hardware always has
1160 * someplace to write a new frame.
1161 */
1162 ds = bf->desc;
1163 ds->ds_link = bf->daddr; /* link to self */
1164 ds->ds_data = bf->skbaddr;
1165 ath5k_hw_setup_rx_desc(ah, ds,
1166 skb_tailroom(skb), /* buffer size */
1167 0);
1168
1169 if (sc->rxlink != NULL)
1170 *sc->rxlink = bf->daddr;
1171 sc->rxlink = &ds->ds_link;
1172 return 0;
1173}
1174
1175static int
e039fa4a 1176ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1177{
1178 struct ath5k_hw *ah = sc->ah;
1179 struct ath5k_txq *txq = sc->txq;
1180 struct ath5k_desc *ds = bf->desc;
1181 struct sk_buff *skb = bf->skb;
a888d52d 1182 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1183 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1184 int ret;
1185
1186 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1187
fa1c114f
JS		 1188 /* XXX endianness */
1189 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1190 PCI_DMA_TODEVICE);
1191
e039fa4a 1192 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1193 flags |= AR5K_TXDESC_NOACK;
1194
281c56dd 1195 pktlen = skb->len;
fa1c114f 1196
d0f09804 1197 if (info->control.hw_key) {
e039fa4a
JB		 1198 keyidx = info->control.hw_key->hw_key_idx;
1199 pktlen += info->control.icv_len;
fa1c114f 1200 }
fa1c114f
JS		 1201 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1202 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1203 (sc->power_level * 2),
e039fa4a
JB		 1204 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1205 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1206 if (ret)
1207 goto err_unmap;
1208
1209 ds->ds_link = 0;
1210 ds->ds_data = bf->skbaddr;
1211
1212 spin_lock_bh(&txq->lock);
1213 list_add_tail(&bf->list, &txq->q);
57ffc589 1214 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1215 if (txq->link == NULL) /* is this first packet? */
1216 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1217 else /* no, so only link it */
1218 *txq->link = bf->daddr;
1219
1220 txq->link = &ds->ds_link;
1221 ath5k_hw_tx_start(ah, txq->qnum);
274c7c36 1222 mmiowb();
fa1c114f
JS		 1223 spin_unlock_bh(&txq->lock);
1224
1225 return 0;
1226err_unmap:
1227 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1228 return ret;
1229}
1230
1231/*******************\
1232* Descriptors setup *
1233\*******************/
1234
1235static int
1236ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1237{
1238 struct ath5k_desc *ds;
1239 struct ath5k_buf *bf;
1240 dma_addr_t da;
1241 unsigned int i;
1242 int ret;
1243
1244 /* allocate descriptors */
1245 sc->desc_len = sizeof(struct ath5k_desc) *
1246 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1247 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1248 if (sc->desc == NULL) {
1249 ATH5K_ERR(sc, "can't allocate descriptors\n");
1250 ret = -ENOMEM;
1251 goto err;
1252 }
1253 ds = sc->desc;
1254 da = sc->desc_daddr;
1255 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1256 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1257
1258 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1259 sizeof(struct ath5k_buf), GFP_KERNEL);
1260 if (bf == NULL) {
1261 ATH5K_ERR(sc, "can't allocate bufptr\n");
1262 ret = -ENOMEM;
1263 goto err_free;
1264 }
1265 sc->bufptr = bf;
1266
1267 INIT_LIST_HEAD(&sc->rxbuf);
1268 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1269 bf->desc = ds;
1270 bf->daddr = da;
1271 list_add_tail(&bf->list, &sc->rxbuf);
1272 }
1273
1274 INIT_LIST_HEAD(&sc->txbuf);
1275 sc->txbuf_len = ATH_TXBUF;
1276 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1277 da += sizeof(*ds)) {
1278 bf->desc = ds;
1279 bf->daddr = da;
1280 list_add_tail(&bf->list, &sc->txbuf);
1281 }
1282
1283 /* beacon buffer */
1284 bf->desc = ds;
1285 bf->daddr = da;
1286 sc->bbuf = bf;
1287
1288 return 0;
1289err_free:
1290 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1291err:
1292 sc->desc = NULL;
1293 return ret;
1294}
1295
1296static void
1297ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1298{
1299 struct ath5k_buf *bf;
1300
1301 ath5k_txbuf_free(sc, sc->bbuf);
1302 list_for_each_entry(bf, &sc->txbuf, list)
1303 ath5k_txbuf_free(sc, bf);
1304 list_for_each_entry(bf, &sc->rxbuf, list)
1305 ath5k_txbuf_free(sc, bf);
1306
1307 /* Free memory associated with all descriptors */
1308 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1309
1310 kfree(sc->bufptr);
1311 sc->bufptr = NULL;
1312}
1313
1314
1315
1316
1317
1318/**************\
1319* Queues setup *
1320\**************/
1321
1322static struct ath5k_txq *
1323ath5k_txq_setup(struct ath5k_softc *sc,
1324 int qtype, int subtype)
1325{
1326 struct ath5k_hw *ah = sc->ah;
1327 struct ath5k_txq *txq;
1328 struct ath5k_txq_info qi = {
1329 .tqi_subtype = subtype,
1330 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1331 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1332 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1333 };
1334 int qnum;
1335
1336 /*
1337 * Enable interrupts only for EOL and DESC conditions.
1338 * We mark tx descriptors to receive a DESC interrupt
1339 * when a tx queue gets deep; otherwise waiting for the
1340 * EOL to reap descriptors. Note that this is done to
1341 * reduce interrupt load and this only defers reaping
1342 * descriptors, never transmitting frames. Aside from
1343 * reducing interrupts this also permits more concurrency.
1344 * The only potential downside is if the tx queue backs
1345 * up in which case the top half of the kernel may backup
1346 * due to a lack of tx descriptors.
1347 */
1348 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1349 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1350 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1351 if (qnum < 0) {
1352 /*
1353 * NB: don't print a message, this happens
1354 * normally on parts with too few tx queues
1355 */
1356 return ERR_PTR(qnum);
1357 }
1358 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1359 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1360 qnum, ARRAY_SIZE(sc->txqs));
1361 ath5k_hw_release_tx_queue(ah, qnum);
1362 return ERR_PTR(-EINVAL);
1363 }
1364 txq = &sc->txqs[qnum];
1365 if (!txq->setup) {
1366 txq->qnum = qnum;
1367 txq->link = NULL;
1368 INIT_LIST_HEAD(&txq->q);
1369 spin_lock_init(&txq->lock);
1370 txq->setup = true;
1371 }
1372 return &sc->txqs[qnum];
1373}
1374
1375static int
1376ath5k_beaconq_setup(struct ath5k_hw *ah)
1377{
1378 struct ath5k_txq_info qi = {
1379 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1380 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1381 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1382 /* NB: for dynamic turbo, don't enable any other interrupts */
1383 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1384 };
1385
1386 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1387}
1388
1389static int
1390ath5k_beaconq_config(struct ath5k_softc *sc)
1391{
1392 struct ath5k_hw *ah = sc->ah;
1393 struct ath5k_txq_info qi;
1394 int ret;
1395
1396 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1397 if (ret)
1398 return ret;
8e5f3d0a
AY		 1399 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1400 sc->opmode == IEEE80211_IF_TYPE_MESH_POINT) {
fa1c114f
JS		 1401 /*
1402 * Always burst out beacon and CAB traffic
1403 * (aifs = cwmin = cwmax = 0)
1404 */
1405 qi.tqi_aifs = 0;
1406 qi.tqi_cw_min = 0;
1407 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1408 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1409 /*
1410 * Adhoc mode; backoff between 0 and (2 * cw_min).
1411 */
1412 qi.tqi_aifs = 0;
1413 qi.tqi_cw_min = 0;
1414 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1415 }
1416
6d91e1d8
BR		 1417 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1418 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1419 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1420
fa1c114f
JS		 1421 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1422 if (ret) {
1423 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1424 "hardware queue!\n", __func__);
1425 return ret;
1426 }
1427
1428 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1429}
1430
1431static void
1432ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1433{
1434 struct ath5k_buf *bf, *bf0;
1435
1436 /*
1437 * NB: this assumes output has been stopped and
1438 * we do not need to block ath5k_tx_tasklet
1439 */
1440 spin_lock_bh(&txq->lock);
1441 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1442 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1443
1444 ath5k_txbuf_free(sc, bf);
1445
1446 spin_lock_bh(&sc->txbuflock);
57ffc589 1447 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1448 list_move_tail(&bf->list, &sc->txbuf);
1449 sc->txbuf_len++;
1450 spin_unlock_bh(&sc->txbuflock);
1451 }
1452 txq->link = NULL;
1453 spin_unlock_bh(&txq->lock);
1454}
1455
1456/*
1457 * Drain the transmit queues and reclaim resources.
1458 */
1459static void
1460ath5k_txq_cleanup(struct ath5k_softc *sc)
1461{
1462 struct ath5k_hw *ah = sc->ah;
1463 unsigned int i;
1464
1465 /* XXX return value */
1466 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1467 /* don't touch the hardware if marked invalid */
1468 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1469 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1470 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1471 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1472 if (sc->txqs[i].setup) {
1473 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1474 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1475 "link %p\n",
1476 sc->txqs[i].qnum,
1477 ath5k_hw_get_tx_buf(ah,
1478 sc->txqs[i].qnum),
1479 sc->txqs[i].link);
1480 }
1481 }
36d6825b 1482 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1483
1484 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1485 if (sc->txqs[i].setup)
1486 ath5k_txq_drainq(sc, &sc->txqs[i]);
1487}
1488
1489static void
1490ath5k_txq_release(struct ath5k_softc *sc)
1491{
1492 struct ath5k_txq *txq = sc->txqs;
1493 unsigned int i;
1494
1495 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1496 if (txq->setup) {
1497 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1498 txq->setup = false;
1499 }
1500}
1501
1502
1503
1504
1505/*************\
1506* RX Handling *
1507\*************/
1508
1509/*
1510 * Enable the receive h/w following a reset.
1511 */
1512static int
1513ath5k_rx_start(struct ath5k_softc *sc)
1514{
1515 struct ath5k_hw *ah = sc->ah;
1516 struct ath5k_buf *bf;
1517 int ret;
1518
1519 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1520
1521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1522 sc->cachelsz, sc->rxbufsize);
1523
1524 sc->rxlink = NULL;
1525
1526 spin_lock_bh(&sc->rxbuflock);
1527 list_for_each_entry(bf, &sc->rxbuf, list) {
1528 ret = ath5k_rxbuf_setup(sc, bf);
1529 if (ret != 0) {
1530 spin_unlock_bh(&sc->rxbuflock);
1531 goto err;
1532 }
1533 }
1534 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1535 spin_unlock_bh(&sc->rxbuflock);
1536
1537 ath5k_hw_put_rx_buf(ah, bf->daddr);
1538 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1539 ath5k_mode_setup(sc); /* set filters, etc. */
1540 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1541
1542 return 0;
1543err:
1544 return ret;
1545}
1546
1547/*
1548 * Disable the receive h/w in preparation for a reset.
1549 */
1550static void
1551ath5k_rx_stop(struct ath5k_softc *sc)
1552{
1553 struct ath5k_hw *ah = sc->ah;
1554
1555 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1556 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1557 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1558
1559 ath5k_debug_printrxbuffs(sc, ah);
1560
1561 sc->rxlink = NULL; /* just in case */
1562}
1563
1564static unsigned int
1565ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1566 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1567{
1568 struct ieee80211_hdr *hdr = (void *)skb->data;
1569 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1570
b47f407b
BR		 1571 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1572 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1573 return RX_FLAG_DECRYPTED;
1574
1575 /* Apparently when a default key is used to decrypt the packet
1576 the hw does not set the index used to decrypt. In such cases
1577 get the index from the packet. */
24b56e70
HH		 1578 if (ieee80211_has_protected(hdr->frame_control) &&
1579 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1580 skb->len >= hlen + 4) {
fa1c114f
JS		 1581 keyix = skb->data[hlen + 3] >> 6;
1582
1583 if (test_bit(keyix, sc->keymap))
1584 return RX_FLAG_DECRYPTED;
1585 }
1586
1587 return 0;
1588}
1589
036cd1ec
BR		 1590
1591static void
6ba81c2c
BR		 1592ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1593 struct ieee80211_rx_status *rxs)
036cd1ec 1594{
6ba81c2c 1595 u64 tsf, bc_tstamp;
036cd1ec
BR		 1596 u32 hw_tu;
1597 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1598
24b56e70 1599 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1600 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1601 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1602 /*
6ba81c2c
BR		 1603 * Received an IBSS beacon with the same BSSID. Hardware *must*
1604 * have updated the local TSF. We have to work around various
1605 * hardware bugs, though...
036cd1ec 1606 */
6ba81c2c
BR		 1607 tsf = ath5k_hw_get_tsf64(sc->ah);
1608 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1609 hw_tu = TSF_TO_TU(tsf);
1610
1611 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1612 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1613 (unsigned long long)bc_tstamp,
1614 (unsigned long long)rxs->mactime,
1615 (unsigned long long)(rxs->mactime - bc_tstamp),
1616 (unsigned long long)tsf);
6ba81c2c
BR		 1617
1618 /*
1619 * Sometimes the HW will give us a wrong tstamp in the rx
1620 * status, causing the timestamp extension to go wrong.
1621 * (This seems to happen especially with beacon frames bigger
1622 * than 78 byte (incl. FCS))
1623 * But we know that the receive timestamp must be later than the
1624 * timestamp of the beacon since HW must have synced to that.
1625 *
1626 * NOTE: here we assume mactime to be after the frame was
1627 * received, not like mac80211 which defines it at the start.
1628 */
1629 if (bc_tstamp > rxs->mactime) {
036cd1ec 1630 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1631 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1632 (unsigned long long)rxs->mactime,
1633 (unsigned long long)tsf);
6ba81c2c 1634 rxs->mactime = tsf;
036cd1ec 1635 }
6ba81c2c
BR		 1636
1637 /*
1638 * Local TSF might have moved higher than our beacon timers,
1639 * in that case we have to update them to continue sending
1640 * beacons. This also takes care of synchronizing beacon sending
1641 * times with other stations.
1642 */
1643 if (hw_tu >= sc->nexttbtt)
1644 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1645 }
1646}
1647
1648
fa1c114f
JS		 1649static void
1650ath5k_tasklet_rx(unsigned long data)
1651{
1652 struct ieee80211_rx_status rxs = {};
b47f407b 1653 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1654 struct sk_buff *skb;
1655 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1656 struct ath5k_buf *bf, *bf_last;
fa1c114f 1657 struct ath5k_desc *ds;
fa1c114f
JS		 1658 int ret;
1659 int hdrlen;
1660 int pad;
1661
1662 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1663 if (list_empty(&sc->rxbuf)) {
1664 ATH5K_WARN(sc, "empty rx buf pool\n");
1665 goto unlock;
1666 }
1667 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1668 do {
d6894b5b
BC		 1669 rxs.flag = 0;
1670
fa1c114f
JS		 1671 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1672 BUG_ON(bf->skb == NULL);
1673 skb = bf->skb;
1674 ds = bf->desc;
1675
3a0f2c87
JS		 1676 /*
1677 * last buffer must not be freed to ensure proper hardware
1678 * function. When the hardware finishes also a packet next to
1679 * it, we are sure, it doesn't use it anymore and we can go on.
1680 */
1681 if (bf_last == bf)
1682 bf->flags |= 1;
1683 if (bf->flags) {
1684 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1685 struct ath5k_buf, list);
1686 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1687 &rs);
1688 if (ret)
1689 break;
1690 bf->flags &= ~1;
1691 /* skip the overwritten one (even status is martian) */
1692 goto next;
1693 }
fa1c114f 1694
b47f407b 1695 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1696 if (unlikely(ret == -EINPROGRESS))
1697 break;
1698 else if (unlikely(ret)) {
1699 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1700 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1701 return;
1702 }
1703
b47f407b 1704 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1705 ATH5K_WARN(sc, "unsupported jumbo\n");
1706 goto next;
1707 }
1708
b47f407b
BR		 1709 if (unlikely(rs.rs_status)) {
1710 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1711 goto next;
b47f407b 1712 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1713 /*
1714 * Decrypt error. If the error occurred
1715 * because there was no hardware key, then
1716 * let the frame through so the upper layers
1717 * can process it. This is necessary for 5210
1718 * parts which have no way to setup a ``clear''
1719 * key cache entry.
1720 *
1721 * XXX do key cache faulting
1722 */
b47f407b
BR		 1723 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1724 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1725 goto accept;
1726 }
b47f407b 1727 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1728 rxs.flag |= RX_FLAG_MMIC_ERROR;
1729 goto accept;
1730 }
1731
1732 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1733 if ((rs.rs_status &
1734 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1735 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1736 goto next;
1737 }
1738accept:
fa1c114f
JS		 1739 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1740 PCI_DMA_FROMDEVICE);
1741 bf->skb = NULL;
1742
b47f407b 1743 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1744
1745 /*
1746 * the hardware adds a padding to 4 byte boundaries between
1747 * the header and the payload data if the header length is
1748 * not multiples of 4 - remove it
1749 */
1750 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1751 if (hdrlen & 3) {
1752 pad = hdrlen % 4;
1753 memmove(skb->data + pad, skb->data, hdrlen);
1754 skb_pull(skb, pad);
1755 }
1756
c0e1899b
BR		 1757 /*
1758 * always extend the mac timestamp, since this information is
1759 * also needed for proper IBSS merging.
1760 *
1761 * XXX: it might be too late to do it here, since rs_tstamp is
1762 * 15bit only. that means TSF extension has to be done within
1763 * 32768usec (about 32ms). it might be necessary to move this to
1764 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1765 *
1766 * Unfortunately we don't know when the hardware takes the rx
1767 * timestamp (beginning of phy frame, data frame, end of rx?).
1768 * The only thing we know is that it is hardware specific...
1769 * On AR5213 it seems the rx timestamp is at the end of the
1770 * frame, but i'm not sure.
1771 *
1772 * NOTE: mac80211 defines mactime at the beginning of the first
1773 * data symbol. Since we don't have any time references it's
1774 * impossible to comply to that. This affects IBSS merge only
1775 * right now, so it's not too bad...
c0e1899b 1776 */
b47f407b 1777 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1778 rxs.flag |= RX_FLAG_TSFT;
1779
d8ee398d
LR		 1780 rxs.freq = sc->curchan->center_freq;
1781 rxs.band = sc->curband->band;
fa1c114f 1782
fa1c114f 1783 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1784 rxs.signal = rxs.noise + rs.rs_rssi;
1785 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1786
b47f407b
BR		 1787 rxs.antenna = rs.rs_antenna;
1788 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1789 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1790
1791 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1792
036cd1ec
BR		 1793 /* check beacons in IBSS mode */
1794 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1795 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1796
fa1c114f 1797 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1798next:
1799 list_move_tail(&bf->list, &sc->rxbuf);
1800 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1801unlock:
fa1c114f
JS		 1802 spin_unlock(&sc->rxbuflock);
1803}
1804
1805
1806
1807
1808/*************\
1809* TX Handling *
1810\*************/
1811
1812static void
1813ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1814{
b47f407b 1815 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1816 struct ath5k_buf *bf, *bf0;
1817 struct ath5k_desc *ds;
1818 struct sk_buff *skb;
e039fa4a 1819 struct ieee80211_tx_info *info;
fa1c114f
JS		 1820 int ret;
1821
1822 spin_lock(&txq->lock);
1823 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1824 ds = bf->desc;
1825
b47f407b 1826 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1827 if (unlikely(ret == -EINPROGRESS))
1828 break;
1829 else if (unlikely(ret)) {
1830 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1831 ret, txq->qnum);
1832 break;
1833 }
1834
1835 skb = bf->skb;
a888d52d 1836 info = IEEE80211_SKB_CB(skb);
fa1c114f 1837 bf->skb = NULL;
e039fa4a 1838
fa1c114f
JS		 1839 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1840 PCI_DMA_TODEVICE);
1841
e039fa4a 1842 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1843 if (unlikely(ts.ts_status)) {
fa1c114f 1844 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1845 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1846 info->status.excessive_retries = 1;
b47f407b 1847 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1848 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1849 } else {
e039fa4a
JB		 1850 info->flags |= IEEE80211_TX_STAT_ACK;
1851 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1852 }
1853
e039fa4a 1854 ieee80211_tx_status(sc->hw, skb);
57ffc589 1855 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1856
1857 spin_lock(&sc->txbuflock);
57ffc589 1858 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1859 list_move_tail(&bf->list, &sc->txbuf);
1860 sc->txbuf_len++;
1861 spin_unlock(&sc->txbuflock);
1862 }
1863 if (likely(list_empty(&txq->q)))
1864 txq->link = NULL;
1865 spin_unlock(&txq->lock);
1866 if (sc->txbuf_len > ATH_TXBUF / 5)
1867 ieee80211_wake_queues(sc->hw);
1868}
1869
1870static void
1871ath5k_tasklet_tx(unsigned long data)
1872{
1873 struct ath5k_softc *sc = (void *)data;
1874
1875 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1876}
1877
1878
fa1c114f
JS		 1879/*****************\
1880* Beacon handling *
1881\*****************/
1882
1883/*
1884 * Setup the beacon frame for transmit.
1885 */
1886static int
e039fa4a 1887ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1888{
1889 struct sk_buff *skb = bf->skb;
a888d52d 1890 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1891 struct ath5k_hw *ah = sc->ah;
1892 struct ath5k_desc *ds;
1893 int ret, antenna = 0;
1894 u32 flags;
1895
1896 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1897 PCI_DMA_TODEVICE);
1898 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1899 "skbaddr %llx\n", skb, skb->data, skb->len,
1900 (unsigned long long)bf->skbaddr);
8d8bb39b 1901 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1902 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1903 return -EIO;
1904 }
1905
1906 ds = bf->desc;
1907
1908 flags = AR5K_TXDESC_NOACK;
1909 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1910 ds->ds_link = bf->daddr; /* self-linked */
1911 flags |= AR5K_TXDESC_VEOL;
1912 /*
1913 * Let hardware handle antenna switching if txantenna is not set
1914 */
1915 } else {
1916 ds->ds_link = 0;
1917 /*
1918 * Switch antenna every 4 beacons if txantenna is not set
1919 * XXX assumes two antennas
1920 */
1921 if (antenna == 0)
1922 antenna = sc->bsent & 4 ? 2 : 1;
1923 }
1924
1925 ds->ds_data = bf->skbaddr;
281c56dd 1926 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1927 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1928 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1929 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1930 1, AR5K_TXKEYIX_INVALID,
400ec45a 1931 antenna, flags, 0, 0);
fa1c114f
JS		 1932 if (ret)
1933 goto err_unmap;
1934
1935 return 0;
1936err_unmap:
1937 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1938 return ret;
1939}
1940
1941/*
1942 * Transmit a beacon frame at SWBA. Dynamic updates to the
1943 * frame contents are done as needed and the slot time is
1944 * also adjusted based on current state.
1945 *
1946 * this is usually called from interrupt context (ath5k_intr())
1947 * but also from ath5k_beacon_config() in IBSS mode which in turn
1948 * can be called from a tasklet and user context
1949 */
1950static void
1951ath5k_beacon_send(struct ath5k_softc *sc)
1952{
1953 struct ath5k_buf *bf = sc->bbuf;
1954 struct ath5k_hw *ah = sc->ah;
1955
be9b7259 1956 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1957
1958 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1959 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1960 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1961 return;
1962 }
1963 /*
1964 * Check if the previous beacon has gone out. If
1965 * not don't don't try to post another, skip this
1966 * period and wait for the next. Missed beacons
1967 * indicate a problem and should not occur. If we
1968 * miss too many consecutive beacons reset the device.
1969 */
1970 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1971 sc->bmisscount++;
be9b7259 1972 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1973 "missed %u consecutive beacons\n", sc->bmisscount);
1974 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1975 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1976 "stuck beacon time (%u missed)\n",
1977 sc->bmisscount);
1978 tasklet_schedule(&sc->restq);
1979 }
1980 return;
1981 }
1982 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1983 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1984 "resume beacon xmit after %u misses\n",
1985 sc->bmisscount);
1986 sc->bmisscount = 0;
1987 }
1988
1989 /*
1990 * Stop any current dma and put the new frame on the queue.
1991 * This should never fail since we check above that no frames
1992 * are still pending on the queue.
1993 */
1994 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1995 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1996 /* NB: hw still stops DMA, so proceed */
1997 }
fa1c114f
JS		 1998
1999 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2000 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2001 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2002 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2003
2004 sc->bsent++;
2005}
2006
2007
9804b98d
BR		 2008/**
2009 * ath5k_beacon_update_timers - update beacon timers
2010 *
2011 * @sc: struct ath5k_softc pointer we are operating on
2012 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2013 * beacon timer update based on the current HW TSF.
2014 *
2015 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2016 * of a received beacon or the current local hardware TSF and write it to the
2017 * beacon timer registers.
2018 *
2019 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2020 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2021 * when we otherwise know we have to update the timers, but we keep it in this
2022 * function to have it all together in one place.
2023 */
fa1c114f 2024static void
9804b98d 2025ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2026{
2027 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2028 u32 nexttbtt, intval, hw_tu, bc_tu;
2029 u64 hw_tsf;
fa1c114f
JS		 2030
2031 intval = sc->bintval & AR5K_BEACON_PERIOD;
2032 if (WARN_ON(!intval))
2033 return;
2034
9804b98d
BR		 2035 /* beacon TSF converted to TU */
2036 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2037
9804b98d
BR		 2038 /* current TSF converted to TU */
2039 hw_tsf = ath5k_hw_get_tsf64(ah);
2040 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2041
9804b98d
BR		 2042#define FUDGE 3
2043 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2044 if (bc_tsf == -1) {
2045 /*
2046 * no beacons received, called internally.
2047 * just need to refresh timers based on HW TSF.
2048 */
2049 nexttbtt = roundup(hw_tu + FUDGE, intval);
2050 } else if (bc_tsf == 0) {
2051 /*
2052 * no beacon received, probably called by ath5k_reset_tsf().
2053 * reset TSF to start with 0.
2054 */
2055 nexttbtt = intval;
2056 intval |= AR5K_BEACON_RESET_TSF;
2057 } else if (bc_tsf > hw_tsf) {
2058 /*
2059 * beacon received, SW merge happend but HW TSF not yet updated.
2060 * not possible to reconfigure timers yet, but next time we
2061 * receive a beacon with the same BSSID, the hardware will
2062 * automatically update the TSF and then we need to reconfigure
2063 * the timers.
2064 */
2065 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2066 "need to wait for HW TSF sync\n");
2067 return;
2068 } else {
2069 /*
2070 * most important case for beacon synchronization between STA.
2071 *
2072 * beacon received and HW TSF has been already updated by HW.
2073 * update next TBTT based on the TSF of the beacon, but make
2074 * sure it is ahead of our local TSF timer.
2075 */
2076 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2077 }
2078#undef FUDGE
fa1c114f 2079
036cd1ec
BR		 2080 sc->nexttbtt = nexttbtt;
2081
fa1c114f 2082 intval |= AR5K_BEACON_ENA;
fa1c114f 2083 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2084
2085 /*
2086 * debugging output last in order to preserve the time critical aspect
2087 * of this function
2088 */
2089 if (bc_tsf == -1)
2090 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2091 "reconfigured timers based on HW TSF\n");
2092 else if (bc_tsf == 0)
2093 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2094 "reset HW TSF and timers\n");
2095 else
2096 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2097 "updated timers based on beacon TSF\n");
2098
2099 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2100 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2101 (unsigned long long) bc_tsf,
2102 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2103 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2104 intval & AR5K_BEACON_PERIOD,
2105 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2106 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2107}
2108
2109
036cd1ec
BR		 2110/**
2111 * ath5k_beacon_config - Configure the beacon queues and interrupts
2112 *
2113 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2114 *
2115 * When operating in station mode we want to receive a BMISS interrupt when we
2116 * stop seeing beacons from the AP we've associated with so we can look for
2117 * another AP to associate with.
2118 *
036cd1ec 2119 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2120 * interrupts to detect TSF updates only.
036cd1ec
BR		 2121 *
2122 * AP mode is missing.
fa1c114f
JS		 2123 */
2124static void
2125ath5k_beacon_config(struct ath5k_softc *sc)
2126{
2127 struct ath5k_hw *ah = sc->ah;
2128
2129 ath5k_hw_set_intr(ah, 0);
2130 sc->bmisscount = 0;
dc1968e7 2131 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f
JS		 2132
2133 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2134 sc->imask |= AR5K_INT_BMISS;
2135 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2136 /*
036cd1ec
BR		 2137 * In IBSS mode we use a self-linked tx descriptor and let the
2138 * hardware send the beacons automatically. We have to load it
fa1c114f 2139 * only once here.
036cd1ec 2140 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2141 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2142 */
2143 ath5k_beaconq_config(sc);
fa1c114f 2144
036cd1ec
BR		 2145 sc->imask |= AR5K_INT_SWBA;
2146
2147 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2148 ath5k_beacon_send(sc);
2149 }
2150 /* TODO else AP */
2151
2152 ath5k_hw_set_intr(ah, sc->imask);
2153}
2154
2155
2156/********************\
2157* Interrupt handling *
2158\********************/
2159
2160static int
2161ath5k_init(struct ath5k_softc *sc)
2162{
2163 int ret;
2164
2165 mutex_lock(&sc->lock);
2166
2167 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2168
2169 /*
2170 * Stop anything previously setup. This is safe
2171 * no matter this is the first time through or not.
2172 */
2173 ath5k_stop_locked(sc);
2174
2175 /*
2176 * The basic interface to setting the hardware in a good
2177 * state is ``reset''. On return the hardware is known to
2178 * be powered up and with interrupts disabled. This must
2179 * be followed by initialization of the appropriate bits
2180 * and then setup of the interrupt mask.
2181 */
d8ee398d
LR		 2182 sc->curchan = sc->hw->conf.channel;
2183 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2184 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2185 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2186 AR5K_INT_MIB;
d7dc1003
JS		 2187 ret = ath5k_reset(sc, false, false);
2188 if (ret)
2189 goto done;
fa1c114f 2190
fa1c114f
JS		 2191 /* Set ack to be sent at low bit-rates */
2192 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2193
2194 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2195 msecs_to_jiffies(ath5k_calinterval * 1000)));
2196
2197 ret = 0;
2198done:
274c7c36 2199 mmiowb();
fa1c114f
JS		 2200 mutex_unlock(&sc->lock);
2201 return ret;
2202}
2203
2204static int
2205ath5k_stop_locked(struct ath5k_softc *sc)
2206{
2207 struct ath5k_hw *ah = sc->ah;
2208
2209 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2210 test_bit(ATH_STAT_INVALID, sc->status));
2211
2212 /*
2213 * Shutdown the hardware and driver:
2214 * stop output from above
2215 * disable interrupts
2216 * turn off timers
2217 * turn off the radio
2218 * clear transmit machinery
2219 * clear receive machinery
2220 * drain and release tx queues
2221 * reclaim beacon resources
2222 * power down hardware
2223 *
2224 * Note that some of this work is not possible if the
2225 * hardware is gone (invalid).
2226 */
2227 ieee80211_stop_queues(sc->hw);
2228
2229 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2230 ath5k_led_off(sc);
fa1c114f 2231 ath5k_hw_set_intr(ah, 0);
274c7c36 2232 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2233 }
2234 ath5k_txq_cleanup(sc);
2235 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2236 ath5k_rx_stop(sc);
2237 ath5k_hw_phy_disable(ah);
2238 } else
2239 sc->rxlink = NULL;
2240
2241 return 0;
2242}
2243
2244/*
2245 * Stop the device, grabbing the top-level lock to protect
2246 * against concurrent entry through ath5k_init (which can happen
2247 * if another thread does a system call and the thread doing the
2248 * stop is preempted).
2249 */
2250static int
2251ath5k_stop_hw(struct ath5k_softc *sc)
2252{
2253 int ret;
2254
2255 mutex_lock(&sc->lock);
2256 ret = ath5k_stop_locked(sc);
2257 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2258 /*
2259 * Set the chip in full sleep mode. Note that we are
2260 * careful to do this only when bringing the interface
2261 * completely to a stop. When the chip is in this state
2262 * it must be carefully woken up or references to
2263 * registers in the PCI clock domain may freeze the bus
2264 * (and system). This varies by chip and is mostly an
2265 * issue with newer parts that go to sleep more quickly.
2266 */
2267 if (sc->ah->ah_mac_srev >= 0x78) {
2268 /*
2269 * XXX
2270 * don't put newer MAC revisions > 7.8 to sleep because
2271 * of the above mentioned problems
2272 */
2273 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2274 "not putting device to sleep\n");
2275 } else {
2276 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2277 "putting device to full sleep\n");
2278 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2279 }
2280 }
2281 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2282 mmiowb();
fa1c114f
JS		 2283 mutex_unlock(&sc->lock);
2284
2285 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2286 tasklet_kill(&sc->rxtq);
2287 tasklet_kill(&sc->txtq);
2288 tasklet_kill(&sc->restq);
fa1c114f
JS		 2289
2290 return ret;
2291}
2292
2293static irqreturn_t
2294ath5k_intr(int irq, void *dev_id)
2295{
2296 struct ath5k_softc *sc = dev_id;
2297 struct ath5k_hw *ah = sc->ah;
2298 enum ath5k_int status;
2299 unsigned int counter = 1000;
2300
2301 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2302 !ath5k_hw_is_intr_pending(ah)))
2303 return IRQ_NONE;
2304
2305 do {
2306 /*
2307 * Figure out the reason(s) for the interrupt. Note
2308 * that get_isr returns a pseudo-ISR that may include
2309 * bits we haven't explicitly enabled so we mask the
2310 * value to insure we only process bits we requested.
2311 */
2312 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2313 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2314 status, sc->imask);
2315 status &= sc->imask; /* discard unasked for bits */
2316 if (unlikely(status & AR5K_INT_FATAL)) {
2317 /*
2318 * Fatal errors are unrecoverable.
2319 * Typically these are caused by DMA errors.
2320 */
2321 tasklet_schedule(&sc->restq);
2322 } else if (unlikely(status & AR5K_INT_RXORN)) {
2323 tasklet_schedule(&sc->restq);
2324 } else {
2325 if (status & AR5K_INT_SWBA) {
2326 /*
2327 * Software beacon alert--time to send a beacon.
2328 * Handle beacon transmission directly; deferring
2329 * this is too slow to meet timing constraints
2330 * under load.
036cd1ec
BR		 2331 *
2332 * In IBSS mode we use this interrupt just to
2333 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2334 * transmission time) in order to detect wether
2335 * automatic TSF updates happened.
fa1c114f 2336 */
036cd1ec
BR		 2337 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2338 /* XXX: only if VEOL suppported */
2339 u64 tsf = ath5k_hw_get_tsf64(ah);
2340 sc->nexttbtt += sc->bintval;
2341 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2342 "SWBA nexttbtt: %x hw_tu: %x "
2343 "TSF: %llx\n",
2344 sc->nexttbtt,
2345 TSF_TO_TU(tsf),
2346 (unsigned long long) tsf);
036cd1ec
BR		 2347 } else {
2348 ath5k_beacon_send(sc);
2349 }
fa1c114f
JS		 2350 }
2351 if (status & AR5K_INT_RXEOL) {
2352 /*
2353 * NB: the hardware should re-read the link when
2354 * RXE bit is written, but it doesn't work at
2355 * least on older hardware revs.
2356 */
2357 sc->rxlink = NULL;
2358 }
2359 if (status & AR5K_INT_TXURN) {
2360 /* bump tx trigger level */
2361 ath5k_hw_update_tx_triglevel(ah, true);
2362 }
2363 if (status & AR5K_INT_RX)
2364 tasklet_schedule(&sc->rxtq);
2365 if (status & AR5K_INT_TX)
2366 tasklet_schedule(&sc->txtq);
2367 if (status & AR5K_INT_BMISS) {
2368 }
2369 if (status & AR5K_INT_MIB) {
194828a2
NK		 2370 /*
2371 * These stats are also used for ANI i think
2372 * so how about updating them more often ?
2373 */
2374 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2375 }
2376 }
2377 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2378
2379 if (unlikely(!counter))
2380 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2381
2382 return IRQ_HANDLED;
2383}
2384
2385static void
2386ath5k_tasklet_reset(unsigned long data)
2387{
2388 struct ath5k_softc *sc = (void *)data;
2389
d7dc1003 2390 ath5k_reset_wake(sc);
fa1c114f
JS		 2391}
2392
2393/*
2394 * Periodically recalibrate the PHY to account
2395 * for temperature/environment changes.
2396 */
2397static void
2398ath5k_calibrate(unsigned long data)
2399{
2400 struct ath5k_softc *sc = (void *)data;
2401 struct ath5k_hw *ah = sc->ah;
2402
2403 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2404 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2405 sc->curchan->hw_value);
fa1c114f
JS		 2406
2407 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2408 /*
2409 * Rfgain is out of bounds, reset the chip
2410 * to load new gain values.
2411 */
2412 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2413 ath5k_reset_wake(sc);
fa1c114f
JS		 2414 }
2415 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2416 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2417 ieee80211_frequency_to_channel(
2418 sc->curchan->center_freq));
fa1c114f
JS		 2419
2420 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2421 msecs_to_jiffies(ath5k_calinterval * 1000)));
2422}
2423
2424
2425
2426/***************\
2427* LED functions *
2428\***************/
2429
2430static void
3a078876 2431ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2432{
3a078876
BC		 2433 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2434 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2435 ath5k_led_off(sc);
fa1c114f
JS		 2436 }
2437}
2438
fa1c114f 2439static void
3a078876 2440ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2441{
3a078876
BC		 2442 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2443 return;
fa1c114f 2444 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2445}
2446
2447static void
3a078876 2448ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2449{
3a078876 2450 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2451 return;
3a078876
BC		 2452 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2453}
2454
2455static void
2456ath5k_led_brightness_set(struct led_classdev *led_dev,
2457 enum led_brightness brightness)
2458{
2459 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2460 led_dev);
2461
2462 if (brightness == LED_OFF)
2463 ath5k_led_off(led->sc);
2464 else
2465 ath5k_led_on(led->sc);
2466}
2467
2468static int
2469ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2470 const char *name, char *trigger)
2471{
2472 int err;
2473
2474 led->sc = sc;
2475 strncpy(led->name, name, sizeof(led->name));
2476 led->led_dev.name = led->name;
2477 led->led_dev.default_trigger = trigger;
2478 led->led_dev.brightness_set = ath5k_led_brightness_set;
2479
2480 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2481 if (err)
2482 {
2483 ATH5K_WARN(sc, "could not register LED %s\n", name);
2484 led->sc = NULL;
fa1c114f 2485 }
3a078876 2486 return err;
fa1c114f
JS		 2487}
2488
3a078876
BC		 2489static void
2490ath5k_unregister_led(struct ath5k_led *led)
2491{
2492 if (!led->sc)
2493 return;
2494 led_classdev_unregister(&led->led_dev);
2495 ath5k_led_off(led->sc);
2496 led->sc = NULL;
2497}
2498
2499static void
2500ath5k_unregister_leds(struct ath5k_softc *sc)
2501{
2502 ath5k_unregister_led(&sc->rx_led);
2503 ath5k_unregister_led(&sc->tx_led);
2504}
2505
2506
2507static int
2508ath5k_init_leds(struct ath5k_softc *sc)
2509{
2510 int ret = 0;
2511 struct ieee80211_hw *hw = sc->hw;
2512 struct pci_dev *pdev = sc->pdev;
2513 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2514
3a078876
BC		 2515 /*
2516 * Auto-enable soft led processing for IBM cards and for
2517 * 5211 minipci cards.
2518 */
2519 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2520 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2521 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2522 sc->led_pin = 0;
734b5aa9 2523 sc->led_on = 0; /* active low */
3a078876
BC		 2524 }
2525 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2526 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2527 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2528 sc->led_pin = 1;
734b5aa9 2529 sc->led_on = 1; /* active high */
3a078876
BC		 2530 }
2531 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2532 goto out;
2533
2534 ath5k_led_enable(sc);
2535
2536 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2537 ret = ath5k_register_led(sc, &sc->rx_led, name,
2538 ieee80211_get_rx_led_name(hw));
2539 if (ret)
2540 goto out;
2541
2542 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2543 ret = ath5k_register_led(sc, &sc->tx_led, name,
2544 ieee80211_get_tx_led_name(hw));
2545out:
2546 return ret;
2547}
fa1c114f
JS		 2548
2549
2550/********************\
2551* Mac80211 functions *
2552\********************/
2553
2554static int
e039fa4a 2555ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2556{
2557 struct ath5k_softc *sc = hw->priv;
2558 struct ath5k_buf *bf;
2559 unsigned long flags;
2560 int hdrlen;
2561 int pad;
2562
2563 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2564
2565 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2566 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2567
2568 /*
2569 * the hardware expects the header padded to 4 byte boundaries
2570 * if this is not the case we add the padding after the header
2571 */
2572 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2573 if (hdrlen & 3) {
2574 pad = hdrlen % 4;
2575 if (skb_headroom(skb) < pad) {
2576 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2577 " headroom to pad %d\n", hdrlen, pad);
2578 return -1;
2579 }
2580 skb_push(skb, pad);
2581 memmove(skb->data, skb->data+pad, hdrlen);
2582 }
2583
fa1c114f
JS		 2584 spin_lock_irqsave(&sc->txbuflock, flags);
2585 if (list_empty(&sc->txbuf)) {
2586 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2587 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2588 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2589 return -1;
2590 }
2591 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2592 list_del(&bf->list);
2593 sc->txbuf_len--;
2594 if (list_empty(&sc->txbuf))
2595 ieee80211_stop_queues(hw);
2596 spin_unlock_irqrestore(&sc->txbuflock, flags);
2597
2598 bf->skb = skb;
2599
e039fa4a 2600 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2601 bf->skb = NULL;
2602 spin_lock_irqsave(&sc->txbuflock, flags);
2603 list_add_tail(&bf->list, &sc->txbuf);
2604 sc->txbuf_len++;
2605 spin_unlock_irqrestore(&sc->txbuflock, flags);
2606 dev_kfree_skb_any(skb);
2607 return 0;
2608 }
2609
2610 return 0;
2611}
2612
2613static int
d7dc1003 2614ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2615{
fa1c114f
JS		 2616 struct ath5k_hw *ah = sc->ah;
2617 int ret;
2618
2619 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2620
d7dc1003
JS		 2621 if (stop) {
2622 ath5k_hw_set_intr(ah, 0);
2623 ath5k_txq_cleanup(sc);
2624 ath5k_rx_stop(sc);
2625 }
fa1c114f 2626 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2627 if (ret) {
fa1c114f
JS		 2628 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2629 goto err;
2630 }
d7dc1003
JS		 2631
2632 /*
2633 * This is needed only to setup initial state
2634 * but it's best done after a reset.
2635 */
fa1c114f
JS		 2636 ath5k_hw_set_txpower_limit(sc->ah, 0);
2637
2638 ret = ath5k_rx_start(sc);
d7dc1003 2639 if (ret) {
fa1c114f
JS		 2640 ATH5K_ERR(sc, "can't start recv logic\n");
2641 goto err;
2642 }
d7dc1003 2643
fa1c114f 2644 /*
d7dc1003
JS		 2645 * Change channels and update the h/w rate map if we're switching;
2646 * e.g. 11a to 11b/g.
2647 *
2648 * We may be doing a reset in response to an ioctl that changes the
2649 * channel so update any state that might change as a result.
fa1c114f
JS		 2650 *
2651 * XXX needed?
2652 */
2653/* ath5k_chan_change(sc, c); */
fa1c114f 2654
d7dc1003
JS		 2655 ath5k_beacon_config(sc);
2656 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2657
2658 return 0;
2659err:
2660 return ret;
2661}
2662
d7dc1003
JS		 2663static int
2664ath5k_reset_wake(struct ath5k_softc *sc)
2665{
2666 int ret;
2667
2668 ret = ath5k_reset(sc, true, true);
2669 if (!ret)
2670 ieee80211_wake_queues(sc->hw);
2671
2672 return ret;
2673}
2674
fa1c114f
JS		 2675static int ath5k_start(struct ieee80211_hw *hw)
2676{
2677 return ath5k_init(hw->priv);
2678}
2679
2680static void ath5k_stop(struct ieee80211_hw *hw)
2681{
2682 ath5k_stop_hw(hw->priv);
2683}
2684
2685static int ath5k_add_interface(struct ieee80211_hw *hw,
2686 struct ieee80211_if_init_conf *conf)
2687{
2688 struct ath5k_softc *sc = hw->priv;
2689 int ret;
2690
2691 mutex_lock(&sc->lock);
32bfd35d 2692 if (sc->vif) {
fa1c114f
JS		 2693 ret = 0;
2694 goto end;
2695 }
2696
32bfd35d 2697 sc->vif = conf->vif;
fa1c114f
JS		 2698
2699 switch (conf->type) {
2700 case IEEE80211_IF_TYPE_STA:
2701 case IEEE80211_IF_TYPE_IBSS:
2702 case IEEE80211_IF_TYPE_MNTR:
2703 sc->opmode = conf->type;
2704 break;
2705 default:
2706 ret = -EOPNOTSUPP;
2707 goto end;
2708 }
2709 ret = 0;
2710end:
2711 mutex_unlock(&sc->lock);
2712 return ret;
2713}
2714
2715static void
2716ath5k_remove_interface(struct ieee80211_hw *hw,
2717 struct ieee80211_if_init_conf *conf)
2718{
2719 struct ath5k_softc *sc = hw->priv;
2720
2721 mutex_lock(&sc->lock);
32bfd35d 2722 if (sc->vif != conf->vif)
fa1c114f
JS		 2723 goto end;
2724
32bfd35d 2725 sc->vif = NULL;
fa1c114f
JS		 2726end:
2727 mutex_unlock(&sc->lock);
2728}
2729
d8ee398d
LR		 2730/*
2731 * TODO: Phy disable/diversity etc
2732 */
fa1c114f
JS		 2733static int
2734ath5k_config(struct ieee80211_hw *hw,
2735 struct ieee80211_conf *conf)
2736{
2737 struct ath5k_softc *sc = hw->priv;
2738
e535c1ac 2739 sc->bintval = conf->beacon_int;
d8ee398d 2740 sc->power_level = conf->power_level;
fa1c114f 2741
d8ee398d 2742 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2743}
2744
2745static int
32bfd35d 2746ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2747 struct ieee80211_if_conf *conf)
2748{
2749 struct ath5k_softc *sc = hw->priv;
2750 struct ath5k_hw *ah = sc->ah;
2751 int ret;
2752
2753 /* Set to a reasonable value. Note that this will
2754 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2755 sc->bintval = 1000;
fa1c114f 2756 mutex_lock(&sc->lock);
32bfd35d 2757 if (sc->vif != vif) {
fa1c114f
JS		 2758 ret = -EIO;
2759 goto unlock;
2760 }
2761 if (conf->bssid) {
2762 /* Cache for later use during resets */
2763 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2764 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2765 * a clean way of letting us retrieve this yet. */
2766 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2767 mmiowb();
fa1c114f 2768 }
9d139c81
JB		 2769
2770 if (conf->changed & IEEE80211_IFCC_BEACON &&
2771 vif->type == IEEE80211_IF_TYPE_IBSS) {
2772 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2773 if (!beacon) {
2774 ret = -ENOMEM;
2775 goto unlock;
2776 }
2777 /* call old handler for now */
2778 ath5k_beacon_update(hw, beacon);
2779 }
2780
fa1c114f
JS		 2781 mutex_unlock(&sc->lock);
2782
d7dc1003 2783 return ath5k_reset_wake(sc);
fa1c114f
JS		 2784unlock:
2785 mutex_unlock(&sc->lock);
2786 return ret;
2787}
2788
2789#define SUPPORTED_FIF_FLAGS \
2790 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2791 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2792 FIF_BCN_PRBRESP_PROMISC
2793/*
2794 * o always accept unicast, broadcast, and multicast traffic
2795 * o multicast traffic for all BSSIDs will be enabled if mac80211
2796 * says it should be
2797 * o maintain current state of phy ofdm or phy cck error reception.
2798 * If the hardware detects any of these type of errors then
2799 * ath5k_hw_get_rx_filter() will pass to us the respective
2800 * hardware filters to be able to receive these type of frames.
2801 * o probe request frames are accepted only when operating in
2802 * hostap, adhoc, or monitor modes
2803 * o enable promiscuous mode according to the interface state
2804 * o accept beacons:
2805 * - when operating in adhoc mode so the 802.11 layer creates
2806 * node table entries for peers,
2807 * - when operating in station mode for collecting rssi data when
2808 * the station is otherwise quiet, or
2809 * - when scanning
2810 */
2811static void ath5k_configure_filter(struct ieee80211_hw *hw,
2812 unsigned int changed_flags,
2813 unsigned int *new_flags,
2814 int mc_count, struct dev_mc_list *mclist)
2815{
2816 struct ath5k_softc *sc = hw->priv;
2817 struct ath5k_hw *ah = sc->ah;
2818 u32 mfilt[2], val, rfilt;
2819 u8 pos;
2820 int i;
2821
2822 mfilt[0] = 0;
2823 mfilt[1] = 0;
2824
2825 /* Only deal with supported flags */
2826 changed_flags &= SUPPORTED_FIF_FLAGS;
2827 *new_flags &= SUPPORTED_FIF_FLAGS;
2828
2829 /* If HW detects any phy or radar errors, leave those filters on.
2830 * Also, always enable Unicast, Broadcasts and Multicast
2831 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2832 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2833 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2834 AR5K_RX_FILTER_MCAST);
2835
2836 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2837 if (*new_flags & FIF_PROMISC_IN_BSS) {
2838 rfilt |= AR5K_RX_FILTER_PROM;
2839 __set_bit(ATH_STAT_PROMISC, sc->status);
2840 }
2841 else
2842 __clear_bit(ATH_STAT_PROMISC, sc->status);
2843 }
2844
2845 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2846 if (*new_flags & FIF_ALLMULTI) {
2847 mfilt[0] = ~0;
2848 mfilt[1] = ~0;
2849 } else {
2850 for (i = 0; i < mc_count; i++) {
2851 if (!mclist)
2852 break;
2853 /* calculate XOR of eight 6-bit values */
533dd1b0 2854 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2855 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2856 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2857 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2858 pos &= 0x3f;
2859 mfilt[pos / 32] |= (1 << (pos % 32));
2860 /* XXX: we might be able to just do this instead,
2861 * but not sure, needs testing, if we do use this we'd
2862 * neet to inform below to not reset the mcast */
2863 /* ath5k_hw_set_mcast_filterindex(ah,
2864 * mclist->dmi_addr[5]); */
2865 mclist = mclist->next;
2866 }
2867 }
2868
2869 /* This is the best we can do */
2870 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2871 rfilt |= AR5K_RX_FILTER_PHYERR;
2872
2873 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2874 * and probes for any BSSID, this needs testing */
2875 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2876 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2877
2878 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2879 * set we should only pass on control frames for this
2880 * station. This needs testing. I believe right now this
2881 * enables *all* control frames, which is OK.. but
2882 * but we should see if we can improve on granularity */
2883 if (*new_flags & FIF_CONTROL)
2884 rfilt |= AR5K_RX_FILTER_CONTROL;
2885
2886 /* Additional settings per mode -- this is per ath5k */
2887
2888 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2889
2890 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2891 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2892 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2893 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2894 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2895 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
8e5f3d0a 2896 sc->opmode != IEEE80211_IF_TYPE_MESH_POINT &&
fa1c114f
JS		 2897 test_bit(ATH_STAT_PROMISC, sc->status))
2898 rfilt |= AR5K_RX_FILTER_PROM;
2899 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2900 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2901 rfilt |= AR5K_RX_FILTER_BEACON;
2902 }
2903
2904 /* Set filters */
2905 ath5k_hw_set_rx_filter(ah,rfilt);
2906
2907 /* Set multicast bits */
2908 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2909 /* Set the cached hw filter flags, this will alter actually
2910 * be set in HW */
2911 sc->filter_flags = rfilt;
2912}
2913
2914static int
2915ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2916 const u8 *local_addr, const u8 *addr,
2917 struct ieee80211_key_conf *key)
2918{
2919 struct ath5k_softc *sc = hw->priv;
2920 int ret = 0;
2921
2922 switch(key->alg) {
2923 case ALG_WEP:
6844e63a
LR		 2924 /* XXX: fix hardware encryption, its not working. For now
2925 * allow software encryption */
2926 /* break; */
fa1c114f
JS		 2927 case ALG_TKIP:
2928 case ALG_CCMP:
2929 return -EOPNOTSUPP;
2930 default:
2931 WARN_ON(1);
2932 return -EINVAL;
2933 }
2934
2935 mutex_lock(&sc->lock);
2936
2937 switch (cmd) {
2938 case SET_KEY:
2939 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2940 if (ret) {
2941 ATH5K_ERR(sc, "can't set the key\n");
2942 goto unlock;
2943 }
2944 __set_bit(key->keyidx, sc->keymap);
2945 key->hw_key_idx = key->keyidx;
2946 break;
2947 case DISABLE_KEY:
2948 ath5k_hw_reset_key(sc->ah, key->keyidx);
2949 __clear_bit(key->keyidx, sc->keymap);
2950 break;
2951 default:
2952 ret = -EINVAL;
2953 goto unlock;
2954 }
2955
2956unlock:
274c7c36 2957 mmiowb();
fa1c114f
JS		 2958 mutex_unlock(&sc->lock);
2959 return ret;
2960}
2961
2962static int
2963ath5k_get_stats(struct ieee80211_hw *hw,
2964 struct ieee80211_low_level_stats *stats)
2965{
2966 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2967 struct ath5k_hw *ah = sc->ah;
2968
2969 /* Force update */
2970 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2971
2972 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2973
2974 return 0;
2975}
2976
2977static int
2978ath5k_get_tx_stats(struct ieee80211_hw *hw,
2979 struct ieee80211_tx_queue_stats *stats)
2980{
2981 struct ath5k_softc *sc = hw->priv;
2982
2983 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2984
2985 return 0;
2986}
2987
2988static u64
2989ath5k_get_tsf(struct ieee80211_hw *hw)
2990{
2991 struct ath5k_softc *sc = hw->priv;
2992
2993 return ath5k_hw_get_tsf64(sc->ah);
2994}
2995
2996static void
2997ath5k_reset_tsf(struct ieee80211_hw *hw)
2998{
2999 struct ath5k_softc *sc = hw->priv;
3000
9804b98d
BR		 3001 /*
3002 * in IBSS mode we need to update the beacon timers too.
3003 * this will also reset the TSF if we call it with 0
3004 */
3005 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3006 ath5k_beacon_update_timers(sc, 0);
3007 else
3008 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3009}
3010
3011static int
e039fa4a 3012ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3013{
3014 struct ath5k_softc *sc = hw->priv;
3015 int ret;
3016
3017 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3018
fa1c114f
JS		 3019 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3020 ret = -EIO;
3021 goto end;
3022 }
3023
3024 ath5k_txbuf_free(sc, sc->bbuf);
3025 sc->bbuf->skb = skb;
e039fa4a 3026 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3027 if (ret)
3028 sc->bbuf->skb = NULL;
274c7c36 3029 else {
fa1c114f 3030 ath5k_beacon_config(sc);
274c7c36
JS		 3031 mmiowb();
3032 }
fa1c114f
JS		 3033
3034end:
fa1c114f
JS		 3035 return ret;
3036}
3037
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