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ath5k: add notes about rx timestamp
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
61/* unaligned little endian access */
62#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68};
69
70static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
400ec45a 83MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 84
85
86/* Known PCI ids */
87static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
112static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 121 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
122 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 123 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
124 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
125 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
126 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
127 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
128 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
129 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
135 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
136 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 137 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 138 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
139 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
140 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142};
143
144/*
145 * Prototypes - PCI stack related functions
146 */
147static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
148 const struct pci_device_id *id);
149static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
150#ifdef CONFIG_PM
151static int ath5k_pci_suspend(struct pci_dev *pdev,
152 pm_message_t state);
153static int ath5k_pci_resume(struct pci_dev *pdev);
154#else
155#define ath5k_pci_suspend NULL
156#define ath5k_pci_resume NULL
157#endif /* CONFIG_PM */
158
04a9e451 159static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 160 .name = "ath5k_pci",
161 .id_table = ath5k_pci_id_table,
162 .probe = ath5k_pci_probe,
163 .remove = __devexit_p(ath5k_pci_remove),
164 .suspend = ath5k_pci_suspend,
165 .resume = ath5k_pci_resume,
166};
167
168
169
170/*
171 * Prototypes - MAC 802.11 stack related functions
172 */
173static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
174 struct ieee80211_tx_control *ctl);
175static int ath5k_reset(struct ieee80211_hw *hw);
176static int ath5k_start(struct ieee80211_hw *hw);
177static void ath5k_stop(struct ieee80211_hw *hw);
178static int ath5k_add_interface(struct ieee80211_hw *hw,
179 struct ieee80211_if_init_conf *conf);
180static void ath5k_remove_interface(struct ieee80211_hw *hw,
181 struct ieee80211_if_init_conf *conf);
182static int ath5k_config(struct ieee80211_hw *hw,
183 struct ieee80211_conf *conf);
32bfd35d
JB		 184static int ath5k_config_interface(struct ieee80211_hw *hw,
185 struct ieee80211_vif *vif,
fa1c114f
JS		 186 struct ieee80211_if_conf *conf);
187static void ath5k_configure_filter(struct ieee80211_hw *hw,
188 unsigned int changed_flags,
189 unsigned int *new_flags,
190 int mc_count, struct dev_mc_list *mclist);
191static int ath5k_set_key(struct ieee80211_hw *hw,
192 enum set_key_cmd cmd,
193 const u8 *local_addr, const u8 *addr,
194 struct ieee80211_key_conf *key);
195static int ath5k_get_stats(struct ieee80211_hw *hw,
196 struct ieee80211_low_level_stats *stats);
197static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
198 struct ieee80211_tx_queue_stats *stats);
199static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
200static void ath5k_reset_tsf(struct ieee80211_hw *hw);
201static int ath5k_beacon_update(struct ieee80211_hw *hw,
202 struct sk_buff *skb,
203 struct ieee80211_tx_control *ctl);
204
205static struct ieee80211_ops ath5k_hw_ops = {
206 .tx = ath5k_tx,
207 .start = ath5k_start,
208 .stop = ath5k_stop,
209 .add_interface = ath5k_add_interface,
210 .remove_interface = ath5k_remove_interface,
211 .config = ath5k_config,
212 .config_interface = ath5k_config_interface,
213 .configure_filter = ath5k_configure_filter,
214 .set_key = ath5k_set_key,
215 .get_stats = ath5k_get_stats,
216 .conf_tx = NULL,
217 .get_tx_stats = ath5k_get_tx_stats,
218 .get_tsf = ath5k_get_tsf,
219 .reset_tsf = ath5k_reset_tsf,
220 .beacon_update = ath5k_beacon_update,
221};
222
223/*
224 * Prototypes - Internal functions
225 */
226/* Attach detach */
227static int ath5k_attach(struct pci_dev *pdev,
228 struct ieee80211_hw *hw);
229static void ath5k_detach(struct pci_dev *pdev,
230 struct ieee80211_hw *hw);
231/* Channel/mode setup */
232static inline short ath5k_ieee2mhz(short chan);
233static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
234 const struct ath5k_rate_table *rt,
235 unsigned int max);
236static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
237 struct ieee80211_channel *channels,
238 unsigned int mode,
239 unsigned int max);
240static int ath5k_getchannels(struct ieee80211_hw *hw);
241static int ath5k_chan_set(struct ath5k_softc *sc,
242 struct ieee80211_channel *chan);
243static void ath5k_setcurmode(struct ath5k_softc *sc,
244 unsigned int mode);
245static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 246static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
247
fa1c114f
JS		 248/* Descriptor setup */
249static int ath5k_desc_alloc(struct ath5k_softc *sc,
250 struct pci_dev *pdev);
251static void ath5k_desc_free(struct ath5k_softc *sc,
252 struct pci_dev *pdev);
253/* Buffers setup */
254static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
255 struct ath5k_buf *bf);
256static int ath5k_txbuf_setup(struct ath5k_softc *sc,
257 struct ath5k_buf *bf,
258 struct ieee80211_tx_control *ctl);
259
260static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
261 struct ath5k_buf *bf)
262{
263 BUG_ON(!bf);
264 if (!bf->skb)
265 return;
266 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
267 PCI_DMA_TODEVICE);
268 dev_kfree_skb(bf->skb);
269 bf->skb = NULL;
270}
271
272/* Queues setup */
273static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
274 int qtype, int subtype);
275static int ath5k_beaconq_setup(struct ath5k_hw *ah);
276static int ath5k_beaconq_config(struct ath5k_softc *sc);
277static void ath5k_txq_drainq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279static void ath5k_txq_cleanup(struct ath5k_softc *sc);
280static void ath5k_txq_release(struct ath5k_softc *sc);
281/* Rx handling */
282static int ath5k_rx_start(struct ath5k_softc *sc);
283static void ath5k_rx_stop(struct ath5k_softc *sc);
284static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
285 struct ath5k_desc *ds,
b47f407b
BR		 286 struct sk_buff *skb,
287 struct ath5k_rx_status *rs);
fa1c114f
JS		 288static void ath5k_tasklet_rx(unsigned long data);
289/* Tx handling */
290static void ath5k_tx_processq(struct ath5k_softc *sc,
291 struct ath5k_txq *txq);
292static void ath5k_tasklet_tx(unsigned long data);
293/* Beacon handling */
294static int ath5k_beacon_setup(struct ath5k_softc *sc,
295 struct ath5k_buf *bf,
296 struct ieee80211_tx_control *ctl);
297static void ath5k_beacon_send(struct ath5k_softc *sc);
298static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 299static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 300
301static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
302{
303 u64 tsf = ath5k_hw_get_tsf64(ah);
304
305 if ((tsf & 0x7fff) < rstamp)
306 tsf -= 0x8000;
307
308 return (tsf & ~0x7fff) | rstamp;
309}
310
311/* Interrupt handling */
312static int ath5k_init(struct ath5k_softc *sc);
313static int ath5k_stop_locked(struct ath5k_softc *sc);
314static int ath5k_stop_hw(struct ath5k_softc *sc);
315static irqreturn_t ath5k_intr(int irq, void *dev_id);
316static void ath5k_tasklet_reset(unsigned long data);
317
318static void ath5k_calibrate(unsigned long data);
319/* LED functions */
320static void ath5k_led_off(unsigned long data);
321static void ath5k_led_blink(struct ath5k_softc *sc,
322 unsigned int on,
323 unsigned int off);
324static void ath5k_led_event(struct ath5k_softc *sc,
325 int event);
326
327
328/*
329 * Module init/exit functions
330 */
331static int __init
332init_ath5k_pci(void)
333{
334 int ret;
335
336 ath5k_debug_init();
337
04a9e451 338 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 339 if (ret) {
340 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
341 return ret;
342 }
343
344 return 0;
345}
346
347static void __exit
348exit_ath5k_pci(void)
349{
04a9e451 350 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 351
352 ath5k_debug_finish();
353}
354
355module_init(init_ath5k_pci);
356module_exit(exit_ath5k_pci);
357
358
359/********************\
360* PCI Initialization *
361\********************/
362
363static const char *
364ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
365{
366 const char *name = "xxxxx";
367 unsigned int i;
368
369 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
370 if (srev_names[i].sr_type != type)
371 continue;
372 if ((val & 0xff) < srev_names[i + 1].sr_val) {
373 name = srev_names[i].sr_name;
374 break;
375 }
376 }
377
378 return name;
379}
380
381static int __devinit
382ath5k_pci_probe(struct pci_dev *pdev,
383 const struct pci_device_id *id)
384{
385 void __iomem *mem;
386 struct ath5k_softc *sc;
387 struct ieee80211_hw *hw;
388 int ret;
389 u8 csz;
390
391 ret = pci_enable_device(pdev);
392 if (ret) {
393 dev_err(&pdev->dev, "can't enable device\n");
394 goto err;
395 }
396
397 /* XXX 32-bit addressing only */
398 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
399 if (ret) {
400 dev_err(&pdev->dev, "32-bit DMA not available\n");
401 goto err_dis;
402 }
403
404 /*
405 * Cache line size is used to size and align various
406 * structures used to communicate with the hardware.
407 */
408 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
409 if (csz == 0) {
410 /*
411 * Linux 2.4.18 (at least) writes the cache line size
412 * register as a 16-bit wide register which is wrong.
413 * We must have this setup properly for rx buffer
414 * DMA to work so force a reasonable value here if it
415 * comes up zero.
416 */
417 csz = L1_CACHE_BYTES / sizeof(u32);
418 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
419 }
420 /*
421 * The default setting of latency timer yields poor results,
422 * set it to the value used by other systems. It may be worth
423 * tweaking this setting more.
424 */
425 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
426
427 /* Enable bus mastering */
428 pci_set_master(pdev);
429
430 /*
431 * Disable the RETRY_TIMEOUT register (0x41) to keep
432 * PCI Tx retries from interfering with C3 CPU state.
433 */
434 pci_write_config_byte(pdev, 0x41, 0);
435
436 ret = pci_request_region(pdev, 0, "ath5k");
437 if (ret) {
438 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
439 goto err_dis;
440 }
441
442 mem = pci_iomap(pdev, 0, 0);
443 if (!mem) {
444 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
445 ret = -EIO;
446 goto err_reg;
447 }
448
449 /*
450 * Allocate hw (mac80211 main struct)
451 * and hw->priv (driver private data)
452 */
453 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
454 if (hw == NULL) {
455 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
456 ret = -ENOMEM;
457 goto err_map;
458 }
459
460 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
461
462 /* Initialize driver private data */
463 SET_IEEE80211_DEV(hw, &pdev->dev);
464 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
465 hw->extra_tx_headroom = 2;
466 hw->channel_change_time = 5000;
467 /* these names are misleading */
468 hw->max_rssi = -110; /* signal in dBm */
469 hw->max_noise = -110; /* noise in dBm */
470 hw->max_signal = 100; /* we will provide a percentage based on rssi */
471 sc = hw->priv;
472 sc->hw = hw;
473 sc->pdev = pdev;
474
475 ath5k_debug_init_device(sc);
476
477 /*
478 * Mark the device as detached to avoid processing
479 * interrupts until setup is complete.
480 */
481 __set_bit(ATH_STAT_INVALID, sc->status);
482
483 sc->iobase = mem; /* So we can unmap it on detach */
484 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
485 sc->opmode = IEEE80211_IF_TYPE_STA;
486 mutex_init(&sc->lock);
487 spin_lock_init(&sc->rxbuflock);
488 spin_lock_init(&sc->txbuflock);
489
490 /* Set private data */
491 pci_set_drvdata(pdev, hw);
492
493 /* Enable msi for devices that support it */
494 pci_enable_msi(pdev);
495
496 /* Setup interrupt handler */
497 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
498 if (ret) {
499 ATH5K_ERR(sc, "request_irq failed\n");
500 goto err_free;
501 }
502
503 /* Initialize device */
504 sc->ah = ath5k_hw_attach(sc, id->driver_data);
505 if (IS_ERR(sc->ah)) {
506 ret = PTR_ERR(sc->ah);
507 goto err_irq;
508 }
509
510 /* Finish private driver data initialization */
511 ret = ath5k_attach(pdev, hw);
512 if (ret)
513 goto err_ah;
514
515 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
516 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
517 sc->ah->ah_mac_srev,
518 sc->ah->ah_phy_revision);
519
400ec45a 520 if (!sc->ah->ah_single_chip) {
fa1c114f 521 /* Single chip radio (!RF5111) */
400ec45a
LR		 522 if (sc->ah->ah_radio_5ghz_revision &&
523 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 524 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 525 if (!test_bit(AR5K_MODE_11A,
526 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 527 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 528 ath5k_chip_name(AR5K_VERSION_RAD,
529 sc->ah->ah_radio_5ghz_revision),
530 sc->ah->ah_radio_5ghz_revision);
531 /* No 2GHz support (5110 and some
532 * 5Ghz only cards) -> report 5Ghz radio */
533 } else if (!test_bit(AR5K_MODE_11B,
534 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 535 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 536 ath5k_chip_name(AR5K_VERSION_RAD,
537 sc->ah->ah_radio_5ghz_revision),
538 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 539 /* Multiband radio */
540 } else {
541 ATH5K_INFO(sc, "RF%s multiband radio found"
542 " (0x%x)\n",
400ec45a
LR		 543 ath5k_chip_name(AR5K_VERSION_RAD,
544 sc->ah->ah_radio_5ghz_revision),
545 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 546 }
547 }
400ec45a
LR		 548 /* Multi chip radio (RF5111 - RF2111) ->
549 * report both 2GHz/5GHz radios */
550 else if (sc->ah->ah_radio_5ghz_revision &&
551 sc->ah->ah_radio_2ghz_revision){
fa1c114f 552 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 553 ath5k_chip_name(AR5K_VERSION_RAD,
554 sc->ah->ah_radio_5ghz_revision),
555 sc->ah->ah_radio_5ghz_revision);
fa1c114f 556 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 557 ath5k_chip_name(AR5K_VERSION_RAD,
558 sc->ah->ah_radio_2ghz_revision),
559 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 560 }
561 }
562
563
564 /* ready to process interrupts */
565 __clear_bit(ATH_STAT_INVALID, sc->status);
566
567 return 0;
568err_ah:
569 ath5k_hw_detach(sc->ah);
570err_irq:
571 free_irq(pdev->irq, sc);
572err_free:
573 pci_disable_msi(pdev);
574 ieee80211_free_hw(hw);
575err_map:
576 pci_iounmap(pdev, mem);
577err_reg:
578 pci_release_region(pdev, 0);
579err_dis:
580 pci_disable_device(pdev);
581err:
582 return ret;
583}
584
585static void __devexit
586ath5k_pci_remove(struct pci_dev *pdev)
587{
588 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
589 struct ath5k_softc *sc = hw->priv;
590
591 ath5k_debug_finish_device(sc);
592 ath5k_detach(pdev, hw);
593 ath5k_hw_detach(sc->ah);
594 free_irq(pdev->irq, sc);
595 pci_disable_msi(pdev);
596 pci_iounmap(pdev, sc->iobase);
597 pci_release_region(pdev, 0);
598 pci_disable_device(pdev);
599 ieee80211_free_hw(hw);
600}
601
602#ifdef CONFIG_PM
603static int
604ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
605{
606 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
607 struct ath5k_softc *sc = hw->priv;
608
609 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
610 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
611
612 ath5k_stop_hw(sc);
613 pci_save_state(pdev);
614 pci_disable_device(pdev);
615 pci_set_power_state(pdev, PCI_D3hot);
616
617 return 0;
618}
619
620static int
621ath5k_pci_resume(struct pci_dev *pdev)
622{
623 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
624 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 625 struct ath5k_hw *ah = sc->ah;
626 int i, err;
fa1c114f
JS		 627
628 err = pci_set_power_state(pdev, PCI_D0);
629 if (err)
630 return err;
631
632 err = pci_enable_device(pdev);
633 if (err)
634 return err;
635
636 pci_restore_state(pdev);
637 /*
638 * Suspend/Resume resets the PCI configuration space, so we have to
639 * re-disable the RETRY_TIMEOUT register (0x41) to keep
640 * PCI Tx retries from interfering with C3 CPU state
641 */
642 pci_write_config_byte(pdev, 0x41, 0);
643
644 ath5k_init(sc);
645 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
247ae449
JL		 646 ath5k_hw_set_gpio_output(ah, sc->led_pin);
647 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
fa1c114f
JS		 648 }
649
247ae449
JL		 650 /*
651 * Reset the key cache since some parts do not
652 * reset the contents on initial power up or resume.
653 *
654 * FIXME: This may need to be revisited when mac80211 becomes
655 * aware of suspend/resume.
656 */
657 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
658 ath5k_hw_reset_key(ah, i);
659
fa1c114f
JS		 660 return 0;
661}
662#endif /* CONFIG_PM */
663
664
665
666/***********************\
667* Driver Initialization *
668\***********************/
669
670static int
671ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
672{
673 struct ath5k_softc *sc = hw->priv;
674 struct ath5k_hw *ah = sc->ah;
675 u8 mac[ETH_ALEN];
676 unsigned int i;
677 int ret;
678
679 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
680
681 /*
682 * Check if the MAC has multi-rate retry support.
683 * We do this by trying to setup a fake extended
684 * descriptor. MAC's that don't have support will
685 * return false w/o doing anything. MAC's that do
686 * support it will return true w/o doing anything.
687 */
b9887638
JS		 688 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
689 if (ret < 0)
690 goto err;
691 if (ret > 0)
fa1c114f
JS		 692 __set_bit(ATH_STAT_MRRETRY, sc->status);
693
694 /*
695 * Reset the key cache since some parts do not
696 * reset the contents on initial power up.
697 */
c65638a7 698 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 699 ath5k_hw_reset_key(ah, i);
700
701 /*
702 * Collect the channel list. The 802.11 layer
703 * is resposible for filtering this list based
704 * on settings like the phy mode and regulatory
705 * domain restrictions.
706 */
707 ret = ath5k_getchannels(hw);
708 if (ret) {
709 ATH5K_ERR(sc, "can't get channels\n");
710 goto err;
711 }
712
d8ee398d
LR		 713 /* Set *_rates so we can map hw rate index */
714 ath5k_set_total_hw_rates(sc);
715
fa1c114f 716 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 717 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
718 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 719 else
d8ee398d 720 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 721
722 /*
723 * Allocate tx+rx descriptors and populate the lists.
724 */
725 ret = ath5k_desc_alloc(sc, pdev);
726 if (ret) {
727 ATH5K_ERR(sc, "can't allocate descriptors\n");
728 goto err;
729 }
730
731 /*
732 * Allocate hardware transmit queues: one queue for
733 * beacon frames and one data queue for each QoS
734 * priority. Note that hw functions handle reseting
735 * these queues at the needed time.
736 */
737 ret = ath5k_beaconq_setup(ah);
738 if (ret < 0) {
739 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
740 goto err_desc;
741 }
742 sc->bhalq = ret;
743
744 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
745 if (IS_ERR(sc->txq)) {
746 ATH5K_ERR(sc, "can't setup xmit queue\n");
747 ret = PTR_ERR(sc->txq);
748 goto err_bhal;
749 }
750
751 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
752 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
753 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
754 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
755 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
756
757 sc->led_on = 0; /* low true */
758 /*
759 * Auto-enable soft led processing for IBM cards and for
760 * 5211 minipci cards.
761 */
762 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
763 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
764 __set_bit(ATH_STAT_LEDSOFT, sc->status);
765 sc->led_pin = 0;
766 }
767 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
768 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
769 __set_bit(ATH_STAT_LEDSOFT, sc->status);
770 sc->led_pin = 0;
771 }
772 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
773 ath5k_hw_set_gpio_output(ah, sc->led_pin);
774 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
775 }
776
777 ath5k_hw_get_lladdr(ah, mac);
778 SET_IEEE80211_PERM_ADDR(hw, mac);
779 /* All MAC address bits matter for ACKs */
780 memset(sc->bssidmask, 0xff, ETH_ALEN);
781 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
782
783 ret = ieee80211_register_hw(hw);
784 if (ret) {
785 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
786 goto err_queues;
787 }
788
789 return 0;
790err_queues:
791 ath5k_txq_release(sc);
792err_bhal:
793 ath5k_hw_release_tx_queue(ah, sc->bhalq);
794err_desc:
795 ath5k_desc_free(sc, pdev);
796err:
797 return ret;
798}
799
800static void
801ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
802{
803 struct ath5k_softc *sc = hw->priv;
804
805 /*
806 * NB: the order of these is important:
807 * o call the 802.11 layer before detaching ath5k_hw to
808 * insure callbacks into the driver to delete global
809 * key cache entries can be handled
810 * o reclaim the tx queue data structures after calling
811 * the 802.11 layer as we'll get called back to reclaim
812 * node state and potentially want to use them
813 * o to cleanup the tx queues the hal is called, so detach
814 * it last
815 * XXX: ??? detach ath5k_hw ???
816 * Other than that, it's straightforward...
817 */
818 ieee80211_unregister_hw(hw);
819 ath5k_desc_free(sc, pdev);
820 ath5k_txq_release(sc);
821 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
822
823 /*
824 * NB: can't reclaim these until after ieee80211_ifdetach
825 * returns because we'll get called back to reclaim node
826 * state and potentially want to use them.
827 */
828}
829
830
831
832
833/********************\
834* Channel/mode setup *
835\********************/
836
837/*
838 * Convert IEEE channel number to MHz frequency.
839 */
840static inline short
841ath5k_ieee2mhz(short chan)
842{
843 if (chan <= 14 || chan >= 27)
844 return ieee80211chan2mhz(chan);
845 else
846 return 2212 + chan * 20;
847}
848
849static unsigned int
850ath5k_copy_rates(struct ieee80211_rate *rates,
851 const struct ath5k_rate_table *rt,
852 unsigned int max)
853{
854 unsigned int i, count;
855
856 if (rt == NULL)
857 return 0;
858
859 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 860 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
861 rates[count].hw_value = rt->rates[i].rate_code;
862 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 863 count++;
864 max--;
865 }
866
867 return count;
868}
869
870static unsigned int
871ath5k_copy_channels(struct ath5k_hw *ah,
872 struct ieee80211_channel *channels,
873 unsigned int mode,
874 unsigned int max)
875{
d8ee398d 876 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 877
878 if (!test_bit(mode, ah->ah_modes))
879 return 0;
880
fa1c114f 881 switch (mode) {
d8ee398d
LR		 882 case AR5K_MODE_11A:
883 case AR5K_MODE_11A_TURBO:
fa1c114f 884 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 885 size = 220 ;
fa1c114f
JS		 886 chfreq = CHANNEL_5GHZ;
887 break;
d8ee398d
LR		 888 case AR5K_MODE_11B:
889 case AR5K_MODE_11G:
890 case AR5K_MODE_11G_TURBO:
891 size = 26;
fa1c114f
JS		 892 chfreq = CHANNEL_2GHZ;
893 break;
894 default:
895 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
896 return 0;
897 }
898
899 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 900 ch = i + 1 ;
901 freq = ath5k_ieee2mhz(ch);
fa1c114f 902
d8ee398d
LR		 903 /* Check if channel is supported by the chipset */
904 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 905 continue;
906
d8ee398d
LR		 907 /* Write channel info and increment counter */
908 channels[count].center_freq = freq;
a3f4b914
LR		 909 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
910 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 911 switch (mode) {
912 case AR5K_MODE_11A:
913 case AR5K_MODE_11G:
914 channels[count].hw_value = chfreq | CHANNEL_OFDM;
915 break;
916 case AR5K_MODE_11A_TURBO:
917 case AR5K_MODE_11G_TURBO:
918 channels[count].hw_value = chfreq |
919 CHANNEL_OFDM | CHANNEL_TURBO;
920 break;
921 case AR5K_MODE_11B:
d8ee398d
LR		 922 channels[count].hw_value = CHANNEL_B;
923 }
fa1c114f 924
fa1c114f
JS		 925 count++;
926 max--;
927 }
928
929 return count;
930}
931
d8ee398d
LR		 932static int
933ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 934{
935 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 936 struct ath5k_hw *ah = sc->ah;
937 struct ieee80211_supported_band *sbands = sc->sbands;
938 const struct ath5k_rate_table *hw_rates;
939 unsigned int max_r, max_c, count_r, count_c;
940 int mode2g = AR5K_MODE_11G;
fa1c114f 941
d8ee398d 942 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 943
d8ee398d
LR		 944 max_r = ARRAY_SIZE(sc->rates);
945 max_c = ARRAY_SIZE(sc->channels);
946 count_r = count_c = 0;
947
948 /* 2GHz band */
400ec45a 949 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 950 mode2g = AR5K_MODE_11B;
400ec45a
LR		 951 if (!test_bit(AR5K_MODE_11B,
952 sc->ah->ah_capabilities.cap_mode))
d8ee398d 953 mode2g = -1;
fa1c114f 954 }
fa1c114f 955
400ec45a
LR		 956 if (mode2g > 0) {
957 struct ieee80211_supported_band *sband =
958 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 959
d8ee398d
LR		 960 sband->bitrates = sc->rates;
961 sband->channels = sc->channels;
fa1c114f 962
d8ee398d
LR		 963 sband->band = IEEE80211_BAND_2GHZ;
964 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
965 mode2g, max_c);
fa1c114f 966
d8ee398d
LR		 967 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
968 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 969 hw_rates, max_r);
fa1c114f 970
d8ee398d
LR		 971 count_c = sband->n_channels;
972 count_r = sband->n_bitrates;
fa1c114f 973
d8ee398d
LR		 974 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
975
976 max_r -= count_r;
977 max_c -= count_c;
fa1c114f 978
fa1c114f
JS		 979 }
980
d8ee398d 981 /* 5GHz band */
fa1c114f 982
400ec45a
LR		 983 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
984 struct ieee80211_supported_band *sband =
985 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 986
d8ee398d
LR		 987 sband->bitrates = &sc->rates[count_r];
988 sband->channels = &sc->channels[count_c];
fa1c114f 989
d8ee398d
LR		 990 sband->band = IEEE80211_BAND_5GHZ;
991 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
992 AR5K_MODE_11A, max_c);
993
994 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
995 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 996 hw_rates, max_r);
d8ee398d
LR		 997
998 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
999 }
1000
b446197c 1001 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1002
1003 return 0;
fa1c114f
JS		 1004}
1005
1006/*
1007 * Set/change channels. If the channel is really being changed,
1008 * it's done by reseting the chip. To accomplish this we must
1009 * first cleanup any pending DMA, then restart stuff after a la
1010 * ath5k_init.
1011 */
1012static int
1013ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1014{
1015 struct ath5k_hw *ah = sc->ah;
1016 int ret;
1017
d8ee398d
LR		 1018 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1019 sc->curchan->center_freq, chan->center_freq);
1020
1021 if (chan->center_freq != sc->curchan->center_freq ||
1022 chan->hw_value != sc->curchan->hw_value) {
1023
1024 sc->curchan = chan;
1025 sc->curband = &sc->sbands[chan->band];
fa1c114f 1026
fa1c114f
JS		 1027 /*
1028 * To switch channels clear any pending DMA operations;
1029 * wait long enough for the RX fifo to drain, reset the
1030 * hardware at the new frequency, and then re-enable
1031 * the relevant bits of the h/w.
1032 */
1033 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1034 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1035 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 1036 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 1037 if (ret) {
d8ee398d
LR		 1038 ATH5K_ERR(sc, "%s: unable to reset channel "
1039 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 1040 return ret;
1041 }
d8ee398d 1042
fa1c114f
JS		 1043 ath5k_hw_set_txpower_limit(sc->ah, 0);
1044
1045 /*
1046 * Re-enable rx framework.
1047 */
1048 ret = ath5k_rx_start(sc);
1049 if (ret) {
1050 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1051 __func__);
1052 return ret;
1053 }
1054
1055 /*
1056 * Change channels and update the h/w rate map
1057 * if we're switching; e.g. 11a to 11b/g.
1058 *
1059 * XXX needed?
1060 */
1061/* ath5k_chan_change(sc, chan); */
1062
1063 ath5k_beacon_config(sc);
1064 /*
1065 * Re-enable interrupts.
1066 */
1067 ath5k_hw_set_intr(ah, sc->imask);
1068 }
1069
1070 return 0;
1071}
1072
d8ee398d
LR		 1073/*
1074 * TODO: CLEAN THIS !!!
1075 */
fa1c114f
JS		 1076static void
1077ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1078{
1079 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1080 /* from Atheros NDIS driver, w/ permission */
1081 static const struct {
1082 u16 rate; /* tx/rx 802.11 rate */
1083 u16 timeOn; /* LED on time (ms) */
1084 u16 timeOff; /* LED off time (ms) */
1085 } blinkrates[] = {
1086 { 108, 40, 10 },
1087 { 96, 44, 11 },
1088 { 72, 50, 13 },
1089 { 48, 57, 14 },
1090 { 36, 67, 16 },
1091 { 24, 80, 20 },
1092 { 22, 100, 25 },
1093 { 18, 133, 34 },
1094 { 12, 160, 40 },
1095 { 10, 200, 50 },
1096 { 6, 240, 58 },
1097 { 4, 267, 66 },
1098 { 2, 400, 100 },
1099 { 0, 500, 130 }
1100 };
1101 const struct ath5k_rate_table *rt =
1102 ath5k_hw_get_rate_table(sc->ah, mode);
1103 unsigned int i, j;
1104
1105 BUG_ON(rt == NULL);
1106
1107 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1108 for (i = 0; i < 32; i++) {
1109 u8 ix = rt->rate_code_to_index[i];
1110 if (ix == 0xff) {
1111 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1112 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1113 continue;
1114 }
1115 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
fa1c114f
JS		 1116 /* receive frames include FCS */
1117 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1118 IEEE80211_RADIOTAP_F_FCS;
1119 /* setup blink rate table to avoid per-packet lookup */
1120 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1121 if (blinkrates[j].rate == /* XXX why 7f? */
1122 (rt->rates[ix].dot11_rate&0x7f))
1123 break;
1124
1125 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1126 timeOn);
1127 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1128 timeOff);
1129 }
1130 }
1131
1132 sc->curmode = mode;
d8ee398d 1133
400ec45a 1134 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1135 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1136 } else {
1137 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1138 }
fa1c114f
JS		 1139}
1140
1141static void
1142ath5k_mode_setup(struct ath5k_softc *sc)
1143{
1144 struct ath5k_hw *ah = sc->ah;
1145 u32 rfilt;
1146
1147 /* configure rx filter */
1148 rfilt = sc->filter_flags;
1149 ath5k_hw_set_rx_filter(ah, rfilt);
1150
1151 if (ath5k_hw_hasbssidmask(ah))
1152 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1153
1154 /* configure operational mode */
1155 ath5k_hw_set_opmode(ah);
1156
1157 ath5k_hw_set_mcast_filter(ah, 0, 0);
1158 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1159}
1160
d8ee398d
LR		 1161/*
1162 * Match the hw provided rate index (through descriptors)
1163 * to an index for sc->curband->bitrates, so it can be used
1164 * by the stack.
1165 *
1166 * This one is a little bit tricky but i think i'm right
1167 * about this...
1168 *
1169 * We have 4 rate tables in the following order:
1170 * XR (4 rates)
1171 * 802.11a (8 rates)
1172 * 802.11b (4 rates)
1173 * 802.11g (12 rates)
1174 * that make the hw rate table.
1175 *
1176 * Lets take a 5211 for example that supports a and b modes only.
1177 * First comes the 802.11a table and then 802.11b (total 12 rates).
1178 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1179 * if it returns 2 it points to the second 802.11a rate etc.
1180 *
1181 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1182 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1183 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1184 */
1185static void
400ec45a 1186ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1187
1188 struct ath5k_hw *ah = sc->ah;
1189
400ec45a 1190 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1191 sc->a_rates = 8;
1192
400ec45a 1193 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1194 sc->b_rates = 4;
1195
400ec45a 1196 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1197 sc->g_rates = 12;
1198
1199 /* XXX: Need to see what what happens when
1200 xr disable bits in eeprom are set */
400ec45a 1201 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1202 sc->xr_rates = 4;
1203
1204}
1205
1206static inline int
400ec45a 1207ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1208
1209 int mac80211_rix;
1210
400ec45a 1211 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1212 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1213 mac80211_rix =
1214 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1215 } else {
1216 mac80211_rix = hw_rix - sc->xr_rates;
1217 }
1218
1219 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1220 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1221 (mac80211_rix <= 0 ))
d8ee398d 1222 mac80211_rix = 1;
d8ee398d
LR		 1223
1224 return mac80211_rix;
1225}
1226
fa1c114f
JS		 1227
1228
1229
1230/***************\
1231* Buffers setup *
1232\***************/
1233
1234static int
1235ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1236{
1237 struct ath5k_hw *ah = sc->ah;
1238 struct sk_buff *skb = bf->skb;
1239 struct ath5k_desc *ds;
1240
1241 if (likely(skb == NULL)) {
1242 unsigned int off;
1243
1244 /*
1245 * Allocate buffer with headroom_needed space for the
1246 * fake physical layer header at the start.
1247 */
1248 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1249 if (unlikely(skb == NULL)) {
1250 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1251 sc->rxbufsize + sc->cachelsz - 1);
1252 return -ENOMEM;
1253 }
1254 /*
1255 * Cache-line-align. This is important (for the
1256 * 5210 at least) as not doing so causes bogus data
1257 * in rx'd frames.
1258 */
1259 off = ((unsigned long)skb->data) % sc->cachelsz;
1260 if (off != 0)
1261 skb_reserve(skb, sc->cachelsz - off);
1262
1263 bf->skb = skb;
1264 bf->skbaddr = pci_map_single(sc->pdev,
1265 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1266 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1267 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1268 dev_kfree_skb(skb);
1269 bf->skb = NULL;
1270 return -ENOMEM;
1271 }
1272 }
1273
1274 /*
1275 * Setup descriptors. For receive we always terminate
1276 * the descriptor list with a self-linked entry so we'll
1277 * not get overrun under high load (as can happen with a
1278 * 5212 when ANI processing enables PHY error frames).
1279 *
1280 * To insure the last descriptor is self-linked we create
1281 * each descriptor as self-linked and add it to the end. As
1282 * each additional descriptor is added the previous self-linked
1283 * entry is ``fixed'' naturally. This should be safe even
1284 * if DMA is happening. When processing RX interrupts we
1285 * never remove/process the last, self-linked, entry on the
1286 * descriptor list. This insures the hardware always has
1287 * someplace to write a new frame.
1288 */
1289 ds = bf->desc;
1290 ds->ds_link = bf->daddr; /* link to self */
1291 ds->ds_data = bf->skbaddr;
1292 ath5k_hw_setup_rx_desc(ah, ds,
1293 skb_tailroom(skb), /* buffer size */
1294 0);
1295
1296 if (sc->rxlink != NULL)
1297 *sc->rxlink = bf->daddr;
1298 sc->rxlink = &ds->ds_link;
1299 return 0;
1300}
1301
1302static int
1303ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1304 struct ieee80211_tx_control *ctl)
1305{
1306 struct ath5k_hw *ah = sc->ah;
1307 struct ath5k_txq *txq = sc->txq;
1308 struct ath5k_desc *ds = bf->desc;
1309 struct sk_buff *skb = bf->skb;
1310 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1311 int ret;
1312
1313 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1314 bf->ctl = *ctl;
1315 /* XXX endianness */
1316 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1317 PCI_DMA_TODEVICE);
1318
1319 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1320 flags |= AR5K_TXDESC_NOACK;
1321
281c56dd 1322 pktlen = skb->len;
fa1c114f
JS		 1323
1324 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1325 keyidx = ctl->key_idx;
1326 pktlen += ctl->icv_len;
1327 }
1328
1329 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1330 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
400ec45a
LR		 1331 (sc->power_level * 2), ctl->tx_rate->hw_value,
1332 ctl->retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1333 if (ret)
1334 goto err_unmap;
1335
1336 ds->ds_link = 0;
1337 ds->ds_data = bf->skbaddr;
1338
1339 spin_lock_bh(&txq->lock);
1340 list_add_tail(&bf->list, &txq->q);
1341 sc->tx_stats.data[txq->qnum].len++;
1342 if (txq->link == NULL) /* is this first packet? */
1343 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1344 else /* no, so only link it */
1345 *txq->link = bf->daddr;
1346
1347 txq->link = &ds->ds_link;
1348 ath5k_hw_tx_start(ah, txq->qnum);
1349 spin_unlock_bh(&txq->lock);
1350
1351 return 0;
1352err_unmap:
1353 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1354 return ret;
1355}
1356
1357/*******************\
1358* Descriptors setup *
1359\*******************/
1360
1361static int
1362ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1363{
1364 struct ath5k_desc *ds;
1365 struct ath5k_buf *bf;
1366 dma_addr_t da;
1367 unsigned int i;
1368 int ret;
1369
1370 /* allocate descriptors */
1371 sc->desc_len = sizeof(struct ath5k_desc) *
1372 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1373 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1374 if (sc->desc == NULL) {
1375 ATH5K_ERR(sc, "can't allocate descriptors\n");
1376 ret = -ENOMEM;
1377 goto err;
1378 }
1379 ds = sc->desc;
1380 da = sc->desc_daddr;
1381 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1382 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1383
1384 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1385 sizeof(struct ath5k_buf), GFP_KERNEL);
1386 if (bf == NULL) {
1387 ATH5K_ERR(sc, "can't allocate bufptr\n");
1388 ret = -ENOMEM;
1389 goto err_free;
1390 }
1391 sc->bufptr = bf;
1392
1393 INIT_LIST_HEAD(&sc->rxbuf);
1394 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1395 bf->desc = ds;
1396 bf->daddr = da;
1397 list_add_tail(&bf->list, &sc->rxbuf);
1398 }
1399
1400 INIT_LIST_HEAD(&sc->txbuf);
1401 sc->txbuf_len = ATH_TXBUF;
1402 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1403 da += sizeof(*ds)) {
1404 bf->desc = ds;
1405 bf->daddr = da;
1406 list_add_tail(&bf->list, &sc->txbuf);
1407 }
1408
1409 /* beacon buffer */
1410 bf->desc = ds;
1411 bf->daddr = da;
1412 sc->bbuf = bf;
1413
1414 return 0;
1415err_free:
1416 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1417err:
1418 sc->desc = NULL;
1419 return ret;
1420}
1421
1422static void
1423ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1424{
1425 struct ath5k_buf *bf;
1426
1427 ath5k_txbuf_free(sc, sc->bbuf);
1428 list_for_each_entry(bf, &sc->txbuf, list)
1429 ath5k_txbuf_free(sc, bf);
1430 list_for_each_entry(bf, &sc->rxbuf, list)
1431 ath5k_txbuf_free(sc, bf);
1432
1433 /* Free memory associated with all descriptors */
1434 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1435
1436 kfree(sc->bufptr);
1437 sc->bufptr = NULL;
1438}
1439
1440
1441
1442
1443
1444/**************\
1445* Queues setup *
1446\**************/
1447
1448static struct ath5k_txq *
1449ath5k_txq_setup(struct ath5k_softc *sc,
1450 int qtype, int subtype)
1451{
1452 struct ath5k_hw *ah = sc->ah;
1453 struct ath5k_txq *txq;
1454 struct ath5k_txq_info qi = {
1455 .tqi_subtype = subtype,
1456 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1457 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1458 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1459 };
1460 int qnum;
1461
1462 /*
1463 * Enable interrupts only for EOL and DESC conditions.
1464 * We mark tx descriptors to receive a DESC interrupt
1465 * when a tx queue gets deep; otherwise waiting for the
1466 * EOL to reap descriptors. Note that this is done to
1467 * reduce interrupt load and this only defers reaping
1468 * descriptors, never transmitting frames. Aside from
1469 * reducing interrupts this also permits more concurrency.
1470 * The only potential downside is if the tx queue backs
1471 * up in which case the top half of the kernel may backup
1472 * due to a lack of tx descriptors.
1473 */
1474 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1475 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1476 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1477 if (qnum < 0) {
1478 /*
1479 * NB: don't print a message, this happens
1480 * normally on parts with too few tx queues
1481 */
1482 return ERR_PTR(qnum);
1483 }
1484 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1485 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1486 qnum, ARRAY_SIZE(sc->txqs));
1487 ath5k_hw_release_tx_queue(ah, qnum);
1488 return ERR_PTR(-EINVAL);
1489 }
1490 txq = &sc->txqs[qnum];
1491 if (!txq->setup) {
1492 txq->qnum = qnum;
1493 txq->link = NULL;
1494 INIT_LIST_HEAD(&txq->q);
1495 spin_lock_init(&txq->lock);
1496 txq->setup = true;
1497 }
1498 return &sc->txqs[qnum];
1499}
1500
1501static int
1502ath5k_beaconq_setup(struct ath5k_hw *ah)
1503{
1504 struct ath5k_txq_info qi = {
1505 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1506 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1507 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1508 /* NB: for dynamic turbo, don't enable any other interrupts */
1509 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1510 };
1511
1512 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1513}
1514
1515static int
1516ath5k_beaconq_config(struct ath5k_softc *sc)
1517{
1518 struct ath5k_hw *ah = sc->ah;
1519 struct ath5k_txq_info qi;
1520 int ret;
1521
1522 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1523 if (ret)
1524 return ret;
6d91e1d8 1525 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1526 /*
1527 * Always burst out beacon and CAB traffic
1528 * (aifs = cwmin = cwmax = 0)
1529 */
1530 qi.tqi_aifs = 0;
1531 qi.tqi_cw_min = 0;
1532 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1533 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1534 /*
1535 * Adhoc mode; backoff between 0 and (2 * cw_min).
1536 */
1537 qi.tqi_aifs = 0;
1538 qi.tqi_cw_min = 0;
1539 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1540 }
1541
6d91e1d8
BR		 1542 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1543 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1544 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1545
fa1c114f
JS		 1546 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1547 if (ret) {
1548 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1549 "hardware queue!\n", __func__);
1550 return ret;
1551 }
1552
1553 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1554}
1555
1556static void
1557ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1558{
1559 struct ath5k_buf *bf, *bf0;
1560
1561 /*
1562 * NB: this assumes output has been stopped and
1563 * we do not need to block ath5k_tx_tasklet
1564 */
1565 spin_lock_bh(&txq->lock);
1566 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1567 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1568
1569 ath5k_txbuf_free(sc, bf);
1570
1571 spin_lock_bh(&sc->txbuflock);
1572 sc->tx_stats.data[txq->qnum].len--;
1573 list_move_tail(&bf->list, &sc->txbuf);
1574 sc->txbuf_len++;
1575 spin_unlock_bh(&sc->txbuflock);
1576 }
1577 txq->link = NULL;
1578 spin_unlock_bh(&txq->lock);
1579}
1580
1581/*
1582 * Drain the transmit queues and reclaim resources.
1583 */
1584static void
1585ath5k_txq_cleanup(struct ath5k_softc *sc)
1586{
1587 struct ath5k_hw *ah = sc->ah;
1588 unsigned int i;
1589
1590 /* XXX return value */
1591 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1592 /* don't touch the hardware if marked invalid */
1593 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1594 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1595 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1596 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1597 if (sc->txqs[i].setup) {
1598 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1599 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1600 "link %p\n",
1601 sc->txqs[i].qnum,
1602 ath5k_hw_get_tx_buf(ah,
1603 sc->txqs[i].qnum),
1604 sc->txqs[i].link);
1605 }
1606 }
1607 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1608
1609 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1610 if (sc->txqs[i].setup)
1611 ath5k_txq_drainq(sc, &sc->txqs[i]);
1612}
1613
1614static void
1615ath5k_txq_release(struct ath5k_softc *sc)
1616{
1617 struct ath5k_txq *txq = sc->txqs;
1618 unsigned int i;
1619
1620 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1621 if (txq->setup) {
1622 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1623 txq->setup = false;
1624 }
1625}
1626
1627
1628
1629
1630/*************\
1631* RX Handling *
1632\*************/
1633
1634/*
1635 * Enable the receive h/w following a reset.
1636 */
1637static int
1638ath5k_rx_start(struct ath5k_softc *sc)
1639{
1640 struct ath5k_hw *ah = sc->ah;
1641 struct ath5k_buf *bf;
1642 int ret;
1643
1644 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1645
1646 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1647 sc->cachelsz, sc->rxbufsize);
1648
1649 sc->rxlink = NULL;
1650
1651 spin_lock_bh(&sc->rxbuflock);
1652 list_for_each_entry(bf, &sc->rxbuf, list) {
1653 ret = ath5k_rxbuf_setup(sc, bf);
1654 if (ret != 0) {
1655 spin_unlock_bh(&sc->rxbuflock);
1656 goto err;
1657 }
1658 }
1659 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1660 spin_unlock_bh(&sc->rxbuflock);
1661
1662 ath5k_hw_put_rx_buf(ah, bf->daddr);
1663 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1664 ath5k_mode_setup(sc); /* set filters, etc. */
1665 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1666
1667 return 0;
1668err:
1669 return ret;
1670}
1671
1672/*
1673 * Disable the receive h/w in preparation for a reset.
1674 */
1675static void
1676ath5k_rx_stop(struct ath5k_softc *sc)
1677{
1678 struct ath5k_hw *ah = sc->ah;
1679
1680 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1681 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1682 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1683 mdelay(3); /* 3ms is long enough for 1 frame */
1684
1685 ath5k_debug_printrxbuffs(sc, ah);
1686
1687 sc->rxlink = NULL; /* just in case */
1688}
1689
1690static unsigned int
1691ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1692 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1693{
1694 struct ieee80211_hdr *hdr = (void *)skb->data;
1695 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1696
b47f407b
BR		 1697 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1698 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1699 return RX_FLAG_DECRYPTED;
1700
1701 /* Apparently when a default key is used to decrypt the packet
1702 the hw does not set the index used to decrypt. In such cases
1703 get the index from the packet. */
1704 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
b47f407b 1705 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
fa1c114f
JS		 1706 skb->len >= hlen + 4) {
1707 keyix = skb->data[hlen + 3] >> 6;
1708
1709 if (test_bit(keyix, sc->keymap))
1710 return RX_FLAG_DECRYPTED;
1711 }
1712
1713 return 0;
1714}
1715
036cd1ec
BR		 1716
1717static void
1718ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1719{
1720 u32 hw_tu;
1721 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1722
38c07b43 1723 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) ==
036cd1ec 1724 IEEE80211_FTYPE_MGMT &&
38c07b43 1725 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
036cd1ec 1726 IEEE80211_STYPE_BEACON &&
38c07b43 1727 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1728 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1729 /*
1730 * Received an IBSS beacon with the same BSSID. Hardware might
1731 * have updated the TSF, check if we need to update timers.
1732 */
1733 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1734 if (hw_tu >= sc->nexttbtt) {
1735 ath5k_beacon_update_timers(sc,
38c07b43 1736 le64_to_cpu(mgmt->u.beacon.timestamp));
036cd1ec
BR		 1737 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1738 "detected HW merge from received beacon\n");
1739 }
1740 }
1741}
1742
1743
fa1c114f
JS		 1744static void
1745ath5k_tasklet_rx(unsigned long data)
1746{
1747 struct ieee80211_rx_status rxs = {};
b47f407b 1748 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1749 struct sk_buff *skb;
1750 struct ath5k_softc *sc = (void *)data;
1751 struct ath5k_buf *bf;
1752 struct ath5k_desc *ds;
fa1c114f
JS		 1753 int ret;
1754 int hdrlen;
1755 int pad;
1756
1757 spin_lock(&sc->rxbuflock);
1758 do {
1759 if (unlikely(list_empty(&sc->rxbuf))) {
1760 ATH5K_WARN(sc, "empty rx buf pool\n");
1761 break;
1762 }
1763 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1764 BUG_ON(bf->skb == NULL);
1765 skb = bf->skb;
1766 ds = bf->desc;
1767
1768 /* TODO only one segment */
1769 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1770 sc->desc_len, PCI_DMA_FROMDEVICE);
1771
1772 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1773 break;
1774
b47f407b 1775 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1776 if (unlikely(ret == -EINPROGRESS))
1777 break;
1778 else if (unlikely(ret)) {
1779 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1780 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1781 return;
1782 }
1783
b47f407b 1784 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1785 ATH5K_WARN(sc, "unsupported jumbo\n");
1786 goto next;
1787 }
1788
b47f407b
BR		 1789 if (unlikely(rs.rs_status)) {
1790 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1791 goto next;
b47f407b 1792 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1793 /*
1794 * Decrypt error. If the error occurred
1795 * because there was no hardware key, then
1796 * let the frame through so the upper layers
1797 * can process it. This is necessary for 5210
1798 * parts which have no way to setup a ``clear''
1799 * key cache entry.
1800 *
1801 * XXX do key cache faulting
1802 */
b47f407b
BR		 1803 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1804 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1805 goto accept;
1806 }
b47f407b 1807 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1808 rxs.flag |= RX_FLAG_MMIC_ERROR;
1809 goto accept;
1810 }
1811
1812 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1813 if ((rs.rs_status &
1814 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1815 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1816 goto next;
1817 }
1818accept:
b47f407b
BR		 1819 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1820 rs.rs_datalen, PCI_DMA_FROMDEVICE);
fa1c114f
JS		 1821 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1822 PCI_DMA_FROMDEVICE);
1823 bf->skb = NULL;
1824
b47f407b 1825 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1826
1827 /*
1828 * the hardware adds a padding to 4 byte boundaries between
1829 * the header and the payload data if the header length is
1830 * not multiples of 4 - remove it
1831 */
1832 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1833 if (hdrlen & 3) {
1834 pad = hdrlen % 4;
1835 memmove(skb->data + pad, skb->data, hdrlen);
1836 skb_pull(skb, pad);
1837 }
1838
c0e1899b
BR		 1839 /*
1840 * always extend the mac timestamp, since this information is
1841 * also needed for proper IBSS merging.
1842 *
1843 * XXX: it might be too late to do it here, since rs_tstamp is
1844 * 15bit only. that means TSF extension has to be done within
1845 * 32768usec (about 32ms). it might be necessary to move this to
1846 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1847 *
1848 * Unfortunately we don't know when the hardware takes the rx
1849 * timestamp (beginning of phy frame, data frame, end of rx?).
1850 * The only thing we know is that it is hardware specific...
1851 * On AR5213 it seems the rx timestamp is at the end of the
1852 * frame, but i'm not sure.
1853 *
1854 * NOTE: mac80211 defines mactime at the beginning of the first
1855 * data symbol. Since we don't have any time references it's
1856 * impossible to comply to that. This affects IBSS merge only
1857 * right now, so it's not too bad...
c0e1899b 1858 */
b47f407b 1859 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1860 rxs.flag |= RX_FLAG_TSFT;
1861
d8ee398d
LR		 1862 rxs.freq = sc->curchan->center_freq;
1863 rxs.band = sc->curband->band;
fa1c114f
JS		 1864
1865 /*
1866 * signal quality:
1867 * the names here are misleading and the usage of these
1868 * values by iwconfig makes it even worse
1869 */
1870 /* noise floor in dBm, from the last noise calibration */
1871 rxs.noise = sc->ah->ah_noise_floor;
1872 /* signal level in dBm */
b47f407b 1873 rxs.ssi = rxs.noise + rs.rs_rssi;
fa1c114f
JS		 1874 /*
1875 * "signal" is actually displayed as Link Quality by iwconfig
1876 * we provide a percentage based on rssi (assuming max rssi 64)
1877 */
b47f407b 1878 rxs.signal = rs.rs_rssi * 100 / 64;
fa1c114f 1879
b47f407b
BR		 1880 rxs.antenna = rs.rs_antenna;
1881 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1882 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1883
1884 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1885
036cd1ec
BR		 1886 /* check beacons in IBSS mode */
1887 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1888 ath5k_check_ibss_hw_merge(sc, skb);
1889
fa1c114f 1890 __ieee80211_rx(sc->hw, skb, &rxs);
b47f407b 1891 sc->led_rxrate = rs.rs_rate;
fa1c114f
JS		 1892 ath5k_led_event(sc, ATH_LED_RX);
1893next:
1894 list_move_tail(&bf->list, &sc->rxbuf);
1895 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1896 spin_unlock(&sc->rxbuflock);
1897}
1898
1899
1900
1901
1902/*************\
1903* TX Handling *
1904\*************/
1905
1906static void
1907ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1908{
1909 struct ieee80211_tx_status txs = {};
b47f407b 1910 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1911 struct ath5k_buf *bf, *bf0;
1912 struct ath5k_desc *ds;
1913 struct sk_buff *skb;
1914 int ret;
1915
1916 spin_lock(&txq->lock);
1917 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1918 ds = bf->desc;
1919
1920 /* TODO only one segment */
1921 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1922 sc->desc_len, PCI_DMA_FROMDEVICE);
b47f407b 1923 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1924 if (unlikely(ret == -EINPROGRESS))
1925 break;
1926 else if (unlikely(ret)) {
1927 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1928 ret, txq->qnum);
1929 break;
1930 }
1931
1932 skb = bf->skb;
1933 bf->skb = NULL;
1934 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1935 PCI_DMA_TODEVICE);
1936
1937 txs.control = bf->ctl;
b47f407b
BR		 1938 txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1939 if (unlikely(ts.ts_status)) {
fa1c114f 1940 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1941 if (ts.ts_status & AR5K_TXERR_XRETRY)
fa1c114f 1942 txs.excessive_retries = 1;
b47f407b 1943 else if (ts.ts_status & AR5K_TXERR_FILT)
fa1c114f
JS		 1944 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1945 } else {
1946 txs.flags |= IEEE80211_TX_STATUS_ACK;
b47f407b 1947 txs.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1948 }
1949
1950 ieee80211_tx_status(sc->hw, skb, &txs);
1951 sc->tx_stats.data[txq->qnum].count++;
1952
1953 spin_lock(&sc->txbuflock);
1954 sc->tx_stats.data[txq->qnum].len--;
1955 list_move_tail(&bf->list, &sc->txbuf);
1956 sc->txbuf_len++;
1957 spin_unlock(&sc->txbuflock);
1958 }
1959 if (likely(list_empty(&txq->q)))
1960 txq->link = NULL;
1961 spin_unlock(&txq->lock);
1962 if (sc->txbuf_len > ATH_TXBUF / 5)
1963 ieee80211_wake_queues(sc->hw);
1964}
1965
1966static void
1967ath5k_tasklet_tx(unsigned long data)
1968{
1969 struct ath5k_softc *sc = (void *)data;
1970
1971 ath5k_tx_processq(sc, sc->txq);
1972
1973 ath5k_led_event(sc, ATH_LED_TX);
1974}
1975
1976
1977
1978
1979/*****************\
1980* Beacon handling *
1981\*****************/
1982
1983/*
1984 * Setup the beacon frame for transmit.
1985 */
1986static int
1987ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1988 struct ieee80211_tx_control *ctl)
1989{
1990 struct sk_buff *skb = bf->skb;
1991 struct ath5k_hw *ah = sc->ah;
1992 struct ath5k_desc *ds;
1993 int ret, antenna = 0;
1994 u32 flags;
1995
1996 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1997 PCI_DMA_TODEVICE);
1998 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1999 "skbaddr %llx\n", skb, skb->data, skb->len,
2000 (unsigned long long)bf->skbaddr);
2001 if (pci_dma_mapping_error(bf->skbaddr)) {
2002 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2003 return -EIO;
2004 }
2005
2006 ds = bf->desc;
2007
2008 flags = AR5K_TXDESC_NOACK;
2009 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
2010 ds->ds_link = bf->daddr; /* self-linked */
2011 flags |= AR5K_TXDESC_VEOL;
2012 /*
2013 * Let hardware handle antenna switching if txantenna is not set
2014 */
2015 } else {
2016 ds->ds_link = 0;
2017 /*
2018 * Switch antenna every 4 beacons if txantenna is not set
2019 * XXX assumes two antennas
2020 */
2021 if (antenna == 0)
2022 antenna = sc->bsent & 4 ? 2 : 1;
2023 }
2024
2025 ds->ds_data = bf->skbaddr;
281c56dd 2026 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2027 ieee80211_get_hdrlen_from_skb(skb),
400ec45a
LR		 2028 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2029 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID,
2030 antenna, flags, 0, 0);
fa1c114f
JS		 2031 if (ret)
2032 goto err_unmap;
2033
2034 return 0;
2035err_unmap:
2036 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2037 return ret;
2038}
2039
2040/*
2041 * Transmit a beacon frame at SWBA. Dynamic updates to the
2042 * frame contents are done as needed and the slot time is
2043 * also adjusted based on current state.
2044 *
2045 * this is usually called from interrupt context (ath5k_intr())
2046 * but also from ath5k_beacon_config() in IBSS mode which in turn
2047 * can be called from a tasklet and user context
2048 */
2049static void
2050ath5k_beacon_send(struct ath5k_softc *sc)
2051{
2052 struct ath5k_buf *bf = sc->bbuf;
2053 struct ath5k_hw *ah = sc->ah;
2054
be9b7259 2055 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 2056
2057 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2058 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2059 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2060 return;
2061 }
2062 /*
2063 * Check if the previous beacon has gone out. If
2064 * not don't don't try to post another, skip this
2065 * period and wait for the next. Missed beacons
2066 * indicate a problem and should not occur. If we
2067 * miss too many consecutive beacons reset the device.
2068 */
2069 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2070 sc->bmisscount++;
be9b7259 2071 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2072 "missed %u consecutive beacons\n", sc->bmisscount);
2073 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2074 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2075 "stuck beacon time (%u missed)\n",
2076 sc->bmisscount);
2077 tasklet_schedule(&sc->restq);
2078 }
2079 return;
2080 }
2081 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2082 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2083 "resume beacon xmit after %u misses\n",
2084 sc->bmisscount);
2085 sc->bmisscount = 0;
2086 }
2087
2088 /*
2089 * Stop any current dma and put the new frame on the queue.
2090 * This should never fail since we check above that no frames
2091 * are still pending on the queue.
2092 */
2093 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2094 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2095 /* NB: hw still stops DMA, so proceed */
2096 }
2097 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2098 PCI_DMA_TODEVICE);
2099
2100 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2101 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2102 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2103 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2104
2105 sc->bsent++;
2106}
2107
2108
9804b98d
BR		 2109/**
2110 * ath5k_beacon_update_timers - update beacon timers
2111 *
2112 * @sc: struct ath5k_softc pointer we are operating on
2113 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2114 * beacon timer update based on the current HW TSF.
2115 *
2116 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2117 * of a received beacon or the current local hardware TSF and write it to the
2118 * beacon timer registers.
2119 *
2120 * This is called in a variety of situations, e.g. when a beacon is received,
2121 * when a HW merge has been detected, but also when an new IBSS is created or
2122 * when we otherwise know we have to update the timers, but we keep it in this
2123 * function to have it all together in one place.
2124 */
fa1c114f 2125static void
9804b98d 2126ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2127{
2128 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2129 u32 nexttbtt, intval, hw_tu, bc_tu;
2130 u64 hw_tsf;
fa1c114f
JS		 2131
2132 intval = sc->bintval & AR5K_BEACON_PERIOD;
2133 if (WARN_ON(!intval))
2134 return;
2135
9804b98d
BR		 2136 /* beacon TSF converted to TU */
2137 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2138
9804b98d
BR		 2139 /* current TSF converted to TU */
2140 hw_tsf = ath5k_hw_get_tsf64(ah);
2141 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2142
9804b98d
BR		 2143#define FUDGE 3
2144 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2145 if (bc_tsf == -1) {
2146 /*
2147 * no beacons received, called internally.
2148 * just need to refresh timers based on HW TSF.
2149 */
2150 nexttbtt = roundup(hw_tu + FUDGE, intval);
2151 } else if (bc_tsf == 0) {
2152 /*
2153 * no beacon received, probably called by ath5k_reset_tsf().
2154 * reset TSF to start with 0.
2155 */
2156 nexttbtt = intval;
2157 intval |= AR5K_BEACON_RESET_TSF;
2158 } else if (bc_tsf > hw_tsf) {
2159 /*
2160 * beacon received, SW merge happend but HW TSF not yet updated.
2161 * not possible to reconfigure timers yet, but next time we
2162 * receive a beacon with the same BSSID, the hardware will
2163 * automatically update the TSF and then we need to reconfigure
2164 * the timers.
2165 */
2166 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2167 "need to wait for HW TSF sync\n");
2168 return;
2169 } else {
2170 /*
2171 * most important case for beacon synchronization between STA.
2172 *
2173 * beacon received and HW TSF has been already updated by HW.
2174 * update next TBTT based on the TSF of the beacon, but make
2175 * sure it is ahead of our local TSF timer.
2176 */
2177 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2178 }
2179#undef FUDGE
fa1c114f 2180
036cd1ec
BR		 2181 sc->nexttbtt = nexttbtt;
2182
fa1c114f 2183 intval |= AR5K_BEACON_ENA;
fa1c114f 2184 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2185
2186 /*
2187 * debugging output last in order to preserve the time critical aspect
2188 * of this function
2189 */
2190 if (bc_tsf == -1)
2191 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2192 "reconfigured timers based on HW TSF\n");
2193 else if (bc_tsf == 0)
2194 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2195 "reset HW TSF and timers\n");
2196 else
2197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2198 "updated timers based on beacon TSF\n");
2199
2200 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2201 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2202 (unsigned long long) bc_tsf,
2203 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2204 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2205 intval & AR5K_BEACON_PERIOD,
2206 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2207 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2208}
2209
2210
036cd1ec
BR		 2211/**
2212 * ath5k_beacon_config - Configure the beacon queues and interrupts
2213 *
2214 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2215 *
2216 * When operating in station mode we want to receive a BMISS interrupt when we
2217 * stop seeing beacons from the AP we've associated with so we can look for
2218 * another AP to associate with.
2219 *
036cd1ec
BR		 2220 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2221 * interrupts to detect HW merges only.
2222 *
2223 * AP mode is missing.
fa1c114f
JS		 2224 */
2225static void
2226ath5k_beacon_config(struct ath5k_softc *sc)
2227{
2228 struct ath5k_hw *ah = sc->ah;
2229
2230 ath5k_hw_set_intr(ah, 0);
2231 sc->bmisscount = 0;
2232
2233 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2234 sc->imask |= AR5K_INT_BMISS;
2235 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2236 /*
036cd1ec
BR		 2237 * In IBSS mode we use a self-linked tx descriptor and let the
2238 * hardware send the beacons automatically. We have to load it
fa1c114f 2239 * only once here.
036cd1ec
BR		 2240 * We use the SWBA interrupt only to keep track of the beacon
2241 * timers in order to detect HW merges (automatic TSF updates).
fa1c114f
JS		 2242 */
2243 ath5k_beaconq_config(sc);
fa1c114f 2244
036cd1ec
BR		 2245 sc->imask |= AR5K_INT_SWBA;
2246
2247 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2248 ath5k_beacon_send(sc);
2249 }
2250 /* TODO else AP */
2251
2252 ath5k_hw_set_intr(ah, sc->imask);
2253}
2254
2255
2256/********************\
2257* Interrupt handling *
2258\********************/
2259
2260static int
2261ath5k_init(struct ath5k_softc *sc)
2262{
2263 int ret;
2264
2265 mutex_lock(&sc->lock);
2266
2267 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2268
2269 /*
2270 * Stop anything previously setup. This is safe
2271 * no matter this is the first time through or not.
2272 */
2273 ath5k_stop_locked(sc);
2274
2275 /*
2276 * The basic interface to setting the hardware in a good
2277 * state is ``reset''. On return the hardware is known to
2278 * be powered up and with interrupts disabled. This must
2279 * be followed by initialization of the appropriate bits
2280 * and then setup of the interrupt mask.
2281 */
d8ee398d
LR		 2282 sc->curchan = sc->hw->conf.channel;
2283 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2284 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2285 if (ret) {
2286 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2287 goto done;
2288 }
2289 /*
2290 * This is needed only to setup initial state
2291 * but it's best done after a reset.
2292 */
2293 ath5k_hw_set_txpower_limit(sc->ah, 0);
2294
2295 /*
2296 * Setup the hardware after reset: the key cache
2297 * is filled as needed and the receive engine is
2298 * set going. Frame transmit is handled entirely
2299 * in the frame output path; there's nothing to do
2300 * here except setup the interrupt mask.
2301 */
2302 ret = ath5k_rx_start(sc);
2303 if (ret)
2304 goto done;
2305
2306 /*
2307 * Enable interrupts.
2308 */
2309 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2310 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2311
2312 ath5k_hw_set_intr(sc->ah, sc->imask);
2313 /* Set ack to be sent at low bit-rates */
2314 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2315
2316 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2317 msecs_to_jiffies(ath5k_calinterval * 1000)));
2318
2319 ret = 0;
2320done:
2321 mutex_unlock(&sc->lock);
2322 return ret;
2323}
2324
2325static int
2326ath5k_stop_locked(struct ath5k_softc *sc)
2327{
2328 struct ath5k_hw *ah = sc->ah;
2329
2330 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2331 test_bit(ATH_STAT_INVALID, sc->status));
2332
2333 /*
2334 * Shutdown the hardware and driver:
2335 * stop output from above
2336 * disable interrupts
2337 * turn off timers
2338 * turn off the radio
2339 * clear transmit machinery
2340 * clear receive machinery
2341 * drain and release tx queues
2342 * reclaim beacon resources
2343 * power down hardware
2344 *
2345 * Note that some of this work is not possible if the
2346 * hardware is gone (invalid).
2347 */
2348 ieee80211_stop_queues(sc->hw);
2349
2350 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2351 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2352 del_timer_sync(&sc->led_tim);
2353 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2354 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2355 }
2356 ath5k_hw_set_intr(ah, 0);
2357 }
2358 ath5k_txq_cleanup(sc);
2359 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2360 ath5k_rx_stop(sc);
2361 ath5k_hw_phy_disable(ah);
2362 } else
2363 sc->rxlink = NULL;
2364
2365 return 0;
2366}
2367
2368/*
2369 * Stop the device, grabbing the top-level lock to protect
2370 * against concurrent entry through ath5k_init (which can happen
2371 * if another thread does a system call and the thread doing the
2372 * stop is preempted).
2373 */
2374static int
2375ath5k_stop_hw(struct ath5k_softc *sc)
2376{
2377 int ret;
2378
2379 mutex_lock(&sc->lock);
2380 ret = ath5k_stop_locked(sc);
2381 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2382 /*
2383 * Set the chip in full sleep mode. Note that we are
2384 * careful to do this only when bringing the interface
2385 * completely to a stop. When the chip is in this state
2386 * it must be carefully woken up or references to
2387 * registers in the PCI clock domain may freeze the bus
2388 * (and system). This varies by chip and is mostly an
2389 * issue with newer parts that go to sleep more quickly.
2390 */
2391 if (sc->ah->ah_mac_srev >= 0x78) {
2392 /*
2393 * XXX
2394 * don't put newer MAC revisions > 7.8 to sleep because
2395 * of the above mentioned problems
2396 */
2397 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2398 "not putting device to sleep\n");
2399 } else {
2400 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2401 "putting device to full sleep\n");
2402 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2403 }
2404 }
2405 ath5k_txbuf_free(sc, sc->bbuf);
2406 mutex_unlock(&sc->lock);
2407
2408 del_timer_sync(&sc->calib_tim);
2409
2410 return ret;
2411}
2412
2413static irqreturn_t
2414ath5k_intr(int irq, void *dev_id)
2415{
2416 struct ath5k_softc *sc = dev_id;
2417 struct ath5k_hw *ah = sc->ah;
2418 enum ath5k_int status;
2419 unsigned int counter = 1000;
2420
2421 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2422 !ath5k_hw_is_intr_pending(ah)))
2423 return IRQ_NONE;
2424
2425 do {
2426 /*
2427 * Figure out the reason(s) for the interrupt. Note
2428 * that get_isr returns a pseudo-ISR that may include
2429 * bits we haven't explicitly enabled so we mask the
2430 * value to insure we only process bits we requested.
2431 */
2432 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2433 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2434 status, sc->imask);
2435 status &= sc->imask; /* discard unasked for bits */
2436 if (unlikely(status & AR5K_INT_FATAL)) {
2437 /*
2438 * Fatal errors are unrecoverable.
2439 * Typically these are caused by DMA errors.
2440 */
2441 tasklet_schedule(&sc->restq);
2442 } else if (unlikely(status & AR5K_INT_RXORN)) {
2443 tasklet_schedule(&sc->restq);
2444 } else {
2445 if (status & AR5K_INT_SWBA) {
2446 /*
2447 * Software beacon alert--time to send a beacon.
2448 * Handle beacon transmission directly; deferring
2449 * this is too slow to meet timing constraints
2450 * under load.
036cd1ec
BR		 2451 *
2452 * In IBSS mode we use this interrupt just to
2453 * keep track of the next TBTT (target beacon
2454 * transmission time) in order to detect hardware
2455 * merges (TSF updates).
fa1c114f 2456 */
036cd1ec
BR		 2457 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2458 /* XXX: only if VEOL suppported */
2459 u64 tsf = ath5k_hw_get_tsf64(ah);
2460 sc->nexttbtt += sc->bintval;
2461 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2462 "SWBA nexttbtt: %x hw_tu: %x "
2463 "TSF: %llx\n",
2464 sc->nexttbtt,
2465 TSF_TO_TU(tsf),
2466 (unsigned long long) tsf);
036cd1ec
BR		 2467 } else {
2468 ath5k_beacon_send(sc);
2469 }
fa1c114f
JS		 2470 }
2471 if (status & AR5K_INT_RXEOL) {
2472 /*
2473 * NB: the hardware should re-read the link when
2474 * RXE bit is written, but it doesn't work at
2475 * least on older hardware revs.
2476 */
2477 sc->rxlink = NULL;
2478 }
2479 if (status & AR5K_INT_TXURN) {
2480 /* bump tx trigger level */
2481 ath5k_hw_update_tx_triglevel(ah, true);
2482 }
2483 if (status & AR5K_INT_RX)
2484 tasklet_schedule(&sc->rxtq);
2485 if (status & AR5K_INT_TX)
2486 tasklet_schedule(&sc->txtq);
2487 if (status & AR5K_INT_BMISS) {
2488 }
2489 if (status & AR5K_INT_MIB) {
2490 /* TODO */
2491 }
2492 }
2493 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2494
2495 if (unlikely(!counter))
2496 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2497
2498 return IRQ_HANDLED;
2499}
2500
2501static void
2502ath5k_tasklet_reset(unsigned long data)
2503{
2504 struct ath5k_softc *sc = (void *)data;
2505
2506 ath5k_reset(sc->hw);
2507}
2508
2509/*
2510 * Periodically recalibrate the PHY to account
2511 * for temperature/environment changes.
2512 */
2513static void
2514ath5k_calibrate(unsigned long data)
2515{
2516 struct ath5k_softc *sc = (void *)data;
2517 struct ath5k_hw *ah = sc->ah;
2518
2519 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2520 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2521 sc->curchan->hw_value);
fa1c114f
JS		 2522
2523 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2524 /*
2525 * Rfgain is out of bounds, reset the chip
2526 * to load new gain values.
2527 */
2528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2529 ath5k_reset(sc->hw);
2530 }
2531 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2532 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2533 ieee80211_frequency_to_channel(
2534 sc->curchan->center_freq));
fa1c114f
JS		 2535
2536 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2537 msecs_to_jiffies(ath5k_calinterval * 1000)));
2538}
2539
2540
2541
2542/***************\
2543* LED functions *
2544\***************/
2545
2546static void
2547ath5k_led_off(unsigned long data)
2548{
2549 struct ath5k_softc *sc = (void *)data;
2550
2551 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2552 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2553 else {
2554 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2555 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2556 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2557 }
2558}
2559
2560/*
2561 * Blink the LED according to the specified on/off times.
2562 */
2563static void
2564ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2565 unsigned int off)
2566{
2567 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2568 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2569 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2570 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2571 sc->led_off = off;
2572 mod_timer(&sc->led_tim, jiffies + on);
2573}
2574
2575static void
2576ath5k_led_event(struct ath5k_softc *sc, int event)
2577{
2578 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2579 return;
2580 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2581 return; /* don't interrupt active blink */
2582 switch (event) {
2583 case ATH_LED_TX:
2584 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2585 sc->hwmap[sc->led_txrate].ledoff);
2586 break;
2587 case ATH_LED_RX:
2588 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2589 sc->hwmap[sc->led_rxrate].ledoff);
2590 break;
2591 }
2592}
2593
2594
2595
2596
2597/********************\
2598* Mac80211 functions *
2599\********************/
2600
2601static int
2602ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2603 struct ieee80211_tx_control *ctl)
2604{
2605 struct ath5k_softc *sc = hw->priv;
2606 struct ath5k_buf *bf;
2607 unsigned long flags;
2608 int hdrlen;
2609 int pad;
2610
2611 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2612
2613 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2614 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2615
2616 /*
2617 * the hardware expects the header padded to 4 byte boundaries
2618 * if this is not the case we add the padding after the header
2619 */
2620 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2621 if (hdrlen & 3) {
2622 pad = hdrlen % 4;
2623 if (skb_headroom(skb) < pad) {
2624 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2625 " headroom to pad %d\n", hdrlen, pad);
2626 return -1;
2627 }
2628 skb_push(skb, pad);
2629 memmove(skb->data, skb->data+pad, hdrlen);
2630 }
2631
d8ee398d 2632 sc->led_txrate = ctl->tx_rate->hw_value;
fa1c114f
JS		 2633
2634 spin_lock_irqsave(&sc->txbuflock, flags);
2635 if (list_empty(&sc->txbuf)) {
2636 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2637 spin_unlock_irqrestore(&sc->txbuflock, flags);
2638 ieee80211_stop_queue(hw, ctl->queue);
2639 return -1;
2640 }
2641 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2642 list_del(&bf->list);
2643 sc->txbuf_len--;
2644 if (list_empty(&sc->txbuf))
2645 ieee80211_stop_queues(hw);
2646 spin_unlock_irqrestore(&sc->txbuflock, flags);
2647
2648 bf->skb = skb;
2649
2650 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2651 bf->skb = NULL;
2652 spin_lock_irqsave(&sc->txbuflock, flags);
2653 list_add_tail(&bf->list, &sc->txbuf);
2654 sc->txbuf_len++;
2655 spin_unlock_irqrestore(&sc->txbuflock, flags);
2656 dev_kfree_skb_any(skb);
2657 return 0;
2658 }
2659
2660 return 0;
2661}
2662
2663static int
2664ath5k_reset(struct ieee80211_hw *hw)
2665{
2666 struct ath5k_softc *sc = hw->priv;
2667 struct ath5k_hw *ah = sc->ah;
2668 int ret;
2669
2670 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2671
2672 ath5k_hw_set_intr(ah, 0);
2673 ath5k_txq_cleanup(sc);
2674 ath5k_rx_stop(sc);
2675
2676 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2677 if (unlikely(ret)) {
2678 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2679 goto err;
2680 }
2681 ath5k_hw_set_txpower_limit(sc->ah, 0);
2682
2683 ret = ath5k_rx_start(sc);
2684 if (unlikely(ret)) {
2685 ATH5K_ERR(sc, "can't start recv logic\n");
2686 goto err;
2687 }
2688 /*
2689 * We may be doing a reset in response to an ioctl
2690 * that changes the channel so update any state that
2691 * might change as a result.
2692 *
2693 * XXX needed?
2694 */
2695/* ath5k_chan_change(sc, c); */
2696 ath5k_beacon_config(sc);
2697 /* intrs are started by ath5k_beacon_config */
2698
2699 ieee80211_wake_queues(hw);
2700
2701 return 0;
2702err:
2703 return ret;
2704}
2705
2706static int ath5k_start(struct ieee80211_hw *hw)
2707{
2708 return ath5k_init(hw->priv);
2709}
2710
2711static void ath5k_stop(struct ieee80211_hw *hw)
2712{
2713 ath5k_stop_hw(hw->priv);
2714}
2715
2716static int ath5k_add_interface(struct ieee80211_hw *hw,
2717 struct ieee80211_if_init_conf *conf)
2718{
2719 struct ath5k_softc *sc = hw->priv;
2720 int ret;
2721
2722 mutex_lock(&sc->lock);
32bfd35d 2723 if (sc->vif) {
fa1c114f
JS		 2724 ret = 0;
2725 goto end;
2726 }
2727
32bfd35d 2728 sc->vif = conf->vif;
fa1c114f
JS		 2729
2730 switch (conf->type) {
2731 case IEEE80211_IF_TYPE_STA:
2732 case IEEE80211_IF_TYPE_IBSS:
2733 case IEEE80211_IF_TYPE_MNTR:
2734 sc->opmode = conf->type;
2735 break;
2736 default:
2737 ret = -EOPNOTSUPP;
2738 goto end;
2739 }
2740 ret = 0;
2741end:
2742 mutex_unlock(&sc->lock);
2743 return ret;
2744}
2745
2746static void
2747ath5k_remove_interface(struct ieee80211_hw *hw,
2748 struct ieee80211_if_init_conf *conf)
2749{
2750 struct ath5k_softc *sc = hw->priv;
2751
2752 mutex_lock(&sc->lock);
32bfd35d 2753 if (sc->vif != conf->vif)
fa1c114f
JS		 2754 goto end;
2755
32bfd35d 2756 sc->vif = NULL;
fa1c114f
JS		 2757end:
2758 mutex_unlock(&sc->lock);
2759}
2760
d8ee398d
LR		 2761/*
2762 * TODO: Phy disable/diversity etc
2763 */
fa1c114f
JS		 2764static int
2765ath5k_config(struct ieee80211_hw *hw,
2766 struct ieee80211_conf *conf)
2767{
2768 struct ath5k_softc *sc = hw->priv;
2769
e535c1ac 2770 sc->bintval = conf->beacon_int;
d8ee398d 2771 sc->power_level = conf->power_level;
fa1c114f 2772
d8ee398d 2773 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2774}
2775
2776static int
32bfd35d 2777ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2778 struct ieee80211_if_conf *conf)
2779{
2780 struct ath5k_softc *sc = hw->priv;
2781 struct ath5k_hw *ah = sc->ah;
2782 int ret;
2783
2784 /* Set to a reasonable value. Note that this will
2785 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2786 sc->bintval = 1000;
fa1c114f 2787 mutex_lock(&sc->lock);
32bfd35d 2788 if (sc->vif != vif) {
fa1c114f
JS		 2789 ret = -EIO;
2790 goto unlock;
2791 }
2792 if (conf->bssid) {
2793 /* Cache for later use during resets */
2794 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2795 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2796 * a clean way of letting us retrieve this yet. */
2797 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2798 }
2799 mutex_unlock(&sc->lock);
2800
2801 return ath5k_reset(hw);
2802unlock:
2803 mutex_unlock(&sc->lock);
2804 return ret;
2805}
2806
2807#define SUPPORTED_FIF_FLAGS \
2808 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2809 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2810 FIF_BCN_PRBRESP_PROMISC
2811/*
2812 * o always accept unicast, broadcast, and multicast traffic
2813 * o multicast traffic for all BSSIDs will be enabled if mac80211
2814 * says it should be
2815 * o maintain current state of phy ofdm or phy cck error reception.
2816 * If the hardware detects any of these type of errors then
2817 * ath5k_hw_get_rx_filter() will pass to us the respective
2818 * hardware filters to be able to receive these type of frames.
2819 * o probe request frames are accepted only when operating in
2820 * hostap, adhoc, or monitor modes
2821 * o enable promiscuous mode according to the interface state
2822 * o accept beacons:
2823 * - when operating in adhoc mode so the 802.11 layer creates
2824 * node table entries for peers,
2825 * - when operating in station mode for collecting rssi data when
2826 * the station is otherwise quiet, or
2827 * - when scanning
2828 */
2829static void ath5k_configure_filter(struct ieee80211_hw *hw,
2830 unsigned int changed_flags,
2831 unsigned int *new_flags,
2832 int mc_count, struct dev_mc_list *mclist)
2833{
2834 struct ath5k_softc *sc = hw->priv;
2835 struct ath5k_hw *ah = sc->ah;
2836 u32 mfilt[2], val, rfilt;
2837 u8 pos;
2838 int i;
2839
2840 mfilt[0] = 0;
2841 mfilt[1] = 0;
2842
2843 /* Only deal with supported flags */
2844 changed_flags &= SUPPORTED_FIF_FLAGS;
2845 *new_flags &= SUPPORTED_FIF_FLAGS;
2846
2847 /* If HW detects any phy or radar errors, leave those filters on.
2848 * Also, always enable Unicast, Broadcasts and Multicast
2849 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2850 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2851 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2852 AR5K_RX_FILTER_MCAST);
2853
2854 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2855 if (*new_flags & FIF_PROMISC_IN_BSS) {
2856 rfilt |= AR5K_RX_FILTER_PROM;
2857 __set_bit(ATH_STAT_PROMISC, sc->status);
2858 }
2859 else
2860 __clear_bit(ATH_STAT_PROMISC, sc->status);
2861 }
2862
2863 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2864 if (*new_flags & FIF_ALLMULTI) {
2865 mfilt[0] = ~0;
2866 mfilt[1] = ~0;
2867 } else {
2868 for (i = 0; i < mc_count; i++) {
2869 if (!mclist)
2870 break;
2871 /* calculate XOR of eight 6-bit values */
2872 val = LE_READ_4(mclist->dmi_addr + 0);
2873 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2874 val = LE_READ_4(mclist->dmi_addr + 3);
2875 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2876 pos &= 0x3f;
2877 mfilt[pos / 32] |= (1 << (pos % 32));
2878 /* XXX: we might be able to just do this instead,
2879 * but not sure, needs testing, if we do use this we'd
2880 * neet to inform below to not reset the mcast */
2881 /* ath5k_hw_set_mcast_filterindex(ah,
2882 * mclist->dmi_addr[5]); */
2883 mclist = mclist->next;
2884 }
2885 }
2886
2887 /* This is the best we can do */
2888 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2889 rfilt |= AR5K_RX_FILTER_PHYERR;
2890
2891 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2892 * and probes for any BSSID, this needs testing */
2893 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2894 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2895
2896 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2897 * set we should only pass on control frames for this
2898 * station. This needs testing. I believe right now this
2899 * enables *all* control frames, which is OK.. but
2900 * but we should see if we can improve on granularity */
2901 if (*new_flags & FIF_CONTROL)
2902 rfilt |= AR5K_RX_FILTER_CONTROL;
2903
2904 /* Additional settings per mode -- this is per ath5k */
2905
2906 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2907
2908 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2909 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2910 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2911 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2912 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2913 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2914 test_bit(ATH_STAT_PROMISC, sc->status))
2915 rfilt |= AR5K_RX_FILTER_PROM;
2916 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2917 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2918 rfilt |= AR5K_RX_FILTER_BEACON;
2919 }
2920
2921 /* Set filters */
2922 ath5k_hw_set_rx_filter(ah,rfilt);
2923
2924 /* Set multicast bits */
2925 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2926 /* Set the cached hw filter flags, this will alter actually
2927 * be set in HW */
2928 sc->filter_flags = rfilt;
2929}
2930
2931static int
2932ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2933 const u8 *local_addr, const u8 *addr,
2934 struct ieee80211_key_conf *key)
2935{
2936 struct ath5k_softc *sc = hw->priv;
2937 int ret = 0;
2938
2939 switch(key->alg) {
2940 case ALG_WEP:
6844e63a
LR		 2941 /* XXX: fix hardware encryption, its not working. For now
2942 * allow software encryption */
2943 /* break; */
fa1c114f
JS		 2944 case ALG_TKIP:
2945 case ALG_CCMP:
2946 return -EOPNOTSUPP;
2947 default:
2948 WARN_ON(1);
2949 return -EINVAL;
2950 }
2951
2952 mutex_lock(&sc->lock);
2953
2954 switch (cmd) {
2955 case SET_KEY:
2956 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2957 if (ret) {
2958 ATH5K_ERR(sc, "can't set the key\n");
2959 goto unlock;
2960 }
2961 __set_bit(key->keyidx, sc->keymap);
2962 key->hw_key_idx = key->keyidx;
2963 break;
2964 case DISABLE_KEY:
2965 ath5k_hw_reset_key(sc->ah, key->keyidx);
2966 __clear_bit(key->keyidx, sc->keymap);
2967 break;
2968 default:
2969 ret = -EINVAL;
2970 goto unlock;
2971 }
2972
2973unlock:
2974 mutex_unlock(&sc->lock);
2975 return ret;
2976}
2977
2978static int
2979ath5k_get_stats(struct ieee80211_hw *hw,
2980 struct ieee80211_low_level_stats *stats)
2981{
2982 struct ath5k_softc *sc = hw->priv;
2983
2984 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2985
2986 return 0;
2987}
2988
2989static int
2990ath5k_get_tx_stats(struct ieee80211_hw *hw,
2991 struct ieee80211_tx_queue_stats *stats)
2992{
2993 struct ath5k_softc *sc = hw->priv;
2994
2995 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2996
2997 return 0;
2998}
2999
3000static u64
3001ath5k_get_tsf(struct ieee80211_hw *hw)
3002{
3003 struct ath5k_softc *sc = hw->priv;
3004
3005 return ath5k_hw_get_tsf64(sc->ah);
3006}
3007
3008static void
3009ath5k_reset_tsf(struct ieee80211_hw *hw)
3010{
3011 struct ath5k_softc *sc = hw->priv;
3012
9804b98d
BR		 3013 /*
3014 * in IBSS mode we need to update the beacon timers too.
3015 * this will also reset the TSF if we call it with 0
3016 */
3017 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3018 ath5k_beacon_update_timers(sc, 0);
3019 else
3020 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3021}
3022
3023static int
3024ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3025 struct ieee80211_tx_control *ctl)
3026{
3027 struct ath5k_softc *sc = hw->priv;
3028 int ret;
3029
3030 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3031
3032 mutex_lock(&sc->lock);
3033
3034 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3035 ret = -EIO;
3036 goto end;
3037 }
3038
3039 ath5k_txbuf_free(sc, sc->bbuf);
3040 sc->bbuf->skb = skb;
3041 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3042 if (ret)
3043 sc->bbuf->skb = NULL;
3044 else
3045 ath5k_beacon_config(sc);
3046
3047end:
3048 mutex_unlock(&sc->lock);
3049 return ret;
3050}
3051
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