[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / debug.c

/*
 * Copyright (c) 2007-2008 Bruno Randolf <bruno@thinktube.com>
 *
 *  This file is free software: you may copy, redistribute and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation, either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  This file is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 * This file incorporates work covered by the following copyright and
 * permission notice:
 *
 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
 * Copyright (c) 2004-2005 Atheros Communications, Inc.
 * Copyright (c) 2006 Devicescape Software, Inc.
 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
 *    redistribution must be conditioned upon including a substantially
 *    similar Disclaimer requirement for further binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGES.
 */

#include "base.h"
#include "debug.h"

static unsigned int ath5k_debug;
module_param_named(debug, ath5k_debug, uint, 0);


#ifdef CONFIG_ATH5K_DEBUG

#include <linux/seq_file.h>
#include "reg.h"

static struct dentry *ath5k_global_debugfs;

static int ath5k_debugfs_open(struct inode *inode, struct file *file)
{
	file->private_data = inode->i_private;
	return 0;
}


/* debugfs: registers */

struct reg {
	const char *name;
	int addr;
};

#define REG_STRUCT_INIT(r) { #r, r }

/* just a few random registers, might want to add more */
static const struct reg regs[] = {
	REG_STRUCT_INIT(AR5K_CR),
	REG_STRUCT_INIT(AR5K_RXDP),
	REG_STRUCT_INIT(AR5K_CFG),
	REG_STRUCT_INIT(AR5K_IER),
	REG_STRUCT_INIT(AR5K_BCR),
	REG_STRUCT_INIT(AR5K_RTSD0),
	REG_STRUCT_INIT(AR5K_RTSD1),
	REG_STRUCT_INIT(AR5K_TXCFG),
	REG_STRUCT_INIT(AR5K_RXCFG),
	REG_STRUCT_INIT(AR5K_RXJLA),
	REG_STRUCT_INIT(AR5K_MIBC),
	REG_STRUCT_INIT(AR5K_TOPS),
	REG_STRUCT_INIT(AR5K_RXNOFRM),
	REG_STRUCT_INIT(AR5K_TXNOFRM),
	REG_STRUCT_INIT(AR5K_RPGTO),
	REG_STRUCT_INIT(AR5K_RFCNT),
	REG_STRUCT_INIT(AR5K_MISC),
	REG_STRUCT_INIT(AR5K_QCUDCU_CLKGT),
	REG_STRUCT_INIT(AR5K_ISR),
	REG_STRUCT_INIT(AR5K_PISR),
	REG_STRUCT_INIT(AR5K_SISR0),
	REG_STRUCT_INIT(AR5K_SISR1),
	REG_STRUCT_INIT(AR5K_SISR2),
	REG_STRUCT_INIT(AR5K_SISR3),
	REG_STRUCT_INIT(AR5K_SISR4),
	REG_STRUCT_INIT(AR5K_IMR),
	REG_STRUCT_INIT(AR5K_PIMR),
	REG_STRUCT_INIT(AR5K_SIMR0),
	REG_STRUCT_INIT(AR5K_SIMR1),
	REG_STRUCT_INIT(AR5K_SIMR2),
	REG_STRUCT_INIT(AR5K_SIMR3),
	REG_STRUCT_INIT(AR5K_SIMR4),
	REG_STRUCT_INIT(AR5K_DCM_ADDR),
	REG_STRUCT_INIT(AR5K_DCCFG),
	REG_STRUCT_INIT(AR5K_CCFG),
	REG_STRUCT_INIT(AR5K_CPC0),
	REG_STRUCT_INIT(AR5K_CPC1),
	REG_STRUCT_INIT(AR5K_CPC2),
	REG_STRUCT_INIT(AR5K_CPC3),
	REG_STRUCT_INIT(AR5K_CPCOVF),
	REG_STRUCT_INIT(AR5K_RESET_CTL),
	REG_STRUCT_INIT(AR5K_SLEEP_CTL),
	REG_STRUCT_INIT(AR5K_INTPEND),
	REG_STRUCT_INIT(AR5K_SFR),
	REG_STRUCT_INIT(AR5K_PCICFG),
	REG_STRUCT_INIT(AR5K_GPIOCR),
	REG_STRUCT_INIT(AR5K_GPIODO),
	REG_STRUCT_INIT(AR5K_SREV),
};

static void *reg_start(struct seq_file *seq, loff_t *pos)
{
	return *pos < ARRAY_SIZE(regs) ? (void *)&regs[*pos] : NULL;
}

static void reg_stop(struct seq_file *seq, void *p)
{
	/* nothing to do */
}

static void *reg_next(struct seq_file *seq, void *p, loff_t *pos)
{
	++*pos;
	return *pos < ARRAY_SIZE(regs) ? (void *)&regs[*pos] : NULL;
}

static int reg_show(struct seq_file *seq, void *p)
{
	struct ath5k_softc *sc = seq->private;
	struct reg *r = p;
	seq_printf(seq, "%-25s0x%08x\n", r->name,
		ath5k_hw_reg_read(sc->ah, r->addr));
	return 0;
}

static const struct seq_operations register_seq_ops = {
	.start = reg_start,
	.next  = reg_next,
	.stop  = reg_stop,
	.show  = reg_show
};

static int open_file_registers(struct inode *inode, struct file *file)
{
	struct seq_file *s;
	int res;
	res = seq_open(file, &register_seq_ops);
	if (res == 0) {
		s = file->private_data;
		s->private = inode->i_private;
	}
	return res;
}

static const struct file_operations fops_registers = {
	.open = open_file_registers,
	.read    = seq_read,
	.llseek  = seq_lseek,
	.release = seq_release,
	.owner = THIS_MODULE,
};


/* debugfs: beacons */

static ssize_t read_file_beacon(struct file *file, char __user *user_buf,
				   size_t count, loff_t *ppos)
{
	struct ath5k_softc *sc = file->private_data;
	struct ath5k_hw *ah = sc->ah;
	char buf[500];
	unsigned int len = 0;
	unsigned int v;
	u64 tsf;

	v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON);
	len += snprintf(buf+len, sizeof(buf)-len,
		"%-24s0x%08x\tintval: %d\tTIM: 0x%x\n",
		"AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
		(v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);

	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n",
		"AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP));

	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n\n",
		"AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT));

	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0);
	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
		"AR5K_TIMER0 (TBTT)", v, v);

	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1);
	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
		"AR5K_TIMER1 (DMA)", v, v >> 3);

	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2);
	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
		"AR5K_TIMER2 (SWBA)", v, v >> 3);

	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3);
	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
		"AR5K_TIMER3 (ATIM)", v, v);

	tsf = ath5k_hw_get_tsf64(sc->ah);
	len += snprintf(buf+len, sizeof(buf)-len,
		"TSF\t\t0x%016llx\tTU: %08x\n",
		(unsigned long long)tsf, TSF_TO_TU(tsf));

	return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}

static ssize_t write_file_beacon(struct file *file,
				 const char __user *userbuf,
				 size_t count, loff_t *ppos)
{
	struct ath5k_softc *sc = file->private_data;
	struct ath5k_hw *ah = sc->ah;
	char buf[20];

	if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
		return -EFAULT;

	if (strncmp(buf, "disable", 7) == 0) {
		AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
		printk(KERN_INFO "debugfs disable beacons\n");
	} else if (strncmp(buf, "enable", 6) == 0) {
		AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
		printk(KERN_INFO "debugfs enable beacons\n");
	}
	return count;
}

static const struct file_operations fops_beacon = {
	.read = read_file_beacon,
	.write = write_file_beacon,
	.open = ath5k_debugfs_open,
	.owner = THIS_MODULE,
};


/* debugfs: reset */

static ssize_t write_file_reset(struct file *file,
				 const char __user *userbuf,
				 size_t count, loff_t *ppos)
{
	struct ath5k_softc *sc = file->private_data;
	tasklet_schedule(&sc->restq);
	return count;
}

static const struct file_operations fops_reset = {
	.write = write_file_reset,
	.open = ath5k_debugfs_open,
	.owner = THIS_MODULE,
};


/* debugfs: debug level */

static const struct {
	enum ath5k_debug_level level;
	const char *name;
	const char *desc;
} dbg_info[] = {
	{ ATH5K_DEBUG_RESET,	"reset",	"reset and initialization" },
	{ ATH5K_DEBUG_INTR,	"intr",		"interrupt handling" },
	{ ATH5K_DEBUG_MODE,	"mode",		"mode init/setup" },
	{ ATH5K_DEBUG_XMIT,	"xmit",		"basic xmit operation" },
	{ ATH5K_DEBUG_BEACON,	"beacon",	"beacon handling" },
	{ ATH5K_DEBUG_CALIBRATE, "calib",	"periodic calibration" },
	{ ATH5K_DEBUG_TXPOWER,	"txpower",	"transmit power setting" },
	{ ATH5K_DEBUG_LED,	"led",		"LED management" },
	{ ATH5K_DEBUG_DUMP_RX,	"dumprx",	"print received skb content" },
	{ ATH5K_DEBUG_DUMP_TX,	"dumptx",	"print transmit skb content" },
	{ ATH5K_DEBUG_DUMPBANDS, "dumpbands",	"dump bands" },
	{ ATH5K_DEBUG_TRACE,	"trace",	"trace function calls" },
	{ ATH5K_DEBUG_ANY,	"all",		"show all debug levels" },
};

static ssize_t read_file_debug(struct file *file, char __user *user_buf,
				   size_t count, loff_t *ppos)
{
	struct ath5k_softc *sc = file->private_data;
	char buf[700];
	unsigned int len = 0;
	unsigned int i;

	len += snprintf(buf+len, sizeof(buf)-len,
		"DEBUG LEVEL: 0x%08x\n\n", sc->debug.level);

	for (i = 0; i < ARRAY_SIZE(dbg_info) - 1; i++) {
		len += snprintf(buf+len, sizeof(buf)-len,
			"%10s %c 0x%08x - %s\n", dbg_info[i].name,
			sc->debug.level & dbg_info[i].level ? '+' : ' ',
			dbg_info[i].level, dbg_info[i].desc);
	}
	len += snprintf(buf+len, sizeof(buf)-len,
		"%10s %c 0x%08x - %s\n", dbg_info[i].name,
		sc->debug.level == dbg_info[i].level ? '+' : ' ',
		dbg_info[i].level, dbg_info[i].desc);

	return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}

static ssize_t write_file_debug(struct file *file,
				 const char __user *userbuf,
				 size_t count, loff_t *ppos)
{
	struct ath5k_softc *sc = file->private_data;
	unsigned int i;
	char buf[20];

	if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
		return -EFAULT;

	for (i = 0; i < ARRAY_SIZE(dbg_info); i++) {
		if (strncmp(buf, dbg_info[i].name,
					strlen(dbg_info[i].name)) == 0) {
			sc->debug.level ^= dbg_info[i].level; /* toggle bit */
			break;
		}
	}
	return count;
}

static const struct file_operations fops_debug = {
	.read = read_file_debug,
	.write = write_file_debug,
	.open = ath5k_debugfs_open,
	.owner = THIS_MODULE,
};


/* init */

void
ath5k_debug_init(void)
{
	ath5k_global_debugfs = debugfs_create_dir("ath5k", NULL);
}

void
ath5k_debug_init_device(struct ath5k_softc *sc)
{
	sc->debug.level = ath5k_debug;

	sc->debug.debugfs_phydir = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
				ath5k_global_debugfs);

	sc->debug.debugfs_debug = debugfs_create_file("debug", S_IWUSR | S_IRUGO,
				sc->debug.debugfs_phydir, sc, &fops_debug);

	sc->debug.debugfs_registers = debugfs_create_file("registers", S_IRUGO,
				sc->debug.debugfs_phydir, sc, &fops_registers);

	sc->debug.debugfs_beacon = debugfs_create_file("beacon", S_IWUSR | S_IRUGO,
				sc->debug.debugfs_phydir, sc, &fops_beacon);

	sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR,
				sc->debug.debugfs_phydir, sc, &fops_reset);
}

void
ath5k_debug_finish(void)
{
	debugfs_remove(ath5k_global_debugfs);
}

void
ath5k_debug_finish_device(struct ath5k_softc *sc)
{
	debugfs_remove(sc->debug.debugfs_debug);
	debugfs_remove(sc->debug.debugfs_registers);
	debugfs_remove(sc->debug.debugfs_beacon);
	debugfs_remove(sc->debug.debugfs_reset);
	debugfs_remove(sc->debug.debugfs_phydir);
}


/* functions used in other places */

void
ath5k_debug_dump_bands(struct ath5k_softc *sc)
{
	unsigned int b, i;

	if (likely(!(sc->debug.level & ATH5K_DEBUG_DUMPBANDS)))
		return;

	BUG_ON(!sc->sbands);

	for (b = 0; b < IEEE80211_NUM_BANDS; b++) {
		struct ieee80211_supported_band *band = &sc->sbands[b];
		char bname[5];
		switch (band->band) {
		case IEEE80211_BAND_2GHZ:
			strcpy(bname, "2 GHz");
			break;
		case IEEE80211_BAND_5GHZ:
			strcpy(bname, "5 GHz");
			break;
		default:
			printk(KERN_DEBUG "Band not supported: %d\n",
				band->band);
			return;
		}
		printk(KERN_DEBUG "Band %s: channels %d, rates %d\n", bname,
				band->n_channels, band->n_bitrates);
		printk(KERN_DEBUG " channels:\n");
		for (i = 0; i < band->n_channels; i++)
			printk(KERN_DEBUG "  %3d %d %.4x %.4x\n",
					ieee80211_frequency_to_channel(
						band->channels[i].center_freq),
					band->channels[i].center_freq,
					band->channels[i].hw_value,
					band->channels[i].flags);
		printk(KERN_DEBUG " rates:\n");
		for (i = 0; i < band->n_bitrates; i++)
			printk(KERN_DEBUG "  %4d %.4x %.4x %.4x\n",
					band->bitrates[i].bitrate,
					band->bitrates[i].hw_value,
					band->bitrates[i].flags,
					band->bitrates[i].hw_value_short);
	}
}

static inline void
ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done,
		       struct ath5k_rx_status *rs)
{
	struct ath5k_desc *ds = bf->desc;
	struct ath5k_hw_all_rx_desc *rd = &ds->ud.ds_rx;

	printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
		ds, (unsigned long long)bf->daddr,
		ds->ds_link, ds->ds_data,
		rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1,
		rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0,
		!done ? ' ' : (rs->rs_status == 0) ? '*' : '!');
}

void
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
{
	struct ath5k_desc *ds;
	struct ath5k_buf *bf;
	struct ath5k_rx_status rs = {};
	int status;

	if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
		return;

	printk(KERN_DEBUG "rx queue %x, link %p\n",
		ath5k_hw_get_rxdp(ah), sc->rxlink);

	spin_lock_bh(&sc->rxbuflock);
	list_for_each_entry(bf, &sc->rxbuf, list) {
		ds = bf->desc;
		status = ah->ah_proc_rx_desc(ah, ds, &rs);
		if (!status)
			ath5k_debug_printrxbuf(bf, status == 0, &rs);
	}
	spin_unlock_bh(&sc->rxbuflock);
}

void
ath5k_debug_dump_skb(struct ath5k_softc *sc,
			struct sk_buff *skb, const char *prefix, int tx)
{
	char buf[16];

	if (likely(!((tx && (sc->debug.level & ATH5K_DEBUG_DUMP_TX)) ||
		     (!tx && (sc->debug.level & ATH5K_DEBUG_DUMP_RX)))))
		return;

	snprintf(buf, sizeof(buf), "%s %s", wiphy_name(sc->hw->wiphy), prefix);

	print_hex_dump_bytes(buf, DUMP_PREFIX_NONE, skb->data,
		min(200U, skb->len));

	printk(KERN_DEBUG "\n");
}

void
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf)
{
	struct ath5k_desc *ds = bf->desc;
	struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212;
	struct ath5k_tx_status ts = {};
	int done;

	if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
		return;

	done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts);

	printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
		"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
		ds->ds_data, td->tx_ctl.tx_control_0, td->tx_ctl.tx_control_1,
		td->tx_ctl.tx_control_2, td->tx_ctl.tx_control_3,
		td->tx_stat.tx_status_0, td->tx_stat.tx_status_1,
		done ? ' ' : (ts.ts_status == 0) ? '*' : '!');
}

#endif /* ifdef CONFIG_ATH5K_DEBUG */
Commit	Line	Data
fa1c114f	1	/*
be9b7259	2	* Copyright (c) 2007-2008 Bruno Randolf <bruno@thinktube.com>
fa1c114f JS	3	*
	4	* This file is free software: you may copy, redistribute and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation, either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* This file is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	*
	18	* This file incorporates work covered by the following copyright and
	19	* permission notice:
	20	*
	21	* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
	22	* Copyright (c) 2004-2005 Atheros Communications, Inc.
	23	* Copyright (c) 2006 Devicescape Software, Inc.
	24	* Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
	25	* Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
	26	*
	27	* All rights reserved.
	28	*
	29	* Redistribution and use in source and binary forms, with or without
	30	* modification, are permitted provided that the following conditions
	31	* are met:
	32	* 1. Redistributions of source code must retain the above copyright
	33	* notice, this list of conditions and the following disclaimer,
	34	* without modification.
	35	* 2. Redistributions in binary form must reproduce at minimum a disclaimer
	36	* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
	37	* redistribution must be conditioned upon including a substantially
	38	* similar Disclaimer requirement for further binary redistribution.
	39	* 3. Neither the names of the above-listed copyright holders nor the names
	40	* of any contributors may be used to endorse or promote products derived
	41	* from this software without specific prior written permission.
	42	*
	43	* Alternatively, this software may be distributed under the terms of the
	44	* GNU General Public License ("GPL") version 2 as published by the Free
	45	* Software Foundation.
	46	*
	47	* NO WARRANTY
	48	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	49	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	50	* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
	51	* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
	52	* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
	53	* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	54	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	55	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
	56	* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	57	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	58	* THE POSSIBILITY OF SUCH DAMAGES.
	59	*/
	60
fa1c114f	61	#include "base.h"
c6e387a2	62	#include "debug.h"
fa1c114f JS	63
	64	static unsigned int ath5k_debug;
	65	module_param_named(debug, ath5k_debug, uint, 0);
	66
	67
b446197c	68	#ifdef CONFIG_ATH5K_DEBUG
fa1c114f JS	69
	70	#include <linux/seq_file.h>
	71	#include "reg.h"
	72
	73	static struct dentry *ath5k_global_debugfs;
	74
	75	static int ath5k_debugfs_open(struct inode inode, struct file file)
	76	{
	77	file->private_data = inode->i_private;
	78	return 0;
	79	}
	80
	81
	82	/* debugfs: registers */
	83
	84	struct reg {
2c91108c	85	const char *name;
fa1c114f JS	86	int addr;
	87	};
	88
	89	#define REG_STRUCT_INIT(r) { #r, r }
	90
	91	/* just a few random registers, might want to add more */
2c91108c	92	static const struct reg regs[] = {
fa1c114f JS	93	REG_STRUCT_INIT(AR5K_CR),
	94	REG_STRUCT_INIT(AR5K_RXDP),
	95	REG_STRUCT_INIT(AR5K_CFG),
	96	REG_STRUCT_INIT(AR5K_IER),
	97	REG_STRUCT_INIT(AR5K_BCR),
	98	REG_STRUCT_INIT(AR5K_RTSD0),
	99	REG_STRUCT_INIT(AR5K_RTSD1),
	100	REG_STRUCT_INIT(AR5K_TXCFG),
	101	REG_STRUCT_INIT(AR5K_RXCFG),
	102	REG_STRUCT_INIT(AR5K_RXJLA),
	103	REG_STRUCT_INIT(AR5K_MIBC),
	104	REG_STRUCT_INIT(AR5K_TOPS),
	105	REG_STRUCT_INIT(AR5K_RXNOFRM),
	106	REG_STRUCT_INIT(AR5K_TXNOFRM),
	107	REG_STRUCT_INIT(AR5K_RPGTO),
	108	REG_STRUCT_INIT(AR5K_RFCNT),
	109	REG_STRUCT_INIT(AR5K_MISC),
	110	REG_STRUCT_INIT(AR5K_QCUDCU_CLKGT),
	111	REG_STRUCT_INIT(AR5K_ISR),
	112	REG_STRUCT_INIT(AR5K_PISR),
	113	REG_STRUCT_INIT(AR5K_SISR0),
	114	REG_STRUCT_INIT(AR5K_SISR1),
	115	REG_STRUCT_INIT(AR5K_SISR2),
	116	REG_STRUCT_INIT(AR5K_SISR3),
	117	REG_STRUCT_INIT(AR5K_SISR4),
	118	REG_STRUCT_INIT(AR5K_IMR),
	119	REG_STRUCT_INIT(AR5K_PIMR),
	120	REG_STRUCT_INIT(AR5K_SIMR0),
	121	REG_STRUCT_INIT(AR5K_SIMR1),
	122	REG_STRUCT_INIT(AR5K_SIMR2),
	123	REG_STRUCT_INIT(AR5K_SIMR3),
	124	REG_STRUCT_INIT(AR5K_SIMR4),
	125	REG_STRUCT_INIT(AR5K_DCM_ADDR),
	126	REG_STRUCT_INIT(AR5K_DCCFG),
	127	REG_STRUCT_INIT(AR5K_CCFG),
	128	REG_STRUCT_INIT(AR5K_CPC0),
	129	REG_STRUCT_INIT(AR5K_CPC1),
	130	REG_STRUCT_INIT(AR5K_CPC2),
	131	REG_STRUCT_INIT(AR5K_CPC3),
0bacdf30	132	REG_STRUCT_INIT(AR5K_CPCOVF),
fa1c114f JS	133	REG_STRUCT_INIT(AR5K_RESET_CTL),
	134	REG_STRUCT_INIT(AR5K_SLEEP_CTL),
	135	REG_STRUCT_INIT(AR5K_INTPEND),
	136	REG_STRUCT_INIT(AR5K_SFR),
	137	REG_STRUCT_INIT(AR5K_PCICFG),
	138	REG_STRUCT_INIT(AR5K_GPIOCR),
	139	REG_STRUCT_INIT(AR5K_GPIODO),
	140	REG_STRUCT_INIT(AR5K_SREV),
	141	};
	142
	143	static void reg_start(struct seq_file seq, loff_t *pos)
	144	{
2c91108c	145	return pos < ARRAY_SIZE(regs) ? (void )&regs[*pos] : NULL;
fa1c114f JS	146	}
	147
	148	static void reg_stop(struct seq_file seq, void p)
	149	{
	150	/* nothing to do */
	151	}
	152
	153	static void reg_next(struct seq_file seq, void p, loff_t pos)
	154	{
	155	++*pos;
2c91108c	156	return pos < ARRAY_SIZE(regs) ? (void )&regs[*pos] : NULL;
fa1c114f JS	157	}
	158
	159	static int reg_show(struct seq_file seq, void p)
	160	{
	161	struct ath5k_softc *sc = seq->private;
	162	struct reg *r = p;
	163	seq_printf(seq, "%-25s0x%08x\n", r->name,
	164	ath5k_hw_reg_read(sc->ah, r->addr));
	165	return 0;
	166	}
	167
4101dec9	168	static const struct seq_operations register_seq_ops = {
fa1c114f JS	169	.start = reg_start,
	170	.next = reg_next,
	171	.stop = reg_stop,
	172	.show = reg_show
	173	};
	174
	175	static int open_file_registers(struct inode inode, struct file file)
	176	{
	177	struct seq_file *s;
	178	int res;
	179	res = seq_open(file, &register_seq_ops);
	180	if (res == 0) {
	181	s = file->private_data;
	182	s->private = inode->i_private;
	183	}
	184	return res;
	185	}
	186
	187	static const struct file_operations fops_registers = {
	188	.open = open_file_registers,
	189	.read = seq_read,
	190	.llseek = seq_lseek,
	191	.release = seq_release,
	192	.owner = THIS_MODULE,
	193	};
	194
	195
fa1c114f JS	196	/* debugfs: beacons */
	197
	198	static ssize_t read_file_beacon(struct file file, char __user user_buf,
	199	size_t count, loff_t *ppos)
	200	{
	201	struct ath5k_softc *sc = file->private_data;
	202	struct ath5k_hw *ah = sc->ah;
be9b7259 BR	203	char buf[500];
be9b7259 BR	204	unsigned int len = 0;
fa1c114f JS	205	unsigned int v;
	206	u64 tsf;
	207
	208	v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON);
	209	len += snprintf(buf+len, sizeof(buf)-len,
	210	"%-24s0x%08x\tintval: %d\tTIM: 0x%x\n",
	211	"AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
	212	(v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);
	213
	214	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n",
	215	"AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP));
	216
	217	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n\n",
	218	"AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT));
	219
	220	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0);
	221	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
	222	"AR5K_TIMER0 (TBTT)", v, v);
	223
	224	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1);
	225	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
	226	"AR5K_TIMER1 (DMA)", v, v >> 3);
	227
	228	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2);
	229	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
	230	"AR5K_TIMER2 (SWBA)", v, v >> 3);
	231
	232	v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3);
	233	len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
	234	"AR5K_TIMER3 (ATIM)", v, v);
	235
	236	tsf = ath5k_hw_get_tsf64(sc->ah);
	237	len += snprintf(buf+len, sizeof(buf)-len,
f868f4e1 JL	238	"TSF\t\t0x%016llx\tTU: %08x\n",
f868f4e1 JL	239	(unsigned long long)tsf, TSF_TO_TU(tsf));
fa1c114f JS	240
	241	return simple_read_from_buffer(user_buf, count, ppos, buf, len);
	242	}
	243
	244	static ssize_t write_file_beacon(struct file *file,
	245	const char __user *userbuf,
	246	size_t count, loff_t *ppos)
	247	{
	248	struct ath5k_softc *sc = file->private_data;
	249	struct ath5k_hw *ah = sc->ah;
be9b7259	250	char buf[20];
fa1c114f	251
be9b7259 BR	252	if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
	253	return -EFAULT;
	254
	255	if (strncmp(buf, "disable", 7) == 0) {
fa1c114f JS	256	AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
fa1c114f JS	257	printk(KERN_INFO "debugfs disable beacons\n");
be9b7259	258	} else if (strncmp(buf, "enable", 6) == 0) {
fa1c114f JS	259	AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
	260	printk(KERN_INFO "debugfs enable beacons\n");
	261	}
	262	return count;
	263	}
	264
	265	static const struct file_operations fops_beacon = {
	266	.read = read_file_beacon,
	267	.write = write_file_beacon,
	268	.open = ath5k_debugfs_open,
	269	.owner = THIS_MODULE,
	270	};
	271
	272
	273	/* debugfs: reset */
	274
	275	static ssize_t write_file_reset(struct file *file,
	276	const char __user *userbuf,
	277	size_t count, loff_t *ppos)
	278	{
	279	struct ath5k_softc *sc = file->private_data;
	280	tasklet_schedule(&sc->restq);
	281	return count;
	282	}
	283
	284	static const struct file_operations fops_reset = {
	285	.write = write_file_reset,
	286	.open = ath5k_debugfs_open,
	287	.owner = THIS_MODULE,
	288	};
	289
	290
be9b7259 BR	291	/* debugfs: debug level */
be9b7259 BR	292
2c91108c	293	static const struct {
be9b7259 BR	294	enum ath5k_debug_level level;
	295	const char *name;
	296	const char *desc;
	297	} dbg_info[] = {
	298	{ ATH5K_DEBUG_RESET, "reset", "reset and initialization" },
	299	{ ATH5K_DEBUG_INTR, "intr", "interrupt handling" },
	300	{ ATH5K_DEBUG_MODE, "mode", "mode init/setup" },
	301	{ ATH5K_DEBUG_XMIT, "xmit", "basic xmit operation" },
	302	{ ATH5K_DEBUG_BEACON, "beacon", "beacon handling" },
	303	{ ATH5K_DEBUG_CALIBRATE, "calib", "periodic calibration" },
	304	{ ATH5K_DEBUG_TXPOWER, "txpower", "transmit power setting" },
85519a65	305	{ ATH5K_DEBUG_LED, "led", "LED management" },
be9b7259 BR	306	{ ATH5K_DEBUG_DUMP_RX, "dumprx", "print received skb content" },
be9b7259 BR	307	{ ATH5K_DEBUG_DUMP_TX, "dumptx", "print transmit skb content" },
b446197c	308	{ ATH5K_DEBUG_DUMPBANDS, "dumpbands", "dump bands" },
be9b7259 BR	309	{ ATH5K_DEBUG_TRACE, "trace", "trace function calls" },
	310	{ ATH5K_DEBUG_ANY, "all", "show all debug levels" },
	311	};
	312
	313	static ssize_t read_file_debug(struct file file, char __user user_buf,
	314	size_t count, loff_t *ppos)
	315	{
	316	struct ath5k_softc *sc = file->private_data;
	317	char buf[700];
	318	unsigned int len = 0;
	319	unsigned int i;
	320
	321	len += snprintf(buf+len, sizeof(buf)-len,
	322	"DEBUG LEVEL: 0x%08x\n\n", sc->debug.level);
	323
	324	for (i = 0; i < ARRAY_SIZE(dbg_info) - 1; i++) {
	325	len += snprintf(buf+len, sizeof(buf)-len,
	326	"%10s %c 0x%08x - %s\n", dbg_info[i].name,
	327	sc->debug.level & dbg_info[i].level ? '+' : ' ',
	328	dbg_info[i].level, dbg_info[i].desc);
	329	}
	330	len += snprintf(buf+len, sizeof(buf)-len,
	331	"%10s %c 0x%08x - %s\n", dbg_info[i].name,
	332	sc->debug.level == dbg_info[i].level ? '+' : ' ',
	333	dbg_info[i].level, dbg_info[i].desc);
	334
	335	return simple_read_from_buffer(user_buf, count, ppos, buf, len);
	336	}
	337
	338	static ssize_t write_file_debug(struct file *file,
	339	const char __user *userbuf,
	340	size_t count, loff_t *ppos)
	341	{
	342	struct ath5k_softc *sc = file->private_data;
	343	unsigned int i;
	344	char buf[20];
	345
	346	if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
	347	return -EFAULT;
	348
	349	for (i = 0; i < ARRAY_SIZE(dbg_info); i++) {
	350	if (strncmp(buf, dbg_info[i].name,
	351	strlen(dbg_info[i].name)) == 0) {
	352	sc->debug.level ^= dbg_info[i].level; /* toggle bit */
	353	break;
	354	}
	355	}
	356	return count;
	357	}
	358
	359	static const struct file_operations fops_debug = {
	360	.read = read_file_debug,
	361	.write = write_file_debug,
	362	.open = ath5k_debugfs_open,
	363	.owner = THIS_MODULE,
	364	};
	365
	366
fa1c114f JS	367	/* init */
	368
	369	void
	370	ath5k_debug_init(void)
	371	{
	372	ath5k_global_debugfs = debugfs_create_dir("ath5k", NULL);
	373	}
	374
	375	void
	376	ath5k_debug_init_device(struct ath5k_softc *sc)
	377	{
	378	sc->debug.level = ath5k_debug;
be9b7259	379
fa1c114f	380	sc->debug.debugfs_phydir = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
be9b7259 BR	381	ath5k_global_debugfs);
be9b7259 BR	382
33ab625f	383	sc->debug.debugfs_debug = debugfs_create_file("debug", S_IWUSR \| S_IRUGO,
be9b7259	384	sc->debug.debugfs_phydir, sc, &fops_debug);
fa1c114f	385
33ab625f	386	sc->debug.debugfs_registers = debugfs_create_file("registers", S_IRUGO,
be9b7259	387	sc->debug.debugfs_phydir, sc, &fops_registers);
fa1c114f	388
33ab625f	389	sc->debug.debugfs_beacon = debugfs_create_file("beacon", S_IWUSR \| S_IRUGO,
be9b7259	390	sc->debug.debugfs_phydir, sc, &fops_beacon);
fa1c114f	391
33ab625f	392	sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR,
be9b7259	393	sc->debug.debugfs_phydir, sc, &fops_reset);
fa1c114f JS	394	}
	395
	396	void
	397	ath5k_debug_finish(void)
	398	{
	399	debugfs_remove(ath5k_global_debugfs);
	400	}
	401
	402	void
	403	ath5k_debug_finish_device(struct ath5k_softc *sc)
	404	{
	405	debugfs_remove(sc->debug.debugfs_debug);
	406	debugfs_remove(sc->debug.debugfs_registers);
fa1c114f JS	407	debugfs_remove(sc->debug.debugfs_beacon);
	408	debugfs_remove(sc->debug.debugfs_reset);
	409	debugfs_remove(sc->debug.debugfs_phydir);
	410	}
	411
	412
	413	/* functions used in other places */
	414
	415	void
b446197c	416	ath5k_debug_dump_bands(struct ath5k_softc *sc)
fa1c114f	417	{
b446197c	418	unsigned int b, i;
fa1c114f	419
b446197c	420	if (likely(!(sc->debug.level & ATH5K_DEBUG_DUMPBANDS)))
fa1c114f JS	421	return;
fa1c114f JS	422
b446197c LR	423	BUG_ON(!sc->sbands);
	424
	425	for (b = 0; b < IEEE80211_NUM_BANDS; b++) {
	426	struct ieee80211_supported_band *band = &sc->sbands[b];
	427	char bname[5];
	428	switch (band->band) {
	429	case IEEE80211_BAND_2GHZ:
	430	strcpy(bname, "2 GHz");
	431	break;
	432	case IEEE80211_BAND_5GHZ:
	433	strcpy(bname, "5 GHz");
	434	break;
	435	default:
	436	printk(KERN_DEBUG "Band not supported: %d\n",
	437	band->band);
	438	return;
	439	}
	440	printk(KERN_DEBUG "Band %s: channels %d, rates %d\n", bname,
	441	band->n_channels, band->n_bitrates);
fa1c114f	442	printk(KERN_DEBUG " channels:\n");
b446197c	443	for (i = 0; i < band->n_channels; i++)
fa1c114f	444	printk(KERN_DEBUG " %3d %d %.4x %.4x\n",
b446197c LR	445	ieee80211_frequency_to_channel(
	446	band->channels[i].center_freq),
	447	band->channels[i].center_freq,
	448	band->channels[i].hw_value,
	449	band->channels[i].flags);
fa1c114f	450	printk(KERN_DEBUG " rates:\n");
b446197c	451	for (i = 0; i < band->n_bitrates; i++)
fa1c114f	452	printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n",
b446197c LR	453	band->bitrates[i].bitrate,
	454	band->bitrates[i].hw_value,
	455	band->bitrates[i].flags,
	456	band->bitrates[i].hw_value_short);
fa1c114f JS	457	}
	458	}
	459
	460	static inline void
b47f407b BR	461	ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done,
b47f407b BR	462	struct ath5k_rx_status *rs)
fa1c114f JS	463	{
fa1c114f JS	464	struct ath5k_desc *ds = bf->desc;
19fd6e55	465	struct ath5k_hw_all_rx_desc *rd = &ds->ud.ds_rx;
fa1c114f JS	466
	467	printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
	468	ds, (unsigned long long)bf->daddr,
19fd6e55 BR	469	ds->ds_link, ds->ds_data,
	470	rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1,
	471	rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0,
b47f407b	472	!done ? ' ' : (rs->rs_status == 0) ? '*' : '!');
fa1c114f JS	473	}
	474
	475	void
	476	ath5k_debug_printrxbuffs(struct ath5k_softc sc, struct ath5k_hw ah)
	477	{
	478	struct ath5k_desc *ds;
	479	struct ath5k_buf *bf;
b47f407b	480	struct ath5k_rx_status rs = {};
fa1c114f JS	481	int status;
fa1c114f JS	482
be9b7259	483	if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
fa1c114f JS	484	return;
	485
	486	printk(KERN_DEBUG "rx queue %x, link %p\n",
c6e387a2	487	ath5k_hw_get_rxdp(ah), sc->rxlink);
fa1c114f JS	488
	489	spin_lock_bh(&sc->rxbuflock);
	490	list_for_each_entry(bf, &sc->rxbuf, list) {
	491	ds = bf->desc;
b47f407b	492	status = ah->ah_proc_rx_desc(ah, ds, &rs);
be9b7259	493	if (!status)
b47f407b	494	ath5k_debug_printrxbuf(bf, status == 0, &rs);
fa1c114f JS	495	}
	496	spin_unlock_bh(&sc->rxbuflock);
	497	}
	498
	499	void
	500	ath5k_debug_dump_skb(struct ath5k_softc *sc,
	501	struct sk_buff skb, const char prefix, int tx)
	502	{
	503	char buf[16];
	504
	505	if (likely(!((tx && (sc->debug.level & ATH5K_DEBUG_DUMP_TX)) \|\|
	506	(!tx && (sc->debug.level & ATH5K_DEBUG_DUMP_RX)))))
	507	return;
	508
	509	snprintf(buf, sizeof(buf), "%s %s", wiphy_name(sc->hw->wiphy), prefix);
	510
	511	print_hex_dump_bytes(buf, DUMP_PREFIX_NONE, skb->data,
	512	min(200U, skb->len));
	513
	514	printk(KERN_DEBUG "\n");
	515	}
	516
	517	void
b47f407b	518	ath5k_debug_printtxbuf(struct ath5k_softc sc, struct ath5k_buf bf)
fa1c114f JS	519	{
fa1c114f JS	520	struct ath5k_desc *ds = bf->desc;
19fd6e55	521	struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212;
b47f407b BR	522	struct ath5k_tx_status ts = {};
b47f407b BR	523	int done;
fa1c114f JS	524
	525	if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
	526	return;
	527
b47f407b BR	528	done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts);
b47f407b BR	529
fa1c114f JS	530	printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
fa1c114f JS	531	"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
19fd6e55 BR	532	ds->ds_data, td->tx_ctl.tx_control_0, td->tx_ctl.tx_control_1,
	533	td->tx_ctl.tx_control_2, td->tx_ctl.tx_control_3,
	534	td->tx_stat.tx_status_0, td->tx_stat.tx_status_1,
b47f407b	535	done ? ' ' : (ts.ts_status == 0) ? '*' : '!');
fa1c114f JS	536	}
fa1c114f JS	537
b446197c	538	#endif /* ifdef CONFIG_ATH5K_DEBUG */