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1 | /* |
2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * | |
5 | * Permission to use, copy, modify, and distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | * | |
17 | */ | |
18 | ||
19 | /* | |
20 | * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) | |
21 | */ | |
22 | #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ | |
23 | #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ | |
24 | #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ | |
25 | #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ | |
26 | #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ | |
27 | ||
28 | #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ | |
29 | #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ | |
30 | #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ | |
31 | #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ | |
32 | #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 | |
33 | #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ | |
34 | #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 | |
35 | #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ | |
36 | #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 | |
37 | #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ | |
38 | #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 | |
39 | #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ | |
40 | #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 | |
41 | #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ | |
42 | #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 | |
43 | #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ | |
44 | #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 | |
45 | #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ | |
46 | #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ | |
47 | #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) | |
48 | #define AR5K_EEPROM_INFO_CKSUM 0xffff | |
49 | #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) | |
50 | ||
51 | #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ | |
52 | #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ | |
53 | #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ | |
54 | #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ | |
55 | #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ | |
56 | #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */ | |
57 | #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ | |
58 | #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ | |
59 | #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ | |
60 | #define AR5K_EEPROM_VERSION_4_3 0x4003 | |
61 | #define AR5K_EEPROM_VERSION_4_4 0x4004 | |
62 | #define AR5K_EEPROM_VERSION_4_5 0x4005 | |
63 | #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ | |
64 | #define AR5K_EEPROM_VERSION_4_7 0x4007 | |
65 | ||
66 | #define AR5K_EEPROM_MODE_11A 0 | |
67 | #define AR5K_EEPROM_MODE_11B 1 | |
68 | #define AR5K_EEPROM_MODE_11G 2 | |
69 | ||
70 | #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ | |
71 | #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) | |
72 | #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) | |
73 | #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) | |
74 | #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ | |
75 | #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ | |
76 | #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) | |
77 | #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */ | |
78 | #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ | |
79 | ||
80 | #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c | |
81 | #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 | |
82 | #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 | |
83 | #define AR5K_EEPROM_RFKILL_POLARITY_S 1 | |
84 | ||
85 | /* Newer EEPROMs are using a different offset */ | |
86 | #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ | |
87 | (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) | |
88 | ||
89 | #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) | |
90 | #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) | |
91 | #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) | |
92 | ||
93 | /* calibration settings */ | |
94 | #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) | |
95 | #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) | |
96 | #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) | |
97 | #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ | |
98 | ||
99 | /* [3.1 - 3.3] */ | |
100 | #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec | |
101 | #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed | |
102 | ||
103 | /* Misc values available since EEPROM 4.0 */ | |
104 | #define AR5K_EEPROM_MISC0 0x00c4 | |
105 | #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) | |
106 | #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) | |
107 | #define AR5K_EEPROM_MISC1 0x00c5 | |
108 | #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) | |
109 | #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) | |
110 | ||
111 | ||
112 | /* Some EEPROM defines */ | |
113 | #define AR5K_EEPROM_EEP_SCALE 100 | |
114 | #define AR5K_EEPROM_EEP_DELTA 10 | |
115 | #define AR5K_EEPROM_N_MODES 3 | |
116 | #define AR5K_EEPROM_N_5GHZ_CHAN 10 | |
117 | #define AR5K_EEPROM_N_2GHZ_CHAN 3 | |
118 | #define AR5K_EEPROM_MAX_CHAN 10 | |
119 | #define AR5K_EEPROM_N_PCDAC 11 | |
120 | #define AR5K_EEPROM_N_TEST_FREQ 8 | |
121 | #define AR5K_EEPROM_N_EDGES 8 | |
122 | #define AR5K_EEPROM_N_INTERCEPTS 11 | |
123 | #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) | |
124 | #define AR5K_EEPROM_PCDAC_M 0x3f | |
125 | #define AR5K_EEPROM_PCDAC_START 1 | |
126 | #define AR5K_EEPROM_PCDAC_STOP 63 | |
127 | #define AR5K_EEPROM_PCDAC_STEP 1 | |
128 | #define AR5K_EEPROM_NON_EDGE_M 0x40 | |
129 | #define AR5K_EEPROM_CHANNEL_POWER 8 | |
130 | #define AR5K_EEPROM_N_OBDB 4 | |
131 | #define AR5K_EEPROM_OBDB_DIS 0xffff | |
132 | #define AR5K_EEPROM_CHANNEL_DIS 0xff | |
133 | #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) | |
134 | #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) | |
135 | #define AR5K_EEPROM_MAX_CTLS 32 | |
136 | #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 | |
137 | #define AR5K_EEPROM_N_XPD0_POINTS 4 | |
138 | #define AR5K_EEPROM_N_XPD3_POINTS 3 | |
139 | #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 | |
140 | #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 | |
141 | #define AR5K_EEPROM_POWER_M 0x3f | |
142 | #define AR5K_EEPROM_POWER_MIN 0 | |
143 | #define AR5K_EEPROM_POWER_MAX 3150 | |
144 | #define AR5K_EEPROM_POWER_STEP 50 | |
145 | #define AR5K_EEPROM_POWER_TABLE_SIZE 64 | |
146 | #define AR5K_EEPROM_N_POWER_LOC_11B 4 | |
147 | #define AR5K_EEPROM_N_POWER_LOC_11G 6 | |
148 | #define AR5K_EEPROM_I_GAIN 10 | |
149 | #define AR5K_EEPROM_CCK_OFDM_DELTA 15 | |
150 | #define AR5K_EEPROM_N_IQ_CAL 2 | |
151 | ||
152 | #define AR5K_EEPROM_READ(_o, _v) do { \ | |
153 | ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \ | |
154 | if (ret) \ | |
155 | return ret; \ | |
156 | } while (0) | |
157 | ||
158 | #define AR5K_EEPROM_READ_HDR(_o, _v) \ | |
159 | AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ | |
160 | ||
161 | /* Struct to hold EEPROM calibration data */ | |
162 | struct ath5k_eeprom_info { | |
163 | u16 ee_magic; | |
164 | u16 ee_protect; | |
165 | u16 ee_regdomain; | |
166 | u16 ee_version; | |
167 | u16 ee_header; | |
168 | u16 ee_ant_gain; | |
169 | u16 ee_misc0; | |
170 | u16 ee_misc1; | |
171 | u16 ee_cck_ofdm_gain_delta; | |
172 | u16 ee_cck_ofdm_power_delta; | |
173 | u16 ee_scaled_cck_delta; | |
174 | ||
175 | /* Used for tx thermal adjustment (eeprom_init, rfregs) */ | |
176 | u16 ee_tx_clip; | |
177 | u16 ee_pwd_84; | |
178 | u16 ee_pwd_90; | |
179 | u16 ee_gain_select; | |
180 | ||
181 | /* RF Calibration settings (reset, rfregs) */ | |
182 | u16 ee_i_cal[AR5K_EEPROM_N_MODES]; | |
183 | u16 ee_q_cal[AR5K_EEPROM_N_MODES]; | |
184 | u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; | |
185 | u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; | |
186 | u16 ee_xr_power[AR5K_EEPROM_N_MODES]; | |
187 | u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; | |
188 | u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; | |
189 | u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; | |
190 | u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; | |
191 | u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; | |
192 | u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; | |
193 | u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; | |
194 | u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; | |
195 | u16 ee_thr_62[AR5K_EEPROM_N_MODES]; | |
196 | u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; | |
197 | u16 ee_xpd[AR5K_EEPROM_N_MODES]; | |
198 | u16 ee_x_gain[AR5K_EEPROM_N_MODES]; | |
199 | u16 ee_i_gain[AR5K_EEPROM_N_MODES]; | |
200 | u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; | |
201 | ||
202 | /* Unused */ | |
203 | u16 ee_false_detect[AR5K_EEPROM_N_MODES]; | |
204 | u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; | |
205 | u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; /*empty*/ | |
206 | ||
207 | /* Conformance test limits (Unused) */ | |
208 | u16 ee_ctls; | |
209 | u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; | |
210 | ||
211 | /* Noise Floor Calibration settings */ | |
212 | s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; | |
213 | s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; | |
214 | s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; | |
215 | }; |