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fa1c114f JS |
1 | /* |
2 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org> | |
5 | * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu> | |
6 | * | |
7 | * Permission to use, copy, modify, and distribute this software for any | |
8 | * purpose with or without fee is hereby granted, provided that the above | |
9 | * copyright notice and this permission notice appear in all copies. | |
10 | * | |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | ||
22 | /* | |
23 | * Gain settings | |
24 | */ | |
25 | ||
26 | enum ath5k_rfgain { | |
27 | AR5K_RFGAIN_INACTIVE = 0, | |
28 | AR5K_RFGAIN_READ_REQUESTED, | |
29 | AR5K_RFGAIN_NEED_CHANGE, | |
30 | }; | |
31 | ||
32 | #define AR5K_GAIN_CRN_FIX_BITS_5111 4 | |
33 | #define AR5K_GAIN_CRN_FIX_BITS_5112 7 | |
34 | #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 | |
35 | #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 | |
36 | #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 | |
37 | #define AR5K_GAIN_CCK_PROBE_CORR 5 | |
38 | #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 | |
39 | #define AR5K_GAIN_STEP_COUNT 10 | |
40 | #define AR5K_GAIN_PARAM_TX_CLIP 0 | |
41 | #define AR5K_GAIN_PARAM_PD_90 1 | |
42 | #define AR5K_GAIN_PARAM_PD_84 2 | |
43 | #define AR5K_GAIN_PARAM_GAIN_SEL 3 | |
44 | #define AR5K_GAIN_PARAM_MIX_ORN 0 | |
45 | #define AR5K_GAIN_PARAM_PD_138 1 | |
46 | #define AR5K_GAIN_PARAM_PD_137 2 | |
47 | #define AR5K_GAIN_PARAM_PD_136 3 | |
48 | #define AR5K_GAIN_PARAM_PD_132 4 | |
49 | #define AR5K_GAIN_PARAM_PD_131 5 | |
50 | #define AR5K_GAIN_PARAM_PD_130 6 | |
51 | #define AR5K_GAIN_CHECK_ADJUST(_g) \ | |
52 | ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) | |
53 | ||
54 | struct ath5k_gain_opt_step { | |
55 | s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; | |
56 | s32 gos_gain; | |
57 | }; | |
58 | ||
59 | struct ath5k_gain { | |
60 | u32 g_step_idx; | |
61 | u32 g_current; | |
62 | u32 g_target; | |
63 | u32 g_low; | |
64 | u32 g_high; | |
65 | u32 g_f_corr; | |
66 | u32 g_active; | |
67 | const struct ath5k_gain_opt_step *g_step; | |
68 | }; | |
69 | ||
70 | ||
71 | /* | |
72 | * HW SPECIFIC STRUCTS | |
73 | */ | |
74 | ||
75 | /* Some EEPROM defines */ | |
76 | #define AR5K_EEPROM_EEP_SCALE 100 | |
77 | #define AR5K_EEPROM_EEP_DELTA 10 | |
78 | #define AR5K_EEPROM_N_MODES 3 | |
79 | #define AR5K_EEPROM_N_5GHZ_CHAN 10 | |
80 | #define AR5K_EEPROM_N_2GHZ_CHAN 3 | |
81 | #define AR5K_EEPROM_MAX_CHAN 10 | |
82 | #define AR5K_EEPROM_N_PCDAC 11 | |
83 | #define AR5K_EEPROM_N_TEST_FREQ 8 | |
84 | #define AR5K_EEPROM_N_EDGES 8 | |
85 | #define AR5K_EEPROM_N_INTERCEPTS 11 | |
86 | #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) | |
87 | #define AR5K_EEPROM_PCDAC_M 0x3f | |
88 | #define AR5K_EEPROM_PCDAC_START 1 | |
89 | #define AR5K_EEPROM_PCDAC_STOP 63 | |
90 | #define AR5K_EEPROM_PCDAC_STEP 1 | |
91 | #define AR5K_EEPROM_NON_EDGE_M 0x40 | |
92 | #define AR5K_EEPROM_CHANNEL_POWER 8 | |
93 | #define AR5K_EEPROM_N_OBDB 4 | |
94 | #define AR5K_EEPROM_OBDB_DIS 0xffff | |
95 | #define AR5K_EEPROM_CHANNEL_DIS 0xff | |
96 | #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) | |
97 | #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) | |
98 | #define AR5K_EEPROM_MAX_CTLS 32 | |
99 | #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 | |
100 | #define AR5K_EEPROM_N_XPD0_POINTS 4 | |
101 | #define AR5K_EEPROM_N_XPD3_POINTS 3 | |
102 | #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 | |
103 | #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 | |
104 | #define AR5K_EEPROM_POWER_M 0x3f | |
105 | #define AR5K_EEPROM_POWER_MIN 0 | |
106 | #define AR5K_EEPROM_POWER_MAX 3150 | |
107 | #define AR5K_EEPROM_POWER_STEP 50 | |
108 | #define AR5K_EEPROM_POWER_TABLE_SIZE 64 | |
109 | #define AR5K_EEPROM_N_POWER_LOC_11B 4 | |
110 | #define AR5K_EEPROM_N_POWER_LOC_11G 6 | |
111 | #define AR5K_EEPROM_I_GAIN 10 | |
112 | #define AR5K_EEPROM_CCK_OFDM_DELTA 15 | |
113 | #define AR5K_EEPROM_N_IQ_CAL 2 | |
114 | ||
115 | /* Struct to hold EEPROM calibration data */ | |
116 | struct ath5k_eeprom_info { | |
117 | u16 ee_magic; | |
118 | u16 ee_protect; | |
119 | u16 ee_regdomain; | |
120 | u16 ee_version; | |
121 | u16 ee_header; | |
122 | u16 ee_ant_gain; | |
123 | u16 ee_misc0; | |
124 | u16 ee_misc1; | |
125 | u16 ee_cck_ofdm_gain_delta; | |
126 | u16 ee_cck_ofdm_power_delta; | |
127 | u16 ee_scaled_cck_delta; | |
128 | ||
129 | /* Used for tx thermal adjustment (eeprom_init, rfregs) */ | |
130 | u16 ee_tx_clip; | |
131 | u16 ee_pwd_84; | |
132 | u16 ee_pwd_90; | |
133 | u16 ee_gain_select; | |
134 | ||
135 | /* RF Calibration settings (reset, rfregs) */ | |
136 | u16 ee_i_cal[AR5K_EEPROM_N_MODES]; | |
137 | u16 ee_q_cal[AR5K_EEPROM_N_MODES]; | |
138 | u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; | |
139 | u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; | |
140 | u16 ee_xr_power[AR5K_EEPROM_N_MODES]; | |
141 | u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; | |
142 | u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; | |
143 | u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; | |
144 | u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; | |
145 | u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; | |
146 | u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; | |
147 | u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; | |
148 | u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; | |
149 | u16 ee_thr_62[AR5K_EEPROM_N_MODES]; | |
150 | u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; | |
151 | u16 ee_xpd[AR5K_EEPROM_N_MODES]; | |
152 | u16 ee_x_gain[AR5K_EEPROM_N_MODES]; | |
153 | u16 ee_i_gain[AR5K_EEPROM_N_MODES]; | |
154 | u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; | |
155 | ||
156 | /* Unused */ | |
157 | u16 ee_false_detect[AR5K_EEPROM_N_MODES]; | |
158 | u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; | |
159 | u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; /*empty*/ | |
160 | ||
161 | /* Conformance test limits (Unused) */ | |
162 | u16 ee_ctls; | |
163 | u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; | |
164 | ||
165 | /* Noise Floor Calibration settings */ | |
166 | s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; | |
167 | s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; | |
168 | s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; | |
169 | }; | |
170 | ||
171 | /* | |
172 | * Internal RX/TX descriptor structures | |
173 | * (rX: reserved fields possibily used by future versions of the ar5k chipset) | |
174 | */ | |
175 | ||
19fd6e55 BR |
176 | /* |
177 | * common hardware RX control descriptor | |
178 | */ | |
179 | struct ath5k_hw_rx_ctl { | |
fa1c114f JS |
180 | u32 rx_control_0; /* RX control word 0 */ |
181 | ||
182 | #define AR5K_DESC_RX_CTL0 0x00000000 | |
183 | ||
184 | u32 rx_control_1; /* RX control word 1 */ | |
185 | ||
186 | #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff | |
187 | #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 | |
188 | } __packed; | |
189 | ||
190 | /* | |
19fd6e55 BR |
191 | * common hardware RX status descriptor |
192 | * 5210/11 and 5212 differ only in the flags defined below | |
fa1c114f | 193 | */ |
19fd6e55 | 194 | struct ath5k_hw_rx_status { |
fa1c114f | 195 | u32 rx_status_0; /* RX status word 0 */ |
fa1c114f | 196 | u32 rx_status_1; /* RX status word 1 */ |
fa1c114f JS |
197 | } __packed; |
198 | ||
19fd6e55 BR |
199 | /* 5210/5211 */ |
200 | #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff | |
201 | #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 | |
202 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 | |
203 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15 | |
204 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 | |
205 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 | |
206 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 | |
207 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 | |
208 | #define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 | |
209 | #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 | |
210 | #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 | |
211 | #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 | |
212 | #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 | |
213 | #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 | |
214 | #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5 | |
215 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 | |
216 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 | |
217 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9 | |
218 | #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 | |
219 | #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 | |
220 | #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 | |
221 | ||
222 | /* 5212 */ | |
223 | #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff | |
224 | #define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 | |
225 | #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 | |
226 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 | |
227 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15 | |
228 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 | |
229 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 | |
230 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 | |
231 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 | |
232 | #define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 | |
233 | #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 | |
234 | #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 | |
235 | #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 | |
236 | #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 | |
237 | #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 | |
238 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 | |
239 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 | |
240 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9 | |
241 | #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 | |
242 | #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 | |
243 | #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 | |
244 | ||
fa1c114f | 245 | /* |
19fd6e55 | 246 | * common hardware RX error descriptor |
fa1c114f | 247 | */ |
fa1c114f JS |
248 | struct ath5k_hw_rx_error { |
249 | u32 rx_error_0; /* RX error word 0 */ | |
250 | ||
251 | #define AR5K_RX_DESC_ERROR0 0x00000000 | |
252 | ||
253 | u32 rx_error_1; /* RX error word 1 */ | |
254 | ||
255 | #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 | |
256 | #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 | |
257 | } __packed; | |
258 | ||
259 | #define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 | |
260 | #define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 | |
261 | #define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 | |
262 | #define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 | |
263 | #define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 | |
264 | #define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 | |
265 | #define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 | |
266 | #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 | |
267 | ||
19fd6e55 BR |
268 | /* |
269 | * 5210/5211 hardware 2-word TX control descriptor | |
270 | */ | |
271 | struct ath5k_hw_2w_tx_ctl { | |
fa1c114f JS |
272 | u32 tx_control_0; /* TX control word 0 */ |
273 | ||
274 | #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff | |
275 | #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ | |
276 | #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 | |
277 | #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 | |
278 | #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 | |
279 | #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 | |
280 | #define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 | |
281 | #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ | |
282 | #define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ | |
283 | #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ | |
284 | #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 | |
285 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 | |
286 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 | |
287 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (ah->ah_version == AR5K_AR5210 ? \ | |
288 | AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ | |
289 | AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) | |
290 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 | |
291 | #define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 | |
292 | #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 | |
293 | ||
294 | u32 tx_control_1; /* TX control word 1 */ | |
295 | ||
296 | #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff | |
297 | #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 | |
298 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 | |
299 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 | |
300 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (ah->ah_version == AR5K_AR5210 ? \ | |
301 | AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ | |
302 | AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) | |
303 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 | |
304 | #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ | |
305 | #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 | |
306 | #define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ | |
307 | #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ | |
308 | } __packed; | |
309 | ||
310 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 | |
311 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 | |
312 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 | |
313 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c | |
314 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 | |
315 | ||
316 | /* | |
19fd6e55 | 317 | * 5212 hardware 4-word TX control descriptor |
fa1c114f | 318 | */ |
19fd6e55 | 319 | struct ath5k_hw_4w_tx_ctl { |
fa1c114f JS |
320 | u32 tx_control_0; /* TX control word 0 */ |
321 | ||
322 | #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff | |
323 | #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 | |
324 | #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 | |
325 | #define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 | |
326 | #define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 | |
327 | #define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 | |
328 | #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 | |
329 | #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 | |
330 | #define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 | |
331 | #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 | |
332 | #define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 | |
333 | ||
334 | u32 tx_control_1; /* TX control word 1 */ | |
335 | ||
336 | #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff | |
337 | #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 | |
338 | #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 | |
339 | #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 | |
340 | #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 | |
341 | #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 | |
342 | #define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 | |
343 | #define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 | |
344 | #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 | |
345 | #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 | |
346 | #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 | |
347 | #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 | |
348 | #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 | |
349 | ||
350 | u32 tx_control_2; /* TX control word 2 */ | |
351 | ||
352 | #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff | |
353 | #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 | |
354 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 | |
355 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 | |
356 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 | |
357 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 | |
358 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 | |
359 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 | |
360 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 | |
361 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 | |
362 | ||
363 | u32 tx_control_3; /* TX control word 3 */ | |
364 | ||
365 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f | |
366 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 | |
367 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 | |
368 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 | |
369 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 | |
370 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 | |
371 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 | |
372 | #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 | |
373 | #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 | |
374 | } __packed; | |
375 | ||
376 | /* | |
19fd6e55 | 377 | * Common TX status descriptor |
fa1c114f JS |
378 | */ |
379 | struct ath5k_hw_tx_status { | |
380 | u32 tx_status_0; /* TX status word 0 */ | |
381 | ||
382 | #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 | |
383 | #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 | |
384 | #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 | |
385 | #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 | |
386 | /*??? | |
387 | #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 | |
388 | #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 | |
389 | */ | |
390 | #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 | |
391 | #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 | |
392 | /*??? | |
393 | #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 | |
394 | #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 | |
395 | */ | |
396 | #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 | |
397 | #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 | |
398 | #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 | |
399 | #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 | |
400 | #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 | |
401 | #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 | |
402 | ||
403 | u32 tx_status_1; /* TX status word 1 */ | |
404 | ||
405 | #define AR5K_DESC_TX_STATUS1_DONE 0x00000001 | |
406 | #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe | |
407 | #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 | |
408 | #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 | |
409 | #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 | |
410 | #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 | |
411 | #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 | |
412 | #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 | |
413 | #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 | |
414 | } __packed; | |
415 | ||
416 | ||
19fd6e55 BR |
417 | /* |
418 | * 5210/5211 hardware TX descriptor | |
419 | */ | |
420 | struct ath5k_hw_5210_tx_desc { | |
421 | struct ath5k_hw_2w_tx_ctl tx_ctl; | |
422 | struct ath5k_hw_tx_status tx_stat; | |
423 | } __packed; | |
424 | ||
425 | /* | |
426 | * 5212 hardware TX descriptor | |
427 | */ | |
428 | struct ath5k_hw_5212_tx_desc { | |
429 | struct ath5k_hw_4w_tx_ctl tx_ctl; | |
430 | struct ath5k_hw_tx_status tx_stat; | |
431 | } __packed; | |
432 | ||
433 | /* | |
434 | * common hardware RX descriptor | |
435 | */ | |
436 | struct ath5k_hw_all_rx_desc { | |
437 | struct ath5k_hw_rx_ctl rx_ctl; | |
438 | union { | |
439 | struct ath5k_hw_rx_status rx_stat; | |
440 | struct ath5k_hw_rx_error rx_err; | |
441 | } u; | |
442 | } __packed; | |
443 | ||
444 | ||
fa1c114f JS |
445 | /* |
446 | * AR5K REGISTER ACCESS | |
447 | */ | |
448 | ||
449 | /*Swap RX/TX Descriptor for big endian archs*/ | |
450 | #if defined(__BIG_ENDIAN) | |
451 | #define AR5K_INIT_CFG ( \ | |
452 | AR5K_CFG_SWTD | AR5K_CFG_SWRD \ | |
453 | ) | |
454 | #else | |
455 | #define AR5K_INIT_CFG 0x00000000 | |
456 | #endif | |
457 | ||
458 | /*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(ah, _reg) | |
459 | ||
460 | #define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(ah, _val, _reg)*/ | |
461 | ||
462 | #define AR5K_REG_SM(_val, _flags) \ | |
463 | (((_val) << _flags##_S) & (_flags)) | |
464 | ||
465 | #define AR5K_REG_MS(_val, _flags) \ | |
466 | (((_val) & (_flags)) >> _flags##_S) | |
467 | ||
468 | /* Some registers can hold multiple values of interest. For this | |
469 | * reason when we want to write to these registers we must first | |
470 | * retrieve the values which we do not want to clear (lets call this | |
471 | * old_data) and then set the register with this and our new_value: | |
472 | * ( old_data | new_value) */ | |
473 | #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ | |
474 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ | |
475 | (((_val) << _flags##_S) & (_flags)), _reg) | |
476 | ||
477 | #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ | |
478 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ | |
479 | (_mask)) | (_flags), _reg) | |
480 | ||
481 | #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ | |
482 | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) | |
483 | ||
484 | #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ | |
485 | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) | |
486 | ||
487 | #define AR5K_PHY_WRITE(ah, _reg, _val) \ | |
488 | ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) | |
489 | ||
490 | #define AR5K_PHY_READ(ah, _reg) \ | |
491 | ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) | |
492 | ||
493 | #define AR5K_REG_WAIT(_i) do { \ | |
494 | if (_i % 64) \ | |
495 | udelay(1); \ | |
496 | } while (0) | |
497 | ||
498 | #define AR5K_EEPROM_READ(_o, _v) do { \ | |
499 | if ((ret = ath5k_hw_eeprom_read(ah, (_o), &(_v))) != 0) \ | |
500 | return (ret); \ | |
501 | } while (0) | |
502 | ||
503 | #define AR5K_EEPROM_READ_HDR(_o, _v) \ | |
504 | AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ | |
505 | ||
506 | /* Read status of selected queue */ | |
507 | #define AR5K_REG_READ_Q(ah, _reg, _queue) \ | |
508 | (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ | |
509 | ||
510 | #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ | |
511 | ath5k_hw_reg_write(ah, (1 << _queue), _reg) | |
512 | ||
513 | #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ | |
514 | _reg |= 1 << _queue; \ | |
515 | } while (0) | |
516 | ||
517 | #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ | |
518 | _reg &= ~(1 << _queue); \ | |
519 | } while (0) | |
520 | ||
521 | #define AR5K_LOW_ID(_a)( \ | |
522 | (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ | |
523 | ) | |
524 | ||
525 | #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) | |
526 | ||
527 | /* | |
528 | * Initial register values | |
529 | */ | |
530 | ||
531 | /* | |
532 | * Common initial register values | |
533 | */ | |
534 | #define AR5K_INIT_MODE CHANNEL_B | |
535 | ||
536 | #define AR5K_INIT_TX_LATENCY 502 | |
537 | #define AR5K_INIT_USEC 39 | |
538 | #define AR5K_INIT_USEC_TURBO 79 | |
539 | #define AR5K_INIT_USEC_32 31 | |
540 | #define AR5K_INIT_CARR_SENSE_EN 1 | |
541 | #define AR5K_INIT_PROG_IFS 920 | |
542 | #define AR5K_INIT_PROG_IFS_TURBO 960 | |
543 | #define AR5K_INIT_EIFS 3440 | |
544 | #define AR5K_INIT_EIFS_TURBO 6880 | |
545 | #define AR5K_INIT_SLOT_TIME 396 | |
546 | #define AR5K_INIT_SLOT_TIME_TURBO 480 | |
547 | #define AR5K_INIT_ACK_CTS_TIMEOUT 1024 | |
548 | #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 | |
549 | #define AR5K_INIT_SIFS 560 | |
550 | #define AR5K_INIT_SIFS_TURBO 480 | |
551 | #define AR5K_INIT_SH_RETRY 10 | |
552 | #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY | |
553 | #define AR5K_INIT_SSH_RETRY 32 | |
554 | #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY | |
555 | #define AR5K_INIT_TX_RETRY 10 | |
556 | #define AR5K_INIT_TOPS 8 | |
557 | #define AR5K_INIT_RXNOFRM 8 | |
558 | #define AR5K_INIT_RPGTO 0 | |
559 | #define AR5K_INIT_TXNOFRM 0 | |
560 | #define AR5K_INIT_BEACON_PERIOD 65535 | |
561 | #define AR5K_INIT_TIM_OFFSET 0 | |
562 | #define AR5K_INIT_BEACON_EN 0 | |
563 | #define AR5K_INIT_RESET_TSF 0 | |
564 | ||
565 | #define AR5K_INIT_TRANSMIT_LATENCY ( \ | |
566 | (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ | |
567 | (AR5K_INIT_USEC) \ | |
568 | ) | |
569 | #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ | |
570 | (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ | |
571 | (AR5K_INIT_USEC_TURBO) \ | |
572 | ) | |
573 | #define AR5K_INIT_PROTO_TIME_CNTRL ( \ | |
574 | (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ | |
575 | (AR5K_INIT_PROG_IFS) \ | |
576 | ) | |
577 | #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ | |
578 | (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ | |
579 | (AR5K_INIT_PROG_IFS_TURBO) \ | |
580 | ) | |
581 | #define AR5K_INIT_BEACON_CONTROL ( \ | |
582 | (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ | |
583 | (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ | |
584 | ) | |
585 | ||
586 | /* | |
587 | * Non-common initial register values which have to be loaded into the | |
588 | * card at boot time and after each reset. | |
589 | */ | |
590 | ||
591 | /* Register dumps are done per operation mode */ | |
592 | #define AR5K_INI_RFGAIN_5GHZ 0 | |
593 | #define AR5K_INI_RFGAIN_2GHZ 1 | |
594 | ||
595 | #define AR5K_INI_VAL_11A 0 | |
596 | #define AR5K_INI_VAL_11A_TURBO 1 | |
597 | #define AR5K_INI_VAL_11B 2 | |
598 | #define AR5K_INI_VAL_11G 3 | |
599 | #define AR5K_INI_VAL_11G_TURBO 4 | |
600 | #define AR5K_INI_VAL_XR 0 | |
601 | #define AR5K_INI_VAL_MAX 5 | |
602 | ||
603 | #define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS | |
604 | #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS | |
605 | ||
606 | static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) | |
607 | { | |
608 | u32 retval = 0, bit, i; | |
609 | ||
610 | for (i = 0; i < bits; i++) { | |
611 | bit = (val >> i) & 1; | |
612 | retval = (retval << 1) | bit; | |
613 | } | |
614 | ||
615 | return retval; | |
616 | } |