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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/leds.h> | |
24 | #include <linux/rfkill.h> | |
25 | ||
26 | #include "hw.h" | |
27 | #include "rc.h" | |
28 | #include "debug.h" | |
29 | ||
30 | struct ath_node; | |
31 | ||
32 | /* Macro to expand scalars to 64-bit objects */ | |
33 | ||
34 | #define ito64(x) (sizeof(x) == 8) ? \ | |
35 | (((unsigned long long int)(x)) & (0xff)) : \ | |
36 | (sizeof(x) == 16) ? \ | |
37 | (((unsigned long long int)(x)) & 0xffff) : \ | |
38 | ((sizeof(x) == 32) ? \ | |
39 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
40 | (unsigned long long int)(x)) | |
41 | ||
42 | /* increment with wrap-around */ | |
43 | #define INCR(_l, _sz) do { \ | |
44 | (_l)++; \ | |
45 | (_l) &= ((_sz) - 1); \ | |
46 | } while (0) | |
47 | ||
48 | /* decrement with wrap-around */ | |
49 | #define DECR(_l, _sz) do { \ | |
50 | (_l)--; \ | |
51 | (_l) &= ((_sz) - 1); \ | |
52 | } while (0) | |
53 | ||
54 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
55 | ||
56 | #define ASSERT(exp) do { \ | |
57 | if (unlikely(!(exp))) { \ | |
58 | BUG(); \ | |
59 | } \ | |
60 | } while (0) | |
61 | ||
62 | #define TSF_TO_TU(_h,_l) \ | |
63 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
64 | ||
65 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
66 | ||
67 | static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
68 | ||
69 | struct ath_config { | |
70 | u32 ath_aggr_prot; | |
71 | u16 txpowlimit; | |
72 | u8 cabqReadytime; | |
73 | u8 swBeaconProcess; | |
74 | }; | |
75 | ||
76 | /*************************/ | |
77 | /* Descriptor Management */ | |
78 | /*************************/ | |
79 | ||
80 | #define ATH_TXBUF_RESET(_bf) do { \ | |
81 | (_bf)->bf_status = 0; \ | |
82 | (_bf)->bf_lastbf = NULL; \ | |
83 | (_bf)->bf_next = NULL; \ | |
84 | memset(&((_bf)->bf_state), 0, \ | |
85 | sizeof(struct ath_buf_state)); \ | |
86 | } while (0) | |
87 | ||
88 | /** | |
89 | * enum buffer_type - Buffer type flags | |
90 | * | |
91 | * @BUF_HT: Send this buffer using HT capabilities | |
92 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
93 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
94 | * (used in aggregation scheduling) | |
95 | * @BUF_RETRY: Indicates whether the buffer is retried | |
96 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
97 | */ | |
98 | enum buffer_type { | |
99 | BUF_HT = BIT(1), | |
100 | BUF_AMPDU = BIT(2), | |
101 | BUF_AGGR = BIT(3), | |
102 | BUF_RETRY = BIT(4), | |
103 | BUF_XRETRY = BIT(5), | |
104 | }; | |
105 | ||
106 | struct ath_buf_state { | |
17d7904d S |
107 | int bfs_nframes; |
108 | u16 bfs_al; | |
109 | u16 bfs_frmlen; | |
110 | int bfs_seqno; | |
111 | int bfs_tidno; | |
112 | int bfs_retries; | |
113 | u32 bf_type; | |
394cf0a1 S |
114 | u32 bfs_keyix; |
115 | enum ath9k_key_type bfs_keytype; | |
116 | }; | |
117 | ||
118 | #define bf_nframes bf_state.bfs_nframes | |
119 | #define bf_al bf_state.bfs_al | |
120 | #define bf_frmlen bf_state.bfs_frmlen | |
121 | #define bf_retries bf_state.bfs_retries | |
122 | #define bf_seqno bf_state.bfs_seqno | |
123 | #define bf_tidno bf_state.bfs_tidno | |
124 | #define bf_keyix bf_state.bfs_keyix | |
125 | #define bf_keytype bf_state.bfs_keytype | |
126 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
127 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
128 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
129 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
130 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 131 | |
394cf0a1 S |
132 | struct ath_buf { |
133 | struct list_head list; | |
134 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
135 | an aggregate) */ | |
136 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
137 | void *bf_mpdu; /* enclosing frame structure */ | |
138 | struct ath_desc *bf_desc; /* virtual addr of desc */ | |
139 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
140 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | |
141 | u32 bf_status; | |
17d7904d S |
142 | u16 bf_flags; |
143 | struct ath_buf_state bf_state; | |
394cf0a1 S |
144 | dma_addr_t bf_dmacontext; |
145 | }; | |
146 | ||
147 | #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) | |
148 | #define ATH_BUFSTATUS_STALE 0x00000002 | |
149 | ||
394cf0a1 S |
150 | struct ath_descdma { |
151 | const char *dd_name; | |
17d7904d S |
152 | struct ath_desc *dd_desc; |
153 | dma_addr_t dd_desc_paddr; | |
154 | u32 dd_desc_len; | |
155 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
156 | dma_addr_t dd_dmacontext; |
157 | }; | |
158 | ||
159 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
160 | struct list_head *head, const char *name, | |
161 | int nbuf, int ndesc); | |
162 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, | |
163 | struct list_head *head); | |
164 | ||
165 | /***********/ | |
166 | /* RX / TX */ | |
167 | /***********/ | |
168 | ||
169 | #define ATH_MAX_ANTENNA 3 | |
170 | #define ATH_RXBUF 512 | |
171 | #define WME_NUM_TID 16 | |
172 | #define ATH_TXBUF 512 | |
173 | #define ATH_TXMAXTRY 13 | |
174 | #define ATH_11N_TXMAXTRY 10 | |
175 | #define ATH_MGT_TXMAXTRY 4 | |
176 | #define WME_BA_BMP_SIZE 64 | |
177 | #define WME_MAX_BA WME_BA_BMP_SIZE | |
178 | #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) | |
179 | ||
180 | #define TID_TO_WME_AC(_tid) \ | |
181 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
182 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
183 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
184 | WME_AC_VO) | |
185 | ||
186 | #define WME_AC_BE 0 | |
187 | #define WME_AC_BK 1 | |
188 | #define WME_AC_VI 2 | |
189 | #define WME_AC_VO 3 | |
190 | #define WME_NUM_AC 4 | |
191 | ||
192 | #define ADDBA_EXCHANGE_ATTEMPTS 10 | |
193 | #define ATH_AGGR_DELIM_SZ 4 | |
194 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
195 | /* number of delimiters for encryption padding */ | |
196 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
197 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
198 | #define ATH_AGGR_MIN_QDEPTH 2 | |
199 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
200 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | |
201 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX | |
202 | ||
203 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
204 | #define IEEE80211_SEQ_MAX 4096 | |
205 | #define IEEE80211_MIN_AMPDU_BUF 0x8 | |
206 | #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 | |
207 | #define IEEE80211_WEP_IVLEN 3 | |
208 | #define IEEE80211_WEP_KIDLEN 1 | |
209 | #define IEEE80211_WEP_CRCLEN 4 | |
210 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
211 | (IEEE80211_WEP_IVLEN + \ | |
212 | IEEE80211_WEP_KIDLEN + \ | |
213 | IEEE80211_WEP_CRCLEN)) | |
214 | ||
215 | /* return whether a bit at index _n in bitmap _bm is set | |
216 | * _sz is the size of the bitmap */ | |
217 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
218 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
219 | ||
220 | /* return block-ack bitmap index given sequence and starting sequence */ | |
221 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
222 | ||
223 | /* returns delimiter padding required given the packet length */ | |
224 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
225 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
226 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
227 | ||
228 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
229 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
230 | ||
231 | #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) | |
232 | #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) | |
233 | #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) | |
234 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) | |
235 | ||
236 | enum ATH_AGGR_STATUS { | |
237 | ATH_AGGR_DONE, | |
238 | ATH_AGGR_BAW_CLOSED, | |
239 | ATH_AGGR_LIMITED, | |
240 | }; | |
241 | ||
242 | struct ath_txq { | |
17d7904d S |
243 | u32 axq_qnum; |
244 | u32 *axq_link; | |
245 | struct list_head axq_q; | |
394cf0a1 | 246 | spinlock_t axq_lock; |
17d7904d S |
247 | u32 axq_depth; |
248 | u8 axq_aggr_depth; | |
249 | u32 axq_totalqueued; | |
250 | bool stopped; | |
251 | struct ath_buf *axq_linkbuf; | |
394cf0a1 S |
252 | |
253 | /* first desc of the last descriptor that contains CTS */ | |
254 | struct ath_desc *axq_lastdsWithCTS; | |
255 | ||
256 | /* final desc of the gating desc that determines whether | |
257 | lastdsWithCTS has been DMA'ed or not */ | |
258 | struct ath_desc *axq_gatingds; | |
259 | ||
260 | struct list_head axq_acq; | |
261 | }; | |
262 | ||
263 | #define AGGR_CLEANUP BIT(1) | |
264 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
265 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
266 | ||
394cf0a1 | 267 | struct ath_atx_tid { |
17d7904d S |
268 | struct list_head list; |
269 | struct list_head buf_q; | |
394cf0a1 S |
270 | struct ath_node *an; |
271 | struct ath_atx_ac *ac; | |
17d7904d | 272 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; |
394cf0a1 S |
273 | u16 seq_start; |
274 | u16 seq_next; | |
275 | u16 baw_size; | |
276 | int tidno; | |
17d7904d S |
277 | int baw_head; /* first un-acked tx buffer */ |
278 | int baw_tail; /* next unused tx buffer slot */ | |
394cf0a1 S |
279 | int sched; |
280 | int paused; | |
281 | u8 state; | |
282 | int addba_exchangeattempts; | |
283 | }; | |
284 | ||
394cf0a1 | 285 | struct ath_atx_ac { |
17d7904d S |
286 | int sched; |
287 | int qnum; | |
288 | struct list_head list; | |
289 | struct list_head tid_q; | |
394cf0a1 S |
290 | }; |
291 | ||
394cf0a1 S |
292 | struct ath_tx_control { |
293 | struct ath_txq *txq; | |
294 | int if_id; | |
f0ed85c6 | 295 | enum ath9k_internal_frame_type frame_type; |
394cf0a1 S |
296 | }; |
297 | ||
394cf0a1 | 298 | struct ath_xmit_status { |
17d7904d S |
299 | int retries; |
300 | int flags; | |
394cf0a1 S |
301 | #define ATH_TX_ERROR 0x01 |
302 | #define ATH_TX_XRETRY 0x02 | |
303 | #define ATH_TX_BAR 0x04 | |
304 | }; | |
305 | ||
306 | /* All RSSI values are noise floor adjusted */ | |
307 | struct ath_tx_stat { | |
308 | int rssi; | |
309 | int rssictl[ATH_MAX_ANTENNA]; | |
310 | int rssiextn[ATH_MAX_ANTENNA]; | |
311 | int rateieee; | |
312 | int rateKbps; | |
313 | int ratecode; | |
314 | int flags; | |
315 | u32 airtime; /* time on air per final tx rate */ | |
316 | }; | |
317 | ||
318 | struct aggr_rifs_param { | |
319 | int param_max_frames; | |
320 | int param_max_len; | |
321 | int param_rl; | |
322 | int param_al; | |
323 | struct ath_rc_series *param_rcs; | |
324 | }; | |
325 | ||
326 | struct ath_node { | |
327 | struct ath_softc *an_sc; | |
328 | struct ath_atx_tid tid[WME_NUM_TID]; | |
329 | struct ath_atx_ac ac[WME_NUM_AC]; | |
330 | u16 maxampdu; | |
331 | u8 mpdudensity; | |
332 | }; | |
333 | ||
334 | struct ath_tx { | |
335 | u16 seq_no; | |
336 | u32 txqsetup; | |
337 | int hwq_map[ATH9K_WME_AC_VO+1]; | |
338 | spinlock_t txbuflock; | |
339 | struct list_head txbuf; | |
340 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
341 | struct ath_descdma txdma; | |
342 | }; | |
343 | ||
344 | struct ath_rx { | |
345 | u8 defant; | |
346 | u8 rxotherant; | |
347 | u32 *rxlink; | |
348 | int bufsize; | |
349 | unsigned int rxfilter; | |
350 | spinlock_t rxflushlock; | |
351 | spinlock_t rxbuflock; | |
352 | struct list_head rxbuf; | |
353 | struct ath_descdma rxdma; | |
354 | }; | |
355 | ||
356 | int ath_startrecv(struct ath_softc *sc); | |
357 | bool ath_stoprecv(struct ath_softc *sc); | |
358 | void ath_flushrecv(struct ath_softc *sc); | |
359 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
360 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
361 | void ath_rx_cleanup(struct ath_softc *sc); | |
362 | int ath_rx_tasklet(struct ath_softc *sc, int flush); | |
363 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); | |
364 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
365 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
366 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
367 | void ath_draintxq(struct ath_softc *sc, | |
368 | struct ath_txq *txq, bool retry_tx); | |
369 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
370 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
371 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
372 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
373 | int ath_tx_cleanup(struct ath_softc *sc); | |
374 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); | |
375 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
376 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 377 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
378 | struct ath_tx_control *txctl); |
379 | void ath_tx_tasklet(struct ath_softc *sc); | |
c52f33d0 | 380 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
394cf0a1 S |
381 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); |
382 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
383 | u16 tid, u16 *ssn); | |
384 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
385 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
386 | ||
387 | /********/ | |
17d7904d | 388 | /* VIFs */ |
394cf0a1 | 389 | /********/ |
f078f209 | 390 | |
17d7904d | 391 | struct ath_vif { |
394cf0a1 S |
392 | int av_bslot; |
393 | enum nl80211_iftype av_opmode; | |
394 | struct ath_buf *av_bcbuf; | |
395 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 396 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
397 | }; |
398 | ||
394cf0a1 S |
399 | /*******************/ |
400 | /* Beacon Handling */ | |
401 | /*******************/ | |
f078f209 | 402 | |
394cf0a1 S |
403 | /* |
404 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
405 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
406 | * number of beacon intervals, the game's up. | |
407 | */ | |
408 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
409 | #define ATH_BCBUF 1 | |
410 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ | |
411 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
412 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
413 | ||
414 | struct ath_beacon_config { | |
415 | u16 beacon_interval; | |
416 | u16 listen_interval; | |
417 | u16 dtim_period; | |
418 | u16 bmiss_timeout; | |
419 | u8 dtim_count; | |
394cf0a1 S |
420 | }; |
421 | ||
422 | struct ath_beacon { | |
423 | enum { | |
424 | OK, /* no change needed */ | |
425 | UPDATE, /* update pending */ | |
426 | COMMIT /* beacon sent, commit change */ | |
427 | } updateslot; /* slot time update fsm */ | |
428 | ||
429 | u32 beaconq; | |
430 | u32 bmisscnt; | |
431 | u32 ast_be_xmit; | |
432 | u64 bc_tstamp; | |
2c3db3d5 | 433 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 434 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
435 | int slottime; |
436 | int slotupdate; | |
437 | struct ath9k_tx_queue_info beacon_qi; | |
438 | struct ath_descdma bdma; | |
439 | struct ath_txq *cabq; | |
440 | struct list_head bbuf; | |
441 | }; | |
442 | ||
9fc9ab0a | 443 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 444 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
cbe61d8a | 445 | int ath_beaconq_setup(struct ath_hw *ah); |
c52f33d0 | 446 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 447 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
394cf0a1 S |
448 | |
449 | /*******/ | |
450 | /* ANI */ | |
451 | /*******/ | |
f078f209 | 452 | |
20977d3e S |
453 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
454 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
455 | #define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ | |
456 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ | |
457 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 458 | |
394cf0a1 | 459 | struct ath_ani { |
17d7904d S |
460 | bool caldone; |
461 | int16_t noise_floor; | |
462 | unsigned int longcal_timer; | |
463 | unsigned int shortcal_timer; | |
464 | unsigned int resetcal_timer; | |
465 | unsigned int checkani_timer; | |
394cf0a1 | 466 | struct timer_list timer; |
f078f209 LR |
467 | }; |
468 | ||
394cf0a1 S |
469 | /********************/ |
470 | /* LED Control */ | |
471 | /********************/ | |
f078f209 | 472 | |
394cf0a1 S |
473 | #define ATH_LED_PIN 1 |
474 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ | |
475 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 476 | |
394cf0a1 S |
477 | enum ath_led_type { |
478 | ATH_LED_RADIO, | |
479 | ATH_LED_ASSOC, | |
480 | ATH_LED_TX, | |
481 | ATH_LED_RX | |
f078f209 LR |
482 | }; |
483 | ||
394cf0a1 S |
484 | struct ath_led { |
485 | struct ath_softc *sc; | |
486 | struct led_classdev led_cdev; | |
487 | enum ath_led_type led_type; | |
488 | char name[32]; | |
489 | bool registered; | |
f078f209 LR |
490 | }; |
491 | ||
394cf0a1 S |
492 | /* Rfkill */ |
493 | #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ | |
f078f209 | 494 | |
394cf0a1 S |
495 | struct ath_rfkill { |
496 | struct rfkill *rfkill; | |
497 | struct delayed_work rfkill_poll; | |
498 | char rfkill_name[32]; | |
f078f209 LR |
499 | }; |
500 | ||
394cf0a1 S |
501 | /********************/ |
502 | /* Main driver core */ | |
503 | /********************/ | |
f078f209 | 504 | |
394cf0a1 S |
505 | /* |
506 | * Default cache line size, in bytes. | |
507 | * Used when PCI device not fully initialized by bootrom/BIOS | |
508 | */ | |
509 | #define DEFAULT_CACHELINE 32 | |
510 | #define ATH_DEFAULT_NOISE_FLOOR -95 | |
511 | #define ATH_REGCLASSIDS_MAX 10 | |
512 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
513 | #define ATH_MAX_SW_RETRIES 10 | |
514 | #define ATH_CHAN_MAX 255 | |
515 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 516 | |
394cf0a1 S |
517 | /* |
518 | * The key cache is used for h/w cipher state and also for | |
519 | * tracking station state such as the current tx antenna. | |
520 | * We also setup a mapping table between key cache slot indices | |
521 | * and station state to short-circuit node lookups on rx. | |
522 | * Different parts have different size key caches. We handle | |
523 | * up to ATH_KEYMAX entries (could dynamically allocate state). | |
524 | */ | |
525 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | |
526 | ||
394cf0a1 S |
527 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
528 | #define ATH_RSSI_DUMMY_MARKER 0x127 | |
529 | #define ATH_RATE_DUMMY_MARKER 0 | |
530 | ||
b238e90e S |
531 | #define SC_OP_INVALID BIT(0) |
532 | #define SC_OP_BEACONS BIT(1) | |
533 | #define SC_OP_RXAGGR BIT(2) | |
534 | #define SC_OP_TXAGGR BIT(3) | |
535 | #define SC_OP_CHAINMASK_UPDATE BIT(4) | |
536 | #define SC_OP_FULL_RESET BIT(5) | |
537 | #define SC_OP_PREAMBLE_SHORT BIT(6) | |
538 | #define SC_OP_PROTECT_ENABLE BIT(7) | |
539 | #define SC_OP_RXFLUSH BIT(8) | |
540 | #define SC_OP_LED_ASSOCIATED BIT(9) | |
541 | #define SC_OP_RFKILL_REGISTERED BIT(10) | |
542 | #define SC_OP_RFKILL_SW_BLOCKED BIT(11) | |
543 | #define SC_OP_RFKILL_HW_BLOCKED BIT(12) | |
544 | #define SC_OP_WAIT_FOR_BEACON BIT(13) | |
545 | #define SC_OP_LED_ON BIT(14) | |
546 | #define SC_OP_SCANNING BIT(15) | |
547 | #define SC_OP_TSF_RESET BIT(16) | |
394cf0a1 S |
548 | |
549 | struct ath_bus_ops { | |
550 | void (*read_cachesize)(struct ath_softc *sc, int *csz); | |
551 | void (*cleanup)(struct ath_softc *sc); | |
cbe61d8a | 552 | bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); |
394cf0a1 S |
553 | }; |
554 | ||
bce048d7 JM |
555 | struct ath_wiphy; |
556 | ||
394cf0a1 S |
557 | struct ath_softc { |
558 | struct ieee80211_hw *hw; | |
559 | struct device *dev; | |
c52f33d0 JM |
560 | |
561 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 562 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
563 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
564 | * have NULL entries */ | |
565 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
566 | int chan_idx; |
567 | int chan_is_ht; | |
568 | struct ath_wiphy *next_wiphy; | |
569 | struct work_struct chan_work; | |
7ec3e514 JM |
570 | int wiphy_select_failures; |
571 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
572 | struct delayed_work wiphy_work; |
573 | unsigned long wiphy_scheduler_int; | |
574 | int wiphy_scheduler_index; | |
0e2dedf9 | 575 | |
394cf0a1 S |
576 | struct tasklet_struct intr_tq; |
577 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 578 | struct ath_hw *sc_ah; |
394cf0a1 S |
579 | void __iomem *mem; |
580 | int irq; | |
581 | spinlock_t sc_resetlock; | |
2d6a5e95 | 582 | spinlock_t sc_serial_rw; |
394cf0a1 S |
583 | struct mutex mutex; |
584 | ||
17d7904d | 585 | u8 curbssid[ETH_ALEN]; |
17d7904d S |
586 | u8 bssidmask[ETH_ALEN]; |
587 | u32 intrstatus; | |
394cf0a1 | 588 | u32 sc_flags; /* SC_OP_* */ |
17d7904d S |
589 | u16 curtxpow; |
590 | u16 curaid; | |
591 | u16 cachelsz; | |
592 | u8 nbcnvifs; | |
593 | u16 nvifs; | |
594 | u8 tx_chainmask; | |
595 | u8 rx_chainmask; | |
596 | u32 keymax; | |
597 | DECLARE_BITMAP(keymap, ATH_KEYMAX); | |
598 | u8 splitmic; | |
394cf0a1 | 599 | atomic_t ps_usecount; |
17d7904d S |
600 | enum ath9k_int imask; |
601 | enum ath9k_ht_extprotspacing ht_extprotspacing; | |
394cf0a1 S |
602 | enum ath9k_ht_macmode tx_chan_width; |
603 | ||
17d7904d | 604 | struct ath_config config; |
394cf0a1 S |
605 | struct ath_rx rx; |
606 | struct ath_tx tx; | |
607 | struct ath_beacon beacon; | |
394cf0a1 S |
608 | struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; |
609 | struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; | |
610 | struct ath_rate_table *cur_rate_table; | |
611 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; | |
612 | ||
613 | struct ath_led radio_led; | |
614 | struct ath_led assoc_led; | |
615 | struct ath_led tx_led; | |
616 | struct ath_led rx_led; | |
617 | struct delayed_work ath_led_blink_work; | |
618 | int led_on_duration; | |
619 | int led_off_duration; | |
620 | int led_on_cnt; | |
621 | int led_off_cnt; | |
622 | ||
623 | struct ath_rfkill rf_kill; | |
17d7904d S |
624 | struct ath_ani ani; |
625 | struct ath9k_node_stats nodestats; | |
394cf0a1 | 626 | #ifdef CONFIG_ATH9K_DEBUG |
17d7904d | 627 | struct ath9k_debug debug; |
394cf0a1 S |
628 | #endif |
629 | struct ath_bus_ops *bus_ops; | |
630 | }; | |
631 | ||
bce048d7 JM |
632 | struct ath_wiphy { |
633 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
634 | struct ieee80211_hw *hw; | |
f0ed85c6 | 635 | enum ath_wiphy_state { |
9580a222 | 636 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
637 | ATH_WIPHY_ACTIVE, |
638 | ATH_WIPHY_PAUSING, | |
639 | ATH_WIPHY_PAUSED, | |
8089cc47 | 640 | ATH_WIPHY_SCAN, |
f0ed85c6 | 641 | } state; |
0e2dedf9 JM |
642 | int chan_idx; |
643 | int chan_is_ht; | |
bce048d7 JM |
644 | }; |
645 | ||
394cf0a1 S |
646 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
647 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |
648 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | |
649 | int ath_cabq_update(struct ath_softc *); | |
650 | ||
651 | static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) | |
652 | { | |
653 | sc->bus_ops->read_cachesize(sc, csz); | |
654 | } | |
655 | ||
656 | static inline void ath_bus_cleanup(struct ath_softc *sc) | |
657 | { | |
658 | sc->bus_ops->cleanup(sc); | |
659 | } | |
660 | ||
661 | extern struct ieee80211_ops ath9k_ops; | |
662 | ||
663 | irqreturn_t ath_isr(int irq, void *dev); | |
664 | void ath_cleanup(struct ath_softc *sc); | |
665 | int ath_attach(u16 devid, struct ath_softc *sc); | |
666 | void ath_detach(struct ath_softc *sc); | |
667 | const char *ath_mac_bb_name(u32 mac_bb_version); | |
668 | const char *ath_rf_name(u16 rf_version); | |
c52f33d0 | 669 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
670 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
671 | struct ath9k_channel *ichan); | |
672 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
673 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
674 | struct ath9k_channel *hchan); | |
7ec3e514 JM |
675 | void ath_radio_enable(struct ath_softc *sc); |
676 | void ath_radio_disable(struct ath_softc *sc); | |
394cf0a1 S |
677 | |
678 | #ifdef CONFIG_PCI | |
679 | int ath_pci_init(void); | |
680 | void ath_pci_exit(void); | |
681 | #else | |
682 | static inline int ath_pci_init(void) { return 0; }; | |
683 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 684 | #endif |
f1dc5600 | 685 | |
394cf0a1 S |
686 | #ifdef CONFIG_ATHEROS_AR71XX |
687 | int ath_ahb_init(void); | |
688 | void ath_ahb_exit(void); | |
689 | #else | |
690 | static inline int ath_ahb_init(void) { return 0; }; | |
691 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 692 | #endif |
394cf0a1 S |
693 | |
694 | static inline void ath9k_ps_wakeup(struct ath_softc *sc) | |
695 | { | |
696 | if (atomic_inc_return(&sc->ps_usecount) == 1) | |
2660b81a S |
697 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) { |
698 | sc->sc_ah->restore_mode = sc->sc_ah->power_mode; | |
394cf0a1 S |
699 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
700 | } | |
701 | } | |
702 | ||
703 | static inline void ath9k_ps_restore(struct ath_softc *sc) | |
704 | { | |
705 | if (atomic_dec_and_test(&sc->ps_usecount)) | |
541d8dd5 VN |
706 | if ((sc->hw->conf.flags & IEEE80211_CONF_PS) && |
707 | !(sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) | |
394cf0a1 | 708 | ath9k_hw_setpower(sc->sc_ah, |
2660b81a | 709 | sc->sc_ah->restore_mode); |
394cf0a1 | 710 | } |
0c98de65 | 711 | |
8ca21f01 JM |
712 | |
713 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw); | |
c52f33d0 JM |
714 | int ath9k_wiphy_add(struct ath_softc *sc); |
715 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
716 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
717 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
718 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 719 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 720 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 721 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 722 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
723 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
724 | struct ath_wiphy *selected); | |
8089cc47 | 725 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 726 | void ath9k_wiphy_work(struct work_struct *work); |
8ca21f01 | 727 | |
2d6a5e95 DM |
728 | /* |
729 | * Read and write, they both share the same lock. We do this to serialize | |
730 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
731 | * as the FIFO on these devices can only accept sanely 2 requests. After | |
732 | * that the device goes bananas. Serializing the reads/writes prevents this | |
733 | * from happening. | |
734 | */ | |
f1dc5600 | 735 | |
2d6a5e95 DM |
736 | static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val) |
737 | { | |
738 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
739 | unsigned long flags; | |
740 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | |
741 | iowrite32(val, ah->ah_sc->mem + reg_offset); | |
742 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | |
743 | } else | |
744 | iowrite32(val, ah->ah_sc->mem + reg_offset); | |
745 | } | |
746 | ||
747 | static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset) | |
748 | { | |
749 | u32 val; | |
750 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
751 | unsigned long flags; | |
752 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | |
753 | val = ioread32(ah->ah_sc->mem + reg_offset); | |
754 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | |
755 | } else | |
756 | val = ioread32(ah->ah_sc->mem + reg_offset); | |
757 | return val; | |
758 | } | |
759 | ||
394cf0a1 | 760 | #endif /* ATH9K_H */ |