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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
20 | #include <linux/io.h> | |
21 | ||
22 | #define ATHEROS_VENDOR_ID 0x168c | |
23 | ||
24 | #define AR5416_DEVID_PCI 0x0023 | |
25 | #define AR5416_DEVID_PCIE 0x0024 | |
26 | #define AR9160_DEVID_PCI 0x0027 | |
27 | #define AR9280_DEVID_PCI 0x0029 | |
28 | #define AR9280_DEVID_PCIE 0x002a | |
e7594072 | 29 | #define AR9285_DEVID_PCIE 0x002b |
f078f209 LR |
30 | |
31 | #define AR5416_AR9100_DEVID 0x000b | |
32 | ||
33 | #define AR_SUBVENDOR_ID_NOG 0x0e11 | |
34 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
35 | ||
36 | #define ATH9K_TXERR_XRETRY 0x01 | |
37 | #define ATH9K_TXERR_FILT 0x02 | |
38 | #define ATH9K_TXERR_FIFO 0x04 | |
39 | #define ATH9K_TXERR_XTXOP 0x08 | |
40 | #define ATH9K_TXERR_TIMER_EXPIRED 0x10 | |
41 | ||
42 | #define ATH9K_TX_BA 0x01 | |
43 | #define ATH9K_TX_PWRMGMT 0x02 | |
44 | #define ATH9K_TX_DESC_CFG_ERR 0x04 | |
45 | #define ATH9K_TX_DATA_UNDERRUN 0x08 | |
46 | #define ATH9K_TX_DELIM_UNDERRUN 0x10 | |
47 | #define ATH9K_TX_SW_ABORTED 0x40 | |
48 | #define ATH9K_TX_SW_FILTERED 0x80 | |
49 | ||
50 | #define NBBY 8 | |
51 | ||
52 | struct ath_tx_status { | |
53 | u32 ts_tstamp; | |
54 | u16 ts_seqnum; | |
55 | u8 ts_status; | |
56 | u8 ts_ratecode; | |
57 | u8 ts_rateindex; | |
58 | int8_t ts_rssi; | |
59 | u8 ts_shortretry; | |
60 | u8 ts_longretry; | |
61 | u8 ts_virtcol; | |
62 | u8 ts_antenna; | |
63 | u8 ts_flags; | |
64 | int8_t ts_rssi_ctl0; | |
65 | int8_t ts_rssi_ctl1; | |
66 | int8_t ts_rssi_ctl2; | |
67 | int8_t ts_rssi_ext0; | |
68 | int8_t ts_rssi_ext1; | |
69 | int8_t ts_rssi_ext2; | |
70 | u8 pad[3]; | |
71 | u32 ba_low; | |
72 | u32 ba_high; | |
73 | u32 evm0; | |
74 | u32 evm1; | |
75 | u32 evm2; | |
76 | }; | |
77 | ||
78 | struct ath_rx_status { | |
79 | u32 rs_tstamp; | |
80 | u16 rs_datalen; | |
81 | u8 rs_status; | |
82 | u8 rs_phyerr; | |
83 | int8_t rs_rssi; | |
84 | u8 rs_keyix; | |
85 | u8 rs_rate; | |
86 | u8 rs_antenna; | |
87 | u8 rs_more; | |
88 | int8_t rs_rssi_ctl0; | |
89 | int8_t rs_rssi_ctl1; | |
90 | int8_t rs_rssi_ctl2; | |
91 | int8_t rs_rssi_ext0; | |
92 | int8_t rs_rssi_ext1; | |
93 | int8_t rs_rssi_ext2; | |
94 | u8 rs_isaggr; | |
95 | u8 rs_moreaggr; | |
96 | u8 rs_num_delims; | |
97 | u8 rs_flags; | |
98 | u32 evm0; | |
99 | u32 evm1; | |
100 | u32 evm2; | |
101 | }; | |
102 | ||
103 | #define ATH9K_RXERR_CRC 0x01 | |
104 | #define ATH9K_RXERR_PHY 0x02 | |
105 | #define ATH9K_RXERR_FIFO 0x04 | |
106 | #define ATH9K_RXERR_DECRYPT 0x08 | |
107 | #define ATH9K_RXERR_MIC 0x10 | |
108 | ||
109 | #define ATH9K_RX_MORE 0x01 | |
110 | #define ATH9K_RX_MORE_AGGR 0x02 | |
111 | #define ATH9K_RX_GI 0x04 | |
112 | #define ATH9K_RX_2040 0x08 | |
113 | #define ATH9K_RX_DELIM_CRC_PRE 0x10 | |
114 | #define ATH9K_RX_DELIM_CRC_POST 0x20 | |
115 | #define ATH9K_RX_DECRYPT_BUSY 0x40 | |
116 | ||
117 | #define ATH9K_RXKEYIX_INVALID ((u8)-1) | |
118 | #define ATH9K_TXKEYIX_INVALID ((u32)-1) | |
119 | ||
120 | struct ath_desc { | |
121 | u32 ds_link; | |
122 | u32 ds_data; | |
123 | u32 ds_ctl0; | |
124 | u32 ds_ctl1; | |
125 | u32 ds_hw[20]; | |
126 | union { | |
127 | struct ath_tx_status tx; | |
128 | struct ath_rx_status rx; | |
129 | void *stats; | |
130 | } ds_us; | |
131 | void *ds_vdata; | |
132 | } __packed; | |
133 | ||
134 | #define ds_txstat ds_us.tx | |
135 | #define ds_rxstat ds_us.rx | |
136 | #define ds_stat ds_us.stats | |
137 | ||
138 | #define ATH9K_TXDESC_CLRDMASK 0x0001 | |
139 | #define ATH9K_TXDESC_NOACK 0x0002 | |
140 | #define ATH9K_TXDESC_RTSENA 0x0004 | |
141 | #define ATH9K_TXDESC_CTSENA 0x0008 | |
b139a10a LR |
142 | /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for |
143 | * the descriptor its marked on. We take a tx interrupt to reap | |
144 | * descriptors when the h/w hits an EOL condition or | |
145 | * when the descriptor is specifically marked to generate | |
146 | * an interrupt with this flag. Descriptors should be | |
147 | * marked periodically to insure timely replenishing of the | |
148 | * supply needed for sending frames. Defering interrupts | |
149 | * reduces system load and potentially allows more concurrent | |
150 | * work to be done but if done to aggressively can cause | |
151 | * senders to backup. When the hardware queue is left too | |
152 | * large rate control information may also be too out of | |
153 | * date. An Alternative for this is TX interrupt mitigation | |
154 | * but this needs more testing. */ | |
f078f209 LR |
155 | #define ATH9K_TXDESC_INTREQ 0x0010 |
156 | #define ATH9K_TXDESC_VEOL 0x0020 | |
157 | #define ATH9K_TXDESC_EXT_ONLY 0x0040 | |
158 | #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 | |
159 | #define ATH9K_TXDESC_VMF 0x0100 | |
160 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 | |
e022edbd | 161 | #define ATH9K_TXDESC_CAB 0x0400 |
f078f209 LR |
162 | |
163 | #define ATH9K_RXDESC_INTREQ 0x0020 | |
164 | ||
86b89eed S |
165 | enum wireless_mode { |
166 | ATH9K_MODE_11A = 0, | |
167 | ATH9K_MODE_11B = 2, | |
168 | ATH9K_MODE_11G = 3, | |
169 | ATH9K_MODE_11NA_HT20 = 6, | |
170 | ATH9K_MODE_11NG_HT20 = 7, | |
171 | ATH9K_MODE_11NA_HT40PLUS = 8, | |
172 | ATH9K_MODE_11NA_HT40MINUS = 9, | |
173 | ATH9K_MODE_11NG_HT40PLUS = 10, | |
174 | ATH9K_MODE_11NG_HT40MINUS = 11, | |
175 | ATH9K_MODE_MAX | |
176 | }; | |
177 | ||
60b67f51 S |
178 | enum ath9k_hw_caps { |
179 | ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), | |
180 | ATH9K_HW_CAP_MIC_AESCCM = BIT(1), | |
181 | ATH9K_HW_CAP_MIC_CKIP = BIT(2), | |
182 | ATH9K_HW_CAP_MIC_TKIP = BIT(3), | |
183 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), | |
184 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), | |
185 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), | |
186 | ATH9K_HW_CAP_VEOL = BIT(7), | |
187 | ATH9K_HW_CAP_BSSIDMASK = BIT(8), | |
188 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), | |
189 | ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), | |
190 | ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), | |
191 | ATH9K_HW_CAP_HT = BIT(12), | |
192 | ATH9K_HW_CAP_GTT = BIT(13), | |
193 | ATH9K_HW_CAP_FASTCC = BIT(14), | |
194 | ATH9K_HW_CAP_RFSILENT = BIT(15), | |
195 | ATH9K_HW_CAP_WOW = BIT(16), | |
196 | ATH9K_HW_CAP_CST = BIT(17), | |
197 | ATH9K_HW_CAP_ENHANCEDPM = BIT(18), | |
198 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), | |
199 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), | |
200 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), | |
c97c92d9 | 201 | ATH9K_HW_CAP_BT_COEX = BIT(22) |
60b67f51 S |
202 | }; |
203 | ||
204 | enum ath9k_capability_type { | |
205 | ATH9K_CAP_CIPHER = 0, | |
206 | ATH9K_CAP_TKIP_MIC, | |
207 | ATH9K_CAP_TKIP_SPLIT, | |
208 | ATH9K_CAP_PHYCOUNTERS, | |
209 | ATH9K_CAP_DIVERSITY, | |
210 | ATH9K_CAP_TXPOW, | |
211 | ATH9K_CAP_PHYDIAG, | |
212 | ATH9K_CAP_MCAST_KEYSRCH, | |
213 | ATH9K_CAP_TSF_ADJUST, | |
214 | ATH9K_CAP_WME_TKIPMIC, | |
215 | ATH9K_CAP_RFSILENT, | |
216 | ATH9K_CAP_ANT_CFG_2GHZ, | |
217 | ATH9K_CAP_ANT_CFG_5GHZ | |
218 | }; | |
219 | ||
220 | struct ath9k_hw_capabilities { | |
221 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
86b89eed | 222 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ |
60b67f51 S |
223 | u16 total_queues; |
224 | u16 keycache_size; | |
225 | u16 low_5ghz_chan, high_5ghz_chan; | |
226 | u16 low_2ghz_chan, high_2ghz_chan; | |
227 | u16 num_mr_retries; | |
228 | u16 rts_aggr_limit; | |
229 | u8 tx_chainmask; | |
230 | u8 rx_chainmask; | |
231 | u16 tx_triglevel_max; | |
232 | u16 reg_cap; | |
233 | u8 num_gpio_pins; | |
234 | u8 num_antcfg_2ghz; | |
235 | u8 num_antcfg_5ghz; | |
236 | }; | |
237 | ||
238 | struct ath9k_ops_config { | |
239 | int dma_beacon_response_time; | |
240 | int sw_beacon_response_time; | |
241 | int additional_swba_backoff; | |
242 | int ack_6mb; | |
243 | int cwm_ignore_extcca; | |
244 | u8 pcie_powersave_enable; | |
245 | u8 pcie_l1skp_enable; | |
246 | u8 pcie_clock_req; | |
247 | u32 pcie_waen; | |
248 | int pcie_power_reset; | |
249 | u8 pcie_restore; | |
250 | u8 analog_shiftreg; | |
251 | u8 ht_enable; | |
252 | u32 ofdm_trig_low; | |
253 | u32 ofdm_trig_high; | |
254 | u32 cck_trig_high; | |
255 | u32 cck_trig_low; | |
256 | u32 enable_ani; | |
257 | u8 noise_immunity_level; | |
258 | u32 ofdm_weaksignal_det; | |
259 | u32 cck_weaksignal_thr; | |
260 | u8 spur_immunity_level; | |
261 | u8 firstep_level; | |
262 | int8_t rssi_thr_high; | |
263 | int8_t rssi_thr_low; | |
264 | u16 diversity_control; | |
265 | u16 antenna_switch_swap; | |
266 | int serialize_regmode; | |
267 | int intr_mitigation; | |
f078f209 LR |
268 | #define SPUR_DISABLE 0 |
269 | #define SPUR_ENABLE_IOCTL 1 | |
270 | #define SPUR_ENABLE_EEPROM 2 | |
271 | #define AR_EEPROM_MODAL_SPURS 5 | |
272 | #define AR_SPUR_5413_1 1640 | |
273 | #define AR_SPUR_5413_2 1200 | |
274 | #define AR_NO_SPUR 0x8000 | |
275 | #define AR_BASE_FREQ_2GHZ 2300 | |
276 | #define AR_BASE_FREQ_5GHZ 4900 | |
277 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
278 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
60b67f51 S |
279 | int spurmode; |
280 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f078f209 LR |
281 | }; |
282 | ||
283 | enum ath9k_tx_queue { | |
284 | ATH9K_TX_QUEUE_INACTIVE = 0, | |
285 | ATH9K_TX_QUEUE_DATA, | |
286 | ATH9K_TX_QUEUE_BEACON, | |
287 | ATH9K_TX_QUEUE_CAB, | |
288 | ATH9K_TX_QUEUE_UAPSD, | |
289 | ATH9K_TX_QUEUE_PSPOLL | |
290 | }; | |
291 | ||
292 | #define ATH9K_NUM_TX_QUEUES 10 | |
293 | ||
294 | enum ath9k_tx_queue_subtype { | |
295 | ATH9K_WME_AC_BK = 0, | |
296 | ATH9K_WME_AC_BE, | |
297 | ATH9K_WME_AC_VI, | |
298 | ATH9K_WME_AC_VO, | |
299 | ATH9K_WME_UPSD | |
300 | }; | |
301 | ||
302 | enum ath9k_tx_queue_flags { | |
303 | TXQ_FLAG_TXOKINT_ENABLE = 0x0001, | |
304 | TXQ_FLAG_TXERRINT_ENABLE = 0x0001, | |
305 | TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, | |
306 | TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, | |
307 | TXQ_FLAG_TXURNINT_ENABLE = 0x0008, | |
308 | TXQ_FLAG_BACKOFF_DISABLE = 0x0010, | |
309 | TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, | |
310 | TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, | |
311 | TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, | |
312 | }; | |
313 | ||
f078f209 LR |
314 | #define ATH9K_TXQ_USEDEFAULT ((u32) -1) |
315 | ||
316 | #define ATH9K_DECOMP_MASK_SIZE 128 | |
317 | #define ATH9K_READY_TIME_LO_BOUND 50 | |
318 | #define ATH9K_READY_TIME_HI_BOUND 96 | |
319 | ||
320 | enum ath9k_pkt_type { | |
321 | ATH9K_PKT_TYPE_NORMAL = 0, | |
322 | ATH9K_PKT_TYPE_ATIM, | |
323 | ATH9K_PKT_TYPE_PSPOLL, | |
324 | ATH9K_PKT_TYPE_BEACON, | |
325 | ATH9K_PKT_TYPE_PROBE_RESP, | |
326 | ATH9K_PKT_TYPE_CHIRP, | |
327 | ATH9K_PKT_TYPE_GRP_POLL, | |
328 | }; | |
329 | ||
330 | struct ath9k_tx_queue_info { | |
331 | u32 tqi_ver; | |
332 | enum ath9k_tx_queue tqi_type; | |
333 | enum ath9k_tx_queue_subtype tqi_subtype; | |
334 | enum ath9k_tx_queue_flags tqi_qflags; | |
335 | u32 tqi_priority; | |
336 | u32 tqi_aifs; | |
337 | u32 tqi_cwmin; | |
338 | u32 tqi_cwmax; | |
339 | u16 tqi_shretry; | |
340 | u16 tqi_lgretry; | |
341 | u32 tqi_cbrPeriod; | |
342 | u32 tqi_cbrOverflowLimit; | |
343 | u32 tqi_burstTime; | |
344 | u32 tqi_readyTime; | |
345 | u32 tqi_physCompBuf; | |
346 | u32 tqi_intFlags; | |
347 | }; | |
348 | ||
349 | enum ath9k_rx_filter { | |
350 | ATH9K_RX_FILTER_UCAST = 0x00000001, | |
351 | ATH9K_RX_FILTER_MCAST = 0x00000002, | |
352 | ATH9K_RX_FILTER_BCAST = 0x00000004, | |
353 | ATH9K_RX_FILTER_CONTROL = 0x00000008, | |
354 | ATH9K_RX_FILTER_BEACON = 0x00000010, | |
355 | ATH9K_RX_FILTER_PROM = 0x00000020, | |
356 | ATH9K_RX_FILTER_PROBEREQ = 0x00000080, | |
357 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, | |
358 | ATH9K_RX_FILTER_PHYERR = 0x00000100, | |
359 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, | |
360 | }; | |
361 | ||
362 | enum ath9k_int { | |
363 | ATH9K_INT_RX = 0x00000001, | |
364 | ATH9K_INT_RXDESC = 0x00000002, | |
365 | ATH9K_INT_RXNOFRM = 0x00000008, | |
366 | ATH9K_INT_RXEOL = 0x00000010, | |
367 | ATH9K_INT_RXORN = 0x00000020, | |
368 | ATH9K_INT_TX = 0x00000040, | |
369 | ATH9K_INT_TXDESC = 0x00000080, | |
370 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
371 | ATH9K_INT_TXURN = 0x00000800, | |
372 | ATH9K_INT_MIB = 0x00001000, | |
373 | ATH9K_INT_RXPHY = 0x00004000, | |
374 | ATH9K_INT_RXKCM = 0x00008000, | |
375 | ATH9K_INT_SWBA = 0x00010000, | |
376 | ATH9K_INT_BMISS = 0x00040000, | |
377 | ATH9K_INT_BNR = 0x00100000, | |
378 | ATH9K_INT_TIM = 0x00200000, | |
379 | ATH9K_INT_DTIM = 0x00400000, | |
380 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
381 | ATH9K_INT_GPIO = 0x01000000, | |
382 | ATH9K_INT_CABEND = 0x02000000, | |
383 | ATH9K_INT_CST = 0x10000000, | |
384 | ATH9K_INT_GTT = 0x20000000, | |
385 | ATH9K_INT_FATAL = 0x40000000, | |
386 | ATH9K_INT_GLOBAL = 0x80000000, | |
387 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
388 | ATH9K_INT_DTIM | | |
389 | ATH9K_INT_DTIMSYNC | | |
390 | ATH9K_INT_CABEND, | |
391 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
392 | ATH9K_INT_RXDESC | | |
393 | ATH9K_INT_RXEOL | | |
394 | ATH9K_INT_RXORN | | |
395 | ATH9K_INT_TXURN | | |
396 | ATH9K_INT_TXDESC | | |
397 | ATH9K_INT_MIB | | |
398 | ATH9K_INT_RXPHY | | |
399 | ATH9K_INT_RXKCM | | |
400 | ATH9K_INT_SWBA | | |
401 | ATH9K_INT_BMISS | | |
402 | ATH9K_INT_GPIO, | |
403 | ATH9K_INT_NOCARD = 0xffffffff | |
404 | }; | |
405 | ||
f078f209 LR |
406 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 |
407 | #define ATH9K_RATESERIES_2040 0x0002 | |
408 | #define ATH9K_RATESERIES_HALFGI 0x0004 | |
409 | ||
410 | struct ath9k_11n_rate_series { | |
411 | u32 Tries; | |
412 | u32 Rate; | |
413 | u32 PktDuration; | |
414 | u32 ChSel; | |
415 | u32 RateFlags; | |
416 | }; | |
417 | ||
418 | #define CHANNEL_CW_INT 0x00002 | |
419 | #define CHANNEL_CCK 0x00020 | |
420 | #define CHANNEL_OFDM 0x00040 | |
421 | #define CHANNEL_2GHZ 0x00080 | |
422 | #define CHANNEL_5GHZ 0x00100 | |
423 | #define CHANNEL_PASSIVE 0x00200 | |
424 | #define CHANNEL_DYN 0x00400 | |
425 | #define CHANNEL_HALF 0x04000 | |
426 | #define CHANNEL_QUARTER 0x08000 | |
427 | #define CHANNEL_HT20 0x10000 | |
428 | #define CHANNEL_HT40PLUS 0x20000 | |
429 | #define CHANNEL_HT40MINUS 0x40000 | |
430 | ||
431 | #define CHANNEL_INTERFERENCE 0x01 | |
432 | #define CHANNEL_DFS 0x02 | |
433 | #define CHANNEL_4MS_LIMIT 0x04 | |
434 | #define CHANNEL_DFS_CLEAR 0x08 | |
435 | #define CHANNEL_DISALLOW_ADHOC 0x10 | |
436 | #define CHANNEL_PER_11D_ADHOC 0x20 | |
437 | ||
438 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) | |
439 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
440 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
441 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
442 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
443 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
444 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
445 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
446 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
447 | #define CHANNEL_ALL \ | |
448 | (CHANNEL_OFDM| \ | |
449 | CHANNEL_CCK| \ | |
450 | CHANNEL_2GHZ | \ | |
451 | CHANNEL_5GHZ | \ | |
452 | CHANNEL_HT20 | \ | |
453 | CHANNEL_HT40PLUS | \ | |
454 | CHANNEL_HT40MINUS) | |
455 | ||
456 | struct ath9k_channel { | |
76061abb | 457 | struct ieee80211_channel *chan; |
f078f209 LR |
458 | u16 channel; |
459 | u32 channelFlags; | |
460 | u8 privFlags; | |
461 | int8_t maxRegTxPower; | |
462 | int8_t maxTxPower; | |
463 | int8_t minTxPower; | |
464 | u32 chanmode; | |
465 | int32_t CalValid; | |
466 | bool oneTimeCalsDone; | |
467 | int8_t iCoff; | |
468 | int8_t qCoff; | |
469 | int16_t rawNoiseFloor; | |
470 | int8_t antennaMax; | |
471 | u32 regDmnFlags; | |
472 | u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */ | |
473 | #ifdef ATH_NF_PER_CHAN | |
474 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | |
475 | #endif | |
476 | }; | |
477 | ||
478 | #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ | |
479 | (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ | |
480 | (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ | |
481 | (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) | |
f078f209 LR |
482 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
483 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
484 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
485 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
f078f209 LR |
486 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) |
487 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
488 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
489 | #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) | |
490 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) | |
491 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
492 | ||
493 | /* These macros check chanmode and not channelFlags */ | |
788a3d6f | 494 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) |
f078f209 LR |
495 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ |
496 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
497 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
498 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
499 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
500 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
501 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
502 | ||
503 | #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) | |
504 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | |
505 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | |
506 | (((_c)->channel % 20) != 0) && \ | |
507 | (((_c)->channel % 10) != 0)) | |
508 | ||
509 | struct ath9k_keyval { | |
510 | u8 kv_type; | |
511 | u8 kv_pad; | |
512 | u16 kv_len; | |
513 | u8 kv_val[16]; | |
514 | u8 kv_mic[8]; | |
515 | u8 kv_txmic[8]; | |
516 | }; | |
517 | ||
518 | enum ath9k_key_type { | |
519 | ATH9K_KEY_TYPE_CLEAR, | |
520 | ATH9K_KEY_TYPE_WEP, | |
521 | ATH9K_KEY_TYPE_AES, | |
522 | ATH9K_KEY_TYPE_TKIP, | |
523 | }; | |
524 | ||
525 | enum ath9k_cipher { | |
526 | ATH9K_CIPHER_WEP = 0, | |
527 | ATH9K_CIPHER_AES_OCB = 1, | |
528 | ATH9K_CIPHER_AES_CCM = 2, | |
529 | ATH9K_CIPHER_CKIP = 3, | |
530 | ATH9K_CIPHER_TKIP = 4, | |
531 | ATH9K_CIPHER_CLR = 5, | |
532 | ATH9K_CIPHER_MIC = 127 | |
533 | }; | |
534 | ||
535 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 | |
536 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 | |
537 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 | |
538 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 | |
539 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 | |
540 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 | |
541 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 | |
542 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 | |
543 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 | |
544 | ||
545 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 | |
546 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 | |
547 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 | |
548 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 | |
549 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 | |
550 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 | |
551 | ||
552 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 | |
553 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 | |
554 | ||
555 | #define SD_NO_CTL 0xE0 | |
556 | #define NO_CTL 0xff | |
557 | #define CTL_MODE_M 7 | |
558 | #define CTL_11A 0 | |
559 | #define CTL_11B 1 | |
560 | #define CTL_11G 2 | |
561 | #define CTL_2GHT20 5 | |
562 | #define CTL_5GHT20 6 | |
563 | #define CTL_2GHT40 7 | |
564 | #define CTL_5GHT40 8 | |
565 | ||
566 | #define AR_EEPROM_MAC(i) (0x1d+(i)) | |
f078f209 LR |
567 | |
568 | #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c | |
569 | #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 | |
570 | #define AR_EEPROM_RFSILENT_POLARITY 0x0002 | |
571 | #define AR_EEPROM_RFSILENT_POLARITY_S 1 | |
572 | ||
573 | #define CTRY_DEBUG 0x1ff | |
574 | #define CTRY_DEFAULT 0 | |
575 | ||
576 | enum reg_ext_bitmap { | |
577 | REG_EXT_JAPAN_MIDBAND = 1, | |
578 | REG_EXT_FCC_DFS_HT40 = 2, | |
579 | REG_EXT_JAPAN_NONDFS_HT40 = 3, | |
580 | REG_EXT_JAPAN_DFS_HT40 = 4 | |
581 | }; | |
582 | ||
583 | struct ath9k_country_entry { | |
584 | u16 countryCode; | |
585 | u16 regDmnEnum; | |
586 | u16 regDmn5G; | |
587 | u16 regDmn2G; | |
588 | u8 isMultidomain; | |
589 | u8 iso[3]; | |
590 | }; | |
591 | ||
592 | #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) | |
593 | #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) | |
594 | ||
595 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | |
596 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
597 | #define REG_RMW(_a, _r, _set, _clr) \ | |
598 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
599 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
600 | REG_WRITE(_a, _r, \ | |
601 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
602 | #define REG_SET_BIT(_a, _r, _f) \ | |
603 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
604 | #define REG_CLR_BIT(_a, _r, _f) \ | |
605 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
606 | ||
f078f209 LR |
607 | #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 |
608 | ||
609 | #define INIT_AIFS 2 | |
610 | #define INIT_CWMIN 15 | |
611 | #define INIT_CWMIN_11B 31 | |
612 | #define INIT_CWMAX 1023 | |
613 | #define INIT_SH_RETRY 10 | |
614 | #define INIT_LG_RETRY 10 | |
615 | #define INIT_SSH_RETRY 32 | |
616 | #define INIT_SLG_RETRY 32 | |
617 | ||
618 | #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) | |
619 | ||
620 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | |
621 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX | |
622 | ||
623 | #define IEEE80211_WEP_IVLEN 3 | |
624 | #define IEEE80211_WEP_KIDLEN 1 | |
625 | #define IEEE80211_WEP_CRCLEN 4 | |
626 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
627 | (IEEE80211_WEP_IVLEN + \ | |
628 | IEEE80211_WEP_KIDLEN + \ | |
629 | IEEE80211_WEP_CRCLEN)) | |
f078f209 LR |
630 | #define MAX_RATE_POWER 63 |
631 | ||
632 | enum ath9k_power_mode { | |
633 | ATH9K_PM_AWAKE = 0, | |
634 | ATH9K_PM_FULL_SLEEP, | |
635 | ATH9K_PM_NETWORK_SLEEP, | |
636 | ATH9K_PM_UNDEFINED | |
637 | }; | |
638 | ||
f078f209 LR |
639 | struct ath9k_mib_stats { |
640 | u32 ackrcv_bad; | |
641 | u32 rts_bad; | |
642 | u32 rts_good; | |
643 | u32 fcs_bad; | |
644 | u32 beacons; | |
645 | }; | |
646 | ||
647 | enum ath9k_ant_setting { | |
648 | ATH9K_ANT_VARIABLE = 0, | |
649 | ATH9K_ANT_FIXED_A, | |
650 | ATH9K_ANT_FIXED_B | |
651 | }; | |
652 | ||
f078f209 LR |
653 | #define ATH9K_SLOT_TIME_6 6 |
654 | #define ATH9K_SLOT_TIME_9 9 | |
655 | #define ATH9K_SLOT_TIME_20 20 | |
656 | ||
657 | enum ath9k_ht_macmode { | |
658 | ATH9K_HT_MACMODE_20 = 0, | |
659 | ATH9K_HT_MACMODE_2040 = 1, | |
660 | }; | |
661 | ||
662 | enum ath9k_ht_extprotspacing { | |
663 | ATH9K_HT_EXTPROTSPACING_20 = 0, | |
664 | ATH9K_HT_EXTPROTSPACING_25 = 1, | |
665 | }; | |
666 | ||
667 | struct ath9k_ht_cwm { | |
668 | enum ath9k_ht_macmode ht_macmode; | |
669 | enum ath9k_ht_extprotspacing ht_extprotspacing; | |
670 | }; | |
671 | ||
f078f209 LR |
672 | enum ath9k_ani_cmd { |
673 | ATH9K_ANI_PRESENT = 0x1, | |
674 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, | |
675 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, | |
676 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, | |
677 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, | |
678 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, | |
679 | ATH9K_ANI_MODE = 0x40, | |
680 | ATH9K_ANI_PHYERR_RESET = 0x80, | |
681 | ATH9K_ANI_ALL = 0xff | |
682 | }; | |
683 | ||
46d14a58 S |
684 | enum { |
685 | WLAN_RC_PHY_OFDM, | |
686 | WLAN_RC_PHY_CCK, | |
687 | WLAN_RC_PHY_HT_20_SS, | |
688 | WLAN_RC_PHY_HT_20_DS, | |
689 | WLAN_RC_PHY_HT_40_SS, | |
690 | WLAN_RC_PHY_HT_40_DS, | |
691 | WLAN_RC_PHY_HT_20_SS_HGI, | |
692 | WLAN_RC_PHY_HT_20_DS_HGI, | |
693 | WLAN_RC_PHY_HT_40_SS_HGI, | |
694 | WLAN_RC_PHY_HT_40_DS_HGI, | |
695 | WLAN_RC_PHY_MAX | |
f078f209 | 696 | }; |
f078f209 | 697 | |
f078f209 LR |
698 | enum ath9k_tp_scale { |
699 | ATH9K_TP_SCALE_MAX = 0, | |
700 | ATH9K_TP_SCALE_50, | |
701 | ATH9K_TP_SCALE_25, | |
702 | ATH9K_TP_SCALE_12, | |
703 | ATH9K_TP_SCALE_MIN | |
704 | }; | |
705 | ||
706 | enum ser_reg_mode { | |
707 | SER_REG_MODE_OFF = 0, | |
708 | SER_REG_MODE_ON = 1, | |
709 | SER_REG_MODE_AUTO = 2, | |
710 | }; | |
711 | ||
712 | #define AR_PHY_CCA_MAX_GOOD_VALUE -85 | |
713 | #define AR_PHY_CCA_MAX_HIGH_VALUE -62 | |
714 | #define AR_PHY_CCA_MIN_BAD_VALUE -121 | |
715 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 | |
716 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 | |
717 | ||
718 | #define ATH9K_NF_CAL_HIST_MAX 5 | |
719 | #define NUM_NF_READINGS 6 | |
720 | ||
721 | struct ath9k_nfcal_hist { | |
722 | int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; | |
723 | u8 currIndex; | |
724 | int16_t privNF; | |
725 | u8 invalidNFcount; | |
726 | }; | |
727 | ||
728 | struct ath9k_beacon_state { | |
729 | u32 bs_nexttbtt; | |
730 | u32 bs_nextdtim; | |
731 | u32 bs_intval; | |
732 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
733 | #define ATH9K_BEACON_ENA 0x00800000 | |
734 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
735 | u32 bs_dtimperiod; | |
736 | u16 bs_cfpperiod; | |
737 | u16 bs_cfpmaxduration; | |
738 | u32 bs_cfpnext; | |
739 | u16 bs_timoffset; | |
740 | u16 bs_bmissthreshold; | |
741 | u32 bs_sleepduration; | |
742 | }; | |
743 | ||
744 | struct ath9k_node_stats { | |
745 | u32 ns_avgbrssi; | |
746 | u32 ns_avgrssi; | |
747 | u32 ns_avgtxrssi; | |
748 | u32 ns_avgtxrate; | |
749 | }; | |
750 | ||
751 | #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) | |
752 | ||
c83be688 VT |
753 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
754 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
755 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
c97c92d9 | 756 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 |
c83be688 VT |
757 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
758 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 LR |
759 | |
760 | enum { | |
761 | ATH9K_RESET_POWER_ON, | |
762 | ATH9K_RESET_WARM, | |
763 | ATH9K_RESET_COLD, | |
764 | }; | |
765 | ||
766 | #define AH_USE_EEPROM 0x1 | |
767 | ||
768 | struct ath_hal { | |
769 | u32 ah_magic; | |
770 | u16 ah_devid; | |
771 | u16 ah_subvendorid; | |
f078f209 LR |
772 | u32 ah_macVersion; |
773 | u16 ah_macRev; | |
774 | u16 ah_phyRev; | |
775 | u16 ah_analog5GhzRev; | |
776 | u16 ah_analog2GhzRev; | |
6a2b9e8c S |
777 | |
778 | void __iomem *ah_sh; | |
779 | struct ath_softc *ah_sc; | |
d97809db CM |
780 | |
781 | enum nl80211_iftype ah_opmode; | |
60b67f51 S |
782 | struct ath9k_ops_config ah_config; |
783 | struct ath9k_hw_capabilities ah_caps; | |
6a2b9e8c S |
784 | |
785 | u16 ah_countryCode; | |
786 | u32 ah_flags; | |
f078f209 LR |
787 | int16_t ah_powerLimit; |
788 | u16 ah_maxPowerLevel; | |
789 | u32 ah_tpScale; | |
790 | u16 ah_currentRD; | |
791 | u16 ah_currentRDExt; | |
792 | u16 ah_currentRDInUse; | |
793 | u16 ah_currentRD5G; | |
794 | u16 ah_currentRD2G; | |
795 | char ah_iso[4]; | |
6a2b9e8c | 796 | |
f078f209 | 797 | struct ath9k_channel ah_channels[150]; |
f078f209 | 798 | struct ath9k_channel *ah_curchan; |
6a2b9e8c S |
799 | u32 ah_nchan; |
800 | ||
f078f209 LR |
801 | bool ah_isPciExpress; |
802 | u16 ah_txTrigLevel; | |
500c064d VT |
803 | u16 ah_rfsilent; |
804 | u32 ah_rfkill_gpio; | |
805 | u32 ah_rfkill_polarity; | |
c97c92d9 VT |
806 | u32 ah_btactive_gpio; |
807 | u32 ah_wlanactive_gpio; | |
6a2b9e8c | 808 | |
f078f209 LR |
809 | #ifndef ATH_NF_PER_CHAN |
810 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | |
811 | #endif | |
0ced0e17 JM |
812 | |
813 | bool sw_mgmt_crypto; | |
f078f209 LR |
814 | }; |
815 | ||
f078f209 LR |
816 | struct chan_centers { |
817 | u16 synth_center; | |
818 | u16 ctl_center; | |
819 | u16 ext_center; | |
820 | }; | |
821 | ||
e63835b0 S |
822 | struct ath_rate_table; |
823 | ||
f1dc5600 S |
824 | /* Helpers */ |
825 | ||
826 | enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, | |
827 | const struct ath9k_channel *chan); | |
828 | bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); | |
829 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); | |
830 | bool ath9k_get_channel_edges(struct ath_hal *ah, | |
831 | u16 flags, u16 *low, | |
832 | u16 *high); | |
833 | u16 ath9k_hw_computetxtime(struct ath_hal *ah, | |
e63835b0 | 834 | struct ath_rate_table *rates, |
f1dc5600 S |
835 | u32 frameLen, u16 rateix, |
836 | bool shortPreamble); | |
f078f209 | 837 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); |
f1dc5600 S |
838 | void ath9k_hw_get_channel_centers(struct ath_hal *ah, |
839 | struct ath9k_channel *chan, | |
840 | struct chan_centers *centers); | |
841 | ||
842 | /* Attach, Detach */ | |
843 | ||
844 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); | |
845 | void ath9k_hw_detach(struct ath_hal *ah); | |
846 | struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, | |
847 | void __iomem *mem, int *error); | |
848 | void ath9k_hw_rfdetach(struct ath_hal *ah); | |
849 | ||
850 | ||
851 | /* HW Reset */ | |
852 | ||
ae8d2858 LR |
853 | int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, |
854 | bool bChannelChange); | |
f1dc5600 S |
855 | |
856 | /* Key Cache Management */ | |
857 | ||
f078f209 | 858 | bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); |
f1dc5600 S |
859 | bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); |
860 | bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, | |
861 | const struct ath9k_keyval *k, | |
862 | const u8 *mac, int xorKey); | |
863 | bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); | |
864 | ||
865 | /* Power Management */ | |
866 | ||
f078f209 LR |
867 | bool ath9k_hw_setpower(struct ath_hal *ah, |
868 | enum ath9k_power_mode mode); | |
f1dc5600 S |
869 | void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); |
870 | ||
871 | /* Beacon timers */ | |
872 | ||
873 | void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); | |
874 | void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, | |
875 | const struct ath9k_beacon_state *bs); | |
f1dc5600 S |
876 | /* HW Capabilities */ |
877 | ||
878 | bool ath9k_hw_fill_cap_info(struct ath_hal *ah); | |
879 | bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, | |
880 | u32 capability, u32 *result); | |
881 | bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, | |
882 | u32 capability, u32 setting, int *status); | |
883 | ||
884 | /* GPIO / RFKILL / Antennae */ | |
885 | ||
886 | void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); | |
887 | u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); | |
888 | void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, | |
889 | u32 ah_signal_type); | |
890 | void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); | |
e97275cb | 891 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
f1dc5600 S |
892 | void ath9k_enable_rfkill(struct ath_hal *ah); |
893 | #endif | |
894 | int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg); | |
f078f209 | 895 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah); |
f1dc5600 | 896 | void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); |
f078f209 LR |
897 | bool ath9k_hw_setantennaswitch(struct ath_hal *ah, |
898 | enum ath9k_ant_setting settings, | |
899 | struct ath9k_channel *chan, | |
900 | u8 *tx_chainmask, | |
901 | u8 *rx_chainmask, | |
902 | u8 *antenna_cfgd); | |
f1dc5600 S |
903 | |
904 | /* General Operation */ | |
905 | ||
906 | u32 ath9k_hw_getrxfilter(struct ath_hal *ah); | |
907 | void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); | |
908 | bool ath9k_hw_phy_disable(struct ath_hal *ah); | |
909 | bool ath9k_hw_disable(struct ath_hal *ah); | |
910 | bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); | |
911 | void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); | |
912 | bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); | |
913 | void ath9k_hw_setopmode(struct ath_hal *ah); | |
914 | void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); | |
915 | void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); | |
916 | bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask); | |
917 | void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId); | |
918 | u64 ath9k_hw_gettsf64(struct ath_hal *ah); | |
919 | void ath9k_hw_reset_tsf(struct ath_hal *ah); | |
920 | bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); | |
921 | bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); | |
922 | void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); | |
923 | ||
924 | /* Regulatory */ | |
925 | ||
926 | bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah); | |
927 | struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah, | |
928 | const struct ath9k_channel *c); | |
929 | u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); | |
930 | u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah, | |
931 | struct ath9k_channel *chan); | |
932 | bool ath9k_regd_init_channels(struct ath_hal *ah, | |
933 | u32 maxchans, u32 *nchans, u8 *regclassids, | |
934 | u32 maxregids, u32 *nregids, u16 cc, | |
935 | bool enableOutdoor, bool enableExtendedChannels); | |
936 | ||
937 | /* ANI */ | |
938 | ||
939 | void ath9k_ani_reset(struct ath_hal *ah); | |
940 | void ath9k_hw_ani_monitor(struct ath_hal *ah, | |
941 | const struct ath9k_node_stats *stats, | |
942 | struct ath9k_channel *chan); | |
943 | bool ath9k_hw_phycounters(struct ath_hal *ah); | |
944 | void ath9k_enable_mib_counters(struct ath_hal *ah); | |
945 | void ath9k_hw_disable_mib_counters(struct ath_hal *ah); | |
946 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | |
947 | u32 *rxc_pcnt, | |
948 | u32 *rxf_pcnt, | |
949 | u32 *txf_pcnt); | |
950 | void ath9k_hw_procmibevent(struct ath_hal *ah, | |
951 | const struct ath9k_node_stats *stats); | |
952 | void ath9k_hw_ani_setup(struct ath_hal *ah); | |
953 | void ath9k_hw_ani_attach(struct ath_hal *ah); | |
954 | void ath9k_hw_ani_detach(struct ath_hal *ah); | |
955 | ||
956 | /* Calibration */ | |
957 | ||
c9e27d94 | 958 | bool ath9k_hw_reset_calvalid(struct ath_hal *ah); |
f1dc5600 S |
959 | void ath9k_hw_start_nfcal(struct ath_hal *ah); |
960 | void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); | |
961 | int16_t ath9k_hw_getnf(struct ath_hal *ah, | |
962 | struct ath9k_channel *chan); | |
963 | void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); | |
964 | s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); | |
965 | bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, | |
966 | u8 rxchainmask, bool longcal, | |
967 | bool *isCalDone); | |
968 | bool ath9k_hw_init_cal(struct ath_hal *ah, | |
969 | struct ath9k_channel *chan); | |
970 | ||
971 | ||
972 | /* EEPROM */ | |
973 | ||
974 | int ath9k_hw_set_txpower(struct ath_hal *ah, | |
975 | struct ath9k_channel *chan, | |
976 | u16 cfgCtl, | |
977 | u8 twiceAntennaReduction, | |
978 | u8 twiceMaxRegulatoryPower, | |
979 | u8 powerLimit); | |
980 | void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); | |
981 | bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, | |
982 | struct ath9k_channel *chan, | |
983 | int16_t *ratesArray, | |
984 | u16 cfgCtl, | |
985 | u8 AntennaReduction, | |
986 | u8 twiceMaxRegulatoryPower, | |
987 | u8 powerLimit); | |
988 | bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, | |
989 | struct ath9k_channel *chan, | |
990 | int16_t *pTxPowerIndexOffset); | |
991 | bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, | |
992 | struct ath9k_channel *chan); | |
993 | int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, | |
994 | struct ath9k_channel *chan, | |
995 | u8 index, u16 *config); | |
996 | u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, | |
997 | enum ieee80211_band freq_band); | |
998 | u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); | |
999 | int ath9k_hw_eeprom_attach(struct ath_hal *ah); | |
1000 | ||
1001 | /* Interrupt Handling */ | |
1002 | ||
1003 | bool ath9k_hw_intrpend(struct ath_hal *ah); | |
1004 | bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); | |
1005 | enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); | |
1006 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); | |
1007 | ||
1008 | /* MAC (PCU/QCU) */ | |
1009 | ||
f1dc5600 S |
1010 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); |
1011 | bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); | |
f078f209 | 1012 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); |
f1dc5600 S |
1013 | u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); |
1014 | bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); | |
1015 | bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); | |
1016 | bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, | |
1017 | u32 segLen, bool firstSeg, | |
1018 | bool lastSeg, const struct ath_desc *ds0); | |
1019 | void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); | |
1020 | int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); | |
1021 | void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, | |
1022 | u32 pktLen, enum ath9k_pkt_type type, u32 txPower, | |
1023 | u32 keyIx, enum ath9k_key_type keyType, u32 flags); | |
f078f209 LR |
1024 | void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, |
1025 | struct ath_desc *lastds, | |
1026 | u32 durUpdateEn, u32 rtsctsRate, | |
1027 | u32 rtsctsDuration, | |
1028 | struct ath9k_11n_rate_series series[], | |
1029 | u32 nseries, u32 flags); | |
f1dc5600 S |
1030 | void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, |
1031 | u32 aggrLen); | |
1032 | void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, | |
1033 | u32 numDelims); | |
1034 | void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); | |
1035 | void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); | |
1036 | void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, | |
f078f209 | 1037 | u32 burstDuration); |
f1dc5600 S |
1038 | void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, |
1039 | u32 vmf); | |
1040 | void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); | |
ea9880fb S |
1041 | bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, |
1042 | const struct ath9k_tx_queue_info *qinfo); | |
f1dc5600 S |
1043 | bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, |
1044 | struct ath9k_tx_queue_info *qinfo); | |
1045 | int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, | |
1046 | const struct ath9k_tx_queue_info *qinfo); | |
1047 | bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); | |
1048 | bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); | |
1049 | int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, | |
1050 | u32 pa, struct ath_desc *nds, u64 tsf); | |
f078f209 LR |
1051 | bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, |
1052 | u32 size, u32 flags); | |
f1dc5600 | 1053 | bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); |
f078f209 LR |
1054 | void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); |
1055 | void ath9k_hw_rxena(struct ath_hal *ah); | |
f078f209 LR |
1056 | void ath9k_hw_startpcureceive(struct ath_hal *ah); |
1057 | void ath9k_hw_stoppcurecv(struct ath_hal *ah); | |
1058 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah); | |
c97c92d9 | 1059 | void ath9k_hw_btcoex_enable(struct ath_hal *ah); |
f1dc5600 | 1060 | |
f078f209 | 1061 | #endif |