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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/leds.h> | |
24 | #include <linux/rfkill.h> | |
25 | ||
26 | #include "hw.h" | |
27 | #include "rc.h" | |
28 | #include "debug.h" | |
29 | ||
30 | struct ath_node; | |
31 | ||
32 | /* Macro to expand scalars to 64-bit objects */ | |
33 | ||
34 | #define ito64(x) (sizeof(x) == 8) ? \ | |
35 | (((unsigned long long int)(x)) & (0xff)) : \ | |
36 | (sizeof(x) == 16) ? \ | |
37 | (((unsigned long long int)(x)) & 0xffff) : \ | |
38 | ((sizeof(x) == 32) ? \ | |
39 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
40 | (unsigned long long int)(x)) | |
41 | ||
42 | /* increment with wrap-around */ | |
43 | #define INCR(_l, _sz) do { \ | |
44 | (_l)++; \ | |
45 | (_l) &= ((_sz) - 1); \ | |
46 | } while (0) | |
47 | ||
48 | /* decrement with wrap-around */ | |
49 | #define DECR(_l, _sz) do { \ | |
50 | (_l)--; \ | |
51 | (_l) &= ((_sz) - 1); \ | |
52 | } while (0) | |
53 | ||
54 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
55 | ||
56 | #define ASSERT(exp) do { \ | |
57 | if (unlikely(!(exp))) { \ | |
58 | BUG(); \ | |
59 | } \ | |
60 | } while (0) | |
61 | ||
62 | #define TSF_TO_TU(_h,_l) \ | |
63 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
64 | ||
65 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
66 | ||
67 | static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
68 | ||
69 | struct ath_config { | |
70 | u32 ath_aggr_prot; | |
71 | u16 txpowlimit; | |
72 | u8 cabqReadytime; | |
73 | u8 swBeaconProcess; | |
74 | }; | |
75 | ||
76 | /*************************/ | |
77 | /* Descriptor Management */ | |
78 | /*************************/ | |
79 | ||
80 | #define ATH_TXBUF_RESET(_bf) do { \ | |
81 | (_bf)->bf_status = 0; \ | |
82 | (_bf)->bf_lastbf = NULL; \ | |
83 | (_bf)->bf_next = NULL; \ | |
84 | memset(&((_bf)->bf_state), 0, \ | |
85 | sizeof(struct ath_buf_state)); \ | |
86 | } while (0) | |
87 | ||
88 | /** | |
89 | * enum buffer_type - Buffer type flags | |
90 | * | |
91 | * @BUF_HT: Send this buffer using HT capabilities | |
92 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
93 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
94 | * (used in aggregation scheduling) | |
95 | * @BUF_RETRY: Indicates whether the buffer is retried | |
96 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
97 | */ | |
98 | enum buffer_type { | |
99 | BUF_HT = BIT(1), | |
100 | BUF_AMPDU = BIT(2), | |
101 | BUF_AGGR = BIT(3), | |
102 | BUF_RETRY = BIT(4), | |
103 | BUF_XRETRY = BIT(5), | |
104 | }; | |
105 | ||
106 | struct ath_buf_state { | |
107 | int bfs_nframes; /* # frames in aggregate */ | |
108 | u16 bfs_al; /* length of aggregate */ | |
109 | u16 bfs_frmlen; /* length of frame */ | |
110 | int bfs_seqno; /* sequence number */ | |
111 | int bfs_tidno; /* tid of this frame */ | |
112 | int bfs_retries; /* current retries */ | |
113 | u32 bf_type; /* BUF_* (enum buffer_type) */ | |
114 | u32 bfs_keyix; | |
115 | enum ath9k_key_type bfs_keytype; | |
116 | }; | |
117 | ||
118 | #define bf_nframes bf_state.bfs_nframes | |
119 | #define bf_al bf_state.bfs_al | |
120 | #define bf_frmlen bf_state.bfs_frmlen | |
121 | #define bf_retries bf_state.bfs_retries | |
122 | #define bf_seqno bf_state.bfs_seqno | |
123 | #define bf_tidno bf_state.bfs_tidno | |
124 | #define bf_keyix bf_state.bfs_keyix | |
125 | #define bf_keytype bf_state.bfs_keytype | |
126 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
127 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
128 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
129 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
130 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 131 | |
394cf0a1 S |
132 | /* |
133 | * Abstraction of a contiguous buffer to transmit/receive. There is only | |
134 | * a single hw descriptor encapsulated here. | |
135 | */ | |
136 | struct ath_buf { | |
137 | struct list_head list; | |
138 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
139 | an aggregate) */ | |
140 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
141 | void *bf_mpdu; /* enclosing frame structure */ | |
142 | struct ath_desc *bf_desc; /* virtual addr of desc */ | |
143 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
144 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | |
145 | u32 bf_status; | |
146 | u16 bf_flags; /* tx descriptor flags */ | |
147 | struct ath_buf_state bf_state; /* buffer state */ | |
148 | dma_addr_t bf_dmacontext; | |
149 | }; | |
150 | ||
151 | #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) | |
152 | #define ATH_BUFSTATUS_STALE 0x00000002 | |
153 | ||
154 | /* DMA state for tx/rx descriptors */ | |
155 | ||
156 | struct ath_descdma { | |
157 | const char *dd_name; | |
158 | struct ath_desc *dd_desc; /* descriptors */ | |
159 | dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ | |
160 | u32 dd_desc_len; /* size of dd_desc */ | |
161 | struct ath_buf *dd_bufptr; /* associated buffers */ | |
162 | dma_addr_t dd_dmacontext; | |
163 | }; | |
164 | ||
165 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
166 | struct list_head *head, const char *name, | |
167 | int nbuf, int ndesc); | |
168 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, | |
169 | struct list_head *head); | |
170 | ||
171 | /***********/ | |
172 | /* RX / TX */ | |
173 | /***********/ | |
174 | ||
175 | #define ATH_MAX_ANTENNA 3 | |
176 | #define ATH_RXBUF 512 | |
177 | #define WME_NUM_TID 16 | |
178 | #define ATH_TXBUF 512 | |
179 | #define ATH_TXMAXTRY 13 | |
180 | #define ATH_11N_TXMAXTRY 10 | |
181 | #define ATH_MGT_TXMAXTRY 4 | |
182 | #define WME_BA_BMP_SIZE 64 | |
183 | #define WME_MAX_BA WME_BA_BMP_SIZE | |
184 | #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) | |
185 | ||
186 | #define TID_TO_WME_AC(_tid) \ | |
187 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
188 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
189 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
190 | WME_AC_VO) | |
191 | ||
192 | #define WME_AC_BE 0 | |
193 | #define WME_AC_BK 1 | |
194 | #define WME_AC_VI 2 | |
195 | #define WME_AC_VO 3 | |
196 | #define WME_NUM_AC 4 | |
197 | ||
198 | #define ADDBA_EXCHANGE_ATTEMPTS 10 | |
199 | #define ATH_AGGR_DELIM_SZ 4 | |
200 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
201 | /* number of delimiters for encryption padding */ | |
202 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
203 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
204 | #define ATH_AGGR_MIN_QDEPTH 2 | |
205 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
206 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | |
207 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX | |
208 | ||
209 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
210 | #define IEEE80211_SEQ_MAX 4096 | |
211 | #define IEEE80211_MIN_AMPDU_BUF 0x8 | |
212 | #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 | |
213 | #define IEEE80211_WEP_IVLEN 3 | |
214 | #define IEEE80211_WEP_KIDLEN 1 | |
215 | #define IEEE80211_WEP_CRCLEN 4 | |
216 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
217 | (IEEE80211_WEP_IVLEN + \ | |
218 | IEEE80211_WEP_KIDLEN + \ | |
219 | IEEE80211_WEP_CRCLEN)) | |
220 | ||
221 | /* return whether a bit at index _n in bitmap _bm is set | |
222 | * _sz is the size of the bitmap */ | |
223 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
224 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
225 | ||
226 | /* return block-ack bitmap index given sequence and starting sequence */ | |
227 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
228 | ||
229 | /* returns delimiter padding required given the packet length */ | |
230 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
231 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
232 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
233 | ||
234 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
235 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
236 | ||
237 | #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) | |
238 | #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) | |
239 | #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) | |
240 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) | |
241 | ||
242 | enum ATH_AGGR_STATUS { | |
243 | ATH_AGGR_DONE, | |
244 | ATH_AGGR_BAW_CLOSED, | |
245 | ATH_AGGR_LIMITED, | |
246 | }; | |
247 | ||
248 | struct ath_txq { | |
249 | u32 axq_qnum; /* hardware q number */ | |
250 | u32 *axq_link; /* link ptr in last TX desc */ | |
251 | struct list_head axq_q; /* transmit queue */ | |
252 | spinlock_t axq_lock; | |
253 | u32 axq_depth; /* queue depth */ | |
254 | u8 axq_aggr_depth; /* aggregates queued */ | |
255 | u32 axq_totalqueued; /* total ever queued */ | |
256 | bool stopped; /* Is mac80211 queue stopped ? */ | |
257 | struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ | |
258 | ||
259 | /* first desc of the last descriptor that contains CTS */ | |
260 | struct ath_desc *axq_lastdsWithCTS; | |
261 | ||
262 | /* final desc of the gating desc that determines whether | |
263 | lastdsWithCTS has been DMA'ed or not */ | |
264 | struct ath_desc *axq_gatingds; | |
265 | ||
266 | struct list_head axq_acq; | |
267 | }; | |
268 | ||
269 | #define AGGR_CLEANUP BIT(1) | |
270 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
271 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
272 | ||
273 | /* per TID aggregate tx state for a destination */ | |
274 | struct ath_atx_tid { | |
275 | struct list_head list; /* round-robin tid entry */ | |
276 | struct list_head buf_q; /* pending buffers */ | |
277 | struct ath_node *an; | |
278 | struct ath_atx_ac *ac; | |
279 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ | |
280 | u16 seq_start; | |
281 | u16 seq_next; | |
282 | u16 baw_size; | |
283 | int tidno; | |
284 | int baw_head; /* first un-acked tx buffer */ | |
285 | int baw_tail; /* next unused tx buffer slot */ | |
286 | int sched; | |
287 | int paused; | |
288 | u8 state; | |
289 | int addba_exchangeattempts; | |
290 | }; | |
291 | ||
292 | /* per access-category aggregate tx state for a destination */ | |
293 | struct ath_atx_ac { | |
294 | int sched; /* dest-ac is scheduled */ | |
295 | int qnum; /* H/W queue number associated | |
296 | with this AC */ | |
297 | struct list_head list; /* round-robin txq entry */ | |
298 | struct list_head tid_q; /* queue of TIDs with buffers */ | |
299 | }; | |
300 | ||
301 | /* per-frame tx control block */ | |
302 | struct ath_tx_control { | |
303 | struct ath_txq *txq; | |
304 | int if_id; | |
305 | }; | |
306 | ||
307 | /* per frame tx status block */ | |
308 | struct ath_xmit_status { | |
309 | int retries; /* number of retries to successufully | |
310 | transmit this frame */ | |
311 | int flags; /* status of transmit */ | |
312 | #define ATH_TX_ERROR 0x01 | |
313 | #define ATH_TX_XRETRY 0x02 | |
314 | #define ATH_TX_BAR 0x04 | |
315 | }; | |
316 | ||
317 | /* All RSSI values are noise floor adjusted */ | |
318 | struct ath_tx_stat { | |
319 | int rssi; | |
320 | int rssictl[ATH_MAX_ANTENNA]; | |
321 | int rssiextn[ATH_MAX_ANTENNA]; | |
322 | int rateieee; | |
323 | int rateKbps; | |
324 | int ratecode; | |
325 | int flags; | |
326 | u32 airtime; /* time on air per final tx rate */ | |
327 | }; | |
328 | ||
329 | struct aggr_rifs_param { | |
330 | int param_max_frames; | |
331 | int param_max_len; | |
332 | int param_rl; | |
333 | int param_al; | |
334 | struct ath_rc_series *param_rcs; | |
335 | }; | |
336 | ||
337 | struct ath_node { | |
338 | struct ath_softc *an_sc; | |
339 | struct ath_atx_tid tid[WME_NUM_TID]; | |
340 | struct ath_atx_ac ac[WME_NUM_AC]; | |
341 | u16 maxampdu; | |
342 | u8 mpdudensity; | |
343 | }; | |
344 | ||
345 | struct ath_tx { | |
346 | u16 seq_no; | |
347 | u32 txqsetup; | |
348 | int hwq_map[ATH9K_WME_AC_VO+1]; | |
349 | spinlock_t txbuflock; | |
350 | struct list_head txbuf; | |
351 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
352 | struct ath_descdma txdma; | |
353 | }; | |
354 | ||
355 | struct ath_rx { | |
356 | u8 defant; | |
357 | u8 rxotherant; | |
358 | u32 *rxlink; | |
359 | int bufsize; | |
360 | unsigned int rxfilter; | |
361 | spinlock_t rxflushlock; | |
362 | spinlock_t rxbuflock; | |
363 | struct list_head rxbuf; | |
364 | struct ath_descdma rxdma; | |
365 | }; | |
366 | ||
367 | int ath_startrecv(struct ath_softc *sc); | |
368 | bool ath_stoprecv(struct ath_softc *sc); | |
369 | void ath_flushrecv(struct ath_softc *sc); | |
370 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
371 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
372 | void ath_rx_cleanup(struct ath_softc *sc); | |
373 | int ath_rx_tasklet(struct ath_softc *sc, int flush); | |
374 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); | |
375 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
376 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
377 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
378 | void ath_draintxq(struct ath_softc *sc, | |
379 | struct ath_txq *txq, bool retry_tx); | |
380 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
381 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
382 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
383 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
384 | int ath_tx_cleanup(struct ath_softc *sc); | |
385 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); | |
386 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
387 | struct ath9k_tx_queue_info *q); | |
388 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, | |
389 | struct ath_tx_control *txctl); | |
390 | void ath_tx_tasklet(struct ath_softc *sc); | |
391 | void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb); | |
392 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); | |
393 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
394 | u16 tid, u16 *ssn); | |
395 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
396 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
397 | ||
398 | /********/ | |
399 | /* VAPs */ | |
400 | /********/ | |
f078f209 | 401 | |
394cf0a1 S |
402 | /* |
403 | * Define the scheme that we select MAC address for multiple | |
404 | * BSS on the same radio. The very first VAP will just use the MAC | |
405 | * address from the EEPROM. For the next 3 VAPs, we set the | |
406 | * U/L bit (bit 1) in MAC address, and use the next two bits as the | |
407 | * index of the VAP. | |
408 | */ | |
f078f209 | 409 | |
394cf0a1 S |
410 | #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ |
411 | ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) | |
f078f209 | 412 | |
394cf0a1 S |
413 | struct ath_vap { |
414 | int av_bslot; | |
415 | enum nl80211_iftype av_opmode; | |
416 | struct ath_buf *av_bcbuf; | |
417 | struct ath_tx_control av_btxctl; | |
f078f209 LR |
418 | }; |
419 | ||
394cf0a1 S |
420 | /*******************/ |
421 | /* Beacon Handling */ | |
422 | /*******************/ | |
f078f209 | 423 | |
394cf0a1 S |
424 | /* |
425 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
426 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
427 | * number of beacon intervals, the game's up. | |
428 | */ | |
429 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
430 | #define ATH_BCBUF 1 | |
431 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ | |
432 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
433 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
434 | ||
435 | struct ath_beacon_config { | |
436 | u16 beacon_interval; | |
437 | u16 listen_interval; | |
438 | u16 dtim_period; | |
439 | u16 bmiss_timeout; | |
440 | u8 dtim_count; | |
441 | u8 tim_offset; | |
442 | union { | |
443 | u64 last_tsf; | |
444 | u8 last_tstamp[8]; | |
445 | } u; /* last received beacon/probe response timestamp of this BSS. */ | |
446 | }; | |
447 | ||
448 | struct ath_beacon { | |
449 | enum { | |
450 | OK, /* no change needed */ | |
451 | UPDATE, /* update pending */ | |
452 | COMMIT /* beacon sent, commit change */ | |
453 | } updateslot; /* slot time update fsm */ | |
454 | ||
455 | u32 beaconq; | |
456 | u32 bmisscnt; | |
457 | u32 ast_be_xmit; | |
458 | u64 bc_tstamp; | |
459 | int bslot[ATH_BCBUF]; | |
460 | int slottime; | |
461 | int slotupdate; | |
462 | struct ath9k_tx_queue_info beacon_qi; | |
463 | struct ath_descdma bdma; | |
464 | struct ath_txq *cabq; | |
465 | struct list_head bbuf; | |
466 | }; | |
467 | ||
468 | void ath9k_beacon_tasklet(unsigned long data); | |
469 | void ath_beacon_config(struct ath_softc *sc, int if_id); | |
470 | int ath_beaconq_setup(struct ath_hal *ah); | |
471 | int ath_beacon_alloc(struct ath_softc *sc, int if_id); | |
472 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); | |
473 | void ath_beacon_sync(struct ath_softc *sc, int if_id); | |
474 | ||
475 | /*******/ | |
476 | /* ANI */ | |
477 | /*******/ | |
f078f209 | 478 | |
394cf0a1 S |
479 | /* ANI values for STA only. |
480 | FIXME: Add appropriate values for AP later */ | |
f078f209 | 481 | |
394cf0a1 S |
482 | #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */ |
483 | #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */ | |
484 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */ | |
485 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ | |
f078f209 | 486 | |
394cf0a1 S |
487 | struct ath_ani { |
488 | bool sc_caldone; | |
489 | int16_t sc_noise_floor; | |
490 | unsigned int sc_longcal_timer; | |
491 | unsigned int sc_shortcal_timer; | |
492 | unsigned int sc_resetcal_timer; | |
493 | unsigned int sc_checkani_timer; | |
494 | struct timer_list timer; | |
f078f209 LR |
495 | }; |
496 | ||
394cf0a1 S |
497 | /********************/ |
498 | /* LED Control */ | |
499 | /********************/ | |
f078f209 | 500 | |
394cf0a1 S |
501 | #define ATH_LED_PIN 1 |
502 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ | |
503 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 504 | |
394cf0a1 S |
505 | enum ath_led_type { |
506 | ATH_LED_RADIO, | |
507 | ATH_LED_ASSOC, | |
508 | ATH_LED_TX, | |
509 | ATH_LED_RX | |
f078f209 LR |
510 | }; |
511 | ||
394cf0a1 S |
512 | struct ath_led { |
513 | struct ath_softc *sc; | |
514 | struct led_classdev led_cdev; | |
515 | enum ath_led_type led_type; | |
516 | char name[32]; | |
517 | bool registered; | |
f078f209 LR |
518 | }; |
519 | ||
394cf0a1 S |
520 | /* Rfkill */ |
521 | #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ | |
f078f209 | 522 | |
394cf0a1 S |
523 | struct ath_rfkill { |
524 | struct rfkill *rfkill; | |
525 | struct delayed_work rfkill_poll; | |
526 | char rfkill_name[32]; | |
f078f209 LR |
527 | }; |
528 | ||
394cf0a1 S |
529 | /********************/ |
530 | /* Main driver core */ | |
531 | /********************/ | |
f078f209 | 532 | |
394cf0a1 S |
533 | /* |
534 | * Default cache line size, in bytes. | |
535 | * Used when PCI device not fully initialized by bootrom/BIOS | |
536 | */ | |
537 | #define DEFAULT_CACHELINE 32 | |
538 | #define ATH_DEFAULT_NOISE_FLOOR -95 | |
539 | #define ATH_REGCLASSIDS_MAX 10 | |
540 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
541 | #define ATH_MAX_SW_RETRIES 10 | |
542 | #define ATH_CHAN_MAX 255 | |
543 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 544 | |
394cf0a1 S |
545 | /* |
546 | * The key cache is used for h/w cipher state and also for | |
547 | * tracking station state such as the current tx antenna. | |
548 | * We also setup a mapping table between key cache slot indices | |
549 | * and station state to short-circuit node lookups on rx. | |
550 | * Different parts have different size key caches. We handle | |
551 | * up to ATH_KEYMAX entries (could dynamically allocate state). | |
552 | */ | |
553 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | |
554 | ||
555 | #define ATH_IF_ID_ANY 0xff | |
556 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ | |
557 | #define ATH_RSSI_DUMMY_MARKER 0x127 | |
558 | #define ATH_RATE_DUMMY_MARKER 0 | |
559 | ||
560 | #define SC_OP_INVALID BIT(0) | |
561 | #define SC_OP_BEACONS BIT(1) | |
562 | #define SC_OP_RXAGGR BIT(2) | |
563 | #define SC_OP_TXAGGR BIT(3) | |
564 | #define SC_OP_CHAINMASK_UPDATE BIT(4) | |
565 | #define SC_OP_FULL_RESET BIT(5) | |
566 | #define SC_OP_NO_RESET BIT(6) | |
567 | #define SC_OP_PREAMBLE_SHORT BIT(7) | |
568 | #define SC_OP_PROTECT_ENABLE BIT(8) | |
569 | #define SC_OP_RXFLUSH BIT(9) | |
570 | #define SC_OP_LED_ASSOCIATED BIT(10) | |
571 | #define SC_OP_RFKILL_REGISTERED BIT(11) | |
572 | #define SC_OP_RFKILL_SW_BLOCKED BIT(12) | |
573 | #define SC_OP_RFKILL_HW_BLOCKED BIT(13) | |
574 | #define SC_OP_WAIT_FOR_BEACON BIT(14) | |
575 | #define SC_OP_LED_ON BIT(15) | |
576 | ||
577 | struct ath_bus_ops { | |
578 | void (*read_cachesize)(struct ath_softc *sc, int *csz); | |
579 | void (*cleanup)(struct ath_softc *sc); | |
580 | bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); | |
581 | }; | |
582 | ||
583 | struct ath_softc { | |
584 | struct ieee80211_hw *hw; | |
585 | struct device *dev; | |
586 | struct tasklet_struct intr_tq; | |
587 | struct tasklet_struct bcon_tasklet; | |
588 | struct ath_hal *sc_ah; | |
589 | void __iomem *mem; | |
590 | int irq; | |
591 | spinlock_t sc_resetlock; | |
592 | struct mutex mutex; | |
593 | ||
594 | u8 sc_curbssid[ETH_ALEN]; | |
595 | u8 sc_myaddr[ETH_ALEN]; | |
596 | u8 sc_bssidmask[ETH_ALEN]; | |
597 | u32 sc_intrstatus; | |
598 | u32 sc_flags; /* SC_OP_* */ | |
599 | u16 sc_curtxpow; | |
600 | u16 sc_curaid; | |
601 | u16 sc_cachelsz; | |
602 | u8 sc_nbcnvaps; | |
603 | u16 sc_nvaps; | |
604 | u8 sc_tx_chainmask; | |
605 | u8 sc_rx_chainmask; | |
606 | u32 sc_keymax; | |
607 | DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); | |
608 | u8 sc_splitmic; | |
609 | atomic_t ps_usecount; | |
610 | enum ath9k_int sc_imask; | |
611 | enum ath9k_ht_extprotspacing sc_ht_extprotspacing; | |
612 | enum ath9k_ht_macmode tx_chan_width; | |
613 | ||
614 | struct ath_config sc_config; | |
615 | struct ath_rx rx; | |
616 | struct ath_tx tx; | |
617 | struct ath_beacon beacon; | |
618 | struct ieee80211_vif *sc_vaps[ATH_BCBUF]; | |
619 | struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; | |
620 | struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; | |
621 | struct ath_rate_table *cur_rate_table; | |
622 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; | |
623 | ||
624 | struct ath_led radio_led; | |
625 | struct ath_led assoc_led; | |
626 | struct ath_led tx_led; | |
627 | struct ath_led rx_led; | |
628 | struct delayed_work ath_led_blink_work; | |
629 | int led_on_duration; | |
630 | int led_off_duration; | |
631 | int led_on_cnt; | |
632 | int led_off_cnt; | |
633 | ||
634 | struct ath_rfkill rf_kill; | |
635 | struct ath_ani sc_ani; | |
636 | struct ath9k_node_stats sc_halstats; | |
637 | #ifdef CONFIG_ATH9K_DEBUG | |
638 | struct ath9k_debug sc_debug; | |
639 | #endif | |
640 | struct ath_bus_ops *bus_ops; | |
641 | }; | |
642 | ||
643 | int ath_reset(struct ath_softc *sc, bool retry_tx); | |
644 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |
645 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | |
646 | int ath_cabq_update(struct ath_softc *); | |
647 | ||
648 | static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) | |
649 | { | |
650 | sc->bus_ops->read_cachesize(sc, csz); | |
651 | } | |
652 | ||
653 | static inline void ath_bus_cleanup(struct ath_softc *sc) | |
654 | { | |
655 | sc->bus_ops->cleanup(sc); | |
656 | } | |
657 | ||
658 | extern struct ieee80211_ops ath9k_ops; | |
659 | ||
660 | irqreturn_t ath_isr(int irq, void *dev); | |
661 | void ath_cleanup(struct ath_softc *sc); | |
662 | int ath_attach(u16 devid, struct ath_softc *sc); | |
663 | void ath_detach(struct ath_softc *sc); | |
664 | const char *ath_mac_bb_name(u32 mac_bb_version); | |
665 | const char *ath_rf_name(u16 rf_version); | |
666 | ||
667 | #ifdef CONFIG_PCI | |
668 | int ath_pci_init(void); | |
669 | void ath_pci_exit(void); | |
670 | #else | |
671 | static inline int ath_pci_init(void) { return 0; }; | |
672 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 673 | #endif |
f1dc5600 | 674 | |
394cf0a1 S |
675 | #ifdef CONFIG_ATHEROS_AR71XX |
676 | int ath_ahb_init(void); | |
677 | void ath_ahb_exit(void); | |
678 | #else | |
679 | static inline int ath_ahb_init(void) { return 0; }; | |
680 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 681 | #endif |
394cf0a1 S |
682 | |
683 | static inline void ath9k_ps_wakeup(struct ath_softc *sc) | |
684 | { | |
685 | if (atomic_inc_return(&sc->ps_usecount) == 1) | |
686 | if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { | |
687 | sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; | |
688 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
689 | } | |
690 | } | |
691 | ||
692 | static inline void ath9k_ps_restore(struct ath_softc *sc) | |
693 | { | |
694 | if (atomic_dec_and_test(&sc->ps_usecount)) | |
695 | if (sc->hw->conf.flags & IEEE80211_CONF_PS) | |
696 | ath9k_hw_setpower(sc->sc_ah, | |
697 | sc->sc_ah->ah_restore_mode); | |
698 | } | |
699 | #endif /* ATH9K_H */ |