]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/ath9k/hw.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2400,rt2500: init led_qual for LED_MODE_DEFAULT
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / hw.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
20#include "core.h"
21#include "hw.h"
22#include "reg.h"
23#include "phy.h"
24#include "initvals.h"
25
4febf7b8
LR		 26#define ATH9K_CLOCK_RATE_CCK 22
27#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
28#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 29
f1dc5600
S		 30static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
31static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
32 enum ath9k_ht_macmode macmode);
33static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
e7594072 34 struct ar5416_eeprom_def *pEepData,
f1dc5600
S		 35 u32 reg, u32 value);
36static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
37static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
f078f209 38
f1dc5600
S		 39/********************/
40/* Helper Functions */
41/********************/
f078f209 42
f1dc5600
S		 43static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
44{
4febf7b8
LR		 45 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
46 if (!ah->ah_curchan) /* should really check for CCK instead */
47 return clks / ATH9K_CLOCK_RATE_CCK;
48 if (conf->channel->band == IEEE80211_BAND_2GHZ)
49 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 51}
f078f209 52
f1dc5600
S		 53static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
54{
4febf7b8
LR		 55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
56 if (conf_is_ht40(conf))
f1dc5600
S		 57 return ath9k_hw_mac_usec(ah, clks) / 2;
58 else
59 return ath9k_hw_mac_usec(ah, clks);
60}
f078f209 61
f1dc5600
S		 62static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
63{
4febf7b8
LR		 64 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
65 if (!ah->ah_curchan) /* should really check for CCK instead */
66 return usecs *ATH9K_CLOCK_RATE_CCK;
67 if (conf->channel->band == IEEE80211_BAND_2GHZ)
68 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
69 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 70}
71
72static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
73{
4febf7b8
LR		 74 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
75 if (conf_is_ht40(conf))
f1dc5600
S		 76 return ath9k_hw_mac_clks(ah, usecs) * 2;
77 else
78 return ath9k_hw_mac_clks(ah, usecs);
79}
f078f209 80
f1dc5600 81bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
f078f209
LR		 82{
83 int i;
84
85 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
86 if ((REG_READ(ah, reg) & mask) == val)
87 return true;
88
89 udelay(AH_TIME_QUANTUM);
90 }
04bd4638
S		 91
92 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
93 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
94 reg, REG_READ(ah, reg), mask, val);
f078f209 95
f1dc5600 96 return false;
f078f209
LR		 97}
98
99u32 ath9k_hw_reverse_bits(u32 val, u32 n)
100{
101 u32 retval;
102 int i;
103
104 for (i = 0, retval = 0; i < n; i++) {
105 retval = (retval << 1) | (val & 1);
106 val >>= 1;
107 }
108 return retval;
109}
110
f1dc5600
S		 111bool ath9k_get_channel_edges(struct ath_hal *ah,
112 u16 flags, u16 *low,
113 u16 *high)
f078f209 114{
f1dc5600 115 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 116
f1dc5600
S		 117 if (flags & CHANNEL_5GHZ) {
118 *low = pCap->low_5ghz_chan;
119 *high = pCap->high_5ghz_chan;
120 return true;
f078f209 121 }
f1dc5600
S		 122 if ((flags & CHANNEL_2GHZ)) {
123 *low = pCap->low_2ghz_chan;
124 *high = pCap->high_2ghz_chan;
125 return true;
126 }
127 return false;
f078f209
LR		 128}
129
f1dc5600 130u16 ath9k_hw_computetxtime(struct ath_hal *ah,
e63835b0 131 struct ath_rate_table *rates,
f1dc5600
S		 132 u32 frameLen, u16 rateix,
133 bool shortPreamble)
f078f209 134{
f1dc5600
S		 135 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
136 u32 kbps;
f078f209 137
e63835b0 138 kbps = rates->info[rateix].ratekbps;
f078f209 139
f1dc5600
S		 140 if (kbps == 0)
141 return 0;
f078f209 142
f1dc5600 143 switch (rates->info[rateix].phy) {
46d14a58 144 case WLAN_RC_PHY_CCK:
f1dc5600 145 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 146 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 147 phyTime >>= 1;
148 numBits = frameLen << 3;
149 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
150 break;
46d14a58 151 case WLAN_RC_PHY_OFDM:
f1dc5600
S		 152 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
153 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
154 numBits = OFDM_PLCP_BITS + (frameLen << 3);
155 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
156 txTime = OFDM_SIFS_TIME_QUARTER
157 + OFDM_PREAMBLE_TIME_QUARTER
158 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
159 } else if (ah->ah_curchan &&
160 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_HALF +
165 OFDM_PREAMBLE_TIME_HALF
166 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
167 } else {
168 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
169 numBits = OFDM_PLCP_BITS + (frameLen << 3);
170 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
171 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
172 + (numSymbols * OFDM_SYMBOL_TIME);
173 }
174 break;
175 default:
04bd4638
S		 176 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
177 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 178 rates->info[rateix].phy, rateix);
179 txTime = 0;
180 break;
181 }
f078f209 182
f1dc5600
S		 183 return txTime;
184}
f078f209 185
f1dc5600
S		 186u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
187{
188 if (flags & CHANNEL_2GHZ) {
189 if (freq == 2484)
190 return 14;
191 if (freq < 2484)
192 return (freq - 2407) / 5;
193 else
194 return 15 + ((freq - 2512) / 20);
195 } else if (flags & CHANNEL_5GHZ) {
196 if (ath9k_regd_is_public_safety_sku(ah) &&
197 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
198 return ((freq * 10) +
199 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
200 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
201 return (freq - 4000) / 5;
202 } else {
203 return (freq - 5000) / 5;
204 }
205 } else {
206 if (freq == 2484)
207 return 14;
208 if (freq < 2484)
209 return (freq - 2407) / 5;
210 if (freq < 5000) {
211 if (ath9k_regd_is_public_safety_sku(ah)
212 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
213 return ((freq * 10) +
214 (((freq % 5) ==
215 2) ? 5 : 0) - 49400) / 5;
216 } else if (freq > 4900) {
217 return (freq - 4000) / 5;
218 } else {
219 return 15 + ((freq - 2512) / 20);
220 }
221 }
222 return (freq - 5000) / 5;
223 }
f078f209
LR		 224}
225
f1dc5600
S		 226void ath9k_hw_get_channel_centers(struct ath_hal *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
f078f209 229{
f1dc5600 230 int8_t extoff;
f078f209
LR		 231 struct ath_hal_5416 *ahp = AH5416(ah);
232
f1dc5600
S		 233 if (!IS_CHAN_HT40(chan)) {
234 centers->ctl_center = centers->ext_center =
235 centers->synth_center = chan->channel;
236 return;
f078f209 237 }
f078f209 238
f1dc5600
S		 239 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
240 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
241 centers->synth_center =
242 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
243 extoff = 1;
244 } else {
245 centers->synth_center =
246 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
247 extoff = -1;
248 }
f078f209 249
f1dc5600
S		 250 centers->ctl_center =
251 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
252 centers->ext_center =
253 centers->synth_center + (extoff *
254 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
255 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209 256
f078f209
LR		 257}
258
f1dc5600
S		 259/******************/
260/* Chip Revisions */
261/******************/
262
263static void ath9k_hw_read_revisions(struct ath_hal *ah)
f078f209 264{
f1dc5600 265 u32 val;
f078f209 266
f1dc5600 267 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 268
f1dc5600
S		 269 if (val == 0xFF) {
270 val = REG_READ(ah, AR_SREV);
271 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
272 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
273 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
274 } else {
275 if (!AR_SREV_9100(ah))
276 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
f078f209 277
f1dc5600 278 ah->ah_macRev = val & AR_SREV_REVISION;
f078f209 279
f1dc5600
S		 280 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
281 ah->ah_isPciExpress = true;
282 }
f078f209
LR		 283}
284
f1dc5600 285static int ath9k_hw_get_radiorev(struct ath_hal *ah)
f078f209 286{
f1dc5600
S		 287 u32 val;
288 int i;
f078f209 289
f1dc5600 290 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 291
f1dc5600
S		 292 for (i = 0; i < 8; i++)
293 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
294 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
295 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 296
f1dc5600 297 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 298}
299
f1dc5600
S		 300/************************************/
301/* HW Attach, Detach, Init Routines */
302/************************************/
303
304static void ath9k_hw_disablepcie(struct ath_hal *ah)
f078f209 305{
f1dc5600
S		 306 if (!AR_SREV_9100(ah))
307 return;
f078f209 308
f1dc5600
S		 309 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 318
f1dc5600 319 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 320}
321
f1dc5600 322static bool ath9k_hw_chip_test(struct ath_hal *ah)
f078f209 323{
f1dc5600
S		 324 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
325 u32 regHold[2];
326 u32 patternData[4] = { 0x55555555,
327 0xaaaaaaaa,
328 0x66666666,
329 0x99999999 };
330 int i, j;
f078f209 331
f1dc5600
S		 332 for (i = 0; i < 2; i++) {
333 u32 addr = regAddr[i];
334 u32 wrData, rdData;
f078f209 335
f1dc5600
S		 336 regHold[i] = REG_READ(ah, addr);
337 for (j = 0; j < 0x100; j++) {
338 wrData = (j << 16) | j;
339 REG_WRITE(ah, addr, wrData);
340 rdData = REG_READ(ah, addr);
341 if (rdData != wrData) {
342 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 343 "address test failed "
f1dc5600 344 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 345 addr, wrData, rdData);
f1dc5600
S		 346 return false;
347 }
348 }
349 for (j = 0; j < 4; j++) {
350 wrData = patternData[j];
351 REG_WRITE(ah, addr, wrData);
352 rdData = REG_READ(ah, addr);
353 if (wrData != rdData) {
354 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 355 "address test failed "
f1dc5600 356 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 357 addr, wrData, rdData);
f1dc5600
S		 358 return false;
359 }
f078f209 360 }
f1dc5600 361 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 362 }
f1dc5600 363 udelay(100);
f078f209
LR		 364 return true;
365}
366
f1dc5600 367static const char *ath9k_hw_devname(u16 devid)
f078f209 368{
f1dc5600
S		 369 switch (devid) {
370 case AR5416_DEVID_PCI:
f1dc5600 371 return "Atheros 5416";
392dff83
BP		 372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
f1dc5600
S		 374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR9280_DEVID_PCI:
377 case AR9280_DEVID_PCIE:
378 return "Atheros 9280";
e7594072
SB		 379 case AR9285_DEVID_PCIE:
380 return "Atheros 9285";
f078f209
LR		 381 }
382
f1dc5600
S		 383 return NULL;
384}
f078f209 385
f1dc5600
S		 386static void ath9k_hw_set_defaults(struct ath_hal *ah)
387{
388 int i;
f078f209 389
f1dc5600
S		 390 ah->ah_config.dma_beacon_response_time = 2;
391 ah->ah_config.sw_beacon_response_time = 10;
392 ah->ah_config.additional_swba_backoff = 0;
393 ah->ah_config.ack_6mb = 0x0;
394 ah->ah_config.cwm_ignore_extcca = 0;
395 ah->ah_config.pcie_powersave_enable = 0;
396 ah->ah_config.pcie_l1skp_enable = 0;
397 ah->ah_config.pcie_clock_req = 0;
398 ah->ah_config.pcie_power_reset = 0x100;
399 ah->ah_config.pcie_restore = 0;
400 ah->ah_config.pcie_waen = 0;
401 ah->ah_config.analog_shiftreg = 1;
402 ah->ah_config.ht_enable = 1;
403 ah->ah_config.ofdm_trig_low = 200;
404 ah->ah_config.ofdm_trig_high = 500;
405 ah->ah_config.cck_trig_high = 200;
406 ah->ah_config.cck_trig_low = 100;
407 ah->ah_config.enable_ani = 1;
408 ah->ah_config.noise_immunity_level = 4;
409 ah->ah_config.ofdm_weaksignal_det = 1;
410 ah->ah_config.cck_weaksignal_thr = 0;
411 ah->ah_config.spur_immunity_level = 2;
412 ah->ah_config.firstep_level = 0;
413 ah->ah_config.rssi_thr_high = 40;
414 ah->ah_config.rssi_thr_low = 7;
415 ah->ah_config.diversity_control = 0;
416 ah->ah_config.antenna_switch_swap = 0;
f078f209 417
f1dc5600
S		 418 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
419 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
420 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 421 }
422
f1dc5600 423 ah->ah_config.intr_mitigation = 1;
f078f209
LR		 424}
425
f078f209
LR		 426static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
427 struct ath_softc *sc,
428 void __iomem *mem,
429 int *status)
430{
431 static const u8 defbssidmask[ETH_ALEN] =
432 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
433 struct ath_hal_5416 *ahp;
434 struct ath_hal *ah;
435
436 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
437 if (ahp == NULL) {
438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 439 "Cannot allocate memory for state block\n");
f078f209
LR		 440 *status = -ENOMEM;
441 return NULL;
442 }
443
444 ah = &ahp->ah;
f078f209
LR		 445 ah->ah_sc = sc;
446 ah->ah_sh = mem;
d2d80ee9
S		 447 ah->ah_magic = AR5416_MAGIC;
448 ah->ah_countryCode = CTRY_DEFAULT;
f078f209
LR		 449 ah->ah_devid = devid;
450 ah->ah_subvendorid = 0;
451
452 ah->ah_flags = 0;
453 if ((devid == AR5416_AR9100_DEVID))
454 ah->ah_macVersion = AR_SREV_VERSION_9100;
455 if (!AR_SREV_9100(ah))
456 ah->ah_flags = AH_USE_EEPROM;
457
458 ah->ah_powerLimit = MAX_RATE_POWER;
459 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
f078f209 460 ahp->ah_atimWindow = 0;
60b67f51 461 ahp->ah_diversityControl = ah->ah_config.diversity_control;
f078f209 462 ahp->ah_antennaSwitchSwap =
60b67f51 463 ah->ah_config.antenna_switch_swap;
f078f209
LR		 464 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
465 ahp->ah_beaconInterval = 100;
466 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
467 ahp->ah_slottime = (u32) -1;
468 ahp->ah_acktimeout = (u32) -1;
469 ahp->ah_ctstimeout = (u32) -1;
470 ahp->ah_globaltxtimeout = (u32) -1;
471 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
472
473 ahp->ah_gBeaconRate = 0;
474
475 return ahp;
476}
477
f1dc5600 478static int ath9k_hw_rfattach(struct ath_hal *ah)
f078f209 479{
f1dc5600
S		 480 bool rfStatus = false;
481 int ecode = 0;
f078f209 482
f1dc5600
S		 483 rfStatus = ath9k_hw_init_rf(ah, &ecode);
484 if (!rfStatus) {
485 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 486 "RF setup failed, status %u\n", ecode);
f1dc5600
S		 487 return ecode;
488 }
f078f209 489
f1dc5600 490 return 0;
f078f209
LR		 491}
492
f1dc5600 493static int ath9k_hw_rf_claim(struct ath_hal *ah)
f078f209 494{
f1dc5600
S		 495 u32 val;
496
497 REG_WRITE(ah, AR_PHY(0), 0x00000007);
498
499 val = ath9k_hw_get_radiorev(ah);
500 switch (val & AR_RADIO_SREV_MAJOR) {
501 case 0:
502 val = AR_RAD5133_SREV_MAJOR;
503 break;
504 case AR_RAD5133_SREV_MAJOR:
505 case AR_RAD5122_SREV_MAJOR:
506 case AR_RAD2133_SREV_MAJOR:
507 case AR_RAD2122_SREV_MAJOR:
508 break;
f078f209 509 default:
f1dc5600 510 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 511 "5G Radio Chip Rev 0x%02X is not "
f1dc5600 512 "supported by this driver\n",
04bd4638 513 ah->ah_analog5GhzRev);
f1dc5600 514 return -EOPNOTSUPP;
f078f209 515 }
f078f209 516
f1dc5600 517 ah->ah_analog5GhzRev = val;
f078f209 518
f1dc5600 519 return 0;
f078f209
LR		 520}
521
ff9b662d 522static int ath9k_hw_init_macaddr(struct ath_hal *ah)
f078f209
LR		 523{
524 u32 sum;
525 int i;
526 u16 eeval;
527 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 528
529 sum = 0;
530 for (i = 0; i < 3; i++) {
f1dc5600 531 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209
LR		 532 sum += eeval;
533 ahp->ah_macaddr[2 * i] = eeval >> 8;
534 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
535 }
536 if (sum == 0 || sum == 0xffff * 3) {
537 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 538 "mac address read failed: %pM\n",
f1dc5600 539 ahp->ah_macaddr);
f078f209
LR		 540 return -EADDRNOTAVAIL;
541 }
542
543 return 0;
544}
545
9f804202
SB		 546static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
547{
548 u32 rxgain_type;
549 struct ath_hal_5416 *ahp = AH5416(ah);
550
551 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
552 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
553
554 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
555 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
556 ar9280Modes_backoff_13db_rxgain_9280_2,
557 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
558 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
559 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
560 ar9280Modes_backoff_23db_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
562 else
563 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
564 ar9280Modes_original_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
566 } else
567 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
568 ar9280Modes_original_rxgain_9280_2,
569 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
570}
571
572static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
573{
574 u32 txgain_type;
575 struct ath_hal_5416 *ahp = AH5416(ah);
576
577 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
578 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
579
580 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
581 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
582 ar9280Modes_high_power_tx_gain_9280_2,
583 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
584 else
585 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
586 ar9280Modes_original_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
588 } else
589 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
590 ar9280Modes_original_tx_gain_9280_2,
591 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
592}
593
f1dc5600 594static int ath9k_hw_post_attach(struct ath_hal *ah)
f078f209 595{
f1dc5600 596 int ecode;
f078f209 597
f1dc5600
S		 598 if (!ath9k_hw_chip_test(ah)) {
599 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 600 "hardware self-test failed\n");
f1dc5600 601 return -ENODEV;
f078f209 602 }
f078f209 603
f1dc5600
S		 604 ecode = ath9k_hw_rf_claim(ah);
605 if (ecode != 0)
f078f209 606 return ecode;
f078f209 607
f1dc5600
S		 608 ecode = ath9k_hw_eeprom_attach(ah);
609 if (ecode != 0)
610 return ecode;
611 ecode = ath9k_hw_rfattach(ah);
612 if (ecode != 0)
613 return ecode;
f078f209 614
f1dc5600
S		 615 if (!AR_SREV_9100(ah)) {
616 ath9k_hw_ani_setup(ah);
617 ath9k_hw_ani_attach(ah);
f078f209
LR		 618 }
619
f078f209
LR		 620 return 0;
621}
622
f1dc5600
S		 623static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
624 void __iomem *mem, int *status)
f078f209 625{
f1dc5600
S		 626 struct ath_hal_5416 *ahp;
627 struct ath_hal *ah;
628 int ecode;
f6688cd8 629 u32 i, j;
f078f209 630
f1dc5600
S		 631 ahp = ath9k_hw_newstate(devid, sc, mem, status);
632 if (ahp == NULL)
633 return NULL;
f078f209 634
f1dc5600 635 ah = &ahp->ah;
f078f209 636
f1dc5600 637 ath9k_hw_set_defaults(ah);
f078f209 638
f1dc5600
S		 639 if (ah->ah_config.intr_mitigation != 0)
640 ahp->ah_intrMitigation = true;
f078f209 641
f1dc5600 642 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
04bd4638 643 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
f1dc5600
S		 644 ecode = -EIO;
645 goto bad;
646 }
f078f209 647
f1dc5600 648 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
04bd4638 649 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
f1dc5600
S		 650 ecode = -EIO;
651 goto bad;
652 }
f078f209 653
f1dc5600
S		 654 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
655 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
656 ah->ah_config.serialize_regmode =
657 SER_REG_MODE_ON;
f078f209 658 } else {
f1dc5600
S		 659 ah->ah_config.serialize_regmode =
660 SER_REG_MODE_OFF;
f078f209
LR		 661 }
662 }
f078f209 663
f1dc5600 664 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 665 "serialize_regmode is %d\n",
666 ah->ah_config.serialize_regmode);
f078f209 667
f1dc5600
S		 668 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
669 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
670 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
e7594072 671 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
f1dc5600 672 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 673 "Mac Chip Rev 0x%02x.%x is not supported by "
674 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
f1dc5600
S		 675 ecode = -EOPNOTSUPP;
676 goto bad;
677 }
f078f209 678
f1dc5600
S		 679 if (AR_SREV_9100(ah)) {
680 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
681 ahp->ah_suppCals = IQ_MISMATCH_CAL;
682 ah->ah_isPciExpress = false;
683 }
684 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
f078f209 685
f1dc5600
S		 686 if (AR_SREV_9160_10_OR_LATER(ah)) {
687 if (AR_SREV_9280_10_OR_LATER(ah)) {
688 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
689 ahp->ah_adcGainCalData.calData =
690 &adc_gain_cal_single_sample;
691 ahp->ah_adcDcCalData.calData =
692 &adc_dc_cal_single_sample;
693 ahp->ah_adcDcCalInitData.calData =
694 &adc_init_dc_cal;
695 } else {
696 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
697 ahp->ah_adcGainCalData.calData =
698 &adc_gain_cal_multi_sample;
699 ahp->ah_adcDcCalData.calData =
700 &adc_dc_cal_multi_sample;
701 ahp->ah_adcDcCalInitData.calData =
702 &adc_init_dc_cal;
703 }
704 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
705 }
f078f209 706
f1dc5600
S		 707 if (AR_SREV_9160(ah)) {
708 ah->ah_config.enable_ani = 1;
709 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
710 ATH9K_ANI_FIRSTEP_LEVEL);
711 } else {
712 ahp->ah_ani_function = ATH9K_ANI_ALL;
713 if (AR_SREV_9280_10_OR_LATER(ah)) {
714 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
715 }
f078f209 716 }
f078f209 717
f1dc5600 718 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 719 "This Mac Chip Rev 0x%02x.%x is \n",
f1dc5600 720 ah->ah_macVersion, ah->ah_macRev);
f078f209 721
e7594072
SB		 722 if (AR_SREV_9285_12_OR_LATER(ah)) {
723 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
724 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
725 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
726 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
727
728 if (ah->ah_config.pcie_clock_req) {
729 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
730 ar9285PciePhy_clkreq_off_L1_9285_1_2,
731 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
732 } else {
733 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
734 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
735 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
736 2);
737 }
738 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
739 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
740 ARRAY_SIZE(ar9285Modes_9285), 6);
741 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
742 ARRAY_SIZE(ar9285Common_9285), 2);
743
744 if (ah->ah_config.pcie_clock_req) {
745 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
746 ar9285PciePhy_clkreq_off_L1_9285,
747 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
748 } else {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9285PciePhy_clkreq_always_on_L1_9285,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
752 }
753 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
f1dc5600
S		 754 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
755 ARRAY_SIZE(ar9280Modes_9280_2), 6);
756 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
757 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 758
f1dc5600
S		 759 if (ah->ah_config.pcie_clock_req) {
760 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
761 ar9280PciePhy_clkreq_off_L1_9280,
762 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
763 } else {
764 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
765 ar9280PciePhy_clkreq_always_on_L1_9280,
766 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
767 }
768 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
769 ar9280Modes_fast_clock_9280_2,
770 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
771 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
772 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
773 ARRAY_SIZE(ar9280Modes_9280), 6);
774 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
775 ARRAY_SIZE(ar9280Common_9280), 2);
776 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
777 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
778 ARRAY_SIZE(ar5416Modes_9160), 6);
779 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
780 ARRAY_SIZE(ar5416Common_9160), 2);
781 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
782 ARRAY_SIZE(ar5416Bank0_9160), 2);
783 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
784 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
786 ARRAY_SIZE(ar5416Bank1_9160), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
788 ARRAY_SIZE(ar5416Bank2_9160), 2);
789 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
790 ARRAY_SIZE(ar5416Bank3_9160), 3);
791 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
792 ARRAY_SIZE(ar5416Bank6_9160), 3);
793 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
794 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
795 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
796 ARRAY_SIZE(ar5416Bank7_9160), 2);
797 if (AR_SREV_9160_11(ah)) {
798 INIT_INI_ARRAY(&ahp->ah_iniAddac,
799 ar5416Addac_91601_1,
800 ARRAY_SIZE(ar5416Addac_91601_1), 2);
801 } else {
802 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
803 ARRAY_SIZE(ar5416Addac_9160), 2);
804 }
805 } else if (AR_SREV_9100_OR_LATER(ah)) {
806 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
807 ARRAY_SIZE(ar5416Modes_9100), 6);
808 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
809 ARRAY_SIZE(ar5416Common_9100), 2);
810 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
811 ARRAY_SIZE(ar5416Bank0_9100), 2);
812 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
813 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
814 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
815 ARRAY_SIZE(ar5416Bank1_9100), 2);
816 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
817 ARRAY_SIZE(ar5416Bank2_9100), 2);
818 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
819 ARRAY_SIZE(ar5416Bank3_9100), 3);
820 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
821 ARRAY_SIZE(ar5416Bank6_9100), 3);
822 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
823 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
824 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
825 ARRAY_SIZE(ar5416Bank7_9100), 2);
826 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
827 ARRAY_SIZE(ar5416Addac_9100), 2);
828 } else {
829 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
830 ARRAY_SIZE(ar5416Modes), 6);
831 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
832 ARRAY_SIZE(ar5416Common), 2);
833 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
834 ARRAY_SIZE(ar5416Bank0), 2);
835 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
836 ARRAY_SIZE(ar5416BB_RfGain), 3);
837 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
838 ARRAY_SIZE(ar5416Bank1), 2);
839 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
840 ARRAY_SIZE(ar5416Bank2), 2);
841 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
842 ARRAY_SIZE(ar5416Bank3), 3);
843 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
844 ARRAY_SIZE(ar5416Bank6), 3);
845 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
846 ARRAY_SIZE(ar5416Bank6TPC), 3);
847 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
848 ARRAY_SIZE(ar5416Bank7), 2);
849 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
850 ARRAY_SIZE(ar5416Addac), 2);
f078f209 851 }
f078f209 852
f1dc5600
S		 853 if (ah->ah_isPciExpress)
854 ath9k_hw_configpcipowersave(ah, 0);
855 else
856 ath9k_hw_disablepcie(ah);
f078f209 857
f1dc5600
S		 858 ecode = ath9k_hw_post_attach(ah);
859 if (ecode != 0)
860 goto bad;
f078f209 861
9f804202 862 /* rxgain table */
e7594072 863 if (AR_SREV_9280_20(ah))
9f804202
SB		 864 ath9k_hw_init_rxgain_ini(ah);
865
866 /* txgain table */
e7594072 867 if (AR_SREV_9280_20(ah))
9f804202
SB		 868 ath9k_hw_init_txgain_ini(ah);
869
f1dc5600
S		 870 if (ah->ah_devid == AR9280_DEVID_PCI) {
871 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
872 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
f078f209 873
f1dc5600
S		 874 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
875 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
f078f209 876
f1dc5600 877 INI_RA(&ahp->ah_iniModes, i, j) =
e7594072
SB		 878 ath9k_hw_ini_fixup(ah,
879 &ahp->ah_eeprom.def,
f1dc5600
S		 880 reg, val);
881 }
f078f209 882 }
f1dc5600 883 }
f6688cd8 884
f1dc5600
S		 885 if (!ath9k_hw_fill_cap_info(ah)) {
886 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 887 "failed ath9k_hw_fill_cap_info\n");
f1dc5600
S		 888 ecode = -EINVAL;
889 goto bad;
f078f209
LR		 890 }
891
f1dc5600
S		 892 ecode = ath9k_hw_init_macaddr(ah);
893 if (ecode != 0) {
f078f209 894 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 895 "failed initializing mac address\n");
f1dc5600 896 goto bad;
f078f209
LR		 897 }
898
f1dc5600
S		 899 if (AR_SREV_9285(ah))
900 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
901 else
902 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 903
f1dc5600 904 ath9k_init_nfcal_hist_buffer(ah);
f078f209 905
f1dc5600
S		 906 return ah;
907bad:
908 if (ahp)
909 ath9k_hw_detach((struct ath_hal *) ahp);
910 if (status)
911 *status = ecode;
f078f209 912
f1dc5600 913 return NULL;
f078f209
LR		 914}
915
f1dc5600
S		 916static void ath9k_hw_init_bb(struct ath_hal *ah,
917 struct ath9k_channel *chan)
f078f209 918{
f1dc5600 919 u32 synthDelay;
f078f209 920
f1dc5600 921 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 922 if (IS_CHAN_B(chan))
f1dc5600
S		 923 synthDelay = (4 * synthDelay) / 22;
924 else
925 synthDelay /= 10;
f078f209 926
f1dc5600 927 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 928
f1dc5600 929 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 930}
931
f1dc5600 932static void ath9k_hw_init_qos(struct ath_hal *ah)
f078f209 933{
f1dc5600
S		 934 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
935 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 936
f1dc5600
S		 937 REG_WRITE(ah, AR_QOS_NO_ACK,
938 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
939 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
940 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
941
942 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
943 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
944 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
945 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
946 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 947}
948
f1dc5600
S		 949static void ath9k_hw_init_pll(struct ath_hal *ah,
950 struct ath9k_channel *chan)
f078f209 951{
f1dc5600 952 u32 pll;
f078f209 953
f1dc5600
S		 954 if (AR_SREV_9100(ah)) {
955 if (chan && IS_CHAN_5GHZ(chan))
956 pll = 0x1450;
f078f209 957 else
f1dc5600
S		 958 pll = 0x1458;
959 } else {
960 if (AR_SREV_9280_10_OR_LATER(ah)) {
961 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 962
f1dc5600
S		 963 if (chan && IS_CHAN_HALF_RATE(chan))
964 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
965 else if (chan && IS_CHAN_QUARTER_RATE(chan))
966 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 967
f1dc5600
S		 968 if (chan && IS_CHAN_5GHZ(chan)) {
969 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 970
f078f209 971
f1dc5600
S		 972 if (AR_SREV_9280_20(ah)) {
973 if (((chan->channel % 20) == 0)
974 || ((chan->channel % 10) == 0))
975 pll = 0x2850;
976 else
977 pll = 0x142c;
978 }
979 } else {
980 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
981 }
f078f209 982
f1dc5600 983 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 984
f1dc5600 985 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 986
f1dc5600
S		 987 if (chan && IS_CHAN_HALF_RATE(chan))
988 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
989 else if (chan && IS_CHAN_QUARTER_RATE(chan))
990 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 991
f1dc5600
S		 992 if (chan && IS_CHAN_5GHZ(chan))
993 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
994 else
995 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
996 } else {
997 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 998
f1dc5600
S		 999 if (chan && IS_CHAN_HALF_RATE(chan))
1000 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1001 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1002 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1003
f1dc5600
S		 1004 if (chan && IS_CHAN_5GHZ(chan))
1005 pll |= SM(0xa, AR_RTC_PLL_DIV);
1006 else
1007 pll |= SM(0xb, AR_RTC_PLL_DIV);
1008 }
1009 }
1010 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
f078f209 1011
f1dc5600
S		 1012 udelay(RTC_PLL_SETTLE_DELAY);
1013
1014 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1015}
1016
ff9b662d 1017static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
f078f209
LR		 1018{
1019 struct ath_hal_5416 *ahp = AH5416(ah);
1020 int rx_chainmask, tx_chainmask;
1021
1022 rx_chainmask = ahp->ah_rxchainmask;
1023 tx_chainmask = ahp->ah_txchainmask;
1024
1025 switch (rx_chainmask) {
1026 case 0x5:
1027 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1028 AR_PHY_SWAP_ALT_CHAIN);
1029 case 0x3:
1030 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1031 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1032 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1033 break;
1034 }
1035 case 0x1:
1036 case 0x2:
f078f209
LR		 1037 case 0x7:
1038 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1039 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1040 break;
1041 default:
1042 break;
1043 }
1044
1045 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1046 if (tx_chainmask == 0x5) {
1047 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1048 AR_PHY_SWAP_ALT_CHAIN);
1049 }
1050 if (AR_SREV_9100(ah))
1051 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1052 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1053}
1054
d97809db
CM		 1055static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1056 enum nl80211_iftype opmode)
f078f209 1057{
f078f209 1058 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1059
f1dc5600
S		 1060 ahp->ah_maskReg = AR_IMR_TXERR |
1061 AR_IMR_TXURN |
1062 AR_IMR_RXERR |
1063 AR_IMR_RXORN |
1064 AR_IMR_BCNMISC;
f078f209 1065
f1dc5600
S		 1066 if (ahp->ah_intrMitigation)
1067 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1068 else
f1dc5600 1069 ahp->ah_maskReg |= AR_IMR_RXOK;
f078f209 1070
f1dc5600 1071 ahp->ah_maskReg |= AR_IMR_TXOK;
f078f209 1072
d97809db 1073 if (opmode == NL80211_IFTYPE_AP)
f1dc5600 1074 ahp->ah_maskReg |= AR_IMR_MIB;
f078f209 1075
f1dc5600
S		 1076 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1077 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1078
f1dc5600
S		 1079 if (!AR_SREV_9100(ah)) {
1080 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1081 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1082 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1083 }
f078f209
LR		 1084}
1085
1086static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1087{
1088 struct ath_hal_5416 *ahp = AH5416(ah);
1089
1090 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1091 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
f078f209
LR		 1092 ahp->ah_acktimeout = (u32) -1;
1093 return false;
1094 } else {
1095 REG_RMW_FIELD(ah, AR_TIME_OUT,
1096 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1097 ahp->ah_acktimeout = us;
1098 return true;
1099 }
1100}
1101
1102static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1103{
1104 struct ath_hal_5416 *ahp = AH5416(ah);
1105
1106 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1107 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
f078f209
LR		 1108 ahp->ah_ctstimeout = (u32) -1;
1109 return false;
1110 } else {
1111 REG_RMW_FIELD(ah, AR_TIME_OUT,
1112 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1113 ahp->ah_ctstimeout = us;
1114 return true;
1115 }
1116}
f1dc5600
S		 1117
1118static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
f078f209
LR		 1119{
1120 struct ath_hal_5416 *ahp = AH5416(ah);
1121
1122 if (tu > 0xFFFF) {
1123 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1124 "bad global tx timeout %u\n", tu);
f078f209
LR		 1125 ahp->ah_globaltxtimeout = (u32) -1;
1126 return false;
1127 } else {
1128 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1129 ahp->ah_globaltxtimeout = tu;
1130 return true;
1131 }
1132}
1133
f1dc5600 1134static void ath9k_hw_init_user_settings(struct ath_hal *ah)
f078f209
LR		 1135{
1136 struct ath_hal_5416 *ahp = AH5416(ah);
1137
04bd4638
S		 1138 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1139 ahp->ah_miscMode);
f1dc5600
S		 1140
1141 if (ahp->ah_miscMode != 0)
1142 REG_WRITE(ah, AR_PCU_MISC,
1143 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1144 if (ahp->ah_slottime != (u32) -1)
1145 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1146 if (ahp->ah_acktimeout != (u32) -1)
1147 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1148 if (ahp->ah_ctstimeout != (u32) -1)
1149 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1150 if (ahp->ah_globaltxtimeout != (u32) -1)
1151 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1152}
1153
1154const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1155{
1156 return vendorid == ATHEROS_VENDOR_ID ?
1157 ath9k_hw_devname(devid) : NULL;
1158}
1159
1160void ath9k_hw_detach(struct ath_hal *ah)
1161{
1162 if (!AR_SREV_9100(ah))
1163 ath9k_hw_ani_detach(ah);
1164
1165 ath9k_hw_rfdetach(ah);
1166 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1167 kfree(ah);
1168}
1169
1170struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1171 void __iomem *mem, int *error)
1172{
1173 struct ath_hal *ah = NULL;
1174
1175 switch (devid) {
1176 case AR5416_DEVID_PCI:
1177 case AR5416_DEVID_PCIE:
1178 case AR9160_DEVID_PCI:
1179 case AR9280_DEVID_PCI:
1180 case AR9280_DEVID_PCIE:
e7594072 1181 case AR9285_DEVID_PCIE:
f1dc5600
S		 1182 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1183 break;
1184 default:
f1dc5600
S		 1185 *error = -ENXIO;
1186 break;
f078f209 1187 }
f1dc5600
S		 1188
1189 return ah;
1190}
1191
1192/*******/
1193/* INI */
1194/*******/
1195
1196static void ath9k_hw_override_ini(struct ath_hal *ah,
1197 struct ath9k_channel *chan)
1198{
8aa15e15
SB		 1199 /*
1200 * Set the RX_ABORT and RX_DIS and clear if off only after
1201 * RXE is set for MAC. This prevents frames with corrupted
1202 * descriptor status.
1203 */
1204 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1205
1206
f1dc5600
S		 1207 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1208 AR_SREV_9280_10_OR_LATER(ah))
1209 return;
1210
1211 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1212}
1213
e7594072
SB		 1214static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1215 struct ar5416_eeprom_def *pEepData,
f1dc5600 1216 u32 reg, u32 value)
f078f209 1217{
f1dc5600 1218 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1219
f1dc5600
S		 1220 switch (ah->ah_devid) {
1221 case AR9280_DEVID_PCI:
1222 if (reg == 0x7894) {
1223 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1224 "ini VAL: %x EEPROM: %x\n", value,
1225 (pBase->version & 0xff));
1226
1227 if ((pBase->version & 0xff) > 0x0a) {
1228 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1229 "PWDCLKIND: %d\n",
1230 pBase->pwdclkind);
1231 value &= ~AR_AN_TOP2_PWDCLKIND;
1232 value |= AR_AN_TOP2_PWDCLKIND &
1233 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1234 } else {
1235 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1236 "PWDCLKIND Earlier Rev\n");
1237 }
1238
1239 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1240 "final ini VAL: %x\n", value);
1241 }
1242 break;
1243 }
1244
1245 return value;
f078f209
LR		 1246}
1247
e7594072
SB		 1248static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1249 struct ar5416_eeprom_def *pEepData,
1250 u32 reg, u32 value)
1251{
1252 struct ath_hal_5416 *ahp = AH5416(ah);
1253
1254 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1255 return value;
1256 else
1257 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1258}
1259
f1dc5600
S		 1260static int ath9k_hw_process_ini(struct ath_hal *ah,
1261 struct ath9k_channel *chan,
1262 enum ath9k_ht_macmode macmode)
f078f209
LR		 1263{
1264 int i, regWrites = 0;
1265 struct ath_hal_5416 *ahp = AH5416(ah);
1266 u32 modesIndex, freqIndex;
1267 int status;
1268
1269 switch (chan->chanmode) {
1270 case CHANNEL_A:
1271 case CHANNEL_A_HT20:
1272 modesIndex = 1;
1273 freqIndex = 1;
1274 break;
1275 case CHANNEL_A_HT40PLUS:
1276 case CHANNEL_A_HT40MINUS:
1277 modesIndex = 2;
1278 freqIndex = 1;
1279 break;
1280 case CHANNEL_G:
1281 case CHANNEL_G_HT20:
1282 case CHANNEL_B:
1283 modesIndex = 4;
1284 freqIndex = 2;
1285 break;
1286 case CHANNEL_G_HT40PLUS:
1287 case CHANNEL_G_HT40MINUS:
1288 modesIndex = 3;
1289 freqIndex = 2;
1290 break;
1291
1292 default:
1293 return -EINVAL;
1294 }
1295
1296 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1297
1298 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1299
1300 ath9k_hw_set_addac(ah, chan);
1301
1302 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1303 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1304 } else {
1305 struct ar5416IniArray temp;
1306 u32 addacSize =
1307 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1308 ahp->ah_iniAddac.ia_columns;
1309
1310 memcpy(ahp->ah_addac5416_21,
1311 ahp->ah_iniAddac.ia_array, addacSize);
1312
f1dc5600 1313 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
f078f209
LR		 1314
1315 temp.ia_array = ahp->ah_addac5416_21;
1316 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1317 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1318 REG_WRITE_ARRAY(&temp, 1, regWrites);
1319 }
f1dc5600 1320
f078f209
LR		 1321 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1322
1323 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1324 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1325 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1326
f078f209
LR		 1327 REG_WRITE(ah, reg, val);
1328
1329 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1330 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1331 udelay(100);
1332 }
1333
1334 DO_DELAY(regWrites);
1335 }
1336
e7594072 1337 if (AR_SREV_9280(ah))
9f804202
SB		 1338 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1339
e7594072 1340 if (AR_SREV_9280(ah))
9f804202
SB		 1341 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1342
f078f209
LR		 1343 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1344 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1345 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1346
1347 REG_WRITE(ah, reg, val);
1348
1349 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1350 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1351 udelay(100);
1352 }
1353
1354 DO_DELAY(regWrites);
1355 }
1356
1357 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1358
1359 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1360 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1361 regWrites);
1362 }
1363
1364 ath9k_hw_override_ini(ah, chan);
1365 ath9k_hw_set_regs(ah, chan, macmode);
1366 ath9k_hw_init_chain_masks(ah);
1367
f1dc5600 1368 status = ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1369 ath9k_regd_get_ctl(ah, chan),
1370 ath9k_regd_get_antenna_allowed(ah,
1371 chan),
1372 chan->maxRegTxPower * 2,
1373 min((u32) MAX_RATE_POWER,
1374 (u32) ah->ah_powerLimit));
1375 if (status != 0) {
1376 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 1377 "error init'ing transmit power\n");
f078f209
LR		 1378 return -EIO;
1379 }
1380
1381 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1382 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 1383 "ar5416SetRfRegs failed\n");
f078f209
LR		 1384 return -EIO;
1385 }
1386
1387 return 0;
1388}
1389
f1dc5600
S		 1390/****************************************/
1391/* Reset and Channel Switching Routines */
1392/****************************************/
1393
1394static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1395{
f1dc5600
S		 1396 u32 rfMode = 0;
1397
1398 if (chan == NULL)
1399 return;
1400
1401 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1402 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1403
1404 if (!AR_SREV_9280_10_OR_LATER(ah))
1405 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1406 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1407
1408 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1409 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1410
1411 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1412}
1413
1414static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1415{
1416 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1417}
1418
1419static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1420{
1421 u32 regval;
1422
1423 regval = REG_READ(ah, AR_AHB_MODE);
1424 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1425
1426 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1427 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1428
1429 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1430
1431 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1432 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1433
1434 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1435
1436 if (AR_SREV_9285(ah)) {
1437 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1438 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1439 } else {
1440 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1441 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1442 }
1443}
1444
1445static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1446{
1447 u32 val;
1448
1449 val = REG_READ(ah, AR_STA_ID1);
1450 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1451 switch (opmode) {
d97809db 1452 case NL80211_IFTYPE_AP:
f1dc5600
S		 1453 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1454 | AR_STA_ID1_KSRCH_MODE);
1455 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1456 break;
d97809db 1457 case NL80211_IFTYPE_ADHOC:
f1dc5600
S		 1458 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1459 | AR_STA_ID1_KSRCH_MODE);
1460 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1461 break;
d97809db
CM		 1462 case NL80211_IFTYPE_STATION:
1463 case NL80211_IFTYPE_MONITOR:
f1dc5600 1464 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1465 break;
f1dc5600
S		 1466 }
1467}
1468
1469static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1470 u32 coef_scaled,
1471 u32 *coef_mantissa,
1472 u32 *coef_exponent)
1473{
1474 u32 coef_exp, coef_man;
1475
1476 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1477 if ((coef_scaled >> coef_exp) & 0x1)
1478 break;
1479
1480 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1481
1482 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1483
1484 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1485 *coef_exponent = coef_exp - 16;
1486}
1487
1488static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1489 struct ath9k_channel *chan)
1490{
1491 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1492 u32 clockMhzScaled = 0x64000000;
1493 struct chan_centers centers;
1494
1495 if (IS_CHAN_HALF_RATE(chan))
1496 clockMhzScaled = clockMhzScaled >> 1;
1497 else if (IS_CHAN_QUARTER_RATE(chan))
1498 clockMhzScaled = clockMhzScaled >> 2;
1499
1500 ath9k_hw_get_channel_centers(ah, chan, &centers);
1501 coef_scaled = clockMhzScaled / centers.synth_center;
1502
1503 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1504 &ds_coef_exp);
1505
1506 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1507 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1508 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1509 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1510
1511 coef_scaled = (9 * coef_scaled) / 10;
1512
1513 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1514 &ds_coef_exp);
1515
1516 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1517 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1518 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1519 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1520}
1521
1522static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1523{
1524 u32 rst_flags;
1525 u32 tmpReg;
1526
1527 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1528 AR_RTC_FORCE_WAKE_ON_INT);
1529
1530 if (AR_SREV_9100(ah)) {
1531 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1532 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1533 } else {
1534 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1535 if (tmpReg &
1536 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1537 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1538 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1539 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1540 } else {
1541 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1542 }
1543
1544 rst_flags = AR_RTC_RC_MAC_WARM;
1545 if (type == ATH9K_RESET_COLD)
1546 rst_flags |= AR_RTC_RC_MAC_COLD;
1547 }
1548
1549 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1550 udelay(50);
1551
1552 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1553 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1554 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1555 "RTC stuck in MAC reset\n");
f1dc5600
S		 1556 return false;
1557 }
1558
1559 if (!AR_SREV_9100(ah))
1560 REG_WRITE(ah, AR_RC, 0);
1561
1562 ath9k_hw_init_pll(ah, NULL);
1563
1564 if (AR_SREV_9100(ah))
1565 udelay(50);
1566
1567 return true;
1568}
1569
1570static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1571{
1572 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1573 AR_RTC_FORCE_WAKE_ON_INT);
1574
1575 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1576 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1577
1578 if (!ath9k_hw_wait(ah,
1579 AR_RTC_STATUS,
1580 AR_RTC_STATUS_M,
1581 AR_RTC_STATUS_ON)) {
04bd4638 1582 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1583 return false;
f078f209
LR		 1584 }
1585
f1dc5600
S		 1586 ath9k_hw_read_revisions(ah);
1587
1588 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1589}
1590
1591static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1592{
1593 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1594 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1595
1596 switch (type) {
1597 case ATH9K_RESET_POWER_ON:
1598 return ath9k_hw_set_reset_power_on(ah);
1599 break;
1600 case ATH9K_RESET_WARM:
1601 case ATH9K_RESET_COLD:
1602 return ath9k_hw_set_reset(ah, type);
1603 break;
1604 default:
1605 return false;
1606 }
f078f209
LR		 1607}
1608
f1dc5600
S		 1609static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1610 enum ath9k_ht_macmode macmode)
f078f209 1611{
f1dc5600 1612 u32 phymode;
e7594072 1613 u32 enableDacFifo = 0;
f078f209 1614 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1615
e7594072
SB		 1616 if (AR_SREV_9285_10_OR_LATER(ah))
1617 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1618 AR_PHY_FC_ENABLE_DAC_FIFO);
1619
f1dc5600 1620 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1621 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1622
1623 if (IS_CHAN_HT40(chan)) {
1624 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1625
f1dc5600
S		 1626 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1627 (chan->chanmode == CHANNEL_G_HT40PLUS))
1628 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1629
f1dc5600
S		 1630 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1631 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1632 }
f1dc5600
S		 1633 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1634
1635 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1636
f1dc5600
S		 1637 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1638 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1639}
1640
f1dc5600
S		 1641static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1642 struct ath9k_channel *chan)
f078f209
LR		 1643{
1644 struct ath_hal_5416 *ahp = AH5416(ah);
1645
f1dc5600
S		 1646 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1647 return false;
f078f209 1648
f1dc5600
S		 1649 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1650 return false;
f078f209 1651
f1dc5600 1652 ahp->ah_chipFullSleep = false;
f078f209 1653
f1dc5600 1654 ath9k_hw_init_pll(ah, chan);
f078f209 1655
f1dc5600 1656 ath9k_hw_set_rfmode(ah, chan);
f078f209 1657
f1dc5600 1658 return true;
f078f209
LR		 1659}
1660
f1dc5600
S		 1661static bool ath9k_hw_channel_change(struct ath_hal *ah,
1662 struct ath9k_channel *chan,
1663 enum ath9k_ht_macmode macmode)
f078f209
LR		 1664{
1665 u32 synthDelay, qnum;
f078f209
LR		 1666
1667 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1668 if (ath9k_hw_numtxpending(ah, qnum)) {
1669 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1670 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1671 return false;
1672 }
1673 }
1674
1675 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1676 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1677 AR_PHY_RFBUS_GRANT_EN)) {
04bd4638
S		 1678 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1679 "Could not kill baseband RX\n");
f078f209
LR		 1680 return false;
1681 }
1682
1683 ath9k_hw_set_regs(ah, chan, macmode);
1684
1685 if (AR_SREV_9280_10_OR_LATER(ah)) {
1686 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1687 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1688 "failed to set channel\n");
f078f209
LR		 1689 return false;
1690 }
1691 } else {
1692 if (!(ath9k_hw_set_channel(ah, chan))) {
1693 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1694 "failed to set channel\n");
f078f209
LR		 1695 return false;
1696 }
1697 }
1698
f1dc5600 1699 if (ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1700 ath9k_regd_get_ctl(ah, chan),
1701 ath9k_regd_get_antenna_allowed(ah, chan),
1702 chan->maxRegTxPower * 2,
1703 min((u32) MAX_RATE_POWER,
1704 (u32) ah->ah_powerLimit)) != 0) {
1705 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 1706 "error init'ing transmit power\n");
f078f209
LR		 1707 return false;
1708 }
1709
1710 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1711 if (IS_CHAN_B(chan))
f078f209
LR		 1712 synthDelay = (4 * synthDelay) / 22;
1713 else
1714 synthDelay /= 10;
1715
1716 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1717
1718 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1719
f1dc5600
S		 1720 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1721 ath9k_hw_set_delta_slope(ah, chan);
1722
1723 if (AR_SREV_9280_10_OR_LATER(ah))
1724 ath9k_hw_9280_spur_mitigate(ah, chan);
1725 else
1726 ath9k_hw_spur_mitigate(ah, chan);
1727
1728 if (!chan->oneTimeCalsDone)
1729 chan->oneTimeCalsDone = true;
1730
1731 return true;
1732}
1733
1734static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1735{
1736 int bb_spur = AR_NO_SPUR;
1737 int freq;
1738 int bin, cur_bin;
1739 int bb_spur_off, spur_subchannel_sd;
1740 int spur_freq_sd;
1741 int spur_delta_phase;
1742 int denominator;
1743 int upper, lower, cur_vit_mask;
1744 int tmp, newVal;
1745 int i;
1746 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1747 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1748 };
1749 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1750 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1751 };
1752 int inc[4] = { 0, 100, 0, 0 };
1753 struct chan_centers centers;
1754
1755 int8_t mask_m[123];
1756 int8_t mask_p[123];
1757 int8_t mask_amt;
1758 int tmp_mask;
1759 int cur_bb_spur;
1760 bool is2GHz = IS_CHAN_2GHZ(chan);
1761
1762 memset(&mask_m, 0, sizeof(int8_t) * 123);
1763 memset(&mask_p, 0, sizeof(int8_t) * 123);
1764
1765 ath9k_hw_get_channel_centers(ah, chan, &centers);
1766 freq = centers.synth_center;
1767
1768 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1769 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1770 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1771
1772 if (is2GHz)
1773 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1774 else
1775 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1776
1777 if (AR_NO_SPUR == cur_bb_spur)
1778 break;
1779 cur_bb_spur = cur_bb_spur - freq;
1780
1781 if (IS_CHAN_HT40(chan)) {
1782 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1783 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1784 bb_spur = cur_bb_spur;
1785 break;
1786 }
1787 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1788 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1789 bb_spur = cur_bb_spur;
1790 break;
1791 }
1792 }
1793
1794 if (AR_NO_SPUR == bb_spur) {
1795 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1796 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1797 return;
1798 } else {
1799 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1801 }
1802
1803 bin = bb_spur * 320;
1804
1805 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1806
1807 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1808 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1809 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1810 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1811 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1812
1813 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1814 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1815 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1816 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1817 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1818 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1819
1820 if (IS_CHAN_HT40(chan)) {
1821 if (bb_spur < 0) {
1822 spur_subchannel_sd = 1;
1823 bb_spur_off = bb_spur + 10;
1824 } else {
1825 spur_subchannel_sd = 0;
1826 bb_spur_off = bb_spur - 10;
1827 }
1828 } else {
1829 spur_subchannel_sd = 0;
1830 bb_spur_off = bb_spur;
1831 }
1832
1833 if (IS_CHAN_HT40(chan))
1834 spur_delta_phase =
1835 ((bb_spur * 262144) /
1836 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1837 else
1838 spur_delta_phase =
1839 ((bb_spur * 524288) /
1840 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1841
1842 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1843 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1844
1845 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1846 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1847 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1848 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1849
1850 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1851 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1852
1853 cur_bin = -6000;
1854 upper = bin + 100;
1855 lower = bin - 100;
1856
1857 for (i = 0; i < 4; i++) {
1858 int pilot_mask = 0;
1859 int chan_mask = 0;
1860 int bp = 0;
1861 for (bp = 0; bp < 30; bp++) {
1862 if ((cur_bin > lower) && (cur_bin < upper)) {
1863 pilot_mask = pilot_mask | 0x1 << bp;
1864 chan_mask = chan_mask | 0x1 << bp;
1865 }
1866 cur_bin += 100;
1867 }
1868 cur_bin += inc[i];
1869 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1870 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1871 }
1872
1873 cur_vit_mask = 6100;
1874 upper = bin + 120;
1875 lower = bin - 120;
1876
1877 for (i = 0; i < 123; i++) {
1878 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1879
1880 /* workaround for gcc bug #37014 */
a085ff71 1881 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 1882
a085ff71 1883 if (tmp_v < 75)
f1dc5600
S		 1884 mask_amt = 1;
1885 else
1886 mask_amt = 0;
1887 if (cur_vit_mask < 0)
1888 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1889 else
1890 mask_p[cur_vit_mask / 100] = mask_amt;
1891 }
1892 cur_vit_mask -= 100;
1893 }
1894
1895 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1896 | (mask_m[48] << 26) | (mask_m[49] << 24)
1897 | (mask_m[50] << 22) | (mask_m[51] << 20)
1898 | (mask_m[52] << 18) | (mask_m[53] << 16)
1899 | (mask_m[54] << 14) | (mask_m[55] << 12)
1900 | (mask_m[56] << 10) | (mask_m[57] << 8)
1901 | (mask_m[58] << 6) | (mask_m[59] << 4)
1902 | (mask_m[60] << 2) | (mask_m[61] << 0);
1903 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1905
1906 tmp_mask = (mask_m[31] << 28)
1907 | (mask_m[32] << 26) | (mask_m[33] << 24)
1908 | (mask_m[34] << 22) | (mask_m[35] << 20)
1909 | (mask_m[36] << 18) | (mask_m[37] << 16)
1910 | (mask_m[48] << 14) | (mask_m[39] << 12)
1911 | (mask_m[40] << 10) | (mask_m[41] << 8)
1912 | (mask_m[42] << 6) | (mask_m[43] << 4)
1913 | (mask_m[44] << 2) | (mask_m[45] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1916
1917 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1918 | (mask_m[18] << 26) | (mask_m[18] << 24)
1919 | (mask_m[20] << 22) | (mask_m[20] << 20)
1920 | (mask_m[22] << 18) | (mask_m[22] << 16)
1921 | (mask_m[24] << 14) | (mask_m[24] << 12)
1922 | (mask_m[25] << 10) | (mask_m[26] << 8)
1923 | (mask_m[27] << 6) | (mask_m[28] << 4)
1924 | (mask_m[29] << 2) | (mask_m[30] << 0);
1925 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1927
1928 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1929 | (mask_m[2] << 26) | (mask_m[3] << 24)
1930 | (mask_m[4] << 22) | (mask_m[5] << 20)
1931 | (mask_m[6] << 18) | (mask_m[7] << 16)
1932 | (mask_m[8] << 14) | (mask_m[9] << 12)
1933 | (mask_m[10] << 10) | (mask_m[11] << 8)
1934 | (mask_m[12] << 6) | (mask_m[13] << 4)
1935 | (mask_m[14] << 2) | (mask_m[15] << 0);
1936 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1938
1939 tmp_mask = (mask_p[15] << 28)
1940 | (mask_p[14] << 26) | (mask_p[13] << 24)
1941 | (mask_p[12] << 22) | (mask_p[11] << 20)
1942 | (mask_p[10] << 18) | (mask_p[9] << 16)
1943 | (mask_p[8] << 14) | (mask_p[7] << 12)
1944 | (mask_p[6] << 10) | (mask_p[5] << 8)
1945 | (mask_p[4] << 6) | (mask_p[3] << 4)
1946 | (mask_p[2] << 2) | (mask_p[1] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 1949
f1dc5600
S		 1950 tmp_mask = (mask_p[30] << 28)
1951 | (mask_p[29] << 26) | (mask_p[28] << 24)
1952 | (mask_p[27] << 22) | (mask_p[26] << 20)
1953 | (mask_p[25] << 18) | (mask_p[24] << 16)
1954 | (mask_p[23] << 14) | (mask_p[22] << 12)
1955 | (mask_p[21] << 10) | (mask_p[20] << 8)
1956 | (mask_p[19] << 6) | (mask_p[18] << 4)
1957 | (mask_p[17] << 2) | (mask_p[16] << 0);
1958 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1959 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 1960
f1dc5600
S		 1961 tmp_mask = (mask_p[45] << 28)
1962 | (mask_p[44] << 26) | (mask_p[43] << 24)
1963 | (mask_p[42] << 22) | (mask_p[41] << 20)
1964 | (mask_p[40] << 18) | (mask_p[39] << 16)
1965 | (mask_p[38] << 14) | (mask_p[37] << 12)
1966 | (mask_p[36] << 10) | (mask_p[35] << 8)
1967 | (mask_p[34] << 6) | (mask_p[33] << 4)
1968 | (mask_p[32] << 2) | (mask_p[31] << 0);
1969 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1970 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 1971
f1dc5600
S		 1972 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1973 | (mask_p[59] << 26) | (mask_p[58] << 24)
1974 | (mask_p[57] << 22) | (mask_p[56] << 20)
1975 | (mask_p[55] << 18) | (mask_p[54] << 16)
1976 | (mask_p[53] << 14) | (mask_p[52] << 12)
1977 | (mask_p[51] << 10) | (mask_p[50] << 8)
1978 | (mask_p[49] << 6) | (mask_p[48] << 4)
1979 | (mask_p[47] << 2) | (mask_p[46] << 0);
1980 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1981 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 1982}
1983
f1dc5600 1984static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1985{
f1dc5600
S		 1986 int bb_spur = AR_NO_SPUR;
1987 int bin, cur_bin;
1988 int spur_freq_sd;
1989 int spur_delta_phase;
1990 int denominator;
1991 int upper, lower, cur_vit_mask;
1992 int tmp, new;
1993 int i;
1994 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1995 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1996 };
1997 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1998 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1999 };
2000 int inc[4] = { 0, 100, 0, 0 };
f078f209 2001
f1dc5600
S		 2002 int8_t mask_m[123];
2003 int8_t mask_p[123];
2004 int8_t mask_amt;
2005 int tmp_mask;
2006 int cur_bb_spur;
2007 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2008
f1dc5600
S		 2009 memset(&mask_m, 0, sizeof(int8_t) * 123);
2010 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2011
f1dc5600
S		 2012 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2013 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2014 if (AR_NO_SPUR == cur_bb_spur)
2015 break;
2016 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2017 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2018 bb_spur = cur_bb_spur;
2019 break;
2020 }
2021 }
f078f209 2022
f1dc5600
S		 2023 if (AR_NO_SPUR == bb_spur)
2024 return;
f078f209 2025
f1dc5600 2026 bin = bb_spur * 32;
f078f209 2027
f1dc5600
S		 2028 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2029 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2030 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2031 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2032 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2033
f1dc5600 2034 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2035
f1dc5600
S		 2036 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2037 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2038 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2039 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2040 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2041 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2042
f1dc5600
S		 2043 spur_delta_phase = ((bb_spur * 524288) / 100) &
2044 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2045
f1dc5600
S		 2046 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2047 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2048
f1dc5600
S		 2049 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2050 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2051 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2052 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2053
f1dc5600
S		 2054 cur_bin = -6000;
2055 upper = bin + 100;
2056 lower = bin - 100;
f078f209 2057
f1dc5600
S		 2058 for (i = 0; i < 4; i++) {
2059 int pilot_mask = 0;
2060 int chan_mask = 0;
2061 int bp = 0;
2062 for (bp = 0; bp < 30; bp++) {
2063 if ((cur_bin > lower) && (cur_bin < upper)) {
2064 pilot_mask = pilot_mask | 0x1 << bp;
2065 chan_mask = chan_mask | 0x1 << bp;
2066 }
2067 cur_bin += 100;
2068 }
2069 cur_bin += inc[i];
2070 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2071 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2072 }
f078f209 2073
f1dc5600
S		 2074 cur_vit_mask = 6100;
2075 upper = bin + 120;
2076 lower = bin - 120;
f078f209 2077
f1dc5600
S		 2078 for (i = 0; i < 123; i++) {
2079 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2080
f1dc5600 2081 /* workaround for gcc bug #37014 */
a085ff71 2082 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2083
a085ff71 2084 if (tmp_v < 75)
f1dc5600
S		 2085 mask_amt = 1;
2086 else
2087 mask_amt = 0;
2088 if (cur_vit_mask < 0)
2089 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2090 else
2091 mask_p[cur_vit_mask / 100] = mask_amt;
2092 }
2093 cur_vit_mask -= 100;
f078f209
LR		 2094 }
2095
f1dc5600
S		 2096 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2097 | (mask_m[48] << 26) | (mask_m[49] << 24)
2098 | (mask_m[50] << 22) | (mask_m[51] << 20)
2099 | (mask_m[52] << 18) | (mask_m[53] << 16)
2100 | (mask_m[54] << 14) | (mask_m[55] << 12)
2101 | (mask_m[56] << 10) | (mask_m[57] << 8)
2102 | (mask_m[58] << 6) | (mask_m[59] << 4)
2103 | (mask_m[60] << 2) | (mask_m[61] << 0);
2104 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2106
f1dc5600
S		 2107 tmp_mask = (mask_m[31] << 28)
2108 | (mask_m[32] << 26) | (mask_m[33] << 24)
2109 | (mask_m[34] << 22) | (mask_m[35] << 20)
2110 | (mask_m[36] << 18) | (mask_m[37] << 16)
2111 | (mask_m[48] << 14) | (mask_m[39] << 12)
2112 | (mask_m[40] << 10) | (mask_m[41] << 8)
2113 | (mask_m[42] << 6) | (mask_m[43] << 4)
2114 | (mask_m[44] << 2) | (mask_m[45] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2117
f1dc5600
S		 2118 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2119 | (mask_m[18] << 26) | (mask_m[18] << 24)
2120 | (mask_m[20] << 22) | (mask_m[20] << 20)
2121 | (mask_m[22] << 18) | (mask_m[22] << 16)
2122 | (mask_m[24] << 14) | (mask_m[24] << 12)
2123 | (mask_m[25] << 10) | (mask_m[26] << 8)
2124 | (mask_m[27] << 6) | (mask_m[28] << 4)
2125 | (mask_m[29] << 2) | (mask_m[30] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2128
f1dc5600
S		 2129 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2130 | (mask_m[2] << 26) | (mask_m[3] << 24)
2131 | (mask_m[4] << 22) | (mask_m[5] << 20)
2132 | (mask_m[6] << 18) | (mask_m[7] << 16)
2133 | (mask_m[8] << 14) | (mask_m[9] << 12)
2134 | (mask_m[10] << 10) | (mask_m[11] << 8)
2135 | (mask_m[12] << 6) | (mask_m[13] << 4)
2136 | (mask_m[14] << 2) | (mask_m[15] << 0);
2137 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2139
f1dc5600
S		 2140 tmp_mask = (mask_p[15] << 28)
2141 | (mask_p[14] << 26) | (mask_p[13] << 24)
2142 | (mask_p[12] << 22) | (mask_p[11] << 20)
2143 | (mask_p[10] << 18) | (mask_p[9] << 16)
2144 | (mask_p[8] << 14) | (mask_p[7] << 12)
2145 | (mask_p[6] << 10) | (mask_p[5] << 8)
2146 | (mask_p[4] << 6) | (mask_p[3] << 4)
2147 | (mask_p[2] << 2) | (mask_p[1] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2150
f1dc5600
S		 2151 tmp_mask = (mask_p[30] << 28)
2152 | (mask_p[29] << 26) | (mask_p[28] << 24)
2153 | (mask_p[27] << 22) | (mask_p[26] << 20)
2154 | (mask_p[25] << 18) | (mask_p[24] << 16)
2155 | (mask_p[23] << 14) | (mask_p[22] << 12)
2156 | (mask_p[21] << 10) | (mask_p[20] << 8)
2157 | (mask_p[19] << 6) | (mask_p[18] << 4)
2158 | (mask_p[17] << 2) | (mask_p[16] << 0);
2159 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2160 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2161
f1dc5600
S		 2162 tmp_mask = (mask_p[45] << 28)
2163 | (mask_p[44] << 26) | (mask_p[43] << 24)
2164 | (mask_p[42] << 22) | (mask_p[41] << 20)
2165 | (mask_p[40] << 18) | (mask_p[39] << 16)
2166 | (mask_p[38] << 14) | (mask_p[37] << 12)
2167 | (mask_p[36] << 10) | (mask_p[35] << 8)
2168 | (mask_p[34] << 6) | (mask_p[33] << 4)
2169 | (mask_p[32] << 2) | (mask_p[31] << 0);
2170 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2171 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2172
f1dc5600
S		 2173 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2174 | (mask_p[59] << 26) | (mask_p[58] << 24)
2175 | (mask_p[57] << 22) | (mask_p[56] << 20)
2176 | (mask_p[55] << 18) | (mask_p[54] << 16)
2177 | (mask_p[53] << 14) | (mask_p[52] << 12)
2178 | (mask_p[51] << 10) | (mask_p[50] << 8)
2179 | (mask_p[49] << 6) | (mask_p[48] << 4)
2180 | (mask_p[47] << 2) | (mask_p[46] << 0);
2181 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2182 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2183}
2184
ae8d2858
LR		 2185int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2186 bool bChannelChange)
f078f209 2187{
f078f209 2188 u32 saveLedState;
ae8d2858 2189 struct ath_softc *sc = ah->ah_sc;
f078f209
LR		 2190 struct ath_hal_5416 *ahp = AH5416(ah);
2191 struct ath9k_channel *curchan = ah->ah_curchan;
2192 u32 saveDefAntenna;
2193 u32 macStaId1;
ae8d2858 2194 int i, rx_chainmask, r;
f078f209 2195
ae8d2858
LR		 2196 ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2197 ahp->ah_txchainmask = sc->sc_tx_chainmask;
2198 ahp->ah_rxchainmask = sc->sc_rx_chainmask;
f078f209
LR		 2199
2200 if (AR_SREV_9280(ah)) {
2201 ahp->ah_txchainmask &= 0x3;
2202 ahp->ah_rxchainmask &= 0x3;
2203 }
2204
0de57d99 2205 if (ath9k_regd_check_channel(ah, chan) == NULL) {
f078f209 2206 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638
S		 2207 "invalid channel %u/0x%x; no mapping\n",
2208 chan->channel, chan->channelFlags);
ae8d2858 2209 return -EINVAL;
f078f209
LR		 2210 }
2211
ae8d2858
LR		 2212 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2213 return -EIO;
f078f209
LR		 2214
2215 if (curchan)
2216 ath9k_hw_getnf(ah, curchan);
2217
2218 if (bChannelChange &&
2219 (ahp->ah_chipFullSleep != true) &&
2220 (ah->ah_curchan != NULL) &&
2221 (chan->channel != ah->ah_curchan->channel) &&
2222 ((chan->channelFlags & CHANNEL_ALL) ==
2223 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2224 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
99405f93 2225 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
f078f209 2226
ae8d2858 2227 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
f078f209
LR		 2228 ath9k_hw_loadnf(ah, ah->ah_curchan);
2229 ath9k_hw_start_nfcal(ah);
ae8d2858 2230 return 0;
f078f209
LR		 2231 }
2232 }
2233
2234 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2235 if (saveDefAntenna == 0)
2236 saveDefAntenna = 1;
2237
2238 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2239
2240 saveLedState = REG_READ(ah, AR_CFG_LED) &
2241 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2242 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2243
2244 ath9k_hw_mark_phy_inactive(ah);
2245
2246 if (!ath9k_hw_chip_reset(ah, chan)) {
04bd4638 2247 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
ae8d2858 2248 return -EINVAL;
f078f209
LR		 2249 }
2250
2251 if (AR_SREV_9280(ah)) {
2252 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2253 AR_GPIO_JTAG_DISABLE);
2254
86b89eed 2255 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
f078f209
LR		 2256 if (IS_CHAN_5GHZ(chan))
2257 ath9k_hw_set_gpio(ah, 9, 0);
2258 else
2259 ath9k_hw_set_gpio(ah, 9, 1);
2260 }
c83be688 2261 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
f078f209
LR		 2262 }
2263
ae8d2858
LR		 2264 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2265 if (r)
2266 return r;
f078f209 2267
0ced0e17
JM		 2268 /* Setup MFP options for CCMP */
2269 if (AR_SREV_9280_20_OR_LATER(ah)) {
2270 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2271 * frames when constructing CCMP AAD. */
2272 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2273 0xc7ff);
2274 ah->sw_mgmt_crypto = false;
2275 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2276 /* Disable hardware crypto for management frames */
2277 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2278 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2279 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2280 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2281 ah->sw_mgmt_crypto = true;
2282 } else
2283 ah->sw_mgmt_crypto = true;
2284
f078f209
LR		 2285 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2286 ath9k_hw_set_delta_slope(ah, chan);
2287
2288 if (AR_SREV_9280_10_OR_LATER(ah))
2289 ath9k_hw_9280_spur_mitigate(ah, chan);
2290 else
2291 ath9k_hw_spur_mitigate(ah, chan);
2292
2293 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2294 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 2295 "error setting board options\n");
ae8d2858 2296 return -EIO;
f078f209
LR		 2297 }
2298
2299 ath9k_hw_decrease_chain_power(ah, chan);
2300
2301 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2302 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2303 | macStaId1
2304 | AR_STA_ID1_RTS_USE_DEF
2305 | (ah->ah_config.
60b67f51 2306 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
f078f209 2307 | ahp->ah_staId1Defaults);
b4696c8b 2308 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 2309
2310 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2311 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2312
2313 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2314
2315 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2316 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2317 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2318
2319 REG_WRITE(ah, AR_ISR, ~0);
2320
2321 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2322
2323 if (AR_SREV_9280_10_OR_LATER(ah)) {
ae8d2858
LR		 2324 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2325 return -EIO;
f078f209 2326 } else {
ae8d2858
LR		 2327 if (!(ath9k_hw_set_channel(ah, chan)))
2328 return -EIO;
f078f209
LR		 2329 }
2330
2331 for (i = 0; i < AR_NUM_DCU; i++)
2332 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2333
2334 ahp->ah_intrTxqs = 0;
60b67f51 2335 for (i = 0; i < ah->ah_caps.total_queues; i++)
f078f209
LR		 2336 ath9k_hw_resettxqueue(ah, i);
2337
b4696c8b 2338 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
f078f209
LR		 2339 ath9k_hw_init_qos(ah);
2340
e97275cb 2341#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2342 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2343 ath9k_enable_rfkill(ah);
2344#endif
f078f209
LR		 2345 ath9k_hw_init_user_settings(ah);
2346
f078f209
LR		 2347 REG_WRITE(ah, AR_STA_ID1,
2348 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2349
2350 ath9k_hw_set_dma(ah);
2351
2352 REG_WRITE(ah, AR_OBS, 8);
2353
2354 if (ahp->ah_intrMitigation) {
2355
2356 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2357 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2358 }
2359
2360 ath9k_hw_init_bb(ah, chan);
2361
ae8d2858
LR		 2362 if (!ath9k_hw_init_cal(ah, chan))
2363 return -EIO;;
f078f209
LR		 2364
2365 rx_chainmask = ahp->ah_rxchainmask;
2366 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2367 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2368 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2369 }
2370
2371 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2372
2373 if (AR_SREV_9100(ah)) {
2374 u32 mask;
2375 mask = REG_READ(ah, AR_CFG);
2376 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2377 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2378 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2379 } else {
2380 mask =
2381 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2382 REG_WRITE(ah, AR_CFG, mask);
2383 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2384 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2385 }
2386 } else {
2387#ifdef __BIG_ENDIAN
2388 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2389#endif
2390 }
2391
ae8d2858 2392 return 0;
f078f209
LR		 2393}
2394
f1dc5600
S		 2395/************************/
2396/* Key Cache Management */
2397/************************/
f078f209 2398
f1dc5600 2399bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
f078f209 2400{
f1dc5600 2401 u32 keyType;
f078f209 2402
f1dc5600
S		 2403 if (entry >= ah->ah_caps.keycache_size) {
2404 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2405 "entry %u out of range\n", entry);
f078f209
LR		 2406 return false;
2407 }
2408
f1dc5600 2409 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2410
f1dc5600
S		 2411 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2412 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2413 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2414 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2415 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2416 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2417 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2418 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2419
f1dc5600
S		 2420 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2421 u16 micentry = entry + 64;
f078f209 2422
f1dc5600
S		 2423 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2424 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2425 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2426 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2427
f078f209
LR		 2428 }
2429
f1dc5600
S		 2430 if (ah->ah_curchan == NULL)
2431 return true;
f078f209
LR		 2432
2433 return true;
2434}
2435
f1dc5600 2436bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
f078f209 2437{
f1dc5600 2438 u32 macHi, macLo;
f078f209 2439
f1dc5600
S		 2440 if (entry >= ah->ah_caps.keycache_size) {
2441 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2442 "entry %u out of range\n", entry);
f1dc5600 2443 return false;
f078f209
LR		 2444 }
2445
f1dc5600
S		 2446 if (mac != NULL) {
2447 macHi = (mac[5] << 8) | mac[4];
2448 macLo = (mac[3] << 24) |
2449 (mac[2] << 16) |
2450 (mac[1] << 8) |
2451 mac[0];
2452 macLo >>= 1;
2453 macLo |= (macHi & 1) << 31;
2454 macHi >>= 1;
f078f209 2455 } else {
f1dc5600 2456 macLo = macHi = 0;
f078f209 2457 }
f1dc5600
S		 2458 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2459 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2460
f1dc5600 2461 return true;
f078f209
LR		 2462}
2463
f1dc5600
S		 2464bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2465 const struct ath9k_keyval *k,
2466 const u8 *mac, int xorKey)
f078f209 2467{
f1dc5600
S		 2468 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2469 u32 key0, key1, key2, key3, key4;
2470 u32 keyType;
2471 u32 xorMask = xorKey ?
2472 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2473 | ATH9K_KEY_XOR) : 0;
f078f209 2474 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 2475
f1dc5600
S		 2476 if (entry >= pCap->keycache_size) {
2477 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2478 "entry %u out of range\n", entry);
f1dc5600 2479 return false;
f078f209
LR		 2480 }
2481
f1dc5600
S		 2482 switch (k->kv_type) {
2483 case ATH9K_CIPHER_AES_OCB:
2484 keyType = AR_KEYTABLE_TYPE_AES;
2485 break;
2486 case ATH9K_CIPHER_AES_CCM:
2487 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2488 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2489 "AES-CCM not supported by mac rev 0x%x\n",
f1dc5600
S		 2490 ah->ah_macRev);
2491 return false;
2492 }
2493 keyType = AR_KEYTABLE_TYPE_CCM;
2494 break;
2495 case ATH9K_CIPHER_TKIP:
2496 keyType = AR_KEYTABLE_TYPE_TKIP;
2497 if (ATH9K_IS_MIC_ENABLED(ah)
2498 && entry + 64 >= pCap->keycache_size) {
2499 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2500 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2501 return false;
2502 }
2503 break;
2504 case ATH9K_CIPHER_WEP:
2505 if (k->kv_len < LEN_WEP40) {
2506 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2507 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2508 return false;
2509 }
2510 if (k->kv_len <= LEN_WEP40)
2511 keyType = AR_KEYTABLE_TYPE_40;
2512 else if (k->kv_len <= LEN_WEP104)
2513 keyType = AR_KEYTABLE_TYPE_104;
2514 else
2515 keyType = AR_KEYTABLE_TYPE_128;
2516 break;
2517 case ATH9K_CIPHER_CLR:
2518 keyType = AR_KEYTABLE_TYPE_CLR;
2519 break;
2520 default:
2521 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2522 "cipher %u not supported\n", k->kv_type);
f1dc5600 2523 return false;
f078f209
LR		 2524 }
2525
f1dc5600
S		 2526 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2527 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2528 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2529 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2530 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2531 if (k->kv_len <= LEN_WEP104)
2532 key4 &= 0xff;
f078f209 2533
f1dc5600
S		 2534 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2535 u16 micentry = entry + 64;
f078f209 2536
f1dc5600
S		 2537 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2538 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2539 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2540 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2541 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2542 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2543 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2544
f1dc5600
S		 2545 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2546 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2547
f1dc5600
S		 2548 mic0 = get_unaligned_le32(k->kv_mic + 0);
2549 mic2 = get_unaligned_le32(k->kv_mic + 4);
2550 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2551 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2552 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2554 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2555 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2556 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2557 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2558 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2559 AR_KEYTABLE_TYPE_CLR);
f078f209 2560
f1dc5600
S		 2561 } else {
2562 u32 mic0, mic2;
f078f209 2563
f1dc5600
S		 2564 mic0 = get_unaligned_le32(k->kv_mic + 0);
2565 mic2 = get_unaligned_le32(k->kv_mic + 4);
2566 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2567 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2568 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2569 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2571 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2572 AR_KEYTABLE_TYPE_CLR);
2573 }
2574 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2575 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2577 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2578 } else {
2579 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2581 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2584 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2585
f1dc5600
S		 2586 (void) ath9k_hw_keysetmac(ah, entry, mac);
2587 }
f078f209 2588
f1dc5600
S		 2589 if (ah->ah_curchan == NULL)
2590 return true;
f078f209
LR		 2591
2592 return true;
2593}
2594
f1dc5600 2595bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
f078f209 2596{
f1dc5600
S		 2597 if (entry < ah->ah_caps.keycache_size) {
2598 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2599 if (val & AR_KEYTABLE_VALID)
2600 return true;
2601 }
2602 return false;
f078f209
LR		 2603}
2604
f1dc5600
S		 2605/******************************/
2606/* Power Management (Chipset) */
2607/******************************/
2608
2609static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
f078f209 2610{
f1dc5600
S		 2611 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2612 if (setChip) {
2613 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2614 AR_RTC_FORCE_WAKE_EN);
2615 if (!AR_SREV_9100(ah))
2616 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2617
f1dc5600
S		 2618 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2619 AR_RTC_RESET_EN);
2620 }
f078f209
LR		 2621}
2622
f1dc5600 2623static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
f078f209 2624{
f1dc5600
S		 2625 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2626 if (setChip) {
2627 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2628
f1dc5600
S		 2629 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2630 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2631 AR_RTC_FORCE_WAKE_ON_INT);
2632 } else {
2633 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2634 AR_RTC_FORCE_WAKE_EN);
f078f209 2635 }
f078f209 2636 }
f078f209
LR		 2637}
2638
f1dc5600
S		 2639static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2640 int setChip)
f078f209 2641{
f1dc5600
S		 2642 u32 val;
2643 int i;
f078f209 2644
f1dc5600
S		 2645 if (setChip) {
2646 if ((REG_READ(ah, AR_RTC_STATUS) &
2647 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2648 if (ath9k_hw_set_reset_reg(ah,
2649 ATH9K_RESET_POWER_ON) != true) {
2650 return false;
2651 }
2652 }
2653 if (AR_SREV_9100(ah))
2654 REG_SET_BIT(ah, AR_RTC_RESET,
2655 AR_RTC_RESET_EN);
f078f209 2656
f1dc5600
S		 2657 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2658 AR_RTC_FORCE_WAKE_EN);
2659 udelay(50);
f078f209 2660
f1dc5600
S		 2661 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2662 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2663 if (val == AR_RTC_STATUS_ON)
2664 break;
2665 udelay(50);
2666 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2667 AR_RTC_FORCE_WAKE_EN);
f078f209 2668 }
f1dc5600
S		 2669 if (i == 0) {
2670 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2671 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2672 return false;
f078f209 2673 }
f078f209
LR		 2674 }
2675
f1dc5600 2676 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2677
f1dc5600 2678 return true;
f078f209
LR		 2679}
2680
f1dc5600
S		 2681bool ath9k_hw_setpower(struct ath_hal *ah,
2682 enum ath9k_power_mode mode)
f078f209
LR		 2683{
2684 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600
S		 2685 static const char *modes[] = {
2686 "AWAKE",
2687 "FULL-SLEEP",
2688 "NETWORK SLEEP",
2689 "UNDEFINED"
2690 };
2691 int status = true, setChip = true;
2692
04bd4638 2693 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
f1dc5600
S		 2694 modes[ahp->ah_powerMode], modes[mode],
2695 setChip ? "set chip " : "");
2696
2697 switch (mode) {
2698 case ATH9K_PM_AWAKE:
2699 status = ath9k_hw_set_power_awake(ah, setChip);
2700 break;
2701 case ATH9K_PM_FULL_SLEEP:
2702 ath9k_set_power_sleep(ah, setChip);
2703 ahp->ah_chipFullSleep = true;
2704 break;
2705 case ATH9K_PM_NETWORK_SLEEP:
2706 ath9k_set_power_network_sleep(ah, setChip);
2707 break;
f078f209 2708 default:
f1dc5600 2709 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2710 "Unknown power mode %u\n", mode);
f078f209
LR		 2711 return false;
2712 }
f1dc5600
S		 2713 ahp->ah_powerMode = mode;
2714
2715 return status;
f078f209
LR		 2716}
2717
f1dc5600 2718void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
f078f209
LR		 2719{
2720 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 2721 u8 i;
f078f209 2722
f1dc5600
S		 2723 if (ah->ah_isPciExpress != true)
2724 return;
f078f209 2725
f1dc5600
S		 2726 if (ah->ah_config.pcie_powersave_enable == 2)
2727 return;
2728
2729 if (restore)
2730 return;
2731
2732 if (AR_SREV_9280_20_OR_LATER(ah)) {
2733 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2734 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2735 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
f078f209 2736 }
f1dc5600
S		 2737 udelay(1000);
2738 } else if (AR_SREV_9280(ah) &&
2739 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2740 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2741 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2742
2743 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2744 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2745 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2746
2747 if (ah->ah_config.pcie_clock_req)
2748 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2749 else
2750 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2751
2752 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2753 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2754 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2755
2756 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2757
2758 udelay(1000);
2759 } else {
2760 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2761 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2762 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2763 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2764 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2766 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2767 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2768 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2769 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 2770 }
2771
f1dc5600
S		 2772 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2773
2774 if (ah->ah_config.pcie_waen) {
2775 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2776 } else {
e7594072
SB		 2777 if (AR_SREV_9285(ah))
2778 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2779 else if (AR_SREV_9280(ah))
2780 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 2781 else
e7594072 2782 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 2783 }
e7594072 2784
f078f209
LR		 2785}
2786
f1dc5600
S		 2787/**********************/
2788/* Interrupt Handling */
2789/**********************/
2790
f078f209
LR		 2791bool ath9k_hw_intrpend(struct ath_hal *ah)
2792{
2793 u32 host_isr;
2794
2795 if (AR_SREV_9100(ah))
2796 return true;
2797
2798 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2799 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2800 return true;
2801
2802 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2803 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2804 && (host_isr != AR_INTR_SPURIOUS))
2805 return true;
2806
2807 return false;
2808}
2809
2810bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2811{
2812 u32 isr = 0;
2813 u32 mask2 = 0;
60b67f51 2814 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 2815 u32 sync_cause = 0;
2816 bool fatal_int = false;
f1dc5600 2817 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 2818
2819 if (!AR_SREV_9100(ah)) {
2820 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2821 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2822 == AR_RTC_STATUS_ON) {
2823 isr = REG_READ(ah, AR_ISR);
2824 }
2825 }
2826
f1dc5600
S		 2827 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2828 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2829
2830 *masked = 0;
2831
2832 if (!isr && !sync_cause)
2833 return false;
2834 } else {
2835 *masked = 0;
2836 isr = REG_READ(ah, AR_ISR);
2837 }
2838
2839 if (isr) {
f078f209
LR		 2840 if (isr & AR_ISR_BCNMISC) {
2841 u32 isr2;
2842 isr2 = REG_READ(ah, AR_ISR_S2);
2843 if (isr2 & AR_ISR_S2_TIM)
2844 mask2 |= ATH9K_INT_TIM;
2845 if (isr2 & AR_ISR_S2_DTIM)
2846 mask2 |= ATH9K_INT_DTIM;
2847 if (isr2 & AR_ISR_S2_DTIMSYNC)
2848 mask2 |= ATH9K_INT_DTIMSYNC;
2849 if (isr2 & (AR_ISR_S2_CABEND))
2850 mask2 |= ATH9K_INT_CABEND;
2851 if (isr2 & AR_ISR_S2_GTT)
2852 mask2 |= ATH9K_INT_GTT;
2853 if (isr2 & AR_ISR_S2_CST)
2854 mask2 |= ATH9K_INT_CST;
2855 }
2856
2857 isr = REG_READ(ah, AR_ISR_RAC);
2858 if (isr == 0xffffffff) {
2859 *masked = 0;
2860 return false;
2861 }
2862
2863 *masked = isr & ATH9K_INT_COMMON;
2864
2865 if (ahp->ah_intrMitigation) {
f078f209
LR		 2866 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2867 *masked |= ATH9K_INT_RX;
2868 }
2869
2870 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2871 *masked |= ATH9K_INT_RX;
2872 if (isr &
2873 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2874 AR_ISR_TXEOL)) {
2875 u32 s0_s, s1_s;
2876
2877 *masked |= ATH9K_INT_TX;
2878
2879 s0_s = REG_READ(ah, AR_ISR_S0_S);
2880 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2881 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2882
2883 s1_s = REG_READ(ah, AR_ISR_S1_S);
2884 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2885 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2886 }
2887
2888 if (isr & AR_ISR_RXORN) {
2889 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2890 "receive FIFO overrun interrupt\n");
f078f209
LR		 2891 }
2892
2893 if (!AR_SREV_9100(ah)) {
60b67f51 2894 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2895 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2896 if (isr5 & AR_ISR_S5_TIM_TIMER)
2897 *masked |= ATH9K_INT_TIM_TIMER;
2898 }
2899 }
2900
2901 *masked |= mask2;
2902 }
f1dc5600 2903
f078f209
LR		 2904 if (AR_SREV_9100(ah))
2905 return true;
f1dc5600 2906
f078f209
LR		 2907 if (sync_cause) {
2908 fatal_int =
2909 (sync_cause &
2910 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2911 ? true : false;
2912
2913 if (fatal_int) {
2914 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2915 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2916 "received PCI FATAL interrupt\n");
f078f209
LR		 2917 }
2918 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2919 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2920 "received PCI PERR interrupt\n");
f078f209
LR		 2921 }
2922 }
2923 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2924 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2925 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2926 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2927 REG_WRITE(ah, AR_RC, 0);
2928 *masked |= ATH9K_INT_FATAL;
2929 }
2930 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2931 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2932 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2933 }
2934
2935 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2936 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2937 }
f1dc5600 2938
f078f209
LR		 2939 return true;
2940}
2941
2942enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2943{
2944 return AH5416(ah)->ah_maskReg;
2945}
2946
2947enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2948{
2949 struct ath_hal_5416 *ahp = AH5416(ah);
2950 u32 omask = ahp->ah_maskReg;
2951 u32 mask, mask2;
60b67f51 2952 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2953
04bd4638 2954 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2955
2956 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 2957 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2958 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2959 (void) REG_READ(ah, AR_IER);
2960 if (!AR_SREV_9100(ah)) {
2961 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2962 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2963
2964 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2965 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2966 }
2967 }
2968
2969 mask = ints & ATH9K_INT_COMMON;
2970 mask2 = 0;
2971
2972 if (ints & ATH9K_INT_TX) {
2973 if (ahp->ah_txOkInterruptMask)
2974 mask |= AR_IMR_TXOK;
2975 if (ahp->ah_txDescInterruptMask)
2976 mask |= AR_IMR_TXDESC;
2977 if (ahp->ah_txErrInterruptMask)
2978 mask |= AR_IMR_TXERR;
2979 if (ahp->ah_txEolInterruptMask)
2980 mask |= AR_IMR_TXEOL;
2981 }
2982 if (ints & ATH9K_INT_RX) {
2983 mask |= AR_IMR_RXERR;
2984 if (ahp->ah_intrMitigation)
2985 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2986 else
2987 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2988 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2989 mask |= AR_IMR_GENTMR;
2990 }
2991
2992 if (ints & (ATH9K_INT_BMISC)) {
2993 mask |= AR_IMR_BCNMISC;
2994 if (ints & ATH9K_INT_TIM)
2995 mask2 |= AR_IMR_S2_TIM;
2996 if (ints & ATH9K_INT_DTIM)
2997 mask2 |= AR_IMR_S2_DTIM;
2998 if (ints & ATH9K_INT_DTIMSYNC)
2999 mask2 |= AR_IMR_S2_DTIMSYNC;
3000 if (ints & ATH9K_INT_CABEND)
3001 mask2 |= (AR_IMR_S2_CABEND);
3002 }
3003
3004 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3005 mask |= AR_IMR_BCNMISC;
3006 if (ints & ATH9K_INT_GTT)
3007 mask2 |= AR_IMR_S2_GTT;
3008 if (ints & ATH9K_INT_CST)
3009 mask2 |= AR_IMR_S2_CST;
3010 }
3011
04bd4638 3012 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3013 REG_WRITE(ah, AR_IMR, mask);
3014 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3015 AR_IMR_S2_DTIM |
3016 AR_IMR_S2_DTIMSYNC |
3017 AR_IMR_S2_CABEND |
3018 AR_IMR_S2_CABTO |
3019 AR_IMR_S2_TSFOOR |
3020 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3021 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3022 ahp->ah_maskReg = ints;
3023
60b67f51 3024 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3025 if (ints & ATH9K_INT_TIM_TIMER)
3026 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3027 else
3028 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3029 }
3030
3031 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3032 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3033 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3034 if (!AR_SREV_9100(ah)) {
3035 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3036 AR_INTR_MAC_IRQ);
3037 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3038
3039
3040 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3041 AR_INTR_SYNC_DEFAULT);
3042 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3043 AR_INTR_SYNC_DEFAULT);
3044 }
3045 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3046 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3047 }
3048
3049 return omask;
3050}
3051
f1dc5600
S		 3052/*******************/
3053/* Beacon Handling */
3054/*******************/
3055
3056void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
f078f209
LR		 3057{
3058 struct ath_hal_5416 *ahp = AH5416(ah);
3059 int flags = 0;
3060
3061 ahp->ah_beaconInterval = beacon_period;
3062
3063 switch (ah->ah_opmode) {
d97809db
CM		 3064 case NL80211_IFTYPE_STATION:
3065 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3066 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3067 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3068 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3069 flags |= AR_TBTT_TIMER_EN;
3070 break;
d97809db 3071 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 3072 REG_SET_BIT(ah, AR_TXCFG,
3073 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3074 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3075 TU_TO_USEC(next_beacon +
3076 (ahp->ah_atimWindow ? ahp->
3077 ah_atimWindow : 1)));
3078 flags |= AR_NDP_TIMER_EN;
d97809db 3079 case NL80211_IFTYPE_AP:
f078f209
LR		 3080 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3081 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3082 TU_TO_USEC(next_beacon -
3083 ah->ah_config.
60b67f51 3084 dma_beacon_response_time));
f078f209
LR		 3085 REG_WRITE(ah, AR_NEXT_SWBA,
3086 TU_TO_USEC(next_beacon -
3087 ah->ah_config.
60b67f51 3088 sw_beacon_response_time));
f078f209
LR		 3089 flags |=
3090 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3091 break;
d97809db
CM		 3092 default:
3093 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3094 "%s: unsupported opmode: %d\n",
3095 __func__, ah->ah_opmode);
3096 return;
3097 break;
f078f209
LR		 3098 }
3099
3100 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3101 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3102 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3103 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3104
3105 beacon_period &= ~ATH9K_BEACON_ENA;
3106 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3107 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3108 ath9k_hw_reset_tsf(ah);
3109 }
3110
3111 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3112}
3113
f1dc5600
S		 3114void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3115 const struct ath9k_beacon_state *bs)
f078f209
LR		 3116{
3117 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
60b67f51 3118 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 3119
3120 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3121
3122 REG_WRITE(ah, AR_BEACON_PERIOD,
3123 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3124 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3125 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3126
3127 REG_RMW_FIELD(ah, AR_RSSI_THR,
3128 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3129
3130 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3131
3132 if (bs->bs_sleepduration > beaconintval)
3133 beaconintval = bs->bs_sleepduration;
3134
3135 dtimperiod = bs->bs_dtimperiod;
3136 if (bs->bs_sleepduration > dtimperiod)
3137 dtimperiod = bs->bs_sleepduration;
3138
3139 if (beaconintval == dtimperiod)
3140 nextTbtt = bs->bs_nextdtim;
3141 else
3142 nextTbtt = bs->bs_nexttbtt;
3143
04bd4638
S		 3144 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3145 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3146 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3147 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3148
f1dc5600
S		 3149 REG_WRITE(ah, AR_NEXT_DTIM,
3150 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3151 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3152
f1dc5600
S		 3153 REG_WRITE(ah, AR_SLEEP1,
3154 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3155 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3156
f1dc5600
S		 3157 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3158 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3159 else
3160 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3161
f1dc5600
S		 3162 REG_WRITE(ah, AR_SLEEP2,
3163 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3164
f1dc5600
S		 3165 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3166 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3167
f1dc5600
S		 3168 REG_SET_BIT(ah, AR_TIMER_MODE,
3169 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3170 AR_DTIM_TIMER_EN);
f078f209 3171
f078f209
LR		 3172}
3173
f1dc5600
S		 3174/*******************/
3175/* HW Capabilities */
3176/*******************/
3177
3178bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
f078f209
LR		 3179{
3180 struct ath_hal_5416 *ahp = AH5416(ah);
60b67f51 3181 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f1dc5600 3182 u16 capField = 0, eeval;
f078f209 3183
f1dc5600 3184 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
f078f209 3185
f1dc5600 3186 ah->ah_currentRD = eeval;
f078f209 3187
f1dc5600
S		 3188 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3189 ah->ah_currentRDExt = eeval;
f078f209 3190
f1dc5600
S		 3191 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3192
d97809db 3193 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
f1dc5600
S		 3194 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3195 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3196 ah->ah_currentRD += 5;
3197 else if (ah->ah_currentRD == 0x41)
3198 ah->ah_currentRD = 0x43;
3199 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
04bd4638 3200 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
f1dc5600 3201 }
f078f209 3202
f1dc5600
S		 3203 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3204 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3205
f1dc5600
S		 3206 if (eeval & AR5416_OPFLAGS_11A) {
3207 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3208 if (ah->ah_config.ht_enable) {
3209 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3210 set_bit(ATH9K_MODE_11NA_HT20,
3211 pCap->wireless_modes);
3212 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3213 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3214 pCap->wireless_modes);
3215 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3216 pCap->wireless_modes);
3217 }
f078f209 3218 }
f078f209
LR		 3219 }
3220
f1dc5600
S		 3221 if (eeval & AR5416_OPFLAGS_11G) {
3222 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3223 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3224 if (ah->ah_config.ht_enable) {
3225 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3226 set_bit(ATH9K_MODE_11NG_HT20,
3227 pCap->wireless_modes);
3228 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3229 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3230 pCap->wireless_modes);
3231 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3232 pCap->wireless_modes);
3233 }
3234 }
f078f209 3235 }
f1dc5600
S		 3236
3237 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3238 if ((ah->ah_isPciExpress)
3239 || (eeval & AR5416_OPFLAGS_11A)) {
3240 pCap->rx_chainmask =
3241 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
f078f209 3242 } else {
f1dc5600
S		 3243 pCap->rx_chainmask =
3244 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
f078f209
LR		 3245 }
3246
f1dc5600
S		 3247 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3248 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3249
f1dc5600
S		 3250 pCap->low_2ghz_chan = 2312;
3251 pCap->high_2ghz_chan = 2732;
f078f209 3252
f1dc5600
S		 3253 pCap->low_5ghz_chan = 4920;
3254 pCap->high_5ghz_chan = 6100;
f078f209 3255
f1dc5600
S		 3256 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3257 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3258 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3259
f1dc5600
S		 3260 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3261 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3262 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3263
f1dc5600 3264 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
f078f209 3265
f1dc5600
S		 3266 if (ah->ah_config.ht_enable)
3267 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3268 else
3269 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3270
f1dc5600
S		 3271 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3272 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3273 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3274 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3275
f1dc5600
S		 3276 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3277 pCap->total_queues =
3278 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3279 else
3280 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3281
f1dc5600
S		 3282 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3283 pCap->keycache_size =
3284 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3285 else
3286 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3287
f1dc5600
S		 3288 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3289 pCap->num_mr_retries = 4;
3290 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3291
cb33c412
SB		 3292 if (AR_SREV_9285_10_OR_LATER(ah))
3293 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3294 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3295 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3296 else
3297 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3298
f1dc5600
S		 3299 if (AR_SREV_9280_10_OR_LATER(ah)) {
3300 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3301 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3302 } else {
3303 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3304 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
f078f209
LR		 3305 }
3306
f1dc5600
S		 3307 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3308 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3309 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3310 } else {
3311 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3312 }
3313
f1dc5600
S		 3314 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3315
e97275cb 3316#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600
S		 3317 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3318 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3319 ah->ah_rfkill_gpio =
3320 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3321 ah->ah_rfkill_polarity =
3322 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3323
3324 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3325 }
f1dc5600 3326#endif
f078f209 3327
f1dc5600
S		 3328 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3329 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3330 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3331 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3332 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3333 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3334 else
f1dc5600 3335 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3336
e7594072 3337 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3338 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3339 else
3340 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3341
f1dc5600
S		 3342 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3343 pCap->reg_cap =
3344 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3345 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3346 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3347 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3348 } else {
f1dc5600
S		 3349 pCap->reg_cap =
3350 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3351 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3352 }
f078f209 3353
f1dc5600
S		 3354 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3355
3356 pCap->num_antcfg_5ghz =
2df1bff4 3357 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3358 pCap->num_antcfg_2ghz =
2df1bff4 3359 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3360
c97c92d9
VT		 3361 if (AR_SREV_9280_10_OR_LATER(ah)) {
3362 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3363 ah->ah_btactive_gpio = 6;
3364 ah->ah_wlanactive_gpio = 5;
3365 }
3366
f1dc5600 3367 return true;
f078f209
LR		 3368}
3369
f1dc5600
S		 3370bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3371 u32 capability, u32 *result)
f078f209 3372{
f1dc5600
S		 3373 struct ath_hal_5416 *ahp = AH5416(ah);
3374 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 3375
f1dc5600
S		 3376 switch (type) {
3377 case ATH9K_CAP_CIPHER:
3378 switch (capability) {
3379 case ATH9K_CIPHER_AES_CCM:
3380 case ATH9K_CIPHER_AES_OCB:
3381 case ATH9K_CIPHER_TKIP:
3382 case ATH9K_CIPHER_WEP:
3383 case ATH9K_CIPHER_MIC:
3384 case ATH9K_CIPHER_CLR:
3385 return true;
3386 default:
3387 return false;
3388 }
3389 case ATH9K_CAP_TKIP_MIC:
3390 switch (capability) {
3391 case 0:
3392 return true;
3393 case 1:
3394 return (ahp->ah_staId1Defaults &
3395 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3396 false;
3397 }
3398 case ATH9K_CAP_TKIP_SPLIT:
3399 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3400 false : true;
3401 case ATH9K_CAP_WME_TKIPMIC:
3402 return 0;
3403 case ATH9K_CAP_PHYCOUNTERS:
3404 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3405 case ATH9K_CAP_DIVERSITY:
3406 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3407 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3408 true : false;
3409 case ATH9K_CAP_PHYDIAG:
3410 return true;
3411 case ATH9K_CAP_MCAST_KEYSRCH:
3412 switch (capability) {
3413 case 0:
3414 return true;
3415 case 1:
3416 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3417 return false;
3418 } else {
3419 return (ahp->ah_staId1Defaults &
3420 AR_STA_ID1_MCAST_KSRCH) ? true :
3421 false;
3422 }
3423 }
3424 return false;
3425 case ATH9K_CAP_TSF_ADJUST:
3426 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3427 true : false;
3428 case ATH9K_CAP_RFSILENT:
3429 if (capability == 3)
3430 return false;
3431 case ATH9K_CAP_ANT_CFG_2GHZ:
3432 *result = pCap->num_antcfg_2ghz;
3433 return true;
3434 case ATH9K_CAP_ANT_CFG_5GHZ:
3435 *result = pCap->num_antcfg_5ghz;
3436 return true;
3437 case ATH9K_CAP_TXPOW:
3438 switch (capability) {
3439 case 0:
3440 return 0;
3441 case 1:
3442 *result = ah->ah_powerLimit;
3443 return 0;
3444 case 2:
3445 *result = ah->ah_maxPowerLevel;
3446 return 0;
3447 case 3:
3448 *result = ah->ah_tpScale;
3449 return 0;
3450 }
3451 return false;
3452 default:
3453 return false;
f078f209 3454 }
f078f209
LR		 3455}
3456
f1dc5600
S		 3457bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3458 u32 capability, u32 setting, int *status)
f078f209 3459{
f078f209 3460 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 3461 u32 v;
f078f209 3462
f1dc5600
S		 3463 switch (type) {
3464 case ATH9K_CAP_TKIP_MIC:
3465 if (setting)
3466 ahp->ah_staId1Defaults |=
3467 AR_STA_ID1_CRPT_MIC_ENABLE;
3468 else
3469 ahp->ah_staId1Defaults &=
3470 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3471 return true;
3472 case ATH9K_CAP_DIVERSITY:
3473 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3474 if (setting)
3475 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3476 else
3477 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3478 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3479 return true;
3480 case ATH9K_CAP_MCAST_KEYSRCH:
3481 if (setting)
3482 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3483 else
3484 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3485 return true;
3486 case ATH9K_CAP_TSF_ADJUST:
3487 if (setting)
3488 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3489 else
3490 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3491 return true;
3492 default:
3493 return false;
f078f209
LR		 3494 }
3495}
3496
f1dc5600
S		 3497/****************************/
3498/* GPIO / RFKILL / Antennae */
3499/****************************/
f078f209 3500
f1dc5600
S		 3501static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3502 u32 gpio, u32 type)
3503{
3504 int addr;
3505 u32 gpio_shift, tmp;
f078f209 3506
f1dc5600
S		 3507 if (gpio > 11)
3508 addr = AR_GPIO_OUTPUT_MUX3;
3509 else if (gpio > 5)
3510 addr = AR_GPIO_OUTPUT_MUX2;
3511 else
3512 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3513
f1dc5600 3514 gpio_shift = (gpio % 6) * 5;
f078f209 3515
f1dc5600
S		 3516 if (AR_SREV_9280_20_OR_LATER(ah)
3517 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3518 REG_RMW(ah, addr, (type << gpio_shift),
3519 (0x1f << gpio_shift));
f078f209 3520 } else {
f1dc5600
S		 3521 tmp = REG_READ(ah, addr);
3522 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3523 tmp &= ~(0x1f << gpio_shift);
3524 tmp |= (type << gpio_shift);
3525 REG_WRITE(ah, addr, tmp);
f078f209 3526 }
f078f209
LR		 3527}
3528
f1dc5600 3529void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
f078f209 3530{
f1dc5600 3531 u32 gpio_shift;
f078f209 3532
f1dc5600 3533 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
f078f209 3534
f1dc5600 3535 gpio_shift = gpio << 1;
f078f209 3536
f1dc5600
S		 3537 REG_RMW(ah,
3538 AR_GPIO_OE_OUT,
3539 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3540 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3541}
3542
f1dc5600 3543u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
f078f209 3544{
cb33c412
SB		 3545#define MS_REG_READ(x, y) \
3546 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3547
f1dc5600
S		 3548 if (gpio >= ah->ah_caps.num_gpio_pins)
3549 return 0xffffffff;
f078f209 3550
cb33c412
SB		 3551 if (AR_SREV_9285_10_OR_LATER(ah))
3552 return MS_REG_READ(AR9285, gpio) != 0;
3553 else if (AR_SREV_9280_10_OR_LATER(ah))
3554 return MS_REG_READ(AR928X, gpio) != 0;
3555 else
3556 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3557}
3558
f1dc5600
S		 3559void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3560 u32 ah_signal_type)
f078f209 3561{
f1dc5600 3562 u32 gpio_shift;
f078f209 3563
f1dc5600 3564 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3565
f1dc5600 3566 gpio_shift = 2 * gpio;
f078f209 3567
f1dc5600
S		 3568 REG_RMW(ah,
3569 AR_GPIO_OE_OUT,
3570 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3571 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3572}
3573
f1dc5600 3574void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
f078f209 3575{
f1dc5600
S		 3576 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3577 AR_GPIO_BIT(gpio));
f078f209
LR		 3578}
3579
e97275cb 3580#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600 3581void ath9k_enable_rfkill(struct ath_hal *ah)
f078f209 3582{
f1dc5600
S		 3583 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3584 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
f078f209 3585
f1dc5600
S		 3586 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3587 AR_GPIO_INPUT_MUX2_RFSILENT);
3588
3589 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3590 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
f078f209 3591}
f1dc5600 3592#endif
f078f209 3593
f1dc5600 3594int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
f078f209 3595{
f1dc5600
S		 3596 struct ath9k_channel *chan = ah->ah_curchan;
3597 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3598 u16 ant_config;
3599 u32 halNumAntConfig;
f078f209 3600
f1dc5600
S		 3601 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3602 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
f078f209 3603
f1dc5600
S		 3604 if (cfg < halNumAntConfig) {
3605 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3606 cfg, &ant_config)) {
3607 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3608 return 0;
f078f209 3609 }
f078f209
LR		 3610 }
3611
f1dc5600 3612 return -EINVAL;
f078f209
LR		 3613}
3614
f1dc5600 3615u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
f078f209 3616{
f1dc5600 3617 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3618}
3619
f1dc5600 3620void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
f078f209 3621{
f1dc5600 3622 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3623}
3624
f1dc5600
S		 3625bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3626 enum ath9k_ant_setting settings,
3627 struct ath9k_channel *chan,
3628 u8 *tx_chainmask,
3629 u8 *rx_chainmask,
3630 u8 *antenna_cfgd)
f078f209 3631{
f1dc5600
S		 3632 struct ath_hal_5416 *ahp = AH5416(ah);
3633 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3634
f1dc5600
S		 3635 if (AR_SREV_9280(ah)) {
3636 if (!tx_chainmask_cfg) {
f078f209 3637
f1dc5600
S		 3638 tx_chainmask_cfg = *tx_chainmask;
3639 rx_chainmask_cfg = *rx_chainmask;
3640 }
f078f209 3641
f1dc5600
S		 3642 switch (settings) {
3643 case ATH9K_ANT_FIXED_A:
3644 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3645 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3646 *antenna_cfgd = true;
3647 break;
3648 case ATH9K_ANT_FIXED_B:
3649 if (ah->ah_caps.tx_chainmask >
3650 ATH9K_ANTENNA1_CHAINMASK) {
3651 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3652 }
3653 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3654 *antenna_cfgd = true;
3655 break;
3656 case ATH9K_ANT_VARIABLE:
3657 *tx_chainmask = tx_chainmask_cfg;
3658 *rx_chainmask = rx_chainmask_cfg;
3659 *antenna_cfgd = true;
3660 break;
3661 default:
3662 break;
3663 }
3664 } else {
3665 ahp->ah_diversityControl = settings;
f078f209 3666 }
f078f209 3667
f1dc5600 3668 return true;
f078f209
LR		 3669}
3670
f1dc5600
S		 3671/*********************/
3672/* General Operation */
3673/*********************/
3674
3675u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
f078f209 3676{
f1dc5600
S		 3677 u32 bits = REG_READ(ah, AR_RX_FILTER);
3678 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3679
f1dc5600
S		 3680 if (phybits & AR_PHY_ERR_RADAR)
3681 bits |= ATH9K_RX_FILTER_PHYRADAR;
3682 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3683 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3684
f1dc5600 3685 return bits;
f078f209
LR		 3686}
3687
f1dc5600 3688void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
f078f209 3689{
f1dc5600 3690 u32 phybits;
f078f209 3691
f1dc5600
S		 3692 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3693 phybits = 0;
3694 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3695 phybits |= AR_PHY_ERR_RADAR;
3696 if (bits & ATH9K_RX_FILTER_PHYERR)
3697 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3698 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3699
f1dc5600
S		 3700 if (phybits)
3701 REG_WRITE(ah, AR_RXCFG,
3702 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3703 else
3704 REG_WRITE(ah, AR_RXCFG,
3705 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3706}
f078f209 3707
f1dc5600
S		 3708bool ath9k_hw_phy_disable(struct ath_hal *ah)
3709{
3710 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3711}
f078f209 3712
f1dc5600
S		 3713bool ath9k_hw_disable(struct ath_hal *ah)
3714{
3715 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3716 return false;
f078f209 3717
f1dc5600 3718 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3719}
3720
f1dc5600 3721bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
f078f209 3722{
f1dc5600 3723 struct ath9k_channel *chan = ah->ah_curchan;
f078f209 3724
f1dc5600 3725 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3726
f1dc5600
S		 3727 if (ath9k_hw_set_txpower(ah, chan,
3728 ath9k_regd_get_ctl(ah, chan),
3729 ath9k_regd_get_antenna_allowed(ah, chan),
3730 chan->maxRegTxPower * 2,
3731 min((u32) MAX_RATE_POWER,
3732 (u32) ah->ah_powerLimit)) != 0)
6f255425 3733 return false;
f1dc5600 3734
6f255425
LR		 3735 return true;
3736}
3737
f1dc5600 3738void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
f078f209 3739{
f1dc5600 3740 struct ath_hal_5416 *ahp = AH5416(ah);
6f255425 3741
f1dc5600 3742 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
f078f209
LR		 3743}
3744
f1dc5600 3745bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
f078f209
LR		 3746{
3747 struct ath_hal_5416 *ahp = AH5416(ah);
3748
f1dc5600
S		 3749 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3750
f078f209
LR		 3751 return true;
3752}
3753
f1dc5600 3754void ath9k_hw_setopmode(struct ath_hal *ah)
f078f209 3755{
f1dc5600 3756 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 3757}
3758
f1dc5600 3759void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
f078f209 3760{
f1dc5600
S		 3761 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3762 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3763}
3764
f1dc5600 3765void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
f078f209 3766{
f1dc5600 3767 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3768
f1dc5600 3769 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
f078f209
LR		 3770}
3771
f1dc5600 3772bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
f078f209 3773{
f1dc5600
S		 3774 struct ath_hal_5416 *ahp = AH5416(ah);
3775
3776 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
f078f209 3777
f1dc5600
S		 3778 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3779 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
f078f209
LR		 3780
3781 return true;
3782}
3783
f1dc5600 3784void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
f078f209 3785{
f1dc5600 3786 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3787
f1dc5600
S		 3788 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3789 ahp->ah_assocId = assocId;
f078f209 3790
f1dc5600
S		 3791 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3792 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3793 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 3794}
3795
f1dc5600 3796u64 ath9k_hw_gettsf64(struct ath_hal *ah)
f078f209 3797{
f1dc5600 3798 u64 tsf;
f078f209 3799
f1dc5600
S		 3800 tsf = REG_READ(ah, AR_TSF_U32);
3801 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3802
f1dc5600
S		 3803 return tsf;
3804}
f078f209 3805
f1dc5600
S		 3806void ath9k_hw_reset_tsf(struct ath_hal *ah)
3807{
3808 int count;
f078f209 3809
f1dc5600
S		 3810 count = 0;
3811 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3812 count++;
3813 if (count > 10) {
3814 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 3815 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f1dc5600 3816 break;
f078f209 3817 }
f1dc5600
S		 3818 udelay(10);
3819 }
3820 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3821}
f078f209 3822
f1dc5600
S		 3823bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3824{
3825 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3826
f1dc5600
S		 3827 if (setting)
3828 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3829 else
3830 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
f078f209 3831
f1dc5600
S		 3832 return true;
3833}
f078f209 3834
f1dc5600
S		 3835bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3836{
3837 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3838
f1dc5600 3839 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 3840 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
f1dc5600
S		 3841 ahp->ah_slottime = (u32) -1;
3842 return false;
3843 } else {
3844 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3845 ahp->ah_slottime = us;
3846 return true;
f078f209 3847 }
f1dc5600
S		 3848}
3849
3850void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3851{
3852 u32 macmode;
3853
3854 if (mode == ATH9K_HT_MACMODE_2040 &&
3855 !ah->ah_config.cwm_ignore_extcca)
3856 macmode = AR_2040_JOINED_RX_CLEAR;
3857 else
3858 macmode = 0;
f078f209 3859
f1dc5600 3860 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3861}
c97c92d9
VT		 3862
3863/***************************/
3864/* Bluetooth Coexistence */
3865/***************************/
3866
3867void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3868{
3869 /* connect bt_active to baseband */
3870 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3871 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3872 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3873
3874 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3875 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3876
3877 /* Set input mux for bt_active to gpio pin */
3878 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3879 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3880 ah->ah_btactive_gpio);
3881
3882 /* Configure the desired gpio port for input */
3883 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3884
3885 /* Configure the desired GPIO port for TX_FRAME output */
3886 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3887 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3888}
Ubuntu Artful kernel mirror