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cfg80211: allow users to help a driver's compliance
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / hw.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
20#include "core.h"
21#include "hw.h"
22#include "reg.h"
23#include "phy.h"
24#include "initvals.h"
25
138ab2e4
VT		 26static int btcoex_enable;
27module_param(btcoex_enable, bool, 0);
28MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
29
4febf7b8
LR		 30#define ATH9K_CLOCK_RATE_CCK 22
31#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
32#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 33
f1dc5600
S		 34static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
35static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
36 enum ath9k_ht_macmode macmode);
37static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
e7594072 38 struct ar5416_eeprom_def *pEepData,
f1dc5600
S		 39 u32 reg, u32 value);
40static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
41static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
f078f209 42
f1dc5600
S		 43/********************/
44/* Helper Functions */
45/********************/
f078f209 46
f1dc5600
S		 47static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
48{
4febf7b8
LR		 49 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
50 if (!ah->ah_curchan) /* should really check for CCK instead */
51 return clks / ATH9K_CLOCK_RATE_CCK;
52 if (conf->channel->band == IEEE80211_BAND_2GHZ)
53 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
54 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 55}
f078f209 56
f1dc5600
S		 57static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58{
4febf7b8
LR		 59 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
f1dc5600
S		 61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64}
f078f209 65
f1dc5600
S		 66static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
67{
4febf7b8
LR		 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69 if (!ah->ah_curchan) /* should really check for CCK instead */
70 return usecs *ATH9K_CLOCK_RATE_CCK;
71 if (conf->channel->band == IEEE80211_BAND_2GHZ)
72 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
73 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 74}
75
76static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77{
4febf7b8
LR		 78 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
79 if (conf_is_ht40(conf))
f1dc5600
S		 80 return ath9k_hw_mac_clks(ah, usecs) * 2;
81 else
82 return ath9k_hw_mac_clks(ah, usecs);
83}
f078f209 84
f1dc5600 85bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
f078f209
LR		 86{
87 int i;
88
89 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
90 if ((REG_READ(ah, reg) & mask) == val)
91 return true;
92
93 udelay(AH_TIME_QUANTUM);
94 }
04bd4638
S		 95
96 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
97 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
98 reg, REG_READ(ah, reg), mask, val);
f078f209 99
f1dc5600 100 return false;
f078f209
LR		 101}
102
103u32 ath9k_hw_reverse_bits(u32 val, u32 n)
104{
105 u32 retval;
106 int i;
107
108 for (i = 0, retval = 0; i < n; i++) {
109 retval = (retval << 1) | (val & 1);
110 val >>= 1;
111 }
112 return retval;
113}
114
f1dc5600
S		 115bool ath9k_get_channel_edges(struct ath_hal *ah,
116 u16 flags, u16 *low,
117 u16 *high)
f078f209 118{
f1dc5600 119 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 120
f1dc5600
S		 121 if (flags & CHANNEL_5GHZ) {
122 *low = pCap->low_5ghz_chan;
123 *high = pCap->high_5ghz_chan;
124 return true;
f078f209 125 }
f1dc5600
S		 126 if ((flags & CHANNEL_2GHZ)) {
127 *low = pCap->low_2ghz_chan;
128 *high = pCap->high_2ghz_chan;
129 return true;
130 }
131 return false;
f078f209
LR		 132}
133
f1dc5600 134u16 ath9k_hw_computetxtime(struct ath_hal *ah,
e63835b0 135 struct ath_rate_table *rates,
f1dc5600
S		 136 u32 frameLen, u16 rateix,
137 bool shortPreamble)
f078f209 138{
f1dc5600
S		 139 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
140 u32 kbps;
f078f209 141
e63835b0 142 kbps = rates->info[rateix].ratekbps;
f078f209 143
f1dc5600
S		 144 if (kbps == 0)
145 return 0;
f078f209 146
f1dc5600 147 switch (rates->info[rateix].phy) {
46d14a58 148 case WLAN_RC_PHY_CCK:
f1dc5600 149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 150 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
46d14a58 155 case WLAN_RC_PHY_OFDM:
f1dc5600
S		 156 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163 } else if (ah->ah_curchan &&
164 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
04bd4638
S		 180 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
181 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 182 rates->info[rateix].phy, rateix);
183 txTime = 0;
184 break;
185 }
f078f209 186
f1dc5600
S		 187 return txTime;
188}
f078f209 189
f1dc5600
S		 190u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
191{
192 if (flags & CHANNEL_2GHZ) {
193 if (freq == 2484)
194 return 14;
195 if (freq < 2484)
196 return (freq - 2407) / 5;
197 else
198 return 15 + ((freq - 2512) / 20);
199 } else if (flags & CHANNEL_5GHZ) {
200 if (ath9k_regd_is_public_safety_sku(ah) &&
201 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
202 return ((freq * 10) +
203 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
204 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
205 return (freq - 4000) / 5;
206 } else {
207 return (freq - 5000) / 5;
208 }
209 } else {
210 if (freq == 2484)
211 return 14;
212 if (freq < 2484)
213 return (freq - 2407) / 5;
214 if (freq < 5000) {
215 if (ath9k_regd_is_public_safety_sku(ah)
216 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
217 return ((freq * 10) +
218 (((freq % 5) ==
219 2) ? 5 : 0) - 49400) / 5;
220 } else if (freq > 4900) {
221 return (freq - 4000) / 5;
222 } else {
223 return 15 + ((freq - 2512) / 20);
224 }
225 }
226 return (freq - 5000) / 5;
227 }
f078f209
LR		 228}
229
f1dc5600
S		 230void ath9k_hw_get_channel_centers(struct ath_hal *ah,
231 struct ath9k_channel *chan,
232 struct chan_centers *centers)
f078f209 233{
f1dc5600 234 int8_t extoff;
f078f209
LR		 235 struct ath_hal_5416 *ahp = AH5416(ah);
236
f1dc5600
S		 237 if (!IS_CHAN_HT40(chan)) {
238 centers->ctl_center = centers->ext_center =
239 centers->synth_center = chan->channel;
240 return;
f078f209 241 }
f078f209 242
f1dc5600
S		 243 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
244 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
245 centers->synth_center =
246 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
247 extoff = 1;
248 } else {
249 centers->synth_center =
250 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
251 extoff = -1;
252 }
f078f209 253
f1dc5600
S		 254 centers->ctl_center =
255 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
256 centers->ext_center =
257 centers->synth_center + (extoff *
258 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
259 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209 260
f078f209
LR		 261}
262
f1dc5600
S		 263/******************/
264/* Chip Revisions */
265/******************/
266
267static void ath9k_hw_read_revisions(struct ath_hal *ah)
f078f209 268{
f1dc5600 269 u32 val;
f078f209 270
f1dc5600 271 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 272
f1dc5600
S		 273 if (val == 0xFF) {
274 val = REG_READ(ah, AR_SREV);
275 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
276 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
277 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
278 } else {
279 if (!AR_SREV_9100(ah))
280 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
f078f209 281
f1dc5600 282 ah->ah_macRev = val & AR_SREV_REVISION;
f078f209 283
f1dc5600
S		 284 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
285 ah->ah_isPciExpress = true;
286 }
f078f209
LR		 287}
288
f1dc5600 289static int ath9k_hw_get_radiorev(struct ath_hal *ah)
f078f209 290{
f1dc5600
S		 291 u32 val;
292 int i;
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 295
f1dc5600
S		 296 for (i = 0; i < 8; i++)
297 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
298 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
299 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 300
f1dc5600 301 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 302}
303
f1dc5600
S		 304/************************************/
305/* HW Attach, Detach, Init Routines */
306/************************************/
307
308static void ath9k_hw_disablepcie(struct ath_hal *ah)
f078f209 309{
f1dc5600
S		 310 if (!AR_SREV_9100(ah))
311 return;
f078f209 312
f1dc5600
S		 313 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 322
f1dc5600 323 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 324}
325
f1dc5600 326static bool ath9k_hw_chip_test(struct ath_hal *ah)
f078f209 327{
f1dc5600
S		 328 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
329 u32 regHold[2];
330 u32 patternData[4] = { 0x55555555,
331 0xaaaaaaaa,
332 0x66666666,
333 0x99999999 };
334 int i, j;
f078f209 335
f1dc5600
S		 336 for (i = 0; i < 2; i++) {
337 u32 addr = regAddr[i];
338 u32 wrData, rdData;
f078f209 339
f1dc5600
S		 340 regHold[i] = REG_READ(ah, addr);
341 for (j = 0; j < 0x100; j++) {
342 wrData = (j << 16) | j;
343 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr);
345 if (rdData != wrData) {
346 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 347 "address test failed "
f1dc5600 348 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 349 addr, wrData, rdData);
f1dc5600
S		 350 return false;
351 }
352 }
353 for (j = 0; j < 4; j++) {
354 wrData = patternData[j];
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (wrData != rdData) {
358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 359 "address test failed "
f1dc5600 360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 361 addr, wrData, rdData);
f1dc5600
S		 362 return false;
363 }
f078f209 364 }
f1dc5600 365 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 366 }
f1dc5600 367 udelay(100);
f078f209
LR		 368 return true;
369}
370
f1dc5600 371static const char *ath9k_hw_devname(u16 devid)
f078f209 372{
f1dc5600
S		 373 switch (devid) {
374 case AR5416_DEVID_PCI:
f1dc5600 375 return "Atheros 5416";
392dff83
BP		 376 case AR5416_DEVID_PCIE:
377 return "Atheros 5418";
f1dc5600
S		 378 case AR9160_DEVID_PCI:
379 return "Atheros 9160";
0c1aa495
GJ		 380 case AR5416_AR9100_DEVID:
381 return "Atheros 9100";
f1dc5600
S		 382 case AR9280_DEVID_PCI:
383 case AR9280_DEVID_PCIE:
384 return "Atheros 9280";
e7594072
SB		 385 case AR9285_DEVID_PCIE:
386 return "Atheros 9285";
f078f209
LR		 387 }
388
f1dc5600
S		 389 return NULL;
390}
f078f209 391
f1dc5600
S		 392static void ath9k_hw_set_defaults(struct ath_hal *ah)
393{
394 int i;
f078f209 395
f1dc5600
S		 396 ah->ah_config.dma_beacon_response_time = 2;
397 ah->ah_config.sw_beacon_response_time = 10;
398 ah->ah_config.additional_swba_backoff = 0;
399 ah->ah_config.ack_6mb = 0x0;
400 ah->ah_config.cwm_ignore_extcca = 0;
401 ah->ah_config.pcie_powersave_enable = 0;
402 ah->ah_config.pcie_l1skp_enable = 0;
403 ah->ah_config.pcie_clock_req = 0;
404 ah->ah_config.pcie_power_reset = 0x100;
405 ah->ah_config.pcie_restore = 0;
406 ah->ah_config.pcie_waen = 0;
407 ah->ah_config.analog_shiftreg = 1;
408 ah->ah_config.ht_enable = 1;
409 ah->ah_config.ofdm_trig_low = 200;
410 ah->ah_config.ofdm_trig_high = 500;
411 ah->ah_config.cck_trig_high = 200;
412 ah->ah_config.cck_trig_low = 100;
413 ah->ah_config.enable_ani = 1;
414 ah->ah_config.noise_immunity_level = 4;
415 ah->ah_config.ofdm_weaksignal_det = 1;
416 ah->ah_config.cck_weaksignal_thr = 0;
417 ah->ah_config.spur_immunity_level = 2;
418 ah->ah_config.firstep_level = 0;
419 ah->ah_config.rssi_thr_high = 40;
420 ah->ah_config.rssi_thr_low = 7;
421 ah->ah_config.diversity_control = 0;
422 ah->ah_config.antenna_switch_swap = 0;
f078f209 423
f1dc5600
S		 424 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
425 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
426 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 427 }
428
f1dc5600 429 ah->ah_config.intr_mitigation = 1;
f078f209
LR		 430}
431
f078f209
LR		 432static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
433 struct ath_softc *sc,
434 void __iomem *mem,
435 int *status)
436{
437 static const u8 defbssidmask[ETH_ALEN] =
438 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
439 struct ath_hal_5416 *ahp;
440 struct ath_hal *ah;
441
442 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
443 if (ahp == NULL) {
444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 445 "Cannot allocate memory for state block\n");
f078f209
LR		 446 *status = -ENOMEM;
447 return NULL;
448 }
449
450 ah = &ahp->ah;
f078f209
LR		 451 ah->ah_sc = sc;
452 ah->ah_sh = mem;
d2d80ee9
S		 453 ah->ah_magic = AR5416_MAGIC;
454 ah->ah_countryCode = CTRY_DEFAULT;
f078f209
LR		 455 ah->ah_devid = devid;
456 ah->ah_subvendorid = 0;
457
458 ah->ah_flags = 0;
459 if ((devid == AR5416_AR9100_DEVID))
460 ah->ah_macVersion = AR_SREV_VERSION_9100;
461 if (!AR_SREV_9100(ah))
462 ah->ah_flags = AH_USE_EEPROM;
463
464 ah->ah_powerLimit = MAX_RATE_POWER;
465 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
f078f209 466 ahp->ah_atimWindow = 0;
60b67f51 467 ahp->ah_diversityControl = ah->ah_config.diversity_control;
f078f209 468 ahp->ah_antennaSwitchSwap =
60b67f51 469 ah->ah_config.antenna_switch_swap;
f078f209
LR		 470 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
471 ahp->ah_beaconInterval = 100;
472 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
473 ahp->ah_slottime = (u32) -1;
474 ahp->ah_acktimeout = (u32) -1;
475 ahp->ah_ctstimeout = (u32) -1;
476 ahp->ah_globaltxtimeout = (u32) -1;
477 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
478
479 ahp->ah_gBeaconRate = 0;
480
481 return ahp;
482}
483
f1dc5600 484static int ath9k_hw_rfattach(struct ath_hal *ah)
f078f209 485{
f1dc5600
S		 486 bool rfStatus = false;
487 int ecode = 0;
f078f209 488
f1dc5600
S		 489 rfStatus = ath9k_hw_init_rf(ah, &ecode);
490 if (!rfStatus) {
491 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 492 "RF setup failed, status %u\n", ecode);
f1dc5600
S		 493 return ecode;
494 }
f078f209 495
f1dc5600 496 return 0;
f078f209
LR		 497}
498
f1dc5600 499static int ath9k_hw_rf_claim(struct ath_hal *ah)
f078f209 500{
f1dc5600
S		 501 u32 val;
502
503 REG_WRITE(ah, AR_PHY(0), 0x00000007);
504
505 val = ath9k_hw_get_radiorev(ah);
506 switch (val & AR_RADIO_SREV_MAJOR) {
507 case 0:
508 val = AR_RAD5133_SREV_MAJOR;
509 break;
510 case AR_RAD5133_SREV_MAJOR:
511 case AR_RAD5122_SREV_MAJOR:
512 case AR_RAD2133_SREV_MAJOR:
513 case AR_RAD2122_SREV_MAJOR:
514 break;
f078f209 515 default:
f1dc5600 516 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 517 "5G Radio Chip Rev 0x%02X is not "
f1dc5600 518 "supported by this driver\n",
04bd4638 519 ah->ah_analog5GhzRev);
f1dc5600 520 return -EOPNOTSUPP;
f078f209 521 }
f078f209 522
f1dc5600 523 ah->ah_analog5GhzRev = val;
f078f209 524
f1dc5600 525 return 0;
f078f209
LR		 526}
527
ff9b662d 528static int ath9k_hw_init_macaddr(struct ath_hal *ah)
f078f209
LR		 529{
530 u32 sum;
531 int i;
532 u16 eeval;
533 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 534
535 sum = 0;
536 for (i = 0; i < 3; i++) {
f1dc5600 537 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209
LR		 538 sum += eeval;
539 ahp->ah_macaddr[2 * i] = eeval >> 8;
540 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
541 }
542 if (sum == 0 || sum == 0xffff * 3) {
543 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 544 "mac address read failed: %pM\n",
f1dc5600 545 ahp->ah_macaddr);
f078f209
LR		 546 return -EADDRNOTAVAIL;
547 }
548
549 return 0;
550}
551
9f804202
SB		 552static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
553{
554 u32 rxgain_type;
555 struct ath_hal_5416 *ahp = AH5416(ah);
556
557 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
558 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
559
560 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
561 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
562 ar9280Modes_backoff_13db_rxgain_9280_2,
563 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
564 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
565 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
566 ar9280Modes_backoff_23db_rxgain_9280_2,
567 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
568 else
569 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
570 ar9280Modes_original_rxgain_9280_2,
571 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
572 } else
573 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
574 ar9280Modes_original_rxgain_9280_2,
575 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
576}
577
578static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
579{
580 u32 txgain_type;
581 struct ath_hal_5416 *ahp = AH5416(ah);
582
583 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
584 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
585
586 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
587 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
588 ar9280Modes_high_power_tx_gain_9280_2,
589 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
590 else
591 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
592 ar9280Modes_original_tx_gain_9280_2,
593 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
594 } else
595 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
596 ar9280Modes_original_tx_gain_9280_2,
597 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
598}
599
f1dc5600 600static int ath9k_hw_post_attach(struct ath_hal *ah)
f078f209 601{
f1dc5600 602 int ecode;
f078f209 603
f1dc5600
S		 604 if (!ath9k_hw_chip_test(ah)) {
605 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 606 "hardware self-test failed\n");
f1dc5600 607 return -ENODEV;
f078f209 608 }
f078f209 609
f1dc5600
S		 610 ecode = ath9k_hw_rf_claim(ah);
611 if (ecode != 0)
f078f209 612 return ecode;
f078f209 613
f1dc5600
S		 614 ecode = ath9k_hw_eeprom_attach(ah);
615 if (ecode != 0)
616 return ecode;
617 ecode = ath9k_hw_rfattach(ah);
618 if (ecode != 0)
619 return ecode;
f078f209 620
f1dc5600
S		 621 if (!AR_SREV_9100(ah)) {
622 ath9k_hw_ani_setup(ah);
623 ath9k_hw_ani_attach(ah);
f078f209
LR		 624 }
625
f078f209
LR		 626 return 0;
627}
628
f1dc5600
S		 629static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
630 void __iomem *mem, int *status)
f078f209 631{
f1dc5600
S		 632 struct ath_hal_5416 *ahp;
633 struct ath_hal *ah;
634 int ecode;
f6688cd8 635 u32 i, j;
f078f209 636
f1dc5600
S		 637 ahp = ath9k_hw_newstate(devid, sc, mem, status);
638 if (ahp == NULL)
639 return NULL;
f078f209 640
f1dc5600 641 ah = &ahp->ah;
f078f209 642
f1dc5600 643 ath9k_hw_set_defaults(ah);
f078f209 644
f1dc5600
S		 645 if (ah->ah_config.intr_mitigation != 0)
646 ahp->ah_intrMitigation = true;
f078f209 647
f1dc5600 648 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
04bd4638 649 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
f1dc5600
S		 650 ecode = -EIO;
651 goto bad;
652 }
f078f209 653
f1dc5600 654 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
04bd4638 655 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
f1dc5600
S		 656 ecode = -EIO;
657 goto bad;
658 }
f078f209 659
f1dc5600
S		 660 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
661 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
662 ah->ah_config.serialize_regmode =
663 SER_REG_MODE_ON;
f078f209 664 } else {
f1dc5600
S		 665 ah->ah_config.serialize_regmode =
666 SER_REG_MODE_OFF;
f078f209
LR		 667 }
668 }
f078f209 669
f1dc5600 670 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 671 "serialize_regmode is %d\n",
672 ah->ah_config.serialize_regmode);
f078f209 673
f1dc5600
S		 674 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
675 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
676 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
e7594072 677 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
f1dc5600 678 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 679 "Mac Chip Rev 0x%02x.%x is not supported by "
680 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
f1dc5600
S		 681 ecode = -EOPNOTSUPP;
682 goto bad;
683 }
f078f209 684
f1dc5600
S		 685 if (AR_SREV_9100(ah)) {
686 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
687 ahp->ah_suppCals = IQ_MISMATCH_CAL;
688 ah->ah_isPciExpress = false;
689 }
690 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
f078f209 691
f1dc5600
S		 692 if (AR_SREV_9160_10_OR_LATER(ah)) {
693 if (AR_SREV_9280_10_OR_LATER(ah)) {
694 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
695 ahp->ah_adcGainCalData.calData =
696 &adc_gain_cal_single_sample;
697 ahp->ah_adcDcCalData.calData =
698 &adc_dc_cal_single_sample;
699 ahp->ah_adcDcCalInitData.calData =
700 &adc_init_dc_cal;
701 } else {
702 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
703 ahp->ah_adcGainCalData.calData =
704 &adc_gain_cal_multi_sample;
705 ahp->ah_adcDcCalData.calData =
706 &adc_dc_cal_multi_sample;
707 ahp->ah_adcDcCalInitData.calData =
708 &adc_init_dc_cal;
709 }
710 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
711 }
f078f209 712
f1dc5600
S		 713 if (AR_SREV_9160(ah)) {
714 ah->ah_config.enable_ani = 1;
715 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
716 ATH9K_ANI_FIRSTEP_LEVEL);
717 } else {
718 ahp->ah_ani_function = ATH9K_ANI_ALL;
719 if (AR_SREV_9280_10_OR_LATER(ah)) {
720 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
721 }
f078f209 722 }
f078f209 723
f1dc5600 724 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 725 "This Mac Chip Rev 0x%02x.%x is \n",
f1dc5600 726 ah->ah_macVersion, ah->ah_macRev);
f078f209 727
e7594072
SB		 728 if (AR_SREV_9285_12_OR_LATER(ah)) {
729 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
730 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
731 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
732 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
733
734 if (ah->ah_config.pcie_clock_req) {
735 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
736 ar9285PciePhy_clkreq_off_L1_9285_1_2,
737 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
738 } else {
739 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
740 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
741 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
742 2);
743 }
744 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
745 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
746 ARRAY_SIZE(ar9285Modes_9285), 6);
747 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
748 ARRAY_SIZE(ar9285Common_9285), 2);
749
750 if (ah->ah_config.pcie_clock_req) {
751 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
752 ar9285PciePhy_clkreq_off_L1_9285,
753 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
754 } else {
755 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
756 ar9285PciePhy_clkreq_always_on_L1_9285,
757 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
758 }
759 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
f1dc5600
S		 760 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
761 ARRAY_SIZE(ar9280Modes_9280_2), 6);
762 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
763 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 764
f1dc5600
S		 765 if (ah->ah_config.pcie_clock_req) {
766 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
767 ar9280PciePhy_clkreq_off_L1_9280,
768 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
769 } else {
770 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
771 ar9280PciePhy_clkreq_always_on_L1_9280,
772 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
773 }
774 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
775 ar9280Modes_fast_clock_9280_2,
776 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
777 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
778 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
779 ARRAY_SIZE(ar9280Modes_9280), 6);
780 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
781 ARRAY_SIZE(ar9280Common_9280), 2);
782 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
783 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
784 ARRAY_SIZE(ar5416Modes_9160), 6);
785 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
786 ARRAY_SIZE(ar5416Common_9160), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
788 ARRAY_SIZE(ar5416Bank0_9160), 2);
789 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
790 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
791 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
792 ARRAY_SIZE(ar5416Bank1_9160), 2);
793 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
794 ARRAY_SIZE(ar5416Bank2_9160), 2);
795 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
796 ARRAY_SIZE(ar5416Bank3_9160), 3);
797 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
798 ARRAY_SIZE(ar5416Bank6_9160), 3);
799 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
800 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
801 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
802 ARRAY_SIZE(ar5416Bank7_9160), 2);
803 if (AR_SREV_9160_11(ah)) {
804 INIT_INI_ARRAY(&ahp->ah_iniAddac,
805 ar5416Addac_91601_1,
806 ARRAY_SIZE(ar5416Addac_91601_1), 2);
807 } else {
808 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
809 ARRAY_SIZE(ar5416Addac_9160), 2);
810 }
811 } else if (AR_SREV_9100_OR_LATER(ah)) {
812 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
813 ARRAY_SIZE(ar5416Modes_9100), 6);
814 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
815 ARRAY_SIZE(ar5416Common_9100), 2);
816 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
817 ARRAY_SIZE(ar5416Bank0_9100), 2);
818 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
819 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
820 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
821 ARRAY_SIZE(ar5416Bank1_9100), 2);
822 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
823 ARRAY_SIZE(ar5416Bank2_9100), 2);
824 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
825 ARRAY_SIZE(ar5416Bank3_9100), 3);
826 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
827 ARRAY_SIZE(ar5416Bank6_9100), 3);
828 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
829 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
830 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
831 ARRAY_SIZE(ar5416Bank7_9100), 2);
832 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
833 ARRAY_SIZE(ar5416Addac_9100), 2);
834 } else {
835 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
836 ARRAY_SIZE(ar5416Modes), 6);
837 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
838 ARRAY_SIZE(ar5416Common), 2);
839 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
840 ARRAY_SIZE(ar5416Bank0), 2);
841 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
842 ARRAY_SIZE(ar5416BB_RfGain), 3);
843 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
844 ARRAY_SIZE(ar5416Bank1), 2);
845 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
846 ARRAY_SIZE(ar5416Bank2), 2);
847 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
848 ARRAY_SIZE(ar5416Bank3), 3);
849 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
850 ARRAY_SIZE(ar5416Bank6), 3);
851 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
852 ARRAY_SIZE(ar5416Bank6TPC), 3);
853 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
854 ARRAY_SIZE(ar5416Bank7), 2);
855 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
856 ARRAY_SIZE(ar5416Addac), 2);
f078f209 857 }
f078f209 858
f1dc5600
S		 859 if (ah->ah_isPciExpress)
860 ath9k_hw_configpcipowersave(ah, 0);
861 else
862 ath9k_hw_disablepcie(ah);
f078f209 863
f1dc5600
S		 864 ecode = ath9k_hw_post_attach(ah);
865 if (ecode != 0)
866 goto bad;
f078f209 867
9f804202 868 /* rxgain table */
e7594072 869 if (AR_SREV_9280_20(ah))
9f804202
SB		 870 ath9k_hw_init_rxgain_ini(ah);
871
872 /* txgain table */
e7594072 873 if (AR_SREV_9280_20(ah))
9f804202
SB		 874 ath9k_hw_init_txgain_ini(ah);
875
f1dc5600
S		 876 if (ah->ah_devid == AR9280_DEVID_PCI) {
877 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
878 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
f078f209 879
f1dc5600
S		 880 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
881 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
f078f209 882
f1dc5600 883 INI_RA(&ahp->ah_iniModes, i, j) =
e7594072
SB		 884 ath9k_hw_ini_fixup(ah,
885 &ahp->ah_eeprom.def,
f1dc5600
S		 886 reg, val);
887 }
f078f209 888 }
f1dc5600 889 }
f6688cd8 890
f1dc5600
S		 891 if (!ath9k_hw_fill_cap_info(ah)) {
892 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 893 "failed ath9k_hw_fill_cap_info\n");
f1dc5600
S		 894 ecode = -EINVAL;
895 goto bad;
f078f209
LR		 896 }
897
f1dc5600
S		 898 ecode = ath9k_hw_init_macaddr(ah);
899 if (ecode != 0) {
f078f209 900 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 901 "failed initializing mac address\n");
f1dc5600 902 goto bad;
f078f209
LR		 903 }
904
f1dc5600
S		 905 if (AR_SREV_9285(ah))
906 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
907 else
908 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 909
f1dc5600 910 ath9k_init_nfcal_hist_buffer(ah);
f078f209 911
f1dc5600
S		 912 return ah;
913bad:
914 if (ahp)
915 ath9k_hw_detach((struct ath_hal *) ahp);
916 if (status)
917 *status = ecode;
f078f209 918
f1dc5600 919 return NULL;
f078f209
LR		 920}
921
f1dc5600
S		 922static void ath9k_hw_init_bb(struct ath_hal *ah,
923 struct ath9k_channel *chan)
f078f209 924{
f1dc5600 925 u32 synthDelay;
f078f209 926
f1dc5600 927 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 928 if (IS_CHAN_B(chan))
f1dc5600
S		 929 synthDelay = (4 * synthDelay) / 22;
930 else
931 synthDelay /= 10;
f078f209 932
f1dc5600 933 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 934
f1dc5600 935 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 936}
937
f1dc5600 938static void ath9k_hw_init_qos(struct ath_hal *ah)
f078f209 939{
f1dc5600
S		 940 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
941 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 942
f1dc5600
S		 943 REG_WRITE(ah, AR_QOS_NO_ACK,
944 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
945 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
946 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
947
948 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
949 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
950 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
951 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
952 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 953}
954
f1dc5600
S		 955static void ath9k_hw_init_pll(struct ath_hal *ah,
956 struct ath9k_channel *chan)
f078f209 957{
f1dc5600 958 u32 pll;
f078f209 959
f1dc5600
S		 960 if (AR_SREV_9100(ah)) {
961 if (chan && IS_CHAN_5GHZ(chan))
962 pll = 0x1450;
f078f209 963 else
f1dc5600
S		 964 pll = 0x1458;
965 } else {
966 if (AR_SREV_9280_10_OR_LATER(ah)) {
967 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 968
f1dc5600
S		 969 if (chan && IS_CHAN_HALF_RATE(chan))
970 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
971 else if (chan && IS_CHAN_QUARTER_RATE(chan))
972 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 973
f1dc5600
S		 974 if (chan && IS_CHAN_5GHZ(chan)) {
975 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 976
f078f209 977
f1dc5600
S		 978 if (AR_SREV_9280_20(ah)) {
979 if (((chan->channel % 20) == 0)
980 || ((chan->channel % 10) == 0))
981 pll = 0x2850;
982 else
983 pll = 0x142c;
984 }
985 } else {
986 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
987 }
f078f209 988
f1dc5600 989 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 990
f1dc5600 991 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 992
f1dc5600
S		 993 if (chan && IS_CHAN_HALF_RATE(chan))
994 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
995 else if (chan && IS_CHAN_QUARTER_RATE(chan))
996 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 997
f1dc5600
S		 998 if (chan && IS_CHAN_5GHZ(chan))
999 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1000 else
1001 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1002 } else {
1003 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1004
f1dc5600
S		 1005 if (chan && IS_CHAN_HALF_RATE(chan))
1006 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1007 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1008 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1009
f1dc5600
S		 1010 if (chan && IS_CHAN_5GHZ(chan))
1011 pll |= SM(0xa, AR_RTC_PLL_DIV);
1012 else
1013 pll |= SM(0xb, AR_RTC_PLL_DIV);
1014 }
1015 }
d03a66c1 1016 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1017
f1dc5600
S		 1018 udelay(RTC_PLL_SETTLE_DELAY);
1019
1020 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1021}
1022
ff9b662d 1023static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
f078f209
LR		 1024{
1025 struct ath_hal_5416 *ahp = AH5416(ah);
1026 int rx_chainmask, tx_chainmask;
1027
1028 rx_chainmask = ahp->ah_rxchainmask;
1029 tx_chainmask = ahp->ah_txchainmask;
1030
1031 switch (rx_chainmask) {
1032 case 0x5:
1033 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1034 AR_PHY_SWAP_ALT_CHAIN);
1035 case 0x3:
1036 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1037 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1038 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1039 break;
1040 }
1041 case 0x1:
1042 case 0x2:
f078f209
LR		 1043 case 0x7:
1044 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1045 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1046 break;
1047 default:
1048 break;
1049 }
1050
1051 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1052 if (tx_chainmask == 0x5) {
1053 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1054 AR_PHY_SWAP_ALT_CHAIN);
1055 }
1056 if (AR_SREV_9100(ah))
1057 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1058 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1059}
1060
d97809db
CM		 1061static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1062 enum nl80211_iftype opmode)
f078f209 1063{
f078f209 1064 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1065
f1dc5600
S		 1066 ahp->ah_maskReg = AR_IMR_TXERR |
1067 AR_IMR_TXURN |
1068 AR_IMR_RXERR |
1069 AR_IMR_RXORN |
1070 AR_IMR_BCNMISC;
f078f209 1071
f1dc5600
S		 1072 if (ahp->ah_intrMitigation)
1073 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1074 else
f1dc5600 1075 ahp->ah_maskReg |= AR_IMR_RXOK;
f078f209 1076
f1dc5600 1077 ahp->ah_maskReg |= AR_IMR_TXOK;
f078f209 1078
d97809db 1079 if (opmode == NL80211_IFTYPE_AP)
f1dc5600 1080 ahp->ah_maskReg |= AR_IMR_MIB;
f078f209 1081
f1dc5600
S		 1082 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1083 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1084
f1dc5600
S		 1085 if (!AR_SREV_9100(ah)) {
1086 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1087 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1088 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1089 }
f078f209
LR		 1090}
1091
1092static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1093{
1094 struct ath_hal_5416 *ahp = AH5416(ah);
1095
1096 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1097 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
f078f209
LR		 1098 ahp->ah_acktimeout = (u32) -1;
1099 return false;
1100 } else {
1101 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1103 ahp->ah_acktimeout = us;
1104 return true;
1105 }
1106}
1107
1108static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1109{
1110 struct ath_hal_5416 *ahp = AH5416(ah);
1111
1112 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1113 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
f078f209
LR		 1114 ahp->ah_ctstimeout = (u32) -1;
1115 return false;
1116 } else {
1117 REG_RMW_FIELD(ah, AR_TIME_OUT,
1118 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1119 ahp->ah_ctstimeout = us;
1120 return true;
1121 }
1122}
f1dc5600
S		 1123
1124static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
f078f209
LR		 1125{
1126 struct ath_hal_5416 *ahp = AH5416(ah);
1127
1128 if (tu > 0xFFFF) {
1129 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1130 "bad global tx timeout %u\n", tu);
f078f209
LR		 1131 ahp->ah_globaltxtimeout = (u32) -1;
1132 return false;
1133 } else {
1134 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1135 ahp->ah_globaltxtimeout = tu;
1136 return true;
1137 }
1138}
1139
f1dc5600 1140static void ath9k_hw_init_user_settings(struct ath_hal *ah)
f078f209
LR		 1141{
1142 struct ath_hal_5416 *ahp = AH5416(ah);
1143
04bd4638
S		 1144 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1145 ahp->ah_miscMode);
f1dc5600
S		 1146
1147 if (ahp->ah_miscMode != 0)
1148 REG_WRITE(ah, AR_PCU_MISC,
1149 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1150 if (ahp->ah_slottime != (u32) -1)
1151 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1152 if (ahp->ah_acktimeout != (u32) -1)
1153 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1154 if (ahp->ah_ctstimeout != (u32) -1)
1155 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1156 if (ahp->ah_globaltxtimeout != (u32) -1)
1157 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1158}
1159
1160const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1161{
1162 return vendorid == ATHEROS_VENDOR_ID ?
1163 ath9k_hw_devname(devid) : NULL;
1164}
1165
1166void ath9k_hw_detach(struct ath_hal *ah)
1167{
1168 if (!AR_SREV_9100(ah))
1169 ath9k_hw_ani_detach(ah);
1170
1171 ath9k_hw_rfdetach(ah);
1172 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1173 kfree(ah);
1174}
1175
1176struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1177 void __iomem *mem, int *error)
1178{
1179 struct ath_hal *ah = NULL;
1180
1181 switch (devid) {
1182 case AR5416_DEVID_PCI:
1183 case AR5416_DEVID_PCIE:
0c1aa495 1184 case AR5416_AR9100_DEVID:
f1dc5600
S		 1185 case AR9160_DEVID_PCI:
1186 case AR9280_DEVID_PCI:
1187 case AR9280_DEVID_PCIE:
e7594072 1188 case AR9285_DEVID_PCIE:
f1dc5600
S		 1189 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1190 break;
1191 default:
f1dc5600
S		 1192 *error = -ENXIO;
1193 break;
f078f209 1194 }
f1dc5600
S		 1195
1196 return ah;
1197}
1198
1199/*******/
1200/* INI */
1201/*******/
1202
1203static void ath9k_hw_override_ini(struct ath_hal *ah,
1204 struct ath9k_channel *chan)
1205{
8aa15e15
SB		 1206 /*
1207 * Set the RX_ABORT and RX_DIS and clear if off only after
1208 * RXE is set for MAC. This prevents frames with corrupted
1209 * descriptor status.
1210 */
1211 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1212
1213
f1dc5600
S		 1214 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1215 AR_SREV_9280_10_OR_LATER(ah))
1216 return;
1217
1218 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1219}
1220
e7594072
SB		 1221static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1222 struct ar5416_eeprom_def *pEepData,
f1dc5600 1223 u32 reg, u32 value)
f078f209 1224{
f1dc5600 1225 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1226
f1dc5600
S		 1227 switch (ah->ah_devid) {
1228 case AR9280_DEVID_PCI:
1229 if (reg == 0x7894) {
1230 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1231 "ini VAL: %x EEPROM: %x\n", value,
1232 (pBase->version & 0xff));
1233
1234 if ((pBase->version & 0xff) > 0x0a) {
1235 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1236 "PWDCLKIND: %d\n",
1237 pBase->pwdclkind);
1238 value &= ~AR_AN_TOP2_PWDCLKIND;
1239 value |= AR_AN_TOP2_PWDCLKIND &
1240 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1241 } else {
1242 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1243 "PWDCLKIND Earlier Rev\n");
1244 }
1245
1246 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1247 "final ini VAL: %x\n", value);
1248 }
1249 break;
1250 }
1251
1252 return value;
f078f209
LR		 1253}
1254
e7594072
SB		 1255static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1256 struct ar5416_eeprom_def *pEepData,
1257 u32 reg, u32 value)
1258{
1259 struct ath_hal_5416 *ahp = AH5416(ah);
1260
1261 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1262 return value;
1263 else
1264 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1265}
1266
f1dc5600
S		 1267static int ath9k_hw_process_ini(struct ath_hal *ah,
1268 struct ath9k_channel *chan,
1269 enum ath9k_ht_macmode macmode)
f078f209
LR		 1270{
1271 int i, regWrites = 0;
1272 struct ath_hal_5416 *ahp = AH5416(ah);
1273 u32 modesIndex, freqIndex;
1274 int status;
1275
1276 switch (chan->chanmode) {
1277 case CHANNEL_A:
1278 case CHANNEL_A_HT20:
1279 modesIndex = 1;
1280 freqIndex = 1;
1281 break;
1282 case CHANNEL_A_HT40PLUS:
1283 case CHANNEL_A_HT40MINUS:
1284 modesIndex = 2;
1285 freqIndex = 1;
1286 break;
1287 case CHANNEL_G:
1288 case CHANNEL_G_HT20:
1289 case CHANNEL_B:
1290 modesIndex = 4;
1291 freqIndex = 2;
1292 break;
1293 case CHANNEL_G_HT40PLUS:
1294 case CHANNEL_G_HT40MINUS:
1295 modesIndex = 3;
1296 freqIndex = 2;
1297 break;
1298
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1304
1305 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1306
1307 ath9k_hw_set_addac(ah, chan);
1308
1309 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1310 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1311 } else {
1312 struct ar5416IniArray temp;
1313 u32 addacSize =
1314 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1315 ahp->ah_iniAddac.ia_columns;
1316
1317 memcpy(ahp->ah_addac5416_21,
1318 ahp->ah_iniAddac.ia_array, addacSize);
1319
f1dc5600 1320 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
f078f209
LR		 1321
1322 temp.ia_array = ahp->ah_addac5416_21;
1323 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1324 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1325 REG_WRITE_ARRAY(&temp, 1, regWrites);
1326 }
f1dc5600 1327
f078f209
LR		 1328 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1329
1330 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1331 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1332 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1333
f078f209
LR		 1334 REG_WRITE(ah, reg, val);
1335
1336 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1337 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1338 udelay(100);
1339 }
1340
1341 DO_DELAY(regWrites);
1342 }
1343
e7594072 1344 if (AR_SREV_9280(ah))
9f804202
SB		 1345 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1346
e7594072 1347 if (AR_SREV_9280(ah))
9f804202
SB		 1348 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1349
f078f209
LR		 1350 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1351 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1352 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1353
1354 REG_WRITE(ah, reg, val);
1355
1356 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1357 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1358 udelay(100);
1359 }
1360
1361 DO_DELAY(regWrites);
1362 }
1363
1364 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1365
1366 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1367 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1368 regWrites);
1369 }
1370
1371 ath9k_hw_override_ini(ah, chan);
1372 ath9k_hw_set_regs(ah, chan, macmode);
1373 ath9k_hw_init_chain_masks(ah);
1374
f1dc5600 1375 status = ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1376 ath9k_regd_get_ctl(ah, chan),
1377 ath9k_regd_get_antenna_allowed(ah,
1378 chan),
1379 chan->maxRegTxPower * 2,
1380 min((u32) MAX_RATE_POWER,
1381 (u32) ah->ah_powerLimit));
1382 if (status != 0) {
1383 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 1384 "error init'ing transmit power\n");
f078f209
LR		 1385 return -EIO;
1386 }
1387
1388 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1389 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 1390 "ar5416SetRfRegs failed\n");
f078f209
LR		 1391 return -EIO;
1392 }
1393
1394 return 0;
1395}
1396
f1dc5600
S		 1397/****************************************/
1398/* Reset and Channel Switching Routines */
1399/****************************************/
1400
1401static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1402{
f1dc5600
S		 1403 u32 rfMode = 0;
1404
1405 if (chan == NULL)
1406 return;
1407
1408 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1409 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1410
1411 if (!AR_SREV_9280_10_OR_LATER(ah))
1412 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1413 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1414
1415 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1416 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1417
1418 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1419}
1420
1421static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1422{
1423 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1424}
1425
1426static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1427{
1428 u32 regval;
1429
1430 regval = REG_READ(ah, AR_AHB_MODE);
1431 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1432
1433 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1434 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1435
1436 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1437
1438 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1439 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1440
1441 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1442
1443 if (AR_SREV_9285(ah)) {
1444 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1445 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1446 } else {
1447 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1448 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1449 }
1450}
1451
1452static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1453{
1454 u32 val;
1455
1456 val = REG_READ(ah, AR_STA_ID1);
1457 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1458 switch (opmode) {
d97809db 1459 case NL80211_IFTYPE_AP:
f1dc5600
S		 1460 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1461 | AR_STA_ID1_KSRCH_MODE);
1462 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1463 break;
d97809db 1464 case NL80211_IFTYPE_ADHOC:
f1dc5600
S		 1465 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1466 | AR_STA_ID1_KSRCH_MODE);
1467 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1468 break;
d97809db
CM		 1469 case NL80211_IFTYPE_STATION:
1470 case NL80211_IFTYPE_MONITOR:
f1dc5600 1471 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1472 break;
f1dc5600
S		 1473 }
1474}
1475
1476static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1477 u32 coef_scaled,
1478 u32 *coef_mantissa,
1479 u32 *coef_exponent)
1480{
1481 u32 coef_exp, coef_man;
1482
1483 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1484 if ((coef_scaled >> coef_exp) & 0x1)
1485 break;
1486
1487 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1488
1489 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1490
1491 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1492 *coef_exponent = coef_exp - 16;
1493}
1494
1495static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1496 struct ath9k_channel *chan)
1497{
1498 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1499 u32 clockMhzScaled = 0x64000000;
1500 struct chan_centers centers;
1501
1502 if (IS_CHAN_HALF_RATE(chan))
1503 clockMhzScaled = clockMhzScaled >> 1;
1504 else if (IS_CHAN_QUARTER_RATE(chan))
1505 clockMhzScaled = clockMhzScaled >> 2;
1506
1507 ath9k_hw_get_channel_centers(ah, chan, &centers);
1508 coef_scaled = clockMhzScaled / centers.synth_center;
1509
1510 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1511 &ds_coef_exp);
1512
1513 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1514 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1515 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1516 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1517
1518 coef_scaled = (9 * coef_scaled) / 10;
1519
1520 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1521 &ds_coef_exp);
1522
1523 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1524 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1525 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1526 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1527}
1528
1529static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1530{
1531 u32 rst_flags;
1532 u32 tmpReg;
1533
1534 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1535 AR_RTC_FORCE_WAKE_ON_INT);
1536
1537 if (AR_SREV_9100(ah)) {
1538 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1539 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1540 } else {
1541 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1542 if (tmpReg &
1543 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1544 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1545 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1546 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1547 } else {
1548 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1549 }
1550
1551 rst_flags = AR_RTC_RC_MAC_WARM;
1552 if (type == ATH9K_RESET_COLD)
1553 rst_flags |= AR_RTC_RC_MAC_COLD;
1554 }
1555
d03a66c1 1556 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1557 udelay(50);
1558
d03a66c1
GJ		 1559 REG_WRITE(ah, AR_RTC_RC, 0);
1560 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
f1dc5600 1561 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1562 "RTC stuck in MAC reset\n");
f1dc5600
S		 1563 return false;
1564 }
1565
1566 if (!AR_SREV_9100(ah))
1567 REG_WRITE(ah, AR_RC, 0);
1568
1569 ath9k_hw_init_pll(ah, NULL);
1570
1571 if (AR_SREV_9100(ah))
1572 udelay(50);
1573
1574 return true;
1575}
1576
1577static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1578{
1579 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1580 AR_RTC_FORCE_WAKE_ON_INT);
1581
d03a66c1
GJ		 1582 REG_WRITE(ah, AR_RTC_RESET, 0);
1583 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1584
1585 if (!ath9k_hw_wait(ah,
1586 AR_RTC_STATUS,
1587 AR_RTC_STATUS_M,
1588 AR_RTC_STATUS_ON)) {
04bd4638 1589 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1590 return false;
f078f209
LR		 1591 }
1592
f1dc5600
S		 1593 ath9k_hw_read_revisions(ah);
1594
1595 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1596}
1597
1598static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1599{
1600 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1601 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1602
1603 switch (type) {
1604 case ATH9K_RESET_POWER_ON:
1605 return ath9k_hw_set_reset_power_on(ah);
1606 break;
1607 case ATH9K_RESET_WARM:
1608 case ATH9K_RESET_COLD:
1609 return ath9k_hw_set_reset(ah, type);
1610 break;
1611 default:
1612 return false;
1613 }
f078f209
LR		 1614}
1615
f1dc5600
S		 1616static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1617 enum ath9k_ht_macmode macmode)
f078f209 1618{
f1dc5600 1619 u32 phymode;
e7594072 1620 u32 enableDacFifo = 0;
f078f209 1621 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1622
e7594072
SB		 1623 if (AR_SREV_9285_10_OR_LATER(ah))
1624 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1625 AR_PHY_FC_ENABLE_DAC_FIFO);
1626
f1dc5600 1627 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1628 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1629
1630 if (IS_CHAN_HT40(chan)) {
1631 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1632
f1dc5600
S		 1633 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1634 (chan->chanmode == CHANNEL_G_HT40PLUS))
1635 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1636
f1dc5600
S		 1637 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1638 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1639 }
f1dc5600
S		 1640 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1641
1642 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1643
f1dc5600
S		 1644 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1645 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1646}
1647
f1dc5600
S		 1648static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1649 struct ath9k_channel *chan)
f078f209
LR		 1650{
1651 struct ath_hal_5416 *ahp = AH5416(ah);
1652
f1dc5600
S		 1653 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1654 return false;
f078f209 1655
f1dc5600
S		 1656 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1657 return false;
f078f209 1658
f1dc5600 1659 ahp->ah_chipFullSleep = false;
f078f209 1660
f1dc5600 1661 ath9k_hw_init_pll(ah, chan);
f078f209 1662
f1dc5600 1663 ath9k_hw_set_rfmode(ah, chan);
f078f209 1664
f1dc5600 1665 return true;
f078f209
LR		 1666}
1667
f1dc5600
S		 1668static bool ath9k_hw_channel_change(struct ath_hal *ah,
1669 struct ath9k_channel *chan,
1670 enum ath9k_ht_macmode macmode)
f078f209
LR		 1671{
1672 u32 synthDelay, qnum;
f078f209
LR		 1673
1674 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1675 if (ath9k_hw_numtxpending(ah, qnum)) {
1676 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1677 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1678 return false;
1679 }
1680 }
1681
1682 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1683 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1684 AR_PHY_RFBUS_GRANT_EN)) {
04bd4638
S		 1685 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1686 "Could not kill baseband RX\n");
f078f209
LR		 1687 return false;
1688 }
1689
1690 ath9k_hw_set_regs(ah, chan, macmode);
1691
1692 if (AR_SREV_9280_10_OR_LATER(ah)) {
1693 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1694 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1695 "failed to set channel\n");
f078f209
LR		 1696 return false;
1697 }
1698 } else {
1699 if (!(ath9k_hw_set_channel(ah, chan))) {
1700 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1701 "failed to set channel\n");
f078f209
LR		 1702 return false;
1703 }
1704 }
1705
f1dc5600 1706 if (ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1707 ath9k_regd_get_ctl(ah, chan),
1708 ath9k_regd_get_antenna_allowed(ah, chan),
1709 chan->maxRegTxPower * 2,
1710 min((u32) MAX_RATE_POWER,
1711 (u32) ah->ah_powerLimit)) != 0) {
1712 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 1713 "error init'ing transmit power\n");
f078f209
LR		 1714 return false;
1715 }
1716
1717 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1718 if (IS_CHAN_B(chan))
f078f209
LR		 1719 synthDelay = (4 * synthDelay) / 22;
1720 else
1721 synthDelay /= 10;
1722
1723 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1724
1725 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1726
f1dc5600
S		 1727 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1728 ath9k_hw_set_delta_slope(ah, chan);
1729
1730 if (AR_SREV_9280_10_OR_LATER(ah))
1731 ath9k_hw_9280_spur_mitigate(ah, chan);
1732 else
1733 ath9k_hw_spur_mitigate(ah, chan);
1734
1735 if (!chan->oneTimeCalsDone)
1736 chan->oneTimeCalsDone = true;
1737
1738 return true;
1739}
1740
1741static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1742{
1743 int bb_spur = AR_NO_SPUR;
1744 int freq;
1745 int bin, cur_bin;
1746 int bb_spur_off, spur_subchannel_sd;
1747 int spur_freq_sd;
1748 int spur_delta_phase;
1749 int denominator;
1750 int upper, lower, cur_vit_mask;
1751 int tmp, newVal;
1752 int i;
1753 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1754 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1755 };
1756 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1757 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1758 };
1759 int inc[4] = { 0, 100, 0, 0 };
1760 struct chan_centers centers;
1761
1762 int8_t mask_m[123];
1763 int8_t mask_p[123];
1764 int8_t mask_amt;
1765 int tmp_mask;
1766 int cur_bb_spur;
1767 bool is2GHz = IS_CHAN_2GHZ(chan);
1768
1769 memset(&mask_m, 0, sizeof(int8_t) * 123);
1770 memset(&mask_p, 0, sizeof(int8_t) * 123);
1771
1772 ath9k_hw_get_channel_centers(ah, chan, &centers);
1773 freq = centers.synth_center;
1774
1775 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1776 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1777 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1778
1779 if (is2GHz)
1780 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1781 else
1782 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1783
1784 if (AR_NO_SPUR == cur_bb_spur)
1785 break;
1786 cur_bb_spur = cur_bb_spur - freq;
1787
1788 if (IS_CHAN_HT40(chan)) {
1789 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1790 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1791 bb_spur = cur_bb_spur;
1792 break;
1793 }
1794 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1795 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1796 bb_spur = cur_bb_spur;
1797 break;
1798 }
1799 }
1800
1801 if (AR_NO_SPUR == bb_spur) {
1802 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1803 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1804 return;
1805 } else {
1806 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1807 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1808 }
1809
1810 bin = bb_spur * 320;
1811
1812 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1813
1814 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1815 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1816 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1817 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1818 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1819
1820 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1821 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1822 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1823 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1824 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1825 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1826
1827 if (IS_CHAN_HT40(chan)) {
1828 if (bb_spur < 0) {
1829 spur_subchannel_sd = 1;
1830 bb_spur_off = bb_spur + 10;
1831 } else {
1832 spur_subchannel_sd = 0;
1833 bb_spur_off = bb_spur - 10;
1834 }
1835 } else {
1836 spur_subchannel_sd = 0;
1837 bb_spur_off = bb_spur;
1838 }
1839
1840 if (IS_CHAN_HT40(chan))
1841 spur_delta_phase =
1842 ((bb_spur * 262144) /
1843 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1844 else
1845 spur_delta_phase =
1846 ((bb_spur * 524288) /
1847 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1848
1849 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1850 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1851
1852 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1853 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1854 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1855 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1856
1857 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1858 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1859
1860 cur_bin = -6000;
1861 upper = bin + 100;
1862 lower = bin - 100;
1863
1864 for (i = 0; i < 4; i++) {
1865 int pilot_mask = 0;
1866 int chan_mask = 0;
1867 int bp = 0;
1868 for (bp = 0; bp < 30; bp++) {
1869 if ((cur_bin > lower) && (cur_bin < upper)) {
1870 pilot_mask = pilot_mask | 0x1 << bp;
1871 chan_mask = chan_mask | 0x1 << bp;
1872 }
1873 cur_bin += 100;
1874 }
1875 cur_bin += inc[i];
1876 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1877 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1878 }
1879
1880 cur_vit_mask = 6100;
1881 upper = bin + 120;
1882 lower = bin - 120;
1883
1884 for (i = 0; i < 123; i++) {
1885 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1886
1887 /* workaround for gcc bug #37014 */
a085ff71 1888 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 1889
a085ff71 1890 if (tmp_v < 75)
f1dc5600
S		 1891 mask_amt = 1;
1892 else
1893 mask_amt = 0;
1894 if (cur_vit_mask < 0)
1895 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1896 else
1897 mask_p[cur_vit_mask / 100] = mask_amt;
1898 }
1899 cur_vit_mask -= 100;
1900 }
1901
1902 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1903 | (mask_m[48] << 26) | (mask_m[49] << 24)
1904 | (mask_m[50] << 22) | (mask_m[51] << 20)
1905 | (mask_m[52] << 18) | (mask_m[53] << 16)
1906 | (mask_m[54] << 14) | (mask_m[55] << 12)
1907 | (mask_m[56] << 10) | (mask_m[57] << 8)
1908 | (mask_m[58] << 6) | (mask_m[59] << 4)
1909 | (mask_m[60] << 2) | (mask_m[61] << 0);
1910 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1911 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1912
1913 tmp_mask = (mask_m[31] << 28)
1914 | (mask_m[32] << 26) | (mask_m[33] << 24)
1915 | (mask_m[34] << 22) | (mask_m[35] << 20)
1916 | (mask_m[36] << 18) | (mask_m[37] << 16)
1917 | (mask_m[48] << 14) | (mask_m[39] << 12)
1918 | (mask_m[40] << 10) | (mask_m[41] << 8)
1919 | (mask_m[42] << 6) | (mask_m[43] << 4)
1920 | (mask_m[44] << 2) | (mask_m[45] << 0);
1921 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1922 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1923
1924 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1925 | (mask_m[18] << 26) | (mask_m[18] << 24)
1926 | (mask_m[20] << 22) | (mask_m[20] << 20)
1927 | (mask_m[22] << 18) | (mask_m[22] << 16)
1928 | (mask_m[24] << 14) | (mask_m[24] << 12)
1929 | (mask_m[25] << 10) | (mask_m[26] << 8)
1930 | (mask_m[27] << 6) | (mask_m[28] << 4)
1931 | (mask_m[29] << 2) | (mask_m[30] << 0);
1932 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1933 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1934
1935 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1936 | (mask_m[2] << 26) | (mask_m[3] << 24)
1937 | (mask_m[4] << 22) | (mask_m[5] << 20)
1938 | (mask_m[6] << 18) | (mask_m[7] << 16)
1939 | (mask_m[8] << 14) | (mask_m[9] << 12)
1940 | (mask_m[10] << 10) | (mask_m[11] << 8)
1941 | (mask_m[12] << 6) | (mask_m[13] << 4)
1942 | (mask_m[14] << 2) | (mask_m[15] << 0);
1943 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1944 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1945
1946 tmp_mask = (mask_p[15] << 28)
1947 | (mask_p[14] << 26) | (mask_p[13] << 24)
1948 | (mask_p[12] << 22) | (mask_p[11] << 20)
1949 | (mask_p[10] << 18) | (mask_p[9] << 16)
1950 | (mask_p[8] << 14) | (mask_p[7] << 12)
1951 | (mask_p[6] << 10) | (mask_p[5] << 8)
1952 | (mask_p[4] << 6) | (mask_p[3] << 4)
1953 | (mask_p[2] << 2) | (mask_p[1] << 0);
1954 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1955 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 1956
f1dc5600
S		 1957 tmp_mask = (mask_p[30] << 28)
1958 | (mask_p[29] << 26) | (mask_p[28] << 24)
1959 | (mask_p[27] << 22) | (mask_p[26] << 20)
1960 | (mask_p[25] << 18) | (mask_p[24] << 16)
1961 | (mask_p[23] << 14) | (mask_p[22] << 12)
1962 | (mask_p[21] << 10) | (mask_p[20] << 8)
1963 | (mask_p[19] << 6) | (mask_p[18] << 4)
1964 | (mask_p[17] << 2) | (mask_p[16] << 0);
1965 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1966 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 1967
f1dc5600
S		 1968 tmp_mask = (mask_p[45] << 28)
1969 | (mask_p[44] << 26) | (mask_p[43] << 24)
1970 | (mask_p[42] << 22) | (mask_p[41] << 20)
1971 | (mask_p[40] << 18) | (mask_p[39] << 16)
1972 | (mask_p[38] << 14) | (mask_p[37] << 12)
1973 | (mask_p[36] << 10) | (mask_p[35] << 8)
1974 | (mask_p[34] << 6) | (mask_p[33] << 4)
1975 | (mask_p[32] << 2) | (mask_p[31] << 0);
1976 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1977 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 1978
f1dc5600
S		 1979 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1980 | (mask_p[59] << 26) | (mask_p[58] << 24)
1981 | (mask_p[57] << 22) | (mask_p[56] << 20)
1982 | (mask_p[55] << 18) | (mask_p[54] << 16)
1983 | (mask_p[53] << 14) | (mask_p[52] << 12)
1984 | (mask_p[51] << 10) | (mask_p[50] << 8)
1985 | (mask_p[49] << 6) | (mask_p[48] << 4)
1986 | (mask_p[47] << 2) | (mask_p[46] << 0);
1987 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1988 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 1989}
1990
f1dc5600 1991static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1992{
f1dc5600
S		 1993 int bb_spur = AR_NO_SPUR;
1994 int bin, cur_bin;
1995 int spur_freq_sd;
1996 int spur_delta_phase;
1997 int denominator;
1998 int upper, lower, cur_vit_mask;
1999 int tmp, new;
2000 int i;
2001 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2002 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2003 };
2004 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2005 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2006 };
2007 int inc[4] = { 0, 100, 0, 0 };
f078f209 2008
f1dc5600
S		 2009 int8_t mask_m[123];
2010 int8_t mask_p[123];
2011 int8_t mask_amt;
2012 int tmp_mask;
2013 int cur_bb_spur;
2014 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2015
f1dc5600
S		 2016 memset(&mask_m, 0, sizeof(int8_t) * 123);
2017 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2018
f1dc5600
S		 2019 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2020 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2021 if (AR_NO_SPUR == cur_bb_spur)
2022 break;
2023 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2024 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2025 bb_spur = cur_bb_spur;
2026 break;
2027 }
2028 }
f078f209 2029
f1dc5600
S		 2030 if (AR_NO_SPUR == bb_spur)
2031 return;
f078f209 2032
f1dc5600 2033 bin = bb_spur * 32;
f078f209 2034
f1dc5600
S		 2035 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2036 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2037 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2038 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2039 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2040
f1dc5600 2041 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2042
f1dc5600
S		 2043 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2044 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2045 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2046 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2047 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2048 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2049
f1dc5600
S		 2050 spur_delta_phase = ((bb_spur * 524288) / 100) &
2051 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2052
f1dc5600
S		 2053 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2054 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2055
f1dc5600
S		 2056 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2057 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2058 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2059 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2060
f1dc5600
S		 2061 cur_bin = -6000;
2062 upper = bin + 100;
2063 lower = bin - 100;
f078f209 2064
f1dc5600
S		 2065 for (i = 0; i < 4; i++) {
2066 int pilot_mask = 0;
2067 int chan_mask = 0;
2068 int bp = 0;
2069 for (bp = 0; bp < 30; bp++) {
2070 if ((cur_bin > lower) && (cur_bin < upper)) {
2071 pilot_mask = pilot_mask | 0x1 << bp;
2072 chan_mask = chan_mask | 0x1 << bp;
2073 }
2074 cur_bin += 100;
2075 }
2076 cur_bin += inc[i];
2077 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2078 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2079 }
f078f209 2080
f1dc5600
S		 2081 cur_vit_mask = 6100;
2082 upper = bin + 120;
2083 lower = bin - 120;
f078f209 2084
f1dc5600
S		 2085 for (i = 0; i < 123; i++) {
2086 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2087
f1dc5600 2088 /* workaround for gcc bug #37014 */
a085ff71 2089 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2090
a085ff71 2091 if (tmp_v < 75)
f1dc5600
S		 2092 mask_amt = 1;
2093 else
2094 mask_amt = 0;
2095 if (cur_vit_mask < 0)
2096 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2097 else
2098 mask_p[cur_vit_mask / 100] = mask_amt;
2099 }
2100 cur_vit_mask -= 100;
f078f209
LR		 2101 }
2102
f1dc5600
S		 2103 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2104 | (mask_m[48] << 26) | (mask_m[49] << 24)
2105 | (mask_m[50] << 22) | (mask_m[51] << 20)
2106 | (mask_m[52] << 18) | (mask_m[53] << 16)
2107 | (mask_m[54] << 14) | (mask_m[55] << 12)
2108 | (mask_m[56] << 10) | (mask_m[57] << 8)
2109 | (mask_m[58] << 6) | (mask_m[59] << 4)
2110 | (mask_m[60] << 2) | (mask_m[61] << 0);
2111 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2112 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2113
f1dc5600
S		 2114 tmp_mask = (mask_m[31] << 28)
2115 | (mask_m[32] << 26) | (mask_m[33] << 24)
2116 | (mask_m[34] << 22) | (mask_m[35] << 20)
2117 | (mask_m[36] << 18) | (mask_m[37] << 16)
2118 | (mask_m[48] << 14) | (mask_m[39] << 12)
2119 | (mask_m[40] << 10) | (mask_m[41] << 8)
2120 | (mask_m[42] << 6) | (mask_m[43] << 4)
2121 | (mask_m[44] << 2) | (mask_m[45] << 0);
2122 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2123 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2124
f1dc5600
S		 2125 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2126 | (mask_m[18] << 26) | (mask_m[18] << 24)
2127 | (mask_m[20] << 22) | (mask_m[20] << 20)
2128 | (mask_m[22] << 18) | (mask_m[22] << 16)
2129 | (mask_m[24] << 14) | (mask_m[24] << 12)
2130 | (mask_m[25] << 10) | (mask_m[26] << 8)
2131 | (mask_m[27] << 6) | (mask_m[28] << 4)
2132 | (mask_m[29] << 2) | (mask_m[30] << 0);
2133 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2134 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2135
f1dc5600
S		 2136 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2137 | (mask_m[2] << 26) | (mask_m[3] << 24)
2138 | (mask_m[4] << 22) | (mask_m[5] << 20)
2139 | (mask_m[6] << 18) | (mask_m[7] << 16)
2140 | (mask_m[8] << 14) | (mask_m[9] << 12)
2141 | (mask_m[10] << 10) | (mask_m[11] << 8)
2142 | (mask_m[12] << 6) | (mask_m[13] << 4)
2143 | (mask_m[14] << 2) | (mask_m[15] << 0);
2144 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2145 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2146
f1dc5600
S		 2147 tmp_mask = (mask_p[15] << 28)
2148 | (mask_p[14] << 26) | (mask_p[13] << 24)
2149 | (mask_p[12] << 22) | (mask_p[11] << 20)
2150 | (mask_p[10] << 18) | (mask_p[9] << 16)
2151 | (mask_p[8] << 14) | (mask_p[7] << 12)
2152 | (mask_p[6] << 10) | (mask_p[5] << 8)
2153 | (mask_p[4] << 6) | (mask_p[3] << 4)
2154 | (mask_p[2] << 2) | (mask_p[1] << 0);
2155 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2156 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2157
f1dc5600
S		 2158 tmp_mask = (mask_p[30] << 28)
2159 | (mask_p[29] << 26) | (mask_p[28] << 24)
2160 | (mask_p[27] << 22) | (mask_p[26] << 20)
2161 | (mask_p[25] << 18) | (mask_p[24] << 16)
2162 | (mask_p[23] << 14) | (mask_p[22] << 12)
2163 | (mask_p[21] << 10) | (mask_p[20] << 8)
2164 | (mask_p[19] << 6) | (mask_p[18] << 4)
2165 | (mask_p[17] << 2) | (mask_p[16] << 0);
2166 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2167 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2168
f1dc5600
S		 2169 tmp_mask = (mask_p[45] << 28)
2170 | (mask_p[44] << 26) | (mask_p[43] << 24)
2171 | (mask_p[42] << 22) | (mask_p[41] << 20)
2172 | (mask_p[40] << 18) | (mask_p[39] << 16)
2173 | (mask_p[38] << 14) | (mask_p[37] << 12)
2174 | (mask_p[36] << 10) | (mask_p[35] << 8)
2175 | (mask_p[34] << 6) | (mask_p[33] << 4)
2176 | (mask_p[32] << 2) | (mask_p[31] << 0);
2177 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2178 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2179
f1dc5600
S		 2180 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2181 | (mask_p[59] << 26) | (mask_p[58] << 24)
2182 | (mask_p[57] << 22) | (mask_p[56] << 20)
2183 | (mask_p[55] << 18) | (mask_p[54] << 16)
2184 | (mask_p[53] << 14) | (mask_p[52] << 12)
2185 | (mask_p[51] << 10) | (mask_p[50] << 8)
2186 | (mask_p[49] << 6) | (mask_p[48] << 4)
2187 | (mask_p[47] << 2) | (mask_p[46] << 0);
2188 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2189 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2190}
2191
ae8d2858
LR		 2192int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2193 bool bChannelChange)
f078f209 2194{
f078f209 2195 u32 saveLedState;
ae8d2858 2196 struct ath_softc *sc = ah->ah_sc;
f078f209
LR		 2197 struct ath_hal_5416 *ahp = AH5416(ah);
2198 struct ath9k_channel *curchan = ah->ah_curchan;
2199 u32 saveDefAntenna;
2200 u32 macStaId1;
ae8d2858 2201 int i, rx_chainmask, r;
f078f209 2202
ae8d2858
LR		 2203 ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2204 ahp->ah_txchainmask = sc->sc_tx_chainmask;
2205 ahp->ah_rxchainmask = sc->sc_rx_chainmask;
f078f209
LR		 2206
2207 if (AR_SREV_9280(ah)) {
2208 ahp->ah_txchainmask &= 0x3;
2209 ahp->ah_rxchainmask &= 0x3;
2210 }
2211
0de57d99 2212 if (ath9k_regd_check_channel(ah, chan) == NULL) {
f078f209 2213 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638
S		 2214 "invalid channel %u/0x%x; no mapping\n",
2215 chan->channel, chan->channelFlags);
ae8d2858 2216 return -EINVAL;
f078f209
LR		 2217 }
2218
ae8d2858
LR		 2219 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2220 return -EIO;
f078f209
LR		 2221
2222 if (curchan)
2223 ath9k_hw_getnf(ah, curchan);
2224
2225 if (bChannelChange &&
2226 (ahp->ah_chipFullSleep != true) &&
2227 (ah->ah_curchan != NULL) &&
2228 (chan->channel != ah->ah_curchan->channel) &&
2229 ((chan->channelFlags & CHANNEL_ALL) ==
2230 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2231 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
99405f93 2232 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
f078f209 2233
ae8d2858 2234 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
f078f209
LR		 2235 ath9k_hw_loadnf(ah, ah->ah_curchan);
2236 ath9k_hw_start_nfcal(ah);
ae8d2858 2237 return 0;
f078f209
LR		 2238 }
2239 }
2240
2241 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2242 if (saveDefAntenna == 0)
2243 saveDefAntenna = 1;
2244
2245 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2246
2247 saveLedState = REG_READ(ah, AR_CFG_LED) &
2248 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2249 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2250
2251 ath9k_hw_mark_phy_inactive(ah);
2252
2253 if (!ath9k_hw_chip_reset(ah, chan)) {
04bd4638 2254 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
ae8d2858 2255 return -EINVAL;
f078f209
LR		 2256 }
2257
369391db
VT		 2258 if (AR_SREV_9280_10_OR_LATER(ah))
2259 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2260
ae8d2858
LR		 2261 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2262 if (r)
2263 return r;
f078f209 2264
0ced0e17
JM		 2265 /* Setup MFP options for CCMP */
2266 if (AR_SREV_9280_20_OR_LATER(ah)) {
2267 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2268 * frames when constructing CCMP AAD. */
2269 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2270 0xc7ff);
2271 ah->sw_mgmt_crypto = false;
2272 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2273 /* Disable hardware crypto for management frames */
2274 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2275 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2276 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2277 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2278 ah->sw_mgmt_crypto = true;
2279 } else
2280 ah->sw_mgmt_crypto = true;
2281
f078f209
LR		 2282 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2283 ath9k_hw_set_delta_slope(ah, chan);
2284
2285 if (AR_SREV_9280_10_OR_LATER(ah))
2286 ath9k_hw_9280_spur_mitigate(ah, chan);
2287 else
2288 ath9k_hw_spur_mitigate(ah, chan);
2289
2290 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2291 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 2292 "error setting board options\n");
ae8d2858 2293 return -EIO;
f078f209
LR		 2294 }
2295
2296 ath9k_hw_decrease_chain_power(ah, chan);
2297
2298 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2299 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2300 | macStaId1
2301 | AR_STA_ID1_RTS_USE_DEF
2302 | (ah->ah_config.
60b67f51 2303 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
f078f209 2304 | ahp->ah_staId1Defaults);
b4696c8b 2305 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 2306
2307 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2308 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2309
2310 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2311
2312 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2313 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2314 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2315
2316 REG_WRITE(ah, AR_ISR, ~0);
2317
2318 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2319
2320 if (AR_SREV_9280_10_OR_LATER(ah)) {
ae8d2858
LR		 2321 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2322 return -EIO;
f078f209 2323 } else {
ae8d2858
LR		 2324 if (!(ath9k_hw_set_channel(ah, chan)))
2325 return -EIO;
f078f209
LR		 2326 }
2327
2328 for (i = 0; i < AR_NUM_DCU; i++)
2329 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2330
2331 ahp->ah_intrTxqs = 0;
60b67f51 2332 for (i = 0; i < ah->ah_caps.total_queues; i++)
f078f209
LR		 2333 ath9k_hw_resettxqueue(ah, i);
2334
b4696c8b 2335 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
f078f209
LR		 2336 ath9k_hw_init_qos(ah);
2337
e97275cb 2338#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2339 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2340 ath9k_enable_rfkill(ah);
2341#endif
f078f209
LR		 2342 ath9k_hw_init_user_settings(ah);
2343
f078f209
LR		 2344 REG_WRITE(ah, AR_STA_ID1,
2345 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2346
2347 ath9k_hw_set_dma(ah);
2348
2349 REG_WRITE(ah, AR_OBS, 8);
2350
2351 if (ahp->ah_intrMitigation) {
2352
2353 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2354 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2355 }
2356
2357 ath9k_hw_init_bb(ah, chan);
2358
ae8d2858
LR		 2359 if (!ath9k_hw_init_cal(ah, chan))
2360 return -EIO;;
f078f209
LR		 2361
2362 rx_chainmask = ahp->ah_rxchainmask;
2363 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2364 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2365 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2366 }
2367
2368 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2369
2370 if (AR_SREV_9100(ah)) {
2371 u32 mask;
2372 mask = REG_READ(ah, AR_CFG);
2373 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2374 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2375 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2376 } else {
2377 mask =
2378 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2379 REG_WRITE(ah, AR_CFG, mask);
2380 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2381 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2382 }
2383 } else {
2384#ifdef __BIG_ENDIAN
2385 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2386#endif
2387 }
2388
ae8d2858 2389 return 0;
f078f209
LR		 2390}
2391
f1dc5600
S		 2392/************************/
2393/* Key Cache Management */
2394/************************/
f078f209 2395
f1dc5600 2396bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
f078f209 2397{
f1dc5600 2398 u32 keyType;
f078f209 2399
f1dc5600
S		 2400 if (entry >= ah->ah_caps.keycache_size) {
2401 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2402 "entry %u out of range\n", entry);
f078f209
LR		 2403 return false;
2404 }
2405
f1dc5600 2406 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2407
f1dc5600
S		 2408 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2410 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2411 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2412 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2413 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2414 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2415 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2416
f1dc5600
S		 2417 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2418 u16 micentry = entry + 64;
f078f209 2419
f1dc5600
S		 2420 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2421 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2422 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2423 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2424
f078f209
LR		 2425 }
2426
f1dc5600
S		 2427 if (ah->ah_curchan == NULL)
2428 return true;
f078f209
LR		 2429
2430 return true;
2431}
2432
f1dc5600 2433bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
f078f209 2434{
f1dc5600 2435 u32 macHi, macLo;
f078f209 2436
f1dc5600
S		 2437 if (entry >= ah->ah_caps.keycache_size) {
2438 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2439 "entry %u out of range\n", entry);
f1dc5600 2440 return false;
f078f209
LR		 2441 }
2442
f1dc5600
S		 2443 if (mac != NULL) {
2444 macHi = (mac[5] << 8) | mac[4];
2445 macLo = (mac[3] << 24) |
2446 (mac[2] << 16) |
2447 (mac[1] << 8) |
2448 mac[0];
2449 macLo >>= 1;
2450 macLo |= (macHi & 1) << 31;
2451 macHi >>= 1;
f078f209 2452 } else {
f1dc5600 2453 macLo = macHi = 0;
f078f209 2454 }
f1dc5600
S		 2455 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2456 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2457
f1dc5600 2458 return true;
f078f209
LR		 2459}
2460
f1dc5600
S		 2461bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2462 const struct ath9k_keyval *k,
2463 const u8 *mac, int xorKey)
f078f209 2464{
f1dc5600
S		 2465 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2466 u32 key0, key1, key2, key3, key4;
2467 u32 keyType;
2468 u32 xorMask = xorKey ?
2469 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2470 | ATH9K_KEY_XOR) : 0;
f078f209 2471 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 2472
f1dc5600
S		 2473 if (entry >= pCap->keycache_size) {
2474 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2475 "entry %u out of range\n", entry);
f1dc5600 2476 return false;
f078f209
LR		 2477 }
2478
f1dc5600
S		 2479 switch (k->kv_type) {
2480 case ATH9K_CIPHER_AES_OCB:
2481 keyType = AR_KEYTABLE_TYPE_AES;
2482 break;
2483 case ATH9K_CIPHER_AES_CCM:
2484 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2485 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2486 "AES-CCM not supported by mac rev 0x%x\n",
f1dc5600
S		 2487 ah->ah_macRev);
2488 return false;
2489 }
2490 keyType = AR_KEYTABLE_TYPE_CCM;
2491 break;
2492 case ATH9K_CIPHER_TKIP:
2493 keyType = AR_KEYTABLE_TYPE_TKIP;
2494 if (ATH9K_IS_MIC_ENABLED(ah)
2495 && entry + 64 >= pCap->keycache_size) {
2496 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2497 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2498 return false;
2499 }
2500 break;
2501 case ATH9K_CIPHER_WEP:
2502 if (k->kv_len < LEN_WEP40) {
2503 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2504 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2505 return false;
2506 }
2507 if (k->kv_len <= LEN_WEP40)
2508 keyType = AR_KEYTABLE_TYPE_40;
2509 else if (k->kv_len <= LEN_WEP104)
2510 keyType = AR_KEYTABLE_TYPE_104;
2511 else
2512 keyType = AR_KEYTABLE_TYPE_128;
2513 break;
2514 case ATH9K_CIPHER_CLR:
2515 keyType = AR_KEYTABLE_TYPE_CLR;
2516 break;
2517 default:
2518 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2519 "cipher %u not supported\n", k->kv_type);
f1dc5600 2520 return false;
f078f209
LR		 2521 }
2522
f1dc5600
S		 2523 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2524 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2525 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2526 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2527 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2528 if (k->kv_len <= LEN_WEP104)
2529 key4 &= 0xff;
f078f209 2530
f1dc5600
S		 2531 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2532 u16 micentry = entry + 64;
f078f209 2533
f1dc5600
S		 2534 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2535 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2536 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2537 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2538 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2539 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2540 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2541
f1dc5600
S		 2542 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2543 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2544
f1dc5600
S		 2545 mic0 = get_unaligned_le32(k->kv_mic + 0);
2546 mic2 = get_unaligned_le32(k->kv_mic + 4);
2547 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2548 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2549 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2550 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2551 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2552 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2554 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2555 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2556 AR_KEYTABLE_TYPE_CLR);
f078f209 2557
f1dc5600
S		 2558 } else {
2559 u32 mic0, mic2;
f078f209 2560
f1dc5600
S		 2561 mic0 = get_unaligned_le32(k->kv_mic + 0);
2562 mic2 = get_unaligned_le32(k->kv_mic + 4);
2563 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2564 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2565 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2566 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2567 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2568 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2569 AR_KEYTABLE_TYPE_CLR);
2570 }
2571 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2572 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2575 } else {
2576 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2577 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2578 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2579 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2581 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2582
f1dc5600
S		 2583 (void) ath9k_hw_keysetmac(ah, entry, mac);
2584 }
f078f209 2585
f1dc5600
S		 2586 if (ah->ah_curchan == NULL)
2587 return true;
f078f209
LR		 2588
2589 return true;
2590}
2591
f1dc5600 2592bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
f078f209 2593{
f1dc5600
S		 2594 if (entry < ah->ah_caps.keycache_size) {
2595 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2596 if (val & AR_KEYTABLE_VALID)
2597 return true;
2598 }
2599 return false;
f078f209
LR		 2600}
2601
f1dc5600
S		 2602/******************************/
2603/* Power Management (Chipset) */
2604/******************************/
2605
2606static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
f078f209 2607{
f1dc5600
S		 2608 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2609 if (setChip) {
2610 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2611 AR_RTC_FORCE_WAKE_EN);
2612 if (!AR_SREV_9100(ah))
2613 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2614
d03a66c1 2615 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2616 AR_RTC_RESET_EN);
2617 }
f078f209
LR		 2618}
2619
f1dc5600 2620static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
f078f209 2621{
f1dc5600
S		 2622 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2623 if (setChip) {
2624 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2625
f1dc5600
S		 2626 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2627 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2628 AR_RTC_FORCE_WAKE_ON_INT);
2629 } else {
2630 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2631 AR_RTC_FORCE_WAKE_EN);
f078f209 2632 }
f078f209 2633 }
f078f209
LR		 2634}
2635
f1dc5600
S		 2636static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2637 int setChip)
f078f209 2638{
f1dc5600
S		 2639 u32 val;
2640 int i;
f078f209 2641
f1dc5600
S		 2642 if (setChip) {
2643 if ((REG_READ(ah, AR_RTC_STATUS) &
2644 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2645 if (ath9k_hw_set_reset_reg(ah,
2646 ATH9K_RESET_POWER_ON) != true) {
2647 return false;
2648 }
2649 }
2650 if (AR_SREV_9100(ah))
2651 REG_SET_BIT(ah, AR_RTC_RESET,
2652 AR_RTC_RESET_EN);
f078f209 2653
f1dc5600
S		 2654 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2655 AR_RTC_FORCE_WAKE_EN);
2656 udelay(50);
f078f209 2657
f1dc5600
S		 2658 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2659 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2660 if (val == AR_RTC_STATUS_ON)
2661 break;
2662 udelay(50);
2663 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2664 AR_RTC_FORCE_WAKE_EN);
f078f209 2665 }
f1dc5600
S		 2666 if (i == 0) {
2667 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2668 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2669 return false;
f078f209 2670 }
f078f209
LR		 2671 }
2672
f1dc5600 2673 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2674
f1dc5600 2675 return true;
f078f209
LR		 2676}
2677
f1dc5600
S		 2678bool ath9k_hw_setpower(struct ath_hal *ah,
2679 enum ath9k_power_mode mode)
f078f209
LR		 2680{
2681 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600
S		 2682 static const char *modes[] = {
2683 "AWAKE",
2684 "FULL-SLEEP",
2685 "NETWORK SLEEP",
2686 "UNDEFINED"
2687 };
2688 int status = true, setChip = true;
2689
04bd4638 2690 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
3cbb5dd7 2691 modes[ah->ah_power_mode], modes[mode],
f1dc5600
S		 2692 setChip ? "set chip " : "");
2693
2694 switch (mode) {
2695 case ATH9K_PM_AWAKE:
2696 status = ath9k_hw_set_power_awake(ah, setChip);
2697 break;
2698 case ATH9K_PM_FULL_SLEEP:
2699 ath9k_set_power_sleep(ah, setChip);
2700 ahp->ah_chipFullSleep = true;
2701 break;
2702 case ATH9K_PM_NETWORK_SLEEP:
2703 ath9k_set_power_network_sleep(ah, setChip);
2704 break;
f078f209 2705 default:
f1dc5600 2706 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2707 "Unknown power mode %u\n", mode);
f078f209
LR		 2708 return false;
2709 }
3cbb5dd7 2710 ah->ah_power_mode = mode;
f1dc5600
S		 2711
2712 return status;
f078f209
LR		 2713}
2714
f1dc5600 2715void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
f078f209
LR		 2716{
2717 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 2718 u8 i;
f078f209 2719
f1dc5600
S		 2720 if (ah->ah_isPciExpress != true)
2721 return;
f078f209 2722
f1dc5600
S		 2723 if (ah->ah_config.pcie_powersave_enable == 2)
2724 return;
2725
2726 if (restore)
2727 return;
2728
2729 if (AR_SREV_9280_20_OR_LATER(ah)) {
2730 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2731 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2732 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
f078f209 2733 }
f1dc5600
S		 2734 udelay(1000);
2735 } else if (AR_SREV_9280(ah) &&
2736 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2737 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2738 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2739
2740 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2741 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2742 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2743
2744 if (ah->ah_config.pcie_clock_req)
2745 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2746 else
2747 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2748
2749 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2750 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2751 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2752
2753 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2754
2755 udelay(1000);
2756 } else {
2757 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2758 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2759 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2760 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2761 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2762 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2763 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2764 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2766 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 2767 }
2768
f1dc5600
S		 2769 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2770
2771 if (ah->ah_config.pcie_waen) {
2772 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2773 } else {
e7594072
SB		 2774 if (AR_SREV_9285(ah))
2775 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2776 else if (AR_SREV_9280(ah))
2777 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 2778 else
e7594072 2779 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 2780 }
e7594072 2781
f078f209
LR		 2782}
2783
f1dc5600
S		 2784/**********************/
2785/* Interrupt Handling */
2786/**********************/
2787
f078f209
LR		 2788bool ath9k_hw_intrpend(struct ath_hal *ah)
2789{
2790 u32 host_isr;
2791
2792 if (AR_SREV_9100(ah))
2793 return true;
2794
2795 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2796 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2797 return true;
2798
2799 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2800 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2801 && (host_isr != AR_INTR_SPURIOUS))
2802 return true;
2803
2804 return false;
2805}
2806
2807bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2808{
2809 u32 isr = 0;
2810 u32 mask2 = 0;
60b67f51 2811 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 2812 u32 sync_cause = 0;
2813 bool fatal_int = false;
f1dc5600 2814 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 2815
2816 if (!AR_SREV_9100(ah)) {
2817 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2818 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2819 == AR_RTC_STATUS_ON) {
2820 isr = REG_READ(ah, AR_ISR);
2821 }
2822 }
2823
f1dc5600
S		 2824 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2825 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2826
2827 *masked = 0;
2828
2829 if (!isr && !sync_cause)
2830 return false;
2831 } else {
2832 *masked = 0;
2833 isr = REG_READ(ah, AR_ISR);
2834 }
2835
2836 if (isr) {
f078f209
LR		 2837 if (isr & AR_ISR_BCNMISC) {
2838 u32 isr2;
2839 isr2 = REG_READ(ah, AR_ISR_S2);
2840 if (isr2 & AR_ISR_S2_TIM)
2841 mask2 |= ATH9K_INT_TIM;
2842 if (isr2 & AR_ISR_S2_DTIM)
2843 mask2 |= ATH9K_INT_DTIM;
2844 if (isr2 & AR_ISR_S2_DTIMSYNC)
2845 mask2 |= ATH9K_INT_DTIMSYNC;
2846 if (isr2 & (AR_ISR_S2_CABEND))
2847 mask2 |= ATH9K_INT_CABEND;
2848 if (isr2 & AR_ISR_S2_GTT)
2849 mask2 |= ATH9K_INT_GTT;
2850 if (isr2 & AR_ISR_S2_CST)
2851 mask2 |= ATH9K_INT_CST;
2852 }
2853
2854 isr = REG_READ(ah, AR_ISR_RAC);
2855 if (isr == 0xffffffff) {
2856 *masked = 0;
2857 return false;
2858 }
2859
2860 *masked = isr & ATH9K_INT_COMMON;
2861
2862 if (ahp->ah_intrMitigation) {
f078f209
LR		 2863 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2864 *masked |= ATH9K_INT_RX;
2865 }
2866
2867 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2868 *masked |= ATH9K_INT_RX;
2869 if (isr &
2870 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2871 AR_ISR_TXEOL)) {
2872 u32 s0_s, s1_s;
2873
2874 *masked |= ATH9K_INT_TX;
2875
2876 s0_s = REG_READ(ah, AR_ISR_S0_S);
2877 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2878 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2879
2880 s1_s = REG_READ(ah, AR_ISR_S1_S);
2881 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2882 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2883 }
2884
2885 if (isr & AR_ISR_RXORN) {
2886 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2887 "receive FIFO overrun interrupt\n");
f078f209
LR		 2888 }
2889
2890 if (!AR_SREV_9100(ah)) {
60b67f51 2891 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2892 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2893 if (isr5 & AR_ISR_S5_TIM_TIMER)
2894 *masked |= ATH9K_INT_TIM_TIMER;
2895 }
2896 }
2897
2898 *masked |= mask2;
2899 }
f1dc5600 2900
f078f209
LR		 2901 if (AR_SREV_9100(ah))
2902 return true;
f1dc5600 2903
f078f209
LR		 2904 if (sync_cause) {
2905 fatal_int =
2906 (sync_cause &
2907 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2908 ? true : false;
2909
2910 if (fatal_int) {
2911 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2912 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2913 "received PCI FATAL interrupt\n");
f078f209
LR		 2914 }
2915 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2916 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2917 "received PCI PERR interrupt\n");
f078f209
LR		 2918 }
2919 }
2920 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2921 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2922 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2923 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2924 REG_WRITE(ah, AR_RC, 0);
2925 *masked |= ATH9K_INT_FATAL;
2926 }
2927 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2928 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2929 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2930 }
2931
2932 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2933 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2934 }
f1dc5600 2935
f078f209
LR		 2936 return true;
2937}
2938
2939enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2940{
2941 return AH5416(ah)->ah_maskReg;
2942}
2943
2944enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2945{
2946 struct ath_hal_5416 *ahp = AH5416(ah);
2947 u32 omask = ahp->ah_maskReg;
2948 u32 mask, mask2;
60b67f51 2949 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2950
04bd4638 2951 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2952
2953 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 2954 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2955 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2956 (void) REG_READ(ah, AR_IER);
2957 if (!AR_SREV_9100(ah)) {
2958 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2959 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2960
2961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2962 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2963 }
2964 }
2965
2966 mask = ints & ATH9K_INT_COMMON;
2967 mask2 = 0;
2968
2969 if (ints & ATH9K_INT_TX) {
2970 if (ahp->ah_txOkInterruptMask)
2971 mask |= AR_IMR_TXOK;
2972 if (ahp->ah_txDescInterruptMask)
2973 mask |= AR_IMR_TXDESC;
2974 if (ahp->ah_txErrInterruptMask)
2975 mask |= AR_IMR_TXERR;
2976 if (ahp->ah_txEolInterruptMask)
2977 mask |= AR_IMR_TXEOL;
2978 }
2979 if (ints & ATH9K_INT_RX) {
2980 mask |= AR_IMR_RXERR;
2981 if (ahp->ah_intrMitigation)
2982 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2983 else
2984 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2985 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2986 mask |= AR_IMR_GENTMR;
2987 }
2988
2989 if (ints & (ATH9K_INT_BMISC)) {
2990 mask |= AR_IMR_BCNMISC;
2991 if (ints & ATH9K_INT_TIM)
2992 mask2 |= AR_IMR_S2_TIM;
2993 if (ints & ATH9K_INT_DTIM)
2994 mask2 |= AR_IMR_S2_DTIM;
2995 if (ints & ATH9K_INT_DTIMSYNC)
2996 mask2 |= AR_IMR_S2_DTIMSYNC;
2997 if (ints & ATH9K_INT_CABEND)
2998 mask2 |= (AR_IMR_S2_CABEND);
2999 }
3000
3001 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3002 mask |= AR_IMR_BCNMISC;
3003 if (ints & ATH9K_INT_GTT)
3004 mask2 |= AR_IMR_S2_GTT;
3005 if (ints & ATH9K_INT_CST)
3006 mask2 |= AR_IMR_S2_CST;
3007 }
3008
04bd4638 3009 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3010 REG_WRITE(ah, AR_IMR, mask);
3011 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3012 AR_IMR_S2_DTIM |
3013 AR_IMR_S2_DTIMSYNC |
3014 AR_IMR_S2_CABEND |
3015 AR_IMR_S2_CABTO |
3016 AR_IMR_S2_TSFOOR |
3017 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3018 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3019 ahp->ah_maskReg = ints;
3020
60b67f51 3021 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3022 if (ints & ATH9K_INT_TIM_TIMER)
3023 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3024 else
3025 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3026 }
3027
3028 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3029 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3030 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3031 if (!AR_SREV_9100(ah)) {
3032 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3033 AR_INTR_MAC_IRQ);
3034 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3035
3036
3037 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3038 AR_INTR_SYNC_DEFAULT);
3039 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3040 AR_INTR_SYNC_DEFAULT);
3041 }
3042 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3043 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3044 }
3045
3046 return omask;
3047}
3048
f1dc5600
S		 3049/*******************/
3050/* Beacon Handling */
3051/*******************/
3052
3053void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
f078f209
LR		 3054{
3055 struct ath_hal_5416 *ahp = AH5416(ah);
3056 int flags = 0;
3057
3058 ahp->ah_beaconInterval = beacon_period;
3059
3060 switch (ah->ah_opmode) {
d97809db
CM		 3061 case NL80211_IFTYPE_STATION:
3062 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3063 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3064 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3065 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3066 flags |= AR_TBTT_TIMER_EN;
3067 break;
d97809db 3068 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 3069 REG_SET_BIT(ah, AR_TXCFG,
3070 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3071 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3072 TU_TO_USEC(next_beacon +
3073 (ahp->ah_atimWindow ? ahp->
3074 ah_atimWindow : 1)));
3075 flags |= AR_NDP_TIMER_EN;
d97809db 3076 case NL80211_IFTYPE_AP:
f078f209
LR		 3077 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3078 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3079 TU_TO_USEC(next_beacon -
3080 ah->ah_config.
60b67f51 3081 dma_beacon_response_time));
f078f209
LR		 3082 REG_WRITE(ah, AR_NEXT_SWBA,
3083 TU_TO_USEC(next_beacon -
3084 ah->ah_config.
60b67f51 3085 sw_beacon_response_time));
f078f209
LR		 3086 flags |=
3087 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3088 break;
d97809db
CM		 3089 default:
3090 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3091 "%s: unsupported opmode: %d\n",
3092 __func__, ah->ah_opmode);
3093 return;
3094 break;
f078f209
LR		 3095 }
3096
3097 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3098 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3099 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3100 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3101
3102 beacon_period &= ~ATH9K_BEACON_ENA;
3103 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3104 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3105 ath9k_hw_reset_tsf(ah);
3106 }
3107
3108 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3109}
3110
f1dc5600
S		 3111void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3112 const struct ath9k_beacon_state *bs)
f078f209
LR		 3113{
3114 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
60b67f51 3115 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 3116
3117 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3118
3119 REG_WRITE(ah, AR_BEACON_PERIOD,
3120 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3121 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3122 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3123
3124 REG_RMW_FIELD(ah, AR_RSSI_THR,
3125 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3126
3127 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3128
3129 if (bs->bs_sleepduration > beaconintval)
3130 beaconintval = bs->bs_sleepduration;
3131
3132 dtimperiod = bs->bs_dtimperiod;
3133 if (bs->bs_sleepduration > dtimperiod)
3134 dtimperiod = bs->bs_sleepduration;
3135
3136 if (beaconintval == dtimperiod)
3137 nextTbtt = bs->bs_nextdtim;
3138 else
3139 nextTbtt = bs->bs_nexttbtt;
3140
04bd4638
S		 3141 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3142 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3143 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3144 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3145
f1dc5600
S		 3146 REG_WRITE(ah, AR_NEXT_DTIM,
3147 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3148 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3149
f1dc5600
S		 3150 REG_WRITE(ah, AR_SLEEP1,
3151 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3152 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3153
f1dc5600
S		 3154 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3155 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3156 else
3157 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3158
f1dc5600
S		 3159 REG_WRITE(ah, AR_SLEEP2,
3160 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3161
f1dc5600
S		 3162 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3163 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3164
f1dc5600
S		 3165 REG_SET_BIT(ah, AR_TIMER_MODE,
3166 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3167 AR_DTIM_TIMER_EN);
f078f209 3168
f078f209
LR		 3169}
3170
f1dc5600
S		 3171/*******************/
3172/* HW Capabilities */
3173/*******************/
3174
3175bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
f078f209
LR		 3176{
3177 struct ath_hal_5416 *ahp = AH5416(ah);
60b67f51 3178 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f1dc5600 3179 u16 capField = 0, eeval;
f078f209 3180
f1dc5600 3181 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
f078f209 3182
f1dc5600 3183 ah->ah_currentRD = eeval;
f078f209 3184
f1dc5600
S		 3185 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3186 ah->ah_currentRDExt = eeval;
f078f209 3187
f1dc5600
S		 3188 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3189
d97809db 3190 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
f1dc5600
S		 3191 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3192 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3193 ah->ah_currentRD += 5;
3194 else if (ah->ah_currentRD == 0x41)
3195 ah->ah_currentRD = 0x43;
3196 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
04bd4638 3197 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
f1dc5600 3198 }
f078f209 3199
f1dc5600
S		 3200 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3201 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3202
f1dc5600
S		 3203 if (eeval & AR5416_OPFLAGS_11A) {
3204 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3205 if (ah->ah_config.ht_enable) {
3206 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3207 set_bit(ATH9K_MODE_11NA_HT20,
3208 pCap->wireless_modes);
3209 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3210 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3211 pCap->wireless_modes);
3212 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3213 pCap->wireless_modes);
3214 }
f078f209 3215 }
f078f209
LR		 3216 }
3217
f1dc5600
S		 3218 if (eeval & AR5416_OPFLAGS_11G) {
3219 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3220 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3221 if (ah->ah_config.ht_enable) {
3222 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3223 set_bit(ATH9K_MODE_11NG_HT20,
3224 pCap->wireless_modes);
3225 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3226 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3227 pCap->wireless_modes);
3228 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3229 pCap->wireless_modes);
3230 }
3231 }
f078f209 3232 }
f1dc5600
S		 3233
3234 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3235 if ((ah->ah_isPciExpress)
3236 || (eeval & AR5416_OPFLAGS_11A)) {
3237 pCap->rx_chainmask =
3238 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
f078f209 3239 } else {
f1dc5600
S		 3240 pCap->rx_chainmask =
3241 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
f078f209
LR		 3242 }
3243
f1dc5600
S		 3244 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3245 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3246
f1dc5600
S		 3247 pCap->low_2ghz_chan = 2312;
3248 pCap->high_2ghz_chan = 2732;
f078f209 3249
f1dc5600
S		 3250 pCap->low_5ghz_chan = 4920;
3251 pCap->high_5ghz_chan = 6100;
f078f209 3252
f1dc5600
S		 3253 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3254 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3255 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3256
f1dc5600
S		 3257 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3258 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3259 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3260
f1dc5600 3261 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
f078f209 3262
f1dc5600
S		 3263 if (ah->ah_config.ht_enable)
3264 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3265 else
3266 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3267
f1dc5600
S		 3268 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3269 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3270 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3271 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3272
f1dc5600
S		 3273 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3274 pCap->total_queues =
3275 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3276 else
3277 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3278
f1dc5600
S		 3279 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3280 pCap->keycache_size =
3281 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3282 else
3283 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3284
f1dc5600
S		 3285 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3286 pCap->num_mr_retries = 4;
3287 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3288
cb33c412
SB		 3289 if (AR_SREV_9285_10_OR_LATER(ah))
3290 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3291 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3292 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3293 else
3294 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3295
f1dc5600
S		 3296 if (AR_SREV_9280_10_OR_LATER(ah)) {
3297 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3298 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3299 } else {
3300 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3301 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
f078f209
LR		 3302 }
3303
f1dc5600
S		 3304 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3305 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3306 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3307 } else {
3308 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3309 }
3310
f1dc5600
S		 3311 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3312
e97275cb 3313#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600
S		 3314 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3315 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3316 ah->ah_rfkill_gpio =
3317 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3318 ah->ah_rfkill_polarity =
3319 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3320
3321 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3322 }
f1dc5600 3323#endif
f078f209 3324
f1dc5600
S		 3325 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3326 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3327 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3328 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3329 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3330 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3331 else
f1dc5600 3332 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3333
e7594072 3334 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3335 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3336 else
3337 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3338
f1dc5600
S		 3339 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3340 pCap->reg_cap =
3341 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3342 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3343 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3344 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3345 } else {
f1dc5600
S		 3346 pCap->reg_cap =
3347 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3348 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3349 }
f078f209 3350
f1dc5600
S		 3351 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3352
3353 pCap->num_antcfg_5ghz =
2df1bff4 3354 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3355 pCap->num_antcfg_2ghz =
2df1bff4 3356 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3357
138ab2e4 3358 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
c97c92d9
VT		 3359 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3360 ah->ah_btactive_gpio = 6;
3361 ah->ah_wlanactive_gpio = 5;
3362 }
3363
f1dc5600 3364 return true;
f078f209
LR		 3365}
3366
f1dc5600
S		 3367bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3368 u32 capability, u32 *result)
f078f209 3369{
f1dc5600
S		 3370 struct ath_hal_5416 *ahp = AH5416(ah);
3371 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 3372
f1dc5600
S		 3373 switch (type) {
3374 case ATH9K_CAP_CIPHER:
3375 switch (capability) {
3376 case ATH9K_CIPHER_AES_CCM:
3377 case ATH9K_CIPHER_AES_OCB:
3378 case ATH9K_CIPHER_TKIP:
3379 case ATH9K_CIPHER_WEP:
3380 case ATH9K_CIPHER_MIC:
3381 case ATH9K_CIPHER_CLR:
3382 return true;
3383 default:
3384 return false;
3385 }
3386 case ATH9K_CAP_TKIP_MIC:
3387 switch (capability) {
3388 case 0:
3389 return true;
3390 case 1:
3391 return (ahp->ah_staId1Defaults &
3392 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3393 false;
3394 }
3395 case ATH9K_CAP_TKIP_SPLIT:
3396 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3397 false : true;
3398 case ATH9K_CAP_WME_TKIPMIC:
3399 return 0;
3400 case ATH9K_CAP_PHYCOUNTERS:
3401 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3402 case ATH9K_CAP_DIVERSITY:
3403 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3404 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3405 true : false;
3406 case ATH9K_CAP_PHYDIAG:
3407 return true;
3408 case ATH9K_CAP_MCAST_KEYSRCH:
3409 switch (capability) {
3410 case 0:
3411 return true;
3412 case 1:
3413 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3414 return false;
3415 } else {
3416 return (ahp->ah_staId1Defaults &
3417 AR_STA_ID1_MCAST_KSRCH) ? true :
3418 false;
3419 }
3420 }
3421 return false;
3422 case ATH9K_CAP_TSF_ADJUST:
3423 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3424 true : false;
3425 case ATH9K_CAP_RFSILENT:
3426 if (capability == 3)
3427 return false;
3428 case ATH9K_CAP_ANT_CFG_2GHZ:
3429 *result = pCap->num_antcfg_2ghz;
3430 return true;
3431 case ATH9K_CAP_ANT_CFG_5GHZ:
3432 *result = pCap->num_antcfg_5ghz;
3433 return true;
3434 case ATH9K_CAP_TXPOW:
3435 switch (capability) {
3436 case 0:
3437 return 0;
3438 case 1:
3439 *result = ah->ah_powerLimit;
3440 return 0;
3441 case 2:
3442 *result = ah->ah_maxPowerLevel;
3443 return 0;
3444 case 3:
3445 *result = ah->ah_tpScale;
3446 return 0;
3447 }
3448 return false;
3449 default:
3450 return false;
f078f209 3451 }
f078f209
LR		 3452}
3453
f1dc5600
S		 3454bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3455 u32 capability, u32 setting, int *status)
f078f209 3456{
f078f209 3457 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 3458 u32 v;
f078f209 3459
f1dc5600
S		 3460 switch (type) {
3461 case ATH9K_CAP_TKIP_MIC:
3462 if (setting)
3463 ahp->ah_staId1Defaults |=
3464 AR_STA_ID1_CRPT_MIC_ENABLE;
3465 else
3466 ahp->ah_staId1Defaults &=
3467 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3468 return true;
3469 case ATH9K_CAP_DIVERSITY:
3470 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3471 if (setting)
3472 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3473 else
3474 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3475 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3476 return true;
3477 case ATH9K_CAP_MCAST_KEYSRCH:
3478 if (setting)
3479 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3480 else
3481 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3482 return true;
3483 case ATH9K_CAP_TSF_ADJUST:
3484 if (setting)
3485 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3486 else
3487 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3488 return true;
3489 default:
3490 return false;
f078f209
LR		 3491 }
3492}
3493
f1dc5600
S		 3494/****************************/
3495/* GPIO / RFKILL / Antennae */
3496/****************************/
f078f209 3497
f1dc5600
S		 3498static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3499 u32 gpio, u32 type)
3500{
3501 int addr;
3502 u32 gpio_shift, tmp;
f078f209 3503
f1dc5600
S		 3504 if (gpio > 11)
3505 addr = AR_GPIO_OUTPUT_MUX3;
3506 else if (gpio > 5)
3507 addr = AR_GPIO_OUTPUT_MUX2;
3508 else
3509 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3510
f1dc5600 3511 gpio_shift = (gpio % 6) * 5;
f078f209 3512
f1dc5600
S		 3513 if (AR_SREV_9280_20_OR_LATER(ah)
3514 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3515 REG_RMW(ah, addr, (type << gpio_shift),
3516 (0x1f << gpio_shift));
f078f209 3517 } else {
f1dc5600
S		 3518 tmp = REG_READ(ah, addr);
3519 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3520 tmp &= ~(0x1f << gpio_shift);
3521 tmp |= (type << gpio_shift);
3522 REG_WRITE(ah, addr, tmp);
f078f209 3523 }
f078f209
LR		 3524}
3525
f1dc5600 3526void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
f078f209 3527{
f1dc5600 3528 u32 gpio_shift;
f078f209 3529
f1dc5600 3530 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
f078f209 3531
f1dc5600 3532 gpio_shift = gpio << 1;
f078f209 3533
f1dc5600
S		 3534 REG_RMW(ah,
3535 AR_GPIO_OE_OUT,
3536 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3537 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3538}
3539
f1dc5600 3540u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
f078f209 3541{
cb33c412
SB		 3542#define MS_REG_READ(x, y) \
3543 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3544
f1dc5600
S		 3545 if (gpio >= ah->ah_caps.num_gpio_pins)
3546 return 0xffffffff;
f078f209 3547
cb33c412
SB		 3548 if (AR_SREV_9285_10_OR_LATER(ah))
3549 return MS_REG_READ(AR9285, gpio) != 0;
3550 else if (AR_SREV_9280_10_OR_LATER(ah))
3551 return MS_REG_READ(AR928X, gpio) != 0;
3552 else
3553 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3554}
3555
f1dc5600
S		 3556void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3557 u32 ah_signal_type)
f078f209 3558{
f1dc5600 3559 u32 gpio_shift;
f078f209 3560
f1dc5600 3561 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3562
f1dc5600 3563 gpio_shift = 2 * gpio;
f078f209 3564
f1dc5600
S		 3565 REG_RMW(ah,
3566 AR_GPIO_OE_OUT,
3567 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3568 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3569}
3570
f1dc5600 3571void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
f078f209 3572{
f1dc5600
S		 3573 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3574 AR_GPIO_BIT(gpio));
f078f209
LR		 3575}
3576
e97275cb 3577#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600 3578void ath9k_enable_rfkill(struct ath_hal *ah)
f078f209 3579{
f1dc5600
S		 3580 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3581 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
f078f209 3582
f1dc5600
S		 3583 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3584 AR_GPIO_INPUT_MUX2_RFSILENT);
3585
3586 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3587 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
f078f209 3588}
f1dc5600 3589#endif
f078f209 3590
f1dc5600 3591int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
f078f209 3592{
f1dc5600
S		 3593 struct ath9k_channel *chan = ah->ah_curchan;
3594 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3595 u16 ant_config;
3596 u32 halNumAntConfig;
f078f209 3597
f1dc5600
S		 3598 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3599 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
f078f209 3600
f1dc5600
S		 3601 if (cfg < halNumAntConfig) {
3602 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3603 cfg, &ant_config)) {
3604 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3605 return 0;
f078f209 3606 }
f078f209
LR		 3607 }
3608
f1dc5600 3609 return -EINVAL;
f078f209
LR		 3610}
3611
f1dc5600 3612u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
f078f209 3613{
f1dc5600 3614 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3615}
3616
f1dc5600 3617void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
f078f209 3618{
f1dc5600 3619 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3620}
3621
f1dc5600
S		 3622bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3623 enum ath9k_ant_setting settings,
3624 struct ath9k_channel *chan,
3625 u8 *tx_chainmask,
3626 u8 *rx_chainmask,
3627 u8 *antenna_cfgd)
f078f209 3628{
f1dc5600
S		 3629 struct ath_hal_5416 *ahp = AH5416(ah);
3630 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3631
f1dc5600
S		 3632 if (AR_SREV_9280(ah)) {
3633 if (!tx_chainmask_cfg) {
f078f209 3634
f1dc5600
S		 3635 tx_chainmask_cfg = *tx_chainmask;
3636 rx_chainmask_cfg = *rx_chainmask;
3637 }
f078f209 3638
f1dc5600
S		 3639 switch (settings) {
3640 case ATH9K_ANT_FIXED_A:
3641 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3642 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3643 *antenna_cfgd = true;
3644 break;
3645 case ATH9K_ANT_FIXED_B:
3646 if (ah->ah_caps.tx_chainmask >
3647 ATH9K_ANTENNA1_CHAINMASK) {
3648 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3649 }
3650 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3651 *antenna_cfgd = true;
3652 break;
3653 case ATH9K_ANT_VARIABLE:
3654 *tx_chainmask = tx_chainmask_cfg;
3655 *rx_chainmask = rx_chainmask_cfg;
3656 *antenna_cfgd = true;
3657 break;
3658 default:
3659 break;
3660 }
3661 } else {
3662 ahp->ah_diversityControl = settings;
f078f209 3663 }
f078f209 3664
f1dc5600 3665 return true;
f078f209
LR		 3666}
3667
f1dc5600
S		 3668/*********************/
3669/* General Operation */
3670/*********************/
3671
3672u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
f078f209 3673{
f1dc5600
S		 3674 u32 bits = REG_READ(ah, AR_RX_FILTER);
3675 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3676
f1dc5600
S		 3677 if (phybits & AR_PHY_ERR_RADAR)
3678 bits |= ATH9K_RX_FILTER_PHYRADAR;
3679 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3680 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3681
f1dc5600 3682 return bits;
f078f209
LR		 3683}
3684
f1dc5600 3685void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
f078f209 3686{
f1dc5600 3687 u32 phybits;
f078f209 3688
f1dc5600
S		 3689 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3690 phybits = 0;
3691 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3692 phybits |= AR_PHY_ERR_RADAR;
3693 if (bits & ATH9K_RX_FILTER_PHYERR)
3694 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3695 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3696
f1dc5600
S		 3697 if (phybits)
3698 REG_WRITE(ah, AR_RXCFG,
3699 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3700 else
3701 REG_WRITE(ah, AR_RXCFG,
3702 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3703}
f078f209 3704
f1dc5600
S		 3705bool ath9k_hw_phy_disable(struct ath_hal *ah)
3706{
3707 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3708}
f078f209 3709
f1dc5600
S		 3710bool ath9k_hw_disable(struct ath_hal *ah)
3711{
3712 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3713 return false;
f078f209 3714
f1dc5600 3715 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3716}
3717
f1dc5600 3718bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
f078f209 3719{
f1dc5600 3720 struct ath9k_channel *chan = ah->ah_curchan;
f078f209 3721
f1dc5600 3722 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3723
f1dc5600
S		 3724 if (ath9k_hw_set_txpower(ah, chan,
3725 ath9k_regd_get_ctl(ah, chan),
3726 ath9k_regd_get_antenna_allowed(ah, chan),
3727 chan->maxRegTxPower * 2,
3728 min((u32) MAX_RATE_POWER,
3729 (u32) ah->ah_powerLimit)) != 0)
6f255425 3730 return false;
f1dc5600 3731
6f255425
LR		 3732 return true;
3733}
3734
f1dc5600 3735void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
f078f209 3736{
f1dc5600 3737 struct ath_hal_5416 *ahp = AH5416(ah);
6f255425 3738
f1dc5600 3739 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
f078f209
LR		 3740}
3741
f1dc5600 3742bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
f078f209
LR		 3743{
3744 struct ath_hal_5416 *ahp = AH5416(ah);
3745
f1dc5600
S		 3746 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3747
f078f209
LR		 3748 return true;
3749}
3750
f1dc5600 3751void ath9k_hw_setopmode(struct ath_hal *ah)
f078f209 3752{
f1dc5600 3753 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 3754}
3755
f1dc5600 3756void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
f078f209 3757{
f1dc5600
S		 3758 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3759 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3760}
3761
f1dc5600 3762void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
f078f209 3763{
f1dc5600 3764 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3765
f1dc5600 3766 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
f078f209
LR		 3767}
3768
f1dc5600 3769bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
f078f209 3770{
f1dc5600
S		 3771 struct ath_hal_5416 *ahp = AH5416(ah);
3772
3773 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
f078f209 3774
f1dc5600
S		 3775 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3776 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
f078f209
LR		 3777
3778 return true;
3779}
3780
f1dc5600 3781void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
f078f209 3782{
f1dc5600 3783 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3784
f1dc5600
S		 3785 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3786 ahp->ah_assocId = assocId;
f078f209 3787
f1dc5600
S		 3788 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3789 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3790 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 3791}
3792
f1dc5600 3793u64 ath9k_hw_gettsf64(struct ath_hal *ah)
f078f209 3794{
f1dc5600 3795 u64 tsf;
f078f209 3796
f1dc5600
S		 3797 tsf = REG_READ(ah, AR_TSF_U32);
3798 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3799
f1dc5600
S		 3800 return tsf;
3801}
f078f209 3802
f1dc5600
S		 3803void ath9k_hw_reset_tsf(struct ath_hal *ah)
3804{
3805 int count;
f078f209 3806
f1dc5600
S		 3807 count = 0;
3808 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3809 count++;
3810 if (count > 10) {
3811 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 3812 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f1dc5600 3813 break;
f078f209 3814 }
f1dc5600
S		 3815 udelay(10);
3816 }
3817 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3818}
f078f209 3819
f1dc5600
S		 3820bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3821{
3822 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3823
f1dc5600
S		 3824 if (setting)
3825 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3826 else
3827 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
f078f209 3828
f1dc5600
S		 3829 return true;
3830}
f078f209 3831
f1dc5600
S		 3832bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3833{
3834 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3835
f1dc5600 3836 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 3837 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
f1dc5600
S		 3838 ahp->ah_slottime = (u32) -1;
3839 return false;
3840 } else {
3841 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3842 ahp->ah_slottime = us;
3843 return true;
f078f209 3844 }
f1dc5600
S		 3845}
3846
3847void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3848{
3849 u32 macmode;
3850
3851 if (mode == ATH9K_HT_MACMODE_2040 &&
3852 !ah->ah_config.cwm_ignore_extcca)
3853 macmode = AR_2040_JOINED_RX_CLEAR;
3854 else
3855 macmode = 0;
f078f209 3856
f1dc5600 3857 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3858}
c97c92d9
VT		 3859
3860/***************************/
3861/* Bluetooth Coexistence */
3862/***************************/
3863
3864void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3865{
3866 /* connect bt_active to baseband */
3867 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3868 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3869 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3870
3871 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3872 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3873
3874 /* Set input mux for bt_active to gpio pin */
3875 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3876 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3877 ah->ah_btactive_gpio);
3878
3879 /* Configure the desired gpio port for input */
3880 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3881
3882 /* Configure the desired GPIO port for TX_FRAME output */
3883 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3884 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3885}
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