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Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <asm/unaligned.h> | |
19 | ||
394cf0a1 | 20 | #include "ath9k.h" |
f078f209 LR |
21 | #include "initvals.h" |
22 | ||
138ab2e4 VT |
23 | static int btcoex_enable; |
24 | module_param(btcoex_enable, bool, 0); | |
25 | MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support"); | |
26 | ||
4febf7b8 LR |
27 | #define ATH9K_CLOCK_RATE_CCK 22 |
28 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
29 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
f078f209 | 30 | |
cbe61d8a S |
31 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
32 | static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, | |
f1dc5600 | 33 | enum ath9k_ht_macmode macmode); |
cbe61d8a | 34 | static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, |
e7594072 | 35 | struct ar5416_eeprom_def *pEepData, |
f1dc5600 | 36 | u32 reg, u32 value); |
cbe61d8a S |
37 | static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); |
38 | static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); | |
f078f209 | 39 | |
f1dc5600 S |
40 | /********************/ |
41 | /* Helper Functions */ | |
42 | /********************/ | |
f078f209 | 43 | |
cbe61d8a | 44 | static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) |
f1dc5600 | 45 | { |
4febf7b8 | 46 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
cbe61d8a | 47 | |
2660b81a | 48 | if (!ah->curchan) /* should really check for CCK instead */ |
4febf7b8 LR |
49 | return clks / ATH9K_CLOCK_RATE_CCK; |
50 | if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
51 | return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
cbe61d8a | 52 | |
4febf7b8 | 53 | return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; |
f1dc5600 | 54 | } |
f078f209 | 55 | |
cbe61d8a | 56 | static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) |
f1dc5600 | 57 | { |
4febf7b8 | 58 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
cbe61d8a | 59 | |
4febf7b8 | 60 | if (conf_is_ht40(conf)) |
f1dc5600 S |
61 | return ath9k_hw_mac_usec(ah, clks) / 2; |
62 | else | |
63 | return ath9k_hw_mac_usec(ah, clks); | |
64 | } | |
f078f209 | 65 | |
cbe61d8a | 66 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 67 | { |
4febf7b8 | 68 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
cbe61d8a | 69 | |
2660b81a | 70 | if (!ah->curchan) /* should really check for CCK instead */ |
4febf7b8 LR |
71 | return usecs *ATH9K_CLOCK_RATE_CCK; |
72 | if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
73 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
74 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; | |
f1dc5600 S |
75 | } |
76 | ||
cbe61d8a | 77 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 78 | { |
4febf7b8 | 79 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
cbe61d8a | 80 | |
4febf7b8 | 81 | if (conf_is_ht40(conf)) |
f1dc5600 S |
82 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
83 | else | |
84 | return ath9k_hw_mac_clks(ah, usecs); | |
85 | } | |
f078f209 | 86 | |
0caa7b14 | 87 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
88 | { |
89 | int i; | |
90 | ||
0caa7b14 S |
91 | BUG_ON(timeout < AH_TIME_QUANTUM); |
92 | ||
93 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
94 | if ((REG_READ(ah, reg) & mask) == val) |
95 | return true; | |
96 | ||
97 | udelay(AH_TIME_QUANTUM); | |
98 | } | |
04bd4638 S |
99 | |
100 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
0caa7b14 S |
101 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
102 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 103 | |
f1dc5600 | 104 | return false; |
f078f209 LR |
105 | } |
106 | ||
107 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
108 | { | |
109 | u32 retval; | |
110 | int i; | |
111 | ||
112 | for (i = 0, retval = 0; i < n; i++) { | |
113 | retval = (retval << 1) | (val & 1); | |
114 | val >>= 1; | |
115 | } | |
116 | return retval; | |
117 | } | |
118 | ||
cbe61d8a | 119 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
f1dc5600 S |
120 | u16 flags, u16 *low, |
121 | u16 *high) | |
f078f209 | 122 | { |
2660b81a | 123 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 124 | |
f1dc5600 S |
125 | if (flags & CHANNEL_5GHZ) { |
126 | *low = pCap->low_5ghz_chan; | |
127 | *high = pCap->high_5ghz_chan; | |
128 | return true; | |
f078f209 | 129 | } |
f1dc5600 S |
130 | if ((flags & CHANNEL_2GHZ)) { |
131 | *low = pCap->low_2ghz_chan; | |
132 | *high = pCap->high_2ghz_chan; | |
133 | return true; | |
134 | } | |
135 | return false; | |
f078f209 LR |
136 | } |
137 | ||
cbe61d8a | 138 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
e63835b0 | 139 | struct ath_rate_table *rates, |
f1dc5600 S |
140 | u32 frameLen, u16 rateix, |
141 | bool shortPreamble) | |
f078f209 | 142 | { |
f1dc5600 S |
143 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
144 | u32 kbps; | |
f078f209 | 145 | |
e63835b0 | 146 | kbps = rates->info[rateix].ratekbps; |
f078f209 | 147 | |
f1dc5600 S |
148 | if (kbps == 0) |
149 | return 0; | |
f078f209 | 150 | |
f1dc5600 | 151 | switch (rates->info[rateix].phy) { |
46d14a58 | 152 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 153 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
e63835b0 | 154 | if (shortPreamble && rates->info[rateix].short_preamble) |
f1dc5600 S |
155 | phyTime >>= 1; |
156 | numBits = frameLen << 3; | |
157 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
158 | break; | |
46d14a58 | 159 | case WLAN_RC_PHY_OFDM: |
2660b81a | 160 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
161 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
162 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
163 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
164 | txTime = OFDM_SIFS_TIME_QUARTER | |
165 | + OFDM_PREAMBLE_TIME_QUARTER | |
166 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
167 | } else if (ah->curchan && |
168 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
169 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
170 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
171 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
172 | txTime = OFDM_SIFS_TIME_HALF + | |
173 | OFDM_PREAMBLE_TIME_HALF | |
174 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
175 | } else { | |
176 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
177 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
178 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
179 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
180 | + (numSymbols * OFDM_SYMBOL_TIME); | |
181 | } | |
182 | break; | |
183 | default: | |
04bd4638 S |
184 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, |
185 | "Unknown phy %u (rate ix %u)\n", | |
f1dc5600 S |
186 | rates->info[rateix].phy, rateix); |
187 | txTime = 0; | |
188 | break; | |
189 | } | |
f078f209 | 190 | |
f1dc5600 S |
191 | return txTime; |
192 | } | |
f078f209 | 193 | |
cbe61d8a | 194 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
195 | struct ath9k_channel *chan, |
196 | struct chan_centers *centers) | |
f078f209 | 197 | { |
f1dc5600 | 198 | int8_t extoff; |
f078f209 | 199 | |
f1dc5600 S |
200 | if (!IS_CHAN_HT40(chan)) { |
201 | centers->ctl_center = centers->ext_center = | |
202 | centers->synth_center = chan->channel; | |
203 | return; | |
f078f209 | 204 | } |
f078f209 | 205 | |
f1dc5600 S |
206 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
207 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
208 | centers->synth_center = | |
209 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
210 | extoff = 1; | |
211 | } else { | |
212 | centers->synth_center = | |
213 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
214 | extoff = -1; | |
215 | } | |
f078f209 | 216 | |
f1dc5600 S |
217 | centers->ctl_center = |
218 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
219 | centers->ext_center = | |
220 | centers->synth_center + (extoff * | |
2660b81a | 221 | ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? |
f1dc5600 | 222 | HT40_CHANNEL_CENTER_SHIFT : 15)); |
f078f209 LR |
223 | } |
224 | ||
f1dc5600 S |
225 | /******************/ |
226 | /* Chip Revisions */ | |
227 | /******************/ | |
228 | ||
cbe61d8a | 229 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 230 | { |
f1dc5600 | 231 | u32 val; |
f078f209 | 232 | |
f1dc5600 | 233 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 234 | |
f1dc5600 S |
235 | if (val == 0xFF) { |
236 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
237 | ah->hw_version.macVersion = |
238 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
239 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
2660b81a | 240 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
f1dc5600 S |
241 | } else { |
242 | if (!AR_SREV_9100(ah)) | |
d535a42a | 243 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 244 | |
d535a42a | 245 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 246 | |
d535a42a | 247 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 248 | ah->is_pciexpress = true; |
f1dc5600 | 249 | } |
f078f209 LR |
250 | } |
251 | ||
cbe61d8a | 252 | static int ath9k_hw_get_radiorev(struct ath_hw *ah) |
f078f209 | 253 | { |
f1dc5600 S |
254 | u32 val; |
255 | int i; | |
f078f209 | 256 | |
f1dc5600 | 257 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
f078f209 | 258 | |
f1dc5600 S |
259 | for (i = 0; i < 8; i++) |
260 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); | |
261 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; | |
262 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); | |
f078f209 | 263 | |
f1dc5600 | 264 | return ath9k_hw_reverse_bits(val, 8); |
f078f209 LR |
265 | } |
266 | ||
f1dc5600 S |
267 | /************************************/ |
268 | /* HW Attach, Detach, Init Routines */ | |
269 | /************************************/ | |
270 | ||
cbe61d8a | 271 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 272 | { |
feed029c | 273 | if (AR_SREV_9100(ah)) |
f1dc5600 | 274 | return; |
f078f209 | 275 | |
f1dc5600 S |
276 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
277 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
278 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
279 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
280 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
281 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
282 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
283 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
284 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 285 | |
f1dc5600 | 286 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
287 | } |
288 | ||
cbe61d8a | 289 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 290 | { |
f1dc5600 S |
291 | u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; |
292 | u32 regHold[2]; | |
293 | u32 patternData[4] = { 0x55555555, | |
294 | 0xaaaaaaaa, | |
295 | 0x66666666, | |
296 | 0x99999999 }; | |
297 | int i, j; | |
f078f209 | 298 | |
f1dc5600 S |
299 | for (i = 0; i < 2; i++) { |
300 | u32 addr = regAddr[i]; | |
301 | u32 wrData, rdData; | |
f078f209 | 302 | |
f1dc5600 S |
303 | regHold[i] = REG_READ(ah, addr); |
304 | for (j = 0; j < 0x100; j++) { | |
305 | wrData = (j << 16) | j; | |
306 | REG_WRITE(ah, addr, wrData); | |
307 | rdData = REG_READ(ah, addr); | |
308 | if (rdData != wrData) { | |
309 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
04bd4638 | 310 | "address test failed " |
f1dc5600 | 311 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
04bd4638 | 312 | addr, wrData, rdData); |
f1dc5600 S |
313 | return false; |
314 | } | |
315 | } | |
316 | for (j = 0; j < 4; j++) { | |
317 | wrData = patternData[j]; | |
318 | REG_WRITE(ah, addr, wrData); | |
319 | rdData = REG_READ(ah, addr); | |
320 | if (wrData != rdData) { | |
321 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
04bd4638 | 322 | "address test failed " |
f1dc5600 | 323 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
04bd4638 | 324 | addr, wrData, rdData); |
f1dc5600 S |
325 | return false; |
326 | } | |
f078f209 | 327 | } |
f1dc5600 | 328 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 329 | } |
f1dc5600 | 330 | udelay(100); |
cbe61d8a | 331 | |
f078f209 LR |
332 | return true; |
333 | } | |
334 | ||
f1dc5600 | 335 | static const char *ath9k_hw_devname(u16 devid) |
f078f209 | 336 | { |
f1dc5600 S |
337 | switch (devid) { |
338 | case AR5416_DEVID_PCI: | |
f1dc5600 | 339 | return "Atheros 5416"; |
392dff83 BP |
340 | case AR5416_DEVID_PCIE: |
341 | return "Atheros 5418"; | |
f1dc5600 S |
342 | case AR9160_DEVID_PCI: |
343 | return "Atheros 9160"; | |
0c1aa495 GJ |
344 | case AR5416_AR9100_DEVID: |
345 | return "Atheros 9100"; | |
f1dc5600 S |
346 | case AR9280_DEVID_PCI: |
347 | case AR9280_DEVID_PCIE: | |
348 | return "Atheros 9280"; | |
e7594072 SB |
349 | case AR9285_DEVID_PCIE: |
350 | return "Atheros 9285"; | |
f078f209 LR |
351 | } |
352 | ||
f1dc5600 S |
353 | return NULL; |
354 | } | |
f078f209 | 355 | |
cbe61d8a | 356 | static void ath9k_hw_set_defaults(struct ath_hw *ah) |
f1dc5600 S |
357 | { |
358 | int i; | |
f078f209 | 359 | |
2660b81a S |
360 | ah->config.dma_beacon_response_time = 2; |
361 | ah->config.sw_beacon_response_time = 10; | |
362 | ah->config.additional_swba_backoff = 0; | |
363 | ah->config.ack_6mb = 0x0; | |
364 | ah->config.cwm_ignore_extcca = 0; | |
365 | ah->config.pcie_powersave_enable = 0; | |
366 | ah->config.pcie_l1skp_enable = 0; | |
367 | ah->config.pcie_clock_req = 0; | |
368 | ah->config.pcie_power_reset = 0x100; | |
369 | ah->config.pcie_restore = 0; | |
370 | ah->config.pcie_waen = 0; | |
371 | ah->config.analog_shiftreg = 1; | |
372 | ah->config.ht_enable = 1; | |
373 | ah->config.ofdm_trig_low = 200; | |
374 | ah->config.ofdm_trig_high = 500; | |
375 | ah->config.cck_trig_high = 200; | |
376 | ah->config.cck_trig_low = 100; | |
377 | ah->config.enable_ani = 1; | |
378 | ah->config.noise_immunity_level = 4; | |
379 | ah->config.ofdm_weaksignal_det = 1; | |
380 | ah->config.cck_weaksignal_thr = 0; | |
381 | ah->config.spur_immunity_level = 2; | |
382 | ah->config.firstep_level = 0; | |
383 | ah->config.rssi_thr_high = 40; | |
384 | ah->config.rssi_thr_low = 7; | |
385 | ah->config.diversity_control = 0; | |
386 | ah->config.antenna_switch_swap = 0; | |
f078f209 | 387 | |
f1dc5600 | 388 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
389 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
390 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
391 | } |
392 | ||
2660b81a | 393 | ah->config.intr_mitigation = 1; |
6158425b LR |
394 | |
395 | /* | |
396 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
397 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
398 | * This means we use it for all AR5416 devices, and the few | |
399 | * minor PCI AR9280 devices out there. | |
400 | * | |
401 | * Serialization is required because these devices do not handle | |
402 | * well the case of two concurrent reads/writes due to the latency | |
403 | * involved. During one read/write another read/write can be issued | |
404 | * on another CPU while the previous read/write may still be working | |
405 | * on our hardware, if we hit this case the hardware poops in a loop. | |
406 | * We prevent this by serializing reads and writes. | |
407 | * | |
408 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
409 | * devices (legacy, 802.11abg). | |
410 | */ | |
411 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 412 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
413 | } |
414 | ||
cbe61d8a S |
415 | static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, |
416 | int *status) | |
f078f209 | 417 | { |
cbe61d8a | 418 | struct ath_hw *ah; |
f078f209 | 419 | |
cbe61d8a S |
420 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
421 | if (ah == NULL) { | |
f078f209 | 422 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 423 | "Cannot allocate memory for state block\n"); |
f078f209 LR |
424 | *status = -ENOMEM; |
425 | return NULL; | |
426 | } | |
427 | ||
f078f209 | 428 | ah->ah_sc = sc; |
d535a42a | 429 | ah->hw_version.magic = AR5416_MAGIC; |
d6bad496 | 430 | ah->regulatory.country_code = CTRY_DEFAULT; |
d535a42a S |
431 | ah->hw_version.devid = devid; |
432 | ah->hw_version.subvendorid = 0; | |
f078f209 LR |
433 | |
434 | ah->ah_flags = 0; | |
435 | if ((devid == AR5416_AR9100_DEVID)) | |
d535a42a | 436 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
f078f209 LR |
437 | if (!AR_SREV_9100(ah)) |
438 | ah->ah_flags = AH_USE_EEPROM; | |
439 | ||
d6bad496 S |
440 | ah->regulatory.power_limit = MAX_RATE_POWER; |
441 | ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; | |
2660b81a S |
442 | ah->atim_window = 0; |
443 | ah->diversity_control = ah->config.diversity_control; | |
444 | ah->antenna_switch_swap = | |
445 | ah->config.antenna_switch_swap; | |
446 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; | |
447 | ah->beacon_interval = 100; | |
448 | ah->enable_32kHz_clock = DONT_USE_32KHZ; | |
449 | ah->slottime = (u32) -1; | |
450 | ah->acktimeout = (u32) -1; | |
451 | ah->ctstimeout = (u32) -1; | |
452 | ah->globaltxtimeout = (u32) -1; | |
453 | ||
454 | ah->gbeacon_rate = 0; | |
f078f209 | 455 | |
cbe61d8a | 456 | return ah; |
f078f209 LR |
457 | } |
458 | ||
cbe61d8a | 459 | static int ath9k_hw_rfattach(struct ath_hw *ah) |
f078f209 | 460 | { |
f1dc5600 S |
461 | bool rfStatus = false; |
462 | int ecode = 0; | |
f078f209 | 463 | |
f1dc5600 S |
464 | rfStatus = ath9k_hw_init_rf(ah, &ecode); |
465 | if (!rfStatus) { | |
466 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
04bd4638 | 467 | "RF setup failed, status %u\n", ecode); |
f1dc5600 S |
468 | return ecode; |
469 | } | |
f078f209 | 470 | |
f1dc5600 | 471 | return 0; |
f078f209 LR |
472 | } |
473 | ||
cbe61d8a | 474 | static int ath9k_hw_rf_claim(struct ath_hw *ah) |
f078f209 | 475 | { |
f1dc5600 S |
476 | u32 val; |
477 | ||
478 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
479 | ||
480 | val = ath9k_hw_get_radiorev(ah); | |
481 | switch (val & AR_RADIO_SREV_MAJOR) { | |
482 | case 0: | |
483 | val = AR_RAD5133_SREV_MAJOR; | |
484 | break; | |
485 | case AR_RAD5133_SREV_MAJOR: | |
486 | case AR_RAD5122_SREV_MAJOR: | |
487 | case AR_RAD2133_SREV_MAJOR: | |
488 | case AR_RAD2122_SREV_MAJOR: | |
489 | break; | |
f078f209 | 490 | default: |
f1dc5600 | 491 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, |
04bd4638 | 492 | "5G Radio Chip Rev 0x%02X is not " |
f1dc5600 | 493 | "supported by this driver\n", |
d535a42a | 494 | ah->hw_version.analog5GhzRev); |
f1dc5600 | 495 | return -EOPNOTSUPP; |
f078f209 | 496 | } |
f078f209 | 497 | |
d535a42a | 498 | ah->hw_version.analog5GhzRev = val; |
f078f209 | 499 | |
f1dc5600 | 500 | return 0; |
f078f209 LR |
501 | } |
502 | ||
cbe61d8a | 503 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 LR |
504 | { |
505 | u32 sum; | |
506 | int i; | |
507 | u16 eeval; | |
f078f209 LR |
508 | |
509 | sum = 0; | |
510 | for (i = 0; i < 3; i++) { | |
f74df6fb | 511 | eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); |
f078f209 | 512 | sum += eeval; |
ba52da58 S |
513 | ah->macaddr[2 * i] = eeval >> 8; |
514 | ah->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 LR |
515 | } |
516 | if (sum == 0 || sum == 0xffff * 3) { | |
517 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 518 | "mac address read failed: %pM\n", |
ba52da58 | 519 | ah->macaddr); |
f078f209 LR |
520 | return -EADDRNOTAVAIL; |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
cbe61d8a | 526 | static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) |
9f804202 SB |
527 | { |
528 | u32 rxgain_type; | |
9f804202 | 529 | |
f74df6fb S |
530 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { |
531 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); | |
9f804202 SB |
532 | |
533 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) | |
2660b81a | 534 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
535 | ar9280Modes_backoff_13db_rxgain_9280_2, |
536 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); | |
537 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) | |
2660b81a | 538 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
539 | ar9280Modes_backoff_23db_rxgain_9280_2, |
540 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); | |
541 | else | |
2660b81a | 542 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
543 | ar9280Modes_original_rxgain_9280_2, |
544 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 545 | } else { |
2660b81a | 546 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
547 | ar9280Modes_original_rxgain_9280_2, |
548 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 549 | } |
9f804202 SB |
550 | } |
551 | ||
cbe61d8a | 552 | static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) |
9f804202 SB |
553 | { |
554 | u32 txgain_type; | |
9f804202 | 555 | |
f74df6fb S |
556 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { |
557 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); | |
9f804202 SB |
558 | |
559 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) | |
2660b81a | 560 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
561 | ar9280Modes_high_power_tx_gain_9280_2, |
562 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); | |
563 | else | |
2660b81a | 564 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
565 | ar9280Modes_original_tx_gain_9280_2, |
566 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 567 | } else { |
2660b81a | 568 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
569 | ar9280Modes_original_tx_gain_9280_2, |
570 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 571 | } |
9f804202 SB |
572 | } |
573 | ||
cbe61d8a | 574 | static int ath9k_hw_post_attach(struct ath_hw *ah) |
f078f209 | 575 | { |
f1dc5600 | 576 | int ecode; |
f078f209 | 577 | |
f1dc5600 S |
578 | if (!ath9k_hw_chip_test(ah)) { |
579 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
04bd4638 | 580 | "hardware self-test failed\n"); |
f1dc5600 | 581 | return -ENODEV; |
f078f209 | 582 | } |
f078f209 | 583 | |
f1dc5600 S |
584 | ecode = ath9k_hw_rf_claim(ah); |
585 | if (ecode != 0) | |
f078f209 | 586 | return ecode; |
f078f209 | 587 | |
f1dc5600 S |
588 | ecode = ath9k_hw_eeprom_attach(ah); |
589 | if (ecode != 0) | |
590 | return ecode; | |
7d01b221 S |
591 | |
592 | DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", | |
593 | ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); | |
594 | ||
f1dc5600 S |
595 | ecode = ath9k_hw_rfattach(ah); |
596 | if (ecode != 0) | |
597 | return ecode; | |
f078f209 | 598 | |
f1dc5600 S |
599 | if (!AR_SREV_9100(ah)) { |
600 | ath9k_hw_ani_setup(ah); | |
601 | ath9k_hw_ani_attach(ah); | |
f078f209 LR |
602 | } |
603 | ||
f078f209 LR |
604 | return 0; |
605 | } | |
606 | ||
cbe61d8a S |
607 | static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, |
608 | int *status) | |
f078f209 | 609 | { |
cbe61d8a | 610 | struct ath_hw *ah; |
f1dc5600 | 611 | int ecode; |
f6688cd8 | 612 | u32 i, j; |
f078f209 | 613 | |
cbe61d8a S |
614 | ah = ath9k_hw_newstate(devid, sc, status); |
615 | if (ah == NULL) | |
f1dc5600 | 616 | return NULL; |
f078f209 | 617 | |
f1dc5600 | 618 | ath9k_hw_set_defaults(ah); |
f078f209 | 619 | |
2660b81a S |
620 | if (ah->config.intr_mitigation != 0) |
621 | ah->intr_mitigation = true; | |
f078f209 | 622 | |
f1dc5600 | 623 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
cbe61d8a | 624 | DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); |
f1dc5600 S |
625 | ecode = -EIO; |
626 | goto bad; | |
627 | } | |
f078f209 | 628 | |
f1dc5600 | 629 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
cbe61d8a | 630 | DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); |
f1dc5600 S |
631 | ecode = -EIO; |
632 | goto bad; | |
633 | } | |
f078f209 | 634 | |
2660b81a | 635 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
2d6a5e95 DM |
636 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
637 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { | |
2660b81a | 638 | ah->config.serialize_regmode = |
f1dc5600 | 639 | SER_REG_MODE_ON; |
f078f209 | 640 | } else { |
2660b81a | 641 | ah->config.serialize_regmode = |
f1dc5600 | 642 | SER_REG_MODE_OFF; |
f078f209 LR |
643 | } |
644 | } | |
f078f209 | 645 | |
cbe61d8a | 646 | DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", |
2660b81a | 647 | ah->config.serialize_regmode); |
f078f209 | 648 | |
d535a42a S |
649 | if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && |
650 | (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && | |
651 | (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && | |
e7594072 | 652 | (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { |
cbe61d8a | 653 | DPRINTF(sc, ATH_DBG_RESET, |
04bd4638 | 654 | "Mac Chip Rev 0x%02x.%x is not supported by " |
d535a42a S |
655 | "this driver\n", ah->hw_version.macVersion, |
656 | ah->hw_version.macRev); | |
f1dc5600 S |
657 | ecode = -EOPNOTSUPP; |
658 | goto bad; | |
659 | } | |
f078f209 | 660 | |
f1dc5600 | 661 | if (AR_SREV_9100(ah)) { |
2660b81a S |
662 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
663 | ah->supp_cals = IQ_MISMATCH_CAL; | |
664 | ah->is_pciexpress = false; | |
f1dc5600 | 665 | } |
d535a42a | 666 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
f078f209 | 667 | |
f1dc5600 S |
668 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
669 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a S |
670 | ah->iq_caldata.calData = &iq_cal_single_sample; |
671 | ah->adcgain_caldata.calData = | |
f1dc5600 | 672 | &adc_gain_cal_single_sample; |
2660b81a | 673 | ah->adcdc_caldata.calData = |
f1dc5600 | 674 | &adc_dc_cal_single_sample; |
2660b81a | 675 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
676 | &adc_init_dc_cal; |
677 | } else { | |
2660b81a S |
678 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
679 | ah->adcgain_caldata.calData = | |
f1dc5600 | 680 | &adc_gain_cal_multi_sample; |
2660b81a | 681 | ah->adcdc_caldata.calData = |
f1dc5600 | 682 | &adc_dc_cal_multi_sample; |
2660b81a | 683 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
684 | &adc_init_dc_cal; |
685 | } | |
2660b81a | 686 | ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; |
f1dc5600 | 687 | } |
f078f209 | 688 | |
9c81e8be S |
689 | ah->ani_function = ATH9K_ANI_ALL; |
690 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
691 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; | |
f078f209 | 692 | |
cbe61d8a | 693 | DPRINTF(sc, ATH_DBG_RESET, |
04bd4638 | 694 | "This Mac Chip Rev 0x%02x.%x is \n", |
d535a42a | 695 | ah->hw_version.macVersion, ah->hw_version.macRev); |
f078f209 | 696 | |
e7594072 | 697 | if (AR_SREV_9285_12_OR_LATER(ah)) { |
4e845168 | 698 | |
2660b81a | 699 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
e7594072 | 700 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
2660b81a | 701 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
e7594072 SB |
702 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
703 | ||
2660b81a S |
704 | if (ah->config.pcie_clock_req) { |
705 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
706 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
707 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); | |
708 | } else { | |
2660b81a | 709 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
710 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
711 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), | |
712 | 2); | |
713 | } | |
714 | } else if (AR_SREV_9285_10_OR_LATER(ah)) { | |
2660b81a | 715 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, |
e7594072 | 716 | ARRAY_SIZE(ar9285Modes_9285), 6); |
2660b81a | 717 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, |
e7594072 SB |
718 | ARRAY_SIZE(ar9285Common_9285), 2); |
719 | ||
2660b81a S |
720 | if (ah->config.pcie_clock_req) { |
721 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
722 | ar9285PciePhy_clkreq_off_L1_9285, |
723 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); | |
724 | } else { | |
2660b81a | 725 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
726 | ar9285PciePhy_clkreq_always_on_L1_9285, |
727 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); | |
728 | } | |
729 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2660b81a | 730 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
f1dc5600 | 731 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
2660b81a | 732 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
f1dc5600 | 733 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
f078f209 | 734 | |
2660b81a S |
735 | if (ah->config.pcie_clock_req) { |
736 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
f1dc5600 S |
737 | ar9280PciePhy_clkreq_off_L1_9280, |
738 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); | |
739 | } else { | |
2660b81a | 740 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
f1dc5600 S |
741 | ar9280PciePhy_clkreq_always_on_L1_9280, |
742 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | |
743 | } | |
2660b81a | 744 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
f1dc5600 S |
745 | ar9280Modes_fast_clock_9280_2, |
746 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | |
747 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a | 748 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, |
f1dc5600 | 749 | ARRAY_SIZE(ar9280Modes_9280), 6); |
2660b81a | 750 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, |
f1dc5600 S |
751 | ARRAY_SIZE(ar9280Common_9280), 2); |
752 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
2660b81a | 753 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
f1dc5600 | 754 | ARRAY_SIZE(ar5416Modes_9160), 6); |
2660b81a | 755 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
f1dc5600 | 756 | ARRAY_SIZE(ar5416Common_9160), 2); |
2660b81a | 757 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
f1dc5600 | 758 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
2660b81a | 759 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
f1dc5600 | 760 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
2660b81a | 761 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
f1dc5600 | 762 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
2660b81a | 763 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
f1dc5600 | 764 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
2660b81a | 765 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
f1dc5600 | 766 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
2660b81a | 767 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
f1dc5600 | 768 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
2660b81a | 769 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
f1dc5600 | 770 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
2660b81a | 771 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
f1dc5600 S |
772 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
773 | if (AR_SREV_9160_11(ah)) { | |
2660b81a | 774 | INIT_INI_ARRAY(&ah->iniAddac, |
f1dc5600 S |
775 | ar5416Addac_91601_1, |
776 | ARRAY_SIZE(ar5416Addac_91601_1), 2); | |
777 | } else { | |
2660b81a | 778 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
f1dc5600 S |
779 | ARRAY_SIZE(ar5416Addac_9160), 2); |
780 | } | |
781 | } else if (AR_SREV_9100_OR_LATER(ah)) { | |
2660b81a | 782 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
f1dc5600 | 783 | ARRAY_SIZE(ar5416Modes_9100), 6); |
2660b81a | 784 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
f1dc5600 | 785 | ARRAY_SIZE(ar5416Common_9100), 2); |
2660b81a | 786 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
f1dc5600 | 787 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
2660b81a | 788 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
f1dc5600 | 789 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
2660b81a | 790 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
f1dc5600 | 791 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
2660b81a | 792 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
f1dc5600 | 793 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
2660b81a | 794 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
f1dc5600 | 795 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
2660b81a | 796 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
f1dc5600 | 797 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
2660b81a | 798 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
f1dc5600 | 799 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
2660b81a | 800 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
f1dc5600 | 801 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
2660b81a | 802 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
f1dc5600 S |
803 | ARRAY_SIZE(ar5416Addac_9100), 2); |
804 | } else { | |
2660b81a | 805 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
f1dc5600 | 806 | ARRAY_SIZE(ar5416Modes), 6); |
2660b81a | 807 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
f1dc5600 | 808 | ARRAY_SIZE(ar5416Common), 2); |
2660b81a | 809 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
f1dc5600 | 810 | ARRAY_SIZE(ar5416Bank0), 2); |
2660b81a | 811 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
f1dc5600 | 812 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
2660b81a | 813 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
f1dc5600 | 814 | ARRAY_SIZE(ar5416Bank1), 2); |
2660b81a | 815 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
f1dc5600 | 816 | ARRAY_SIZE(ar5416Bank2), 2); |
2660b81a | 817 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
f1dc5600 | 818 | ARRAY_SIZE(ar5416Bank3), 3); |
2660b81a | 819 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
f1dc5600 | 820 | ARRAY_SIZE(ar5416Bank6), 3); |
2660b81a | 821 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
f1dc5600 | 822 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
2660b81a | 823 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
f1dc5600 | 824 | ARRAY_SIZE(ar5416Bank7), 2); |
2660b81a | 825 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
f1dc5600 | 826 | ARRAY_SIZE(ar5416Addac), 2); |
f078f209 | 827 | } |
f078f209 | 828 | |
2660b81a | 829 | if (ah->is_pciexpress) |
f1dc5600 S |
830 | ath9k_hw_configpcipowersave(ah, 0); |
831 | else | |
832 | ath9k_hw_disablepcie(ah); | |
f078f209 | 833 | |
f1dc5600 S |
834 | ecode = ath9k_hw_post_attach(ah); |
835 | if (ecode != 0) | |
836 | goto bad; | |
f078f209 | 837 | |
4e845168 SB |
838 | if (AR_SREV_9285_12_OR_LATER(ah)) { |
839 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); | |
840 | ||
841 | /* txgain table */ | |
842 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { | |
843 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
844 | ar9285Modes_high_power_tx_gain_9285_1_2, | |
845 | ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6); | |
846 | } else { | |
847 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
848 | ar9285Modes_original_tx_gain_9285_1_2, | |
849 | ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6); | |
850 | } | |
851 | ||
852 | } | |
853 | ||
9f804202 | 854 | /* rxgain table */ |
e7594072 | 855 | if (AR_SREV_9280_20(ah)) |
9f804202 SB |
856 | ath9k_hw_init_rxgain_ini(ah); |
857 | ||
858 | /* txgain table */ | |
e7594072 | 859 | if (AR_SREV_9280_20(ah)) |
9f804202 SB |
860 | ath9k_hw_init_txgain_ini(ah); |
861 | ||
06d0f066 S |
862 | if (!ath9k_hw_fill_cap_info(ah)) { |
863 | DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n"); | |
864 | ecode = -EINVAL; | |
865 | goto bad; | |
866 | } | |
867 | ||
868 | if ((ah->hw_version.devid == AR9280_DEVID_PCI) && | |
869 | test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) { | |
870 | ||
871 | /* EEPROM Fixup */ | |
2660b81a S |
872 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
873 | u32 reg = INI_RA(&ah->iniModes, i, 0); | |
f078f209 | 874 | |
2660b81a S |
875 | for (j = 1; j < ah->iniModes.ia_columns; j++) { |
876 | u32 val = INI_RA(&ah->iniModes, i, j); | |
f078f209 | 877 | |
2660b81a | 878 | INI_RA(&ah->iniModes, i, j) = |
e7594072 | 879 | ath9k_hw_ini_fixup(ah, |
2660b81a | 880 | &ah->eeprom.def, |
f1dc5600 S |
881 | reg, val); |
882 | } | |
f078f209 | 883 | } |
f1dc5600 | 884 | } |
f6688cd8 | 885 | |
f1dc5600 S |
886 | ecode = ath9k_hw_init_macaddr(ah); |
887 | if (ecode != 0) { | |
cbe61d8a | 888 | DPRINTF(sc, ATH_DBG_RESET, |
04bd4638 | 889 | "failed initializing mac address\n"); |
f1dc5600 | 890 | goto bad; |
f078f209 LR |
891 | } |
892 | ||
f1dc5600 | 893 | if (AR_SREV_9285(ah)) |
2660b81a | 894 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 895 | else |
2660b81a | 896 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 897 | |
f1dc5600 | 898 | ath9k_init_nfcal_hist_buffer(ah); |
f078f209 | 899 | |
f1dc5600 S |
900 | return ah; |
901 | bad: | |
cbe61d8a S |
902 | if (ah) |
903 | ath9k_hw_detach(ah); | |
f1dc5600 S |
904 | if (status) |
905 | *status = ecode; | |
f078f209 | 906 | |
f1dc5600 | 907 | return NULL; |
f078f209 LR |
908 | } |
909 | ||
cbe61d8a | 910 | static void ath9k_hw_init_bb(struct ath_hw *ah, |
f1dc5600 | 911 | struct ath9k_channel *chan) |
f078f209 | 912 | { |
f1dc5600 | 913 | u32 synthDelay; |
f078f209 | 914 | |
f1dc5600 | 915 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
788a3d6f | 916 | if (IS_CHAN_B(chan)) |
f1dc5600 S |
917 | synthDelay = (4 * synthDelay) / 22; |
918 | else | |
919 | synthDelay /= 10; | |
f078f209 | 920 | |
f1dc5600 | 921 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
f078f209 | 922 | |
f1dc5600 | 923 | udelay(synthDelay + BASE_ACTIVATE_DELAY); |
f078f209 LR |
924 | } |
925 | ||
cbe61d8a | 926 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 927 | { |
f1dc5600 S |
928 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
929 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 930 | |
f1dc5600 S |
931 | REG_WRITE(ah, AR_QOS_NO_ACK, |
932 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
933 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
934 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
935 | ||
936 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
937 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
938 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
939 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
940 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
f078f209 LR |
941 | } |
942 | ||
cbe61d8a | 943 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 944 | struct ath9k_channel *chan) |
f078f209 | 945 | { |
f1dc5600 | 946 | u32 pll; |
f078f209 | 947 | |
f1dc5600 S |
948 | if (AR_SREV_9100(ah)) { |
949 | if (chan && IS_CHAN_5GHZ(chan)) | |
950 | pll = 0x1450; | |
f078f209 | 951 | else |
f1dc5600 S |
952 | pll = 0x1458; |
953 | } else { | |
954 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
955 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | |
f078f209 | 956 | |
f1dc5600 S |
957 | if (chan && IS_CHAN_HALF_RATE(chan)) |
958 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
959 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
960 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 961 | |
f1dc5600 S |
962 | if (chan && IS_CHAN_5GHZ(chan)) { |
963 | pll |= SM(0x28, AR_RTC_9160_PLL_DIV); | |
f078f209 | 964 | |
f078f209 | 965 | |
f1dc5600 S |
966 | if (AR_SREV_9280_20(ah)) { |
967 | if (((chan->channel % 20) == 0) | |
968 | || ((chan->channel % 10) == 0)) | |
969 | pll = 0x2850; | |
970 | else | |
971 | pll = 0x142c; | |
972 | } | |
973 | } else { | |
974 | pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); | |
975 | } | |
f078f209 | 976 | |
f1dc5600 | 977 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
f078f209 | 978 | |
f1dc5600 | 979 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); |
f078f209 | 980 | |
f1dc5600 S |
981 | if (chan && IS_CHAN_HALF_RATE(chan)) |
982 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
983 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
984 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 985 | |
f1dc5600 S |
986 | if (chan && IS_CHAN_5GHZ(chan)) |
987 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | |
988 | else | |
989 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | |
990 | } else { | |
991 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | |
f078f209 | 992 | |
f1dc5600 S |
993 | if (chan && IS_CHAN_HALF_RATE(chan)) |
994 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | |
995 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
996 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | |
f078f209 | 997 | |
f1dc5600 S |
998 | if (chan && IS_CHAN_5GHZ(chan)) |
999 | pll |= SM(0xa, AR_RTC_PLL_DIV); | |
1000 | else | |
1001 | pll |= SM(0xb, AR_RTC_PLL_DIV); | |
1002 | } | |
1003 | } | |
d03a66c1 | 1004 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 1005 | |
f1dc5600 S |
1006 | udelay(RTC_PLL_SETTLE_DELAY); |
1007 | ||
1008 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
1009 | } |
1010 | ||
cbe61d8a | 1011 | static void ath9k_hw_init_chain_masks(struct ath_hw *ah) |
f078f209 | 1012 | { |
f078f209 LR |
1013 | int rx_chainmask, tx_chainmask; |
1014 | ||
2660b81a S |
1015 | rx_chainmask = ah->rxchainmask; |
1016 | tx_chainmask = ah->txchainmask; | |
f078f209 LR |
1017 | |
1018 | switch (rx_chainmask) { | |
1019 | case 0x5: | |
1020 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
1021 | AR_PHY_SWAP_ALT_CHAIN); | |
1022 | case 0x3: | |
d535a42a | 1023 | if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) { |
f078f209 LR |
1024 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); |
1025 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); | |
1026 | break; | |
1027 | } | |
1028 | case 0x1: | |
1029 | case 0x2: | |
f078f209 LR |
1030 | case 0x7: |
1031 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
1032 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
1033 | break; | |
1034 | default: | |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); | |
1039 | if (tx_chainmask == 0x5) { | |
1040 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
1041 | AR_PHY_SWAP_ALT_CHAIN); | |
1042 | } | |
1043 | if (AR_SREV_9100(ah)) | |
1044 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, | |
1045 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); | |
1046 | } | |
1047 | ||
cbe61d8a | 1048 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 1049 | enum nl80211_iftype opmode) |
f078f209 | 1050 | { |
2660b81a | 1051 | ah->mask_reg = AR_IMR_TXERR | |
f1dc5600 S |
1052 | AR_IMR_TXURN | |
1053 | AR_IMR_RXERR | | |
1054 | AR_IMR_RXORN | | |
1055 | AR_IMR_BCNMISC; | |
f078f209 | 1056 | |
2660b81a S |
1057 | if (ah->intr_mitigation) |
1058 | ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
f078f209 | 1059 | else |
2660b81a | 1060 | ah->mask_reg |= AR_IMR_RXOK; |
f078f209 | 1061 | |
2660b81a | 1062 | ah->mask_reg |= AR_IMR_TXOK; |
f078f209 | 1063 | |
d97809db | 1064 | if (opmode == NL80211_IFTYPE_AP) |
2660b81a | 1065 | ah->mask_reg |= AR_IMR_MIB; |
f078f209 | 1066 | |
2660b81a | 1067 | REG_WRITE(ah, AR_IMR, ah->mask_reg); |
f1dc5600 | 1068 | REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); |
f078f209 | 1069 | |
f1dc5600 S |
1070 | if (!AR_SREV_9100(ah)) { |
1071 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
1072 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
1073 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
1074 | } | |
f078f209 LR |
1075 | } |
1076 | ||
cbe61d8a | 1077 | static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 1078 | { |
f078f209 | 1079 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { |
04bd4638 | 1080 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); |
2660b81a | 1081 | ah->acktimeout = (u32) -1; |
f078f209 LR |
1082 | return false; |
1083 | } else { | |
1084 | REG_RMW_FIELD(ah, AR_TIME_OUT, | |
1085 | AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); | |
2660b81a | 1086 | ah->acktimeout = us; |
f078f209 LR |
1087 | return true; |
1088 | } | |
1089 | } | |
1090 | ||
cbe61d8a | 1091 | static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 1092 | { |
f078f209 | 1093 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { |
04bd4638 | 1094 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); |
2660b81a | 1095 | ah->ctstimeout = (u32) -1; |
f078f209 LR |
1096 | return false; |
1097 | } else { | |
1098 | REG_RMW_FIELD(ah, AR_TIME_OUT, | |
1099 | AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); | |
2660b81a | 1100 | ah->ctstimeout = us; |
f078f209 LR |
1101 | return true; |
1102 | } | |
1103 | } | |
f1dc5600 | 1104 | |
cbe61d8a | 1105 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 1106 | { |
f078f209 LR |
1107 | if (tu > 0xFFFF) { |
1108 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | |
04bd4638 | 1109 | "bad global tx timeout %u\n", tu); |
2660b81a | 1110 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
1111 | return false; |
1112 | } else { | |
1113 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 1114 | ah->globaltxtimeout = tu; |
f078f209 LR |
1115 | return true; |
1116 | } | |
1117 | } | |
1118 | ||
cbe61d8a | 1119 | static void ath9k_hw_init_user_settings(struct ath_hw *ah) |
f078f209 | 1120 | { |
2660b81a S |
1121 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
1122 | ah->misc_mode); | |
f078f209 | 1123 | |
2660b81a | 1124 | if (ah->misc_mode != 0) |
f1dc5600 | 1125 | REG_WRITE(ah, AR_PCU_MISC, |
2660b81a S |
1126 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
1127 | if (ah->slottime != (u32) -1) | |
1128 | ath9k_hw_setslottime(ah, ah->slottime); | |
1129 | if (ah->acktimeout != (u32) -1) | |
1130 | ath9k_hw_set_ack_timeout(ah, ah->acktimeout); | |
1131 | if (ah->ctstimeout != (u32) -1) | |
1132 | ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); | |
1133 | if (ah->globaltxtimeout != (u32) -1) | |
1134 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
f1dc5600 S |
1135 | } |
1136 | ||
1137 | const char *ath9k_hw_probe(u16 vendorid, u16 devid) | |
1138 | { | |
1139 | return vendorid == ATHEROS_VENDOR_ID ? | |
1140 | ath9k_hw_devname(devid) : NULL; | |
1141 | } | |
1142 | ||
cbe61d8a | 1143 | void ath9k_hw_detach(struct ath_hw *ah) |
f1dc5600 S |
1144 | { |
1145 | if (!AR_SREV_9100(ah)) | |
1146 | ath9k_hw_ani_detach(ah); | |
1147 | ||
1148 | ath9k_hw_rfdetach(ah); | |
1149 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | |
1150 | kfree(ah); | |
1151 | } | |
1152 | ||
cbe61d8a | 1153 | struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error) |
f1dc5600 | 1154 | { |
cbe61d8a | 1155 | struct ath_hw *ah = NULL; |
f1dc5600 S |
1156 | |
1157 | switch (devid) { | |
1158 | case AR5416_DEVID_PCI: | |
1159 | case AR5416_DEVID_PCIE: | |
0c1aa495 | 1160 | case AR5416_AR9100_DEVID: |
f1dc5600 S |
1161 | case AR9160_DEVID_PCI: |
1162 | case AR9280_DEVID_PCI: | |
1163 | case AR9280_DEVID_PCIE: | |
e7594072 | 1164 | case AR9285_DEVID_PCIE: |
cbe61d8a | 1165 | ah = ath9k_hw_do_attach(devid, sc, error); |
f1dc5600 S |
1166 | break; |
1167 | default: | |
f1dc5600 S |
1168 | *error = -ENXIO; |
1169 | break; | |
f078f209 | 1170 | } |
f1dc5600 S |
1171 | |
1172 | return ah; | |
1173 | } | |
1174 | ||
1175 | /*******/ | |
1176 | /* INI */ | |
1177 | /*******/ | |
1178 | ||
cbe61d8a | 1179 | static void ath9k_hw_override_ini(struct ath_hw *ah, |
f1dc5600 S |
1180 | struct ath9k_channel *chan) |
1181 | { | |
8aa15e15 SB |
1182 | /* |
1183 | * Set the RX_ABORT and RX_DIS and clear if off only after | |
1184 | * RXE is set for MAC. This prevents frames with corrupted | |
1185 | * descriptor status. | |
1186 | */ | |
1187 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | |
1188 | ||
1189 | ||
a8c96d3b | 1190 | if (!AR_SREV_5416_20_OR_LATER(ah) || |
f1dc5600 S |
1191 | AR_SREV_9280_10_OR_LATER(ah)) |
1192 | return; | |
1193 | ||
1194 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); | |
f078f209 LR |
1195 | } |
1196 | ||
cbe61d8a | 1197 | static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, |
e7594072 | 1198 | struct ar5416_eeprom_def *pEepData, |
f1dc5600 | 1199 | u32 reg, u32 value) |
f078f209 | 1200 | { |
f1dc5600 | 1201 | struct base_eep_header *pBase = &(pEepData->baseEepHeader); |
f078f209 | 1202 | |
d535a42a | 1203 | switch (ah->hw_version.devid) { |
f1dc5600 S |
1204 | case AR9280_DEVID_PCI: |
1205 | if (reg == 0x7894) { | |
1206 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1207 | "ini VAL: %x EEPROM: %x\n", value, | |
1208 | (pBase->version & 0xff)); | |
1209 | ||
1210 | if ((pBase->version & 0xff) > 0x0a) { | |
1211 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1212 | "PWDCLKIND: %d\n", | |
1213 | pBase->pwdclkind); | |
1214 | value &= ~AR_AN_TOP2_PWDCLKIND; | |
1215 | value |= AR_AN_TOP2_PWDCLKIND & | |
1216 | (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); | |
1217 | } else { | |
1218 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1219 | "PWDCLKIND Earlier Rev\n"); | |
1220 | } | |
1221 | ||
1222 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1223 | "final ini VAL: %x\n", value); | |
1224 | } | |
1225 | break; | |
1226 | } | |
1227 | ||
1228 | return value; | |
f078f209 LR |
1229 | } |
1230 | ||
cbe61d8a | 1231 | static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, |
e7594072 SB |
1232 | struct ar5416_eeprom_def *pEepData, |
1233 | u32 reg, u32 value) | |
1234 | { | |
2660b81a | 1235 | if (ah->eep_map == EEP_MAP_4KBITS) |
e7594072 SB |
1236 | return value; |
1237 | else | |
1238 | return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); | |
1239 | } | |
1240 | ||
8bd1d07f SB |
1241 | static void ath9k_olc_init(struct ath_hw *ah) |
1242 | { | |
1243 | u32 i; | |
1244 | ||
1245 | for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) | |
1246 | ah->originalGain[i] = | |
1247 | MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), | |
1248 | AR_PHY_TX_GAIN); | |
1249 | ah->PDADCdelta = 0; | |
1250 | } | |
1251 | ||
cbe61d8a | 1252 | static int ath9k_hw_process_ini(struct ath_hw *ah, |
f1dc5600 S |
1253 | struct ath9k_channel *chan, |
1254 | enum ath9k_ht_macmode macmode) | |
f078f209 LR |
1255 | { |
1256 | int i, regWrites = 0; | |
5f8e077c | 1257 | struct ieee80211_channel *channel = chan->chan; |
f078f209 LR |
1258 | u32 modesIndex, freqIndex; |
1259 | int status; | |
1260 | ||
1261 | switch (chan->chanmode) { | |
1262 | case CHANNEL_A: | |
1263 | case CHANNEL_A_HT20: | |
1264 | modesIndex = 1; | |
1265 | freqIndex = 1; | |
1266 | break; | |
1267 | case CHANNEL_A_HT40PLUS: | |
1268 | case CHANNEL_A_HT40MINUS: | |
1269 | modesIndex = 2; | |
1270 | freqIndex = 1; | |
1271 | break; | |
1272 | case CHANNEL_G: | |
1273 | case CHANNEL_G_HT20: | |
1274 | case CHANNEL_B: | |
1275 | modesIndex = 4; | |
1276 | freqIndex = 2; | |
1277 | break; | |
1278 | case CHANNEL_G_HT40PLUS: | |
1279 | case CHANNEL_G_HT40MINUS: | |
1280 | modesIndex = 3; | |
1281 | freqIndex = 2; | |
1282 | break; | |
1283 | ||
1284 | default: | |
1285 | return -EINVAL; | |
1286 | } | |
1287 | ||
1288 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
f078f209 | 1289 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); |
f74df6fb | 1290 | ah->eep_ops->set_addac(ah, chan); |
f078f209 | 1291 | |
a8c96d3b | 1292 | if (AR_SREV_5416_22_OR_LATER(ah)) { |
2660b81a | 1293 | REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); |
f078f209 LR |
1294 | } else { |
1295 | struct ar5416IniArray temp; | |
1296 | u32 addacSize = | |
2660b81a S |
1297 | sizeof(u32) * ah->iniAddac.ia_rows * |
1298 | ah->iniAddac.ia_columns; | |
f078f209 | 1299 | |
2660b81a S |
1300 | memcpy(ah->addac5416_21, |
1301 | ah->iniAddac.ia_array, addacSize); | |
f078f209 | 1302 | |
2660b81a | 1303 | (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; |
f078f209 | 1304 | |
2660b81a S |
1305 | temp.ia_array = ah->addac5416_21; |
1306 | temp.ia_columns = ah->iniAddac.ia_columns; | |
1307 | temp.ia_rows = ah->iniAddac.ia_rows; | |
f078f209 LR |
1308 | REG_WRITE_ARRAY(&temp, 1, regWrites); |
1309 | } | |
f1dc5600 | 1310 | |
f078f209 LR |
1311 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); |
1312 | ||
2660b81a S |
1313 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
1314 | u32 reg = INI_RA(&ah->iniModes, i, 0); | |
1315 | u32 val = INI_RA(&ah->iniModes, i, modesIndex); | |
f078f209 | 1316 | |
f078f209 LR |
1317 | REG_WRITE(ah, reg, val); |
1318 | ||
1319 | if (reg >= 0x7800 && reg < 0x78a0 | |
2660b81a | 1320 | && ah->config.analog_shiftreg) { |
f078f209 LR |
1321 | udelay(100); |
1322 | } | |
1323 | ||
1324 | DO_DELAY(regWrites); | |
1325 | } | |
1326 | ||
e7594072 | 1327 | if (AR_SREV_9280(ah)) |
2660b81a | 1328 | REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); |
9f804202 | 1329 | |
4e845168 SB |
1330 | if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) && |
1331 | AR_SREV_9285_12_OR_LATER(ah))) | |
2660b81a | 1332 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); |
9f804202 | 1333 | |
2660b81a S |
1334 | for (i = 0; i < ah->iniCommon.ia_rows; i++) { |
1335 | u32 reg = INI_RA(&ah->iniCommon, i, 0); | |
1336 | u32 val = INI_RA(&ah->iniCommon, i, 1); | |
f078f209 LR |
1337 | |
1338 | REG_WRITE(ah, reg, val); | |
1339 | ||
1340 | if (reg >= 0x7800 && reg < 0x78a0 | |
2660b81a | 1341 | && ah->config.analog_shiftreg) { |
f078f209 LR |
1342 | udelay(100); |
1343 | } | |
1344 | ||
1345 | DO_DELAY(regWrites); | |
1346 | } | |
1347 | ||
1348 | ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); | |
1349 | ||
1350 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { | |
2660b81a | 1351 | REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, |
f078f209 LR |
1352 | regWrites); |
1353 | } | |
1354 | ||
1355 | ath9k_hw_override_ini(ah, chan); | |
1356 | ath9k_hw_set_regs(ah, chan, macmode); | |
1357 | ath9k_hw_init_chain_masks(ah); | |
1358 | ||
8bd1d07f SB |
1359 | if (OLC_FOR_AR9280_20_LATER) |
1360 | ath9k_olc_init(ah); | |
1361 | ||
f74df6fb S |
1362 | status = ah->eep_ops->set_txpower(ah, chan, |
1363 | ath9k_regd_get_ctl(ah, chan), | |
1364 | channel->max_antenna_gain * 2, | |
1365 | channel->max_power * 2, | |
1366 | min((u32) MAX_RATE_POWER, | |
1367 | (u32) ah->regulatory.power_limit)); | |
f078f209 LR |
1368 | if (status != 0) { |
1369 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
04bd4638 | 1370 | "error init'ing transmit power\n"); |
f078f209 LR |
1371 | return -EIO; |
1372 | } | |
1373 | ||
1374 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { | |
1375 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
04bd4638 | 1376 | "ar5416SetRfRegs failed\n"); |
f078f209 LR |
1377 | return -EIO; |
1378 | } | |
1379 | ||
1380 | return 0; | |
1381 | } | |
1382 | ||
f1dc5600 S |
1383 | /****************************************/ |
1384 | /* Reset and Channel Switching Routines */ | |
1385 | /****************************************/ | |
1386 | ||
cbe61d8a | 1387 | static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) |
f078f209 | 1388 | { |
f1dc5600 S |
1389 | u32 rfMode = 0; |
1390 | ||
1391 | if (chan == NULL) | |
1392 | return; | |
1393 | ||
1394 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | |
1395 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | |
1396 | ||
1397 | if (!AR_SREV_9280_10_OR_LATER(ah)) | |
1398 | rfMode |= (IS_CHAN_5GHZ(chan)) ? | |
1399 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; | |
1400 | ||
1401 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) | |
1402 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); | |
1403 | ||
1404 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | |
1405 | } | |
1406 | ||
cbe61d8a | 1407 | static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) |
f1dc5600 S |
1408 | { |
1409 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | |
1410 | } | |
1411 | ||
cbe61d8a | 1412 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 S |
1413 | { |
1414 | u32 regval; | |
1415 | ||
1416 | regval = REG_READ(ah, AR_AHB_MODE); | |
1417 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
1418 | ||
1419 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; | |
1420 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
1421 | ||
2660b81a | 1422 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
f1dc5600 S |
1423 | |
1424 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; | |
1425 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
1426 | ||
1427 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); | |
1428 | ||
1429 | if (AR_SREV_9285(ah)) { | |
1430 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | |
1431 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1432 | } else { | |
1433 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | |
1434 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1435 | } | |
1436 | } | |
1437 | ||
cbe61d8a | 1438 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 S |
1439 | { |
1440 | u32 val; | |
1441 | ||
1442 | val = REG_READ(ah, AR_STA_ID1); | |
1443 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
1444 | switch (opmode) { | |
d97809db | 1445 | case NL80211_IFTYPE_AP: |
f1dc5600 S |
1446 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
1447 | | AR_STA_ID1_KSRCH_MODE); | |
1448 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1449 | break; |
d97809db | 1450 | case NL80211_IFTYPE_ADHOC: |
f1dc5600 S |
1451 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
1452 | | AR_STA_ID1_KSRCH_MODE); | |
1453 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1454 | break; |
d97809db CM |
1455 | case NL80211_IFTYPE_STATION: |
1456 | case NL80211_IFTYPE_MONITOR: | |
f1dc5600 | 1457 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
f078f209 | 1458 | break; |
f1dc5600 S |
1459 | } |
1460 | } | |
1461 | ||
cbe61d8a | 1462 | static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, |
f1dc5600 S |
1463 | u32 coef_scaled, |
1464 | u32 *coef_mantissa, | |
1465 | u32 *coef_exponent) | |
1466 | { | |
1467 | u32 coef_exp, coef_man; | |
1468 | ||
1469 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1470 | if ((coef_scaled >> coef_exp) & 0x1) | |
1471 | break; | |
1472 | ||
1473 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1474 | ||
1475 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1476 | ||
1477 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1478 | *coef_exponent = coef_exp - 16; | |
1479 | } | |
1480 | ||
cbe61d8a | 1481 | static void ath9k_hw_set_delta_slope(struct ath_hw *ah, |
f1dc5600 S |
1482 | struct ath9k_channel *chan) |
1483 | { | |
1484 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | |
1485 | u32 clockMhzScaled = 0x64000000; | |
1486 | struct chan_centers centers; | |
1487 | ||
1488 | if (IS_CHAN_HALF_RATE(chan)) | |
1489 | clockMhzScaled = clockMhzScaled >> 1; | |
1490 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
1491 | clockMhzScaled = clockMhzScaled >> 2; | |
1492 | ||
1493 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1494 | coef_scaled = clockMhzScaled / centers.synth_center; | |
1495 | ||
1496 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
1497 | &ds_coef_exp); | |
1498 | ||
1499 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
1500 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | |
1501 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
1502 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | |
1503 | ||
1504 | coef_scaled = (9 * coef_scaled) / 10; | |
1505 | ||
1506 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
1507 | &ds_coef_exp); | |
1508 | ||
1509 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
1510 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); | |
1511 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
1512 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); | |
1513 | } | |
1514 | ||
cbe61d8a | 1515 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1516 | { |
1517 | u32 rst_flags; | |
1518 | u32 tmpReg; | |
1519 | ||
70768496 S |
1520 | if (AR_SREV_9100(ah)) { |
1521 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1522 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; | |
1523 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); | |
1524 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); | |
1525 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1526 | } | |
1527 | ||
f1dc5600 S |
1528 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1529 | AR_RTC_FORCE_WAKE_ON_INT); | |
1530 | ||
1531 | if (AR_SREV_9100(ah)) { | |
1532 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1533 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1534 | } else { | |
1535 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1536 | if (tmpReg & | |
1537 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1538 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
1539 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
1540 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
1541 | } else { | |
1542 | REG_WRITE(ah, AR_RC, AR_RC_AHB); | |
1543 | } | |
1544 | ||
1545 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1546 | if (type == ATH9K_RESET_COLD) | |
1547 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1548 | } | |
1549 | ||
d03a66c1 | 1550 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
f1dc5600 S |
1551 | udelay(50); |
1552 | ||
d03a66c1 | 1553 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1554 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
f1dc5600 | 1555 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, |
04bd4638 | 1556 | "RTC stuck in MAC reset\n"); |
f1dc5600 S |
1557 | return false; |
1558 | } | |
1559 | ||
1560 | if (!AR_SREV_9100(ah)) | |
1561 | REG_WRITE(ah, AR_RC, 0); | |
1562 | ||
1563 | ath9k_hw_init_pll(ah, NULL); | |
1564 | ||
1565 | if (AR_SREV_9100(ah)) | |
1566 | udelay(50); | |
1567 | ||
1568 | return true; | |
1569 | } | |
1570 | ||
cbe61d8a | 1571 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 S |
1572 | { |
1573 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | |
1574 | AR_RTC_FORCE_WAKE_ON_INT); | |
1575 | ||
d03a66c1 | 1576 | REG_WRITE(ah, AR_RTC_RESET, 0); |
8bd1d07f | 1577 | udelay(2); |
d03a66c1 | 1578 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1579 | |
1580 | if (!ath9k_hw_wait(ah, | |
1581 | AR_RTC_STATUS, | |
1582 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1583 | AR_RTC_STATUS_ON, |
1584 | AH_WAIT_TIMEOUT)) { | |
04bd4638 | 1585 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n"); |
f1dc5600 | 1586 | return false; |
f078f209 LR |
1587 | } |
1588 | ||
f1dc5600 S |
1589 | ath9k_hw_read_revisions(ah); |
1590 | ||
1591 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1592 | } | |
1593 | ||
cbe61d8a | 1594 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 S |
1595 | { |
1596 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
1597 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1598 | ||
1599 | switch (type) { | |
1600 | case ATH9K_RESET_POWER_ON: | |
1601 | return ath9k_hw_set_reset_power_on(ah); | |
1602 | break; | |
1603 | case ATH9K_RESET_WARM: | |
1604 | case ATH9K_RESET_COLD: | |
1605 | return ath9k_hw_set_reset(ah, type); | |
1606 | break; | |
1607 | default: | |
1608 | return false; | |
1609 | } | |
f078f209 LR |
1610 | } |
1611 | ||
cbe61d8a | 1612 | static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, |
f1dc5600 | 1613 | enum ath9k_ht_macmode macmode) |
f078f209 | 1614 | { |
f1dc5600 | 1615 | u32 phymode; |
e7594072 | 1616 | u32 enableDacFifo = 0; |
f078f209 | 1617 | |
e7594072 SB |
1618 | if (AR_SREV_9285_10_OR_LATER(ah)) |
1619 | enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & | |
1620 | AR_PHY_FC_ENABLE_DAC_FIFO); | |
1621 | ||
f1dc5600 | 1622 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
e7594072 | 1623 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; |
f1dc5600 S |
1624 | |
1625 | if (IS_CHAN_HT40(chan)) { | |
1626 | phymode |= AR_PHY_FC_DYN2040_EN; | |
f078f209 | 1627 | |
f1dc5600 S |
1628 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
1629 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | |
1630 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; | |
f078f209 | 1631 | |
2660b81a | 1632 | if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25) |
f1dc5600 | 1633 | phymode |= AR_PHY_FC_DYN2040_EXT_CH; |
f078f209 | 1634 | } |
f1dc5600 S |
1635 | REG_WRITE(ah, AR_PHY_TURBO, phymode); |
1636 | ||
1637 | ath9k_hw_set11nmac2040(ah, macmode); | |
f078f209 | 1638 | |
f1dc5600 S |
1639 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
1640 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
f078f209 LR |
1641 | } |
1642 | ||
cbe61d8a | 1643 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1644 | struct ath9k_channel *chan) |
f078f209 | 1645 | { |
8bd1d07f SB |
1646 | if (OLC_FOR_AR9280_20_LATER) { |
1647 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) | |
1648 | return false; | |
1649 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | |
f1dc5600 | 1650 | return false; |
f078f209 | 1651 | |
f1dc5600 S |
1652 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
1653 | return false; | |
f078f209 | 1654 | |
2660b81a | 1655 | ah->chip_fullsleep = false; |
f1dc5600 | 1656 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1657 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1658 | |
f1dc5600 | 1659 | return true; |
f078f209 LR |
1660 | } |
1661 | ||
cbe61d8a | 1662 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
f1dc5600 S |
1663 | struct ath9k_channel *chan, |
1664 | enum ath9k_ht_macmode macmode) | |
f078f209 | 1665 | { |
5f8e077c | 1666 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 1667 | u32 synthDelay, qnum; |
f078f209 LR |
1668 | |
1669 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1670 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
1671 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | |
04bd4638 | 1672 | "Transmit frames pending on queue %d\n", qnum); |
f078f209 LR |
1673 | return false; |
1674 | } | |
1675 | } | |
1676 | ||
1677 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | |
1678 | if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | |
0caa7b14 | 1679 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { |
04bd4638 S |
1680 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, |
1681 | "Could not kill baseband RX\n"); | |
f078f209 LR |
1682 | return false; |
1683 | } | |
1684 | ||
1685 | ath9k_hw_set_regs(ah, chan, macmode); | |
1686 | ||
1687 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1688 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { | |
1689 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
04bd4638 | 1690 | "failed to set channel\n"); |
f078f209 LR |
1691 | return false; |
1692 | } | |
1693 | } else { | |
1694 | if (!(ath9k_hw_set_channel(ah, chan))) { | |
1695 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
04bd4638 | 1696 | "failed to set channel\n"); |
f078f209 LR |
1697 | return false; |
1698 | } | |
1699 | } | |
1700 | ||
f74df6fb S |
1701 | if (ah->eep_ops->set_txpower(ah, chan, |
1702 | ath9k_regd_get_ctl(ah, chan), | |
1703 | channel->max_antenna_gain * 2, | |
1704 | channel->max_power * 2, | |
1705 | min((u32) MAX_RATE_POWER, | |
1706 | (u32) ah->regulatory.power_limit)) != 0) { | |
f078f209 | 1707 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, |
04bd4638 | 1708 | "error init'ing transmit power\n"); |
f078f209 LR |
1709 | return false; |
1710 | } | |
1711 | ||
1712 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
788a3d6f | 1713 | if (IS_CHAN_B(chan)) |
f078f209 LR |
1714 | synthDelay = (4 * synthDelay) / 22; |
1715 | else | |
1716 | synthDelay /= 10; | |
1717 | ||
1718 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | |
1719 | ||
1720 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | |
1721 | ||
f1dc5600 S |
1722 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1723 | ath9k_hw_set_delta_slope(ah, chan); | |
1724 | ||
1725 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
1726 | ath9k_hw_9280_spur_mitigate(ah, chan); | |
1727 | else | |
1728 | ath9k_hw_spur_mitigate(ah, chan); | |
1729 | ||
1730 | if (!chan->oneTimeCalsDone) | |
1731 | chan->oneTimeCalsDone = true; | |
1732 | ||
1733 | return true; | |
1734 | } | |
1735 | ||
cbe61d8a | 1736 | static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) |
f1dc5600 S |
1737 | { |
1738 | int bb_spur = AR_NO_SPUR; | |
1739 | int freq; | |
1740 | int bin, cur_bin; | |
1741 | int bb_spur_off, spur_subchannel_sd; | |
1742 | int spur_freq_sd; | |
1743 | int spur_delta_phase; | |
1744 | int denominator; | |
1745 | int upper, lower, cur_vit_mask; | |
1746 | int tmp, newVal; | |
1747 | int i; | |
1748 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | |
1749 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
1750 | }; | |
1751 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | |
1752 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
1753 | }; | |
1754 | int inc[4] = { 0, 100, 0, 0 }; | |
1755 | struct chan_centers centers; | |
1756 | ||
1757 | int8_t mask_m[123]; | |
1758 | int8_t mask_p[123]; | |
1759 | int8_t mask_amt; | |
1760 | int tmp_mask; | |
1761 | int cur_bb_spur; | |
1762 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
1763 | ||
1764 | memset(&mask_m, 0, sizeof(int8_t) * 123); | |
1765 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
1766 | ||
1767 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1768 | freq = centers.synth_center; | |
1769 | ||
2660b81a | 1770 | ah->config.spurmode = SPUR_ENABLE_EEPROM; |
f1dc5600 | 1771 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
f74df6fb | 1772 | cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); |
f1dc5600 S |
1773 | |
1774 | if (is2GHz) | |
1775 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; | |
1776 | else | |
1777 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; | |
1778 | ||
1779 | if (AR_NO_SPUR == cur_bb_spur) | |
1780 | break; | |
1781 | cur_bb_spur = cur_bb_spur - freq; | |
1782 | ||
1783 | if (IS_CHAN_HT40(chan)) { | |
1784 | if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && | |
1785 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { | |
1786 | bb_spur = cur_bb_spur; | |
1787 | break; | |
1788 | } | |
1789 | } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && | |
1790 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { | |
1791 | bb_spur = cur_bb_spur; | |
1792 | break; | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | if (AR_NO_SPUR == bb_spur) { | |
1797 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | |
1798 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | |
1799 | return; | |
1800 | } else { | |
1801 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | |
1802 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | |
1803 | } | |
1804 | ||
1805 | bin = bb_spur * 320; | |
1806 | ||
1807 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | |
1808 | ||
1809 | newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
1810 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
1811 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
1812 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
1813 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); | |
1814 | ||
1815 | newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | |
1816 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
1817 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
1818 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
1819 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
1820 | REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); | |
1821 | ||
1822 | if (IS_CHAN_HT40(chan)) { | |
1823 | if (bb_spur < 0) { | |
1824 | spur_subchannel_sd = 1; | |
1825 | bb_spur_off = bb_spur + 10; | |
1826 | } else { | |
1827 | spur_subchannel_sd = 0; | |
1828 | bb_spur_off = bb_spur - 10; | |
1829 | } | |
1830 | } else { | |
1831 | spur_subchannel_sd = 0; | |
1832 | bb_spur_off = bb_spur; | |
1833 | } | |
1834 | ||
1835 | if (IS_CHAN_HT40(chan)) | |
1836 | spur_delta_phase = | |
1837 | ((bb_spur * 262144) / | |
1838 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
1839 | else | |
1840 | spur_delta_phase = | |
1841 | ((bb_spur * 524288) / | |
1842 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
1843 | ||
1844 | denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; | |
1845 | spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; | |
1846 | ||
1847 | newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | |
1848 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
1849 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
1850 | REG_WRITE(ah, AR_PHY_TIMING11, newVal); | |
1851 | ||
1852 | newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; | |
1853 | REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); | |
1854 | ||
1855 | cur_bin = -6000; | |
1856 | upper = bin + 100; | |
1857 | lower = bin - 100; | |
1858 | ||
1859 | for (i = 0; i < 4; i++) { | |
1860 | int pilot_mask = 0; | |
1861 | int chan_mask = 0; | |
1862 | int bp = 0; | |
1863 | for (bp = 0; bp < 30; bp++) { | |
1864 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
1865 | pilot_mask = pilot_mask | 0x1 << bp; | |
1866 | chan_mask = chan_mask | 0x1 << bp; | |
1867 | } | |
1868 | cur_bin += 100; | |
1869 | } | |
1870 | cur_bin += inc[i]; | |
1871 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
1872 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
1873 | } | |
1874 | ||
1875 | cur_vit_mask = 6100; | |
1876 | upper = bin + 120; | |
1877 | lower = bin - 120; | |
1878 | ||
1879 | for (i = 0; i < 123; i++) { | |
1880 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
1881 | ||
1882 | /* workaround for gcc bug #37014 */ | |
a085ff71 | 1883 | volatile int tmp_v = abs(cur_vit_mask - bin); |
f1dc5600 | 1884 | |
a085ff71 | 1885 | if (tmp_v < 75) |
f1dc5600 S |
1886 | mask_amt = 1; |
1887 | else | |
1888 | mask_amt = 0; | |
1889 | if (cur_vit_mask < 0) | |
1890 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
1891 | else | |
1892 | mask_p[cur_vit_mask / 100] = mask_amt; | |
1893 | } | |
1894 | cur_vit_mask -= 100; | |
1895 | } | |
1896 | ||
1897 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | |
1898 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
1899 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
1900 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
1901 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
1902 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
1903 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
1904 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
1905 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
1906 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
1907 | ||
1908 | tmp_mask = (mask_m[31] << 28) | |
1909 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
1910 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
1911 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
1912 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
1913 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
1914 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
1915 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
1916 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
1917 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
1918 | ||
1919 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | |
1920 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
1921 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
1922 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
1923 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
1924 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
1925 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
1926 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
1927 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
1928 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
1929 | ||
1930 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | |
1931 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
1932 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
1933 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
1934 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
1935 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
1936 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
1937 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
1938 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
1939 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
1940 | ||
1941 | tmp_mask = (mask_p[15] << 28) | |
1942 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
1943 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
1944 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
1945 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
1946 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
1947 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
1948 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
1949 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
1950 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
f078f209 | 1951 | |
f1dc5600 S |
1952 | tmp_mask = (mask_p[30] << 28) |
1953 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
1954 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
1955 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
1956 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
1957 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
1958 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
1959 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
1960 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
1961 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
f078f209 | 1962 | |
f1dc5600 S |
1963 | tmp_mask = (mask_p[45] << 28) |
1964 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
1965 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
1966 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
1967 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
1968 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
1969 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
1970 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
1971 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
1972 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
f078f209 | 1973 | |
f1dc5600 S |
1974 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
1975 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
1976 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
1977 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
1978 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
1979 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
1980 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
1981 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
1982 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
1983 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
f078f209 LR |
1984 | } |
1985 | ||
cbe61d8a | 1986 | static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) |
f078f209 | 1987 | { |
f1dc5600 S |
1988 | int bb_spur = AR_NO_SPUR; |
1989 | int bin, cur_bin; | |
1990 | int spur_freq_sd; | |
1991 | int spur_delta_phase; | |
1992 | int denominator; | |
1993 | int upper, lower, cur_vit_mask; | |
1994 | int tmp, new; | |
1995 | int i; | |
1996 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | |
1997 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
1998 | }; | |
1999 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | |
2000 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
2001 | }; | |
2002 | int inc[4] = { 0, 100, 0, 0 }; | |
f078f209 | 2003 | |
f1dc5600 S |
2004 | int8_t mask_m[123]; |
2005 | int8_t mask_p[123]; | |
2006 | int8_t mask_amt; | |
2007 | int tmp_mask; | |
2008 | int cur_bb_spur; | |
2009 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
f078f209 | 2010 | |
f1dc5600 S |
2011 | memset(&mask_m, 0, sizeof(int8_t) * 123); |
2012 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
f078f209 | 2013 | |
f1dc5600 | 2014 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
f74df6fb | 2015 | cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); |
f1dc5600 S |
2016 | if (AR_NO_SPUR == cur_bb_spur) |
2017 | break; | |
2018 | cur_bb_spur = cur_bb_spur - (chan->channel * 10); | |
2019 | if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { | |
2020 | bb_spur = cur_bb_spur; | |
2021 | break; | |
2022 | } | |
2023 | } | |
f078f209 | 2024 | |
f1dc5600 S |
2025 | if (AR_NO_SPUR == bb_spur) |
2026 | return; | |
f078f209 | 2027 | |
f1dc5600 | 2028 | bin = bb_spur * 32; |
f078f209 | 2029 | |
f1dc5600 S |
2030 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); |
2031 | new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
2032 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
2033 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
2034 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
f078f209 | 2035 | |
f1dc5600 | 2036 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); |
f078f209 | 2037 | |
f1dc5600 S |
2038 | new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | |
2039 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
2040 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
2041 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
2042 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
2043 | REG_WRITE(ah, AR_PHY_SPUR_REG, new); | |
f078f209 | 2044 | |
f1dc5600 S |
2045 | spur_delta_phase = ((bb_spur * 524288) / 100) & |
2046 | AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
f078f209 | 2047 | |
f1dc5600 S |
2048 | denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; |
2049 | spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; | |
f078f209 | 2050 | |
f1dc5600 S |
2051 | new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | |
2052 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
2053 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
2054 | REG_WRITE(ah, AR_PHY_TIMING11, new); | |
f078f209 | 2055 | |
f1dc5600 S |
2056 | cur_bin = -6000; |
2057 | upper = bin + 100; | |
2058 | lower = bin - 100; | |
f078f209 | 2059 | |
f1dc5600 S |
2060 | for (i = 0; i < 4; i++) { |
2061 | int pilot_mask = 0; | |
2062 | int chan_mask = 0; | |
2063 | int bp = 0; | |
2064 | for (bp = 0; bp < 30; bp++) { | |
2065 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
2066 | pilot_mask = pilot_mask | 0x1 << bp; | |
2067 | chan_mask = chan_mask | 0x1 << bp; | |
2068 | } | |
2069 | cur_bin += 100; | |
2070 | } | |
2071 | cur_bin += inc[i]; | |
2072 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
2073 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
f078f209 | 2074 | } |
f078f209 | 2075 | |
f1dc5600 S |
2076 | cur_vit_mask = 6100; |
2077 | upper = bin + 120; | |
2078 | lower = bin - 120; | |
f078f209 | 2079 | |
f1dc5600 S |
2080 | for (i = 0; i < 123; i++) { |
2081 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
f078f209 | 2082 | |
f1dc5600 | 2083 | /* workaround for gcc bug #37014 */ |
a085ff71 | 2084 | volatile int tmp_v = abs(cur_vit_mask - bin); |
f078f209 | 2085 | |
a085ff71 | 2086 | if (tmp_v < 75) |
f1dc5600 S |
2087 | mask_amt = 1; |
2088 | else | |
2089 | mask_amt = 0; | |
2090 | if (cur_vit_mask < 0) | |
2091 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
2092 | else | |
2093 | mask_p[cur_vit_mask / 100] = mask_amt; | |
2094 | } | |
2095 | cur_vit_mask -= 100; | |
f078f209 LR |
2096 | } |
2097 | ||
f1dc5600 S |
2098 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) |
2099 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
2100 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
2101 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
2102 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
2103 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
2104 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
2105 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
2106 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
2107 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
f078f209 | 2108 | |
f1dc5600 S |
2109 | tmp_mask = (mask_m[31] << 28) |
2110 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
2111 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
2112 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
2113 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
2114 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
2115 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
2116 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
2117 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
2118 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
f078f209 | 2119 | |
f1dc5600 S |
2120 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) |
2121 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
2122 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
2123 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
2124 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
2125 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
2126 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
2127 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
2128 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
2129 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
f078f209 | 2130 | |
f1dc5600 S |
2131 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) |
2132 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
2133 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
2134 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
2135 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
2136 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
2137 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
2138 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
2139 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
2140 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
f078f209 | 2141 | |
f1dc5600 S |
2142 | tmp_mask = (mask_p[15] << 28) |
2143 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
2144 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
2145 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
2146 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
2147 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
2148 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
2149 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
2150 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
2151 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
f078f209 | 2152 | |
f1dc5600 S |
2153 | tmp_mask = (mask_p[30] << 28) |
2154 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
2155 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
2156 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
2157 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
2158 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
2159 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
2160 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
2161 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
2162 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
f078f209 | 2163 | |
f1dc5600 S |
2164 | tmp_mask = (mask_p[45] << 28) |
2165 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
2166 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
2167 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
2168 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
2169 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
2170 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
2171 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
2172 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
2173 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
f078f209 | 2174 | |
f1dc5600 S |
2175 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
2176 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
2177 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
2178 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
2179 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
2180 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
2181 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
2182 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
2183 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
2184 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
f078f209 LR |
2185 | } |
2186 | ||
cbe61d8a | 2187 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
ae8d2858 | 2188 | bool bChannelChange) |
f078f209 | 2189 | { |
f078f209 | 2190 | u32 saveLedState; |
ae8d2858 | 2191 | struct ath_softc *sc = ah->ah_sc; |
2660b81a | 2192 | struct ath9k_channel *curchan = ah->curchan; |
f078f209 LR |
2193 | u32 saveDefAntenna; |
2194 | u32 macStaId1; | |
ae8d2858 | 2195 | int i, rx_chainmask, r; |
f078f209 | 2196 | |
2660b81a S |
2197 | ah->extprotspacing = sc->ht_extprotspacing; |
2198 | ah->txchainmask = sc->tx_chainmask; | |
2199 | ah->rxchainmask = sc->rx_chainmask; | |
f078f209 | 2200 | |
793c5929 | 2201 | if (AR_SREV_9285(ah)) { |
2660b81a S |
2202 | ah->txchainmask &= 0x1; |
2203 | ah->rxchainmask &= 0x1; | |
793c5929 | 2204 | } else if (AR_SREV_9280(ah)) { |
2660b81a S |
2205 | ah->txchainmask &= 0x3; |
2206 | ah->rxchainmask &= 0x3; | |
f078f209 LR |
2207 | } |
2208 | ||
ae8d2858 LR |
2209 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
2210 | return -EIO; | |
f078f209 LR |
2211 | |
2212 | if (curchan) | |
2213 | ath9k_hw_getnf(ah, curchan); | |
2214 | ||
2215 | if (bChannelChange && | |
2660b81a S |
2216 | (ah->chip_fullsleep != true) && |
2217 | (ah->curchan != NULL) && | |
2218 | (chan->channel != ah->curchan->channel) && | |
f078f209 | 2219 | ((chan->channelFlags & CHANNEL_ALL) == |
2660b81a | 2220 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
f078f209 | 2221 | (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && |
2660b81a | 2222 | !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) { |
f078f209 | 2223 | |
ae8d2858 | 2224 | if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { |
2660b81a | 2225 | ath9k_hw_loadnf(ah, ah->curchan); |
f078f209 | 2226 | ath9k_hw_start_nfcal(ah); |
ae8d2858 | 2227 | return 0; |
f078f209 LR |
2228 | } |
2229 | } | |
2230 | ||
2231 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
2232 | if (saveDefAntenna == 0) | |
2233 | saveDefAntenna = 1; | |
2234 | ||
2235 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
2236 | ||
2237 | saveLedState = REG_READ(ah, AR_CFG_LED) & | |
2238 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
2239 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
2240 | ||
2241 | ath9k_hw_mark_phy_inactive(ah); | |
2242 | ||
2243 | if (!ath9k_hw_chip_reset(ah, chan)) { | |
04bd4638 | 2244 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n"); |
ae8d2858 | 2245 | return -EINVAL; |
f078f209 LR |
2246 | } |
2247 | ||
369391db VT |
2248 | if (AR_SREV_9280_10_OR_LATER(ah)) |
2249 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); | |
f078f209 | 2250 | |
ae8d2858 LR |
2251 | r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width); |
2252 | if (r) | |
2253 | return r; | |
f078f209 | 2254 | |
0ced0e17 JM |
2255 | /* Setup MFP options for CCMP */ |
2256 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2257 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
2258 | * frames when constructing CCMP AAD. */ | |
2259 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
2260 | 0xc7ff); | |
2261 | ah->sw_mgmt_crypto = false; | |
2262 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
2263 | /* Disable hardware crypto for management frames */ | |
2264 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
2265 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
2266 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
2267 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
2268 | ah->sw_mgmt_crypto = true; | |
2269 | } else | |
2270 | ah->sw_mgmt_crypto = true; | |
2271 | ||
f078f209 LR |
2272 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
2273 | ath9k_hw_set_delta_slope(ah, chan); | |
2274 | ||
2275 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
2276 | ath9k_hw_9280_spur_mitigate(ah, chan); | |
2277 | else | |
2278 | ath9k_hw_spur_mitigate(ah, chan); | |
2279 | ||
f74df6fb | 2280 | if (!ah->eep_ops->set_board_values(ah, chan)) { |
f078f209 | 2281 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, |
04bd4638 | 2282 | "error setting board options\n"); |
ae8d2858 | 2283 | return -EIO; |
f078f209 LR |
2284 | } |
2285 | ||
2286 | ath9k_hw_decrease_chain_power(ah, chan); | |
2287 | ||
ba52da58 S |
2288 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr)); |
2289 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) | |
f078f209 LR |
2290 | | macStaId1 |
2291 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 2292 | | (ah->config. |
60b67f51 | 2293 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a S |
2294 | | ah->sta_id1_defaults); |
2295 | ath9k_hw_set_operating_mode(ah, ah->opmode); | |
f078f209 | 2296 | |
ba52da58 S |
2297 | REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); |
2298 | REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); | |
f078f209 LR |
2299 | |
2300 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
2301 | ||
ba52da58 S |
2302 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); |
2303 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | | |
2304 | ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 LR |
2305 | |
2306 | REG_WRITE(ah, AR_ISR, ~0); | |
2307 | ||
2308 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
2309 | ||
2310 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
ae8d2858 LR |
2311 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) |
2312 | return -EIO; | |
f078f209 | 2313 | } else { |
ae8d2858 LR |
2314 | if (!(ath9k_hw_set_channel(ah, chan))) |
2315 | return -EIO; | |
f078f209 LR |
2316 | } |
2317 | ||
2318 | for (i = 0; i < AR_NUM_DCU; i++) | |
2319 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
2320 | ||
2660b81a S |
2321 | ah->intr_txqs = 0; |
2322 | for (i = 0; i < ah->caps.total_queues; i++) | |
f078f209 LR |
2323 | ath9k_hw_resettxqueue(ah, i); |
2324 | ||
2660b81a | 2325 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
f078f209 LR |
2326 | ath9k_hw_init_qos(ah); |
2327 | ||
e97275cb | 2328 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a | 2329 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
500c064d VT |
2330 | ath9k_enable_rfkill(ah); |
2331 | #endif | |
f078f209 LR |
2332 | ath9k_hw_init_user_settings(ah); |
2333 | ||
f078f209 LR |
2334 | REG_WRITE(ah, AR_STA_ID1, |
2335 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
2336 | ||
2337 | ath9k_hw_set_dma(ah); | |
2338 | ||
2339 | REG_WRITE(ah, AR_OBS, 8); | |
2340 | ||
2660b81a | 2341 | if (ah->intr_mitigation) { |
f078f209 LR |
2342 | |
2343 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); | |
2344 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
2345 | } | |
2346 | ||
2347 | ath9k_hw_init_bb(ah, chan); | |
2348 | ||
ae8d2858 LR |
2349 | if (!ath9k_hw_init_cal(ah, chan)) |
2350 | return -EIO;; | |
f078f209 | 2351 | |
2660b81a | 2352 | rx_chainmask = ah->rxchainmask; |
f078f209 LR |
2353 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { |
2354 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
2355 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
2356 | } | |
2357 | ||
2358 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); | |
2359 | ||
2360 | if (AR_SREV_9100(ah)) { | |
2361 | u32 mask; | |
2362 | mask = REG_READ(ah, AR_CFG); | |
2363 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
2364 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
04bd4638 | 2365 | "CFG Byte Swap Set 0x%x\n", mask); |
f078f209 LR |
2366 | } else { |
2367 | mask = | |
2368 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
2369 | REG_WRITE(ah, AR_CFG, mask); | |
2370 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
04bd4638 | 2371 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
f078f209 LR |
2372 | } |
2373 | } else { | |
2374 | #ifdef __BIG_ENDIAN | |
2375 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
2376 | #endif | |
2377 | } | |
2378 | ||
ae8d2858 | 2379 | return 0; |
f078f209 LR |
2380 | } |
2381 | ||
f1dc5600 S |
2382 | /************************/ |
2383 | /* Key Cache Management */ | |
2384 | /************************/ | |
f078f209 | 2385 | |
cbe61d8a | 2386 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
f078f209 | 2387 | { |
f1dc5600 | 2388 | u32 keyType; |
f078f209 | 2389 | |
2660b81a | 2390 | if (entry >= ah->caps.keycache_size) { |
f1dc5600 | 2391 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, |
04bd4638 | 2392 | "entry %u out of range\n", entry); |
f078f209 LR |
2393 | return false; |
2394 | } | |
2395 | ||
f1dc5600 | 2396 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
f078f209 | 2397 | |
f1dc5600 S |
2398 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
2399 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); | |
2400 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); | |
2401 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); | |
2402 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); | |
2403 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); | |
2404 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); | |
2405 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); | |
f078f209 | 2406 | |
f1dc5600 S |
2407 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
2408 | u16 micentry = entry + 64; | |
f078f209 | 2409 | |
f1dc5600 S |
2410 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
2411 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
2412 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); | |
2413 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
f078f209 | 2414 | |
f078f209 LR |
2415 | } |
2416 | ||
2660b81a | 2417 | if (ah->curchan == NULL) |
f1dc5600 | 2418 | return true; |
f078f209 LR |
2419 | |
2420 | return true; | |
2421 | } | |
2422 | ||
cbe61d8a | 2423 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
f078f209 | 2424 | { |
f1dc5600 | 2425 | u32 macHi, macLo; |
f078f209 | 2426 | |
2660b81a | 2427 | if (entry >= ah->caps.keycache_size) { |
f1dc5600 | 2428 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, |
04bd4638 | 2429 | "entry %u out of range\n", entry); |
f1dc5600 | 2430 | return false; |
f078f209 LR |
2431 | } |
2432 | ||
f1dc5600 S |
2433 | if (mac != NULL) { |
2434 | macHi = (mac[5] << 8) | mac[4]; | |
2435 | macLo = (mac[3] << 24) | | |
2436 | (mac[2] << 16) | | |
2437 | (mac[1] << 8) | | |
2438 | mac[0]; | |
2439 | macLo >>= 1; | |
2440 | macLo |= (macHi & 1) << 31; | |
2441 | macHi >>= 1; | |
f078f209 | 2442 | } else { |
f1dc5600 | 2443 | macLo = macHi = 0; |
f078f209 | 2444 | } |
f1dc5600 S |
2445 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
2446 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); | |
f078f209 | 2447 | |
f1dc5600 | 2448 | return true; |
f078f209 LR |
2449 | } |
2450 | ||
cbe61d8a | 2451 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
f1dc5600 | 2452 | const struct ath9k_keyval *k, |
e0caf9ea | 2453 | const u8 *mac) |
f078f209 | 2454 | { |
2660b81a | 2455 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
f1dc5600 S |
2456 | u32 key0, key1, key2, key3, key4; |
2457 | u32 keyType; | |
f078f209 | 2458 | |
f1dc5600 S |
2459 | if (entry >= pCap->keycache_size) { |
2460 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 2461 | "entry %u out of range\n", entry); |
f1dc5600 | 2462 | return false; |
f078f209 LR |
2463 | } |
2464 | ||
f1dc5600 S |
2465 | switch (k->kv_type) { |
2466 | case ATH9K_CIPHER_AES_OCB: | |
2467 | keyType = AR_KEYTABLE_TYPE_AES; | |
2468 | break; | |
2469 | case ATH9K_CIPHER_AES_CCM: | |
2470 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { | |
2471 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 2472 | "AES-CCM not supported by mac rev 0x%x\n", |
d535a42a | 2473 | ah->hw_version.macRev); |
f1dc5600 S |
2474 | return false; |
2475 | } | |
2476 | keyType = AR_KEYTABLE_TYPE_CCM; | |
2477 | break; | |
2478 | case ATH9K_CIPHER_TKIP: | |
2479 | keyType = AR_KEYTABLE_TYPE_TKIP; | |
2480 | if (ATH9K_IS_MIC_ENABLED(ah) | |
2481 | && entry + 64 >= pCap->keycache_size) { | |
2482 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 2483 | "entry %u inappropriate for TKIP\n", entry); |
f1dc5600 S |
2484 | return false; |
2485 | } | |
2486 | break; | |
2487 | case ATH9K_CIPHER_WEP: | |
2488 | if (k->kv_len < LEN_WEP40) { | |
2489 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 2490 | "WEP key length %u too small\n", k->kv_len); |
f1dc5600 S |
2491 | return false; |
2492 | } | |
2493 | if (k->kv_len <= LEN_WEP40) | |
2494 | keyType = AR_KEYTABLE_TYPE_40; | |
2495 | else if (k->kv_len <= LEN_WEP104) | |
2496 | keyType = AR_KEYTABLE_TYPE_104; | |
2497 | else | |
2498 | keyType = AR_KEYTABLE_TYPE_128; | |
2499 | break; | |
2500 | case ATH9K_CIPHER_CLR: | |
2501 | keyType = AR_KEYTABLE_TYPE_CLR; | |
2502 | break; | |
2503 | default: | |
2504 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 2505 | "cipher %u not supported\n", k->kv_type); |
f1dc5600 | 2506 | return false; |
f078f209 LR |
2507 | } |
2508 | ||
e0caf9ea JM |
2509 | key0 = get_unaligned_le32(k->kv_val + 0); |
2510 | key1 = get_unaligned_le16(k->kv_val + 4); | |
2511 | key2 = get_unaligned_le32(k->kv_val + 6); | |
2512 | key3 = get_unaligned_le16(k->kv_val + 10); | |
2513 | key4 = get_unaligned_le32(k->kv_val + 12); | |
f1dc5600 S |
2514 | if (k->kv_len <= LEN_WEP104) |
2515 | key4 &= 0xff; | |
f078f209 | 2516 | |
672903b3 JM |
2517 | /* |
2518 | * Note: Key cache registers access special memory area that requires | |
2519 | * two 32-bit writes to actually update the values in the internal | |
2520 | * memory. Consequently, the exact order and pairs used here must be | |
2521 | * maintained. | |
2522 | */ | |
2523 | ||
f1dc5600 S |
2524 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
2525 | u16 micentry = entry + 64; | |
f078f209 | 2526 | |
672903b3 JM |
2527 | /* |
2528 | * Write inverted key[47:0] first to avoid Michael MIC errors | |
2529 | * on frames that could be sent or received at the same time. | |
2530 | * The correct key will be written in the end once everything | |
2531 | * else is ready. | |
2532 | */ | |
f1dc5600 S |
2533 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
2534 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); | |
672903b3 JM |
2535 | |
2536 | /* Write key[95:48] */ | |
f1dc5600 S |
2537 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
2538 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
2539 | |
2540 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
2541 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
2542 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
672903b3 JM |
2543 | |
2544 | /* Write MAC address for the entry */ | |
f1dc5600 | 2545 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
f078f209 | 2546 | |
2660b81a | 2547 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
672903b3 JM |
2548 | /* |
2549 | * TKIP uses two key cache entries: | |
2550 | * Michael MIC TX/RX keys in the same key cache entry | |
2551 | * (idx = main index + 64): | |
2552 | * key0 [31:0] = RX key [31:0] | |
2553 | * key1 [15:0] = TX key [31:16] | |
2554 | * key1 [31:16] = reserved | |
2555 | * key2 [31:0] = RX key [63:32] | |
2556 | * key3 [15:0] = TX key [15:0] | |
2557 | * key3 [31:16] = reserved | |
2558 | * key4 [31:0] = TX key [63:32] | |
2559 | */ | |
f1dc5600 | 2560 | u32 mic0, mic1, mic2, mic3, mic4; |
f078f209 | 2561 | |
f1dc5600 S |
2562 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
2563 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
2564 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; | |
2565 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; | |
2566 | mic4 = get_unaligned_le32(k->kv_txmic + 4); | |
672903b3 JM |
2567 | |
2568 | /* Write RX[31:0] and TX[31:16] */ | |
f1dc5600 S |
2569 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
2570 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); | |
672903b3 JM |
2571 | |
2572 | /* Write RX[63:32] and TX[15:0] */ | |
f1dc5600 S |
2573 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
2574 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); | |
672903b3 JM |
2575 | |
2576 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
2577 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
2578 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
2579 | AR_KEYTABLE_TYPE_CLR); | |
f078f209 | 2580 | |
f1dc5600 | 2581 | } else { |
672903b3 JM |
2582 | /* |
2583 | * TKIP uses four key cache entries (two for group | |
2584 | * keys): | |
2585 | * Michael MIC TX/RX keys are in different key cache | |
2586 | * entries (idx = main index + 64 for TX and | |
2587 | * main index + 32 + 96 for RX): | |
2588 | * key0 [31:0] = TX/RX MIC key [31:0] | |
2589 | * key1 [31:0] = reserved | |
2590 | * key2 [31:0] = TX/RX MIC key [63:32] | |
2591 | * key3 [31:0] = reserved | |
2592 | * key4 [31:0] = reserved | |
2593 | * | |
2594 | * Upper layer code will call this function separately | |
2595 | * for TX and RX keys when these registers offsets are | |
2596 | * used. | |
2597 | */ | |
f1dc5600 | 2598 | u32 mic0, mic2; |
f078f209 | 2599 | |
f1dc5600 S |
2600 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
2601 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
672903b3 JM |
2602 | |
2603 | /* Write MIC key[31:0] */ | |
f1dc5600 S |
2604 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
2605 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
672903b3 JM |
2606 | |
2607 | /* Write MIC key[63:32] */ | |
f1dc5600 S |
2608 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
2609 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
672903b3 JM |
2610 | |
2611 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
2612 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
2613 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
2614 | AR_KEYTABLE_TYPE_CLR); | |
2615 | } | |
672903b3 JM |
2616 | |
2617 | /* MAC address registers are reserved for the MIC entry */ | |
f1dc5600 S |
2618 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
2619 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); | |
672903b3 JM |
2620 | |
2621 | /* | |
2622 | * Write the correct (un-inverted) key[47:0] last to enable | |
2623 | * TKIP now that all other registers are set with correct | |
2624 | * values. | |
2625 | */ | |
f1dc5600 S |
2626 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
2627 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
2628 | } else { | |
672903b3 | 2629 | /* Write key[47:0] */ |
f1dc5600 S |
2630 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
2631 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
672903b3 JM |
2632 | |
2633 | /* Write key[95:48] */ | |
f1dc5600 S |
2634 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
2635 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
2636 | |
2637 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
2638 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
2639 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
f078f209 | 2640 | |
672903b3 | 2641 | /* Write MAC address for the entry */ |
f1dc5600 S |
2642 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
2643 | } | |
f078f209 | 2644 | |
f078f209 LR |
2645 | return true; |
2646 | } | |
2647 | ||
cbe61d8a | 2648 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
f078f209 | 2649 | { |
2660b81a | 2650 | if (entry < ah->caps.keycache_size) { |
f1dc5600 S |
2651 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
2652 | if (val & AR_KEYTABLE_VALID) | |
2653 | return true; | |
2654 | } | |
2655 | return false; | |
f078f209 LR |
2656 | } |
2657 | ||
f1dc5600 S |
2658 | /******************************/ |
2659 | /* Power Management (Chipset) */ | |
2660 | /******************************/ | |
2661 | ||
cbe61d8a | 2662 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2663 | { |
f1dc5600 S |
2664 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2665 | if (setChip) { | |
2666 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | |
2667 | AR_RTC_FORCE_WAKE_EN); | |
2668 | if (!AR_SREV_9100(ah)) | |
2669 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
f078f209 | 2670 | |
d03a66c1 | 2671 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
f1dc5600 S |
2672 | AR_RTC_RESET_EN); |
2673 | } | |
f078f209 LR |
2674 | } |
2675 | ||
cbe61d8a | 2676 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2677 | { |
f1dc5600 S |
2678 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2679 | if (setChip) { | |
2660b81a | 2680 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 2681 | |
f1dc5600 S |
2682 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
2683 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
2684 | AR_RTC_FORCE_WAKE_ON_INT); | |
2685 | } else { | |
2686 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | |
2687 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2688 | } |
f078f209 | 2689 | } |
f078f209 LR |
2690 | } |
2691 | ||
cbe61d8a | 2692 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 2693 | { |
f1dc5600 S |
2694 | u32 val; |
2695 | int i; | |
f078f209 | 2696 | |
f1dc5600 S |
2697 | if (setChip) { |
2698 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
2699 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2700 | if (ath9k_hw_set_reset_reg(ah, | |
2701 | ATH9K_RESET_POWER_ON) != true) { | |
2702 | return false; | |
2703 | } | |
2704 | } | |
2705 | if (AR_SREV_9100(ah)) | |
2706 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2707 | AR_RTC_RESET_EN); | |
f078f209 | 2708 | |
f1dc5600 S |
2709 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2710 | AR_RTC_FORCE_WAKE_EN); | |
2711 | udelay(50); | |
f078f209 | 2712 | |
f1dc5600 S |
2713 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2714 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2715 | if (val == AR_RTC_STATUS_ON) | |
2716 | break; | |
2717 | udelay(50); | |
2718 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2719 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2720 | } |
f1dc5600 S |
2721 | if (i == 0) { |
2722 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
04bd4638 | 2723 | "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); |
f1dc5600 | 2724 | return false; |
f078f209 | 2725 | } |
f078f209 LR |
2726 | } |
2727 | ||
f1dc5600 | 2728 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2729 | |
f1dc5600 | 2730 | return true; |
f078f209 LR |
2731 | } |
2732 | ||
cbe61d8a | 2733 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2734 | { |
cbe61d8a | 2735 | int status = true, setChip = true; |
f1dc5600 S |
2736 | static const char *modes[] = { |
2737 | "AWAKE", | |
2738 | "FULL-SLEEP", | |
2739 | "NETWORK SLEEP", | |
2740 | "UNDEFINED" | |
2741 | }; | |
f1dc5600 | 2742 | |
04bd4638 | 2743 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", |
2660b81a | 2744 | modes[ah->power_mode], modes[mode], |
f1dc5600 S |
2745 | setChip ? "set chip " : ""); |
2746 | ||
2747 | switch (mode) { | |
2748 | case ATH9K_PM_AWAKE: | |
2749 | status = ath9k_hw_set_power_awake(ah, setChip); | |
2750 | break; | |
2751 | case ATH9K_PM_FULL_SLEEP: | |
2752 | ath9k_set_power_sleep(ah, setChip); | |
2660b81a | 2753 | ah->chip_fullsleep = true; |
f1dc5600 S |
2754 | break; |
2755 | case ATH9K_PM_NETWORK_SLEEP: | |
2756 | ath9k_set_power_network_sleep(ah, setChip); | |
2757 | break; | |
f078f209 | 2758 | default: |
f1dc5600 | 2759 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, |
04bd4638 | 2760 | "Unknown power mode %u\n", mode); |
f078f209 LR |
2761 | return false; |
2762 | } | |
2660b81a | 2763 | ah->power_mode = mode; |
f1dc5600 S |
2764 | |
2765 | return status; | |
f078f209 LR |
2766 | } |
2767 | ||
24c1a280 LR |
2768 | /* |
2769 | * Helper for ASPM support. | |
2770 | * | |
2771 | * Disable PLL when in L0s as well as receiver clock when in L1. | |
2772 | * This power saving option must be enabled through the SerDes. | |
2773 | * | |
2774 | * Programming the SerDes must go through the same 288 bit serial shift | |
2775 | * register as the other analog registers. Hence the 9 writes. | |
2776 | */ | |
cbe61d8a | 2777 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) |
f078f209 | 2778 | { |
f1dc5600 | 2779 | u8 i; |
f078f209 | 2780 | |
2660b81a | 2781 | if (ah->is_pciexpress != true) |
f1dc5600 | 2782 | return; |
f078f209 | 2783 | |
24c1a280 | 2784 | /* Do not touch SerDes registers */ |
2660b81a | 2785 | if (ah->config.pcie_powersave_enable == 2) |
f1dc5600 S |
2786 | return; |
2787 | ||
24c1a280 | 2788 | /* Nothing to do on restore for 11N */ |
f1dc5600 S |
2789 | if (restore) |
2790 | return; | |
2791 | ||
2792 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
24c1a280 LR |
2793 | /* |
2794 | * AR9280 2.0 or later chips use SerDes values from the | |
2795 | * initvals.h initialized depending on chipset during | |
2796 | * ath9k_hw_do_attach() | |
2797 | */ | |
2660b81a S |
2798 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
2799 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), | |
2800 | INI_RA(&ah->iniPcieSerdes, i, 1)); | |
f078f209 | 2801 | } |
f1dc5600 | 2802 | } else if (AR_SREV_9280(ah) && |
d535a42a | 2803 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { |
f1dc5600 S |
2804 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); |
2805 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
2806 | ||
24c1a280 | 2807 | /* RX shut off when elecidle is asserted */ |
f1dc5600 S |
2808 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); |
2809 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | |
2810 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | |
2811 | ||
24c1a280 | 2812 | /* Shut off CLKREQ active in L1 */ |
2660b81a | 2813 | if (ah->config.pcie_clock_req) |
f1dc5600 S |
2814 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); |
2815 | else | |
2816 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | |
2817 | ||
2818 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
2819 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2820 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | |
2821 | ||
24c1a280 | 2822 | /* Load the new settings */ |
f1dc5600 S |
2823 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
2824 | ||
f1dc5600 S |
2825 | } else { |
2826 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | |
2827 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
24c1a280 LR |
2828 | |
2829 | /* RX shut off when elecidle is asserted */ | |
f1dc5600 S |
2830 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
2831 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | |
2832 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | |
24c1a280 LR |
2833 | |
2834 | /* | |
2835 | * Ignore ah->ah_config.pcie_clock_req setting for | |
2836 | * pre-AR9280 11n | |
2837 | */ | |
f1dc5600 | 2838 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
24c1a280 | 2839 | |
f1dc5600 S |
2840 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
2841 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2842 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | |
24c1a280 LR |
2843 | |
2844 | /* Load the new settings */ | |
f1dc5600 | 2845 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
2846 | } |
2847 | ||
6d08b9b9 LR |
2848 | udelay(1000); |
2849 | ||
24c1a280 | 2850 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
f1dc5600 S |
2851 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
2852 | ||
24c1a280 | 2853 | /* Several PCIe massages to ensure proper behaviour */ |
2660b81a S |
2854 | if (ah->config.pcie_waen) { |
2855 | REG_WRITE(ah, AR_WA, ah->config.pcie_waen); | |
f1dc5600 | 2856 | } else { |
e7594072 SB |
2857 | if (AR_SREV_9285(ah)) |
2858 | REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); | |
24c1a280 LR |
2859 | /* |
2860 | * On AR9280 chips bit 22 of 0x4004 needs to be set to | |
2861 | * otherwise card may disappear. | |
2862 | */ | |
e7594072 SB |
2863 | else if (AR_SREV_9280(ah)) |
2864 | REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); | |
f1dc5600 | 2865 | else |
e7594072 | 2866 | REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); |
f1dc5600 | 2867 | } |
f078f209 LR |
2868 | } |
2869 | ||
f1dc5600 S |
2870 | /**********************/ |
2871 | /* Interrupt Handling */ | |
2872 | /**********************/ | |
2873 | ||
cbe61d8a | 2874 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
f078f209 LR |
2875 | { |
2876 | u32 host_isr; | |
2877 | ||
2878 | if (AR_SREV_9100(ah)) | |
2879 | return true; | |
2880 | ||
2881 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | |
2882 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) | |
2883 | return true; | |
2884 | ||
2885 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
2886 | if ((host_isr & AR_INTR_SYNC_DEFAULT) | |
2887 | && (host_isr != AR_INTR_SPURIOUS)) | |
2888 | return true; | |
2889 | ||
2890 | return false; | |
2891 | } | |
2892 | ||
cbe61d8a | 2893 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) |
f078f209 LR |
2894 | { |
2895 | u32 isr = 0; | |
2896 | u32 mask2 = 0; | |
2660b81a | 2897 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 LR |
2898 | u32 sync_cause = 0; |
2899 | bool fatal_int = false; | |
2900 | ||
2901 | if (!AR_SREV_9100(ah)) { | |
2902 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | |
2903 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | |
2904 | == AR_RTC_STATUS_ON) { | |
2905 | isr = REG_READ(ah, AR_ISR); | |
2906 | } | |
2907 | } | |
2908 | ||
f1dc5600 S |
2909 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
2910 | AR_INTR_SYNC_DEFAULT; | |
f078f209 LR |
2911 | |
2912 | *masked = 0; | |
2913 | ||
2914 | if (!isr && !sync_cause) | |
2915 | return false; | |
2916 | } else { | |
2917 | *masked = 0; | |
2918 | isr = REG_READ(ah, AR_ISR); | |
2919 | } | |
2920 | ||
2921 | if (isr) { | |
f078f209 LR |
2922 | if (isr & AR_ISR_BCNMISC) { |
2923 | u32 isr2; | |
2924 | isr2 = REG_READ(ah, AR_ISR_S2); | |
2925 | if (isr2 & AR_ISR_S2_TIM) | |
2926 | mask2 |= ATH9K_INT_TIM; | |
2927 | if (isr2 & AR_ISR_S2_DTIM) | |
2928 | mask2 |= ATH9K_INT_DTIM; | |
2929 | if (isr2 & AR_ISR_S2_DTIMSYNC) | |
2930 | mask2 |= ATH9K_INT_DTIMSYNC; | |
2931 | if (isr2 & (AR_ISR_S2_CABEND)) | |
2932 | mask2 |= ATH9K_INT_CABEND; | |
2933 | if (isr2 & AR_ISR_S2_GTT) | |
2934 | mask2 |= ATH9K_INT_GTT; | |
2935 | if (isr2 & AR_ISR_S2_CST) | |
2936 | mask2 |= ATH9K_INT_CST; | |
4af9cf4f S |
2937 | if (isr2 & AR_ISR_S2_TSFOOR) |
2938 | mask2 |= ATH9K_INT_TSFOOR; | |
f078f209 LR |
2939 | } |
2940 | ||
2941 | isr = REG_READ(ah, AR_ISR_RAC); | |
2942 | if (isr == 0xffffffff) { | |
2943 | *masked = 0; | |
2944 | return false; | |
2945 | } | |
2946 | ||
2947 | *masked = isr & ATH9K_INT_COMMON; | |
2948 | ||
2660b81a | 2949 | if (ah->intr_mitigation) { |
f078f209 LR |
2950 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
2951 | *masked |= ATH9K_INT_RX; | |
2952 | } | |
2953 | ||
2954 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) | |
2955 | *masked |= ATH9K_INT_RX; | |
2956 | if (isr & | |
2957 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | |
2958 | AR_ISR_TXEOL)) { | |
2959 | u32 s0_s, s1_s; | |
2960 | ||
2961 | *masked |= ATH9K_INT_TX; | |
2962 | ||
2963 | s0_s = REG_READ(ah, AR_ISR_S0_S); | |
2660b81a S |
2964 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); |
2965 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | |
f078f209 LR |
2966 | |
2967 | s1_s = REG_READ(ah, AR_ISR_S1_S); | |
2660b81a S |
2968 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); |
2969 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | |
f078f209 LR |
2970 | } |
2971 | ||
2972 | if (isr & AR_ISR_RXORN) { | |
2973 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
04bd4638 | 2974 | "receive FIFO overrun interrupt\n"); |
f078f209 LR |
2975 | } |
2976 | ||
2977 | if (!AR_SREV_9100(ah)) { | |
60b67f51 | 2978 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2979 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
2980 | if (isr5 & AR_ISR_S5_TIM_TIMER) | |
2981 | *masked |= ATH9K_INT_TIM_TIMER; | |
2982 | } | |
2983 | } | |
2984 | ||
2985 | *masked |= mask2; | |
2986 | } | |
f1dc5600 | 2987 | |
f078f209 LR |
2988 | if (AR_SREV_9100(ah)) |
2989 | return true; | |
f1dc5600 | 2990 | |
f078f209 LR |
2991 | if (sync_cause) { |
2992 | fatal_int = | |
2993 | (sync_cause & | |
2994 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | |
2995 | ? true : false; | |
2996 | ||
2997 | if (fatal_int) { | |
2998 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | |
2999 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
04bd4638 | 3000 | "received PCI FATAL interrupt\n"); |
f078f209 LR |
3001 | } |
3002 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | |
3003 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
04bd4638 | 3004 | "received PCI PERR interrupt\n"); |
f078f209 LR |
3005 | } |
3006 | } | |
3007 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | |
3008 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
04bd4638 | 3009 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); |
f078f209 LR |
3010 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
3011 | REG_WRITE(ah, AR_RC, 0); | |
3012 | *masked |= ATH9K_INT_FATAL; | |
3013 | } | |
3014 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | |
3015 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
04bd4638 | 3016 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
f078f209 LR |
3017 | } |
3018 | ||
3019 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | |
3020 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | |
3021 | } | |
f1dc5600 | 3022 | |
f078f209 LR |
3023 | return true; |
3024 | } | |
3025 | ||
cbe61d8a | 3026 | enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) |
f078f209 | 3027 | { |
2660b81a | 3028 | return ah->mask_reg; |
f078f209 LR |
3029 | } |
3030 | ||
cbe61d8a | 3031 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) |
f078f209 | 3032 | { |
2660b81a | 3033 | u32 omask = ah->mask_reg; |
f078f209 | 3034 | u32 mask, mask2; |
2660b81a | 3035 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 3036 | |
04bd4638 | 3037 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
f078f209 LR |
3038 | |
3039 | if (omask & ATH9K_INT_GLOBAL) { | |
04bd4638 | 3040 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n"); |
f078f209 LR |
3041 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
3042 | (void) REG_READ(ah, AR_IER); | |
3043 | if (!AR_SREV_9100(ah)) { | |
3044 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); | |
3045 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); | |
3046 | ||
3047 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
3048 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); | |
3049 | } | |
3050 | } | |
3051 | ||
3052 | mask = ints & ATH9K_INT_COMMON; | |
3053 | mask2 = 0; | |
3054 | ||
3055 | if (ints & ATH9K_INT_TX) { | |
2660b81a | 3056 | if (ah->txok_interrupt_mask) |
f078f209 | 3057 | mask |= AR_IMR_TXOK; |
2660b81a | 3058 | if (ah->txdesc_interrupt_mask) |
f078f209 | 3059 | mask |= AR_IMR_TXDESC; |
2660b81a | 3060 | if (ah->txerr_interrupt_mask) |
f078f209 | 3061 | mask |= AR_IMR_TXERR; |
2660b81a | 3062 | if (ah->txeol_interrupt_mask) |
f078f209 LR |
3063 | mask |= AR_IMR_TXEOL; |
3064 | } | |
3065 | if (ints & ATH9K_INT_RX) { | |
3066 | mask |= AR_IMR_RXERR; | |
2660b81a | 3067 | if (ah->intr_mitigation) |
f078f209 LR |
3068 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
3069 | else | |
3070 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; | |
60b67f51 | 3071 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
f078f209 LR |
3072 | mask |= AR_IMR_GENTMR; |
3073 | } | |
3074 | ||
3075 | if (ints & (ATH9K_INT_BMISC)) { | |
3076 | mask |= AR_IMR_BCNMISC; | |
3077 | if (ints & ATH9K_INT_TIM) | |
3078 | mask2 |= AR_IMR_S2_TIM; | |
3079 | if (ints & ATH9K_INT_DTIM) | |
3080 | mask2 |= AR_IMR_S2_DTIM; | |
3081 | if (ints & ATH9K_INT_DTIMSYNC) | |
3082 | mask2 |= AR_IMR_S2_DTIMSYNC; | |
3083 | if (ints & ATH9K_INT_CABEND) | |
4af9cf4f S |
3084 | mask2 |= AR_IMR_S2_CABEND; |
3085 | if (ints & ATH9K_INT_TSFOOR) | |
3086 | mask2 |= AR_IMR_S2_TSFOOR; | |
f078f209 LR |
3087 | } |
3088 | ||
3089 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { | |
3090 | mask |= AR_IMR_BCNMISC; | |
3091 | if (ints & ATH9K_INT_GTT) | |
3092 | mask2 |= AR_IMR_S2_GTT; | |
3093 | if (ints & ATH9K_INT_CST) | |
3094 | mask2 |= AR_IMR_S2_CST; | |
3095 | } | |
3096 | ||
04bd4638 | 3097 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
f078f209 LR |
3098 | REG_WRITE(ah, AR_IMR, mask); |
3099 | mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | | |
3100 | AR_IMR_S2_DTIM | | |
3101 | AR_IMR_S2_DTIMSYNC | | |
3102 | AR_IMR_S2_CABEND | | |
3103 | AR_IMR_S2_CABTO | | |
3104 | AR_IMR_S2_TSFOOR | | |
3105 | AR_IMR_S2_GTT | AR_IMR_S2_CST); | |
3106 | REG_WRITE(ah, AR_IMR_S2, mask | mask2); | |
2660b81a | 3107 | ah->mask_reg = ints; |
f078f209 | 3108 | |
60b67f51 | 3109 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
3110 | if (ints & ATH9K_INT_TIM_TIMER) |
3111 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
3112 | else | |
3113 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
3114 | } | |
3115 | ||
3116 | if (ints & ATH9K_INT_GLOBAL) { | |
04bd4638 | 3117 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n"); |
f078f209 LR |
3118 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
3119 | if (!AR_SREV_9100(ah)) { | |
3120 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | |
3121 | AR_INTR_MAC_IRQ); | |
3122 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | |
3123 | ||
3124 | ||
3125 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | |
3126 | AR_INTR_SYNC_DEFAULT); | |
3127 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | |
3128 | AR_INTR_SYNC_DEFAULT); | |
3129 | } | |
3130 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | |
3131 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | |
3132 | } | |
3133 | ||
3134 | return omask; | |
3135 | } | |
3136 | ||
f1dc5600 S |
3137 | /*******************/ |
3138 | /* Beacon Handling */ | |
3139 | /*******************/ | |
3140 | ||
cbe61d8a | 3141 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 3142 | { |
f078f209 LR |
3143 | int flags = 0; |
3144 | ||
2660b81a | 3145 | ah->beacon_interval = beacon_period; |
f078f209 | 3146 | |
2660b81a | 3147 | switch (ah->opmode) { |
d97809db CM |
3148 | case NL80211_IFTYPE_STATION: |
3149 | case NL80211_IFTYPE_MONITOR: | |
f078f209 LR |
3150 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
3151 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | |
3152 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | |
3153 | flags |= AR_TBTT_TIMER_EN; | |
3154 | break; | |
d97809db | 3155 | case NL80211_IFTYPE_ADHOC: |
f078f209 LR |
3156 | REG_SET_BIT(ah, AR_TXCFG, |
3157 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
3158 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
3159 | TU_TO_USEC(next_beacon + | |
2660b81a S |
3160 | (ah->atim_window ? ah-> |
3161 | atim_window : 1))); | |
f078f209 | 3162 | flags |= AR_NDP_TIMER_EN; |
d97809db | 3163 | case NL80211_IFTYPE_AP: |
f078f209 LR |
3164 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
3165 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
3166 | TU_TO_USEC(next_beacon - | |
2660b81a | 3167 | ah->config. |
60b67f51 | 3168 | dma_beacon_response_time)); |
f078f209 LR |
3169 | REG_WRITE(ah, AR_NEXT_SWBA, |
3170 | TU_TO_USEC(next_beacon - | |
2660b81a | 3171 | ah->config. |
60b67f51 | 3172 | sw_beacon_response_time)); |
f078f209 LR |
3173 | flags |= |
3174 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
3175 | break; | |
d97809db CM |
3176 | default: |
3177 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, | |
3178 | "%s: unsupported opmode: %d\n", | |
2660b81a | 3179 | __func__, ah->opmode); |
d97809db CM |
3180 | return; |
3181 | break; | |
f078f209 LR |
3182 | } |
3183 | ||
3184 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
3185 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
3186 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
3187 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
3188 | ||
3189 | beacon_period &= ~ATH9K_BEACON_ENA; | |
3190 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
3191 | beacon_period &= ~ATH9K_BEACON_RESET_TSF; | |
3192 | ath9k_hw_reset_tsf(ah); | |
3193 | } | |
3194 | ||
3195 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
3196 | } | |
3197 | ||
cbe61d8a | 3198 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 3199 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
3200 | { |
3201 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 3202 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 LR |
3203 | |
3204 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); | |
3205 | ||
3206 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
3207 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
3208 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
3209 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
3210 | ||
3211 | REG_RMW_FIELD(ah, AR_RSSI_THR, | |
3212 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
3213 | ||
3214 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
3215 | ||
3216 | if (bs->bs_sleepduration > beaconintval) | |
3217 | beaconintval = bs->bs_sleepduration; | |
3218 | ||
3219 | dtimperiod = bs->bs_dtimperiod; | |
3220 | if (bs->bs_sleepduration > dtimperiod) | |
3221 | dtimperiod = bs->bs_sleepduration; | |
3222 | ||
3223 | if (beaconintval == dtimperiod) | |
3224 | nextTbtt = bs->bs_nextdtim; | |
3225 | else | |
3226 | nextTbtt = bs->bs_nexttbtt; | |
3227 | ||
04bd4638 S |
3228 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
3229 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | |
3230 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | |
3231 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 3232 | |
f1dc5600 S |
3233 | REG_WRITE(ah, AR_NEXT_DTIM, |
3234 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
3235 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 3236 | |
f1dc5600 S |
3237 | REG_WRITE(ah, AR_SLEEP1, |
3238 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
3239 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 3240 | |
f1dc5600 S |
3241 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
3242 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
3243 | else | |
3244 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 3245 | |
f1dc5600 S |
3246 | REG_WRITE(ah, AR_SLEEP2, |
3247 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 3248 | |
f1dc5600 S |
3249 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
3250 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 3251 | |
f1dc5600 S |
3252 | REG_SET_BIT(ah, AR_TIMER_MODE, |
3253 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
3254 | AR_DTIM_TIMER_EN); | |
f078f209 | 3255 | |
4af9cf4f S |
3256 | /* TSF Out of Range Threshold */ |
3257 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 LR |
3258 | } |
3259 | ||
f1dc5600 S |
3260 | /*******************/ |
3261 | /* HW Capabilities */ | |
3262 | /*******************/ | |
3263 | ||
cbe61d8a | 3264 | bool ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 3265 | { |
2660b81a | 3266 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f1dc5600 | 3267 | u16 capField = 0, eeval; |
f078f209 | 3268 | |
f74df6fb | 3269 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
d6bad496 | 3270 | ah->regulatory.current_rd = eeval; |
f078f209 | 3271 | |
f74df6fb | 3272 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
fec0de11 S |
3273 | if (AR_SREV_9285_10_OR_LATER(ah)) |
3274 | eeval |= AR9285_RDEXT_DEFAULT; | |
d6bad496 | 3275 | ah->regulatory.current_rd_ext = eeval; |
f078f209 | 3276 | |
f74df6fb | 3277 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
f1dc5600 | 3278 | |
2660b81a | 3279 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 3280 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
d6bad496 S |
3281 | if (ah->regulatory.current_rd == 0x64 || |
3282 | ah->regulatory.current_rd == 0x65) | |
3283 | ah->regulatory.current_rd += 5; | |
3284 | else if (ah->regulatory.current_rd == 0x41) | |
3285 | ah->regulatory.current_rd = 0x43; | |
f1dc5600 | 3286 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, |
d6bad496 | 3287 | "regdomain mapped to 0x%x\n", ah->regulatory.current_rd); |
f1dc5600 | 3288 | } |
f078f209 | 3289 | |
f74df6fb | 3290 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
f1dc5600 | 3291 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
f078f209 | 3292 | |
f1dc5600 S |
3293 | if (eeval & AR5416_OPFLAGS_11A) { |
3294 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); | |
2660b81a | 3295 | if (ah->config.ht_enable) { |
f1dc5600 S |
3296 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
3297 | set_bit(ATH9K_MODE_11NA_HT20, | |
3298 | pCap->wireless_modes); | |
3299 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { | |
3300 | set_bit(ATH9K_MODE_11NA_HT40PLUS, | |
3301 | pCap->wireless_modes); | |
3302 | set_bit(ATH9K_MODE_11NA_HT40MINUS, | |
3303 | pCap->wireless_modes); | |
3304 | } | |
f078f209 | 3305 | } |
f078f209 LR |
3306 | } |
3307 | ||
f1dc5600 S |
3308 | if (eeval & AR5416_OPFLAGS_11G) { |
3309 | set_bit(ATH9K_MODE_11B, pCap->wireless_modes); | |
3310 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); | |
2660b81a | 3311 | if (ah->config.ht_enable) { |
f1dc5600 S |
3312 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
3313 | set_bit(ATH9K_MODE_11NG_HT20, | |
3314 | pCap->wireless_modes); | |
3315 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { | |
3316 | set_bit(ATH9K_MODE_11NG_HT40PLUS, | |
3317 | pCap->wireless_modes); | |
3318 | set_bit(ATH9K_MODE_11NG_HT40MINUS, | |
3319 | pCap->wireless_modes); | |
3320 | } | |
3321 | } | |
f078f209 | 3322 | } |
f1dc5600 | 3323 | |
f74df6fb | 3324 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
8147f5de S |
3325 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
3326 | !(eeval & AR5416_OPFLAGS_11A)) | |
3327 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; | |
3328 | else | |
3329 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); | |
f078f209 | 3330 | |
d535a42a | 3331 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
2660b81a | 3332 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 3333 | |
f1dc5600 S |
3334 | pCap->low_2ghz_chan = 2312; |
3335 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 3336 | |
f1dc5600 S |
3337 | pCap->low_5ghz_chan = 4920; |
3338 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 3339 | |
f1dc5600 S |
3340 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
3341 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; | |
3342 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; | |
f078f209 | 3343 | |
f1dc5600 S |
3344 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
3345 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | |
3346 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | |
f078f209 | 3347 | |
f1dc5600 | 3348 | pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; |
f078f209 | 3349 | |
2660b81a | 3350 | if (ah->config.ht_enable) |
f1dc5600 S |
3351 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
3352 | else | |
3353 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 3354 | |
f1dc5600 S |
3355 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
3356 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; | |
3357 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; | |
3358 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; | |
f078f209 | 3359 | |
f1dc5600 S |
3360 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
3361 | pCap->total_queues = | |
3362 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
3363 | else | |
3364 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 3365 | |
f1dc5600 S |
3366 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
3367 | pCap->keycache_size = | |
3368 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
3369 | else | |
3370 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 3371 | |
f1dc5600 S |
3372 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
3373 | pCap->num_mr_retries = 4; | |
3374 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 3375 | |
cb33c412 SB |
3376 | if (AR_SREV_9285_10_OR_LATER(ah)) |
3377 | pCap->num_gpio_pins = AR9285_NUM_GPIO; | |
3378 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
f1dc5600 S |
3379 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
3380 | else | |
3381 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 3382 | |
f1dc5600 S |
3383 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
3384 | pCap->hw_caps |= ATH9K_HW_CAP_WOW; | |
3385 | pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | |
3386 | } else { | |
3387 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW; | |
3388 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | |
f078f209 LR |
3389 | } |
3390 | ||
f1dc5600 S |
3391 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
3392 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
3393 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
3394 | } else { | |
3395 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
3396 | } |
3397 | ||
f1dc5600 S |
3398 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
3399 | ||
e97275cb | 3400 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
3401 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
3402 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
3403 | ah->rfkill_gpio = | |
3404 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
3405 | ah->rfkill_polarity = | |
3406 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
3407 | |
3408 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 3409 | } |
f1dc5600 | 3410 | #endif |
f078f209 | 3411 | |
d535a42a S |
3412 | if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || |
3413 | (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) || | |
3414 | (ah->hw_version.macVersion == AR_SREV_VERSION_9160) || | |
3415 | (ah->hw_version.macVersion == AR_SREV_VERSION_9100) || | |
3416 | (ah->hw_version.macVersion == AR_SREV_VERSION_9280)) | |
f1dc5600 | 3417 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
f078f209 | 3418 | else |
f1dc5600 | 3419 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
f078f209 | 3420 | |
e7594072 | 3421 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
3422 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
3423 | else | |
3424 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 3425 | |
d6bad496 | 3426 | if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
f1dc5600 S |
3427 | pCap->reg_cap = |
3428 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
3429 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
3430 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
3431 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 3432 | } else { |
f1dc5600 S |
3433 | pCap->reg_cap = |
3434 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
3435 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 3436 | } |
f078f209 | 3437 | |
f1dc5600 S |
3438 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
3439 | ||
3440 | pCap->num_antcfg_5ghz = | |
f74df6fb | 3441 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
f1dc5600 | 3442 | pCap->num_antcfg_2ghz = |
f74df6fb | 3443 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
f078f209 | 3444 | |
138ab2e4 | 3445 | if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { |
c97c92d9 | 3446 | pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; |
2660b81a S |
3447 | ah->btactive_gpio = 6; |
3448 | ah->wlanactive_gpio = 5; | |
c97c92d9 VT |
3449 | } |
3450 | ||
f1dc5600 | 3451 | return true; |
f078f209 LR |
3452 | } |
3453 | ||
cbe61d8a | 3454 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 3455 | u32 capability, u32 *result) |
f078f209 | 3456 | { |
f1dc5600 S |
3457 | switch (type) { |
3458 | case ATH9K_CAP_CIPHER: | |
3459 | switch (capability) { | |
3460 | case ATH9K_CIPHER_AES_CCM: | |
3461 | case ATH9K_CIPHER_AES_OCB: | |
3462 | case ATH9K_CIPHER_TKIP: | |
3463 | case ATH9K_CIPHER_WEP: | |
3464 | case ATH9K_CIPHER_MIC: | |
3465 | case ATH9K_CIPHER_CLR: | |
3466 | return true; | |
3467 | default: | |
3468 | return false; | |
3469 | } | |
3470 | case ATH9K_CAP_TKIP_MIC: | |
3471 | switch (capability) { | |
3472 | case 0: | |
3473 | return true; | |
3474 | case 1: | |
2660b81a | 3475 | return (ah->sta_id1_defaults & |
f1dc5600 S |
3476 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
3477 | false; | |
3478 | } | |
3479 | case ATH9K_CAP_TKIP_SPLIT: | |
2660b81a | 3480 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
f1dc5600 | 3481 | false : true; |
f1dc5600 S |
3482 | case ATH9K_CAP_DIVERSITY: |
3483 | return (REG_READ(ah, AR_PHY_CCK_DETECT) & | |
3484 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? | |
3485 | true : false; | |
f1dc5600 S |
3486 | case ATH9K_CAP_MCAST_KEYSRCH: |
3487 | switch (capability) { | |
3488 | case 0: | |
3489 | return true; | |
3490 | case 1: | |
3491 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { | |
3492 | return false; | |
3493 | } else { | |
2660b81a | 3494 | return (ah->sta_id1_defaults & |
f1dc5600 S |
3495 | AR_STA_ID1_MCAST_KSRCH) ? true : |
3496 | false; | |
3497 | } | |
3498 | } | |
3499 | return false; | |
f1dc5600 S |
3500 | case ATH9K_CAP_TXPOW: |
3501 | switch (capability) { | |
3502 | case 0: | |
3503 | return 0; | |
3504 | case 1: | |
d6bad496 | 3505 | *result = ah->regulatory.power_limit; |
f1dc5600 S |
3506 | return 0; |
3507 | case 2: | |
d6bad496 | 3508 | *result = ah->regulatory.max_power_level; |
f1dc5600 S |
3509 | return 0; |
3510 | case 3: | |
d6bad496 | 3511 | *result = ah->regulatory.tp_scale; |
f1dc5600 S |
3512 | return 0; |
3513 | } | |
3514 | return false; | |
8bd1d07f SB |
3515 | case ATH9K_CAP_DS: |
3516 | return (AR_SREV_9280_20_OR_LATER(ah) && | |
3517 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) | |
3518 | ? false : true; | |
f1dc5600 S |
3519 | default: |
3520 | return false; | |
f078f209 | 3521 | } |
f078f209 LR |
3522 | } |
3523 | ||
cbe61d8a | 3524 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 3525 | u32 capability, u32 setting, int *status) |
f078f209 | 3526 | { |
f1dc5600 | 3527 | u32 v; |
f078f209 | 3528 | |
f1dc5600 S |
3529 | switch (type) { |
3530 | case ATH9K_CAP_TKIP_MIC: | |
3531 | if (setting) | |
2660b81a | 3532 | ah->sta_id1_defaults |= |
f1dc5600 S |
3533 | AR_STA_ID1_CRPT_MIC_ENABLE; |
3534 | else | |
2660b81a | 3535 | ah->sta_id1_defaults &= |
f1dc5600 S |
3536 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
3537 | return true; | |
3538 | case ATH9K_CAP_DIVERSITY: | |
3539 | v = REG_READ(ah, AR_PHY_CCK_DETECT); | |
3540 | if (setting) | |
3541 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
3542 | else | |
3543 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
3544 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); | |
3545 | return true; | |
3546 | case ATH9K_CAP_MCAST_KEYSRCH: | |
3547 | if (setting) | |
2660b81a | 3548 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 3549 | else |
2660b81a | 3550 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 3551 | return true; |
f1dc5600 S |
3552 | default: |
3553 | return false; | |
f078f209 LR |
3554 | } |
3555 | } | |
3556 | ||
f1dc5600 S |
3557 | /****************************/ |
3558 | /* GPIO / RFKILL / Antennae */ | |
3559 | /****************************/ | |
f078f209 | 3560 | |
cbe61d8a | 3561 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
3562 | u32 gpio, u32 type) |
3563 | { | |
3564 | int addr; | |
3565 | u32 gpio_shift, tmp; | |
f078f209 | 3566 | |
f1dc5600 S |
3567 | if (gpio > 11) |
3568 | addr = AR_GPIO_OUTPUT_MUX3; | |
3569 | else if (gpio > 5) | |
3570 | addr = AR_GPIO_OUTPUT_MUX2; | |
3571 | else | |
3572 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 3573 | |
f1dc5600 | 3574 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 3575 | |
f1dc5600 S |
3576 | if (AR_SREV_9280_20_OR_LATER(ah) |
3577 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
3578 | REG_RMW(ah, addr, (type << gpio_shift), | |
3579 | (0x1f << gpio_shift)); | |
f078f209 | 3580 | } else { |
f1dc5600 S |
3581 | tmp = REG_READ(ah, addr); |
3582 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
3583 | tmp &= ~(0x1f << gpio_shift); | |
3584 | tmp |= (type << gpio_shift); | |
3585 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 3586 | } |
f078f209 LR |
3587 | } |
3588 | ||
cbe61d8a | 3589 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 3590 | { |
f1dc5600 | 3591 | u32 gpio_shift; |
f078f209 | 3592 | |
2660b81a | 3593 | ASSERT(gpio < ah->caps.num_gpio_pins); |
f078f209 | 3594 | |
f1dc5600 | 3595 | gpio_shift = gpio << 1; |
f078f209 | 3596 | |
f1dc5600 S |
3597 | REG_RMW(ah, |
3598 | AR_GPIO_OE_OUT, | |
3599 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
3600 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 LR |
3601 | } |
3602 | ||
cbe61d8a | 3603 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 3604 | { |
cb33c412 SB |
3605 | #define MS_REG_READ(x, y) \ |
3606 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
3607 | ||
2660b81a | 3608 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 3609 | return 0xffffffff; |
f078f209 | 3610 | |
cb33c412 SB |
3611 | if (AR_SREV_9285_10_OR_LATER(ah)) |
3612 | return MS_REG_READ(AR9285, gpio) != 0; | |
3613 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
3614 | return MS_REG_READ(AR928X, gpio) != 0; | |
3615 | else | |
3616 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 LR |
3617 | } |
3618 | ||
cbe61d8a | 3619 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 3620 | u32 ah_signal_type) |
f078f209 | 3621 | { |
f1dc5600 | 3622 | u32 gpio_shift; |
f078f209 | 3623 | |
f1dc5600 | 3624 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f078f209 | 3625 | |
f1dc5600 | 3626 | gpio_shift = 2 * gpio; |
f078f209 | 3627 | |
f1dc5600 S |
3628 | REG_RMW(ah, |
3629 | AR_GPIO_OE_OUT, | |
3630 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
3631 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 LR |
3632 | } |
3633 | ||
cbe61d8a | 3634 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 3635 | { |
f1dc5600 S |
3636 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
3637 | AR_GPIO_BIT(gpio)); | |
f078f209 LR |
3638 | } |
3639 | ||
e97275cb | 3640 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
cbe61d8a | 3641 | void ath9k_enable_rfkill(struct ath_hw *ah) |
f078f209 | 3642 | { |
f1dc5600 S |
3643 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, |
3644 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | |
f078f209 | 3645 | |
f1dc5600 S |
3646 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, |
3647 | AR_GPIO_INPUT_MUX2_RFSILENT); | |
3648 | ||
2660b81a | 3649 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
f1dc5600 | 3650 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); |
f078f209 | 3651 | } |
f1dc5600 | 3652 | #endif |
f078f209 | 3653 | |
cbe61d8a | 3654 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 3655 | { |
f1dc5600 | 3656 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 LR |
3657 | } |
3658 | ||
cbe61d8a | 3659 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 3660 | { |
f1dc5600 | 3661 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 LR |
3662 | } |
3663 | ||
cbe61d8a | 3664 | bool ath9k_hw_setantennaswitch(struct ath_hw *ah, |
f1dc5600 S |
3665 | enum ath9k_ant_setting settings, |
3666 | struct ath9k_channel *chan, | |
3667 | u8 *tx_chainmask, | |
3668 | u8 *rx_chainmask, | |
3669 | u8 *antenna_cfgd) | |
f078f209 | 3670 | { |
f1dc5600 | 3671 | static u8 tx_chainmask_cfg, rx_chainmask_cfg; |
f078f209 | 3672 | |
f1dc5600 S |
3673 | if (AR_SREV_9280(ah)) { |
3674 | if (!tx_chainmask_cfg) { | |
f078f209 | 3675 | |
f1dc5600 S |
3676 | tx_chainmask_cfg = *tx_chainmask; |
3677 | rx_chainmask_cfg = *rx_chainmask; | |
3678 | } | |
f078f209 | 3679 | |
f1dc5600 S |
3680 | switch (settings) { |
3681 | case ATH9K_ANT_FIXED_A: | |
3682 | *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | |
3683 | *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | |
3684 | *antenna_cfgd = true; | |
3685 | break; | |
3686 | case ATH9K_ANT_FIXED_B: | |
2660b81a | 3687 | if (ah->caps.tx_chainmask > |
f1dc5600 S |
3688 | ATH9K_ANTENNA1_CHAINMASK) { |
3689 | *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | |
3690 | } | |
3691 | *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | |
3692 | *antenna_cfgd = true; | |
3693 | break; | |
3694 | case ATH9K_ANT_VARIABLE: | |
3695 | *tx_chainmask = tx_chainmask_cfg; | |
3696 | *rx_chainmask = rx_chainmask_cfg; | |
3697 | *antenna_cfgd = true; | |
3698 | break; | |
3699 | default: | |
3700 | break; | |
3701 | } | |
3702 | } else { | |
2660b81a | 3703 | ah->diversity_control = settings; |
f078f209 | 3704 | } |
f078f209 | 3705 | |
f1dc5600 | 3706 | return true; |
f078f209 LR |
3707 | } |
3708 | ||
f1dc5600 S |
3709 | /*********************/ |
3710 | /* General Operation */ | |
3711 | /*********************/ | |
3712 | ||
cbe61d8a | 3713 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 3714 | { |
f1dc5600 S |
3715 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
3716 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 3717 | |
f1dc5600 S |
3718 | if (phybits & AR_PHY_ERR_RADAR) |
3719 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
3720 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
3721 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 3722 | |
f1dc5600 | 3723 | return bits; |
f078f209 LR |
3724 | } |
3725 | ||
cbe61d8a | 3726 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 3727 | { |
f1dc5600 | 3728 | u32 phybits; |
f078f209 | 3729 | |
f1dc5600 S |
3730 | REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); |
3731 | phybits = 0; | |
3732 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
3733 | phybits |= AR_PHY_ERR_RADAR; | |
3734 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
3735 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
3736 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 3737 | |
f1dc5600 S |
3738 | if (phybits) |
3739 | REG_WRITE(ah, AR_RXCFG, | |
3740 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
3741 | else | |
3742 | REG_WRITE(ah, AR_RXCFG, | |
3743 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
3744 | } | |
f078f209 | 3745 | |
cbe61d8a | 3746 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 S |
3747 | { |
3748 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); | |
3749 | } | |
f078f209 | 3750 | |
cbe61d8a | 3751 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 S |
3752 | { |
3753 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | |
3754 | return false; | |
f078f209 | 3755 | |
f1dc5600 | 3756 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); |
f078f209 LR |
3757 | } |
3758 | ||
cbe61d8a | 3759 | bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
f078f209 | 3760 | { |
2660b81a | 3761 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 3762 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 3763 | |
d6bad496 | 3764 | ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 3765 | |
f74df6fb S |
3766 | if (ah->eep_ops->set_txpower(ah, chan, |
3767 | ath9k_regd_get_ctl(ah, chan), | |
3768 | channel->max_antenna_gain * 2, | |
3769 | channel->max_power * 2, | |
3770 | min((u32) MAX_RATE_POWER, | |
3771 | (u32) ah->regulatory.power_limit)) != 0) | |
6f255425 | 3772 | return false; |
f1dc5600 | 3773 | |
6f255425 LR |
3774 | return true; |
3775 | } | |
3776 | ||
cbe61d8a | 3777 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
f078f209 | 3778 | { |
ba52da58 | 3779 | memcpy(ah->macaddr, mac, ETH_ALEN); |
f078f209 LR |
3780 | } |
3781 | ||
cbe61d8a | 3782 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 3783 | { |
2660b81a | 3784 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 LR |
3785 | } |
3786 | ||
cbe61d8a | 3787 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 3788 | { |
f1dc5600 S |
3789 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
3790 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 LR |
3791 | } |
3792 | ||
ba52da58 | 3793 | void ath9k_hw_setbssidmask(struct ath_softc *sc) |
f078f209 | 3794 | { |
ba52da58 S |
3795 | REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); |
3796 | REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); | |
f078f209 LR |
3797 | } |
3798 | ||
ba52da58 | 3799 | void ath9k_hw_write_associd(struct ath_softc *sc) |
f078f209 | 3800 | { |
ba52da58 S |
3801 | REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); |
3802 | REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | | |
3803 | ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 LR |
3804 | } |
3805 | ||
cbe61d8a | 3806 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 3807 | { |
f1dc5600 | 3808 | u64 tsf; |
f078f209 | 3809 | |
f1dc5600 S |
3810 | tsf = REG_READ(ah, AR_TSF_U32); |
3811 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); | |
f078f209 | 3812 | |
f1dc5600 S |
3813 | return tsf; |
3814 | } | |
f078f209 | 3815 | |
cbe61d8a | 3816 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 3817 | { |
27abe060 | 3818 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 3819 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 AF |
3820 | } |
3821 | ||
cbe61d8a | 3822 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 S |
3823 | { |
3824 | int count; | |
f078f209 | 3825 | |
f1dc5600 S |
3826 | count = 0; |
3827 | while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { | |
3828 | count++; | |
3829 | if (count > 10) { | |
3830 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
04bd4638 | 3831 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
f1dc5600 | 3832 | break; |
f078f209 | 3833 | } |
f1dc5600 S |
3834 | udelay(10); |
3835 | } | |
3836 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); | |
3837 | } | |
f078f209 | 3838 | |
cbe61d8a | 3839 | bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 3840 | { |
f1dc5600 | 3841 | if (setting) |
2660b81a | 3842 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3843 | else |
2660b81a | 3844 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f078f209 | 3845 | |
f1dc5600 S |
3846 | return true; |
3847 | } | |
f078f209 | 3848 | |
cbe61d8a | 3849 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f1dc5600 | 3850 | { |
f1dc5600 | 3851 | if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { |
04bd4638 | 3852 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); |
2660b81a | 3853 | ah->slottime = (u32) -1; |
f1dc5600 S |
3854 | return false; |
3855 | } else { | |
3856 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); | |
2660b81a | 3857 | ah->slottime = us; |
f1dc5600 | 3858 | return true; |
f078f209 | 3859 | } |
f1dc5600 S |
3860 | } |
3861 | ||
cbe61d8a | 3862 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) |
f1dc5600 S |
3863 | { |
3864 | u32 macmode; | |
3865 | ||
3866 | if (mode == ATH9K_HT_MACMODE_2040 && | |
2660b81a | 3867 | !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
3868 | macmode = AR_2040_JOINED_RX_CLEAR; |
3869 | else | |
3870 | macmode = 0; | |
f078f209 | 3871 | |
f1dc5600 | 3872 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 3873 | } |
c97c92d9 VT |
3874 | |
3875 | /***************************/ | |
3876 | /* Bluetooth Coexistence */ | |
3877 | /***************************/ | |
3878 | ||
cbe61d8a | 3879 | void ath9k_hw_btcoex_enable(struct ath_hw *ah) |
c97c92d9 VT |
3880 | { |
3881 | /* connect bt_active to baseband */ | |
3882 | REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, | |
3883 | (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | | |
3884 | AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); | |
3885 | ||
3886 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | |
3887 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); | |
3888 | ||
3889 | /* Set input mux for bt_active to gpio pin */ | |
3890 | REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, | |
3891 | AR_GPIO_INPUT_MUX1_BT_ACTIVE, | |
2660b81a | 3892 | ah->btactive_gpio); |
c97c92d9 VT |
3893 | |
3894 | /* Configure the desired gpio port for input */ | |
2660b81a | 3895 | ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio); |
c97c92d9 VT |
3896 | |
3897 | /* Configure the desired GPIO port for TX_FRAME output */ | |
2660b81a | 3898 | ath9k_hw_cfg_output(ah, ah->wlanactive_gpio, |
c97c92d9 VT |
3899 | AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); |
3900 | } |