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Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <asm/unaligned.h> | |
19 | ||
20 | #include "core.h" | |
21 | #include "hw.h" | |
22 | #include "reg.h" | |
23 | #include "phy.h" | |
24 | #include "initvals.h" | |
25 | ||
f078f209 | 26 | static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; |
f078f209 | 27 | |
f1dc5600 S |
28 | extern struct hal_percal_data iq_cal_multi_sample; |
29 | extern struct hal_percal_data iq_cal_single_sample; | |
30 | extern struct hal_percal_data adc_gain_cal_multi_sample; | |
31 | extern struct hal_percal_data adc_gain_cal_single_sample; | |
32 | extern struct hal_percal_data adc_dc_cal_multi_sample; | |
33 | extern struct hal_percal_data adc_dc_cal_single_sample; | |
34 | extern struct hal_percal_data adc_init_dc_cal; | |
f078f209 | 35 | |
f1dc5600 S |
36 | static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); |
37 | static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, | |
38 | enum ath9k_ht_macmode macmode); | |
39 | static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, | |
40 | struct ar5416_eeprom *pEepData, | |
41 | u32 reg, u32 value); | |
42 | static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); | |
43 | static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); | |
f078f209 | 44 | |
f1dc5600 S |
45 | /********************/ |
46 | /* Helper Functions */ | |
47 | /********************/ | |
f078f209 | 48 | |
f1dc5600 S |
49 | static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) |
50 | { | |
51 | if (ah->ah_curchan != NULL) | |
52 | return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]; | |
53 | else | |
54 | return clks / CLOCK_RATE[ATH9K_MODE_11B]; | |
55 | } | |
f078f209 | 56 | |
f1dc5600 S |
57 | static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) |
58 | { | |
59 | struct ath9k_channel *chan = ah->ah_curchan; | |
f078f209 | 60 | |
f1dc5600 S |
61 | if (chan && IS_CHAN_HT40(chan)) |
62 | return ath9k_hw_mac_usec(ah, clks) / 2; | |
63 | else | |
64 | return ath9k_hw_mac_usec(ah, clks); | |
65 | } | |
f078f209 | 66 | |
f1dc5600 S |
67 | static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) |
68 | { | |
69 | if (ah->ah_curchan != NULL) | |
70 | return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, | |
71 | ah->ah_curchan)]; | |
72 | else | |
73 | return usecs * CLOCK_RATE[ATH9K_MODE_11B]; | |
74 | } | |
75 | ||
76 | static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) | |
77 | { | |
78 | struct ath9k_channel *chan = ah->ah_curchan; | |
79 | ||
80 | if (chan && IS_CHAN_HT40(chan)) | |
81 | return ath9k_hw_mac_clks(ah, usecs) * 2; | |
82 | else | |
83 | return ath9k_hw_mac_clks(ah, usecs); | |
84 | } | |
f078f209 | 85 | |
f1dc5600 S |
86 | enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, |
87 | const struct ath9k_channel *chan) | |
f078f209 LR |
88 | { |
89 | if (IS_CHAN_CCK(chan)) | |
86b89eed | 90 | return ATH9K_MODE_11A; |
f078f209 | 91 | if (IS_CHAN_G(chan)) |
86b89eed S |
92 | return ATH9K_MODE_11G; |
93 | return ATH9K_MODE_11A; | |
f078f209 LR |
94 | } |
95 | ||
f1dc5600 | 96 | bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) |
f078f209 LR |
97 | { |
98 | int i; | |
99 | ||
100 | for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) { | |
101 | if ((REG_READ(ah, reg) & mask) == val) | |
102 | return true; | |
103 | ||
104 | udelay(AH_TIME_QUANTUM); | |
105 | } | |
106 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | |
f1dc5600 S |
107 | "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
108 | __func__, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 109 | |
f1dc5600 | 110 | return false; |
f078f209 LR |
111 | } |
112 | ||
113 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
114 | { | |
115 | u32 retval; | |
116 | int i; | |
117 | ||
118 | for (i = 0, retval = 0; i < n; i++) { | |
119 | retval = (retval << 1) | (val & 1); | |
120 | val >>= 1; | |
121 | } | |
122 | return retval; | |
123 | } | |
124 | ||
f1dc5600 S |
125 | bool ath9k_get_channel_edges(struct ath_hal *ah, |
126 | u16 flags, u16 *low, | |
127 | u16 *high) | |
f078f209 | 128 | { |
f1dc5600 | 129 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
f078f209 | 130 | |
f1dc5600 S |
131 | if (flags & CHANNEL_5GHZ) { |
132 | *low = pCap->low_5ghz_chan; | |
133 | *high = pCap->high_5ghz_chan; | |
134 | return true; | |
f078f209 | 135 | } |
f1dc5600 S |
136 | if ((flags & CHANNEL_2GHZ)) { |
137 | *low = pCap->low_2ghz_chan; | |
138 | *high = pCap->high_2ghz_chan; | |
139 | return true; | |
140 | } | |
141 | return false; | |
f078f209 LR |
142 | } |
143 | ||
f1dc5600 S |
144 | u16 ath9k_hw_computetxtime(struct ath_hal *ah, |
145 | const struct ath9k_rate_table *rates, | |
146 | u32 frameLen, u16 rateix, | |
147 | bool shortPreamble) | |
f078f209 | 148 | { |
f1dc5600 S |
149 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
150 | u32 kbps; | |
f078f209 | 151 | |
f1dc5600 | 152 | kbps = rates->info[rateix].rateKbps; |
f078f209 | 153 | |
f1dc5600 S |
154 | if (kbps == 0) |
155 | return 0; | |
f078f209 | 156 | |
f1dc5600 S |
157 | switch (rates->info[rateix].phy) { |
158 | case PHY_CCK: | |
159 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; | |
160 | if (shortPreamble && rates->info[rateix].shortPreamble) | |
161 | phyTime >>= 1; | |
162 | numBits = frameLen << 3; | |
163 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
164 | break; | |
165 | case PHY_OFDM: | |
166 | if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { | |
167 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; | |
168 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
169 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
170 | txTime = OFDM_SIFS_TIME_QUARTER | |
171 | + OFDM_PREAMBLE_TIME_QUARTER | |
172 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
173 | } else if (ah->ah_curchan && | |
174 | IS_CHAN_HALF_RATE(ah->ah_curchan)) { | |
175 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; | |
176 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
177 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
178 | txTime = OFDM_SIFS_TIME_HALF + | |
179 | OFDM_PREAMBLE_TIME_HALF | |
180 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
181 | } else { | |
182 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
183 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
184 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
185 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
186 | + (numSymbols * OFDM_SYMBOL_TIME); | |
187 | } | |
188 | break; | |
189 | default: | |
190 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | |
191 | "%s: unknown phy %u (rate ix %u)\n", __func__, | |
192 | rates->info[rateix].phy, rateix); | |
193 | txTime = 0; | |
194 | break; | |
195 | } | |
f078f209 | 196 | |
f1dc5600 S |
197 | return txTime; |
198 | } | |
f078f209 | 199 | |
f1dc5600 S |
200 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags) |
201 | { | |
202 | if (flags & CHANNEL_2GHZ) { | |
203 | if (freq == 2484) | |
204 | return 14; | |
205 | if (freq < 2484) | |
206 | return (freq - 2407) / 5; | |
207 | else | |
208 | return 15 + ((freq - 2512) / 20); | |
209 | } else if (flags & CHANNEL_5GHZ) { | |
210 | if (ath9k_regd_is_public_safety_sku(ah) && | |
211 | IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { | |
212 | return ((freq * 10) + | |
213 | (((freq % 5) == 2) ? 5 : 0) - 49400) / 5; | |
214 | } else if ((flags & CHANNEL_A) && (freq <= 5000)) { | |
215 | return (freq - 4000) / 5; | |
216 | } else { | |
217 | return (freq - 5000) / 5; | |
218 | } | |
219 | } else { | |
220 | if (freq == 2484) | |
221 | return 14; | |
222 | if (freq < 2484) | |
223 | return (freq - 2407) / 5; | |
224 | if (freq < 5000) { | |
225 | if (ath9k_regd_is_public_safety_sku(ah) | |
226 | && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { | |
227 | return ((freq * 10) + | |
228 | (((freq % 5) == | |
229 | 2) ? 5 : 0) - 49400) / 5; | |
230 | } else if (freq > 4900) { | |
231 | return (freq - 4000) / 5; | |
232 | } else { | |
233 | return 15 + ((freq - 2512) / 20); | |
234 | } | |
235 | } | |
236 | return (freq - 5000) / 5; | |
237 | } | |
f078f209 LR |
238 | } |
239 | ||
f1dc5600 S |
240 | void ath9k_hw_get_channel_centers(struct ath_hal *ah, |
241 | struct ath9k_channel *chan, | |
242 | struct chan_centers *centers) | |
f078f209 | 243 | { |
f1dc5600 | 244 | int8_t extoff; |
f078f209 LR |
245 | struct ath_hal_5416 *ahp = AH5416(ah); |
246 | ||
f1dc5600 S |
247 | if (!IS_CHAN_HT40(chan)) { |
248 | centers->ctl_center = centers->ext_center = | |
249 | centers->synth_center = chan->channel; | |
250 | return; | |
f078f209 | 251 | } |
f078f209 | 252 | |
f1dc5600 S |
253 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
254 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
255 | centers->synth_center = | |
256 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
257 | extoff = 1; | |
258 | } else { | |
259 | centers->synth_center = | |
260 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
261 | extoff = -1; | |
262 | } | |
f078f209 | 263 | |
f1dc5600 S |
264 | centers->ctl_center = |
265 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
266 | centers->ext_center = | |
267 | centers->synth_center + (extoff * | |
268 | ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? | |
269 | HT40_CHANNEL_CENTER_SHIFT : 15)); | |
f078f209 | 270 | |
f078f209 LR |
271 | } |
272 | ||
f1dc5600 S |
273 | /******************/ |
274 | /* Chip Revisions */ | |
275 | /******************/ | |
276 | ||
277 | static void ath9k_hw_read_revisions(struct ath_hal *ah) | |
f078f209 | 278 | { |
f1dc5600 | 279 | u32 val; |
f078f209 | 280 | |
f1dc5600 | 281 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 282 | |
f1dc5600 S |
283 | if (val == 0xFF) { |
284 | val = REG_READ(ah, AR_SREV); | |
285 | ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
286 | ah->ah_macRev = MS(val, AR_SREV_REVISION2); | |
287 | ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; | |
288 | } else { | |
289 | if (!AR_SREV_9100(ah)) | |
290 | ah->ah_macVersion = MS(val, AR_SREV_VERSION); | |
f078f209 | 291 | |
f1dc5600 | 292 | ah->ah_macRev = val & AR_SREV_REVISION; |
f078f209 | 293 | |
f1dc5600 S |
294 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) |
295 | ah->ah_isPciExpress = true; | |
296 | } | |
f078f209 LR |
297 | } |
298 | ||
f1dc5600 | 299 | static int ath9k_hw_get_radiorev(struct ath_hal *ah) |
f078f209 | 300 | { |
f1dc5600 S |
301 | u32 val; |
302 | int i; | |
f078f209 | 303 | |
f1dc5600 | 304 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
f078f209 | 305 | |
f1dc5600 S |
306 | for (i = 0; i < 8; i++) |
307 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); | |
308 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; | |
309 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); | |
f078f209 | 310 | |
f1dc5600 | 311 | return ath9k_hw_reverse_bits(val, 8); |
f078f209 LR |
312 | } |
313 | ||
f1dc5600 S |
314 | /************************************/ |
315 | /* HW Attach, Detach, Init Routines */ | |
316 | /************************************/ | |
317 | ||
318 | static void ath9k_hw_disablepcie(struct ath_hal *ah) | |
f078f209 | 319 | { |
f1dc5600 S |
320 | if (!AR_SREV_9100(ah)) |
321 | return; | |
f078f209 | 322 | |
f1dc5600 S |
323 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
324 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
325 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
326 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
327 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
328 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
329 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
330 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
331 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 332 | |
f1dc5600 | 333 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
334 | } |
335 | ||
f1dc5600 | 336 | static bool ath9k_hw_chip_test(struct ath_hal *ah) |
f078f209 | 337 | { |
f1dc5600 S |
338 | u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; |
339 | u32 regHold[2]; | |
340 | u32 patternData[4] = { 0x55555555, | |
341 | 0xaaaaaaaa, | |
342 | 0x66666666, | |
343 | 0x99999999 }; | |
344 | int i, j; | |
f078f209 | 345 | |
f1dc5600 S |
346 | for (i = 0; i < 2; i++) { |
347 | u32 addr = regAddr[i]; | |
348 | u32 wrData, rdData; | |
f078f209 | 349 | |
f1dc5600 S |
350 | regHold[i] = REG_READ(ah, addr); |
351 | for (j = 0; j < 0x100; j++) { | |
352 | wrData = (j << 16) | j; | |
353 | REG_WRITE(ah, addr, wrData); | |
354 | rdData = REG_READ(ah, addr); | |
355 | if (rdData != wrData) { | |
356 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
357 | "%s: address test failed " | |
358 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
359 | __func__, addr, wrData, rdData); | |
360 | return false; | |
361 | } | |
362 | } | |
363 | for (j = 0; j < 4; j++) { | |
364 | wrData = patternData[j]; | |
365 | REG_WRITE(ah, addr, wrData); | |
366 | rdData = REG_READ(ah, addr); | |
367 | if (wrData != rdData) { | |
368 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
369 | "%s: address test failed " | |
370 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
371 | __func__, addr, wrData, rdData); | |
372 | return false; | |
373 | } | |
f078f209 | 374 | } |
f1dc5600 | 375 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 376 | } |
f1dc5600 | 377 | udelay(100); |
f078f209 LR |
378 | return true; |
379 | } | |
380 | ||
f1dc5600 | 381 | static const char *ath9k_hw_devname(u16 devid) |
f078f209 | 382 | { |
f1dc5600 S |
383 | switch (devid) { |
384 | case AR5416_DEVID_PCI: | |
f1dc5600 | 385 | return "Atheros 5416"; |
392dff83 BP |
386 | case AR5416_DEVID_PCIE: |
387 | return "Atheros 5418"; | |
f1dc5600 S |
388 | case AR9160_DEVID_PCI: |
389 | return "Atheros 9160"; | |
390 | case AR9280_DEVID_PCI: | |
391 | case AR9280_DEVID_PCIE: | |
392 | return "Atheros 9280"; | |
f078f209 LR |
393 | } |
394 | ||
f1dc5600 S |
395 | return NULL; |
396 | } | |
f078f209 | 397 | |
f1dc5600 S |
398 | static void ath9k_hw_set_defaults(struct ath_hal *ah) |
399 | { | |
400 | int i; | |
f078f209 | 401 | |
f1dc5600 S |
402 | ah->ah_config.dma_beacon_response_time = 2; |
403 | ah->ah_config.sw_beacon_response_time = 10; | |
404 | ah->ah_config.additional_swba_backoff = 0; | |
405 | ah->ah_config.ack_6mb = 0x0; | |
406 | ah->ah_config.cwm_ignore_extcca = 0; | |
407 | ah->ah_config.pcie_powersave_enable = 0; | |
408 | ah->ah_config.pcie_l1skp_enable = 0; | |
409 | ah->ah_config.pcie_clock_req = 0; | |
410 | ah->ah_config.pcie_power_reset = 0x100; | |
411 | ah->ah_config.pcie_restore = 0; | |
412 | ah->ah_config.pcie_waen = 0; | |
413 | ah->ah_config.analog_shiftreg = 1; | |
414 | ah->ah_config.ht_enable = 1; | |
415 | ah->ah_config.ofdm_trig_low = 200; | |
416 | ah->ah_config.ofdm_trig_high = 500; | |
417 | ah->ah_config.cck_trig_high = 200; | |
418 | ah->ah_config.cck_trig_low = 100; | |
419 | ah->ah_config.enable_ani = 1; | |
420 | ah->ah_config.noise_immunity_level = 4; | |
421 | ah->ah_config.ofdm_weaksignal_det = 1; | |
422 | ah->ah_config.cck_weaksignal_thr = 0; | |
423 | ah->ah_config.spur_immunity_level = 2; | |
424 | ah->ah_config.firstep_level = 0; | |
425 | ah->ah_config.rssi_thr_high = 40; | |
426 | ah->ah_config.rssi_thr_low = 7; | |
427 | ah->ah_config.diversity_control = 0; | |
428 | ah->ah_config.antenna_switch_swap = 0; | |
f078f209 | 429 | |
f1dc5600 S |
430 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
431 | ah->ah_config.spurchans[i][0] = AR_NO_SPUR; | |
432 | ah->ah_config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
433 | } |
434 | ||
f1dc5600 | 435 | ah->ah_config.intr_mitigation = 1; |
f078f209 LR |
436 | } |
437 | ||
f078f209 LR |
438 | static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, |
439 | struct ath_softc *sc, | |
440 | void __iomem *mem, | |
441 | int *status) | |
442 | { | |
443 | static const u8 defbssidmask[ETH_ALEN] = | |
444 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
445 | struct ath_hal_5416 *ahp; | |
446 | struct ath_hal *ah; | |
447 | ||
448 | ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); | |
449 | if (ahp == NULL) { | |
450 | DPRINTF(sc, ATH_DBG_FATAL, | |
f1dc5600 S |
451 | "%s: cannot allocate memory for state block\n", |
452 | __func__); | |
f078f209 LR |
453 | *status = -ENOMEM; |
454 | return NULL; | |
455 | } | |
456 | ||
457 | ah = &ahp->ah; | |
f078f209 LR |
458 | ah->ah_sc = sc; |
459 | ah->ah_sh = mem; | |
d2d80ee9 S |
460 | ah->ah_magic = AR5416_MAGIC; |
461 | ah->ah_countryCode = CTRY_DEFAULT; | |
f078f209 LR |
462 | ah->ah_devid = devid; |
463 | ah->ah_subvendorid = 0; | |
464 | ||
465 | ah->ah_flags = 0; | |
466 | if ((devid == AR5416_AR9100_DEVID)) | |
467 | ah->ah_macVersion = AR_SREV_VERSION_9100; | |
468 | if (!AR_SREV_9100(ah)) | |
469 | ah->ah_flags = AH_USE_EEPROM; | |
470 | ||
471 | ah->ah_powerLimit = MAX_RATE_POWER; | |
472 | ah->ah_tpScale = ATH9K_TP_SCALE_MAX; | |
f078f209 | 473 | ahp->ah_atimWindow = 0; |
60b67f51 | 474 | ahp->ah_diversityControl = ah->ah_config.diversity_control; |
f078f209 | 475 | ahp->ah_antennaSwitchSwap = |
60b67f51 | 476 | ah->ah_config.antenna_switch_swap; |
f078f209 LR |
477 | ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
478 | ahp->ah_beaconInterval = 100; | |
479 | ahp->ah_enable32kHzClock = DONT_USE_32KHZ; | |
480 | ahp->ah_slottime = (u32) -1; | |
481 | ahp->ah_acktimeout = (u32) -1; | |
482 | ahp->ah_ctstimeout = (u32) -1; | |
483 | ahp->ah_globaltxtimeout = (u32) -1; | |
484 | memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN); | |
485 | ||
486 | ahp->ah_gBeaconRate = 0; | |
487 | ||
488 | return ahp; | |
489 | } | |
490 | ||
f1dc5600 | 491 | static int ath9k_hw_rfattach(struct ath_hal *ah) |
f078f209 | 492 | { |
f1dc5600 S |
493 | bool rfStatus = false; |
494 | int ecode = 0; | |
f078f209 | 495 | |
f1dc5600 S |
496 | rfStatus = ath9k_hw_init_rf(ah, &ecode); |
497 | if (!rfStatus) { | |
498 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
499 | "%s: RF setup failed, status %u\n", __func__, | |
500 | ecode); | |
501 | return ecode; | |
502 | } | |
f078f209 | 503 | |
f1dc5600 | 504 | return 0; |
f078f209 LR |
505 | } |
506 | ||
f1dc5600 | 507 | static int ath9k_hw_rf_claim(struct ath_hal *ah) |
f078f209 | 508 | { |
f1dc5600 S |
509 | u32 val; |
510 | ||
511 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
512 | ||
513 | val = ath9k_hw_get_radiorev(ah); | |
514 | switch (val & AR_RADIO_SREV_MAJOR) { | |
515 | case 0: | |
516 | val = AR_RAD5133_SREV_MAJOR; | |
517 | break; | |
518 | case AR_RAD5133_SREV_MAJOR: | |
519 | case AR_RAD5122_SREV_MAJOR: | |
520 | case AR_RAD2133_SREV_MAJOR: | |
521 | case AR_RAD2122_SREV_MAJOR: | |
522 | break; | |
f078f209 | 523 | default: |
f1dc5600 S |
524 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, |
525 | "%s: 5G Radio Chip Rev 0x%02X is not " | |
526 | "supported by this driver\n", | |
527 | __func__, ah->ah_analog5GhzRev); | |
528 | return -EOPNOTSUPP; | |
f078f209 | 529 | } |
f078f209 | 530 | |
f1dc5600 | 531 | ah->ah_analog5GhzRev = val; |
f078f209 | 532 | |
f1dc5600 | 533 | return 0; |
f078f209 LR |
534 | } |
535 | ||
ff9b662d | 536 | static int ath9k_hw_init_macaddr(struct ath_hal *ah) |
f078f209 LR |
537 | { |
538 | u32 sum; | |
539 | int i; | |
540 | u16 eeval; | |
541 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f078f209 LR |
542 | |
543 | sum = 0; | |
544 | for (i = 0; i < 3; i++) { | |
f1dc5600 | 545 | eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); |
f078f209 LR |
546 | sum += eeval; |
547 | ahp->ah_macaddr[2 * i] = eeval >> 8; | |
548 | ahp->ah_macaddr[2 * i + 1] = eeval & 0xff; | |
549 | } | |
550 | if (sum == 0 || sum == 0xffff * 3) { | |
551 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
f1dc5600 S |
552 | "%s: mac address read failed: %pM\n", __func__, |
553 | ahp->ah_macaddr); | |
f078f209 LR |
554 | return -EADDRNOTAVAIL; |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
f1dc5600 | 560 | static int ath9k_hw_post_attach(struct ath_hal *ah) |
f078f209 | 561 | { |
f1dc5600 | 562 | int ecode; |
f078f209 | 563 | |
f1dc5600 S |
564 | if (!ath9k_hw_chip_test(ah)) { |
565 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
566 | "%s: hardware self-test failed\n", __func__); | |
567 | return -ENODEV; | |
f078f209 | 568 | } |
f078f209 | 569 | |
f1dc5600 S |
570 | ecode = ath9k_hw_rf_claim(ah); |
571 | if (ecode != 0) | |
f078f209 | 572 | return ecode; |
f078f209 | 573 | |
f1dc5600 S |
574 | ecode = ath9k_hw_eeprom_attach(ah); |
575 | if (ecode != 0) | |
576 | return ecode; | |
577 | ecode = ath9k_hw_rfattach(ah); | |
578 | if (ecode != 0) | |
579 | return ecode; | |
f078f209 | 580 | |
f1dc5600 S |
581 | if (!AR_SREV_9100(ah)) { |
582 | ath9k_hw_ani_setup(ah); | |
583 | ath9k_hw_ani_attach(ah); | |
f078f209 LR |
584 | } |
585 | ||
f078f209 LR |
586 | return 0; |
587 | } | |
588 | ||
f1dc5600 S |
589 | static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, |
590 | void __iomem *mem, int *status) | |
f078f209 | 591 | { |
f1dc5600 S |
592 | struct ath_hal_5416 *ahp; |
593 | struct ath_hal *ah; | |
594 | int ecode; | |
595 | #ifndef CONFIG_SLOW_ANT_DIV | |
596 | u32 i; | |
597 | u32 j; | |
598 | #endif | |
f078f209 | 599 | |
f1dc5600 S |
600 | ahp = ath9k_hw_newstate(devid, sc, mem, status); |
601 | if (ahp == NULL) | |
602 | return NULL; | |
f078f209 | 603 | |
f1dc5600 | 604 | ah = &ahp->ah; |
f078f209 | 605 | |
f1dc5600 | 606 | ath9k_hw_set_defaults(ah); |
f078f209 | 607 | |
f1dc5600 S |
608 | if (ah->ah_config.intr_mitigation != 0) |
609 | ahp->ah_intrMitigation = true; | |
f078f209 | 610 | |
f1dc5600 S |
611 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
612 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n", | |
613 | __func__); | |
614 | ecode = -EIO; | |
615 | goto bad; | |
616 | } | |
f078f209 | 617 | |
f1dc5600 S |
618 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
619 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n", | |
620 | __func__); | |
621 | ecode = -EIO; | |
622 | goto bad; | |
623 | } | |
f078f209 | 624 | |
f1dc5600 S |
625 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { |
626 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { | |
627 | ah->ah_config.serialize_regmode = | |
628 | SER_REG_MODE_ON; | |
f078f209 | 629 | } else { |
f1dc5600 S |
630 | ah->ah_config.serialize_regmode = |
631 | SER_REG_MODE_OFF; | |
f078f209 LR |
632 | } |
633 | } | |
f078f209 | 634 | |
f1dc5600 S |
635 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, |
636 | "%s: serialize_regmode is %d\n", | |
637 | __func__, ah->ah_config.serialize_regmode); | |
f078f209 | 638 | |
f1dc5600 S |
639 | if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && |
640 | (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && | |
641 | (ah->ah_macVersion != AR_SREV_VERSION_9160) && | |
642 | (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { | |
643 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
644 | "%s: Mac Chip Rev 0x%02x.%x is not supported by " | |
645 | "this driver\n", __func__, | |
646 | ah->ah_macVersion, ah->ah_macRev); | |
647 | ecode = -EOPNOTSUPP; | |
648 | goto bad; | |
649 | } | |
f078f209 | 650 | |
f1dc5600 S |
651 | if (AR_SREV_9100(ah)) { |
652 | ahp->ah_iqCalData.calData = &iq_cal_multi_sample; | |
653 | ahp->ah_suppCals = IQ_MISMATCH_CAL; | |
654 | ah->ah_isPciExpress = false; | |
655 | } | |
656 | ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); | |
f078f209 | 657 | |
f1dc5600 S |
658 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
659 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
660 | ahp->ah_iqCalData.calData = &iq_cal_single_sample; | |
661 | ahp->ah_adcGainCalData.calData = | |
662 | &adc_gain_cal_single_sample; | |
663 | ahp->ah_adcDcCalData.calData = | |
664 | &adc_dc_cal_single_sample; | |
665 | ahp->ah_adcDcCalInitData.calData = | |
666 | &adc_init_dc_cal; | |
667 | } else { | |
668 | ahp->ah_iqCalData.calData = &iq_cal_multi_sample; | |
669 | ahp->ah_adcGainCalData.calData = | |
670 | &adc_gain_cal_multi_sample; | |
671 | ahp->ah_adcDcCalData.calData = | |
672 | &adc_dc_cal_multi_sample; | |
673 | ahp->ah_adcDcCalInitData.calData = | |
674 | &adc_init_dc_cal; | |
675 | } | |
676 | ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; | |
677 | } | |
f078f209 | 678 | |
f1dc5600 S |
679 | if (AR_SREV_9160(ah)) { |
680 | ah->ah_config.enable_ani = 1; | |
681 | ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | | |
682 | ATH9K_ANI_FIRSTEP_LEVEL); | |
683 | } else { | |
684 | ahp->ah_ani_function = ATH9K_ANI_ALL; | |
685 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
686 | ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; | |
687 | } | |
f078f209 | 688 | } |
f078f209 | 689 | |
f1dc5600 S |
690 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, |
691 | "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, | |
692 | ah->ah_macVersion, ah->ah_macRev); | |
f078f209 | 693 | |
f1dc5600 S |
694 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
695 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, | |
696 | ARRAY_SIZE(ar9280Modes_9280_2), 6); | |
697 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, | |
698 | ARRAY_SIZE(ar9280Common_9280_2), 2); | |
f078f209 | 699 | |
f1dc5600 S |
700 | if (ah->ah_config.pcie_clock_req) { |
701 | INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, | |
702 | ar9280PciePhy_clkreq_off_L1_9280, | |
703 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); | |
704 | } else { | |
705 | INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, | |
706 | ar9280PciePhy_clkreq_always_on_L1_9280, | |
707 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | |
708 | } | |
709 | INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, | |
710 | ar9280Modes_fast_clock_9280_2, | |
711 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | |
712 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { | |
713 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, | |
714 | ARRAY_SIZE(ar9280Modes_9280), 6); | |
715 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, | |
716 | ARRAY_SIZE(ar9280Common_9280), 2); | |
717 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
718 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, | |
719 | ARRAY_SIZE(ar5416Modes_9160), 6); | |
720 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, | |
721 | ARRAY_SIZE(ar5416Common_9160), 2); | |
722 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, | |
723 | ARRAY_SIZE(ar5416Bank0_9160), 2); | |
724 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, | |
725 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); | |
726 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, | |
727 | ARRAY_SIZE(ar5416Bank1_9160), 2); | |
728 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, | |
729 | ARRAY_SIZE(ar5416Bank2_9160), 2); | |
730 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, | |
731 | ARRAY_SIZE(ar5416Bank3_9160), 3); | |
732 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, | |
733 | ARRAY_SIZE(ar5416Bank6_9160), 3); | |
734 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, | |
735 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); | |
736 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, | |
737 | ARRAY_SIZE(ar5416Bank7_9160), 2); | |
738 | if (AR_SREV_9160_11(ah)) { | |
739 | INIT_INI_ARRAY(&ahp->ah_iniAddac, | |
740 | ar5416Addac_91601_1, | |
741 | ARRAY_SIZE(ar5416Addac_91601_1), 2); | |
742 | } else { | |
743 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, | |
744 | ARRAY_SIZE(ar5416Addac_9160), 2); | |
745 | } | |
746 | } else if (AR_SREV_9100_OR_LATER(ah)) { | |
747 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, | |
748 | ARRAY_SIZE(ar5416Modes_9100), 6); | |
749 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, | |
750 | ARRAY_SIZE(ar5416Common_9100), 2); | |
751 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, | |
752 | ARRAY_SIZE(ar5416Bank0_9100), 2); | |
753 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, | |
754 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); | |
755 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, | |
756 | ARRAY_SIZE(ar5416Bank1_9100), 2); | |
757 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, | |
758 | ARRAY_SIZE(ar5416Bank2_9100), 2); | |
759 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, | |
760 | ARRAY_SIZE(ar5416Bank3_9100), 3); | |
761 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, | |
762 | ARRAY_SIZE(ar5416Bank6_9100), 3); | |
763 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, | |
764 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); | |
765 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, | |
766 | ARRAY_SIZE(ar5416Bank7_9100), 2); | |
767 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, | |
768 | ARRAY_SIZE(ar5416Addac_9100), 2); | |
769 | } else { | |
770 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, | |
771 | ARRAY_SIZE(ar5416Modes), 6); | |
772 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, | |
773 | ARRAY_SIZE(ar5416Common), 2); | |
774 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, | |
775 | ARRAY_SIZE(ar5416Bank0), 2); | |
776 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, | |
777 | ARRAY_SIZE(ar5416BB_RfGain), 3); | |
778 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, | |
779 | ARRAY_SIZE(ar5416Bank1), 2); | |
780 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, | |
781 | ARRAY_SIZE(ar5416Bank2), 2); | |
782 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, | |
783 | ARRAY_SIZE(ar5416Bank3), 3); | |
784 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, | |
785 | ARRAY_SIZE(ar5416Bank6), 3); | |
786 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, | |
787 | ARRAY_SIZE(ar5416Bank6TPC), 3); | |
788 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, | |
789 | ARRAY_SIZE(ar5416Bank7), 2); | |
790 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, | |
791 | ARRAY_SIZE(ar5416Addac), 2); | |
f078f209 | 792 | } |
f078f209 | 793 | |
f1dc5600 S |
794 | if (ah->ah_isPciExpress) |
795 | ath9k_hw_configpcipowersave(ah, 0); | |
796 | else | |
797 | ath9k_hw_disablepcie(ah); | |
f078f209 | 798 | |
f1dc5600 S |
799 | ecode = ath9k_hw_post_attach(ah); |
800 | if (ecode != 0) | |
801 | goto bad; | |
f078f209 | 802 | |
f1dc5600 S |
803 | #ifndef CONFIG_SLOW_ANT_DIV |
804 | if (ah->ah_devid == AR9280_DEVID_PCI) { | |
805 | for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { | |
806 | u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); | |
f078f209 | 807 | |
f1dc5600 S |
808 | for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { |
809 | u32 val = INI_RA(&ahp->ah_iniModes, i, j); | |
f078f209 | 810 | |
f1dc5600 S |
811 | INI_RA(&ahp->ah_iniModes, i, j) = |
812 | ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, | |
813 | reg, val); | |
814 | } | |
f078f209 | 815 | } |
f1dc5600 S |
816 | } |
817 | #endif | |
818 | if (!ath9k_hw_fill_cap_info(ah)) { | |
819 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
820 | "%s:failed ath9k_hw_fill_cap_info\n", __func__); | |
821 | ecode = -EINVAL; | |
822 | goto bad; | |
f078f209 LR |
823 | } |
824 | ||
f1dc5600 S |
825 | ecode = ath9k_hw_init_macaddr(ah); |
826 | if (ecode != 0) { | |
f078f209 | 827 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, |
f1dc5600 | 828 | "%s: failed initializing mac address\n", |
f078f209 | 829 | __func__); |
f1dc5600 | 830 | goto bad; |
f078f209 LR |
831 | } |
832 | ||
f1dc5600 S |
833 | if (AR_SREV_9285(ah)) |
834 | ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); | |
835 | else | |
836 | ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); | |
f078f209 | 837 | |
f1dc5600 | 838 | ath9k_init_nfcal_hist_buffer(ah); |
f078f209 | 839 | |
f1dc5600 S |
840 | return ah; |
841 | bad: | |
842 | if (ahp) | |
843 | ath9k_hw_detach((struct ath_hal *) ahp); | |
844 | if (status) | |
845 | *status = ecode; | |
f078f209 | 846 | |
f1dc5600 | 847 | return NULL; |
f078f209 LR |
848 | } |
849 | ||
f1dc5600 S |
850 | static void ath9k_hw_init_bb(struct ath_hal *ah, |
851 | struct ath9k_channel *chan) | |
f078f209 | 852 | { |
f1dc5600 | 853 | u32 synthDelay; |
f078f209 | 854 | |
f1dc5600 S |
855 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
856 | if (IS_CHAN_CCK(chan)) | |
857 | synthDelay = (4 * synthDelay) / 22; | |
858 | else | |
859 | synthDelay /= 10; | |
f078f209 | 860 | |
f1dc5600 | 861 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
f078f209 | 862 | |
f1dc5600 | 863 | udelay(synthDelay + BASE_ACTIVATE_DELAY); |
f078f209 LR |
864 | } |
865 | ||
f1dc5600 | 866 | static void ath9k_hw_init_qos(struct ath_hal *ah) |
f078f209 | 867 | { |
f1dc5600 S |
868 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
869 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 870 | |
f1dc5600 S |
871 | REG_WRITE(ah, AR_QOS_NO_ACK, |
872 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
873 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
874 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
875 | ||
876 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
877 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
878 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
879 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
880 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
f078f209 LR |
881 | } |
882 | ||
f1dc5600 S |
883 | static void ath9k_hw_init_pll(struct ath_hal *ah, |
884 | struct ath9k_channel *chan) | |
f078f209 | 885 | { |
f1dc5600 | 886 | u32 pll; |
f078f209 | 887 | |
f1dc5600 S |
888 | if (AR_SREV_9100(ah)) { |
889 | if (chan && IS_CHAN_5GHZ(chan)) | |
890 | pll = 0x1450; | |
f078f209 | 891 | else |
f1dc5600 S |
892 | pll = 0x1458; |
893 | } else { | |
894 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
895 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | |
f078f209 | 896 | |
f1dc5600 S |
897 | if (chan && IS_CHAN_HALF_RATE(chan)) |
898 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
899 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
900 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 901 | |
f1dc5600 S |
902 | if (chan && IS_CHAN_5GHZ(chan)) { |
903 | pll |= SM(0x28, AR_RTC_9160_PLL_DIV); | |
f078f209 | 904 | |
f078f209 | 905 | |
f1dc5600 S |
906 | if (AR_SREV_9280_20(ah)) { |
907 | if (((chan->channel % 20) == 0) | |
908 | || ((chan->channel % 10) == 0)) | |
909 | pll = 0x2850; | |
910 | else | |
911 | pll = 0x142c; | |
912 | } | |
913 | } else { | |
914 | pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); | |
915 | } | |
f078f209 | 916 | |
f1dc5600 | 917 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
f078f209 | 918 | |
f1dc5600 | 919 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); |
f078f209 | 920 | |
f1dc5600 S |
921 | if (chan && IS_CHAN_HALF_RATE(chan)) |
922 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
923 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
924 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
f078f209 | 925 | |
f1dc5600 S |
926 | if (chan && IS_CHAN_5GHZ(chan)) |
927 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | |
928 | else | |
929 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | |
930 | } else { | |
931 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | |
f078f209 | 932 | |
f1dc5600 S |
933 | if (chan && IS_CHAN_HALF_RATE(chan)) |
934 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | |
935 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
936 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | |
f078f209 | 937 | |
f1dc5600 S |
938 | if (chan && IS_CHAN_5GHZ(chan)) |
939 | pll |= SM(0xa, AR_RTC_PLL_DIV); | |
940 | else | |
941 | pll |= SM(0xb, AR_RTC_PLL_DIV); | |
942 | } | |
943 | } | |
944 | REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll); | |
f078f209 | 945 | |
f1dc5600 S |
946 | udelay(RTC_PLL_SETTLE_DELAY); |
947 | ||
948 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
949 | } |
950 | ||
ff9b662d | 951 | static void ath9k_hw_init_chain_masks(struct ath_hal *ah) |
f078f209 LR |
952 | { |
953 | struct ath_hal_5416 *ahp = AH5416(ah); | |
954 | int rx_chainmask, tx_chainmask; | |
955 | ||
956 | rx_chainmask = ahp->ah_rxchainmask; | |
957 | tx_chainmask = ahp->ah_txchainmask; | |
958 | ||
959 | switch (rx_chainmask) { | |
960 | case 0x5: | |
961 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
962 | AR_PHY_SWAP_ALT_CHAIN); | |
963 | case 0x3: | |
964 | if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { | |
965 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); | |
966 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); | |
967 | break; | |
968 | } | |
969 | case 0x1: | |
970 | case 0x2: | |
971 | if (!AR_SREV_9280(ah)) | |
972 | break; | |
973 | case 0x7: | |
974 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
975 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
976 | break; | |
977 | default: | |
978 | break; | |
979 | } | |
980 | ||
981 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); | |
982 | if (tx_chainmask == 0x5) { | |
983 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
984 | AR_PHY_SWAP_ALT_CHAIN); | |
985 | } | |
986 | if (AR_SREV_9100(ah)) | |
987 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, | |
988 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); | |
989 | } | |
990 | ||
f1dc5600 | 991 | static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode) |
f078f209 | 992 | { |
f078f209 | 993 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 | 994 | |
f1dc5600 S |
995 | ahp->ah_maskReg = AR_IMR_TXERR | |
996 | AR_IMR_TXURN | | |
997 | AR_IMR_RXERR | | |
998 | AR_IMR_RXORN | | |
999 | AR_IMR_BCNMISC; | |
f078f209 | 1000 | |
f1dc5600 S |
1001 | if (ahp->ah_intrMitigation) |
1002 | ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
f078f209 | 1003 | else |
f1dc5600 | 1004 | ahp->ah_maskReg |= AR_IMR_RXOK; |
f078f209 | 1005 | |
f1dc5600 | 1006 | ahp->ah_maskReg |= AR_IMR_TXOK; |
f078f209 | 1007 | |
f1dc5600 S |
1008 | if (opmode == ATH9K_M_HOSTAP) |
1009 | ahp->ah_maskReg |= AR_IMR_MIB; | |
f078f209 | 1010 | |
f1dc5600 S |
1011 | REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); |
1012 | REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); | |
f078f209 | 1013 | |
f1dc5600 S |
1014 | if (!AR_SREV_9100(ah)) { |
1015 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
1016 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
1017 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
1018 | } | |
f078f209 LR |
1019 | } |
1020 | ||
1021 | static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) | |
1022 | { | |
1023 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1024 | ||
1025 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { | |
1026 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n", | |
1027 | __func__, us); | |
1028 | ahp->ah_acktimeout = (u32) -1; | |
1029 | return false; | |
1030 | } else { | |
1031 | REG_RMW_FIELD(ah, AR_TIME_OUT, | |
1032 | AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); | |
1033 | ahp->ah_acktimeout = us; | |
1034 | return true; | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) | |
1039 | { | |
1040 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1041 | ||
1042 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { | |
1043 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n", | |
1044 | __func__, us); | |
1045 | ahp->ah_ctstimeout = (u32) -1; | |
1046 | return false; | |
1047 | } else { | |
1048 | REG_RMW_FIELD(ah, AR_TIME_OUT, | |
1049 | AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); | |
1050 | ahp->ah_ctstimeout = us; | |
1051 | return true; | |
1052 | } | |
1053 | } | |
f1dc5600 S |
1054 | |
1055 | static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) | |
f078f209 LR |
1056 | { |
1057 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1058 | ||
1059 | if (tu > 0xFFFF) { | |
1060 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | |
1061 | "%s: bad global tx timeout %u\n", __func__, tu); | |
1062 | ahp->ah_globaltxtimeout = (u32) -1; | |
1063 | return false; | |
1064 | } else { | |
1065 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
1066 | ahp->ah_globaltxtimeout = tu; | |
1067 | return true; | |
1068 | } | |
1069 | } | |
1070 | ||
f1dc5600 | 1071 | static void ath9k_hw_init_user_settings(struct ath_hal *ah) |
f078f209 LR |
1072 | { |
1073 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1074 | ||
f1dc5600 S |
1075 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n", |
1076 | __func__, ahp->ah_miscMode); | |
1077 | ||
1078 | if (ahp->ah_miscMode != 0) | |
1079 | REG_WRITE(ah, AR_PCU_MISC, | |
1080 | REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); | |
1081 | if (ahp->ah_slottime != (u32) -1) | |
1082 | ath9k_hw_setslottime(ah, ahp->ah_slottime); | |
1083 | if (ahp->ah_acktimeout != (u32) -1) | |
1084 | ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); | |
1085 | if (ahp->ah_ctstimeout != (u32) -1) | |
1086 | ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); | |
1087 | if (ahp->ah_globaltxtimeout != (u32) -1) | |
1088 | ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); | |
1089 | } | |
1090 | ||
1091 | const char *ath9k_hw_probe(u16 vendorid, u16 devid) | |
1092 | { | |
1093 | return vendorid == ATHEROS_VENDOR_ID ? | |
1094 | ath9k_hw_devname(devid) : NULL; | |
1095 | } | |
1096 | ||
1097 | void ath9k_hw_detach(struct ath_hal *ah) | |
1098 | { | |
1099 | if (!AR_SREV_9100(ah)) | |
1100 | ath9k_hw_ani_detach(ah); | |
1101 | ||
1102 | ath9k_hw_rfdetach(ah); | |
1103 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | |
1104 | kfree(ah); | |
1105 | } | |
1106 | ||
1107 | struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, | |
1108 | void __iomem *mem, int *error) | |
1109 | { | |
1110 | struct ath_hal *ah = NULL; | |
1111 | ||
1112 | switch (devid) { | |
1113 | case AR5416_DEVID_PCI: | |
1114 | case AR5416_DEVID_PCIE: | |
1115 | case AR9160_DEVID_PCI: | |
1116 | case AR9280_DEVID_PCI: | |
1117 | case AR9280_DEVID_PCIE: | |
1118 | ah = ath9k_hw_do_attach(devid, sc, mem, error); | |
1119 | break; | |
1120 | default: | |
1121 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1122 | "devid=0x%x not supported.\n", devid); | |
1123 | ah = NULL; | |
1124 | *error = -ENXIO; | |
1125 | break; | |
f078f209 | 1126 | } |
f1dc5600 S |
1127 | |
1128 | return ah; | |
1129 | } | |
1130 | ||
1131 | /*******/ | |
1132 | /* INI */ | |
1133 | /*******/ | |
1134 | ||
1135 | static void ath9k_hw_override_ini(struct ath_hal *ah, | |
1136 | struct ath9k_channel *chan) | |
1137 | { | |
1138 | if (!AR_SREV_5416_V20_OR_LATER(ah) || | |
1139 | AR_SREV_9280_10_OR_LATER(ah)) | |
1140 | return; | |
1141 | ||
1142 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); | |
f078f209 LR |
1143 | } |
1144 | ||
f1dc5600 S |
1145 | static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, |
1146 | struct ar5416_eeprom *pEepData, | |
1147 | u32 reg, u32 value) | |
f078f209 | 1148 | { |
f1dc5600 | 1149 | struct base_eep_header *pBase = &(pEepData->baseEepHeader); |
f078f209 | 1150 | |
f1dc5600 S |
1151 | switch (ah->ah_devid) { |
1152 | case AR9280_DEVID_PCI: | |
1153 | if (reg == 0x7894) { | |
1154 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1155 | "ini VAL: %x EEPROM: %x\n", value, | |
1156 | (pBase->version & 0xff)); | |
1157 | ||
1158 | if ((pBase->version & 0xff) > 0x0a) { | |
1159 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1160 | "PWDCLKIND: %d\n", | |
1161 | pBase->pwdclkind); | |
1162 | value &= ~AR_AN_TOP2_PWDCLKIND; | |
1163 | value |= AR_AN_TOP2_PWDCLKIND & | |
1164 | (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); | |
1165 | } else { | |
1166 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1167 | "PWDCLKIND Earlier Rev\n"); | |
1168 | } | |
1169 | ||
1170 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
1171 | "final ini VAL: %x\n", value); | |
1172 | } | |
1173 | break; | |
1174 | } | |
1175 | ||
1176 | return value; | |
f078f209 LR |
1177 | } |
1178 | ||
f1dc5600 S |
1179 | static int ath9k_hw_process_ini(struct ath_hal *ah, |
1180 | struct ath9k_channel *chan, | |
1181 | enum ath9k_ht_macmode macmode) | |
f078f209 LR |
1182 | { |
1183 | int i, regWrites = 0; | |
1184 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1185 | u32 modesIndex, freqIndex; | |
1186 | int status; | |
1187 | ||
1188 | switch (chan->chanmode) { | |
1189 | case CHANNEL_A: | |
1190 | case CHANNEL_A_HT20: | |
1191 | modesIndex = 1; | |
1192 | freqIndex = 1; | |
1193 | break; | |
1194 | case CHANNEL_A_HT40PLUS: | |
1195 | case CHANNEL_A_HT40MINUS: | |
1196 | modesIndex = 2; | |
1197 | freqIndex = 1; | |
1198 | break; | |
1199 | case CHANNEL_G: | |
1200 | case CHANNEL_G_HT20: | |
1201 | case CHANNEL_B: | |
1202 | modesIndex = 4; | |
1203 | freqIndex = 2; | |
1204 | break; | |
1205 | case CHANNEL_G_HT40PLUS: | |
1206 | case CHANNEL_G_HT40MINUS: | |
1207 | modesIndex = 3; | |
1208 | freqIndex = 2; | |
1209 | break; | |
1210 | ||
1211 | default: | |
1212 | return -EINVAL; | |
1213 | } | |
1214 | ||
1215 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
1216 | ||
1217 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); | |
1218 | ||
1219 | ath9k_hw_set_addac(ah, chan); | |
1220 | ||
1221 | if (AR_SREV_5416_V22_OR_LATER(ah)) { | |
1222 | REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); | |
1223 | } else { | |
1224 | struct ar5416IniArray temp; | |
1225 | u32 addacSize = | |
1226 | sizeof(u32) * ahp->ah_iniAddac.ia_rows * | |
1227 | ahp->ah_iniAddac.ia_columns; | |
1228 | ||
1229 | memcpy(ahp->ah_addac5416_21, | |
1230 | ahp->ah_iniAddac.ia_array, addacSize); | |
1231 | ||
f1dc5600 | 1232 | (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; |
f078f209 LR |
1233 | |
1234 | temp.ia_array = ahp->ah_addac5416_21; | |
1235 | temp.ia_columns = ahp->ah_iniAddac.ia_columns; | |
1236 | temp.ia_rows = ahp->ah_iniAddac.ia_rows; | |
1237 | REG_WRITE_ARRAY(&temp, 1, regWrites); | |
1238 | } | |
f1dc5600 | 1239 | |
f078f209 LR |
1240 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); |
1241 | ||
1242 | for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { | |
1243 | u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); | |
1244 | u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); | |
1245 | ||
1246 | #ifdef CONFIG_SLOW_ANT_DIV | |
1247 | if (ah->ah_devid == AR9280_DEVID_PCI) | |
f1dc5600 | 1248 | val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val); |
f078f209 LR |
1249 | #endif |
1250 | ||
1251 | REG_WRITE(ah, reg, val); | |
1252 | ||
1253 | if (reg >= 0x7800 && reg < 0x78a0 | |
60b67f51 | 1254 | && ah->ah_config.analog_shiftreg) { |
f078f209 LR |
1255 | udelay(100); |
1256 | } | |
1257 | ||
1258 | DO_DELAY(regWrites); | |
1259 | } | |
1260 | ||
1261 | for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { | |
1262 | u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); | |
1263 | u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); | |
1264 | ||
1265 | REG_WRITE(ah, reg, val); | |
1266 | ||
1267 | if (reg >= 0x7800 && reg < 0x78a0 | |
60b67f51 | 1268 | && ah->ah_config.analog_shiftreg) { |
f078f209 LR |
1269 | udelay(100); |
1270 | } | |
1271 | ||
1272 | DO_DELAY(regWrites); | |
1273 | } | |
1274 | ||
1275 | ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); | |
1276 | ||
1277 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { | |
1278 | REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, | |
1279 | regWrites); | |
1280 | } | |
1281 | ||
1282 | ath9k_hw_override_ini(ah, chan); | |
1283 | ath9k_hw_set_regs(ah, chan, macmode); | |
1284 | ath9k_hw_init_chain_masks(ah); | |
1285 | ||
f1dc5600 | 1286 | status = ath9k_hw_set_txpower(ah, chan, |
f078f209 LR |
1287 | ath9k_regd_get_ctl(ah, chan), |
1288 | ath9k_regd_get_antenna_allowed(ah, | |
1289 | chan), | |
1290 | chan->maxRegTxPower * 2, | |
1291 | min((u32) MAX_RATE_POWER, | |
1292 | (u32) ah->ah_powerLimit)); | |
1293 | if (status != 0) { | |
1294 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
f1dc5600 | 1295 | "%s: error init'ing transmit power\n", __func__); |
f078f209 LR |
1296 | return -EIO; |
1297 | } | |
1298 | ||
1299 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { | |
1300 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
f1dc5600 | 1301 | "%s: ar5416SetRfRegs failed\n", __func__); |
f078f209 LR |
1302 | return -EIO; |
1303 | } | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
f1dc5600 S |
1308 | /****************************************/ |
1309 | /* Reset and Channel Switching Routines */ | |
1310 | /****************************************/ | |
1311 | ||
1312 | static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) | |
f078f209 | 1313 | { |
f1dc5600 S |
1314 | u32 rfMode = 0; |
1315 | ||
1316 | if (chan == NULL) | |
1317 | return; | |
1318 | ||
1319 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | |
1320 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | |
1321 | ||
1322 | if (!AR_SREV_9280_10_OR_LATER(ah)) | |
1323 | rfMode |= (IS_CHAN_5GHZ(chan)) ? | |
1324 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; | |
1325 | ||
1326 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) | |
1327 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); | |
1328 | ||
1329 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | |
1330 | } | |
1331 | ||
1332 | static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) | |
1333 | { | |
1334 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | |
1335 | } | |
1336 | ||
1337 | static inline void ath9k_hw_set_dma(struct ath_hal *ah) | |
1338 | { | |
1339 | u32 regval; | |
1340 | ||
1341 | regval = REG_READ(ah, AR_AHB_MODE); | |
1342 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
1343 | ||
1344 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; | |
1345 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
1346 | ||
1347 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); | |
1348 | ||
1349 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; | |
1350 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
1351 | ||
1352 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); | |
1353 | ||
1354 | if (AR_SREV_9285(ah)) { | |
1355 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | |
1356 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1357 | } else { | |
1358 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | |
1359 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) | |
1364 | { | |
1365 | u32 val; | |
1366 | ||
1367 | val = REG_READ(ah, AR_STA_ID1); | |
1368 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
1369 | switch (opmode) { | |
1370 | case ATH9K_M_HOSTAP: | |
1371 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP | |
1372 | | AR_STA_ID1_KSRCH_MODE); | |
1373 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1374 | break; |
f1dc5600 S |
1375 | case ATH9K_M_IBSS: |
1376 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC | |
1377 | | AR_STA_ID1_KSRCH_MODE); | |
1378 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1379 | break; |
f1dc5600 S |
1380 | case ATH9K_M_STA: |
1381 | case ATH9K_M_MONITOR: | |
1382 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); | |
f078f209 | 1383 | break; |
f1dc5600 S |
1384 | } |
1385 | } | |
1386 | ||
1387 | static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, | |
1388 | u32 coef_scaled, | |
1389 | u32 *coef_mantissa, | |
1390 | u32 *coef_exponent) | |
1391 | { | |
1392 | u32 coef_exp, coef_man; | |
1393 | ||
1394 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1395 | if ((coef_scaled >> coef_exp) & 0x1) | |
1396 | break; | |
1397 | ||
1398 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1399 | ||
1400 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1401 | ||
1402 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1403 | *coef_exponent = coef_exp - 16; | |
1404 | } | |
1405 | ||
1406 | static void ath9k_hw_set_delta_slope(struct ath_hal *ah, | |
1407 | struct ath9k_channel *chan) | |
1408 | { | |
1409 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | |
1410 | u32 clockMhzScaled = 0x64000000; | |
1411 | struct chan_centers centers; | |
1412 | ||
1413 | if (IS_CHAN_HALF_RATE(chan)) | |
1414 | clockMhzScaled = clockMhzScaled >> 1; | |
1415 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
1416 | clockMhzScaled = clockMhzScaled >> 2; | |
1417 | ||
1418 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1419 | coef_scaled = clockMhzScaled / centers.synth_center; | |
1420 | ||
1421 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
1422 | &ds_coef_exp); | |
1423 | ||
1424 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
1425 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | |
1426 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
1427 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | |
1428 | ||
1429 | coef_scaled = (9 * coef_scaled) / 10; | |
1430 | ||
1431 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
1432 | &ds_coef_exp); | |
1433 | ||
1434 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
1435 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); | |
1436 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
1437 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); | |
1438 | } | |
1439 | ||
1440 | static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) | |
1441 | { | |
1442 | u32 rst_flags; | |
1443 | u32 tmpReg; | |
1444 | ||
1445 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | |
1446 | AR_RTC_FORCE_WAKE_ON_INT); | |
1447 | ||
1448 | if (AR_SREV_9100(ah)) { | |
1449 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1450 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1451 | } else { | |
1452 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1453 | if (tmpReg & | |
1454 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1455 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
1456 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
1457 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
1458 | } else { | |
1459 | REG_WRITE(ah, AR_RC, AR_RC_AHB); | |
1460 | } | |
1461 | ||
1462 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1463 | if (type == ATH9K_RESET_COLD) | |
1464 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1465 | } | |
1466 | ||
1467 | REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags); | |
1468 | udelay(50); | |
1469 | ||
1470 | REG_WRITE(ah, (u16) (AR_RTC_RC), 0); | |
1471 | if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { | |
1472 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
1473 | "%s: RTC stuck in MAC reset\n", | |
1474 | __func__); | |
1475 | return false; | |
1476 | } | |
1477 | ||
1478 | if (!AR_SREV_9100(ah)) | |
1479 | REG_WRITE(ah, AR_RC, 0); | |
1480 | ||
1481 | ath9k_hw_init_pll(ah, NULL); | |
1482 | ||
1483 | if (AR_SREV_9100(ah)) | |
1484 | udelay(50); | |
1485 | ||
1486 | return true; | |
1487 | } | |
1488 | ||
1489 | static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) | |
1490 | { | |
1491 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | |
1492 | AR_RTC_FORCE_WAKE_ON_INT); | |
1493 | ||
1494 | REG_WRITE(ah, (u16) (AR_RTC_RESET), 0); | |
1495 | REG_WRITE(ah, (u16) (AR_RTC_RESET), 1); | |
1496 | ||
1497 | if (!ath9k_hw_wait(ah, | |
1498 | AR_RTC_STATUS, | |
1499 | AR_RTC_STATUS_M, | |
1500 | AR_RTC_STATUS_ON)) { | |
1501 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n", | |
f078f209 | 1502 | __func__); |
f1dc5600 | 1503 | return false; |
f078f209 LR |
1504 | } |
1505 | ||
f1dc5600 S |
1506 | ath9k_hw_read_revisions(ah); |
1507 | ||
1508 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1509 | } | |
1510 | ||
1511 | static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) | |
1512 | { | |
1513 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
1514 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1515 | ||
1516 | switch (type) { | |
1517 | case ATH9K_RESET_POWER_ON: | |
1518 | return ath9k_hw_set_reset_power_on(ah); | |
1519 | break; | |
1520 | case ATH9K_RESET_WARM: | |
1521 | case ATH9K_RESET_COLD: | |
1522 | return ath9k_hw_set_reset(ah, type); | |
1523 | break; | |
1524 | default: | |
1525 | return false; | |
1526 | } | |
f078f209 LR |
1527 | } |
1528 | ||
f1dc5600 S |
1529 | static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, |
1530 | enum ath9k_ht_macmode macmode) | |
f078f209 | 1531 | { |
f1dc5600 | 1532 | u32 phymode; |
f078f209 | 1533 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 | 1534 | |
f1dc5600 S |
1535 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
1536 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; | |
1537 | ||
1538 | if (IS_CHAN_HT40(chan)) { | |
1539 | phymode |= AR_PHY_FC_DYN2040_EN; | |
f078f209 | 1540 | |
f1dc5600 S |
1541 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
1542 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | |
1543 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; | |
f078f209 | 1544 | |
f1dc5600 S |
1545 | if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) |
1546 | phymode |= AR_PHY_FC_DYN2040_EXT_CH; | |
f078f209 | 1547 | } |
f1dc5600 S |
1548 | REG_WRITE(ah, AR_PHY_TURBO, phymode); |
1549 | ||
1550 | ath9k_hw_set11nmac2040(ah, macmode); | |
f078f209 | 1551 | |
f1dc5600 S |
1552 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
1553 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
f078f209 LR |
1554 | } |
1555 | ||
f1dc5600 S |
1556 | static bool ath9k_hw_chip_reset(struct ath_hal *ah, |
1557 | struct ath9k_channel *chan) | |
f078f209 LR |
1558 | { |
1559 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1560 | ||
f1dc5600 S |
1561 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
1562 | return false; | |
f078f209 | 1563 | |
f1dc5600 S |
1564 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
1565 | return false; | |
f078f209 | 1566 | |
f1dc5600 | 1567 | ahp->ah_chipFullSleep = false; |
f078f209 | 1568 | |
f1dc5600 | 1569 | ath9k_hw_init_pll(ah, chan); |
f078f209 | 1570 | |
f1dc5600 | 1571 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1572 | |
f1dc5600 | 1573 | return true; |
f078f209 LR |
1574 | } |
1575 | ||
f1dc5600 S |
1576 | static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah, |
1577 | struct ath9k_channel *chan) | |
f078f209 | 1578 | { |
f1dc5600 S |
1579 | if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) { |
1580 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
1581 | "%s: invalid channel %u/0x%x; not marked as " | |
1582 | "2GHz or 5GHz\n", __func__, chan->channel, | |
1583 | chan->channelFlags); | |
1584 | return NULL; | |
1585 | } | |
f078f209 | 1586 | |
f1dc5600 S |
1587 | if (!IS_CHAN_OFDM(chan) && |
1588 | !IS_CHAN_CCK(chan) && | |
1589 | !IS_CHAN_HT20(chan) && | |
1590 | !IS_CHAN_HT40(chan)) { | |
1591 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
1592 | "%s: invalid channel %u/0x%x; not marked as " | |
1593 | "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", | |
1594 | __func__, chan->channel, chan->channelFlags); | |
1595 | return NULL; | |
f078f209 LR |
1596 | } |
1597 | ||
f1dc5600 | 1598 | return ath9k_regd_check_channel(ah, chan); |
f078f209 LR |
1599 | } |
1600 | ||
f1dc5600 S |
1601 | static bool ath9k_hw_channel_change(struct ath_hal *ah, |
1602 | struct ath9k_channel *chan, | |
1603 | enum ath9k_ht_macmode macmode) | |
f078f209 LR |
1604 | { |
1605 | u32 synthDelay, qnum; | |
f078f209 LR |
1606 | |
1607 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1608 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
1609 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | |
f1dc5600 S |
1610 | "%s: Transmit frames pending on queue %d\n", |
1611 | __func__, qnum); | |
f078f209 LR |
1612 | return false; |
1613 | } | |
1614 | } | |
1615 | ||
1616 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | |
1617 | if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | |
1618 | AR_PHY_RFBUS_GRANT_EN)) { | |
1619 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | |
f1dc5600 | 1620 | "%s: Could not kill baseband RX\n", __func__); |
f078f209 LR |
1621 | return false; |
1622 | } | |
1623 | ||
1624 | ath9k_hw_set_regs(ah, chan, macmode); | |
1625 | ||
1626 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1627 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { | |
1628 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
f1dc5600 | 1629 | "%s: failed to set channel\n", __func__); |
f078f209 LR |
1630 | return false; |
1631 | } | |
1632 | } else { | |
1633 | if (!(ath9k_hw_set_channel(ah, chan))) { | |
1634 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
f1dc5600 | 1635 | "%s: failed to set channel\n", __func__); |
f078f209 LR |
1636 | return false; |
1637 | } | |
1638 | } | |
1639 | ||
f1dc5600 | 1640 | if (ath9k_hw_set_txpower(ah, chan, |
f078f209 LR |
1641 | ath9k_regd_get_ctl(ah, chan), |
1642 | ath9k_regd_get_antenna_allowed(ah, chan), | |
1643 | chan->maxRegTxPower * 2, | |
1644 | min((u32) MAX_RATE_POWER, | |
1645 | (u32) ah->ah_powerLimit)) != 0) { | |
1646 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
f1dc5600 | 1647 | "%s: error init'ing transmit power\n", __func__); |
f078f209 LR |
1648 | return false; |
1649 | } | |
1650 | ||
1651 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
1652 | if (IS_CHAN_CCK(chan)) | |
1653 | synthDelay = (4 * synthDelay) / 22; | |
1654 | else | |
1655 | synthDelay /= 10; | |
1656 | ||
1657 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | |
1658 | ||
1659 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | |
1660 | ||
f1dc5600 S |
1661 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1662 | ath9k_hw_set_delta_slope(ah, chan); | |
1663 | ||
1664 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
1665 | ath9k_hw_9280_spur_mitigate(ah, chan); | |
1666 | else | |
1667 | ath9k_hw_spur_mitigate(ah, chan); | |
1668 | ||
1669 | if (!chan->oneTimeCalsDone) | |
1670 | chan->oneTimeCalsDone = true; | |
1671 | ||
1672 | return true; | |
1673 | } | |
1674 | ||
1675 | static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) | |
1676 | { | |
1677 | int bb_spur = AR_NO_SPUR; | |
1678 | int freq; | |
1679 | int bin, cur_bin; | |
1680 | int bb_spur_off, spur_subchannel_sd; | |
1681 | int spur_freq_sd; | |
1682 | int spur_delta_phase; | |
1683 | int denominator; | |
1684 | int upper, lower, cur_vit_mask; | |
1685 | int tmp, newVal; | |
1686 | int i; | |
1687 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | |
1688 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
1689 | }; | |
1690 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | |
1691 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
1692 | }; | |
1693 | int inc[4] = { 0, 100, 0, 0 }; | |
1694 | struct chan_centers centers; | |
1695 | ||
1696 | int8_t mask_m[123]; | |
1697 | int8_t mask_p[123]; | |
1698 | int8_t mask_amt; | |
1699 | int tmp_mask; | |
1700 | int cur_bb_spur; | |
1701 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
1702 | ||
1703 | memset(&mask_m, 0, sizeof(int8_t) * 123); | |
1704 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
1705 | ||
1706 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1707 | freq = centers.synth_center; | |
1708 | ||
1709 | ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; | |
1710 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | |
1711 | cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); | |
1712 | ||
1713 | if (is2GHz) | |
1714 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; | |
1715 | else | |
1716 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; | |
1717 | ||
1718 | if (AR_NO_SPUR == cur_bb_spur) | |
1719 | break; | |
1720 | cur_bb_spur = cur_bb_spur - freq; | |
1721 | ||
1722 | if (IS_CHAN_HT40(chan)) { | |
1723 | if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && | |
1724 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { | |
1725 | bb_spur = cur_bb_spur; | |
1726 | break; | |
1727 | } | |
1728 | } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && | |
1729 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { | |
1730 | bb_spur = cur_bb_spur; | |
1731 | break; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | if (AR_NO_SPUR == bb_spur) { | |
1736 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | |
1737 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | |
1738 | return; | |
1739 | } else { | |
1740 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | |
1741 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | |
1742 | } | |
1743 | ||
1744 | bin = bb_spur * 320; | |
1745 | ||
1746 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | |
1747 | ||
1748 | newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
1749 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
1750 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
1751 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
1752 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); | |
1753 | ||
1754 | newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | |
1755 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
1756 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
1757 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
1758 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
1759 | REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); | |
1760 | ||
1761 | if (IS_CHAN_HT40(chan)) { | |
1762 | if (bb_spur < 0) { | |
1763 | spur_subchannel_sd = 1; | |
1764 | bb_spur_off = bb_spur + 10; | |
1765 | } else { | |
1766 | spur_subchannel_sd = 0; | |
1767 | bb_spur_off = bb_spur - 10; | |
1768 | } | |
1769 | } else { | |
1770 | spur_subchannel_sd = 0; | |
1771 | bb_spur_off = bb_spur; | |
1772 | } | |
1773 | ||
1774 | if (IS_CHAN_HT40(chan)) | |
1775 | spur_delta_phase = | |
1776 | ((bb_spur * 262144) / | |
1777 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
1778 | else | |
1779 | spur_delta_phase = | |
1780 | ((bb_spur * 524288) / | |
1781 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
1782 | ||
1783 | denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; | |
1784 | spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; | |
1785 | ||
1786 | newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | |
1787 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
1788 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
1789 | REG_WRITE(ah, AR_PHY_TIMING11, newVal); | |
1790 | ||
1791 | newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; | |
1792 | REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); | |
1793 | ||
1794 | cur_bin = -6000; | |
1795 | upper = bin + 100; | |
1796 | lower = bin - 100; | |
1797 | ||
1798 | for (i = 0; i < 4; i++) { | |
1799 | int pilot_mask = 0; | |
1800 | int chan_mask = 0; | |
1801 | int bp = 0; | |
1802 | for (bp = 0; bp < 30; bp++) { | |
1803 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
1804 | pilot_mask = pilot_mask | 0x1 << bp; | |
1805 | chan_mask = chan_mask | 0x1 << bp; | |
1806 | } | |
1807 | cur_bin += 100; | |
1808 | } | |
1809 | cur_bin += inc[i]; | |
1810 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
1811 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
1812 | } | |
1813 | ||
1814 | cur_vit_mask = 6100; | |
1815 | upper = bin + 120; | |
1816 | lower = bin - 120; | |
1817 | ||
1818 | for (i = 0; i < 123; i++) { | |
1819 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
1820 | ||
1821 | /* workaround for gcc bug #37014 */ | |
1822 | volatile int tmp = abs(cur_vit_mask - bin); | |
1823 | ||
1824 | if (tmp < 75) | |
1825 | mask_amt = 1; | |
1826 | else | |
1827 | mask_amt = 0; | |
1828 | if (cur_vit_mask < 0) | |
1829 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
1830 | else | |
1831 | mask_p[cur_vit_mask / 100] = mask_amt; | |
1832 | } | |
1833 | cur_vit_mask -= 100; | |
1834 | } | |
1835 | ||
1836 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | |
1837 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
1838 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
1839 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
1840 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
1841 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
1842 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
1843 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
1844 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
1845 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
1846 | ||
1847 | tmp_mask = (mask_m[31] << 28) | |
1848 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
1849 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
1850 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
1851 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
1852 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
1853 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
1854 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
1855 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
1856 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
1857 | ||
1858 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | |
1859 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
1860 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
1861 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
1862 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
1863 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
1864 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
1865 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
1866 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
1867 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
1868 | ||
1869 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | |
1870 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
1871 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
1872 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
1873 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
1874 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
1875 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
1876 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
1877 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
1878 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
1879 | ||
1880 | tmp_mask = (mask_p[15] << 28) | |
1881 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
1882 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
1883 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
1884 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
1885 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
1886 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
1887 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
1888 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
1889 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
f078f209 | 1890 | |
f1dc5600 S |
1891 | tmp_mask = (mask_p[30] << 28) |
1892 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
1893 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
1894 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
1895 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
1896 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
1897 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
1898 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
1899 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
1900 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
f078f209 | 1901 | |
f1dc5600 S |
1902 | tmp_mask = (mask_p[45] << 28) |
1903 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
1904 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
1905 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
1906 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
1907 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
1908 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
1909 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
1910 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
1911 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
f078f209 | 1912 | |
f1dc5600 S |
1913 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
1914 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
1915 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
1916 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
1917 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
1918 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
1919 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
1920 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
1921 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
1922 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
f078f209 LR |
1923 | } |
1924 | ||
f1dc5600 | 1925 | static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) |
f078f209 | 1926 | { |
f1dc5600 S |
1927 | int bb_spur = AR_NO_SPUR; |
1928 | int bin, cur_bin; | |
1929 | int spur_freq_sd; | |
1930 | int spur_delta_phase; | |
1931 | int denominator; | |
1932 | int upper, lower, cur_vit_mask; | |
1933 | int tmp, new; | |
1934 | int i; | |
1935 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | |
1936 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
1937 | }; | |
1938 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | |
1939 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
1940 | }; | |
1941 | int inc[4] = { 0, 100, 0, 0 }; | |
f078f209 | 1942 | |
f1dc5600 S |
1943 | int8_t mask_m[123]; |
1944 | int8_t mask_p[123]; | |
1945 | int8_t mask_amt; | |
1946 | int tmp_mask; | |
1947 | int cur_bb_spur; | |
1948 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
f078f209 | 1949 | |
f1dc5600 S |
1950 | memset(&mask_m, 0, sizeof(int8_t) * 123); |
1951 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
f078f209 | 1952 | |
f1dc5600 S |
1953 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
1954 | cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); | |
1955 | if (AR_NO_SPUR == cur_bb_spur) | |
1956 | break; | |
1957 | cur_bb_spur = cur_bb_spur - (chan->channel * 10); | |
1958 | if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { | |
1959 | bb_spur = cur_bb_spur; | |
1960 | break; | |
1961 | } | |
1962 | } | |
f078f209 | 1963 | |
f1dc5600 S |
1964 | if (AR_NO_SPUR == bb_spur) |
1965 | return; | |
f078f209 | 1966 | |
f1dc5600 | 1967 | bin = bb_spur * 32; |
f078f209 | 1968 | |
f1dc5600 S |
1969 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); |
1970 | new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
1971 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
1972 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
1973 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
f078f209 | 1974 | |
f1dc5600 | 1975 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); |
f078f209 | 1976 | |
f1dc5600 S |
1977 | new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | |
1978 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
1979 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
1980 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
1981 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
1982 | REG_WRITE(ah, AR_PHY_SPUR_REG, new); | |
f078f209 | 1983 | |
f1dc5600 S |
1984 | spur_delta_phase = ((bb_spur * 524288) / 100) & |
1985 | AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
f078f209 | 1986 | |
f1dc5600 S |
1987 | denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; |
1988 | spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; | |
f078f209 | 1989 | |
f1dc5600 S |
1990 | new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | |
1991 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
1992 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
1993 | REG_WRITE(ah, AR_PHY_TIMING11, new); | |
f078f209 | 1994 | |
f1dc5600 S |
1995 | cur_bin = -6000; |
1996 | upper = bin + 100; | |
1997 | lower = bin - 100; | |
f078f209 | 1998 | |
f1dc5600 S |
1999 | for (i = 0; i < 4; i++) { |
2000 | int pilot_mask = 0; | |
2001 | int chan_mask = 0; | |
2002 | int bp = 0; | |
2003 | for (bp = 0; bp < 30; bp++) { | |
2004 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
2005 | pilot_mask = pilot_mask | 0x1 << bp; | |
2006 | chan_mask = chan_mask | 0x1 << bp; | |
2007 | } | |
2008 | cur_bin += 100; | |
2009 | } | |
2010 | cur_bin += inc[i]; | |
2011 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
2012 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
f078f209 | 2013 | } |
f078f209 | 2014 | |
f1dc5600 S |
2015 | cur_vit_mask = 6100; |
2016 | upper = bin + 120; | |
2017 | lower = bin - 120; | |
f078f209 | 2018 | |
f1dc5600 S |
2019 | for (i = 0; i < 123; i++) { |
2020 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
f078f209 | 2021 | |
f1dc5600 S |
2022 | /* workaround for gcc bug #37014 */ |
2023 | volatile int tmp = abs(cur_vit_mask - bin); | |
f078f209 | 2024 | |
f1dc5600 S |
2025 | if (tmp < 75) |
2026 | mask_amt = 1; | |
2027 | else | |
2028 | mask_amt = 0; | |
2029 | if (cur_vit_mask < 0) | |
2030 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
2031 | else | |
2032 | mask_p[cur_vit_mask / 100] = mask_amt; | |
2033 | } | |
2034 | cur_vit_mask -= 100; | |
f078f209 LR |
2035 | } |
2036 | ||
f1dc5600 S |
2037 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) |
2038 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
2039 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
2040 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
2041 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
2042 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
2043 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
2044 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
2045 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
2046 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
f078f209 | 2047 | |
f1dc5600 S |
2048 | tmp_mask = (mask_m[31] << 28) |
2049 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
2050 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
2051 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
2052 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
2053 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
2054 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
2055 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
2056 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
2057 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
f078f209 | 2058 | |
f1dc5600 S |
2059 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) |
2060 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
2061 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
2062 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
2063 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
2064 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
2065 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
2066 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
2067 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
2068 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
f078f209 | 2069 | |
f1dc5600 S |
2070 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) |
2071 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
2072 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
2073 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
2074 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
2075 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
2076 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
2077 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
2078 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
2079 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
f078f209 | 2080 | |
f1dc5600 S |
2081 | tmp_mask = (mask_p[15] << 28) |
2082 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
2083 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
2084 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
2085 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
2086 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
2087 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
2088 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
2089 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
2090 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
f078f209 | 2091 | |
f1dc5600 S |
2092 | tmp_mask = (mask_p[30] << 28) |
2093 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
2094 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
2095 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
2096 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
2097 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
2098 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
2099 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
2100 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
2101 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
f078f209 | 2102 | |
f1dc5600 S |
2103 | tmp_mask = (mask_p[45] << 28) |
2104 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
2105 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
2106 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
2107 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
2108 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
2109 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
2110 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
2111 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
2112 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
f078f209 | 2113 | |
f1dc5600 S |
2114 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
2115 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
2116 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
2117 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
2118 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
2119 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
2120 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
2121 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
2122 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
2123 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
f078f209 LR |
2124 | } |
2125 | ||
f1dc5600 | 2126 | bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, |
f078f209 LR |
2127 | enum ath9k_ht_macmode macmode, |
2128 | u8 txchainmask, u8 rxchainmask, | |
2129 | enum ath9k_ht_extprotspacing extprotspacing, | |
f1dc5600 | 2130 | bool bChannelChange, int *status) |
f078f209 | 2131 | { |
f078f209 LR |
2132 | u32 saveLedState; |
2133 | struct ath_hal_5416 *ahp = AH5416(ah); | |
2134 | struct ath9k_channel *curchan = ah->ah_curchan; | |
2135 | u32 saveDefAntenna; | |
2136 | u32 macStaId1; | |
2137 | int ecode; | |
2138 | int i, rx_chainmask; | |
2139 | ||
2140 | ahp->ah_extprotspacing = extprotspacing; | |
2141 | ahp->ah_txchainmask = txchainmask; | |
2142 | ahp->ah_rxchainmask = rxchainmask; | |
2143 | ||
2144 | if (AR_SREV_9280(ah)) { | |
2145 | ahp->ah_txchainmask &= 0x3; | |
2146 | ahp->ah_rxchainmask &= 0x3; | |
2147 | } | |
2148 | ||
2149 | if (ath9k_hw_check_chan(ah, chan) == NULL) { | |
2150 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | |
f1dc5600 S |
2151 | "%s: invalid channel %u/0x%x; no mapping\n", |
2152 | __func__, chan->channel, chan->channelFlags); | |
1cf69cfb LR |
2153 | ecode = -EINVAL; |
2154 | goto bad; | |
f078f209 LR |
2155 | } |
2156 | ||
d2a3b222 LR |
2157 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
2158 | ecode = -EIO; | |
2159 | goto bad; | |
2160 | } | |
f078f209 LR |
2161 | |
2162 | if (curchan) | |
2163 | ath9k_hw_getnf(ah, curchan); | |
2164 | ||
2165 | if (bChannelChange && | |
2166 | (ahp->ah_chipFullSleep != true) && | |
2167 | (ah->ah_curchan != NULL) && | |
2168 | (chan->channel != ah->ah_curchan->channel) && | |
2169 | ((chan->channelFlags & CHANNEL_ALL) == | |
2170 | (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && | |
2171 | (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && | |
2172 | !IS_CHAN_A_5MHZ_SPACED(ah-> | |
2173 | ah_curchan)))) { | |
2174 | ||
2175 | if (ath9k_hw_channel_change(ah, chan, macmode)) { | |
2176 | ath9k_hw_loadnf(ah, ah->ah_curchan); | |
2177 | ath9k_hw_start_nfcal(ah); | |
2178 | return true; | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
2183 | if (saveDefAntenna == 0) | |
2184 | saveDefAntenna = 1; | |
2185 | ||
2186 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
2187 | ||
2188 | saveLedState = REG_READ(ah, AR_CFG_LED) & | |
2189 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
2190 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
2191 | ||
2192 | ath9k_hw_mark_phy_inactive(ah); | |
2193 | ||
2194 | if (!ath9k_hw_chip_reset(ah, chan)) { | |
2195 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n", | |
2196 | __func__); | |
1cf69cfb LR |
2197 | ecode = -EINVAL; |
2198 | goto bad; | |
f078f209 LR |
2199 | } |
2200 | ||
2201 | if (AR_SREV_9280(ah)) { | |
2202 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | |
2203 | AR_GPIO_JTAG_DISABLE); | |
2204 | ||
86b89eed | 2205 | if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) { |
f078f209 LR |
2206 | if (IS_CHAN_5GHZ(chan)) |
2207 | ath9k_hw_set_gpio(ah, 9, 0); | |
2208 | else | |
2209 | ath9k_hw_set_gpio(ah, 9, 1); | |
2210 | } | |
c83be688 | 2211 | ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
f078f209 LR |
2212 | } |
2213 | ||
2214 | ecode = ath9k_hw_process_ini(ah, chan, macmode); | |
1cf69cfb LR |
2215 | if (ecode != 0) { |
2216 | ecode = -EINVAL; | |
f078f209 | 2217 | goto bad; |
1cf69cfb | 2218 | } |
f078f209 LR |
2219 | |
2220 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) | |
2221 | ath9k_hw_set_delta_slope(ah, chan); | |
2222 | ||
2223 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
2224 | ath9k_hw_9280_spur_mitigate(ah, chan); | |
2225 | else | |
2226 | ath9k_hw_spur_mitigate(ah, chan); | |
2227 | ||
2228 | if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { | |
2229 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
f1dc5600 | 2230 | "%s: error setting board options\n", __func__); |
1cf69cfb LR |
2231 | ecode = -EIO; |
2232 | goto bad; | |
f078f209 LR |
2233 | } |
2234 | ||
2235 | ath9k_hw_decrease_chain_power(ah, chan); | |
2236 | ||
2237 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr)); | |
2238 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4) | |
2239 | | macStaId1 | |
2240 | | AR_STA_ID1_RTS_USE_DEF | |
2241 | | (ah->ah_config. | |
60b67f51 | 2242 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
f078f209 | 2243 | | ahp->ah_staId1Defaults); |
b4696c8b | 2244 | ath9k_hw_set_operating_mode(ah, ah->ah_opmode); |
f078f209 LR |
2245 | |
2246 | REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); | |
2247 | REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); | |
2248 | ||
2249 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
2250 | ||
2251 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); | |
2252 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | | |
2253 | ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S)); | |
2254 | ||
2255 | REG_WRITE(ah, AR_ISR, ~0); | |
2256 | ||
2257 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
2258 | ||
2259 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1cf69cfb LR |
2260 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { |
2261 | ecode = -EIO; | |
2262 | goto bad; | |
2263 | } | |
f078f209 | 2264 | } else { |
1cf69cfb LR |
2265 | if (!(ath9k_hw_set_channel(ah, chan))) { |
2266 | ecode = -EIO; | |
2267 | goto bad; | |
2268 | } | |
f078f209 LR |
2269 | } |
2270 | ||
2271 | for (i = 0; i < AR_NUM_DCU; i++) | |
2272 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
2273 | ||
2274 | ahp->ah_intrTxqs = 0; | |
60b67f51 | 2275 | for (i = 0; i < ah->ah_caps.total_queues; i++) |
f078f209 LR |
2276 | ath9k_hw_resettxqueue(ah, i); |
2277 | ||
b4696c8b | 2278 | ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); |
f078f209 LR |
2279 | ath9k_hw_init_qos(ah); |
2280 | ||
500c064d VT |
2281 | #ifdef CONFIG_RFKILL |
2282 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
2283 | ath9k_enable_rfkill(ah); | |
2284 | #endif | |
f078f209 LR |
2285 | ath9k_hw_init_user_settings(ah); |
2286 | ||
f078f209 LR |
2287 | REG_WRITE(ah, AR_STA_ID1, |
2288 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
2289 | ||
2290 | ath9k_hw_set_dma(ah); | |
2291 | ||
2292 | REG_WRITE(ah, AR_OBS, 8); | |
2293 | ||
2294 | if (ahp->ah_intrMitigation) { | |
2295 | ||
2296 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); | |
2297 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
2298 | } | |
2299 | ||
2300 | ath9k_hw_init_bb(ah, chan); | |
2301 | ||
1cf69cfb LR |
2302 | if (!ath9k_hw_init_cal(ah, chan)){ |
2303 | ecode = -EIO;; | |
2304 | goto bad; | |
2305 | } | |
f078f209 LR |
2306 | |
2307 | rx_chainmask = ahp->ah_rxchainmask; | |
2308 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { | |
2309 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
2310 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
2311 | } | |
2312 | ||
2313 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); | |
2314 | ||
2315 | if (AR_SREV_9100(ah)) { | |
2316 | u32 mask; | |
2317 | mask = REG_READ(ah, AR_CFG); | |
2318 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
2319 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
f1dc5600 S |
2320 | "%s CFG Byte Swap Set 0x%x\n", __func__, |
2321 | mask); | |
f078f209 LR |
2322 | } else { |
2323 | mask = | |
2324 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
2325 | REG_WRITE(ah, AR_CFG, mask); | |
2326 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
f1dc5600 S |
2327 | "%s Setting CFG 0x%x\n", __func__, |
2328 | REG_READ(ah, AR_CFG)); | |
f078f209 LR |
2329 | } |
2330 | } else { | |
2331 | #ifdef __BIG_ENDIAN | |
2332 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
2333 | #endif | |
2334 | } | |
2335 | ||
2336 | return true; | |
2337 | bad: | |
2338 | if (status) | |
2339 | *status = ecode; | |
2340 | return false; | |
f078f209 LR |
2341 | } |
2342 | ||
f1dc5600 S |
2343 | /************************/ |
2344 | /* Key Cache Management */ | |
2345 | /************************/ | |
f078f209 | 2346 | |
f1dc5600 | 2347 | bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) |
f078f209 | 2348 | { |
f1dc5600 | 2349 | u32 keyType; |
f078f209 | 2350 | |
f1dc5600 S |
2351 | if (entry >= ah->ah_caps.keycache_size) { |
2352 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2353 | "%s: entry %u out of range\n", __func__, entry); | |
f078f209 LR |
2354 | return false; |
2355 | } | |
2356 | ||
f1dc5600 | 2357 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
f078f209 | 2358 | |
f1dc5600 S |
2359 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
2360 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); | |
2361 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); | |
2362 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); | |
2363 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); | |
2364 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); | |
2365 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); | |
2366 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); | |
f078f209 | 2367 | |
f1dc5600 S |
2368 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
2369 | u16 micentry = entry + 64; | |
f078f209 | 2370 | |
f1dc5600 S |
2371 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
2372 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
2373 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); | |
2374 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
f078f209 | 2375 | |
f078f209 LR |
2376 | } |
2377 | ||
f1dc5600 S |
2378 | if (ah->ah_curchan == NULL) |
2379 | return true; | |
f078f209 LR |
2380 | |
2381 | return true; | |
2382 | } | |
2383 | ||
f1dc5600 | 2384 | bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) |
f078f209 | 2385 | { |
f1dc5600 | 2386 | u32 macHi, macLo; |
f078f209 | 2387 | |
f1dc5600 S |
2388 | if (entry >= ah->ah_caps.keycache_size) { |
2389 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2390 | "%s: entry %u out of range\n", __func__, entry); | |
2391 | return false; | |
f078f209 LR |
2392 | } |
2393 | ||
f1dc5600 S |
2394 | if (mac != NULL) { |
2395 | macHi = (mac[5] << 8) | mac[4]; | |
2396 | macLo = (mac[3] << 24) | | |
2397 | (mac[2] << 16) | | |
2398 | (mac[1] << 8) | | |
2399 | mac[0]; | |
2400 | macLo >>= 1; | |
2401 | macLo |= (macHi & 1) << 31; | |
2402 | macHi >>= 1; | |
f078f209 | 2403 | } else { |
f1dc5600 | 2404 | macLo = macHi = 0; |
f078f209 | 2405 | } |
f1dc5600 S |
2406 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
2407 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); | |
f078f209 | 2408 | |
f1dc5600 | 2409 | return true; |
f078f209 LR |
2410 | } |
2411 | ||
f1dc5600 S |
2412 | bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, |
2413 | const struct ath9k_keyval *k, | |
2414 | const u8 *mac, int xorKey) | |
f078f209 | 2415 | { |
f1dc5600 S |
2416 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
2417 | u32 key0, key1, key2, key3, key4; | |
2418 | u32 keyType; | |
2419 | u32 xorMask = xorKey ? | |
2420 | (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 | |
2421 | | ATH9K_KEY_XOR) : 0; | |
f078f209 | 2422 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 | 2423 | |
f1dc5600 S |
2424 | if (entry >= pCap->keycache_size) { |
2425 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2426 | "%s: entry %u out of range\n", __func__, entry); | |
2427 | return false; | |
f078f209 LR |
2428 | } |
2429 | ||
f1dc5600 S |
2430 | switch (k->kv_type) { |
2431 | case ATH9K_CIPHER_AES_OCB: | |
2432 | keyType = AR_KEYTABLE_TYPE_AES; | |
2433 | break; | |
2434 | case ATH9K_CIPHER_AES_CCM: | |
2435 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { | |
2436 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2437 | "%s: AES-CCM not supported by " | |
2438 | "mac rev 0x%x\n", __func__, | |
2439 | ah->ah_macRev); | |
2440 | return false; | |
2441 | } | |
2442 | keyType = AR_KEYTABLE_TYPE_CCM; | |
2443 | break; | |
2444 | case ATH9K_CIPHER_TKIP: | |
2445 | keyType = AR_KEYTABLE_TYPE_TKIP; | |
2446 | if (ATH9K_IS_MIC_ENABLED(ah) | |
2447 | && entry + 64 >= pCap->keycache_size) { | |
2448 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2449 | "%s: entry %u inappropriate for TKIP\n", | |
2450 | __func__, entry); | |
2451 | return false; | |
2452 | } | |
2453 | break; | |
2454 | case ATH9K_CIPHER_WEP: | |
2455 | if (k->kv_len < LEN_WEP40) { | |
2456 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2457 | "%s: WEP key length %u too small\n", | |
2458 | __func__, k->kv_len); | |
2459 | return false; | |
2460 | } | |
2461 | if (k->kv_len <= LEN_WEP40) | |
2462 | keyType = AR_KEYTABLE_TYPE_40; | |
2463 | else if (k->kv_len <= LEN_WEP104) | |
2464 | keyType = AR_KEYTABLE_TYPE_104; | |
2465 | else | |
2466 | keyType = AR_KEYTABLE_TYPE_128; | |
2467 | break; | |
2468 | case ATH9K_CIPHER_CLR: | |
2469 | keyType = AR_KEYTABLE_TYPE_CLR; | |
2470 | break; | |
2471 | default: | |
2472 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | |
2473 | "%s: cipher %u not supported\n", __func__, | |
2474 | k->kv_type); | |
2475 | return false; | |
f078f209 LR |
2476 | } |
2477 | ||
f1dc5600 S |
2478 | key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask; |
2479 | key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff; | |
2480 | key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask; | |
2481 | key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff; | |
2482 | key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask; | |
2483 | if (k->kv_len <= LEN_WEP104) | |
2484 | key4 &= 0xff; | |
f078f209 | 2485 | |
f1dc5600 S |
2486 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
2487 | u16 micentry = entry + 64; | |
f078f209 | 2488 | |
f1dc5600 S |
2489 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
2490 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); | |
2491 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); | |
2492 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
2493 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); | |
2494 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
2495 | (void) ath9k_hw_keysetmac(ah, entry, mac); | |
f078f209 | 2496 | |
f1dc5600 S |
2497 | if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { |
2498 | u32 mic0, mic1, mic2, mic3, mic4; | |
f078f209 | 2499 | |
f1dc5600 S |
2500 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
2501 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
2502 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; | |
2503 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; | |
2504 | mic4 = get_unaligned_le32(k->kv_txmic + 4); | |
2505 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); | |
2506 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); | |
2507 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); | |
2508 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); | |
2509 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); | |
2510 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
2511 | AR_KEYTABLE_TYPE_CLR); | |
f078f209 | 2512 | |
f1dc5600 S |
2513 | } else { |
2514 | u32 mic0, mic2; | |
f078f209 | 2515 | |
f1dc5600 S |
2516 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
2517 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
2518 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); | |
2519 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
2520 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); | |
2521 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
2522 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); | |
2523 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
2524 | AR_KEYTABLE_TYPE_CLR); | |
2525 | } | |
2526 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); | |
2527 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); | |
2528 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); | |
2529 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
2530 | } else { | |
2531 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); | |
2532 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
2533 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); | |
2534 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
2535 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); | |
2536 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
f078f209 | 2537 | |
f1dc5600 S |
2538 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
2539 | } | |
f078f209 | 2540 | |
f1dc5600 S |
2541 | if (ah->ah_curchan == NULL) |
2542 | return true; | |
f078f209 LR |
2543 | |
2544 | return true; | |
2545 | } | |
2546 | ||
f1dc5600 | 2547 | bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) |
f078f209 | 2548 | { |
f1dc5600 S |
2549 | if (entry < ah->ah_caps.keycache_size) { |
2550 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); | |
2551 | if (val & AR_KEYTABLE_VALID) | |
2552 | return true; | |
2553 | } | |
2554 | return false; | |
f078f209 LR |
2555 | } |
2556 | ||
f1dc5600 S |
2557 | /******************************/ |
2558 | /* Power Management (Chipset) */ | |
2559 | /******************************/ | |
2560 | ||
2561 | static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) | |
f078f209 | 2562 | { |
f1dc5600 S |
2563 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2564 | if (setChip) { | |
2565 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | |
2566 | AR_RTC_FORCE_WAKE_EN); | |
2567 | if (!AR_SREV_9100(ah)) | |
2568 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
f078f209 | 2569 | |
f1dc5600 S |
2570 | REG_CLR_BIT(ah, (u16) (AR_RTC_RESET), |
2571 | AR_RTC_RESET_EN); | |
2572 | } | |
f078f209 LR |
2573 | } |
2574 | ||
f1dc5600 | 2575 | static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) |
f078f209 | 2576 | { |
f1dc5600 S |
2577 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2578 | if (setChip) { | |
2579 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | |
f078f209 | 2580 | |
f1dc5600 S |
2581 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
2582 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
2583 | AR_RTC_FORCE_WAKE_ON_INT); | |
2584 | } else { | |
2585 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | |
2586 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2587 | } |
f078f209 | 2588 | } |
f078f209 LR |
2589 | } |
2590 | ||
f1dc5600 S |
2591 | static bool ath9k_hw_set_power_awake(struct ath_hal *ah, |
2592 | int setChip) | |
f078f209 | 2593 | { |
f1dc5600 S |
2594 | u32 val; |
2595 | int i; | |
f078f209 | 2596 | |
f1dc5600 S |
2597 | if (setChip) { |
2598 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
2599 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2600 | if (ath9k_hw_set_reset_reg(ah, | |
2601 | ATH9K_RESET_POWER_ON) != true) { | |
2602 | return false; | |
2603 | } | |
2604 | } | |
2605 | if (AR_SREV_9100(ah)) | |
2606 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2607 | AR_RTC_RESET_EN); | |
f078f209 | 2608 | |
f1dc5600 S |
2609 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2610 | AR_RTC_FORCE_WAKE_EN); | |
2611 | udelay(50); | |
f078f209 | 2612 | |
f1dc5600 S |
2613 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2614 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2615 | if (val == AR_RTC_STATUS_ON) | |
2616 | break; | |
2617 | udelay(50); | |
2618 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2619 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2620 | } |
f1dc5600 S |
2621 | if (i == 0) { |
2622 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
2623 | "%s: Failed to wakeup in %uus\n", | |
2624 | __func__, POWER_UP_TIME / 20); | |
2625 | return false; | |
f078f209 | 2626 | } |
f078f209 LR |
2627 | } |
2628 | ||
f1dc5600 | 2629 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2630 | |
f1dc5600 | 2631 | return true; |
f078f209 LR |
2632 | } |
2633 | ||
f1dc5600 S |
2634 | bool ath9k_hw_setpower(struct ath_hal *ah, |
2635 | enum ath9k_power_mode mode) | |
f078f209 LR |
2636 | { |
2637 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f1dc5600 S |
2638 | static const char *modes[] = { |
2639 | "AWAKE", | |
2640 | "FULL-SLEEP", | |
2641 | "NETWORK SLEEP", | |
2642 | "UNDEFINED" | |
2643 | }; | |
2644 | int status = true, setChip = true; | |
2645 | ||
2646 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, | |
2647 | modes[ahp->ah_powerMode], modes[mode], | |
2648 | setChip ? "set chip " : ""); | |
2649 | ||
2650 | switch (mode) { | |
2651 | case ATH9K_PM_AWAKE: | |
2652 | status = ath9k_hw_set_power_awake(ah, setChip); | |
2653 | break; | |
2654 | case ATH9K_PM_FULL_SLEEP: | |
2655 | ath9k_set_power_sleep(ah, setChip); | |
2656 | ahp->ah_chipFullSleep = true; | |
2657 | break; | |
2658 | case ATH9K_PM_NETWORK_SLEEP: | |
2659 | ath9k_set_power_network_sleep(ah, setChip); | |
2660 | break; | |
f078f209 | 2661 | default: |
f1dc5600 S |
2662 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, |
2663 | "%s: unknown power mode %u\n", __func__, mode); | |
f078f209 LR |
2664 | return false; |
2665 | } | |
f1dc5600 S |
2666 | ahp->ah_powerMode = mode; |
2667 | ||
2668 | return status; | |
f078f209 LR |
2669 | } |
2670 | ||
f1dc5600 | 2671 | void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) |
f078f209 LR |
2672 | { |
2673 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f1dc5600 | 2674 | u8 i; |
f078f209 | 2675 | |
f1dc5600 S |
2676 | if (ah->ah_isPciExpress != true) |
2677 | return; | |
f078f209 | 2678 | |
f1dc5600 S |
2679 | if (ah->ah_config.pcie_powersave_enable == 2) |
2680 | return; | |
2681 | ||
2682 | if (restore) | |
2683 | return; | |
2684 | ||
2685 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2686 | for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { | |
2687 | REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), | |
2688 | INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); | |
f078f209 | 2689 | } |
f1dc5600 S |
2690 | udelay(1000); |
2691 | } else if (AR_SREV_9280(ah) && | |
2692 | (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { | |
2693 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); | |
2694 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
2695 | ||
2696 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | |
2697 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | |
2698 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | |
2699 | ||
2700 | if (ah->ah_config.pcie_clock_req) | |
2701 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | |
2702 | else | |
2703 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | |
2704 | ||
2705 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
2706 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2707 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | |
2708 | ||
2709 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
2710 | ||
2711 | udelay(1000); | |
2712 | } else { | |
2713 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | |
2714 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
2715 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); | |
2716 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | |
2717 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | |
2718 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | |
2719 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
2720 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2721 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | |
2722 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
f078f209 LR |
2723 | } |
2724 | ||
f1dc5600 S |
2725 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
2726 | ||
2727 | if (ah->ah_config.pcie_waen) { | |
2728 | REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); | |
2729 | } else { | |
2730 | if (AR_SREV_9280(ah)) | |
2731 | REG_WRITE(ah, AR_WA, 0x0040073f); | |
2732 | else | |
2733 | REG_WRITE(ah, AR_WA, 0x0000073f); | |
2734 | } | |
f078f209 LR |
2735 | } |
2736 | ||
f1dc5600 S |
2737 | /**********************/ |
2738 | /* Interrupt Handling */ | |
2739 | /**********************/ | |
2740 | ||
f078f209 LR |
2741 | bool ath9k_hw_intrpend(struct ath_hal *ah) |
2742 | { | |
2743 | u32 host_isr; | |
2744 | ||
2745 | if (AR_SREV_9100(ah)) | |
2746 | return true; | |
2747 | ||
2748 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | |
2749 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) | |
2750 | return true; | |
2751 | ||
2752 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
2753 | if ((host_isr & AR_INTR_SYNC_DEFAULT) | |
2754 | && (host_isr != AR_INTR_SPURIOUS)) | |
2755 | return true; | |
2756 | ||
2757 | return false; | |
2758 | } | |
2759 | ||
2760 | bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) | |
2761 | { | |
2762 | u32 isr = 0; | |
2763 | u32 mask2 = 0; | |
60b67f51 | 2764 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
f078f209 LR |
2765 | u32 sync_cause = 0; |
2766 | bool fatal_int = false; | |
f1dc5600 | 2767 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 LR |
2768 | |
2769 | if (!AR_SREV_9100(ah)) { | |
2770 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | |
2771 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | |
2772 | == AR_RTC_STATUS_ON) { | |
2773 | isr = REG_READ(ah, AR_ISR); | |
2774 | } | |
2775 | } | |
2776 | ||
f1dc5600 S |
2777 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
2778 | AR_INTR_SYNC_DEFAULT; | |
f078f209 LR |
2779 | |
2780 | *masked = 0; | |
2781 | ||
2782 | if (!isr && !sync_cause) | |
2783 | return false; | |
2784 | } else { | |
2785 | *masked = 0; | |
2786 | isr = REG_READ(ah, AR_ISR); | |
2787 | } | |
2788 | ||
2789 | if (isr) { | |
f078f209 LR |
2790 | if (isr & AR_ISR_BCNMISC) { |
2791 | u32 isr2; | |
2792 | isr2 = REG_READ(ah, AR_ISR_S2); | |
2793 | if (isr2 & AR_ISR_S2_TIM) | |
2794 | mask2 |= ATH9K_INT_TIM; | |
2795 | if (isr2 & AR_ISR_S2_DTIM) | |
2796 | mask2 |= ATH9K_INT_DTIM; | |
2797 | if (isr2 & AR_ISR_S2_DTIMSYNC) | |
2798 | mask2 |= ATH9K_INT_DTIMSYNC; | |
2799 | if (isr2 & (AR_ISR_S2_CABEND)) | |
2800 | mask2 |= ATH9K_INT_CABEND; | |
2801 | if (isr2 & AR_ISR_S2_GTT) | |
2802 | mask2 |= ATH9K_INT_GTT; | |
2803 | if (isr2 & AR_ISR_S2_CST) | |
2804 | mask2 |= ATH9K_INT_CST; | |
2805 | } | |
2806 | ||
2807 | isr = REG_READ(ah, AR_ISR_RAC); | |
2808 | if (isr == 0xffffffff) { | |
2809 | *masked = 0; | |
2810 | return false; | |
2811 | } | |
2812 | ||
2813 | *masked = isr & ATH9K_INT_COMMON; | |
2814 | ||
2815 | if (ahp->ah_intrMitigation) { | |
f078f209 LR |
2816 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
2817 | *masked |= ATH9K_INT_RX; | |
2818 | } | |
2819 | ||
2820 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) | |
2821 | *masked |= ATH9K_INT_RX; | |
2822 | if (isr & | |
2823 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | |
2824 | AR_ISR_TXEOL)) { | |
2825 | u32 s0_s, s1_s; | |
2826 | ||
2827 | *masked |= ATH9K_INT_TX; | |
2828 | ||
2829 | s0_s = REG_READ(ah, AR_ISR_S0_S); | |
2830 | ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); | |
2831 | ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | |
2832 | ||
2833 | s1_s = REG_READ(ah, AR_ISR_S1_S); | |
2834 | ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); | |
2835 | ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | |
2836 | } | |
2837 | ||
2838 | if (isr & AR_ISR_RXORN) { | |
2839 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
f1dc5600 S |
2840 | "%s: receive FIFO overrun interrupt\n", |
2841 | __func__); | |
f078f209 LR |
2842 | } |
2843 | ||
2844 | if (!AR_SREV_9100(ah)) { | |
60b67f51 | 2845 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2846 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
2847 | if (isr5 & AR_ISR_S5_TIM_TIMER) | |
2848 | *masked |= ATH9K_INT_TIM_TIMER; | |
2849 | } | |
2850 | } | |
2851 | ||
2852 | *masked |= mask2; | |
2853 | } | |
f1dc5600 | 2854 | |
f078f209 LR |
2855 | if (AR_SREV_9100(ah)) |
2856 | return true; | |
f1dc5600 | 2857 | |
f078f209 LR |
2858 | if (sync_cause) { |
2859 | fatal_int = | |
2860 | (sync_cause & | |
2861 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | |
2862 | ? true : false; | |
2863 | ||
2864 | if (fatal_int) { | |
2865 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | |
2866 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
f1dc5600 S |
2867 | "%s: received PCI FATAL interrupt\n", |
2868 | __func__); | |
f078f209 LR |
2869 | } |
2870 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | |
2871 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | |
f1dc5600 S |
2872 | "%s: received PCI PERR interrupt\n", |
2873 | __func__); | |
f078f209 LR |
2874 | } |
2875 | } | |
2876 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | |
2877 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
f1dc5600 S |
2878 | "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", |
2879 | __func__); | |
f078f209 LR |
2880 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
2881 | REG_WRITE(ah, AR_RC, 0); | |
2882 | *masked |= ATH9K_INT_FATAL; | |
2883 | } | |
2884 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | |
2885 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | |
f1dc5600 S |
2886 | "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", |
2887 | __func__); | |
f078f209 LR |
2888 | } |
2889 | ||
2890 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | |
2891 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | |
2892 | } | |
f1dc5600 | 2893 | |
f078f209 LR |
2894 | return true; |
2895 | } | |
2896 | ||
2897 | enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) | |
2898 | { | |
2899 | return AH5416(ah)->ah_maskReg; | |
2900 | } | |
2901 | ||
2902 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) | |
2903 | { | |
2904 | struct ath_hal_5416 *ahp = AH5416(ah); | |
2905 | u32 omask = ahp->ah_maskReg; | |
2906 | u32 mask, mask2; | |
60b67f51 | 2907 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
f078f209 LR |
2908 | |
2909 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, | |
2910 | omask, ints); | |
2911 | ||
2912 | if (omask & ATH9K_INT_GLOBAL) { | |
2913 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n", | |
2914 | __func__); | |
2915 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); | |
2916 | (void) REG_READ(ah, AR_IER); | |
2917 | if (!AR_SREV_9100(ah)) { | |
2918 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); | |
2919 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); | |
2920 | ||
2921 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
2922 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); | |
2923 | } | |
2924 | } | |
2925 | ||
2926 | mask = ints & ATH9K_INT_COMMON; | |
2927 | mask2 = 0; | |
2928 | ||
2929 | if (ints & ATH9K_INT_TX) { | |
2930 | if (ahp->ah_txOkInterruptMask) | |
2931 | mask |= AR_IMR_TXOK; | |
2932 | if (ahp->ah_txDescInterruptMask) | |
2933 | mask |= AR_IMR_TXDESC; | |
2934 | if (ahp->ah_txErrInterruptMask) | |
2935 | mask |= AR_IMR_TXERR; | |
2936 | if (ahp->ah_txEolInterruptMask) | |
2937 | mask |= AR_IMR_TXEOL; | |
2938 | } | |
2939 | if (ints & ATH9K_INT_RX) { | |
2940 | mask |= AR_IMR_RXERR; | |
2941 | if (ahp->ah_intrMitigation) | |
2942 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; | |
2943 | else | |
2944 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; | |
60b67f51 | 2945 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
f078f209 LR |
2946 | mask |= AR_IMR_GENTMR; |
2947 | } | |
2948 | ||
2949 | if (ints & (ATH9K_INT_BMISC)) { | |
2950 | mask |= AR_IMR_BCNMISC; | |
2951 | if (ints & ATH9K_INT_TIM) | |
2952 | mask2 |= AR_IMR_S2_TIM; | |
2953 | if (ints & ATH9K_INT_DTIM) | |
2954 | mask2 |= AR_IMR_S2_DTIM; | |
2955 | if (ints & ATH9K_INT_DTIMSYNC) | |
2956 | mask2 |= AR_IMR_S2_DTIMSYNC; | |
2957 | if (ints & ATH9K_INT_CABEND) | |
2958 | mask2 |= (AR_IMR_S2_CABEND); | |
2959 | } | |
2960 | ||
2961 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { | |
2962 | mask |= AR_IMR_BCNMISC; | |
2963 | if (ints & ATH9K_INT_GTT) | |
2964 | mask2 |= AR_IMR_S2_GTT; | |
2965 | if (ints & ATH9K_INT_CST) | |
2966 | mask2 |= AR_IMR_S2_CST; | |
2967 | } | |
2968 | ||
2969 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, | |
2970 | mask); | |
2971 | REG_WRITE(ah, AR_IMR, mask); | |
2972 | mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | | |
2973 | AR_IMR_S2_DTIM | | |
2974 | AR_IMR_S2_DTIMSYNC | | |
2975 | AR_IMR_S2_CABEND | | |
2976 | AR_IMR_S2_CABTO | | |
2977 | AR_IMR_S2_TSFOOR | | |
2978 | AR_IMR_S2_GTT | AR_IMR_S2_CST); | |
2979 | REG_WRITE(ah, AR_IMR_S2, mask | mask2); | |
2980 | ahp->ah_maskReg = ints; | |
2981 | ||
60b67f51 | 2982 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2983 | if (ints & ATH9K_INT_TIM_TIMER) |
2984 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2985 | else | |
2986 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2987 | } | |
2988 | ||
2989 | if (ints & ATH9K_INT_GLOBAL) { | |
2990 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n", | |
2991 | __func__); | |
2992 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); | |
2993 | if (!AR_SREV_9100(ah)) { | |
2994 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | |
2995 | AR_INTR_MAC_IRQ); | |
2996 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | |
2997 | ||
2998 | ||
2999 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | |
3000 | AR_INTR_SYNC_DEFAULT); | |
3001 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | |
3002 | AR_INTR_SYNC_DEFAULT); | |
3003 | } | |
3004 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | |
3005 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | |
3006 | } | |
3007 | ||
3008 | return omask; | |
3009 | } | |
3010 | ||
f1dc5600 S |
3011 | /*******************/ |
3012 | /* Beacon Handling */ | |
3013 | /*******************/ | |
3014 | ||
3015 | void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) | |
f078f209 LR |
3016 | { |
3017 | struct ath_hal_5416 *ahp = AH5416(ah); | |
3018 | int flags = 0; | |
3019 | ||
3020 | ahp->ah_beaconInterval = beacon_period; | |
3021 | ||
3022 | switch (ah->ah_opmode) { | |
3023 | case ATH9K_M_STA: | |
3024 | case ATH9K_M_MONITOR: | |
3025 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); | |
3026 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | |
3027 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | |
3028 | flags |= AR_TBTT_TIMER_EN; | |
3029 | break; | |
3030 | case ATH9K_M_IBSS: | |
3031 | REG_SET_BIT(ah, AR_TXCFG, | |
3032 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
3033 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
3034 | TU_TO_USEC(next_beacon + | |
3035 | (ahp->ah_atimWindow ? ahp-> | |
3036 | ah_atimWindow : 1))); | |
3037 | flags |= AR_NDP_TIMER_EN; | |
3038 | case ATH9K_M_HOSTAP: | |
3039 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); | |
3040 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
3041 | TU_TO_USEC(next_beacon - | |
3042 | ah->ah_config. | |
60b67f51 | 3043 | dma_beacon_response_time)); |
f078f209 LR |
3044 | REG_WRITE(ah, AR_NEXT_SWBA, |
3045 | TU_TO_USEC(next_beacon - | |
3046 | ah->ah_config. | |
60b67f51 | 3047 | sw_beacon_response_time)); |
f078f209 LR |
3048 | flags |= |
3049 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
3050 | break; | |
3051 | } | |
3052 | ||
3053 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
3054 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
3055 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
3056 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
3057 | ||
3058 | beacon_period &= ~ATH9K_BEACON_ENA; | |
3059 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
3060 | beacon_period &= ~ATH9K_BEACON_RESET_TSF; | |
3061 | ath9k_hw_reset_tsf(ah); | |
3062 | } | |
3063 | ||
3064 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
3065 | } | |
3066 | ||
f1dc5600 S |
3067 | void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, |
3068 | const struct ath9k_beacon_state *bs) | |
f078f209 LR |
3069 | { |
3070 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
60b67f51 | 3071 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
f078f209 LR |
3072 | |
3073 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); | |
3074 | ||
3075 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
3076 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
3077 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
3078 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
3079 | ||
3080 | REG_RMW_FIELD(ah, AR_RSSI_THR, | |
3081 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
3082 | ||
3083 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
3084 | ||
3085 | if (bs->bs_sleepduration > beaconintval) | |
3086 | beaconintval = bs->bs_sleepduration; | |
3087 | ||
3088 | dtimperiod = bs->bs_dtimperiod; | |
3089 | if (bs->bs_sleepduration > dtimperiod) | |
3090 | dtimperiod = bs->bs_sleepduration; | |
3091 | ||
3092 | if (beaconintval == dtimperiod) | |
3093 | nextTbtt = bs->bs_nextdtim; | |
3094 | else | |
3095 | nextTbtt = bs->bs_nexttbtt; | |
3096 | ||
3097 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__, | |
3098 | bs->bs_nextdtim); | |
3099 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__, | |
3100 | nextTbtt); | |
3101 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__, | |
f1dc5600 S |
3102 | beaconintval); |
3103 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__, | |
3104 | dtimperiod); | |
f078f209 | 3105 | |
f1dc5600 S |
3106 | REG_WRITE(ah, AR_NEXT_DTIM, |
3107 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
3108 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 3109 | |
f1dc5600 S |
3110 | REG_WRITE(ah, AR_SLEEP1, |
3111 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
3112 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 3113 | |
f1dc5600 S |
3114 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
3115 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
3116 | else | |
3117 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 3118 | |
f1dc5600 S |
3119 | REG_WRITE(ah, AR_SLEEP2, |
3120 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 3121 | |
f1dc5600 S |
3122 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
3123 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 3124 | |
f1dc5600 S |
3125 | REG_SET_BIT(ah, AR_TIMER_MODE, |
3126 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
3127 | AR_DTIM_TIMER_EN); | |
f078f209 | 3128 | |
f078f209 LR |
3129 | } |
3130 | ||
f1dc5600 S |
3131 | /***************/ |
3132 | /* Rate tables */ | |
3133 | /***************/ | |
f078f209 | 3134 | |
f1dc5600 S |
3135 | static struct ath9k_rate_table ar5416_11a_table = { |
3136 | 8, | |
3137 | {0}, | |
3138 | { | |
3139 | {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, | |
3140 | {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, | |
3141 | {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, | |
3142 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2}, | |
3143 | {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4}, | |
3144 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4}, | |
3145 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4}, | |
3146 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4} | |
3147 | }, | |
3148 | }; | |
f078f209 | 3149 | |
f1dc5600 S |
3150 | static struct ath9k_rate_table ar5416_11b_table = { |
3151 | 4, | |
3152 | {0}, | |
3153 | { | |
3154 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | |
3155 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | |
3156 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1}, | |
3157 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1} | |
3158 | }, | |
3159 | }; | |
f078f209 | 3160 | |
f1dc5600 S |
3161 | static struct ath9k_rate_table ar5416_11g_table = { |
3162 | 12, | |
3163 | {0}, | |
3164 | { | |
3165 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | |
3166 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | |
3167 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2}, | |
3168 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3}, | |
f078f209 | 3169 | |
f1dc5600 S |
3170 | {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, |
3171 | {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, | |
3172 | {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, | |
3173 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, | |
3174 | {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, | |
3175 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8}, | |
3176 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8}, | |
3177 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8} | |
3178 | }, | |
3179 | }; | |
f078f209 | 3180 | |
f1dc5600 S |
3181 | static struct ath9k_rate_table ar5416_11ng_table = { |
3182 | 28, | |
3183 | {0}, | |
3184 | { | |
3185 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | |
3186 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | |
3187 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2}, | |
3188 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3}, | |
f078f209 | 3189 | |
f1dc5600 S |
3190 | {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, |
3191 | {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, | |
3192 | {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, | |
3193 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, | |
3194 | {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, | |
3195 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8}, | |
3196 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8}, | |
3197 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}, | |
3198 | {true, PHY_HT, 6500, 0x80, 0x00, 0, 4}, | |
3199 | {true, PHY_HT, 13000, 0x81, 0x00, 1, 6}, | |
3200 | {true, PHY_HT, 19500, 0x82, 0x00, 2, 6}, | |
3201 | {true, PHY_HT, 26000, 0x83, 0x00, 3, 8}, | |
3202 | {true, PHY_HT, 39000, 0x84, 0x00, 4, 8}, | |
3203 | {true, PHY_HT, 52000, 0x85, 0x00, 5, 8}, | |
3204 | {true, PHY_HT, 58500, 0x86, 0x00, 6, 8}, | |
3205 | {true, PHY_HT, 65000, 0x87, 0x00, 7, 8}, | |
3206 | {true, PHY_HT, 13000, 0x88, 0x00, 8, 4}, | |
3207 | {true, PHY_HT, 26000, 0x89, 0x00, 9, 6}, | |
3208 | {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6}, | |
3209 | {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8}, | |
3210 | {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8}, | |
3211 | {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8}, | |
3212 | {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8}, | |
3213 | {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8}, | |
3214 | }, | |
3215 | }; | |
3216 | ||
3217 | static struct ath9k_rate_table ar5416_11na_table = { | |
3218 | 24, | |
3219 | {0}, | |
3220 | { | |
3221 | {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, | |
3222 | {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, | |
3223 | {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, | |
3224 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2}, | |
3225 | {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4}, | |
3226 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4}, | |
3227 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4}, | |
3228 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}, | |
3229 | {true, PHY_HT, 6500, 0x80, 0x00, 0, 0}, | |
3230 | {true, PHY_HT, 13000, 0x81, 0x00, 1, 2}, | |
3231 | {true, PHY_HT, 19500, 0x82, 0x00, 2, 2}, | |
3232 | {true, PHY_HT, 26000, 0x83, 0x00, 3, 4}, | |
3233 | {true, PHY_HT, 39000, 0x84, 0x00, 4, 4}, | |
3234 | {true, PHY_HT, 52000, 0x85, 0x00, 5, 4}, | |
3235 | {true, PHY_HT, 58500, 0x86, 0x00, 6, 4}, | |
3236 | {true, PHY_HT, 65000, 0x87, 0x00, 7, 4}, | |
3237 | {true, PHY_HT, 13000, 0x88, 0x00, 8, 0}, | |
3238 | {true, PHY_HT, 26000, 0x89, 0x00, 9, 2}, | |
3239 | {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2}, | |
3240 | {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4}, | |
3241 | {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4}, | |
3242 | {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4}, | |
3243 | {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4}, | |
3244 | {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4}, | |
3245 | }, | |
3246 | }; | |
f078f209 | 3247 | |
f1dc5600 S |
3248 | static void ath9k_hw_setup_rate_table(struct ath_hal *ah, |
3249 | struct ath9k_rate_table *rt) | |
f078f209 | 3250 | { |
f1dc5600 | 3251 | int i; |
f078f209 | 3252 | |
f1dc5600 S |
3253 | if (rt->rateCodeToIndex[0] != 0) |
3254 | return; | |
ea9880fb | 3255 | |
f1dc5600 S |
3256 | for (i = 0; i < 256; i++) |
3257 | rt->rateCodeToIndex[i] = (u8) -1; | |
3258 | ||
3259 | for (i = 0; i < rt->rateCount; i++) { | |
3260 | u8 code = rt->info[i].rateCode; | |
3261 | u8 cix = rt->info[i].controlRate; | |
3262 | ||
3263 | rt->rateCodeToIndex[code] = i; | |
3264 | rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i; | |
3265 | ||
3266 | rt->info[i].lpAckDuration = | |
3267 | ath9k_hw_computetxtime(ah, rt, | |
3268 | WLAN_CTRL_FRAME_SIZE, | |
3269 | cix, | |
3270 | false); | |
3271 | rt->info[i].spAckDuration = | |
3272 | ath9k_hw_computetxtime(ah, rt, | |
3273 | WLAN_CTRL_FRAME_SIZE, | |
3274 | cix, | |
3275 | true); | |
f078f209 | 3276 | } |
f1dc5600 | 3277 | } |
f078f209 | 3278 | |
f1dc5600 S |
3279 | const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, |
3280 | u32 mode) | |
3281 | { | |
3282 | struct ath9k_rate_table *rt; | |
f078f209 | 3283 | |
f1dc5600 S |
3284 | switch (mode) { |
3285 | case ATH9K_MODE_11A: | |
3286 | rt = &ar5416_11a_table; | |
f078f209 | 3287 | break; |
f1dc5600 S |
3288 | case ATH9K_MODE_11B: |
3289 | rt = &ar5416_11b_table; | |
3290 | break; | |
3291 | case ATH9K_MODE_11G: | |
3292 | rt = &ar5416_11g_table; | |
3293 | break; | |
3294 | case ATH9K_MODE_11NG_HT20: | |
3295 | case ATH9K_MODE_11NG_HT40PLUS: | |
3296 | case ATH9K_MODE_11NG_HT40MINUS: | |
3297 | rt = &ar5416_11ng_table; | |
3298 | break; | |
3299 | case ATH9K_MODE_11NA_HT20: | |
3300 | case ATH9K_MODE_11NA_HT40PLUS: | |
3301 | case ATH9K_MODE_11NA_HT40MINUS: | |
3302 | rt = &ar5416_11na_table; | |
f078f209 | 3303 | break; |
f1dc5600 S |
3304 | default: |
3305 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n", | |
3306 | __func__, mode); | |
3307 | return NULL; | |
f078f209 | 3308 | } |
f1dc5600 S |
3309 | |
3310 | ath9k_hw_setup_rate_table(ah, rt); | |
3311 | ||
3312 | return rt; | |
f078f209 LR |
3313 | } |
3314 | ||
f1dc5600 S |
3315 | /*******************/ |
3316 | /* HW Capabilities */ | |
3317 | /*******************/ | |
3318 | ||
3319 | bool ath9k_hw_fill_cap_info(struct ath_hal *ah) | |
f078f209 LR |
3320 | { |
3321 | struct ath_hal_5416 *ahp = AH5416(ah); | |
60b67f51 | 3322 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; |
f1dc5600 | 3323 | u16 capField = 0, eeval; |
f078f209 | 3324 | |
f1dc5600 | 3325 | eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); |
f078f209 | 3326 | |
f1dc5600 | 3327 | ah->ah_currentRD = eeval; |
f078f209 | 3328 | |
f1dc5600 S |
3329 | eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); |
3330 | ah->ah_currentRDExt = eeval; | |
f078f209 | 3331 | |
f1dc5600 S |
3332 | capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); |
3333 | ||
3334 | if (ah->ah_opmode != ATH9K_M_HOSTAP && | |
3335 | ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { | |
3336 | if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65) | |
3337 | ah->ah_currentRD += 5; | |
3338 | else if (ah->ah_currentRD == 0x41) | |
3339 | ah->ah_currentRD = 0x43; | |
3340 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | |
3341 | "%s: regdomain mapped to 0x%x\n", __func__, | |
3342 | ah->ah_currentRD); | |
3343 | } | |
f078f209 | 3344 | |
f1dc5600 S |
3345 | eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); |
3346 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); | |
f078f209 | 3347 | |
f1dc5600 S |
3348 | if (eeval & AR5416_OPFLAGS_11A) { |
3349 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); | |
3350 | if (ah->ah_config.ht_enable) { | |
3351 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) | |
3352 | set_bit(ATH9K_MODE_11NA_HT20, | |
3353 | pCap->wireless_modes); | |
3354 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { | |
3355 | set_bit(ATH9K_MODE_11NA_HT40PLUS, | |
3356 | pCap->wireless_modes); | |
3357 | set_bit(ATH9K_MODE_11NA_HT40MINUS, | |
3358 | pCap->wireless_modes); | |
3359 | } | |
f078f209 | 3360 | } |
f078f209 LR |
3361 | } |
3362 | ||
f1dc5600 S |
3363 | if (eeval & AR5416_OPFLAGS_11G) { |
3364 | set_bit(ATH9K_MODE_11B, pCap->wireless_modes); | |
3365 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); | |
3366 | if (ah->ah_config.ht_enable) { | |
3367 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) | |
3368 | set_bit(ATH9K_MODE_11NG_HT20, | |
3369 | pCap->wireless_modes); | |
3370 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { | |
3371 | set_bit(ATH9K_MODE_11NG_HT40PLUS, | |
3372 | pCap->wireless_modes); | |
3373 | set_bit(ATH9K_MODE_11NG_HT40MINUS, | |
3374 | pCap->wireless_modes); | |
3375 | } | |
3376 | } | |
f078f209 | 3377 | } |
f1dc5600 S |
3378 | |
3379 | pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); | |
3380 | if ((ah->ah_isPciExpress) | |
3381 | || (eeval & AR5416_OPFLAGS_11A)) { | |
3382 | pCap->rx_chainmask = | |
3383 | ath9k_hw_get_eeprom(ah, EEP_RX_MASK); | |
f078f209 | 3384 | } else { |
f1dc5600 S |
3385 | pCap->rx_chainmask = |
3386 | (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; | |
f078f209 LR |
3387 | } |
3388 | ||
f1dc5600 S |
3389 | if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) |
3390 | ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; | |
f078f209 | 3391 | |
f1dc5600 S |
3392 | pCap->low_2ghz_chan = 2312; |
3393 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 3394 | |
f1dc5600 S |
3395 | pCap->low_5ghz_chan = 4920; |
3396 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 3397 | |
f1dc5600 S |
3398 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
3399 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; | |
3400 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; | |
f078f209 | 3401 | |
f1dc5600 S |
3402 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
3403 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | |
3404 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | |
f078f209 | 3405 | |
f1dc5600 | 3406 | pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; |
f078f209 | 3407 | |
f1dc5600 S |
3408 | if (ah->ah_config.ht_enable) |
3409 | pCap->hw_caps |= ATH9K_HW_CAP_HT; | |
3410 | else | |
3411 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 3412 | |
f1dc5600 S |
3413 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
3414 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; | |
3415 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; | |
3416 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; | |
f078f209 | 3417 | |
f1dc5600 S |
3418 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
3419 | pCap->total_queues = | |
3420 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
3421 | else | |
3422 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 3423 | |
f1dc5600 S |
3424 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
3425 | pCap->keycache_size = | |
3426 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
3427 | else | |
3428 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 3429 | |
f1dc5600 S |
3430 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
3431 | pCap->num_mr_retries = 4; | |
3432 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 3433 | |
f1dc5600 S |
3434 | if (AR_SREV_9280_10_OR_LATER(ah)) |
3435 | pCap->num_gpio_pins = AR928X_NUM_GPIO; | |
3436 | else | |
3437 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 3438 | |
f1dc5600 S |
3439 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
3440 | pCap->hw_caps |= ATH9K_HW_CAP_WOW; | |
3441 | pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | |
3442 | } else { | |
3443 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW; | |
3444 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | |
f078f209 LR |
3445 | } |
3446 | ||
f1dc5600 S |
3447 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
3448 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
3449 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
3450 | } else { | |
3451 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
3452 | } |
3453 | ||
f1dc5600 S |
3454 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
3455 | ||
3456 | #ifdef CONFIG_RFKILL | |
3457 | ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); | |
3458 | if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { | |
3459 | ah->ah_rfkill_gpio = | |
3460 | MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); | |
3461 | ah->ah_rfkill_polarity = | |
3462 | MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); | |
3463 | ||
3464 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 3465 | } |
f1dc5600 | 3466 | #endif |
f078f209 | 3467 | |
f1dc5600 S |
3468 | if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || |
3469 | (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || | |
3470 | (ah->ah_macVersion == AR_SREV_VERSION_9160) || | |
3471 | (ah->ah_macVersion == AR_SREV_VERSION_9100) || | |
3472 | (ah->ah_macVersion == AR_SREV_VERSION_9280)) | |
3473 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 3474 | else |
f1dc5600 | 3475 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
f078f209 | 3476 | |
f1dc5600 S |
3477 | if (AR_SREV_9280(ah)) |
3478 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; | |
3479 | else | |
3480 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 3481 | |
f1dc5600 S |
3482 | if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { |
3483 | pCap->reg_cap = | |
3484 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
3485 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
3486 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
3487 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 3488 | } else { |
f1dc5600 S |
3489 | pCap->reg_cap = |
3490 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
3491 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 3492 | } |
f078f209 | 3493 | |
f1dc5600 S |
3494 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
3495 | ||
3496 | pCap->num_antcfg_5ghz = | |
3497 | ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ); | |
3498 | pCap->num_antcfg_2ghz = | |
3499 | ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ); | |
f078f209 | 3500 | |
f1dc5600 | 3501 | return true; |
f078f209 LR |
3502 | } |
3503 | ||
f1dc5600 S |
3504 | bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, |
3505 | u32 capability, u32 *result) | |
f078f209 | 3506 | { |
f1dc5600 S |
3507 | struct ath_hal_5416 *ahp = AH5416(ah); |
3508 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | |
f078f209 | 3509 | |
f1dc5600 S |
3510 | switch (type) { |
3511 | case ATH9K_CAP_CIPHER: | |
3512 | switch (capability) { | |
3513 | case ATH9K_CIPHER_AES_CCM: | |
3514 | case ATH9K_CIPHER_AES_OCB: | |
3515 | case ATH9K_CIPHER_TKIP: | |
3516 | case ATH9K_CIPHER_WEP: | |
3517 | case ATH9K_CIPHER_MIC: | |
3518 | case ATH9K_CIPHER_CLR: | |
3519 | return true; | |
3520 | default: | |
3521 | return false; | |
3522 | } | |
3523 | case ATH9K_CAP_TKIP_MIC: | |
3524 | switch (capability) { | |
3525 | case 0: | |
3526 | return true; | |
3527 | case 1: | |
3528 | return (ahp->ah_staId1Defaults & | |
3529 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : | |
3530 | false; | |
3531 | } | |
3532 | case ATH9K_CAP_TKIP_SPLIT: | |
3533 | return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? | |
3534 | false : true; | |
3535 | case ATH9K_CAP_WME_TKIPMIC: | |
3536 | return 0; | |
3537 | case ATH9K_CAP_PHYCOUNTERS: | |
3538 | return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; | |
3539 | case ATH9K_CAP_DIVERSITY: | |
3540 | return (REG_READ(ah, AR_PHY_CCK_DETECT) & | |
3541 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? | |
3542 | true : false; | |
3543 | case ATH9K_CAP_PHYDIAG: | |
3544 | return true; | |
3545 | case ATH9K_CAP_MCAST_KEYSRCH: | |
3546 | switch (capability) { | |
3547 | case 0: | |
3548 | return true; | |
3549 | case 1: | |
3550 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { | |
3551 | return false; | |
3552 | } else { | |
3553 | return (ahp->ah_staId1Defaults & | |
3554 | AR_STA_ID1_MCAST_KSRCH) ? true : | |
3555 | false; | |
3556 | } | |
3557 | } | |
3558 | return false; | |
3559 | case ATH9K_CAP_TSF_ADJUST: | |
3560 | return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? | |
3561 | true : false; | |
3562 | case ATH9K_CAP_RFSILENT: | |
3563 | if (capability == 3) | |
3564 | return false; | |
3565 | case ATH9K_CAP_ANT_CFG_2GHZ: | |
3566 | *result = pCap->num_antcfg_2ghz; | |
3567 | return true; | |
3568 | case ATH9K_CAP_ANT_CFG_5GHZ: | |
3569 | *result = pCap->num_antcfg_5ghz; | |
3570 | return true; | |
3571 | case ATH9K_CAP_TXPOW: | |
3572 | switch (capability) { | |
3573 | case 0: | |
3574 | return 0; | |
3575 | case 1: | |
3576 | *result = ah->ah_powerLimit; | |
3577 | return 0; | |
3578 | case 2: | |
3579 | *result = ah->ah_maxPowerLevel; | |
3580 | return 0; | |
3581 | case 3: | |
3582 | *result = ah->ah_tpScale; | |
3583 | return 0; | |
3584 | } | |
3585 | return false; | |
3586 | default: | |
3587 | return false; | |
f078f209 | 3588 | } |
f078f209 LR |
3589 | } |
3590 | ||
f1dc5600 S |
3591 | bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, |
3592 | u32 capability, u32 setting, int *status) | |
f078f209 | 3593 | { |
f078f209 | 3594 | struct ath_hal_5416 *ahp = AH5416(ah); |
f1dc5600 | 3595 | u32 v; |
f078f209 | 3596 | |
f1dc5600 S |
3597 | switch (type) { |
3598 | case ATH9K_CAP_TKIP_MIC: | |
3599 | if (setting) | |
3600 | ahp->ah_staId1Defaults |= | |
3601 | AR_STA_ID1_CRPT_MIC_ENABLE; | |
3602 | else | |
3603 | ahp->ah_staId1Defaults &= | |
3604 | ~AR_STA_ID1_CRPT_MIC_ENABLE; | |
3605 | return true; | |
3606 | case ATH9K_CAP_DIVERSITY: | |
3607 | v = REG_READ(ah, AR_PHY_CCK_DETECT); | |
3608 | if (setting) | |
3609 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
3610 | else | |
3611 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
3612 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); | |
3613 | return true; | |
3614 | case ATH9K_CAP_MCAST_KEYSRCH: | |
3615 | if (setting) | |
3616 | ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; | |
3617 | else | |
3618 | ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; | |
3619 | return true; | |
3620 | case ATH9K_CAP_TSF_ADJUST: | |
3621 | if (setting) | |
3622 | ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; | |
3623 | else | |
3624 | ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; | |
3625 | return true; | |
3626 | default: | |
3627 | return false; | |
f078f209 LR |
3628 | } |
3629 | } | |
3630 | ||
f1dc5600 S |
3631 | /****************************/ |
3632 | /* GPIO / RFKILL / Antennae */ | |
3633 | /****************************/ | |
f078f209 | 3634 | |
f1dc5600 S |
3635 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, |
3636 | u32 gpio, u32 type) | |
3637 | { | |
3638 | int addr; | |
3639 | u32 gpio_shift, tmp; | |
f078f209 | 3640 | |
f1dc5600 S |
3641 | if (gpio > 11) |
3642 | addr = AR_GPIO_OUTPUT_MUX3; | |
3643 | else if (gpio > 5) | |
3644 | addr = AR_GPIO_OUTPUT_MUX2; | |
3645 | else | |
3646 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 3647 | |
f1dc5600 | 3648 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 3649 | |
f1dc5600 S |
3650 | if (AR_SREV_9280_20_OR_LATER(ah) |
3651 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
3652 | REG_RMW(ah, addr, (type << gpio_shift), | |
3653 | (0x1f << gpio_shift)); | |
f078f209 | 3654 | } else { |
f1dc5600 S |
3655 | tmp = REG_READ(ah, addr); |
3656 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
3657 | tmp &= ~(0x1f << gpio_shift); | |
3658 | tmp |= (type << gpio_shift); | |
3659 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 3660 | } |
f078f209 LR |
3661 | } |
3662 | ||
f1dc5600 | 3663 | void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) |
f078f209 | 3664 | { |
f1dc5600 | 3665 | u32 gpio_shift; |
f078f209 | 3666 | |
f1dc5600 | 3667 | ASSERT(gpio < ah->ah_caps.num_gpio_pins); |
f078f209 | 3668 | |
f1dc5600 | 3669 | gpio_shift = gpio << 1; |
f078f209 | 3670 | |
f1dc5600 S |
3671 | REG_RMW(ah, |
3672 | AR_GPIO_OE_OUT, | |
3673 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
3674 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 LR |
3675 | } |
3676 | ||
f1dc5600 | 3677 | u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) |
f078f209 | 3678 | { |
f1dc5600 S |
3679 | if (gpio >= ah->ah_caps.num_gpio_pins) |
3680 | return 0xffffffff; | |
f078f209 | 3681 | |
f1dc5600 S |
3682 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
3683 | return (MS | |
3684 | (REG_READ(ah, AR_GPIO_IN_OUT), | |
3685 | AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; | |
3686 | } else { | |
3687 | return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) & | |
3688 | AR_GPIO_BIT(gpio)) != 0; | |
3689 | } | |
f078f209 LR |
3690 | } |
3691 | ||
f1dc5600 S |
3692 | void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, |
3693 | u32 ah_signal_type) | |
f078f209 | 3694 | { |
f1dc5600 | 3695 | u32 gpio_shift; |
f078f209 | 3696 | |
f1dc5600 | 3697 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f078f209 | 3698 | |
f1dc5600 | 3699 | gpio_shift = 2 * gpio; |
f078f209 | 3700 | |
f1dc5600 S |
3701 | REG_RMW(ah, |
3702 | AR_GPIO_OE_OUT, | |
3703 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
3704 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 LR |
3705 | } |
3706 | ||
f1dc5600 | 3707 | void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) |
f078f209 | 3708 | { |
f1dc5600 S |
3709 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
3710 | AR_GPIO_BIT(gpio)); | |
f078f209 LR |
3711 | } |
3712 | ||
f1dc5600 S |
3713 | #ifdef CONFIG_RFKILL |
3714 | void ath9k_enable_rfkill(struct ath_hal *ah) | |
f078f209 | 3715 | { |
f1dc5600 S |
3716 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, |
3717 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | |
f078f209 | 3718 | |
f1dc5600 S |
3719 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, |
3720 | AR_GPIO_INPUT_MUX2_RFSILENT); | |
3721 | ||
3722 | ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); | |
3723 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | |
f078f209 | 3724 | } |
f1dc5600 | 3725 | #endif |
f078f209 | 3726 | |
f1dc5600 | 3727 | int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg) |
f078f209 | 3728 | { |
f1dc5600 S |
3729 | struct ath9k_channel *chan = ah->ah_curchan; |
3730 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | |
3731 | u16 ant_config; | |
3732 | u32 halNumAntConfig; | |
f078f209 | 3733 | |
f1dc5600 S |
3734 | halNumAntConfig = IS_CHAN_2GHZ(chan) ? |
3735 | pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz; | |
f078f209 | 3736 | |
f1dc5600 S |
3737 | if (cfg < halNumAntConfig) { |
3738 | if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan, | |
3739 | cfg, &ant_config)) { | |
3740 | REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); | |
3741 | return 0; | |
f078f209 | 3742 | } |
f078f209 LR |
3743 | } |
3744 | ||
f1dc5600 | 3745 | return -EINVAL; |
f078f209 LR |
3746 | } |
3747 | ||
f1dc5600 | 3748 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah) |
f078f209 | 3749 | { |
f1dc5600 | 3750 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 LR |
3751 | } |
3752 | ||
f1dc5600 | 3753 | void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) |
f078f209 | 3754 | { |
f1dc5600 | 3755 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 LR |
3756 | } |
3757 | ||
f1dc5600 S |
3758 | bool ath9k_hw_setantennaswitch(struct ath_hal *ah, |
3759 | enum ath9k_ant_setting settings, | |
3760 | struct ath9k_channel *chan, | |
3761 | u8 *tx_chainmask, | |
3762 | u8 *rx_chainmask, | |
3763 | u8 *antenna_cfgd) | |
f078f209 | 3764 | { |
f1dc5600 S |
3765 | struct ath_hal_5416 *ahp = AH5416(ah); |
3766 | static u8 tx_chainmask_cfg, rx_chainmask_cfg; | |
f078f209 | 3767 | |
f1dc5600 S |
3768 | if (AR_SREV_9280(ah)) { |
3769 | if (!tx_chainmask_cfg) { | |
f078f209 | 3770 | |
f1dc5600 S |
3771 | tx_chainmask_cfg = *tx_chainmask; |
3772 | rx_chainmask_cfg = *rx_chainmask; | |
3773 | } | |
f078f209 | 3774 | |
f1dc5600 S |
3775 | switch (settings) { |
3776 | case ATH9K_ANT_FIXED_A: | |
3777 | *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | |
3778 | *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | |
3779 | *antenna_cfgd = true; | |
3780 | break; | |
3781 | case ATH9K_ANT_FIXED_B: | |
3782 | if (ah->ah_caps.tx_chainmask > | |
3783 | ATH9K_ANTENNA1_CHAINMASK) { | |
3784 | *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | |
3785 | } | |
3786 | *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | |
3787 | *antenna_cfgd = true; | |
3788 | break; | |
3789 | case ATH9K_ANT_VARIABLE: | |
3790 | *tx_chainmask = tx_chainmask_cfg; | |
3791 | *rx_chainmask = rx_chainmask_cfg; | |
3792 | *antenna_cfgd = true; | |
3793 | break; | |
3794 | default: | |
3795 | break; | |
3796 | } | |
3797 | } else { | |
3798 | ahp->ah_diversityControl = settings; | |
f078f209 | 3799 | } |
f078f209 | 3800 | |
f1dc5600 | 3801 | return true; |
f078f209 LR |
3802 | } |
3803 | ||
f1dc5600 S |
3804 | /*********************/ |
3805 | /* General Operation */ | |
3806 | /*********************/ | |
3807 | ||
3808 | u32 ath9k_hw_getrxfilter(struct ath_hal *ah) | |
f078f209 | 3809 | { |
f1dc5600 S |
3810 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
3811 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 3812 | |
f1dc5600 S |
3813 | if (phybits & AR_PHY_ERR_RADAR) |
3814 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
3815 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
3816 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 3817 | |
f1dc5600 | 3818 | return bits; |
f078f209 LR |
3819 | } |
3820 | ||
f1dc5600 | 3821 | void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) |
f078f209 | 3822 | { |
f1dc5600 | 3823 | u32 phybits; |
f078f209 | 3824 | |
f1dc5600 S |
3825 | REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); |
3826 | phybits = 0; | |
3827 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
3828 | phybits |= AR_PHY_ERR_RADAR; | |
3829 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
3830 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
3831 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 3832 | |
f1dc5600 S |
3833 | if (phybits) |
3834 | REG_WRITE(ah, AR_RXCFG, | |
3835 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
3836 | else | |
3837 | REG_WRITE(ah, AR_RXCFG, | |
3838 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
3839 | } | |
f078f209 | 3840 | |
f1dc5600 S |
3841 | bool ath9k_hw_phy_disable(struct ath_hal *ah) |
3842 | { | |
3843 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); | |
3844 | } | |
f078f209 | 3845 | |
f1dc5600 S |
3846 | bool ath9k_hw_disable(struct ath_hal *ah) |
3847 | { | |
3848 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | |
3849 | return false; | |
f078f209 | 3850 | |
f1dc5600 | 3851 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); |
f078f209 LR |
3852 | } |
3853 | ||
f1dc5600 | 3854 | bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) |
f078f209 | 3855 | { |
f1dc5600 | 3856 | struct ath9k_channel *chan = ah->ah_curchan; |
f078f209 | 3857 | |
f1dc5600 | 3858 | ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 3859 | |
f1dc5600 S |
3860 | if (ath9k_hw_set_txpower(ah, chan, |
3861 | ath9k_regd_get_ctl(ah, chan), | |
3862 | ath9k_regd_get_antenna_allowed(ah, chan), | |
3863 | chan->maxRegTxPower * 2, | |
3864 | min((u32) MAX_RATE_POWER, | |
3865 | (u32) ah->ah_powerLimit)) != 0) | |
6f255425 | 3866 | return false; |
f1dc5600 | 3867 | |
6f255425 LR |
3868 | return true; |
3869 | } | |
3870 | ||
f1dc5600 | 3871 | void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) |
f078f209 | 3872 | { |
f1dc5600 | 3873 | struct ath_hal_5416 *ahp = AH5416(ah); |
6f255425 | 3874 | |
f1dc5600 | 3875 | memcpy(mac, ahp->ah_macaddr, ETH_ALEN); |
f078f209 LR |
3876 | } |
3877 | ||
f1dc5600 | 3878 | bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) |
f078f209 LR |
3879 | { |
3880 | struct ath_hal_5416 *ahp = AH5416(ah); | |
3881 | ||
f1dc5600 S |
3882 | memcpy(ahp->ah_macaddr, mac, ETH_ALEN); |
3883 | ||
f078f209 LR |
3884 | return true; |
3885 | } | |
3886 | ||
f1dc5600 | 3887 | void ath9k_hw_setopmode(struct ath_hal *ah) |
f078f209 | 3888 | { |
f1dc5600 | 3889 | ath9k_hw_set_operating_mode(ah, ah->ah_opmode); |
f078f209 LR |
3890 | } |
3891 | ||
f1dc5600 | 3892 | void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) |
f078f209 | 3893 | { |
f1dc5600 S |
3894 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
3895 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 LR |
3896 | } |
3897 | ||
f1dc5600 | 3898 | void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) |
f078f209 | 3899 | { |
f1dc5600 | 3900 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 | 3901 | |
f1dc5600 | 3902 | memcpy(mask, ahp->ah_bssidmask, ETH_ALEN); |
f078f209 LR |
3903 | } |
3904 | ||
f1dc5600 | 3905 | bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) |
f078f209 | 3906 | { |
f1dc5600 S |
3907 | struct ath_hal_5416 *ahp = AH5416(ah); |
3908 | ||
3909 | memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); | |
f078f209 | 3910 | |
f1dc5600 S |
3911 | REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); |
3912 | REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); | |
f078f209 LR |
3913 | |
3914 | return true; | |
3915 | } | |
3916 | ||
f1dc5600 | 3917 | void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId) |
f078f209 | 3918 | { |
f1dc5600 | 3919 | struct ath_hal_5416 *ahp = AH5416(ah); |
f078f209 | 3920 | |
f1dc5600 S |
3921 | memcpy(ahp->ah_bssid, bssid, ETH_ALEN); |
3922 | ahp->ah_assocId = assocId; | |
f078f209 | 3923 | |
f1dc5600 S |
3924 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); |
3925 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | | |
3926 | ((assocId & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 LR |
3927 | } |
3928 | ||
f1dc5600 | 3929 | u64 ath9k_hw_gettsf64(struct ath_hal *ah) |
f078f209 | 3930 | { |
f1dc5600 | 3931 | u64 tsf; |
f078f209 | 3932 | |
f1dc5600 S |
3933 | tsf = REG_READ(ah, AR_TSF_U32); |
3934 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); | |
f078f209 | 3935 | |
f1dc5600 S |
3936 | return tsf; |
3937 | } | |
f078f209 | 3938 | |
f1dc5600 S |
3939 | void ath9k_hw_reset_tsf(struct ath_hal *ah) |
3940 | { | |
3941 | int count; | |
f078f209 | 3942 | |
f1dc5600 S |
3943 | count = 0; |
3944 | while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { | |
3945 | count++; | |
3946 | if (count > 10) { | |
3947 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | |
3948 | "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", | |
3949 | __func__); | |
3950 | break; | |
f078f209 | 3951 | } |
f1dc5600 S |
3952 | udelay(10); |
3953 | } | |
3954 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); | |
3955 | } | |
f078f209 | 3956 | |
f1dc5600 S |
3957 | bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) |
3958 | { | |
3959 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f078f209 | 3960 | |
f1dc5600 S |
3961 | if (setting) |
3962 | ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; | |
3963 | else | |
3964 | ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; | |
f078f209 | 3965 | |
f1dc5600 S |
3966 | return true; |
3967 | } | |
f078f209 | 3968 | |
f1dc5600 S |
3969 | bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) |
3970 | { | |
3971 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f078f209 | 3972 | |
f1dc5600 S |
3973 | if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { |
3974 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n", | |
3975 | __func__, us); | |
3976 | ahp->ah_slottime = (u32) -1; | |
3977 | return false; | |
3978 | } else { | |
3979 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); | |
3980 | ahp->ah_slottime = us; | |
3981 | return true; | |
f078f209 | 3982 | } |
f1dc5600 S |
3983 | } |
3984 | ||
3985 | void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) | |
3986 | { | |
3987 | u32 macmode; | |
3988 | ||
3989 | if (mode == ATH9K_HT_MACMODE_2040 && | |
3990 | !ah->ah_config.cwm_ignore_extcca) | |
3991 | macmode = AR_2040_JOINED_RX_CLEAR; | |
3992 | else | |
3993 | macmode = 0; | |
f078f209 | 3994 | |
f1dc5600 | 3995 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 3996 | } |