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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
30 | ||
3a702e49 BC |
31 | #include "../ath/regd.h" |
32 | ||
394cf0a1 S |
33 | #define ATHEROS_VENDOR_ID 0x168c |
34 | #define AR5416_DEVID_PCI 0x0023 | |
35 | #define AR5416_DEVID_PCIE 0x0024 | |
36 | #define AR9160_DEVID_PCI 0x0027 | |
37 | #define AR9280_DEVID_PCI 0x0029 | |
38 | #define AR9280_DEVID_PCIE 0x002a | |
39 | #define AR9285_DEVID_PCIE 0x002b | |
40 | #define AR5416_AR9100_DEVID 0x000b | |
41 | #define AR_SUBVENDOR_ID_NOG 0x0e11 | |
42 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
43 | #define AR5416_MAGIC 0x19641014 | |
44 | ||
45 | /* Register read/write primitives */ | |
2d6a5e95 DM |
46 | #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) |
47 | #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) | |
394cf0a1 S |
48 | |
49 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | |
50 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
51 | #define REG_RMW(_a, _r, _set, _clr) \ | |
52 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
53 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
54 | REG_WRITE(_a, _r, \ | |
55 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
56 | #define REG_SET_BIT(_a, _r, _f) \ | |
57 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
58 | #define REG_CLR_BIT(_a, _r, _f) \ | |
59 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
f078f209 | 60 | |
394cf0a1 S |
61 | #define DO_DELAY(x) do { \ |
62 | if ((++(x) % 64) == 0) \ | |
63 | udelay(1); \ | |
64 | } while (0) | |
f078f209 | 65 | |
394cf0a1 S |
66 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
67 | int r; \ | |
68 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
69 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | |
70 | INI_RA((iniarray), r, (column))); \ | |
71 | DO_DELAY(regWr); \ | |
72 | } \ | |
73 | } while (0) | |
f078f209 | 74 | |
394cf0a1 S |
75 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
76 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
77 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
78 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
79 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 | |
80 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 81 | |
394cf0a1 S |
82 | #define AR_GPIOD_MASK 0x00001FFF |
83 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 84 | |
394cf0a1 S |
85 | #define BASE_ACTIVATE_DELAY 100 |
86 | #define RTC_PLL_SETTLE_DELAY 1000 | |
87 | #define COEF_SCALE_S 24 | |
88 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 89 | |
394cf0a1 S |
90 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
91 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
92 | ||
93 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
94 | #define ATH9K_NUM_QUEUES 10 | |
95 | ||
96 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 97 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
394cf0a1 S |
98 | #define AH_TIME_QUANTUM 10 |
99 | #define AR_KEYTABLE_SIZE 128 | |
100 | #define POWER_UP_TIME 200000 | |
101 | #define SPUR_RSSI_THRESH 40 | |
102 | ||
103 | #define CAB_TIMEOUT_VAL 10 | |
104 | #define BEACON_TIMEOUT_VAL 10 | |
105 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
106 | #define SLEEP_SLOP 3 | |
107 | ||
108 | #define INIT_CONFIG_STATUS 0x00000000 | |
109 | #define INIT_RSSI_THR 0x00000700 | |
110 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
111 | ||
112 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
113 | ||
114 | enum wireless_mode { | |
115 | ATH9K_MODE_11A = 0, | |
116 | ATH9K_MODE_11B = 2, | |
117 | ATH9K_MODE_11G = 3, | |
118 | ATH9K_MODE_11NA_HT20 = 6, | |
119 | ATH9K_MODE_11NG_HT20 = 7, | |
120 | ATH9K_MODE_11NA_HT40PLUS = 8, | |
121 | ATH9K_MODE_11NA_HT40MINUS = 9, | |
122 | ATH9K_MODE_11NG_HT40PLUS = 10, | |
123 | ATH9K_MODE_11NG_HT40MINUS = 11, | |
124 | ATH9K_MODE_MAX | |
125 | }; | |
f078f209 | 126 | |
394cf0a1 | 127 | enum ath9k_hw_caps { |
bdbdf46d S |
128 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
129 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), | |
130 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), | |
131 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), | |
132 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), | |
133 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), | |
134 | ATH9K_HW_CAP_VEOL = BIT(6), | |
135 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), | |
136 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), | |
137 | ATH9K_HW_CAP_HT = BIT(9), | |
138 | ATH9K_HW_CAP_GTT = BIT(10), | |
139 | ATH9K_HW_CAP_FASTCC = BIT(11), | |
140 | ATH9K_HW_CAP_RFSILENT = BIT(12), | |
141 | ATH9K_HW_CAP_CST = BIT(13), | |
142 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), | |
143 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), | |
144 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), | |
145 | ATH9K_HW_CAP_BT_COEX = BIT(17) | |
394cf0a1 | 146 | }; |
f078f209 | 147 | |
394cf0a1 S |
148 | enum ath9k_capability_type { |
149 | ATH9K_CAP_CIPHER = 0, | |
150 | ATH9K_CAP_TKIP_MIC, | |
151 | ATH9K_CAP_TKIP_SPLIT, | |
394cf0a1 S |
152 | ATH9K_CAP_DIVERSITY, |
153 | ATH9K_CAP_TXPOW, | |
394cf0a1 | 154 | ATH9K_CAP_MCAST_KEYSRCH, |
8bd1d07f | 155 | ATH9K_CAP_DS |
394cf0a1 | 156 | }; |
f078f209 | 157 | |
394cf0a1 S |
158 | struct ath9k_hw_capabilities { |
159 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
160 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | |
161 | u16 total_queues; | |
162 | u16 keycache_size; | |
163 | u16 low_5ghz_chan, high_5ghz_chan; | |
164 | u16 low_2ghz_chan, high_2ghz_chan; | |
394cf0a1 S |
165 | u16 rts_aggr_limit; |
166 | u8 tx_chainmask; | |
167 | u8 rx_chainmask; | |
168 | u16 tx_triglevel_max; | |
169 | u16 reg_cap; | |
170 | u8 num_gpio_pins; | |
171 | u8 num_antcfg_2ghz; | |
172 | u8 num_antcfg_5ghz; | |
173 | }; | |
f078f209 | 174 | |
394cf0a1 S |
175 | struct ath9k_ops_config { |
176 | int dma_beacon_response_time; | |
177 | int sw_beacon_response_time; | |
178 | int additional_swba_backoff; | |
179 | int ack_6mb; | |
180 | int cwm_ignore_extcca; | |
181 | u8 pcie_powersave_enable; | |
394cf0a1 S |
182 | u8 pcie_clock_req; |
183 | u32 pcie_waen; | |
394cf0a1 S |
184 | u8 analog_shiftreg; |
185 | u8 ht_enable; | |
186 | u32 ofdm_trig_low; | |
187 | u32 ofdm_trig_high; | |
188 | u32 cck_trig_high; | |
189 | u32 cck_trig_low; | |
190 | u32 enable_ani; | |
394cf0a1 S |
191 | u16 diversity_control; |
192 | u16 antenna_switch_swap; | |
193 | int serialize_regmode; | |
0ef1f168 | 194 | bool intr_mitigation; |
394cf0a1 S |
195 | #define SPUR_DISABLE 0 |
196 | #define SPUR_ENABLE_IOCTL 1 | |
197 | #define SPUR_ENABLE_EEPROM 2 | |
198 | #define AR_EEPROM_MODAL_SPURS 5 | |
199 | #define AR_SPUR_5413_1 1640 | |
200 | #define AR_SPUR_5413_2 1200 | |
201 | #define AR_NO_SPUR 0x8000 | |
202 | #define AR_BASE_FREQ_2GHZ 2300 | |
203 | #define AR_BASE_FREQ_5GHZ 4900 | |
204 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
205 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
206 | int spurmode; | |
207 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
208 | }; | |
f078f209 | 209 | |
394cf0a1 S |
210 | enum ath9k_int { |
211 | ATH9K_INT_RX = 0x00000001, | |
212 | ATH9K_INT_RXDESC = 0x00000002, | |
213 | ATH9K_INT_RXNOFRM = 0x00000008, | |
214 | ATH9K_INT_RXEOL = 0x00000010, | |
215 | ATH9K_INT_RXORN = 0x00000020, | |
216 | ATH9K_INT_TX = 0x00000040, | |
217 | ATH9K_INT_TXDESC = 0x00000080, | |
218 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
219 | ATH9K_INT_TXURN = 0x00000800, | |
220 | ATH9K_INT_MIB = 0x00001000, | |
221 | ATH9K_INT_RXPHY = 0x00004000, | |
222 | ATH9K_INT_RXKCM = 0x00008000, | |
223 | ATH9K_INT_SWBA = 0x00010000, | |
224 | ATH9K_INT_BMISS = 0x00040000, | |
225 | ATH9K_INT_BNR = 0x00100000, | |
226 | ATH9K_INT_TIM = 0x00200000, | |
227 | ATH9K_INT_DTIM = 0x00400000, | |
228 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
229 | ATH9K_INT_GPIO = 0x01000000, | |
230 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 231 | ATH9K_INT_TSFOOR = 0x04000000, |
394cf0a1 S |
232 | ATH9K_INT_CST = 0x10000000, |
233 | ATH9K_INT_GTT = 0x20000000, | |
234 | ATH9K_INT_FATAL = 0x40000000, | |
235 | ATH9K_INT_GLOBAL = 0x80000000, | |
236 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
237 | ATH9K_INT_DTIM | | |
238 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 239 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
240 | ATH9K_INT_CABEND, |
241 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
242 | ATH9K_INT_RXDESC | | |
243 | ATH9K_INT_RXEOL | | |
244 | ATH9K_INT_RXORN | | |
245 | ATH9K_INT_TXURN | | |
246 | ATH9K_INT_TXDESC | | |
247 | ATH9K_INT_MIB | | |
248 | ATH9K_INT_RXPHY | | |
249 | ATH9K_INT_RXKCM | | |
250 | ATH9K_INT_SWBA | | |
251 | ATH9K_INT_BMISS | | |
252 | ATH9K_INT_GPIO, | |
253 | ATH9K_INT_NOCARD = 0xffffffff | |
254 | }; | |
f078f209 | 255 | |
394cf0a1 S |
256 | #define CHANNEL_CW_INT 0x00002 |
257 | #define CHANNEL_CCK 0x00020 | |
258 | #define CHANNEL_OFDM 0x00040 | |
259 | #define CHANNEL_2GHZ 0x00080 | |
260 | #define CHANNEL_5GHZ 0x00100 | |
261 | #define CHANNEL_PASSIVE 0x00200 | |
262 | #define CHANNEL_DYN 0x00400 | |
263 | #define CHANNEL_HALF 0x04000 | |
264 | #define CHANNEL_QUARTER 0x08000 | |
265 | #define CHANNEL_HT20 0x10000 | |
266 | #define CHANNEL_HT40PLUS 0x20000 | |
267 | #define CHANNEL_HT40MINUS 0x40000 | |
268 | ||
269 | #define CHANNEL_INTERFERENCE 0x01 | |
270 | #define CHANNEL_DFS 0x02 | |
271 | #define CHANNEL_4MS_LIMIT 0x04 | |
272 | #define CHANNEL_DFS_CLEAR 0x08 | |
273 | #define CHANNEL_DISALLOW_ADHOC 0x10 | |
274 | #define CHANNEL_PER_11D_ADHOC 0x20 | |
275 | ||
276 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) | |
277 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
278 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
279 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
280 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
281 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
282 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
283 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
284 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
285 | #define CHANNEL_ALL \ | |
286 | (CHANNEL_OFDM| \ | |
287 | CHANNEL_CCK| \ | |
288 | CHANNEL_2GHZ | \ | |
289 | CHANNEL_5GHZ | \ | |
290 | CHANNEL_HT20 | \ | |
291 | CHANNEL_HT40PLUS | \ | |
292 | CHANNEL_HT40MINUS) | |
293 | ||
294 | struct ath9k_channel { | |
295 | struct ieee80211_channel *chan; | |
296 | u16 channel; | |
297 | u32 channelFlags; | |
298 | u32 chanmode; | |
299 | int32_t CalValid; | |
300 | bool oneTimeCalsDone; | |
301 | int8_t iCoff; | |
302 | int8_t qCoff; | |
303 | int16_t rawNoiseFloor; | |
304 | }; | |
f078f209 | 305 | |
394cf0a1 S |
306 | #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ |
307 | (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ | |
308 | (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ | |
309 | (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) | |
310 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ | |
311 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
312 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
313 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
314 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
315 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
316 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
317 | #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) | |
318 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) | |
319 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
320 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | |
321 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | |
322 | (((_c)->channel % 20) != 0) && \ | |
323 | (((_c)->channel % 10) != 0)) | |
324 | ||
325 | /* These macros check chanmode and not channelFlags */ | |
326 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
327 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
328 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
329 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
330 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
331 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
332 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
333 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
334 | ||
335 | enum ath9k_power_mode { | |
336 | ATH9K_PM_AWAKE = 0, | |
337 | ATH9K_PM_FULL_SLEEP, | |
338 | ATH9K_PM_NETWORK_SLEEP, | |
339 | ATH9K_PM_UNDEFINED | |
340 | }; | |
f078f209 | 341 | |
394cf0a1 S |
342 | enum ath9k_ant_setting { |
343 | ATH9K_ANT_VARIABLE = 0, | |
344 | ATH9K_ANT_FIXED_A, | |
345 | ATH9K_ANT_FIXED_B | |
346 | }; | |
f078f209 | 347 | |
394cf0a1 S |
348 | enum ath9k_tp_scale { |
349 | ATH9K_TP_SCALE_MAX = 0, | |
350 | ATH9K_TP_SCALE_50, | |
351 | ATH9K_TP_SCALE_25, | |
352 | ATH9K_TP_SCALE_12, | |
353 | ATH9K_TP_SCALE_MIN | |
354 | }; | |
f078f209 | 355 | |
394cf0a1 S |
356 | enum ser_reg_mode { |
357 | SER_REG_MODE_OFF = 0, | |
358 | SER_REG_MODE_ON = 1, | |
359 | SER_REG_MODE_AUTO = 2, | |
360 | }; | |
f078f209 | 361 | |
394cf0a1 S |
362 | struct ath9k_beacon_state { |
363 | u32 bs_nexttbtt; | |
364 | u32 bs_nextdtim; | |
365 | u32 bs_intval; | |
366 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
367 | #define ATH9K_BEACON_ENA 0x00800000 | |
368 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
4af9cf4f | 369 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
370 | u32 bs_dtimperiod; |
371 | u16 bs_cfpperiod; | |
372 | u16 bs_cfpmaxduration; | |
373 | u32 bs_cfpnext; | |
374 | u16 bs_timoffset; | |
375 | u16 bs_bmissthreshold; | |
376 | u32 bs_sleepduration; | |
4af9cf4f | 377 | u32 bs_tsfoor_threshold; |
394cf0a1 | 378 | }; |
f078f209 | 379 | |
394cf0a1 S |
380 | struct chan_centers { |
381 | u16 synth_center; | |
382 | u16 ctl_center; | |
383 | u16 ext_center; | |
384 | }; | |
f078f209 | 385 | |
394cf0a1 S |
386 | enum { |
387 | ATH9K_RESET_POWER_ON, | |
388 | ATH9K_RESET_WARM, | |
389 | ATH9K_RESET_COLD, | |
390 | }; | |
f078f209 | 391 | |
d535a42a S |
392 | struct ath9k_hw_version { |
393 | u32 magic; | |
394 | u16 devid; | |
395 | u16 subvendorid; | |
396 | u32 macVersion; | |
397 | u16 macRev; | |
398 | u16 phyRev; | |
399 | u16 analog5GhzRev; | |
400 | u16 analog2GhzRev; | |
401 | }; | |
394cf0a1 | 402 | |
cbe61d8a | 403 | struct ath_hw { |
394cf0a1 | 404 | struct ath_softc *ah_sc; |
cbe61d8a | 405 | struct ath9k_hw_version hw_version; |
2660b81a S |
406 | struct ath9k_ops_config config; |
407 | struct ath9k_hw_capabilities caps; | |
3a702e49 | 408 | struct ath_regulatory regulatory; |
2660b81a S |
409 | struct ath9k_channel channels[38]; |
410 | struct ath9k_channel *curchan; | |
394cf0a1 | 411 | |
cbe61d8a S |
412 | union { |
413 | struct ar5416_eeprom_def def; | |
414 | struct ar5416_eeprom_4k map4k; | |
2660b81a | 415 | } eeprom; |
f74df6fb | 416 | const struct eeprom_ops *eep_ops; |
2660b81a | 417 | enum ath9k_eep_map eep_map; |
cbe61d8a S |
418 | |
419 | bool sw_mgmt_crypto; | |
2660b81a | 420 | bool is_pciexpress; |
cbe61d8a | 421 | u8 macaddr[ETH_ALEN]; |
2660b81a S |
422 | u16 tx_trig_level; |
423 | u16 rfsilent; | |
424 | u32 rfkill_gpio; | |
425 | u32 rfkill_polarity; | |
426 | u32 btactive_gpio; | |
427 | u32 wlanactive_gpio; | |
cbe61d8a | 428 | u32 ah_flags; |
394cf0a1 | 429 | |
2660b81a S |
430 | enum nl80211_iftype opmode; |
431 | enum ath9k_power_mode power_mode; | |
432 | enum ath9k_power_mode restore_mode; | |
f078f209 | 433 | |
cbe61d8a | 434 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
2660b81a S |
435 | struct ar5416Stats stats; |
436 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
437 | ||
438 | int16_t curchan_rad_index; | |
439 | u32 mask_reg; | |
440 | u32 txok_interrupt_mask; | |
441 | u32 txerr_interrupt_mask; | |
442 | u32 txdesc_interrupt_mask; | |
443 | u32 txeol_interrupt_mask; | |
444 | u32 txurn_interrupt_mask; | |
445 | bool chip_fullsleep; | |
446 | u32 atim_window; | |
447 | u16 antenna_switch_swap; | |
448 | enum ath9k_ant_setting diversity_control; | |
6a2b9e8c S |
449 | |
450 | /* Calibration */ | |
2660b81a S |
451 | enum hal_cal_types supp_cals; |
452 | struct hal_cal_list iq_caldata; | |
453 | struct hal_cal_list adcgain_caldata; | |
454 | struct hal_cal_list adcdc_calinitdata; | |
455 | struct hal_cal_list adcdc_caldata; | |
456 | struct hal_cal_list *cal_list; | |
457 | struct hal_cal_list *cal_list_last; | |
458 | struct hal_cal_list *cal_list_curr; | |
459 | #define totalPowerMeasI meas0.unsign | |
460 | #define totalPowerMeasQ meas1.unsign | |
461 | #define totalIqCorrMeas meas2.sign | |
462 | #define totalAdcIOddPhase meas0.unsign | |
463 | #define totalAdcIEvenPhase meas1.unsign | |
464 | #define totalAdcQOddPhase meas2.unsign | |
465 | #define totalAdcQEvenPhase meas3.unsign | |
466 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
467 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
468 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
469 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
470 | union { |
471 | u32 unsign[AR5416_MAX_CHAINS]; | |
472 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 473 | } meas0; |
f078f209 LR |
474 | union { |
475 | u32 unsign[AR5416_MAX_CHAINS]; | |
476 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 477 | } meas1; |
f078f209 LR |
478 | union { |
479 | u32 unsign[AR5416_MAX_CHAINS]; | |
480 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 481 | } meas2; |
f078f209 LR |
482 | union { |
483 | u32 unsign[AR5416_MAX_CHAINS]; | |
484 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
485 | } meas3; |
486 | u16 cal_samples; | |
6a2b9e8c | 487 | |
2660b81a S |
488 | u32 sta_id1_defaults; |
489 | u32 misc_mode; | |
f078f209 LR |
490 | enum { |
491 | AUTO_32KHZ, | |
492 | USE_32KHZ, | |
493 | DONT_USE_32KHZ, | |
2660b81a | 494 | } enable_32kHz_clock; |
6a2b9e8c S |
495 | |
496 | /* RF */ | |
2660b81a S |
497 | u32 *analogBank0Data; |
498 | u32 *analogBank1Data; | |
499 | u32 *analogBank2Data; | |
500 | u32 *analogBank3Data; | |
501 | u32 *analogBank6Data; | |
502 | u32 *analogBank6TPCData; | |
503 | u32 *analogBank7Data; | |
504 | u32 *addac5416_21; | |
505 | u32 *bank6Temp; | |
506 | ||
507 | int16_t txpower_indexoffset; | |
508 | u32 beacon_interval; | |
509 | u32 slottime; | |
510 | u32 acktimeout; | |
511 | u32 ctstimeout; | |
512 | u32 globaltxtimeout; | |
513 | u8 gbeacon_rate; | |
6a2b9e8c S |
514 | |
515 | /* ANI */ | |
2660b81a S |
516 | u32 proc_phyerr; |
517 | bool has_hw_phycounters; | |
518 | u32 aniperiod; | |
519 | struct ar5416AniState *curani; | |
520 | struct ar5416AniState ani[255]; | |
521 | int totalSizeDesired[5]; | |
522 | int coarse_high[5]; | |
523 | int coarse_low[5]; | |
524 | int firpwr[5]; | |
525 | enum ath9k_ani_cmd ani_function; | |
526 | ||
527 | u32 intr_txqs; | |
2660b81a S |
528 | enum ath9k_ht_extprotspacing extprotspacing; |
529 | u8 txchainmask; | |
530 | u8 rxchainmask; | |
531 | ||
8bd1d07f SB |
532 | u32 originalGain[22]; |
533 | int initPDADC; | |
534 | int PDADCdelta; | |
535 | ||
2660b81a S |
536 | struct ar5416IniArray iniModes; |
537 | struct ar5416IniArray iniCommon; | |
538 | struct ar5416IniArray iniBank0; | |
539 | struct ar5416IniArray iniBB_RfGain; | |
540 | struct ar5416IniArray iniBank1; | |
541 | struct ar5416IniArray iniBank2; | |
542 | struct ar5416IniArray iniBank3; | |
543 | struct ar5416IniArray iniBank6; | |
544 | struct ar5416IniArray iniBank6TPC; | |
545 | struct ar5416IniArray iniBank7; | |
546 | struct ar5416IniArray iniAddac; | |
547 | struct ar5416IniArray iniPcieSerdes; | |
548 | struct ar5416IniArray iniModesAdditional; | |
549 | struct ar5416IniArray iniModesRxGain; | |
550 | struct ar5416IniArray iniModesTxGain; | |
f078f209 | 551 | }; |
f078f209 | 552 | |
394cf0a1 S |
553 | /* Attach, Detach, Reset */ |
554 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); | |
cbe61d8a S |
555 | void ath9k_hw_detach(struct ath_hw *ah); |
556 | struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error); | |
557 | void ath9k_hw_rfdetach(struct ath_hw *ah); | |
558 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |
394cf0a1 | 559 | bool bChannelChange); |
eef7a574 | 560 | void ath9k_hw_fill_cap_info(struct ath_hw *ah); |
cbe61d8a | 561 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 | 562 | u32 capability, u32 *result); |
cbe61d8a | 563 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 S |
564 | u32 capability, u32 setting, int *status); |
565 | ||
566 | /* Key Cache Management */ | |
cbe61d8a S |
567 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
568 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); | |
569 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, | |
394cf0a1 | 570 | const struct ath9k_keyval *k, |
e0caf9ea | 571 | const u8 *mac); |
cbe61d8a | 572 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); |
394cf0a1 S |
573 | |
574 | /* GPIO / RFKILL / Antennae */ | |
cbe61d8a S |
575 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
576 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
577 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 578 | u32 ah_signal_type); |
cbe61d8a | 579 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
394cf0a1 | 580 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
cbe61d8a | 581 | void ath9k_enable_rfkill(struct ath_hw *ah); |
f078f209 | 582 | #endif |
cbe61d8a S |
583 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
584 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
585 | bool ath9k_hw_setantennaswitch(struct ath_hw *ah, | |
394cf0a1 S |
586 | enum ath9k_ant_setting settings, |
587 | struct ath9k_channel *chan, | |
588 | u8 *tx_chainmask, u8 *rx_chainmask, | |
589 | u8 *antenna_cfgd); | |
590 | ||
591 | /* General Operation */ | |
0caa7b14 | 592 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
394cf0a1 | 593 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
cbe61d8a S |
594 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
595 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, | |
394cf0a1 | 596 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 597 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
598 | struct ath9k_channel *chan, |
599 | struct chan_centers *centers); | |
cbe61d8a S |
600 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
601 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
602 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
603 | bool ath9k_hw_disable(struct ath_hw *ah); | |
604 | bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); | |
605 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); | |
606 | void ath9k_hw_setopmode(struct ath_hw *ah); | |
607 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
ba52da58 S |
608 | void ath9k_hw_setbssidmask(struct ath_softc *sc); |
609 | void ath9k_hw_write_associd(struct ath_softc *sc); | |
cbe61d8a S |
610 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
611 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
612 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
613 | bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); | |
614 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); | |
615 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); | |
616 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); | |
617 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 618 | const struct ath9k_beacon_state *bs); |
cbe61d8a | 619 | bool ath9k_hw_setpower(struct ath_hw *ah, |
394cf0a1 | 620 | enum ath9k_power_mode mode); |
cbe61d8a | 621 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore); |
394cf0a1 S |
622 | |
623 | /* Interrupt Handling */ | |
cbe61d8a S |
624 | bool ath9k_hw_intrpend(struct ath_hw *ah); |
625 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked); | |
626 | enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah); | |
627 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); | |
394cf0a1 | 628 | |
cbe61d8a | 629 | void ath9k_hw_btcoex_enable(struct ath_hw *ah); |
f078f209 LR |
630 | |
631 | #endif |