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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
28 | #include "regd.h" | |
29 | #include "reg.h" | |
30 | #include "phy.h" | |
31 | ||
32 | #define ATHEROS_VENDOR_ID 0x168c | |
33 | #define AR5416_DEVID_PCI 0x0023 | |
34 | #define AR5416_DEVID_PCIE 0x0024 | |
35 | #define AR9160_DEVID_PCI 0x0027 | |
36 | #define AR9280_DEVID_PCI 0x0029 | |
37 | #define AR9280_DEVID_PCIE 0x002a | |
38 | #define AR9285_DEVID_PCIE 0x002b | |
39 | #define AR5416_AR9100_DEVID 0x000b | |
40 | #define AR_SUBVENDOR_ID_NOG 0x0e11 | |
41 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
42 | #define AR5416_MAGIC 0x19641014 | |
43 | ||
44 | /* Register read/write primitives */ | |
2d6a5e95 DM |
45 | #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) |
46 | #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) | |
394cf0a1 S |
47 | |
48 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | |
49 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
50 | #define REG_RMW(_a, _r, _set, _clr) \ | |
51 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
52 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
53 | REG_WRITE(_a, _r, \ | |
54 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
55 | #define REG_SET_BIT(_a, _r, _f) \ | |
56 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
57 | #define REG_CLR_BIT(_a, _r, _f) \ | |
58 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
f078f209 | 59 | |
394cf0a1 S |
60 | #define DO_DELAY(x) do { \ |
61 | if ((++(x) % 64) == 0) \ | |
62 | udelay(1); \ | |
63 | } while (0) | |
f078f209 | 64 | |
394cf0a1 S |
65 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
66 | int r; \ | |
67 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
68 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | |
69 | INI_RA((iniarray), r, (column))); \ | |
70 | DO_DELAY(regWr); \ | |
71 | } \ | |
72 | } while (0) | |
f078f209 | 73 | |
394cf0a1 S |
74 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
75 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
76 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
77 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
78 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 | |
79 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 80 | |
394cf0a1 S |
81 | #define AR_GPIOD_MASK 0x00001FFF |
82 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 83 | |
394cf0a1 S |
84 | #define BASE_ACTIVATE_DELAY 100 |
85 | #define RTC_PLL_SETTLE_DELAY 1000 | |
86 | #define COEF_SCALE_S 24 | |
87 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 88 | |
394cf0a1 S |
89 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
90 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
91 | ||
92 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
93 | #define ATH9K_NUM_QUEUES 10 | |
94 | ||
95 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 96 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
394cf0a1 S |
97 | #define AH_TIME_QUANTUM 10 |
98 | #define AR_KEYTABLE_SIZE 128 | |
99 | #define POWER_UP_TIME 200000 | |
100 | #define SPUR_RSSI_THRESH 40 | |
101 | ||
102 | #define CAB_TIMEOUT_VAL 10 | |
103 | #define BEACON_TIMEOUT_VAL 10 | |
104 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
105 | #define SLEEP_SLOP 3 | |
106 | ||
107 | #define INIT_CONFIG_STATUS 0x00000000 | |
108 | #define INIT_RSSI_THR 0x00000700 | |
109 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
110 | ||
111 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
112 | ||
113 | enum wireless_mode { | |
114 | ATH9K_MODE_11A = 0, | |
115 | ATH9K_MODE_11B = 2, | |
116 | ATH9K_MODE_11G = 3, | |
117 | ATH9K_MODE_11NA_HT20 = 6, | |
118 | ATH9K_MODE_11NG_HT20 = 7, | |
119 | ATH9K_MODE_11NA_HT40PLUS = 8, | |
120 | ATH9K_MODE_11NA_HT40MINUS = 9, | |
121 | ATH9K_MODE_11NG_HT40PLUS = 10, | |
122 | ATH9K_MODE_11NG_HT40MINUS = 11, | |
123 | ATH9K_MODE_MAX | |
124 | }; | |
f078f209 | 125 | |
394cf0a1 S |
126 | enum ath9k_hw_caps { |
127 | ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), | |
128 | ATH9K_HW_CAP_MIC_AESCCM = BIT(1), | |
129 | ATH9K_HW_CAP_MIC_CKIP = BIT(2), | |
130 | ATH9K_HW_CAP_MIC_TKIP = BIT(3), | |
131 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), | |
132 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), | |
133 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), | |
134 | ATH9K_HW_CAP_VEOL = BIT(7), | |
135 | ATH9K_HW_CAP_BSSIDMASK = BIT(8), | |
136 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), | |
137 | ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), | |
138 | ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), | |
139 | ATH9K_HW_CAP_HT = BIT(12), | |
140 | ATH9K_HW_CAP_GTT = BIT(13), | |
141 | ATH9K_HW_CAP_FASTCC = BIT(14), | |
142 | ATH9K_HW_CAP_RFSILENT = BIT(15), | |
143 | ATH9K_HW_CAP_WOW = BIT(16), | |
144 | ATH9K_HW_CAP_CST = BIT(17), | |
145 | ATH9K_HW_CAP_ENHANCEDPM = BIT(18), | |
146 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), | |
147 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), | |
148 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), | |
149 | ATH9K_HW_CAP_BT_COEX = BIT(22) | |
150 | }; | |
f078f209 | 151 | |
394cf0a1 S |
152 | enum ath9k_capability_type { |
153 | ATH9K_CAP_CIPHER = 0, | |
154 | ATH9K_CAP_TKIP_MIC, | |
155 | ATH9K_CAP_TKIP_SPLIT, | |
394cf0a1 S |
156 | ATH9K_CAP_DIVERSITY, |
157 | ATH9K_CAP_TXPOW, | |
394cf0a1 | 158 | ATH9K_CAP_MCAST_KEYSRCH, |
8bd1d07f | 159 | ATH9K_CAP_DS |
394cf0a1 | 160 | }; |
f078f209 | 161 | |
394cf0a1 S |
162 | struct ath9k_hw_capabilities { |
163 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
164 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | |
165 | u16 total_queues; | |
166 | u16 keycache_size; | |
167 | u16 low_5ghz_chan, high_5ghz_chan; | |
168 | u16 low_2ghz_chan, high_2ghz_chan; | |
169 | u16 num_mr_retries; | |
170 | u16 rts_aggr_limit; | |
171 | u8 tx_chainmask; | |
172 | u8 rx_chainmask; | |
173 | u16 tx_triglevel_max; | |
174 | u16 reg_cap; | |
175 | u8 num_gpio_pins; | |
176 | u8 num_antcfg_2ghz; | |
177 | u8 num_antcfg_5ghz; | |
178 | }; | |
f078f209 | 179 | |
394cf0a1 S |
180 | struct ath9k_ops_config { |
181 | int dma_beacon_response_time; | |
182 | int sw_beacon_response_time; | |
183 | int additional_swba_backoff; | |
184 | int ack_6mb; | |
185 | int cwm_ignore_extcca; | |
186 | u8 pcie_powersave_enable; | |
187 | u8 pcie_l1skp_enable; | |
188 | u8 pcie_clock_req; | |
189 | u32 pcie_waen; | |
190 | int pcie_power_reset; | |
191 | u8 pcie_restore; | |
192 | u8 analog_shiftreg; | |
193 | u8 ht_enable; | |
194 | u32 ofdm_trig_low; | |
195 | u32 ofdm_trig_high; | |
196 | u32 cck_trig_high; | |
197 | u32 cck_trig_low; | |
198 | u32 enable_ani; | |
199 | u8 noise_immunity_level; | |
200 | u32 ofdm_weaksignal_det; | |
201 | u32 cck_weaksignal_thr; | |
202 | u8 spur_immunity_level; | |
203 | u8 firstep_level; | |
204 | int8_t rssi_thr_high; | |
205 | int8_t rssi_thr_low; | |
206 | u16 diversity_control; | |
207 | u16 antenna_switch_swap; | |
208 | int serialize_regmode; | |
209 | int intr_mitigation; | |
210 | #define SPUR_DISABLE 0 | |
211 | #define SPUR_ENABLE_IOCTL 1 | |
212 | #define SPUR_ENABLE_EEPROM 2 | |
213 | #define AR_EEPROM_MODAL_SPURS 5 | |
214 | #define AR_SPUR_5413_1 1640 | |
215 | #define AR_SPUR_5413_2 1200 | |
216 | #define AR_NO_SPUR 0x8000 | |
217 | #define AR_BASE_FREQ_2GHZ 2300 | |
218 | #define AR_BASE_FREQ_5GHZ 4900 | |
219 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
220 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
221 | int spurmode; | |
222 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
223 | }; | |
f078f209 | 224 | |
394cf0a1 S |
225 | enum ath9k_int { |
226 | ATH9K_INT_RX = 0x00000001, | |
227 | ATH9K_INT_RXDESC = 0x00000002, | |
228 | ATH9K_INT_RXNOFRM = 0x00000008, | |
229 | ATH9K_INT_RXEOL = 0x00000010, | |
230 | ATH9K_INT_RXORN = 0x00000020, | |
231 | ATH9K_INT_TX = 0x00000040, | |
232 | ATH9K_INT_TXDESC = 0x00000080, | |
233 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
234 | ATH9K_INT_TXURN = 0x00000800, | |
235 | ATH9K_INT_MIB = 0x00001000, | |
236 | ATH9K_INT_RXPHY = 0x00004000, | |
237 | ATH9K_INT_RXKCM = 0x00008000, | |
238 | ATH9K_INT_SWBA = 0x00010000, | |
239 | ATH9K_INT_BMISS = 0x00040000, | |
240 | ATH9K_INT_BNR = 0x00100000, | |
241 | ATH9K_INT_TIM = 0x00200000, | |
242 | ATH9K_INT_DTIM = 0x00400000, | |
243 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
244 | ATH9K_INT_GPIO = 0x01000000, | |
245 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 246 | ATH9K_INT_TSFOOR = 0x04000000, |
394cf0a1 S |
247 | ATH9K_INT_CST = 0x10000000, |
248 | ATH9K_INT_GTT = 0x20000000, | |
249 | ATH9K_INT_FATAL = 0x40000000, | |
250 | ATH9K_INT_GLOBAL = 0x80000000, | |
251 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
252 | ATH9K_INT_DTIM | | |
253 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 254 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
255 | ATH9K_INT_CABEND, |
256 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
257 | ATH9K_INT_RXDESC | | |
258 | ATH9K_INT_RXEOL | | |
259 | ATH9K_INT_RXORN | | |
260 | ATH9K_INT_TXURN | | |
261 | ATH9K_INT_TXDESC | | |
262 | ATH9K_INT_MIB | | |
263 | ATH9K_INT_RXPHY | | |
264 | ATH9K_INT_RXKCM | | |
265 | ATH9K_INT_SWBA | | |
266 | ATH9K_INT_BMISS | | |
267 | ATH9K_INT_GPIO, | |
268 | ATH9K_INT_NOCARD = 0xffffffff | |
269 | }; | |
f078f209 | 270 | |
394cf0a1 S |
271 | #define CHANNEL_CW_INT 0x00002 |
272 | #define CHANNEL_CCK 0x00020 | |
273 | #define CHANNEL_OFDM 0x00040 | |
274 | #define CHANNEL_2GHZ 0x00080 | |
275 | #define CHANNEL_5GHZ 0x00100 | |
276 | #define CHANNEL_PASSIVE 0x00200 | |
277 | #define CHANNEL_DYN 0x00400 | |
278 | #define CHANNEL_HALF 0x04000 | |
279 | #define CHANNEL_QUARTER 0x08000 | |
280 | #define CHANNEL_HT20 0x10000 | |
281 | #define CHANNEL_HT40PLUS 0x20000 | |
282 | #define CHANNEL_HT40MINUS 0x40000 | |
283 | ||
284 | #define CHANNEL_INTERFERENCE 0x01 | |
285 | #define CHANNEL_DFS 0x02 | |
286 | #define CHANNEL_4MS_LIMIT 0x04 | |
287 | #define CHANNEL_DFS_CLEAR 0x08 | |
288 | #define CHANNEL_DISALLOW_ADHOC 0x10 | |
289 | #define CHANNEL_PER_11D_ADHOC 0x20 | |
290 | ||
291 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) | |
292 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
293 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
294 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
295 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
296 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
297 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
298 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
299 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
300 | #define CHANNEL_ALL \ | |
301 | (CHANNEL_OFDM| \ | |
302 | CHANNEL_CCK| \ | |
303 | CHANNEL_2GHZ | \ | |
304 | CHANNEL_5GHZ | \ | |
305 | CHANNEL_HT20 | \ | |
306 | CHANNEL_HT40PLUS | \ | |
307 | CHANNEL_HT40MINUS) | |
308 | ||
309 | struct ath9k_channel { | |
310 | struct ieee80211_channel *chan; | |
311 | u16 channel; | |
312 | u32 channelFlags; | |
313 | u32 chanmode; | |
314 | int32_t CalValid; | |
315 | bool oneTimeCalsDone; | |
316 | int8_t iCoff; | |
317 | int8_t qCoff; | |
318 | int16_t rawNoiseFloor; | |
319 | }; | |
f078f209 | 320 | |
394cf0a1 S |
321 | #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ |
322 | (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ | |
323 | (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ | |
324 | (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) | |
325 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ | |
326 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
327 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
328 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
329 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
330 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
331 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
332 | #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) | |
333 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) | |
334 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
335 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | |
336 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | |
337 | (((_c)->channel % 20) != 0) && \ | |
338 | (((_c)->channel % 10) != 0)) | |
339 | ||
340 | /* These macros check chanmode and not channelFlags */ | |
341 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
342 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
343 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
344 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
345 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
346 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
347 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
348 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
349 | ||
350 | enum ath9k_power_mode { | |
351 | ATH9K_PM_AWAKE = 0, | |
352 | ATH9K_PM_FULL_SLEEP, | |
353 | ATH9K_PM_NETWORK_SLEEP, | |
354 | ATH9K_PM_UNDEFINED | |
355 | }; | |
f078f209 | 356 | |
394cf0a1 S |
357 | enum ath9k_ant_setting { |
358 | ATH9K_ANT_VARIABLE = 0, | |
359 | ATH9K_ANT_FIXED_A, | |
360 | ATH9K_ANT_FIXED_B | |
361 | }; | |
f078f209 | 362 | |
394cf0a1 S |
363 | enum ath9k_tp_scale { |
364 | ATH9K_TP_SCALE_MAX = 0, | |
365 | ATH9K_TP_SCALE_50, | |
366 | ATH9K_TP_SCALE_25, | |
367 | ATH9K_TP_SCALE_12, | |
368 | ATH9K_TP_SCALE_MIN | |
369 | }; | |
f078f209 | 370 | |
394cf0a1 S |
371 | enum ser_reg_mode { |
372 | SER_REG_MODE_OFF = 0, | |
373 | SER_REG_MODE_ON = 1, | |
374 | SER_REG_MODE_AUTO = 2, | |
375 | }; | |
f078f209 | 376 | |
394cf0a1 S |
377 | struct ath9k_beacon_state { |
378 | u32 bs_nexttbtt; | |
379 | u32 bs_nextdtim; | |
380 | u32 bs_intval; | |
381 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
382 | #define ATH9K_BEACON_ENA 0x00800000 | |
383 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
4af9cf4f | 384 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
385 | u32 bs_dtimperiod; |
386 | u16 bs_cfpperiod; | |
387 | u16 bs_cfpmaxduration; | |
388 | u32 bs_cfpnext; | |
389 | u16 bs_timoffset; | |
390 | u16 bs_bmissthreshold; | |
391 | u32 bs_sleepduration; | |
4af9cf4f | 392 | u32 bs_tsfoor_threshold; |
394cf0a1 | 393 | }; |
f078f209 | 394 | |
394cf0a1 S |
395 | struct chan_centers { |
396 | u16 synth_center; | |
397 | u16 ctl_center; | |
398 | u16 ext_center; | |
399 | }; | |
f078f209 | 400 | |
394cf0a1 S |
401 | enum { |
402 | ATH9K_RESET_POWER_ON, | |
403 | ATH9K_RESET_WARM, | |
404 | ATH9K_RESET_COLD, | |
405 | }; | |
f078f209 | 406 | |
d535a42a S |
407 | struct ath9k_hw_version { |
408 | u32 magic; | |
409 | u16 devid; | |
410 | u16 subvendorid; | |
411 | u32 macVersion; | |
412 | u16 macRev; | |
413 | u16 phyRev; | |
414 | u16 analog5GhzRev; | |
415 | u16 analog2GhzRev; | |
416 | }; | |
394cf0a1 | 417 | |
cbe61d8a | 418 | struct ath_hw { |
394cf0a1 | 419 | struct ath_softc *ah_sc; |
cbe61d8a | 420 | struct ath9k_hw_version hw_version; |
2660b81a S |
421 | struct ath9k_ops_config config; |
422 | struct ath9k_hw_capabilities caps; | |
d6bad496 | 423 | struct ath9k_regulatory regulatory; |
2660b81a S |
424 | struct ath9k_channel channels[38]; |
425 | struct ath9k_channel *curchan; | |
394cf0a1 | 426 | |
cbe61d8a S |
427 | union { |
428 | struct ar5416_eeprom_def def; | |
429 | struct ar5416_eeprom_4k map4k; | |
2660b81a | 430 | } eeprom; |
f74df6fb | 431 | const struct eeprom_ops *eep_ops; |
2660b81a | 432 | enum ath9k_eep_map eep_map; |
cbe61d8a S |
433 | |
434 | bool sw_mgmt_crypto; | |
2660b81a | 435 | bool is_pciexpress; |
cbe61d8a | 436 | u8 macaddr[ETH_ALEN]; |
2660b81a S |
437 | u16 tx_trig_level; |
438 | u16 rfsilent; | |
439 | u32 rfkill_gpio; | |
440 | u32 rfkill_polarity; | |
441 | u32 btactive_gpio; | |
442 | u32 wlanactive_gpio; | |
cbe61d8a | 443 | u32 ah_flags; |
394cf0a1 | 444 | |
2660b81a S |
445 | enum nl80211_iftype opmode; |
446 | enum ath9k_power_mode power_mode; | |
447 | enum ath9k_power_mode restore_mode; | |
f078f209 | 448 | |
cbe61d8a | 449 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
2660b81a S |
450 | struct ar5416Stats stats; |
451 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
452 | ||
453 | int16_t curchan_rad_index; | |
454 | u32 mask_reg; | |
455 | u32 txok_interrupt_mask; | |
456 | u32 txerr_interrupt_mask; | |
457 | u32 txdesc_interrupt_mask; | |
458 | u32 txeol_interrupt_mask; | |
459 | u32 txurn_interrupt_mask; | |
460 | bool chip_fullsleep; | |
461 | u32 atim_window; | |
462 | u16 antenna_switch_swap; | |
463 | enum ath9k_ant_setting diversity_control; | |
6a2b9e8c S |
464 | |
465 | /* Calibration */ | |
2660b81a S |
466 | enum hal_cal_types supp_cals; |
467 | struct hal_cal_list iq_caldata; | |
468 | struct hal_cal_list adcgain_caldata; | |
469 | struct hal_cal_list adcdc_calinitdata; | |
470 | struct hal_cal_list adcdc_caldata; | |
471 | struct hal_cal_list *cal_list; | |
472 | struct hal_cal_list *cal_list_last; | |
473 | struct hal_cal_list *cal_list_curr; | |
474 | #define totalPowerMeasI meas0.unsign | |
475 | #define totalPowerMeasQ meas1.unsign | |
476 | #define totalIqCorrMeas meas2.sign | |
477 | #define totalAdcIOddPhase meas0.unsign | |
478 | #define totalAdcIEvenPhase meas1.unsign | |
479 | #define totalAdcQOddPhase meas2.unsign | |
480 | #define totalAdcQEvenPhase meas3.unsign | |
481 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
482 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
483 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
484 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
485 | union { |
486 | u32 unsign[AR5416_MAX_CHAINS]; | |
487 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 488 | } meas0; |
f078f209 LR |
489 | union { |
490 | u32 unsign[AR5416_MAX_CHAINS]; | |
491 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 492 | } meas1; |
f078f209 LR |
493 | union { |
494 | u32 unsign[AR5416_MAX_CHAINS]; | |
495 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 496 | } meas2; |
f078f209 LR |
497 | union { |
498 | u32 unsign[AR5416_MAX_CHAINS]; | |
499 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
500 | } meas3; |
501 | u16 cal_samples; | |
6a2b9e8c | 502 | |
2660b81a S |
503 | u32 sta_id1_defaults; |
504 | u32 misc_mode; | |
f078f209 LR |
505 | enum { |
506 | AUTO_32KHZ, | |
507 | USE_32KHZ, | |
508 | DONT_USE_32KHZ, | |
2660b81a | 509 | } enable_32kHz_clock; |
6a2b9e8c S |
510 | |
511 | /* RF */ | |
2660b81a S |
512 | u32 *analogBank0Data; |
513 | u32 *analogBank1Data; | |
514 | u32 *analogBank2Data; | |
515 | u32 *analogBank3Data; | |
516 | u32 *analogBank6Data; | |
517 | u32 *analogBank6TPCData; | |
518 | u32 *analogBank7Data; | |
519 | u32 *addac5416_21; | |
520 | u32 *bank6Temp; | |
521 | ||
522 | int16_t txpower_indexoffset; | |
523 | u32 beacon_interval; | |
524 | u32 slottime; | |
525 | u32 acktimeout; | |
526 | u32 ctstimeout; | |
527 | u32 globaltxtimeout; | |
528 | u8 gbeacon_rate; | |
6a2b9e8c S |
529 | |
530 | /* ANI */ | |
2660b81a S |
531 | u32 proc_phyerr; |
532 | bool has_hw_phycounters; | |
533 | u32 aniperiod; | |
534 | struct ar5416AniState *curani; | |
535 | struct ar5416AniState ani[255]; | |
536 | int totalSizeDesired[5]; | |
537 | int coarse_high[5]; | |
538 | int coarse_low[5]; | |
539 | int firpwr[5]; | |
540 | enum ath9k_ani_cmd ani_function; | |
541 | ||
542 | u32 intr_txqs; | |
543 | bool intr_mitigation; | |
544 | enum ath9k_ht_extprotspacing extprotspacing; | |
545 | u8 txchainmask; | |
546 | u8 rxchainmask; | |
547 | ||
8bd1d07f SB |
548 | u32 originalGain[22]; |
549 | int initPDADC; | |
550 | int PDADCdelta; | |
551 | ||
2660b81a S |
552 | struct ar5416IniArray iniModes; |
553 | struct ar5416IniArray iniCommon; | |
554 | struct ar5416IniArray iniBank0; | |
555 | struct ar5416IniArray iniBB_RfGain; | |
556 | struct ar5416IniArray iniBank1; | |
557 | struct ar5416IniArray iniBank2; | |
558 | struct ar5416IniArray iniBank3; | |
559 | struct ar5416IniArray iniBank6; | |
560 | struct ar5416IniArray iniBank6TPC; | |
561 | struct ar5416IniArray iniBank7; | |
562 | struct ar5416IniArray iniAddac; | |
563 | struct ar5416IniArray iniPcieSerdes; | |
564 | struct ar5416IniArray iniModesAdditional; | |
565 | struct ar5416IniArray iniModesRxGain; | |
566 | struct ar5416IniArray iniModesTxGain; | |
f078f209 | 567 | }; |
f078f209 | 568 | |
394cf0a1 S |
569 | /* Attach, Detach, Reset */ |
570 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); | |
cbe61d8a S |
571 | void ath9k_hw_detach(struct ath_hw *ah); |
572 | struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error); | |
573 | void ath9k_hw_rfdetach(struct ath_hw *ah); | |
574 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |
394cf0a1 | 575 | bool bChannelChange); |
cbe61d8a S |
576 | bool ath9k_hw_fill_cap_info(struct ath_hw *ah); |
577 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, | |
394cf0a1 | 578 | u32 capability, u32 *result); |
cbe61d8a | 579 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 S |
580 | u32 capability, u32 setting, int *status); |
581 | ||
582 | /* Key Cache Management */ | |
cbe61d8a S |
583 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
584 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); | |
585 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, | |
394cf0a1 | 586 | const struct ath9k_keyval *k, |
e0caf9ea | 587 | const u8 *mac); |
cbe61d8a | 588 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); |
394cf0a1 S |
589 | |
590 | /* GPIO / RFKILL / Antennae */ | |
cbe61d8a S |
591 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
592 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
593 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 594 | u32 ah_signal_type); |
cbe61d8a | 595 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
394cf0a1 | 596 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
cbe61d8a | 597 | void ath9k_enable_rfkill(struct ath_hw *ah); |
f078f209 | 598 | #endif |
cbe61d8a S |
599 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
600 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
601 | bool ath9k_hw_setantennaswitch(struct ath_hw *ah, | |
394cf0a1 S |
602 | enum ath9k_ant_setting settings, |
603 | struct ath9k_channel *chan, | |
604 | u8 *tx_chainmask, u8 *rx_chainmask, | |
605 | u8 *antenna_cfgd); | |
606 | ||
607 | /* General Operation */ | |
0caa7b14 | 608 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
394cf0a1 | 609 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
cbe61d8a S |
610 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
611 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, | |
394cf0a1 | 612 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 613 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
614 | struct ath9k_channel *chan, |
615 | struct chan_centers *centers); | |
cbe61d8a S |
616 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
617 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
618 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
619 | bool ath9k_hw_disable(struct ath_hw *ah); | |
620 | bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); | |
621 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); | |
622 | void ath9k_hw_setopmode(struct ath_hw *ah); | |
623 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
ba52da58 S |
624 | void ath9k_hw_setbssidmask(struct ath_softc *sc); |
625 | void ath9k_hw_write_associd(struct ath_softc *sc); | |
cbe61d8a S |
626 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
627 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
628 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
629 | bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); | |
630 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); | |
631 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); | |
632 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); | |
633 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 634 | const struct ath9k_beacon_state *bs); |
cbe61d8a | 635 | bool ath9k_hw_setpower(struct ath_hw *ah, |
394cf0a1 | 636 | enum ath9k_power_mode mode); |
cbe61d8a | 637 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore); |
394cf0a1 S |
638 | |
639 | /* Interrupt Handling */ | |
cbe61d8a S |
640 | bool ath9k_hw_intrpend(struct ath_hw *ah); |
641 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked); | |
642 | enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah); | |
643 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); | |
394cf0a1 | 644 | |
cbe61d8a | 645 | void ath9k_hw_btcoex_enable(struct ath_hw *ah); |
f078f209 LR |
646 | |
647 | #endif |