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ath9k: Change return value of ath9k_hw_fill_cap_info
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath9k / hw.h
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f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
28#include "regd.h"
29#include "reg.h"
30#include "phy.h"
31
32#define ATHEROS_VENDOR_ID 0x168c
33#define AR5416_DEVID_PCI 0x0023
34#define AR5416_DEVID_PCIE 0x0024
35#define AR9160_DEVID_PCI 0x0027
36#define AR9280_DEVID_PCI 0x0029
37#define AR9280_DEVID_PCIE 0x002a
38#define AR9285_DEVID_PCIE 0x002b
39#define AR5416_AR9100_DEVID 0x000b
40#define AR_SUBVENDOR_ID_NOG 0x0e11
41#define AR_SUBVENDOR_ID_NEW_A 0x7065
42#define AR5416_MAGIC 0x19641014
43
44/* Register read/write primitives */
2d6a5e95
DM		 45#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
46#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
394cf0a1
S		 47
48#define SM(_v, _f) (((_v) << _f##_S) & _f)
49#define MS(_v, _f) (((_v) & _f) >> _f##_S)
50#define REG_RMW(_a, _r, _set, _clr) \
51 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
52#define REG_RMW_FIELD(_a, _r, _f, _v) \
53 REG_WRITE(_a, _r, \
54 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
55#define REG_SET_BIT(_a, _r, _f) \
56 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
57#define REG_CLR_BIT(_a, _r, _f) \
58 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 59
394cf0a1
S		 60#define DO_DELAY(x) do { \
61 if ((++(x) % 64) == 0) \
62 udelay(1); \
63 } while (0)
f078f209 64
394cf0a1
S		 65#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
66 int r; \
67 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
68 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
69 INI_RA((iniarray), r, (column))); \
70 DO_DELAY(regWr); \
71 } \
72 } while (0)
f078f209 73
394cf0a1
S		 74#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
75#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
76#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
77#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
78#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
79#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 80
394cf0a1
S		 81#define AR_GPIOD_MASK 0x00001FFF
82#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 83
394cf0a1
S		 84#define BASE_ACTIVATE_DELAY 100
85#define RTC_PLL_SETTLE_DELAY 1000
86#define COEF_SCALE_S 24
87#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 88
394cf0a1
S		 89#define ATH9K_ANTENNA0_CHAINMASK 0x1
90#define ATH9K_ANTENNA1_CHAINMASK 0x2
91
92#define ATH9K_NUM_DMA_DEBUG_REGS 8
93#define ATH9K_NUM_QUEUES 10
94
95#define MAX_RATE_POWER 63
0caa7b14 96#define AH_WAIT_TIMEOUT 100000 /* (us) */
394cf0a1
S		 97#define AH_TIME_QUANTUM 10
98#define AR_KEYTABLE_SIZE 128
99#define POWER_UP_TIME 200000
100#define SPUR_RSSI_THRESH 40
101
102#define CAB_TIMEOUT_VAL 10
103#define BEACON_TIMEOUT_VAL 10
104#define MIN_BEACON_TIMEOUT_VAL 1
105#define SLEEP_SLOP 3
106
107#define INIT_CONFIG_STATUS 0x00000000
108#define INIT_RSSI_THR 0x00000700
109#define INIT_BCON_CNTRL_REG 0x00000000
110
111#define TU_TO_USEC(_tu) ((_tu) << 10)
112
113enum wireless_mode {
114 ATH9K_MODE_11A = 0,
115 ATH9K_MODE_11B = 2,
116 ATH9K_MODE_11G = 3,
117 ATH9K_MODE_11NA_HT20 = 6,
118 ATH9K_MODE_11NG_HT20 = 7,
119 ATH9K_MODE_11NA_HT40PLUS = 8,
120 ATH9K_MODE_11NA_HT40MINUS = 9,
121 ATH9K_MODE_11NG_HT40PLUS = 10,
122 ATH9K_MODE_11NG_HT40MINUS = 11,
123 ATH9K_MODE_MAX
124};
f078f209 125
394cf0a1 126enum ath9k_hw_caps {
bdbdf46d
S		 127 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
128 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
129 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
130 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
131 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
132 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
133 ATH9K_HW_CAP_VEOL = BIT(6),
134 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
135 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
136 ATH9K_HW_CAP_HT = BIT(9),
137 ATH9K_HW_CAP_GTT = BIT(10),
138 ATH9K_HW_CAP_FASTCC = BIT(11),
139 ATH9K_HW_CAP_RFSILENT = BIT(12),
140 ATH9K_HW_CAP_CST = BIT(13),
141 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
142 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
143 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
144 ATH9K_HW_CAP_BT_COEX = BIT(17)
394cf0a1 145};
f078f209 146
394cf0a1
S		 147enum ath9k_capability_type {
148 ATH9K_CAP_CIPHER = 0,
149 ATH9K_CAP_TKIP_MIC,
150 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 151 ATH9K_CAP_DIVERSITY,
152 ATH9K_CAP_TXPOW,
394cf0a1 153 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 154 ATH9K_CAP_DS
394cf0a1 155};
f078f209 156
394cf0a1
S		 157struct ath9k_hw_capabilities {
158 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
159 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
160 u16 total_queues;
161 u16 keycache_size;
162 u16 low_5ghz_chan, high_5ghz_chan;
163 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 164 u16 rts_aggr_limit;
165 u8 tx_chainmask;
166 u8 rx_chainmask;
167 u16 tx_triglevel_max;
168 u16 reg_cap;
169 u8 num_gpio_pins;
170 u8 num_antcfg_2ghz;
171 u8 num_antcfg_5ghz;
172};
f078f209 173
394cf0a1
S		 174struct ath9k_ops_config {
175 int dma_beacon_response_time;
176 int sw_beacon_response_time;
177 int additional_swba_backoff;
178 int ack_6mb;
179 int cwm_ignore_extcca;
180 u8 pcie_powersave_enable;
394cf0a1
S		 181 u8 pcie_clock_req;
182 u32 pcie_waen;
394cf0a1
S		 183 u8 analog_shiftreg;
184 u8 ht_enable;
185 u32 ofdm_trig_low;
186 u32 ofdm_trig_high;
187 u32 cck_trig_high;
188 u32 cck_trig_low;
189 u32 enable_ani;
394cf0a1
S		 190 u16 diversity_control;
191 u16 antenna_switch_swap;
192 int serialize_regmode;
193 int intr_mitigation;
194#define SPUR_DISABLE 0
195#define SPUR_ENABLE_IOCTL 1
196#define SPUR_ENABLE_EEPROM 2
197#define AR_EEPROM_MODAL_SPURS 5
198#define AR_SPUR_5413_1 1640
199#define AR_SPUR_5413_2 1200
200#define AR_NO_SPUR 0x8000
201#define AR_BASE_FREQ_2GHZ 2300
202#define AR_BASE_FREQ_5GHZ 4900
203#define AR_SPUR_FEEQ_BOUND_HT40 19
204#define AR_SPUR_FEEQ_BOUND_HT20 10
205 int spurmode;
206 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
207};
f078f209 208
394cf0a1
S		 209enum ath9k_int {
210 ATH9K_INT_RX = 0x00000001,
211 ATH9K_INT_RXDESC = 0x00000002,
212 ATH9K_INT_RXNOFRM = 0x00000008,
213 ATH9K_INT_RXEOL = 0x00000010,
214 ATH9K_INT_RXORN = 0x00000020,
215 ATH9K_INT_TX = 0x00000040,
216 ATH9K_INT_TXDESC = 0x00000080,
217 ATH9K_INT_TIM_TIMER = 0x00000100,
218 ATH9K_INT_TXURN = 0x00000800,
219 ATH9K_INT_MIB = 0x00001000,
220 ATH9K_INT_RXPHY = 0x00004000,
221 ATH9K_INT_RXKCM = 0x00008000,
222 ATH9K_INT_SWBA = 0x00010000,
223 ATH9K_INT_BMISS = 0x00040000,
224 ATH9K_INT_BNR = 0x00100000,
225 ATH9K_INT_TIM = 0x00200000,
226 ATH9K_INT_DTIM = 0x00400000,
227 ATH9K_INT_DTIMSYNC = 0x00800000,
228 ATH9K_INT_GPIO = 0x01000000,
229 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 230 ATH9K_INT_TSFOOR = 0x04000000,
394cf0a1
S		 231 ATH9K_INT_CST = 0x10000000,
232 ATH9K_INT_GTT = 0x20000000,
233 ATH9K_INT_FATAL = 0x40000000,
234 ATH9K_INT_GLOBAL = 0x80000000,
235 ATH9K_INT_BMISC = ATH9K_INT_TIM |
236 ATH9K_INT_DTIM |
237 ATH9K_INT_DTIMSYNC |
4af9cf4f 238 ATH9K_INT_TSFOOR |
394cf0a1
S		 239 ATH9K_INT_CABEND,
240 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
241 ATH9K_INT_RXDESC |
242 ATH9K_INT_RXEOL |
243 ATH9K_INT_RXORN |
244 ATH9K_INT_TXURN |
245 ATH9K_INT_TXDESC |
246 ATH9K_INT_MIB |
247 ATH9K_INT_RXPHY |
248 ATH9K_INT_RXKCM |
249 ATH9K_INT_SWBA |
250 ATH9K_INT_BMISS |
251 ATH9K_INT_GPIO,
252 ATH9K_INT_NOCARD = 0xffffffff
253};
f078f209 254
394cf0a1
S		 255#define CHANNEL_CW_INT 0x00002
256#define CHANNEL_CCK 0x00020
257#define CHANNEL_OFDM 0x00040
258#define CHANNEL_2GHZ 0x00080
259#define CHANNEL_5GHZ 0x00100
260#define CHANNEL_PASSIVE 0x00200
261#define CHANNEL_DYN 0x00400
262#define CHANNEL_HALF 0x04000
263#define CHANNEL_QUARTER 0x08000
264#define CHANNEL_HT20 0x10000
265#define CHANNEL_HT40PLUS 0x20000
266#define CHANNEL_HT40MINUS 0x40000
267
268#define CHANNEL_INTERFERENCE 0x01
269#define CHANNEL_DFS 0x02
270#define CHANNEL_4MS_LIMIT 0x04
271#define CHANNEL_DFS_CLEAR 0x08
272#define CHANNEL_DISALLOW_ADHOC 0x10
273#define CHANNEL_PER_11D_ADHOC 0x20
274
275#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
276#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
277#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
278#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
279#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
280#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
281#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
282#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
283#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
284#define CHANNEL_ALL \
285 (CHANNEL_OFDM| \
286 CHANNEL_CCK| \
287 CHANNEL_2GHZ | \
288 CHANNEL_5GHZ | \
289 CHANNEL_HT20 | \
290 CHANNEL_HT40PLUS | \
291 CHANNEL_HT40MINUS)
292
293struct ath9k_channel {
294 struct ieee80211_channel *chan;
295 u16 channel;
296 u32 channelFlags;
297 u32 chanmode;
298 int32_t CalValid;
299 bool oneTimeCalsDone;
300 int8_t iCoff;
301 int8_t qCoff;
302 int16_t rawNoiseFloor;
303};
f078f209 304
394cf0a1
S		 305#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
306 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
307 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
308 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
309#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
310 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
311 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
312 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
313#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
314#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
315#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
316#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
317#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
318#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
319#define IS_CHAN_A_5MHZ_SPACED(_c) \
320 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
321 (((_c)->channel % 20) != 0) && \
322 (((_c)->channel % 10) != 0))
323
324/* These macros check chanmode and not channelFlags */
325#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
326#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
327 ((_c)->chanmode == CHANNEL_G_HT20))
328#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
329 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
330 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
331 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
332#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
333
334enum ath9k_power_mode {
335 ATH9K_PM_AWAKE = 0,
336 ATH9K_PM_FULL_SLEEP,
337 ATH9K_PM_NETWORK_SLEEP,
338 ATH9K_PM_UNDEFINED
339};
f078f209 340
394cf0a1
S		 341enum ath9k_ant_setting {
342 ATH9K_ANT_VARIABLE = 0,
343 ATH9K_ANT_FIXED_A,
344 ATH9K_ANT_FIXED_B
345};
f078f209 346
394cf0a1
S		 347enum ath9k_tp_scale {
348 ATH9K_TP_SCALE_MAX = 0,
349 ATH9K_TP_SCALE_50,
350 ATH9K_TP_SCALE_25,
351 ATH9K_TP_SCALE_12,
352 ATH9K_TP_SCALE_MIN
353};
f078f209 354
394cf0a1
S		 355enum ser_reg_mode {
356 SER_REG_MODE_OFF = 0,
357 SER_REG_MODE_ON = 1,
358 SER_REG_MODE_AUTO = 2,
359};
f078f209 360
394cf0a1
S		 361struct ath9k_beacon_state {
362 u32 bs_nexttbtt;
363 u32 bs_nextdtim;
364 u32 bs_intval;
365#define ATH9K_BEACON_PERIOD 0x0000ffff
366#define ATH9K_BEACON_ENA 0x00800000
367#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 368#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 369 u32 bs_dtimperiod;
370 u16 bs_cfpperiod;
371 u16 bs_cfpmaxduration;
372 u32 bs_cfpnext;
373 u16 bs_timoffset;
374 u16 bs_bmissthreshold;
375 u32 bs_sleepduration;
4af9cf4f 376 u32 bs_tsfoor_threshold;
394cf0a1 377};
f078f209 378
394cf0a1
S		 379struct chan_centers {
380 u16 synth_center;
381 u16 ctl_center;
382 u16 ext_center;
383};
f078f209 384
394cf0a1
S		 385enum {
386 ATH9K_RESET_POWER_ON,
387 ATH9K_RESET_WARM,
388 ATH9K_RESET_COLD,
389};
f078f209 390
d535a42a
S		 391struct ath9k_hw_version {
392 u32 magic;
393 u16 devid;
394 u16 subvendorid;
395 u32 macVersion;
396 u16 macRev;
397 u16 phyRev;
398 u16 analog5GhzRev;
399 u16 analog2GhzRev;
400};
394cf0a1 401
cbe61d8a 402struct ath_hw {
394cf0a1 403 struct ath_softc *ah_sc;
cbe61d8a 404 struct ath9k_hw_version hw_version;
2660b81a
S		 405 struct ath9k_ops_config config;
406 struct ath9k_hw_capabilities caps;
d6bad496 407 struct ath9k_regulatory regulatory;
2660b81a
S		 408 struct ath9k_channel channels[38];
409 struct ath9k_channel *curchan;
394cf0a1 410
cbe61d8a
S		 411 union {
412 struct ar5416_eeprom_def def;
413 struct ar5416_eeprom_4k map4k;
2660b81a 414 } eeprom;
f74df6fb 415 const struct eeprom_ops *eep_ops;
2660b81a 416 enum ath9k_eep_map eep_map;
cbe61d8a
S		 417
418 bool sw_mgmt_crypto;
2660b81a 419 bool is_pciexpress;
cbe61d8a 420 u8 macaddr[ETH_ALEN];
2660b81a
S		 421 u16 tx_trig_level;
422 u16 rfsilent;
423 u32 rfkill_gpio;
424 u32 rfkill_polarity;
425 u32 btactive_gpio;
426 u32 wlanactive_gpio;
cbe61d8a 427 u32 ah_flags;
394cf0a1 428
2660b81a
S		 429 enum nl80211_iftype opmode;
430 enum ath9k_power_mode power_mode;
431 enum ath9k_power_mode restore_mode;
f078f209 432
cbe61d8a 433 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
2660b81a
S		 434 struct ar5416Stats stats;
435 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
436
437 int16_t curchan_rad_index;
438 u32 mask_reg;
439 u32 txok_interrupt_mask;
440 u32 txerr_interrupt_mask;
441 u32 txdesc_interrupt_mask;
442 u32 txeol_interrupt_mask;
443 u32 txurn_interrupt_mask;
444 bool chip_fullsleep;
445 u32 atim_window;
446 u16 antenna_switch_swap;
447 enum ath9k_ant_setting diversity_control;
6a2b9e8c
S		 448
449 /* Calibration */
2660b81a
S		 450 enum hal_cal_types supp_cals;
451 struct hal_cal_list iq_caldata;
452 struct hal_cal_list adcgain_caldata;
453 struct hal_cal_list adcdc_calinitdata;
454 struct hal_cal_list adcdc_caldata;
455 struct hal_cal_list *cal_list;
456 struct hal_cal_list *cal_list_last;
457 struct hal_cal_list *cal_list_curr;
458#define totalPowerMeasI meas0.unsign
459#define totalPowerMeasQ meas1.unsign
460#define totalIqCorrMeas meas2.sign
461#define totalAdcIOddPhase meas0.unsign
462#define totalAdcIEvenPhase meas1.unsign
463#define totalAdcQOddPhase meas2.unsign
464#define totalAdcQEvenPhase meas3.unsign
465#define totalAdcDcOffsetIOddPhase meas0.sign
466#define totalAdcDcOffsetIEvenPhase meas1.sign
467#define totalAdcDcOffsetQOddPhase meas2.sign
468#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 469 union {
470 u32 unsign[AR5416_MAX_CHAINS];
471 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 472 } meas0;
f078f209
LR		 473 union {
474 u32 unsign[AR5416_MAX_CHAINS];
475 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 476 } meas1;
f078f209
LR		 477 union {
478 u32 unsign[AR5416_MAX_CHAINS];
479 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 480 } meas2;
f078f209
LR		 481 union {
482 u32 unsign[AR5416_MAX_CHAINS];
483 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 484 } meas3;
485 u16 cal_samples;
6a2b9e8c 486
2660b81a
S		 487 u32 sta_id1_defaults;
488 u32 misc_mode;
f078f209
LR		 489 enum {
490 AUTO_32KHZ,
491 USE_32KHZ,
492 DONT_USE_32KHZ,
2660b81a 493 } enable_32kHz_clock;
6a2b9e8c
S		 494
495 /* RF */
2660b81a
S		 496 u32 *analogBank0Data;
497 u32 *analogBank1Data;
498 u32 *analogBank2Data;
499 u32 *analogBank3Data;
500 u32 *analogBank6Data;
501 u32 *analogBank6TPCData;
502 u32 *analogBank7Data;
503 u32 *addac5416_21;
504 u32 *bank6Temp;
505
506 int16_t txpower_indexoffset;
507 u32 beacon_interval;
508 u32 slottime;
509 u32 acktimeout;
510 u32 ctstimeout;
511 u32 globaltxtimeout;
512 u8 gbeacon_rate;
6a2b9e8c
S		 513
514 /* ANI */
2660b81a
S		 515 u32 proc_phyerr;
516 bool has_hw_phycounters;
517 u32 aniperiod;
518 struct ar5416AniState *curani;
519 struct ar5416AniState ani[255];
520 int totalSizeDesired[5];
521 int coarse_high[5];
522 int coarse_low[5];
523 int firpwr[5];
524 enum ath9k_ani_cmd ani_function;
525
526 u32 intr_txqs;
527 bool intr_mitigation;
528 enum ath9k_ht_extprotspacing extprotspacing;
529 u8 txchainmask;
530 u8 rxchainmask;
531
8bd1d07f
SB		 532 u32 originalGain[22];
533 int initPDADC;
534 int PDADCdelta;
535
2660b81a
S		 536 struct ar5416IniArray iniModes;
537 struct ar5416IniArray iniCommon;
538 struct ar5416IniArray iniBank0;
539 struct ar5416IniArray iniBB_RfGain;
540 struct ar5416IniArray iniBank1;
541 struct ar5416IniArray iniBank2;
542 struct ar5416IniArray iniBank3;
543 struct ar5416IniArray iniBank6;
544 struct ar5416IniArray iniBank6TPC;
545 struct ar5416IniArray iniBank7;
546 struct ar5416IniArray iniAddac;
547 struct ar5416IniArray iniPcieSerdes;
548 struct ar5416IniArray iniModesAdditional;
549 struct ar5416IniArray iniModesRxGain;
550 struct ar5416IniArray iniModesTxGain;
f078f209 551};
f078f209 552
394cf0a1
S		 553/* Attach, Detach, Reset */
554const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a
S		 555void ath9k_hw_detach(struct ath_hw *ah);
556struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error);
557void ath9k_hw_rfdetach(struct ath_hw *ah);
558int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 559 bool bChannelChange);
eef7a574 560void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 561bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 562 u32 capability, u32 *result);
cbe61d8a 563bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 564 u32 capability, u32 setting, int *status);
565
566/* Key Cache Management */
cbe61d8a
S		 567bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
568bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
569bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 570 const struct ath9k_keyval *k,
e0caf9ea 571 const u8 *mac);
cbe61d8a 572bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 573
574/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 575void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
576u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
577void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 578 u32 ah_signal_type);
cbe61d8a 579void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
394cf0a1 580#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
cbe61d8a 581void ath9k_enable_rfkill(struct ath_hw *ah);
f078f209 582#endif
cbe61d8a
S		 583u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
584void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
585bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 586 enum ath9k_ant_setting settings,
587 struct ath9k_channel *chan,
588 u8 *tx_chainmask, u8 *rx_chainmask,
589 u8 *antenna_cfgd);
590
591/* General Operation */
0caa7b14 592bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 593u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a
S		 594bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
595u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates,
394cf0a1 596 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 597void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 598 struct ath9k_channel *chan,
599 struct chan_centers *centers);
cbe61d8a
S		 600u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
601void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
602bool ath9k_hw_phy_disable(struct ath_hw *ah);
603bool ath9k_hw_disable(struct ath_hw *ah);
604bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
605void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
606void ath9k_hw_setopmode(struct ath_hw *ah);
607void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
ba52da58
S		 608void ath9k_hw_setbssidmask(struct ath_softc *sc);
609void ath9k_hw_write_associd(struct ath_softc *sc);
cbe61d8a
S		 610u64 ath9k_hw_gettsf64(struct ath_hw *ah);
611void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
612void ath9k_hw_reset_tsf(struct ath_hw *ah);
613bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
614bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
615void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
616void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
617void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 618 const struct ath9k_beacon_state *bs);
cbe61d8a 619bool ath9k_hw_setpower(struct ath_hw *ah,
394cf0a1 620 enum ath9k_power_mode mode);
cbe61d8a 621void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
394cf0a1
S		 622
623/* Interrupt Handling */
cbe61d8a
S		 624bool ath9k_hw_intrpend(struct ath_hw *ah);
625bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
626enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah);
627enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 628
cbe61d8a 629void ath9k_hw_btcoex_enable(struct ath_hw *ah);
f078f209
LR		 630
631#endif
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