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Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | /* | |
20 | * Setup and link descriptors. | |
21 | * | |
22 | * 11N: we can no longer afford to self link the last descriptor. | |
23 | * MAC acknowledges BA status as long as it copies frames to host | |
24 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
25 | * to a sender if last desc is self-linked. | |
f078f209 | 26 | */ |
f078f209 LR |
27 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
28 | { | |
29 | struct ath_hal *ah = sc->sc_ah; | |
30 | struct ath_desc *ds; | |
31 | struct sk_buff *skb; | |
32 | ||
33 | ATH_RXBUF_RESET(bf); | |
34 | ||
35 | ds = bf->bf_desc; | |
be0418ad | 36 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
37 | ds->ds_data = bf->bf_buf_addr; |
38 | ||
be0418ad | 39 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
40 | skb = bf->bf_mpdu; |
41 | ASSERT(skb != NULL); | |
42 | ds->ds_vdata = skb->data; | |
43 | ||
b77f483f | 44 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
45 | * how much data it can DMA to us and that we are prepared |
46 | * to process */ | |
b77f483f S |
47 | ath9k_hw_setuprxdesc(ah, ds, |
48 | sc->rx.bufsize, | |
f078f209 LR |
49 | 0); |
50 | ||
b77f483f | 51 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
52 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
53 | else | |
b77f483f | 54 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 55 | |
b77f483f | 56 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
57 | ath9k_hw_rxena(ah); |
58 | } | |
59 | ||
ff37e337 S |
60 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
61 | { | |
62 | /* XXX block beacon interrupts */ | |
63 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
64 | sc->rx.defant = antenna; |
65 | sc->rx.rxotherant = 0; | |
ff37e337 S |
66 | } |
67 | ||
68 | /* | |
69 | * Extend 15-bit time stamp from rx descriptor to | |
70 | * a full 64-bit TSF using the current h/w TSF. | |
71 | */ | |
72 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
73 | { | |
74 | u64 tsf; | |
75 | ||
76 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
77 | if ((tsf & 0x7fff) < rstamp) | |
78 | tsf -= 0x8000; | |
79 | return (tsf & ~0x7fff) | rstamp; | |
80 | } | |
81 | ||
be0418ad | 82 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) |
f078f209 LR |
83 | { |
84 | struct sk_buff *skb; | |
85 | u32 off; | |
86 | ||
87 | /* | |
88 | * Cache-line-align. This is important (for the | |
89 | * 5210 at least) as not doing so causes bogus data | |
90 | * in rx'd frames. | |
91 | */ | |
92 | ||
b4b6cda2 LR |
93 | /* Note: the kernel can allocate a value greater than |
94 | * what we ask it to give us. We really only need 4 KB as that | |
95 | * is this hardware supports and in fact we need at least 3849 | |
96 | * as that is the MAX AMSDU size this hardware supports. | |
97 | * Unfortunately this means we may get 8 KB here from the | |
98 | * kernel... and that is actually what is observed on some | |
99 | * systems :( */ | |
17d7904d | 100 | skb = dev_alloc_skb(len + sc->cachelsz - 1); |
f078f209 | 101 | if (skb != NULL) { |
17d7904d | 102 | off = ((unsigned long) skb->data) % sc->cachelsz; |
f078f209 | 103 | if (off != 0) |
17d7904d | 104 | skb_reserve(skb, sc->cachelsz - off); |
f078f209 LR |
105 | } else { |
106 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 107 | "skbuff alloc of size %u failed\n", len); |
f078f209 LR |
108 | return NULL; |
109 | } | |
110 | ||
111 | return skb; | |
112 | } | |
113 | ||
f078f209 | 114 | /* |
be0418ad S |
115 | * For Decrypt or Demic errors, we only mark packet status here and always push |
116 | * up the frame up to let mac80211 handle the actual error case, be it no | |
117 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 118 | */ |
be0418ad S |
119 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
120 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
121 | struct ath_softc *sc) | |
f078f209 | 122 | { |
be0418ad | 123 | struct ieee80211_hdr *hdr; |
be0418ad S |
124 | u8 ratecode; |
125 | __le16 fc; | |
126 | ||
127 | hdr = (struct ieee80211_hdr *)skb->data; | |
128 | fc = hdr->frame_control; | |
129 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
130 | ||
131 | if (ds->ds_rxstat.rs_more) { | |
132 | /* | |
133 | * Frame spans multiple descriptors; this cannot happen yet | |
134 | * as we don't support jumbograms. If not in monitor mode, | |
135 | * discard the frame. Enable this if you want to see | |
136 | * error frames in Monitor mode. | |
137 | */ | |
d97809db | 138 | if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) |
be0418ad S |
139 | goto rx_next; |
140 | } else if (ds->ds_rxstat.rs_status != 0) { | |
141 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
142 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
143 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
144 | goto rx_next; | |
f078f209 | 145 | |
be0418ad S |
146 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
147 | *decrypt_error = true; | |
148 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
149 | if (ieee80211_is_ctl(fc)) | |
150 | /* | |
151 | * Sometimes, we get invalid | |
152 | * MIC failures on valid control frames. | |
153 | * Remove these mic errors. | |
154 | */ | |
155 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
156 | else | |
157 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
158 | } | |
159 | /* | |
160 | * Reject error frames with the exception of | |
161 | * decryption and MIC failures. For monitor mode, | |
162 | * we also ignore the CRC error. | |
163 | */ | |
d97809db | 164 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { |
be0418ad S |
165 | if (ds->ds_rxstat.rs_status & |
166 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
167 | ATH9K_RXERR_CRC)) | |
168 | goto rx_next; | |
169 | } else { | |
170 | if (ds->ds_rxstat.rs_status & | |
171 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
172 | goto rx_next; | |
173 | } | |
174 | } | |
f078f209 LR |
175 | } |
176 | ||
be0418ad | 177 | ratecode = ds->ds_rxstat.rs_rate; |
be0418ad | 178 | |
be0418ad | 179 | if (ratecode & 0x80) { |
baad1d92 JM |
180 | /* HT rate */ |
181 | rx_status->flag |= RX_FLAG_HT; | |
be0418ad | 182 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) |
baad1d92 | 183 | rx_status->flag |= RX_FLAG_40MHZ; |
be0418ad | 184 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) |
baad1d92 JM |
185 | rx_status->flag |= RX_FLAG_SHORT_GI; |
186 | rx_status->rate_idx = ratecode & 0x7f; | |
187 | } else { | |
188 | int i = 0, cur_band, n_rates; | |
189 | struct ieee80211_hw *hw = sc->hw; | |
190 | ||
191 | cur_band = hw->conf.channel->band; | |
192 | n_rates = sc->sbands[cur_band].n_bitrates; | |
193 | ||
194 | for (i = 0; i < n_rates; i++) { | |
195 | if (sc->sbands[cur_band].bitrates[i].hw_value == | |
196 | ratecode) { | |
197 | rx_status->rate_idx = i; | |
198 | break; | |
199 | } | |
200 | ||
201 | if (sc->sbands[cur_band].bitrates[i].hw_value_short == | |
202 | ratecode) { | |
203 | rx_status->rate_idx = i; | |
204 | rx_status->flag |= RX_FLAG_SHORTPRE; | |
205 | break; | |
206 | } | |
207 | } | |
be0418ad S |
208 | } |
209 | ||
210 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
211 | rx_status->band = sc->hw->conf.channel->band; | |
212 | rx_status->freq = sc->hw->conf.channel->center_freq; | |
17d7904d | 213 | rx_status->noise = sc->ani.noise_floor; |
be0418ad | 214 | rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; |
be0418ad S |
215 | rx_status->antenna = ds->ds_rxstat.rs_antenna; |
216 | ||
217 | /* at 45 you will be able to use MCS 15 reliably. A more elaborate | |
218 | * scheme can be used here but it requires tables of SNR/throughput for | |
219 | * each possible mode used. */ | |
220 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
221 | ||
222 | /* rssi can be more than 45 though, anything above that | |
223 | * should be considered at 100% */ | |
224 | if (rx_status->qual > 100) | |
225 | rx_status->qual = 100; | |
226 | ||
227 | rx_status->flag |= RX_FLAG_TSFT; | |
228 | ||
229 | return 1; | |
230 | rx_next: | |
231 | return 0; | |
f078f209 LR |
232 | } |
233 | ||
234 | static void ath_opmode_init(struct ath_softc *sc) | |
235 | { | |
236 | struct ath_hal *ah = sc->sc_ah; | |
237 | u32 rfilt, mfilt[2]; | |
238 | ||
239 | /* configure rx filter */ | |
240 | rfilt = ath_calcrxfilter(sc); | |
241 | ath9k_hw_setrxfilter(ah, rfilt); | |
242 | ||
243 | /* configure bssid mask */ | |
60b67f51 | 244 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
17d7904d | 245 | ath9k_hw_setbssidmask(ah, sc->bssidmask); |
f078f209 LR |
246 | |
247 | /* configure operational mode */ | |
248 | ath9k_hw_setopmode(ah); | |
249 | ||
250 | /* Handle any link-level address change. */ | |
17d7904d | 251 | ath9k_hw_setmac(ah, sc->macaddr); |
f078f209 LR |
252 | |
253 | /* calculate and install multicast filter */ | |
254 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 255 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
256 | } |
257 | ||
258 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
259 | { | |
260 | struct sk_buff *skb; | |
261 | struct ath_buf *bf; | |
262 | int error = 0; | |
263 | ||
264 | do { | |
b77f483f | 265 | spin_lock_init(&sc->rx.rxflushlock); |
98deeea0 | 266 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 267 | spin_lock_init(&sc->rx.rxbuflock); |
f078f209 | 268 | |
b77f483f | 269 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
17d7904d | 270 | min(sc->cachelsz, |
f078f209 LR |
271 | (u16)64)); |
272 | ||
04bd4638 | 273 | DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
17d7904d | 274 | sc->cachelsz, sc->rx.bufsize); |
f078f209 LR |
275 | |
276 | /* Initialize rx descriptors */ | |
277 | ||
b77f483f | 278 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
f078f209 LR |
279 | "rx", nbufs, 1); |
280 | if (error != 0) { | |
281 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 282 | "failed to allocate rx descriptors: %d\n", error); |
f078f209 LR |
283 | break; |
284 | } | |
285 | ||
b77f483f S |
286 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
287 | skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); | |
f078f209 LR |
288 | if (skb == NULL) { |
289 | error = -ENOMEM; | |
290 | break; | |
291 | } | |
292 | ||
293 | bf->bf_mpdu = skb; | |
7da3c55c | 294 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
b77f483f | 295 | sc->rx.bufsize, |
7da3c55c GJ |
296 | DMA_FROM_DEVICE); |
297 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
298 | bf->bf_buf_addr))) { |
299 | dev_kfree_skb_any(skb); | |
300 | bf->bf_mpdu = NULL; | |
301 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 302 | "dma_mapping_error() on RX init\n"); |
f8316df1 LR |
303 | error = -ENOMEM; |
304 | break; | |
305 | } | |
927e70e9 | 306 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 | 307 | } |
b77f483f | 308 | sc->rx.rxlink = NULL; |
f078f209 LR |
309 | |
310 | } while (0); | |
311 | ||
312 | if (error) | |
313 | ath_rx_cleanup(sc); | |
314 | ||
315 | return error; | |
316 | } | |
317 | ||
f078f209 LR |
318 | void ath_rx_cleanup(struct ath_softc *sc) |
319 | { | |
320 | struct sk_buff *skb; | |
321 | struct ath_buf *bf; | |
322 | ||
b77f483f | 323 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 LR |
324 | skb = bf->bf_mpdu; |
325 | if (skb) | |
326 | dev_kfree_skb(skb); | |
327 | } | |
328 | ||
b77f483f S |
329 | if (sc->rx.rxdma.dd_desc_len != 0) |
330 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
331 | } |
332 | ||
333 | /* | |
334 | * Calculate the receive filter according to the | |
335 | * operating mode and state: | |
336 | * | |
337 | * o always accept unicast, broadcast, and multicast traffic | |
338 | * o maintain current state of phy error reception (the hal | |
339 | * may enable phy error frames for noise immunity work) | |
340 | * o probe request frames are accepted only when operating in | |
341 | * hostap, adhoc, or monitor modes | |
342 | * o enable promiscuous mode according to the interface state | |
343 | * o accept beacons: | |
344 | * - when operating in adhoc mode so the 802.11 layer creates | |
345 | * node table entries for peers, | |
346 | * - when operating in station mode for collecting rssi data when | |
347 | * the station is otherwise quiet, or | |
348 | * - when operating as a repeater so we see repeater-sta beacons | |
349 | * - when scanning | |
350 | */ | |
351 | ||
352 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
353 | { | |
354 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 355 | |
f078f209 LR |
356 | u32 rfilt; |
357 | ||
358 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
359 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
360 | | ATH9K_RX_FILTER_MCAST; | |
361 | ||
362 | /* If not a STA, enable processing of Probe Requests */ | |
d97809db | 363 | if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
364 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
365 | ||
366 | /* Can't set HOSTAP into promiscous mode */ | |
d97809db | 367 | if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && |
b77f483f | 368 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
d97809db | 369 | (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { |
f078f209 LR |
370 | rfilt |= ATH9K_RX_FILTER_PROM; |
371 | /* ??? To prevent from sending ACK */ | |
372 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | |
373 | } | |
374 | ||
d42c6b71 S |
375 | if (sc->rx.rxfilter & FIF_CONTROL) |
376 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
377 | ||
d97809db CM |
378 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || |
379 | sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) | |
f078f209 LR |
380 | rfilt |= ATH9K_RX_FILTER_BEACON; |
381 | ||
382 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames | |
383 | & beacon frames */ | |
d97809db | 384 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) |
f078f209 | 385 | rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); |
be0418ad | 386 | |
f078f209 | 387 | return rfilt; |
7dcfdcd9 | 388 | |
f078f209 LR |
389 | #undef RX_FILTER_PRESERVE |
390 | } | |
391 | ||
f078f209 LR |
392 | int ath_startrecv(struct ath_softc *sc) |
393 | { | |
394 | struct ath_hal *ah = sc->sc_ah; | |
395 | struct ath_buf *bf, *tbf; | |
396 | ||
b77f483f S |
397 | spin_lock_bh(&sc->rx.rxbuflock); |
398 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
399 | goto start_recv; |
400 | ||
b77f483f S |
401 | sc->rx.rxlink = NULL; |
402 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
403 | ath_rx_buf_link(sc, bf); |
404 | } | |
405 | ||
406 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 407 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
408 | goto start_recv; |
409 | ||
b77f483f | 410 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 411 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 412 | ath9k_hw_rxena(ah); |
f078f209 LR |
413 | |
414 | start_recv: | |
b77f483f | 415 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
416 | ath_opmode_init(sc); |
417 | ath9k_hw_startpcureceive(ah); | |
418 | ||
f078f209 LR |
419 | return 0; |
420 | } | |
421 | ||
f078f209 LR |
422 | bool ath_stoprecv(struct ath_softc *sc) |
423 | { | |
424 | struct ath_hal *ah = sc->sc_ah; | |
f078f209 LR |
425 | bool stopped; |
426 | ||
be0418ad S |
427 | ath9k_hw_stoppcurecv(ah); |
428 | ath9k_hw_setrxfilter(ah, 0); | |
429 | stopped = ath9k_hw_stopdmarecv(ah); | |
430 | mdelay(3); /* 3ms is long enough for 1 frame */ | |
b77f483f | 431 | sc->rx.rxlink = NULL; |
be0418ad | 432 | |
f078f209 LR |
433 | return stopped; |
434 | } | |
435 | ||
f078f209 LR |
436 | void ath_flushrecv(struct ath_softc *sc) |
437 | { | |
b77f483f | 438 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 439 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 440 | ath_rx_tasklet(sc, 1); |
98deeea0 | 441 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 442 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
443 | } |
444 | ||
f078f209 LR |
445 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
446 | { | |
447 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
448 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
449 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 450 | |
be0418ad | 451 | struct ath_buf *bf; |
f078f209 | 452 | struct ath_desc *ds; |
cb71d9ba | 453 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 454 | struct ieee80211_rx_status rx_status; |
f078f209 | 455 | struct ath_hal *ah = sc->sc_ah; |
be0418ad S |
456 | struct ieee80211_hdr *hdr; |
457 | int hdrlen, padsize, retval; | |
458 | bool decrypt_error = false; | |
459 | u8 keyix; | |
460 | ||
b77f483f | 461 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
462 | |
463 | do { | |
464 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 465 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
466 | break; |
467 | ||
b77f483f S |
468 | if (list_empty(&sc->rx.rxbuf)) { |
469 | sc->rx.rxlink = NULL; | |
f078f209 LR |
470 | break; |
471 | } | |
472 | ||
b77f483f | 473 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 474 | ds = bf->bf_desc; |
f078f209 LR |
475 | |
476 | /* | |
477 | * Must provide the virtual address of the current | |
478 | * descriptor, the physical address, and the virtual | |
479 | * address of the next descriptor in the h/w chain. | |
480 | * This allows the HAL to look ahead to see if the | |
481 | * hardware is done with a descriptor by checking the | |
482 | * done bit in the following descriptor and the address | |
483 | * of the current descriptor the DMA engine is working | |
484 | * on. All this is necessary because of our use of | |
485 | * a self-linked list to avoid rx overruns. | |
486 | */ | |
be0418ad | 487 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
488 | bf->bf_daddr, |
489 | PA2DESC(sc, ds->ds_link), | |
490 | 0); | |
491 | if (retval == -EINPROGRESS) { | |
492 | struct ath_buf *tbf; | |
493 | struct ath_desc *tds; | |
494 | ||
b77f483f S |
495 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
496 | sc->rx.rxlink = NULL; | |
f078f209 LR |
497 | break; |
498 | } | |
499 | ||
500 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
501 | ||
502 | /* | |
503 | * On some hardware the descriptor status words could | |
504 | * get corrupted, including the done bit. Because of | |
505 | * this, check if the next descriptor's done bit is | |
506 | * set or not. | |
507 | * | |
508 | * If the next descriptor's done bit is set, the current | |
509 | * descriptor has been corrupted. Force s/w to discard | |
510 | * this descriptor and continue... | |
511 | */ | |
512 | ||
513 | tds = tbf->bf_desc; | |
be0418ad S |
514 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
515 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 516 | if (retval == -EINPROGRESS) { |
f078f209 LR |
517 | break; |
518 | } | |
519 | } | |
520 | ||
f078f209 | 521 | skb = bf->bf_mpdu; |
be0418ad | 522 | if (!skb) |
f078f209 | 523 | continue; |
f078f209 | 524 | |
9bf9fca8 VT |
525 | /* |
526 | * Synchronize the DMA transfer with CPU before | |
527 | * 1. accessing the frame | |
528 | * 2. requeueing the same buffer to h/w | |
529 | */ | |
7da3c55c | 530 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 531 | sc->rx.bufsize, |
7da3c55c | 532 | DMA_FROM_DEVICE); |
9bf9fca8 | 533 | |
f078f209 | 534 | /* |
be0418ad S |
535 | * If we're asked to flush receive queue, directly |
536 | * chain it back at the queue without processing it. | |
f078f209 | 537 | */ |
be0418ad | 538 | if (flush) |
cb71d9ba | 539 | goto requeue; |
f078f209 | 540 | |
be0418ad | 541 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 542 | goto requeue; |
f078f209 | 543 | |
be0418ad | 544 | /* The status portion of the descriptor could get corrupted. */ |
b77f483f | 545 | if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 546 | goto requeue; |
f078f209 | 547 | |
be0418ad | 548 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
549 | goto requeue; |
550 | ||
551 | /* Ensure we always have an skb to requeue once we are done | |
552 | * processing the current buffer's skb */ | |
b77f483f | 553 | requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); |
cb71d9ba LR |
554 | |
555 | /* If there is no memory we ignore the current RX'd frame, | |
556 | * tell hardware it can give us a new frame using the old | |
b77f483f | 557 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
558 | * processing. */ |
559 | if (!requeue_skb) | |
560 | goto requeue; | |
f078f209 | 561 | |
9bf9fca8 | 562 | /* Unmap the frame */ |
7da3c55c | 563 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 564 | sc->rx.bufsize, |
7da3c55c | 565 | DMA_FROM_DEVICE); |
f078f209 | 566 | |
be0418ad S |
567 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
568 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
569 | ||
570 | /* see if any padding is done by the hw and remove it */ | |
571 | hdr = (struct ieee80211_hdr *)skb->data; | |
572 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
573 | ||
9c5f89b3 JM |
574 | /* The MAC header is padded to have 32-bit boundary if the |
575 | * packet payload is non-zero. The general calculation for | |
576 | * padsize would take into account odd header lengths: | |
577 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
578 | * even-length headers are used, padding can only be 0 or 2 | |
579 | * bytes and we can optimize this a bit. In addition, we must | |
580 | * not try to remove padding from short control frames that do | |
581 | * not have payload. */ | |
582 | padsize = hdrlen & 3; | |
583 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
584 | memmove(skb->data + padsize, skb->data, hdrlen); |
585 | skb_pull(skb, padsize); | |
f078f209 LR |
586 | } |
587 | ||
be0418ad | 588 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 589 | |
be0418ad S |
590 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
591 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
592 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | |
593 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
594 | keyix = skb->data[hdrlen + 3] >> 6; | |
595 | ||
17d7904d | 596 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
597 | rx_status.flag |= RX_FLAG_DECRYPTED; |
598 | } | |
0ced0e17 JM |
599 | if (ah->sw_mgmt_crypto && |
600 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
601 | ieee80211_is_mgmt(hdr->frame_control)) { | |
602 | /* Use software decrypt for management frames. */ | |
603 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
604 | } | |
be0418ad S |
605 | |
606 | /* Send the frame to mac80211 */ | |
607 | __ieee80211_rx(sc->hw, skb, &rx_status); | |
cb71d9ba LR |
608 | |
609 | /* We will now give hardware our shiny new allocated skb */ | |
610 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 611 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 612 | sc->rx.bufsize, |
7da3c55c GJ |
613 | DMA_FROM_DEVICE); |
614 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
615 | bf->bf_buf_addr))) { |
616 | dev_kfree_skb_any(requeue_skb); | |
617 | bf->bf_mpdu = NULL; | |
618 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 619 | "dma_mapping_error() on RX\n"); |
f8316df1 LR |
620 | break; |
621 | } | |
cb71d9ba | 622 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
623 | |
624 | /* | |
625 | * change the default rx antenna if rx diversity chooses the | |
626 | * other antenna 3 times in a row. | |
627 | */ | |
b77f483f S |
628 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
629 | if (++sc->rx.rxotherant >= 3) | |
be0418ad | 630 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 | 631 | } else { |
b77f483f | 632 | sc->rx.rxotherant = 0; |
f078f209 | 633 | } |
3cbb5dd7 VN |
634 | |
635 | if (ieee80211_is_beacon(hdr->frame_control) && | |
636 | (sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) { | |
637 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; | |
638 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); | |
639 | } | |
cb71d9ba | 640 | requeue: |
b77f483f | 641 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 642 | ath_rx_buf_link(sc, bf); |
be0418ad S |
643 | } while (1); |
644 | ||
b77f483f | 645 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
646 | |
647 | return 0; | |
648 | #undef PA2DESC | |
649 | } |