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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
51 | struct ath_desc *ds; |
52 | struct sk_buff *skb; | |
53 | ||
54 | ATH_RXBUF_RESET(bf); | |
55 | ||
56 | ds = bf->bf_desc; | |
be0418ad | 57 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
58 | ds->ds_data = bf->bf_buf_addr; |
59 | ||
be0418ad | 60 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
61 | skb = bf->bf_mpdu; |
62 | ASSERT(skb != NULL); | |
63 | ds->ds_vdata = skb->data; | |
64 | ||
b77f483f | 65 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
66 | * how much data it can DMA to us and that we are prepared |
67 | * to process */ | |
b77f483f S |
68 | ath9k_hw_setuprxdesc(ah, ds, |
69 | sc->rx.bufsize, | |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
89 | /* | |
90 | * Extend 15-bit time stamp from rx descriptor to | |
91 | * a full 64-bit TSF using the current h/w TSF. | |
92 | */ | |
93 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
94 | { | |
95 | u64 tsf; | |
96 | ||
97 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
98 | if ((tsf & 0x7fff) < rstamp) | |
99 | tsf -= 0x8000; | |
100 | return (tsf & ~0x7fff) | rstamp; | |
101 | } | |
102 | ||
f0e6ce13 | 103 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len, gfp_t gfp_mask) |
f078f209 LR |
104 | { |
105 | struct sk_buff *skb; | |
106 | u32 off; | |
107 | ||
108 | /* | |
109 | * Cache-line-align. This is important (for the | |
110 | * 5210 at least) as not doing so causes bogus data | |
111 | * in rx'd frames. | |
112 | */ | |
113 | ||
b4b6cda2 LR |
114 | /* Note: the kernel can allocate a value greater than |
115 | * what we ask it to give us. We really only need 4 KB as that | |
116 | * is this hardware supports and in fact we need at least 3849 | |
117 | * as that is the MAX AMSDU size this hardware supports. | |
118 | * Unfortunately this means we may get 8 KB here from the | |
119 | * kernel... and that is actually what is observed on some | |
120 | * systems :( */ | |
f0e6ce13 | 121 | skb = __dev_alloc_skb(len + sc->cachelsz - 1, gfp_mask); |
f078f209 | 122 | if (skb != NULL) { |
17d7904d | 123 | off = ((unsigned long) skb->data) % sc->cachelsz; |
f078f209 | 124 | if (off != 0) |
17d7904d | 125 | skb_reserve(skb, sc->cachelsz - off); |
f078f209 LR |
126 | } else { |
127 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 128 | "skbuff alloc of size %u failed\n", len); |
f078f209 LR |
129 | return NULL; |
130 | } | |
131 | ||
132 | return skb; | |
133 | } | |
134 | ||
f078f209 | 135 | /* |
be0418ad S |
136 | * For Decrypt or Demic errors, we only mark packet status here and always push |
137 | * up the frame up to let mac80211 handle the actual error case, be it no | |
138 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 139 | */ |
be0418ad S |
140 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
141 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
142 | struct ath_softc *sc) | |
f078f209 | 143 | { |
be0418ad | 144 | struct ieee80211_hdr *hdr; |
be0418ad S |
145 | u8 ratecode; |
146 | __le16 fc; | |
bce048d7 | 147 | struct ieee80211_hw *hw; |
be0418ad S |
148 | |
149 | hdr = (struct ieee80211_hdr *)skb->data; | |
150 | fc = hdr->frame_control; | |
151 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
bce048d7 | 152 | hw = ath_get_virt_hw(sc, hdr); |
be0418ad S |
153 | |
154 | if (ds->ds_rxstat.rs_more) { | |
155 | /* | |
156 | * Frame spans multiple descriptors; this cannot happen yet | |
157 | * as we don't support jumbograms. If not in monitor mode, | |
158 | * discard the frame. Enable this if you want to see | |
159 | * error frames in Monitor mode. | |
160 | */ | |
2660b81a | 161 | if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR) |
be0418ad S |
162 | goto rx_next; |
163 | } else if (ds->ds_rxstat.rs_status != 0) { | |
164 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
165 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
166 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
167 | goto rx_next; | |
f078f209 | 168 | |
be0418ad S |
169 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
170 | *decrypt_error = true; | |
171 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
172 | if (ieee80211_is_ctl(fc)) | |
173 | /* | |
174 | * Sometimes, we get invalid | |
175 | * MIC failures on valid control frames. | |
176 | * Remove these mic errors. | |
177 | */ | |
178 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
179 | else | |
180 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
181 | } | |
182 | /* | |
183 | * Reject error frames with the exception of | |
184 | * decryption and MIC failures. For monitor mode, | |
185 | * we also ignore the CRC error. | |
186 | */ | |
2660b81a | 187 | if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) { |
be0418ad S |
188 | if (ds->ds_rxstat.rs_status & |
189 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
190 | ATH9K_RXERR_CRC)) | |
191 | goto rx_next; | |
192 | } else { | |
193 | if (ds->ds_rxstat.rs_status & | |
194 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
195 | goto rx_next; | |
196 | } | |
197 | } | |
f078f209 LR |
198 | } |
199 | ||
be0418ad | 200 | ratecode = ds->ds_rxstat.rs_rate; |
be0418ad | 201 | |
be0418ad | 202 | if (ratecode & 0x80) { |
baad1d92 JM |
203 | /* HT rate */ |
204 | rx_status->flag |= RX_FLAG_HT; | |
be0418ad | 205 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) |
baad1d92 | 206 | rx_status->flag |= RX_FLAG_40MHZ; |
be0418ad | 207 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) |
baad1d92 JM |
208 | rx_status->flag |= RX_FLAG_SHORT_GI; |
209 | rx_status->rate_idx = ratecode & 0x7f; | |
210 | } else { | |
211 | int i = 0, cur_band, n_rates; | |
baad1d92 JM |
212 | |
213 | cur_band = hw->conf.channel->band; | |
214 | n_rates = sc->sbands[cur_band].n_bitrates; | |
215 | ||
216 | for (i = 0; i < n_rates; i++) { | |
217 | if (sc->sbands[cur_band].bitrates[i].hw_value == | |
218 | ratecode) { | |
219 | rx_status->rate_idx = i; | |
220 | break; | |
221 | } | |
222 | ||
223 | if (sc->sbands[cur_band].bitrates[i].hw_value_short == | |
224 | ratecode) { | |
225 | rx_status->rate_idx = i; | |
226 | rx_status->flag |= RX_FLAG_SHORTPRE; | |
227 | break; | |
228 | } | |
229 | } | |
be0418ad S |
230 | } |
231 | ||
232 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
bce048d7 JM |
233 | rx_status->band = hw->conf.channel->band; |
234 | rx_status->freq = hw->conf.channel->center_freq; | |
17d7904d | 235 | rx_status->noise = sc->ani.noise_floor; |
be0418ad | 236 | rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; |
be0418ad S |
237 | rx_status->antenna = ds->ds_rxstat.rs_antenna; |
238 | ||
239 | /* at 45 you will be able to use MCS 15 reliably. A more elaborate | |
240 | * scheme can be used here but it requires tables of SNR/throughput for | |
241 | * each possible mode used. */ | |
242 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
243 | ||
244 | /* rssi can be more than 45 though, anything above that | |
245 | * should be considered at 100% */ | |
246 | if (rx_status->qual > 100) | |
247 | rx_status->qual = 100; | |
248 | ||
249 | rx_status->flag |= RX_FLAG_TSFT; | |
250 | ||
251 | return 1; | |
252 | rx_next: | |
253 | return 0; | |
f078f209 LR |
254 | } |
255 | ||
256 | static void ath_opmode_init(struct ath_softc *sc) | |
257 | { | |
cbe61d8a | 258 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
259 | u32 rfilt, mfilt[2]; |
260 | ||
261 | /* configure rx filter */ | |
262 | rfilt = ath_calcrxfilter(sc); | |
263 | ath9k_hw_setrxfilter(ah, rfilt); | |
264 | ||
265 | /* configure bssid mask */ | |
2660b81a | 266 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
ba52da58 | 267 | ath9k_hw_setbssidmask(sc); |
f078f209 LR |
268 | |
269 | /* configure operational mode */ | |
270 | ath9k_hw_setopmode(ah); | |
271 | ||
272 | /* Handle any link-level address change. */ | |
ba52da58 | 273 | ath9k_hw_setmac(ah, sc->sc_ah->macaddr); |
f078f209 LR |
274 | |
275 | /* calculate and install multicast filter */ | |
276 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 277 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
278 | } |
279 | ||
280 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
281 | { | |
282 | struct sk_buff *skb; | |
283 | struct ath_buf *bf; | |
284 | int error = 0; | |
285 | ||
797fe5cb S |
286 | spin_lock_init(&sc->rx.rxflushlock); |
287 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
288 | spin_lock_init(&sc->rx.rxbuflock); | |
f078f209 | 289 | |
797fe5cb S |
290 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
291 | min(sc->cachelsz, (u16)64)); | |
f078f209 | 292 | |
797fe5cb S |
293 | DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
294 | sc->cachelsz, sc->rx.bufsize); | |
f078f209 | 295 | |
797fe5cb | 296 | /* Initialize rx descriptors */ |
f078f209 | 297 | |
797fe5cb S |
298 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
299 | "rx", nbufs, 1); | |
300 | if (error != 0) { | |
301 | DPRINTF(sc, ATH_DBG_FATAL, | |
302 | "failed to allocate rx descriptors: %d\n", error); | |
303 | goto err; | |
304 | } | |
f078f209 | 305 | |
797fe5cb S |
306 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
307 | skb = ath_rxbuf_alloc(sc, sc->rx.bufsize, GFP_KERNEL); | |
308 | if (skb == NULL) { | |
309 | error = -ENOMEM; | |
310 | goto err; | |
f078f209 | 311 | } |
f078f209 | 312 | |
797fe5cb S |
313 | bf->bf_mpdu = skb; |
314 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
315 | sc->rx.bufsize, | |
316 | DMA_FROM_DEVICE); | |
317 | if (unlikely(dma_mapping_error(sc->dev, | |
318 | bf->bf_buf_addr))) { | |
319 | dev_kfree_skb_any(skb); | |
320 | bf->bf_mpdu = NULL; | |
321 | DPRINTF(sc, ATH_DBG_FATAL, | |
322 | "dma_mapping_error() on RX init\n"); | |
323 | error = -ENOMEM; | |
324 | goto err; | |
325 | } | |
326 | bf->bf_dmacontext = bf->bf_buf_addr; | |
327 | } | |
328 | sc->rx.rxlink = NULL; | |
f078f209 | 329 | |
797fe5cb | 330 | err: |
f078f209 LR |
331 | if (error) |
332 | ath_rx_cleanup(sc); | |
333 | ||
334 | return error; | |
335 | } | |
336 | ||
f078f209 LR |
337 | void ath_rx_cleanup(struct ath_softc *sc) |
338 | { | |
339 | struct sk_buff *skb; | |
340 | struct ath_buf *bf; | |
341 | ||
b77f483f | 342 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 | 343 | skb = bf->bf_mpdu; |
051b9191 | 344 | if (skb) { |
797fe5cb S |
345 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
346 | sc->rx.bufsize, DMA_FROM_DEVICE); | |
f078f209 | 347 | dev_kfree_skb(skb); |
051b9191 | 348 | } |
f078f209 LR |
349 | } |
350 | ||
b77f483f S |
351 | if (sc->rx.rxdma.dd_desc_len != 0) |
352 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
353 | } |
354 | ||
355 | /* | |
356 | * Calculate the receive filter according to the | |
357 | * operating mode and state: | |
358 | * | |
359 | * o always accept unicast, broadcast, and multicast traffic | |
360 | * o maintain current state of phy error reception (the hal | |
361 | * may enable phy error frames for noise immunity work) | |
362 | * o probe request frames are accepted only when operating in | |
363 | * hostap, adhoc, or monitor modes | |
364 | * o enable promiscuous mode according to the interface state | |
365 | * o accept beacons: | |
366 | * - when operating in adhoc mode so the 802.11 layer creates | |
367 | * node table entries for peers, | |
368 | * - when operating in station mode for collecting rssi data when | |
369 | * the station is otherwise quiet, or | |
370 | * - when operating as a repeater so we see repeater-sta beacons | |
371 | * - when scanning | |
372 | */ | |
373 | ||
374 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
375 | { | |
376 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 377 | |
f078f209 LR |
378 | u32 rfilt; |
379 | ||
380 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
381 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
382 | | ATH9K_RX_FILTER_MCAST; | |
383 | ||
384 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 385 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
386 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
387 | ||
217ba9da JM |
388 | /* |
389 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
390 | * mode interface or when in monitor mode. AP mode does not need this | |
391 | * since it receives all in-BSS frames anyway. | |
392 | */ | |
2660b81a | 393 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 394 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 395 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 396 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 397 | |
d42c6b71 S |
398 | if (sc->rx.rxfilter & FIF_CONTROL) |
399 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
400 | ||
dbaaa147 VT |
401 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
402 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
403 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
404 | else | |
f078f209 LR |
405 | rfilt |= ATH9K_RX_FILTER_BEACON; |
406 | ||
dbaaa147 | 407 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames */ |
2660b81a | 408 | if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) |
dbaaa147 | 409 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 410 | |
b93bce2a JM |
411 | if (sc->sec_wiphy) { |
412 | /* TODO: only needed if more than one BSSID is in use in | |
413 | * station/adhoc mode */ | |
414 | /* TODO: for older chips, may need to add ATH9K_RX_FILTER_PROM | |
415 | */ | |
416 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; | |
417 | } | |
418 | ||
f078f209 | 419 | return rfilt; |
7dcfdcd9 | 420 | |
f078f209 LR |
421 | #undef RX_FILTER_PRESERVE |
422 | } | |
423 | ||
f078f209 LR |
424 | int ath_startrecv(struct ath_softc *sc) |
425 | { | |
cbe61d8a | 426 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
427 | struct ath_buf *bf, *tbf; |
428 | ||
b77f483f S |
429 | spin_lock_bh(&sc->rx.rxbuflock); |
430 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
431 | goto start_recv; |
432 | ||
b77f483f S |
433 | sc->rx.rxlink = NULL; |
434 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
435 | ath_rx_buf_link(sc, bf); |
436 | } | |
437 | ||
438 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 439 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
440 | goto start_recv; |
441 | ||
b77f483f | 442 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 443 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 444 | ath9k_hw_rxena(ah); |
f078f209 LR |
445 | |
446 | start_recv: | |
b77f483f | 447 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
448 | ath_opmode_init(sc); |
449 | ath9k_hw_startpcureceive(ah); | |
450 | ||
f078f209 LR |
451 | return 0; |
452 | } | |
453 | ||
f078f209 LR |
454 | bool ath_stoprecv(struct ath_softc *sc) |
455 | { | |
cbe61d8a | 456 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
457 | bool stopped; |
458 | ||
be0418ad S |
459 | ath9k_hw_stoppcurecv(ah); |
460 | ath9k_hw_setrxfilter(ah, 0); | |
461 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 462 | sc->rx.rxlink = NULL; |
be0418ad | 463 | |
f078f209 LR |
464 | return stopped; |
465 | } | |
466 | ||
f078f209 LR |
467 | void ath_flushrecv(struct ath_softc *sc) |
468 | { | |
b77f483f | 469 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 470 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 471 | ath_rx_tasklet(sc, 1); |
98deeea0 | 472 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 473 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
474 | } |
475 | ||
f078f209 LR |
476 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
477 | { | |
478 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
479 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
480 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 481 | |
be0418ad | 482 | struct ath_buf *bf; |
f078f209 | 483 | struct ath_desc *ds; |
cb71d9ba | 484 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 485 | struct ieee80211_rx_status rx_status; |
cbe61d8a | 486 | struct ath_hw *ah = sc->sc_ah; |
be0418ad S |
487 | struct ieee80211_hdr *hdr; |
488 | int hdrlen, padsize, retval; | |
489 | bool decrypt_error = false; | |
490 | u8 keyix; | |
853da11b | 491 | __le16 fc; |
be0418ad | 492 | |
b77f483f | 493 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
494 | |
495 | do { | |
496 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 497 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
498 | break; |
499 | ||
b77f483f S |
500 | if (list_empty(&sc->rx.rxbuf)) { |
501 | sc->rx.rxlink = NULL; | |
f078f209 LR |
502 | break; |
503 | } | |
504 | ||
b77f483f | 505 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 506 | ds = bf->bf_desc; |
f078f209 LR |
507 | |
508 | /* | |
509 | * Must provide the virtual address of the current | |
510 | * descriptor, the physical address, and the virtual | |
511 | * address of the next descriptor in the h/w chain. | |
512 | * This allows the HAL to look ahead to see if the | |
513 | * hardware is done with a descriptor by checking the | |
514 | * done bit in the following descriptor and the address | |
515 | * of the current descriptor the DMA engine is working | |
516 | * on. All this is necessary because of our use of | |
517 | * a self-linked list to avoid rx overruns. | |
518 | */ | |
be0418ad | 519 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
520 | bf->bf_daddr, |
521 | PA2DESC(sc, ds->ds_link), | |
522 | 0); | |
523 | if (retval == -EINPROGRESS) { | |
524 | struct ath_buf *tbf; | |
525 | struct ath_desc *tds; | |
526 | ||
b77f483f S |
527 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
528 | sc->rx.rxlink = NULL; | |
f078f209 LR |
529 | break; |
530 | } | |
531 | ||
532 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
533 | ||
534 | /* | |
535 | * On some hardware the descriptor status words could | |
536 | * get corrupted, including the done bit. Because of | |
537 | * this, check if the next descriptor's done bit is | |
538 | * set or not. | |
539 | * | |
540 | * If the next descriptor's done bit is set, the current | |
541 | * descriptor has been corrupted. Force s/w to discard | |
542 | * this descriptor and continue... | |
543 | */ | |
544 | ||
545 | tds = tbf->bf_desc; | |
be0418ad S |
546 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
547 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 548 | if (retval == -EINPROGRESS) { |
f078f209 LR |
549 | break; |
550 | } | |
551 | } | |
552 | ||
f078f209 | 553 | skb = bf->bf_mpdu; |
be0418ad | 554 | if (!skb) |
f078f209 | 555 | continue; |
f078f209 | 556 | |
9bf9fca8 VT |
557 | /* |
558 | * Synchronize the DMA transfer with CPU before | |
559 | * 1. accessing the frame | |
560 | * 2. requeueing the same buffer to h/w | |
561 | */ | |
7da3c55c | 562 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 563 | sc->rx.bufsize, |
7da3c55c | 564 | DMA_FROM_DEVICE); |
9bf9fca8 | 565 | |
f078f209 | 566 | /* |
be0418ad S |
567 | * If we're asked to flush receive queue, directly |
568 | * chain it back at the queue without processing it. | |
f078f209 | 569 | */ |
be0418ad | 570 | if (flush) |
cb71d9ba | 571 | goto requeue; |
f078f209 | 572 | |
be0418ad | 573 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 574 | goto requeue; |
f078f209 | 575 | |
be0418ad | 576 | /* The status portion of the descriptor could get corrupted. */ |
b77f483f | 577 | if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 578 | goto requeue; |
f078f209 | 579 | |
be0418ad | 580 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
581 | goto requeue; |
582 | ||
583 | /* Ensure we always have an skb to requeue once we are done | |
584 | * processing the current buffer's skb */ | |
f0e6ce13 | 585 | requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize, GFP_ATOMIC); |
cb71d9ba LR |
586 | |
587 | /* If there is no memory we ignore the current RX'd frame, | |
588 | * tell hardware it can give us a new frame using the old | |
b77f483f | 589 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
590 | * processing. */ |
591 | if (!requeue_skb) | |
592 | goto requeue; | |
f078f209 | 593 | |
9bf9fca8 | 594 | /* Unmap the frame */ |
7da3c55c | 595 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 596 | sc->rx.bufsize, |
7da3c55c | 597 | DMA_FROM_DEVICE); |
f078f209 | 598 | |
be0418ad S |
599 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
600 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
601 | ||
602 | /* see if any padding is done by the hw and remove it */ | |
603 | hdr = (struct ieee80211_hdr *)skb->data; | |
604 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
853da11b | 605 | fc = hdr->frame_control; |
be0418ad | 606 | |
9c5f89b3 JM |
607 | /* The MAC header is padded to have 32-bit boundary if the |
608 | * packet payload is non-zero. The general calculation for | |
609 | * padsize would take into account odd header lengths: | |
610 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
611 | * even-length headers are used, padding can only be 0 or 2 | |
612 | * bytes and we can optimize this a bit. In addition, we must | |
613 | * not try to remove padding from short control frames that do | |
614 | * not have payload. */ | |
615 | padsize = hdrlen & 3; | |
616 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
617 | memmove(skb->data + padsize, skb->data, hdrlen); |
618 | skb_pull(skb, padsize); | |
f078f209 LR |
619 | } |
620 | ||
be0418ad | 621 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 622 | |
be0418ad S |
623 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
624 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
625 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | |
626 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
627 | keyix = skb->data[hdrlen + 3] >> 6; | |
628 | ||
17d7904d | 629 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
630 | rx_status.flag |= RX_FLAG_DECRYPTED; |
631 | } | |
0ced0e17 JM |
632 | if (ah->sw_mgmt_crypto && |
633 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
634 | ieee80211_is_mgmt(hdr->frame_control)) { | |
635 | /* Use software decrypt for management frames. */ | |
636 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
637 | } | |
be0418ad S |
638 | |
639 | /* Send the frame to mac80211 */ | |
c52f33d0 JM |
640 | if (hdr->addr1[5] & 0x01) { |
641 | int i; | |
642 | /* | |
643 | * Deliver broadcast/multicast frames to all suitable | |
644 | * virtual wiphys. | |
645 | */ | |
646 | /* TODO: filter based on channel configuration */ | |
647 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
648 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
649 | struct sk_buff *nskb; | |
650 | if (aphy == NULL) | |
651 | continue; | |
652 | nskb = skb_copy(skb, GFP_ATOMIC); | |
653 | if (nskb) | |
654 | __ieee80211_rx(aphy->hw, nskb, | |
655 | &rx_status); | |
656 | } | |
657 | __ieee80211_rx(sc->hw, skb, &rx_status); | |
658 | } else { | |
659 | /* Deliver unicast frames based on receiver address */ | |
660 | __ieee80211_rx(ath_get_virt_hw(sc, hdr), skb, | |
661 | &rx_status); | |
662 | } | |
cb71d9ba LR |
663 | |
664 | /* We will now give hardware our shiny new allocated skb */ | |
665 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 666 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 667 | sc->rx.bufsize, |
7da3c55c GJ |
668 | DMA_FROM_DEVICE); |
669 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
670 | bf->bf_buf_addr))) { |
671 | dev_kfree_skb_any(requeue_skb); | |
672 | bf->bf_mpdu = NULL; | |
d8baa939 | 673 | DPRINTF(sc, ATH_DBG_FATAL, |
7da3c55c | 674 | "dma_mapping_error() on RX\n"); |
f8316df1 LR |
675 | break; |
676 | } | |
cb71d9ba | 677 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
678 | |
679 | /* | |
680 | * change the default rx antenna if rx diversity chooses the | |
681 | * other antenna 3 times in a row. | |
682 | */ | |
b77f483f S |
683 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
684 | if (++sc->rx.rxotherant >= 3) | |
be0418ad | 685 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 | 686 | } else { |
b77f483f | 687 | sc->rx.rxotherant = 0; |
f078f209 | 688 | } |
3cbb5dd7 | 689 | |
853da11b | 690 | if (ieee80211_is_beacon(fc) && |
3cbb5dd7 VN |
691 | (sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) { |
692 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; | |
693 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); | |
694 | } | |
cb71d9ba | 695 | requeue: |
b77f483f | 696 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 697 | ath_rx_buf_link(sc, bf); |
be0418ad S |
698 | } while (1); |
699 | ||
b77f483f | 700 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
701 | |
702 | return 0; | |
703 | #undef PA2DESC | |
704 | } |