]>
Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include "core.h" |
18 | ||
19 | /* | |
20 | * Setup and link descriptors. | |
21 | * | |
22 | * 11N: we can no longer afford to self link the last descriptor. | |
23 | * MAC acknowledges BA status as long as it copies frames to host | |
24 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
25 | * to a sender if last desc is self-linked. | |
f078f209 | 26 | */ |
f078f209 LR |
27 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
28 | { | |
29 | struct ath_hal *ah = sc->sc_ah; | |
30 | struct ath_desc *ds; | |
31 | struct sk_buff *skb; | |
32 | ||
33 | ATH_RXBUF_RESET(bf); | |
34 | ||
35 | ds = bf->bf_desc; | |
be0418ad | 36 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
37 | ds->ds_data = bf->bf_buf_addr; |
38 | ||
be0418ad | 39 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
40 | skb = bf->bf_mpdu; |
41 | ASSERT(skb != NULL); | |
42 | ds->ds_vdata = skb->data; | |
43 | ||
b4b6cda2 LR |
44 | /* setup rx descriptors. The sc_rxbufsize here tells the harware |
45 | * how much data it can DMA to us and that we are prepared | |
46 | * to process */ | |
f078f209 LR |
47 | ath9k_hw_setuprxdesc(ah, |
48 | ds, | |
b4b6cda2 | 49 | sc->sc_rxbufsize, |
f078f209 LR |
50 | 0); |
51 | ||
52 | if (sc->sc_rxlink == NULL) | |
53 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | |
54 | else | |
55 | *sc->sc_rxlink = bf->bf_daddr; | |
56 | ||
57 | sc->sc_rxlink = &ds->ds_link; | |
58 | ath9k_hw_rxena(ah); | |
59 | } | |
60 | ||
ff37e337 S |
61 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
62 | { | |
63 | /* XXX block beacon interrupts */ | |
64 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
65 | sc->sc_defant = antenna; | |
66 | sc->sc_rxotherant = 0; | |
67 | } | |
68 | ||
69 | /* | |
70 | * Extend 15-bit time stamp from rx descriptor to | |
71 | * a full 64-bit TSF using the current h/w TSF. | |
72 | */ | |
73 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
74 | { | |
75 | u64 tsf; | |
76 | ||
77 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
78 | if ((tsf & 0x7fff) < rstamp) | |
79 | tsf -= 0x8000; | |
80 | return (tsf & ~0x7fff) | rstamp; | |
81 | } | |
82 | ||
be0418ad | 83 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) |
f078f209 LR |
84 | { |
85 | struct sk_buff *skb; | |
86 | u32 off; | |
87 | ||
88 | /* | |
89 | * Cache-line-align. This is important (for the | |
90 | * 5210 at least) as not doing so causes bogus data | |
91 | * in rx'd frames. | |
92 | */ | |
93 | ||
b4b6cda2 LR |
94 | /* Note: the kernel can allocate a value greater than |
95 | * what we ask it to give us. We really only need 4 KB as that | |
96 | * is this hardware supports and in fact we need at least 3849 | |
97 | * as that is the MAX AMSDU size this hardware supports. | |
98 | * Unfortunately this means we may get 8 KB here from the | |
99 | * kernel... and that is actually what is observed on some | |
100 | * systems :( */ | |
f078f209 LR |
101 | skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); |
102 | if (skb != NULL) { | |
103 | off = ((unsigned long) skb->data) % sc->sc_cachelsz; | |
104 | if (off != 0) | |
105 | skb_reserve(skb, sc->sc_cachelsz - off); | |
106 | } else { | |
107 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 108 | "skbuff alloc of size %u failed\n", len); |
f078f209 LR |
109 | return NULL; |
110 | } | |
111 | ||
112 | return skb; | |
113 | } | |
114 | ||
be0418ad S |
115 | static int ath_rate2idx(struct ath_softc *sc, int rate) |
116 | { | |
117 | int i = 0, cur_band, n_rates; | |
118 | struct ieee80211_hw *hw = sc->hw; | |
119 | ||
120 | cur_band = hw->conf.channel->band; | |
121 | n_rates = sc->sbands[cur_band].n_bitrates; | |
122 | ||
123 | for (i = 0; i < n_rates; i++) { | |
124 | if (sc->sbands[cur_band].bitrates[i].bitrate == rate) | |
125 | break; | |
126 | } | |
127 | ||
128 | /* | |
129 | * NB:mac80211 validates rx rate index against the supported legacy rate | |
130 | * index only (should be done against ht rates also), return the highest | |
131 | * legacy rate index for rx rate which does not match any one of the | |
132 | * supported basic and extended rates to make mac80211 happy. | |
133 | * The following hack will be cleaned up once the issue with | |
134 | * the rx rate index validation in mac80211 is fixed. | |
135 | */ | |
136 | if (i == n_rates) | |
137 | return n_rates - 1; | |
138 | ||
139 | return i; | |
f078f209 LR |
140 | } |
141 | ||
142 | /* | |
be0418ad S |
143 | * For Decrypt or Demic errors, we only mark packet status here and always push |
144 | * up the frame up to let mac80211 handle the actual error case, be it no | |
145 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 146 | */ |
be0418ad S |
147 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
148 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
149 | struct ath_softc *sc) | |
f078f209 | 150 | { |
e63835b0 | 151 | struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode]; |
be0418ad | 152 | struct ieee80211_hdr *hdr; |
e63835b0 | 153 | int ratekbps, rix; |
be0418ad S |
154 | u8 ratecode; |
155 | __le16 fc; | |
156 | ||
157 | hdr = (struct ieee80211_hdr *)skb->data; | |
158 | fc = hdr->frame_control; | |
159 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
160 | ||
161 | if (ds->ds_rxstat.rs_more) { | |
162 | /* | |
163 | * Frame spans multiple descriptors; this cannot happen yet | |
164 | * as we don't support jumbograms. If not in monitor mode, | |
165 | * discard the frame. Enable this if you want to see | |
166 | * error frames in Monitor mode. | |
167 | */ | |
168 | if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR) | |
169 | goto rx_next; | |
170 | } else if (ds->ds_rxstat.rs_status != 0) { | |
171 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
172 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
173 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
174 | goto rx_next; | |
f078f209 | 175 | |
be0418ad S |
176 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
177 | *decrypt_error = true; | |
178 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
179 | if (ieee80211_is_ctl(fc)) | |
180 | /* | |
181 | * Sometimes, we get invalid | |
182 | * MIC failures on valid control frames. | |
183 | * Remove these mic errors. | |
184 | */ | |
185 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
186 | else | |
187 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
188 | } | |
189 | /* | |
190 | * Reject error frames with the exception of | |
191 | * decryption and MIC failures. For monitor mode, | |
192 | * we also ignore the CRC error. | |
193 | */ | |
194 | if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) { | |
195 | if (ds->ds_rxstat.rs_status & | |
196 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
197 | ATH9K_RXERR_CRC)) | |
198 | goto rx_next; | |
199 | } else { | |
200 | if (ds->ds_rxstat.rs_status & | |
201 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
202 | goto rx_next; | |
203 | } | |
204 | } | |
f078f209 LR |
205 | } |
206 | ||
be0418ad | 207 | ratecode = ds->ds_rxstat.rs_rate; |
e63835b0 S |
208 | rix = rate_table->rateCodeToIndex[ratecode]; |
209 | ratekbps = rate_table->info[rix].ratekbps; | |
be0418ad S |
210 | |
211 | /* HT rate */ | |
212 | if (ratecode & 0x80) { | |
213 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) | |
214 | ratekbps = (ratekbps * 27) / 13; | |
215 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) | |
216 | ratekbps = (ratekbps * 10) / 9; | |
217 | } | |
218 | ||
219 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
220 | rx_status->band = sc->hw->conf.channel->band; | |
221 | rx_status->freq = sc->hw->conf.channel->center_freq; | |
222 | rx_status->noise = sc->sc_ani.sc_noise_floor; | |
223 | rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; | |
224 | rx_status->rate_idx = ath_rate2idx(sc, (ratekbps / 100)); | |
225 | rx_status->antenna = ds->ds_rxstat.rs_antenna; | |
226 | ||
227 | /* at 45 you will be able to use MCS 15 reliably. A more elaborate | |
228 | * scheme can be used here but it requires tables of SNR/throughput for | |
229 | * each possible mode used. */ | |
230 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
231 | ||
232 | /* rssi can be more than 45 though, anything above that | |
233 | * should be considered at 100% */ | |
234 | if (rx_status->qual > 100) | |
235 | rx_status->qual = 100; | |
236 | ||
237 | rx_status->flag |= RX_FLAG_TSFT; | |
238 | ||
239 | return 1; | |
240 | rx_next: | |
241 | return 0; | |
f078f209 LR |
242 | } |
243 | ||
244 | static void ath_opmode_init(struct ath_softc *sc) | |
245 | { | |
246 | struct ath_hal *ah = sc->sc_ah; | |
247 | u32 rfilt, mfilt[2]; | |
248 | ||
249 | /* configure rx filter */ | |
250 | rfilt = ath_calcrxfilter(sc); | |
251 | ath9k_hw_setrxfilter(ah, rfilt); | |
252 | ||
253 | /* configure bssid mask */ | |
60b67f51 | 254 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
f078f209 LR |
255 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); |
256 | ||
257 | /* configure operational mode */ | |
258 | ath9k_hw_setopmode(ah); | |
259 | ||
260 | /* Handle any link-level address change. */ | |
261 | ath9k_hw_setmac(ah, sc->sc_myaddr); | |
262 | ||
263 | /* calculate and install multicast filter */ | |
264 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 265 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
266 | } |
267 | ||
268 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
269 | { | |
270 | struct sk_buff *skb; | |
271 | struct ath_buf *bf; | |
272 | int error = 0; | |
273 | ||
274 | do { | |
275 | spin_lock_init(&sc->sc_rxflushlock); | |
98deeea0 | 276 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
277 | spin_lock_init(&sc->sc_rxbuflock); |
278 | ||
f078f209 LR |
279 | sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
280 | min(sc->sc_cachelsz, | |
281 | (u16)64)); | |
282 | ||
04bd4638 S |
283 | DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
284 | sc->sc_cachelsz, sc->sc_rxbufsize); | |
f078f209 LR |
285 | |
286 | /* Initialize rx descriptors */ | |
287 | ||
288 | error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, | |
289 | "rx", nbufs, 1); | |
290 | if (error != 0) { | |
291 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 292 | "failed to allocate rx descriptors: %d\n", error); |
f078f209 LR |
293 | break; |
294 | } | |
295 | ||
f078f209 LR |
296 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { |
297 | skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | |
298 | if (skb == NULL) { | |
299 | error = -ENOMEM; | |
300 | break; | |
301 | } | |
302 | ||
303 | bf->bf_mpdu = skb; | |
927e70e9 | 304 | bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data, |
ca0c7e51 | 305 | sc->sc_rxbufsize, |
927e70e9 S |
306 | PCI_DMA_FROMDEVICE); |
307 | bf->bf_dmacontext = bf->bf_buf_addr; | |
f078f209 LR |
308 | } |
309 | sc->sc_rxlink = NULL; | |
310 | ||
311 | } while (0); | |
312 | ||
313 | if (error) | |
314 | ath_rx_cleanup(sc); | |
315 | ||
316 | return error; | |
317 | } | |
318 | ||
f078f209 LR |
319 | void ath_rx_cleanup(struct ath_softc *sc) |
320 | { | |
321 | struct sk_buff *skb; | |
322 | struct ath_buf *bf; | |
323 | ||
324 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { | |
325 | skb = bf->bf_mpdu; | |
326 | if (skb) | |
327 | dev_kfree_skb(skb); | |
328 | } | |
329 | ||
f078f209 LR |
330 | if (sc->sc_rxdma.dd_desc_len != 0) |
331 | ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); | |
332 | } | |
333 | ||
334 | /* | |
335 | * Calculate the receive filter according to the | |
336 | * operating mode and state: | |
337 | * | |
338 | * o always accept unicast, broadcast, and multicast traffic | |
339 | * o maintain current state of phy error reception (the hal | |
340 | * may enable phy error frames for noise immunity work) | |
341 | * o probe request frames are accepted only when operating in | |
342 | * hostap, adhoc, or monitor modes | |
343 | * o enable promiscuous mode according to the interface state | |
344 | * o accept beacons: | |
345 | * - when operating in adhoc mode so the 802.11 layer creates | |
346 | * node table entries for peers, | |
347 | * - when operating in station mode for collecting rssi data when | |
348 | * the station is otherwise quiet, or | |
349 | * - when operating as a repeater so we see repeater-sta beacons | |
350 | * - when scanning | |
351 | */ | |
352 | ||
353 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
354 | { | |
355 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 356 | |
f078f209 LR |
357 | u32 rfilt; |
358 | ||
359 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
360 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
361 | | ATH9K_RX_FILTER_MCAST; | |
362 | ||
363 | /* If not a STA, enable processing of Probe Requests */ | |
b4696c8b | 364 | if (sc->sc_ah->ah_opmode != ATH9K_M_STA) |
f078f209 LR |
365 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
366 | ||
367 | /* Can't set HOSTAP into promiscous mode */ | |
b4696c8b | 368 | if (((sc->sc_ah->ah_opmode != ATH9K_M_HOSTAP) && |
7dcfdcd9 | 369 | (sc->rx_filter & FIF_PROMISC_IN_BSS)) || |
b4696c8b | 370 | (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR)) { |
f078f209 LR |
371 | rfilt |= ATH9K_RX_FILTER_PROM; |
372 | /* ??? To prevent from sending ACK */ | |
373 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | |
374 | } | |
375 | ||
ffb82676 | 376 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA || |
be0418ad | 377 | sc->sc_ah->ah_opmode == ATH9K_M_IBSS) |
f078f209 LR |
378 | rfilt |= ATH9K_RX_FILTER_BEACON; |
379 | ||
380 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames | |
381 | & beacon frames */ | |
b4696c8b | 382 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) |
f078f209 | 383 | rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); |
be0418ad | 384 | |
f078f209 | 385 | return rfilt; |
7dcfdcd9 | 386 | |
f078f209 LR |
387 | #undef RX_FILTER_PRESERVE |
388 | } | |
389 | ||
f078f209 LR |
390 | int ath_startrecv(struct ath_softc *sc) |
391 | { | |
392 | struct ath_hal *ah = sc->sc_ah; | |
393 | struct ath_buf *bf, *tbf; | |
394 | ||
395 | spin_lock_bh(&sc->sc_rxbuflock); | |
396 | if (list_empty(&sc->sc_rxbuf)) | |
397 | goto start_recv; | |
398 | ||
399 | sc->sc_rxlink = NULL; | |
400 | list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) { | |
f078f209 LR |
401 | ath_rx_buf_link(sc, bf); |
402 | } | |
403 | ||
404 | /* We could have deleted elements so the list may be empty now */ | |
405 | if (list_empty(&sc->sc_rxbuf)) | |
406 | goto start_recv; | |
407 | ||
408 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | |
409 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | |
be0418ad | 410 | ath9k_hw_rxena(ah); |
f078f209 LR |
411 | |
412 | start_recv: | |
413 | spin_unlock_bh(&sc->sc_rxbuflock); | |
be0418ad S |
414 | ath_opmode_init(sc); |
415 | ath9k_hw_startpcureceive(ah); | |
416 | ||
f078f209 LR |
417 | return 0; |
418 | } | |
419 | ||
f078f209 LR |
420 | bool ath_stoprecv(struct ath_softc *sc) |
421 | { | |
422 | struct ath_hal *ah = sc->sc_ah; | |
f078f209 LR |
423 | bool stopped; |
424 | ||
be0418ad S |
425 | ath9k_hw_stoppcurecv(ah); |
426 | ath9k_hw_setrxfilter(ah, 0); | |
427 | stopped = ath9k_hw_stopdmarecv(ah); | |
428 | mdelay(3); /* 3ms is long enough for 1 frame */ | |
429 | sc->sc_rxlink = NULL; | |
430 | ||
f078f209 LR |
431 | return stopped; |
432 | } | |
433 | ||
f078f209 LR |
434 | void ath_flushrecv(struct ath_softc *sc) |
435 | { | |
f078f209 | 436 | spin_lock_bh(&sc->sc_rxflushlock); |
98deeea0 | 437 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 438 | ath_rx_tasklet(sc, 1); |
98deeea0 | 439 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
440 | spin_unlock_bh(&sc->sc_rxflushlock); |
441 | } | |
442 | ||
f078f209 LR |
443 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
444 | { | |
445 | #define PA2DESC(_sc, _pa) \ | |
446 | ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ | |
447 | ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) | |
448 | ||
be0418ad | 449 | struct ath_buf *bf; |
f078f209 | 450 | struct ath_desc *ds; |
cb71d9ba | 451 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 452 | struct ieee80211_rx_status rx_status; |
f078f209 | 453 | struct ath_hal *ah = sc->sc_ah; |
be0418ad S |
454 | struct ieee80211_hdr *hdr; |
455 | int hdrlen, padsize, retval; | |
456 | bool decrypt_error = false; | |
457 | u8 keyix; | |
458 | ||
459 | spin_lock_bh(&sc->sc_rxbuflock); | |
f078f209 LR |
460 | |
461 | do { | |
462 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 463 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
464 | break; |
465 | ||
f078f209 LR |
466 | if (list_empty(&sc->sc_rxbuf)) { |
467 | sc->sc_rxlink = NULL; | |
f078f209 LR |
468 | break; |
469 | } | |
470 | ||
471 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | |
f078f209 | 472 | ds = bf->bf_desc; |
f078f209 LR |
473 | |
474 | /* | |
475 | * Must provide the virtual address of the current | |
476 | * descriptor, the physical address, and the virtual | |
477 | * address of the next descriptor in the h/w chain. | |
478 | * This allows the HAL to look ahead to see if the | |
479 | * hardware is done with a descriptor by checking the | |
480 | * done bit in the following descriptor and the address | |
481 | * of the current descriptor the DMA engine is working | |
482 | * on. All this is necessary because of our use of | |
483 | * a self-linked list to avoid rx overruns. | |
484 | */ | |
be0418ad | 485 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
486 | bf->bf_daddr, |
487 | PA2DESC(sc, ds->ds_link), | |
488 | 0); | |
489 | if (retval == -EINPROGRESS) { | |
490 | struct ath_buf *tbf; | |
491 | struct ath_desc *tds; | |
492 | ||
493 | if (list_is_last(&bf->list, &sc->sc_rxbuf)) { | |
be0418ad | 494 | sc->sc_rxlink = NULL; |
f078f209 LR |
495 | break; |
496 | } | |
497 | ||
498 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
499 | ||
500 | /* | |
501 | * On some hardware the descriptor status words could | |
502 | * get corrupted, including the done bit. Because of | |
503 | * this, check if the next descriptor's done bit is | |
504 | * set or not. | |
505 | * | |
506 | * If the next descriptor's done bit is set, the current | |
507 | * descriptor has been corrupted. Force s/w to discard | |
508 | * this descriptor and continue... | |
509 | */ | |
510 | ||
511 | tds = tbf->bf_desc; | |
be0418ad S |
512 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
513 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 514 | if (retval == -EINPROGRESS) { |
f078f209 LR |
515 | break; |
516 | } | |
517 | } | |
518 | ||
f078f209 | 519 | skb = bf->bf_mpdu; |
be0418ad | 520 | if (!skb) |
f078f209 | 521 | continue; |
f078f209 | 522 | |
f078f209 | 523 | /* |
be0418ad S |
524 | * If we're asked to flush receive queue, directly |
525 | * chain it back at the queue without processing it. | |
f078f209 | 526 | */ |
be0418ad | 527 | if (flush) |
cb71d9ba | 528 | goto requeue; |
f078f209 | 529 | |
be0418ad | 530 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 531 | goto requeue; |
f078f209 | 532 | |
be0418ad | 533 | /* The status portion of the descriptor could get corrupted. */ |
f078f209 | 534 | if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 535 | goto requeue; |
f078f209 | 536 | |
be0418ad | 537 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
538 | goto requeue; |
539 | ||
540 | /* Ensure we always have an skb to requeue once we are done | |
541 | * processing the current buffer's skb */ | |
542 | requeue_skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | |
543 | ||
544 | /* If there is no memory we ignore the current RX'd frame, | |
545 | * tell hardware it can give us a new frame using the old | |
546 | * skb and put it at the tail of the sc->sc_rxbuf list for | |
547 | * processing. */ | |
548 | if (!requeue_skb) | |
549 | goto requeue; | |
f078f209 LR |
550 | |
551 | pci_dma_sync_single_for_cpu(sc->pdev, | |
552 | bf->bf_buf_addr, | |
ca0c7e51 | 553 | sc->sc_rxbufsize, |
f078f209 | 554 | PCI_DMA_FROMDEVICE); |
be0418ad | 555 | pci_unmap_single(sc->pdev, bf->bf_buf_addr, |
f078f209 LR |
556 | sc->sc_rxbufsize, |
557 | PCI_DMA_FROMDEVICE); | |
558 | ||
be0418ad S |
559 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
560 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
561 | ||
562 | /* see if any padding is done by the hw and remove it */ | |
563 | hdr = (struct ieee80211_hdr *)skb->data; | |
564 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
565 | ||
566 | if (hdrlen & 3) { | |
567 | padsize = hdrlen % 4; | |
568 | memmove(skb->data + padsize, skb->data, hdrlen); | |
569 | skb_pull(skb, padsize); | |
f078f209 LR |
570 | } |
571 | ||
be0418ad | 572 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 573 | |
be0418ad S |
574 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
575 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
576 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | |
577 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
578 | keyix = skb->data[hdrlen + 3] >> 6; | |
579 | ||
580 | if (test_bit(keyix, sc->sc_keymap)) | |
581 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
582 | } | |
583 | ||
584 | /* Send the frame to mac80211 */ | |
585 | __ieee80211_rx(sc->hw, skb, &rx_status); | |
cb71d9ba LR |
586 | |
587 | /* We will now give hardware our shiny new allocated skb */ | |
588 | bf->bf_mpdu = requeue_skb; | |
589 | bf->bf_buf_addr = pci_map_single(sc->pdev, requeue_skb->data, | |
590 | sc->sc_rxbufsize, | |
591 | PCI_DMA_FROMDEVICE); | |
592 | bf->bf_dmacontext = bf->bf_buf_addr; | |
f078f209 LR |
593 | |
594 | /* | |
595 | * change the default rx antenna if rx diversity chooses the | |
596 | * other antenna 3 times in a row. | |
597 | */ | |
598 | if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { | |
599 | if (++sc->sc_rxotherant >= 3) | |
be0418ad | 600 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 LR |
601 | } else { |
602 | sc->sc_rxotherant = 0; | |
603 | } | |
cb71d9ba LR |
604 | requeue: |
605 | list_move_tail(&bf->list, &sc->sc_rxbuf); | |
606 | ath_rx_buf_link(sc, bf); | |
be0418ad S |
607 | } while (1); |
608 | ||
609 | spin_unlock_bh(&sc->sc_rxbuflock); | |
f078f209 LR |
610 | |
611 | return 0; | |
612 | #undef PA2DESC | |
613 | } |