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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Implementation of receive path. | |
19 | */ | |
20 | ||
21 | #include "core.h" | |
22 | ||
23 | /* | |
24 | * Setup and link descriptors. | |
25 | * | |
26 | * 11N: we can no longer afford to self link the last descriptor. | |
27 | * MAC acknowledges BA status as long as it copies frames to host | |
28 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
29 | * to a sender if last desc is self-linked. | |
30 | * | |
31 | * NOTE: Caller should hold the rxbuf lock. | |
32 | */ | |
33 | ||
34 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) | |
35 | { | |
36 | struct ath_hal *ah = sc->sc_ah; | |
37 | struct ath_desc *ds; | |
38 | struct sk_buff *skb; | |
39 | ||
40 | ATH_RXBUF_RESET(bf); | |
41 | ||
42 | ds = bf->bf_desc; | |
43 | ds->ds_link = 0; /* link to null */ | |
44 | ds->ds_data = bf->bf_buf_addr; | |
45 | ||
46 | /* XXX For RADAR? | |
47 | * virtual addr of the beginning of the buffer. */ | |
48 | skb = bf->bf_mpdu; | |
49 | ASSERT(skb != NULL); | |
50 | ds->ds_vdata = skb->data; | |
51 | ||
52 | /* setup rx descriptors */ | |
53 | ath9k_hw_setuprxdesc(ah, | |
54 | ds, | |
55 | skb_tailroom(skb), /* buffer size */ | |
56 | 0); | |
57 | ||
58 | if (sc->sc_rxlink == NULL) | |
59 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | |
60 | else | |
61 | *sc->sc_rxlink = bf->bf_daddr; | |
62 | ||
63 | sc->sc_rxlink = &ds->ds_link; | |
64 | ath9k_hw_rxena(ah); | |
65 | } | |
66 | ||
67 | /* Process received BAR frame */ | |
68 | ||
69 | static int ath_bar_rx(struct ath_softc *sc, | |
70 | struct ath_node *an, | |
71 | struct sk_buff *skb) | |
72 | { | |
73 | struct ieee80211_bar *bar; | |
74 | struct ath_arx_tid *rxtid; | |
75 | struct sk_buff *tskb; | |
76 | struct ath_recv_status *rx_status; | |
77 | int tidno, index, cindex; | |
78 | u16 seqno; | |
79 | ||
80 | /* look at BAR contents */ | |
81 | ||
82 | bar = (struct ieee80211_bar *)skb->data; | |
83 | tidno = (le16_to_cpu(bar->control) & IEEE80211_BAR_CTL_TID_M) | |
84 | >> IEEE80211_BAR_CTL_TID_S; | |
85 | seqno = le16_to_cpu(bar->start_seq_num) >> IEEE80211_SEQ_SEQ_SHIFT; | |
86 | ||
87 | /* process BAR - indicate all pending RX frames till the BAR seqno */ | |
88 | ||
89 | rxtid = &an->an_aggr.rx.tid[tidno]; | |
90 | ||
91 | spin_lock_bh(&rxtid->tidlock); | |
92 | ||
93 | /* get relative index */ | |
94 | ||
95 | index = ATH_BA_INDEX(rxtid->seq_next, seqno); | |
96 | ||
97 | /* drop BAR if old sequence (index is too large) */ | |
98 | ||
99 | if ((index > rxtid->baw_size) && | |
100 | (index > (IEEE80211_SEQ_MAX - (rxtid->baw_size << 2)))) | |
101 | /* discard frame, ieee layer may not treat frame as a dup */ | |
102 | goto unlock_and_free; | |
103 | ||
104 | /* complete receive processing for all pending frames upto BAR seqno */ | |
105 | ||
106 | cindex = (rxtid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
107 | while ((rxtid->baw_head != rxtid->baw_tail) && | |
108 | (rxtid->baw_head != cindex)) { | |
109 | tskb = rxtid->rxbuf[rxtid->baw_head].rx_wbuf; | |
110 | rx_status = &rxtid->rxbuf[rxtid->baw_head].rx_status; | |
111 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf = NULL; | |
112 | ||
113 | if (tskb != NULL) | |
114 | ath_rx_subframe(an, tskb, rx_status); | |
115 | ||
116 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
117 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
118 | } | |
119 | ||
120 | /* ... and indicate rest of the frames in-order */ | |
121 | ||
122 | while (rxtid->baw_head != rxtid->baw_tail && | |
123 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf != NULL) { | |
124 | tskb = rxtid->rxbuf[rxtid->baw_head].rx_wbuf; | |
125 | rx_status = &rxtid->rxbuf[rxtid->baw_head].rx_status; | |
126 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf = NULL; | |
127 | ||
128 | ath_rx_subframe(an, tskb, rx_status); | |
129 | ||
130 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
131 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
132 | } | |
133 | ||
134 | unlock_and_free: | |
135 | spin_unlock_bh(&rxtid->tidlock); | |
136 | /* free bar itself */ | |
137 | dev_kfree_skb(skb); | |
138 | return IEEE80211_FTYPE_CTL; | |
139 | } | |
140 | ||
141 | /* Function to handle a subframe of aggregation when HT is enabled */ | |
142 | ||
143 | static int ath_ampdu_input(struct ath_softc *sc, | |
144 | struct ath_node *an, | |
145 | struct sk_buff *skb, | |
146 | struct ath_recv_status *rx_status) | |
147 | { | |
148 | struct ieee80211_hdr *hdr; | |
149 | struct ath_arx_tid *rxtid; | |
150 | struct ath_rxbuf *rxbuf; | |
151 | u8 type, subtype; | |
152 | u16 rxseq; | |
153 | int tid = 0, index, cindex, rxdiff; | |
154 | __le16 fc; | |
155 | u8 *qc; | |
156 | ||
157 | hdr = (struct ieee80211_hdr *)skb->data; | |
158 | fc = hdr->frame_control; | |
159 | ||
160 | /* collect stats of frames with non-zero version */ | |
161 | ||
162 | if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_VERS) != 0) { | |
163 | dev_kfree_skb(skb); | |
164 | return -1; | |
165 | } | |
166 | ||
167 | type = le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_FTYPE; | |
168 | subtype = le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_STYPE; | |
169 | ||
170 | if (ieee80211_is_back_req(fc)) | |
171 | return ath_bar_rx(sc, an, skb); | |
172 | ||
173 | /* special aggregate processing only for qos unicast data frames */ | |
174 | ||
175 | if (!ieee80211_is_data(fc) || | |
176 | !ieee80211_is_data_qos(fc) || | |
177 | is_multicast_ether_addr(hdr->addr1)) | |
178 | return ath_rx_subframe(an, skb, rx_status); | |
179 | ||
180 | /* lookup rx tid state */ | |
181 | ||
182 | if (ieee80211_is_data_qos(fc)) { | |
183 | qc = ieee80211_get_qos_ctl(hdr); | |
184 | tid = qc[0] & 0xf; | |
185 | } | |
186 | ||
b4696c8b | 187 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { |
f078f209 LR |
188 | /* Drop the frame not belonging to me. */ |
189 | if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) { | |
190 | dev_kfree_skb(skb); | |
191 | return -1; | |
192 | } | |
193 | } | |
194 | ||
195 | rxtid = &an->an_aggr.rx.tid[tid]; | |
196 | ||
197 | spin_lock(&rxtid->tidlock); | |
198 | ||
199 | rxdiff = (rxtid->baw_tail - rxtid->baw_head) & | |
200 | (ATH_TID_MAX_BUFS - 1); | |
201 | ||
202 | /* | |
203 | * If the ADDBA exchange has not been completed by the source, | |
204 | * process via legacy path (i.e. no reordering buffer is needed) | |
205 | */ | |
206 | if (!rxtid->addba_exchangecomplete) { | |
207 | spin_unlock(&rxtid->tidlock); | |
208 | return ath_rx_subframe(an, skb, rx_status); | |
209 | } | |
210 | ||
211 | /* extract sequence number from recvd frame */ | |
212 | ||
213 | rxseq = le16_to_cpu(hdr->seq_ctrl) >> IEEE80211_SEQ_SEQ_SHIFT; | |
214 | ||
215 | if (rxtid->seq_reset) { | |
216 | rxtid->seq_reset = 0; | |
217 | rxtid->seq_next = rxseq; | |
218 | } | |
219 | ||
220 | index = ATH_BA_INDEX(rxtid->seq_next, rxseq); | |
221 | ||
222 | /* drop frame if old sequence (index is too large) */ | |
223 | ||
224 | if (index > (IEEE80211_SEQ_MAX - (rxtid->baw_size << 2))) { | |
225 | /* discard frame, ieee layer may not treat frame as a dup */ | |
226 | spin_unlock(&rxtid->tidlock); | |
227 | dev_kfree_skb(skb); | |
228 | return IEEE80211_FTYPE_DATA; | |
229 | } | |
230 | ||
231 | /* sequence number is beyond block-ack window */ | |
232 | ||
233 | if (index >= rxtid->baw_size) { | |
234 | ||
235 | /* complete receive processing for all pending frames */ | |
236 | ||
237 | while (index >= rxtid->baw_size) { | |
238 | ||
239 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | |
240 | ||
241 | if (rxbuf->rx_wbuf != NULL) { | |
242 | ath_rx_subframe(an, rxbuf->rx_wbuf, | |
243 | &rxbuf->rx_status); | |
244 | rxbuf->rx_wbuf = NULL; | |
245 | } | |
246 | ||
247 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
248 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
249 | ||
250 | index--; | |
251 | } | |
252 | } | |
253 | ||
254 | /* add buffer to the recv ba window */ | |
255 | ||
256 | cindex = (rxtid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
257 | rxbuf = rxtid->rxbuf + cindex; | |
258 | ||
259 | if (rxbuf->rx_wbuf != NULL) { | |
260 | spin_unlock(&rxtid->tidlock); | |
261 | /* duplicate frame */ | |
262 | dev_kfree_skb(skb); | |
263 | return IEEE80211_FTYPE_DATA; | |
264 | } | |
265 | ||
266 | rxbuf->rx_wbuf = skb; | |
267 | rxbuf->rx_time = get_timestamp(); | |
268 | rxbuf->rx_status = *rx_status; | |
269 | ||
270 | /* advance tail if sequence received is newer | |
271 | * than any received so far */ | |
272 | ||
273 | if (index >= rxdiff) { | |
274 | rxtid->baw_tail = cindex; | |
275 | INCR(rxtid->baw_tail, ATH_TID_MAX_BUFS); | |
276 | } | |
277 | ||
278 | /* indicate all in-order received frames */ | |
279 | ||
280 | while (rxtid->baw_head != rxtid->baw_tail) { | |
281 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | |
282 | if (!rxbuf->rx_wbuf) | |
283 | break; | |
284 | ||
285 | ath_rx_subframe(an, rxbuf->rx_wbuf, &rxbuf->rx_status); | |
286 | rxbuf->rx_wbuf = NULL; | |
287 | ||
288 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
289 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
290 | } | |
291 | ||
292 | /* | |
293 | * start a timer to flush all received frames if there are pending | |
294 | * receive frames | |
295 | */ | |
296 | if (rxtid->baw_head != rxtid->baw_tail) | |
297 | mod_timer(&rxtid->timer, ATH_RX_TIMEOUT); | |
298 | else | |
299 | del_timer_sync(&rxtid->timer); | |
300 | ||
301 | spin_unlock(&rxtid->tidlock); | |
302 | return IEEE80211_FTYPE_DATA; | |
303 | } | |
304 | ||
305 | /* Timer to flush all received sub-frames */ | |
306 | ||
307 | static void ath_rx_timer(unsigned long data) | |
308 | { | |
309 | struct ath_arx_tid *rxtid = (struct ath_arx_tid *)data; | |
310 | struct ath_node *an = rxtid->an; | |
311 | struct ath_rxbuf *rxbuf; | |
312 | int nosched; | |
313 | ||
314 | spin_lock_bh(&rxtid->tidlock); | |
315 | while (rxtid->baw_head != rxtid->baw_tail) { | |
316 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | |
317 | if (!rxbuf->rx_wbuf) { | |
318 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
319 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
320 | continue; | |
321 | } | |
322 | ||
323 | /* | |
324 | * Stop if the next one is a very recent frame. | |
325 | * | |
326 | * Call get_timestamp in every iteration to protect against the | |
327 | * case in which a new frame is received while we are executing | |
328 | * this function. Using a timestamp obtained before entering | |
329 | * the loop could lead to a very large time interval | |
330 | * (a negative value typecast to unsigned), breaking the | |
331 | * function's logic. | |
332 | */ | |
333 | if ((get_timestamp() - rxbuf->rx_time) < | |
334 | (ATH_RX_TIMEOUT * HZ / 1000)) | |
335 | break; | |
336 | ||
337 | ath_rx_subframe(an, rxbuf->rx_wbuf, | |
338 | &rxbuf->rx_status); | |
339 | rxbuf->rx_wbuf = NULL; | |
340 | ||
341 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
342 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
343 | } | |
344 | ||
345 | /* | |
346 | * start a timer to flush all received frames if there are pending | |
347 | * receive frames | |
348 | */ | |
349 | if (rxtid->baw_head != rxtid->baw_tail) | |
350 | nosched = 0; | |
351 | else | |
352 | nosched = 1; /* no need to re-arm the timer again */ | |
353 | ||
354 | spin_unlock_bh(&rxtid->tidlock); | |
355 | } | |
356 | ||
357 | /* Free all pending sub-frames in the re-ordering buffer */ | |
358 | ||
359 | static void ath_rx_flush_tid(struct ath_softc *sc, | |
360 | struct ath_arx_tid *rxtid, int drop) | |
361 | { | |
362 | struct ath_rxbuf *rxbuf; | |
773b4e02 | 363 | unsigned long flag; |
f078f209 | 364 | |
773b4e02 | 365 | spin_lock_irqsave(&rxtid->tidlock, flag); |
f078f209 LR |
366 | while (rxtid->baw_head != rxtid->baw_tail) { |
367 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | |
368 | if (!rxbuf->rx_wbuf) { | |
369 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
370 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
371 | continue; | |
372 | } | |
373 | ||
374 | if (drop) | |
375 | dev_kfree_skb(rxbuf->rx_wbuf); | |
376 | else | |
377 | ath_rx_subframe(rxtid->an, | |
378 | rxbuf->rx_wbuf, | |
379 | &rxbuf->rx_status); | |
380 | ||
381 | rxbuf->rx_wbuf = NULL; | |
382 | ||
383 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | |
384 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | |
385 | } | |
773b4e02 | 386 | spin_unlock_irqrestore(&rxtid->tidlock, flag); |
f078f209 LR |
387 | } |
388 | ||
389 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, | |
390 | u32 len) | |
391 | { | |
392 | struct sk_buff *skb; | |
393 | u32 off; | |
394 | ||
395 | /* | |
396 | * Cache-line-align. This is important (for the | |
397 | * 5210 at least) as not doing so causes bogus data | |
398 | * in rx'd frames. | |
399 | */ | |
400 | ||
401 | skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); | |
402 | if (skb != NULL) { | |
403 | off = ((unsigned long) skb->data) % sc->sc_cachelsz; | |
404 | if (off != 0) | |
405 | skb_reserve(skb, sc->sc_cachelsz - off); | |
406 | } else { | |
407 | DPRINTF(sc, ATH_DBG_FATAL, | |
408 | "%s: skbuff alloc of size %u failed\n", | |
409 | __func__, len); | |
410 | return NULL; | |
411 | } | |
412 | ||
413 | return skb; | |
414 | } | |
415 | ||
416 | static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb) | |
417 | { | |
418 | struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf; | |
419 | ||
420 | ASSERT(bf != NULL); | |
421 | ||
422 | spin_lock_bh(&sc->sc_rxbuflock); | |
423 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | |
424 | /* | |
425 | * This buffer is still held for hw acess. | |
426 | * Mark it as free to be re-queued it later. | |
427 | */ | |
428 | bf->bf_status |= ATH_BUFSTATUS_FREE; | |
429 | } else { | |
430 | /* XXX: we probably never enter here, remove after | |
431 | * verification */ | |
432 | list_add_tail(&bf->list, &sc->sc_rxbuf); | |
433 | ath_rx_buf_link(sc, bf); | |
434 | } | |
435 | spin_unlock_bh(&sc->sc_rxbuflock); | |
436 | } | |
437 | ||
438 | /* | |
439 | * The skb indicated to upper stack won't be returned to us. | |
440 | * So we have to allocate a new one and queue it by ourselves. | |
441 | */ | |
442 | static int ath_rx_indicate(struct ath_softc *sc, | |
443 | struct sk_buff *skb, | |
444 | struct ath_recv_status *status, | |
445 | u16 keyix) | |
446 | { | |
447 | struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf; | |
448 | struct sk_buff *nskb; | |
449 | int type; | |
450 | ||
451 | /* indicate frame to the stack, which will free the old skb. */ | |
19b73c7f | 452 | type = _ath_rx_indicate(sc, skb, status, keyix); |
f078f209 LR |
453 | |
454 | /* allocate a new skb and queue it to for H/W processing */ | |
455 | nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | |
456 | if (nskb != NULL) { | |
457 | bf->bf_mpdu = nskb; | |
927e70e9 S |
458 | bf->bf_buf_addr = pci_map_single(sc->pdev, nskb->data, |
459 | skb_end_pointer(nskb) - nskb->head, | |
460 | PCI_DMA_FROMDEVICE); | |
461 | bf->bf_dmacontext = bf->bf_buf_addr; | |
f078f209 LR |
462 | ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf; |
463 | ||
464 | /* queue the new wbuf to H/W */ | |
465 | ath_rx_requeue(sc, nskb); | |
466 | } | |
467 | ||
468 | return type; | |
469 | } | |
470 | ||
471 | static void ath_opmode_init(struct ath_softc *sc) | |
472 | { | |
473 | struct ath_hal *ah = sc->sc_ah; | |
474 | u32 rfilt, mfilt[2]; | |
475 | ||
476 | /* configure rx filter */ | |
477 | rfilt = ath_calcrxfilter(sc); | |
478 | ath9k_hw_setrxfilter(ah, rfilt); | |
479 | ||
480 | /* configure bssid mask */ | |
60b67f51 | 481 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
f078f209 LR |
482 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); |
483 | ||
484 | /* configure operational mode */ | |
485 | ath9k_hw_setopmode(ah); | |
486 | ||
487 | /* Handle any link-level address change. */ | |
488 | ath9k_hw_setmac(ah, sc->sc_myaddr); | |
489 | ||
490 | /* calculate and install multicast filter */ | |
491 | mfilt[0] = mfilt[1] = ~0; | |
492 | ||
493 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); | |
494 | DPRINTF(sc, ATH_DBG_CONFIG , | |
495 | "%s: RX filter 0x%x, MC filter %08x:%08x\n", | |
496 | __func__, rfilt, mfilt[0], mfilt[1]); | |
497 | } | |
498 | ||
499 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
500 | { | |
501 | struct sk_buff *skb; | |
502 | struct ath_buf *bf; | |
503 | int error = 0; | |
504 | ||
505 | do { | |
506 | spin_lock_init(&sc->sc_rxflushlock); | |
98deeea0 | 507 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
508 | spin_lock_init(&sc->sc_rxbuflock); |
509 | ||
510 | /* | |
511 | * Cisco's VPN software requires that drivers be able to | |
512 | * receive encapsulated frames that are larger than the MTU. | |
513 | * Since we can't be sure how large a frame we'll get, setup | |
514 | * to handle the larges on possible. | |
515 | */ | |
516 | sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN, | |
517 | min(sc->sc_cachelsz, | |
518 | (u16)64)); | |
519 | ||
520 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n", | |
521 | __func__, sc->sc_cachelsz, sc->sc_rxbufsize); | |
522 | ||
523 | /* Initialize rx descriptors */ | |
524 | ||
525 | error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, | |
526 | "rx", nbufs, 1); | |
527 | if (error != 0) { | |
528 | DPRINTF(sc, ATH_DBG_FATAL, | |
529 | "%s: failed to allocate rx descriptors: %d\n", | |
530 | __func__, error); | |
531 | break; | |
532 | } | |
533 | ||
534 | /* Pre-allocate a wbuf for each rx buffer */ | |
535 | ||
536 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { | |
537 | skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | |
538 | if (skb == NULL) { | |
539 | error = -ENOMEM; | |
540 | break; | |
541 | } | |
542 | ||
543 | bf->bf_mpdu = skb; | |
927e70e9 S |
544 | bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data, |
545 | skb_end_pointer(skb) - skb->head, | |
546 | PCI_DMA_FROMDEVICE); | |
547 | bf->bf_dmacontext = bf->bf_buf_addr; | |
f078f209 LR |
548 | ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf; |
549 | } | |
550 | sc->sc_rxlink = NULL; | |
551 | ||
552 | } while (0); | |
553 | ||
554 | if (error) | |
555 | ath_rx_cleanup(sc); | |
556 | ||
557 | return error; | |
558 | } | |
559 | ||
560 | /* Reclaim all rx queue resources */ | |
561 | ||
562 | void ath_rx_cleanup(struct ath_softc *sc) | |
563 | { | |
564 | struct sk_buff *skb; | |
565 | struct ath_buf *bf; | |
566 | ||
567 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { | |
568 | skb = bf->bf_mpdu; | |
569 | if (skb) | |
570 | dev_kfree_skb(skb); | |
571 | } | |
572 | ||
573 | /* cleanup rx descriptors */ | |
574 | ||
575 | if (sc->sc_rxdma.dd_desc_len != 0) | |
576 | ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); | |
577 | } | |
578 | ||
579 | /* | |
580 | * Calculate the receive filter according to the | |
581 | * operating mode and state: | |
582 | * | |
583 | * o always accept unicast, broadcast, and multicast traffic | |
584 | * o maintain current state of phy error reception (the hal | |
585 | * may enable phy error frames for noise immunity work) | |
586 | * o probe request frames are accepted only when operating in | |
587 | * hostap, adhoc, or monitor modes | |
588 | * o enable promiscuous mode according to the interface state | |
589 | * o accept beacons: | |
590 | * - when operating in adhoc mode so the 802.11 layer creates | |
591 | * node table entries for peers, | |
592 | * - when operating in station mode for collecting rssi data when | |
593 | * the station is otherwise quiet, or | |
594 | * - when operating as a repeater so we see repeater-sta beacons | |
595 | * - when scanning | |
596 | */ | |
597 | ||
598 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
599 | { | |
600 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 601 | |
f078f209 LR |
602 | u32 rfilt; |
603 | ||
604 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
605 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
606 | | ATH9K_RX_FILTER_MCAST; | |
607 | ||
608 | /* If not a STA, enable processing of Probe Requests */ | |
b4696c8b | 609 | if (sc->sc_ah->ah_opmode != ATH9K_M_STA) |
f078f209 LR |
610 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
611 | ||
612 | /* Can't set HOSTAP into promiscous mode */ | |
b4696c8b | 613 | if (((sc->sc_ah->ah_opmode != ATH9K_M_HOSTAP) && |
7dcfdcd9 | 614 | (sc->rx_filter & FIF_PROMISC_IN_BSS)) || |
b4696c8b | 615 | (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR)) { |
f078f209 LR |
616 | rfilt |= ATH9K_RX_FILTER_PROM; |
617 | /* ??? To prevent from sending ACK */ | |
618 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | |
619 | } | |
620 | ||
b4696c8b | 621 | if (((sc->sc_ah->ah_opmode == ATH9K_M_STA) && |
7dcfdcd9 | 622 | (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)) || |
b4696c8b | 623 | (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)) |
f078f209 LR |
624 | rfilt |= ATH9K_RX_FILTER_BEACON; |
625 | ||
626 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames | |
627 | & beacon frames */ | |
b4696c8b | 628 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) |
f078f209 LR |
629 | rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); |
630 | return rfilt; | |
7dcfdcd9 | 631 | |
f078f209 LR |
632 | #undef RX_FILTER_PRESERVE |
633 | } | |
634 | ||
635 | /* Enable the receive h/w following a reset. */ | |
636 | ||
637 | int ath_startrecv(struct ath_softc *sc) | |
638 | { | |
639 | struct ath_hal *ah = sc->sc_ah; | |
640 | struct ath_buf *bf, *tbf; | |
641 | ||
642 | spin_lock_bh(&sc->sc_rxbuflock); | |
643 | if (list_empty(&sc->sc_rxbuf)) | |
644 | goto start_recv; | |
645 | ||
646 | sc->sc_rxlink = NULL; | |
647 | list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) { | |
648 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | |
649 | /* restarting h/w, no need for holding descriptors */ | |
650 | bf->bf_status &= ~ATH_BUFSTATUS_STALE; | |
651 | /* | |
652 | * Upper layer may not be done with the frame yet so | |
653 | * we can't just re-queue it to hardware. Remove it | |
654 | * from h/w queue. It'll be re-queued when upper layer | |
655 | * returns the frame and ath_rx_requeue_mpdu is called. | |
656 | */ | |
657 | if (!(bf->bf_status & ATH_BUFSTATUS_FREE)) { | |
658 | list_del(&bf->list); | |
659 | continue; | |
660 | } | |
661 | } | |
662 | /* chain descriptors */ | |
663 | ath_rx_buf_link(sc, bf); | |
664 | } | |
665 | ||
666 | /* We could have deleted elements so the list may be empty now */ | |
667 | if (list_empty(&sc->sc_rxbuf)) | |
668 | goto start_recv; | |
669 | ||
670 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | |
671 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | |
672 | ath9k_hw_rxena(ah); /* enable recv descriptors */ | |
673 | ||
674 | start_recv: | |
675 | spin_unlock_bh(&sc->sc_rxbuflock); | |
676 | ath_opmode_init(sc); /* set filters, etc. */ | |
677 | ath9k_hw_startpcureceive(ah); /* re-enable PCU/DMA engine */ | |
678 | return 0; | |
679 | } | |
680 | ||
681 | /* Disable the receive h/w in preparation for a reset. */ | |
682 | ||
683 | bool ath_stoprecv(struct ath_softc *sc) | |
684 | { | |
685 | struct ath_hal *ah = sc->sc_ah; | |
686 | u64 tsf; | |
687 | bool stopped; | |
688 | ||
689 | ath9k_hw_stoppcurecv(ah); /* disable PCU */ | |
690 | ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */ | |
691 | stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */ | |
692 | mdelay(3); /* 3ms is long enough for 1 frame */ | |
693 | tsf = ath9k_hw_gettsf64(ah); | |
694 | sc->sc_rxlink = NULL; /* just in case */ | |
695 | return stopped; | |
696 | } | |
697 | ||
698 | /* Flush receive queue */ | |
699 | ||
700 | void ath_flushrecv(struct ath_softc *sc) | |
701 | { | |
702 | /* | |
703 | * ath_rx_tasklet may be used to handle rx interrupt and flush receive | |
704 | * queue at the same time. Use a lock to serialize the access of rx | |
705 | * queue. | |
706 | * ath_rx_tasklet cannot hold the spinlock while indicating packets. | |
707 | * Instead, do not claim the spinlock but check for a flush in | |
708 | * progress (see references to sc_rxflush) | |
709 | */ | |
710 | spin_lock_bh(&sc->sc_rxflushlock); | |
98deeea0 | 711 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 LR |
712 | |
713 | ath_rx_tasklet(sc, 1); | |
714 | ||
98deeea0 | 715 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
716 | spin_unlock_bh(&sc->sc_rxflushlock); |
717 | } | |
718 | ||
719 | /* Process an individual frame */ | |
720 | ||
721 | int ath_rx_input(struct ath_softc *sc, | |
722 | struct ath_node *an, | |
723 | int is_ampdu, | |
724 | struct sk_buff *skb, | |
725 | struct ath_recv_status *rx_status, | |
726 | enum ATH_RX_TYPE *status) | |
727 | { | |
672840ac | 728 | if (is_ampdu && (sc->sc_flags & SC_OP_RXAGGR)) { |
f078f209 LR |
729 | *status = ATH_RX_CONSUMED; |
730 | return ath_ampdu_input(sc, an, skb, rx_status); | |
731 | } else { | |
732 | *status = ATH_RX_NON_CONSUMED; | |
733 | return -1; | |
734 | } | |
735 | } | |
736 | ||
737 | /* Process receive queue, as well as LED, etc. */ | |
738 | ||
739 | int ath_rx_tasklet(struct ath_softc *sc, int flush) | |
740 | { | |
741 | #define PA2DESC(_sc, _pa) \ | |
742 | ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ | |
743 | ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) | |
744 | ||
745 | struct ath_buf *bf, *bf_held = NULL; | |
746 | struct ath_desc *ds; | |
747 | struct ieee80211_hdr *hdr; | |
748 | struct sk_buff *skb = NULL; | |
749 | struct ath_recv_status rx_status; | |
750 | struct ath_hal *ah = sc->sc_ah; | |
751 | int type, rx_processed = 0; | |
752 | u32 phyerr; | |
753 | u8 chainreset = 0; | |
754 | int retval; | |
755 | __le16 fc; | |
756 | ||
757 | do { | |
758 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 759 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
760 | break; |
761 | ||
762 | spin_lock_bh(&sc->sc_rxbuflock); | |
763 | if (list_empty(&sc->sc_rxbuf)) { | |
764 | sc->sc_rxlink = NULL; | |
765 | spin_unlock_bh(&sc->sc_rxbuflock); | |
766 | break; | |
767 | } | |
768 | ||
769 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | |
770 | ||
771 | /* | |
772 | * There is a race condition that BH gets scheduled after sw | |
773 | * writes RxE and before hw re-load the last descriptor to get | |
774 | * the newly chained one. Software must keep the last DONE | |
775 | * descriptor as a holding descriptor - software does so by | |
776 | * marking it with the STALE flag. | |
777 | */ | |
778 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | |
779 | bf_held = bf; | |
780 | if (list_is_last(&bf_held->list, &sc->sc_rxbuf)) { | |
781 | /* | |
782 | * The holding descriptor is the last | |
783 | * descriptor in queue. It's safe to | |
784 | * remove the last holding descriptor | |
785 | * in BH context. | |
786 | */ | |
787 | list_del(&bf_held->list); | |
788 | bf_held->bf_status &= ~ATH_BUFSTATUS_STALE; | |
789 | sc->sc_rxlink = NULL; | |
790 | ||
791 | if (bf_held->bf_status & ATH_BUFSTATUS_FREE) { | |
792 | list_add_tail(&bf_held->list, | |
793 | &sc->sc_rxbuf); | |
794 | ath_rx_buf_link(sc, bf_held); | |
795 | } | |
796 | spin_unlock_bh(&sc->sc_rxbuflock); | |
797 | break; | |
798 | } | |
799 | bf = list_entry(bf->list.next, struct ath_buf, list); | |
800 | } | |
801 | ||
802 | ds = bf->bf_desc; | |
803 | ++rx_processed; | |
804 | ||
805 | /* | |
806 | * Must provide the virtual address of the current | |
807 | * descriptor, the physical address, and the virtual | |
808 | * address of the next descriptor in the h/w chain. | |
809 | * This allows the HAL to look ahead to see if the | |
810 | * hardware is done with a descriptor by checking the | |
811 | * done bit in the following descriptor and the address | |
812 | * of the current descriptor the DMA engine is working | |
813 | * on. All this is necessary because of our use of | |
814 | * a self-linked list to avoid rx overruns. | |
815 | */ | |
816 | retval = ath9k_hw_rxprocdesc(ah, | |
817 | ds, | |
818 | bf->bf_daddr, | |
819 | PA2DESC(sc, ds->ds_link), | |
820 | 0); | |
821 | if (retval == -EINPROGRESS) { | |
822 | struct ath_buf *tbf; | |
823 | struct ath_desc *tds; | |
824 | ||
825 | if (list_is_last(&bf->list, &sc->sc_rxbuf)) { | |
826 | spin_unlock_bh(&sc->sc_rxbuflock); | |
827 | break; | |
828 | } | |
829 | ||
830 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
831 | ||
832 | /* | |
833 | * On some hardware the descriptor status words could | |
834 | * get corrupted, including the done bit. Because of | |
835 | * this, check if the next descriptor's done bit is | |
836 | * set or not. | |
837 | * | |
838 | * If the next descriptor's done bit is set, the current | |
839 | * descriptor has been corrupted. Force s/w to discard | |
840 | * this descriptor and continue... | |
841 | */ | |
842 | ||
843 | tds = tbf->bf_desc; | |
844 | retval = ath9k_hw_rxprocdesc(ah, | |
845 | tds, tbf->bf_daddr, | |
846 | PA2DESC(sc, tds->ds_link), 0); | |
847 | if (retval == -EINPROGRESS) { | |
848 | spin_unlock_bh(&sc->sc_rxbuflock); | |
849 | break; | |
850 | } | |
851 | } | |
852 | ||
853 | /* XXX: we do not support frames spanning | |
854 | * multiple descriptors */ | |
855 | bf->bf_status |= ATH_BUFSTATUS_DONE; | |
856 | ||
857 | skb = bf->bf_mpdu; | |
858 | if (skb == NULL) { /* XXX ??? can this happen */ | |
859 | spin_unlock_bh(&sc->sc_rxbuflock); | |
860 | continue; | |
861 | } | |
862 | /* | |
863 | * Now we know it's a completed frame, we can indicate the | |
864 | * frame. Remove the previous holding descriptor and leave | |
865 | * this one in the queue as the new holding descriptor. | |
866 | */ | |
867 | if (bf_held) { | |
868 | list_del(&bf_held->list); | |
869 | bf_held->bf_status &= ~ATH_BUFSTATUS_STALE; | |
870 | if (bf_held->bf_status & ATH_BUFSTATUS_FREE) { | |
871 | list_add_tail(&bf_held->list, &sc->sc_rxbuf); | |
872 | /* try to requeue this descriptor */ | |
873 | ath_rx_buf_link(sc, bf_held); | |
874 | } | |
875 | } | |
876 | ||
877 | bf->bf_status |= ATH_BUFSTATUS_STALE; | |
878 | bf_held = bf; | |
879 | /* | |
880 | * Release the lock here in case ieee80211_input() return | |
881 | * the frame immediately by calling ath_rx_mpdu_requeue(). | |
882 | */ | |
883 | spin_unlock_bh(&sc->sc_rxbuflock); | |
884 | ||
885 | if (flush) { | |
886 | /* | |
887 | * If we're asked to flush receive queue, directly | |
888 | * chain it back at the queue without processing it. | |
889 | */ | |
890 | goto rx_next; | |
891 | } | |
892 | ||
893 | hdr = (struct ieee80211_hdr *)skb->data; | |
894 | fc = hdr->frame_control; | |
895 | memzero(&rx_status, sizeof(struct ath_recv_status)); | |
896 | ||
897 | if (ds->ds_rxstat.rs_more) { | |
898 | /* | |
899 | * Frame spans multiple descriptors; this | |
900 | * cannot happen yet as we don't support | |
901 | * jumbograms. If not in monitor mode, | |
902 | * discard the frame. | |
903 | */ | |
904 | #ifndef ERROR_FRAMES | |
905 | /* | |
906 | * Enable this if you want to see | |
907 | * error frames in Monitor mode. | |
908 | */ | |
b4696c8b | 909 | if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR) |
f078f209 LR |
910 | goto rx_next; |
911 | #endif | |
912 | /* fall thru for monitor mode handling... */ | |
913 | } else if (ds->ds_rxstat.rs_status != 0) { | |
914 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
915 | rx_status.flags |= ATH_RX_FCS_ERROR; | |
916 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) { | |
917 | phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; | |
918 | goto rx_next; | |
919 | } | |
920 | ||
921 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { | |
922 | /* | |
923 | * Decrypt error. We only mark packet status | |
924 | * here and always push up the frame up to let | |
925 | * mac80211 handle the actual error case, be | |
926 | * it no decryption key or real decryption | |
927 | * error. This let us keep statistics there. | |
928 | */ | |
929 | rx_status.flags |= ATH_RX_DECRYPT_ERROR; | |
930 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
931 | /* | |
932 | * Demic error. We only mark frame status here | |
933 | * and always push up the frame up to let | |
934 | * mac80211 handle the actual error case. This | |
935 | * let us keep statistics there. Hardware may | |
936 | * post a false-positive MIC error. | |
937 | */ | |
938 | if (ieee80211_is_ctl(fc)) | |
939 | /* | |
940 | * Sometimes, we get invalid | |
941 | * MIC failures on valid control frames. | |
942 | * Remove these mic errors. | |
943 | */ | |
944 | ds->ds_rxstat.rs_status &= | |
945 | ~ATH9K_RXERR_MIC; | |
946 | else | |
947 | rx_status.flags |= ATH_RX_MIC_ERROR; | |
948 | } | |
949 | /* | |
950 | * Reject error frames with the exception of | |
951 | * decryption and MIC failures. For monitor mode, | |
952 | * we also ignore the CRC error. | |
953 | */ | |
b4696c8b | 954 | if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) { |
f078f209 LR |
955 | if (ds->ds_rxstat.rs_status & |
956 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
957 | ATH9K_RXERR_CRC)) | |
958 | goto rx_next; | |
959 | } else { | |
960 | if (ds->ds_rxstat.rs_status & | |
961 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
962 | goto rx_next; | |
963 | } | |
964 | } | |
965 | } | |
966 | /* | |
967 | * The status portion of the descriptor could get corrupted. | |
968 | */ | |
969 | if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen) | |
970 | goto rx_next; | |
971 | /* | |
972 | * Sync and unmap the frame. At this point we're | |
973 | * committed to passing the sk_buff somewhere so | |
974 | * clear buf_skb; this means a new sk_buff must be | |
975 | * allocated when the rx descriptor is setup again | |
976 | * to receive another frame. | |
977 | */ | |
978 | skb_put(skb, ds->ds_rxstat.rs_datalen); | |
979 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
980 | rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
981 | rx_status.rateieee = | |
982 | sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate; | |
983 | rx_status.rateKbps = | |
984 | sc->sc_hwmap[ds->ds_rxstat.rs_rate].rateKbps; | |
985 | rx_status.ratecode = ds->ds_rxstat.rs_rate; | |
986 | ||
987 | /* HT rate */ | |
988 | if (rx_status.ratecode & 0x80) { | |
989 | /* TODO - add table to avoid division */ | |
990 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) { | |
991 | rx_status.flags |= ATH_RX_40MHZ; | |
992 | rx_status.rateKbps = | |
993 | (rx_status.rateKbps * 27) / 13; | |
994 | } | |
995 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) | |
996 | rx_status.rateKbps = | |
997 | (rx_status.rateKbps * 10) / 9; | |
998 | else | |
999 | rx_status.flags |= ATH_RX_SHORT_GI; | |
1000 | } | |
1001 | ||
1002 | /* sc->sc_noise_floor is only available when the station | |
1003 | attaches to an AP, so we use a default value | |
1004 | if we are not yet attached. */ | |
1005 | ||
1006 | /* XXX we should use either sc->sc_noise_floor or | |
1007 | * ath_hal_getChanNoise(ah, &sc->sc_curchan) | |
1008 | * to calculate the noise floor. | |
1009 | * However, the value returned by ath_hal_getChanNoise | |
1010 | * seems to be incorrect (-31dBm on the last test), | |
1011 | * so we will use a hard-coded value until we | |
1012 | * figure out what is going on. | |
1013 | */ | |
1014 | rx_status.abs_rssi = | |
1015 | ds->ds_rxstat.rs_rssi + ATH_DEFAULT_NOISE_FLOOR; | |
1016 | ||
1017 | pci_dma_sync_single_for_cpu(sc->pdev, | |
1018 | bf->bf_buf_addr, | |
1019 | skb_tailroom(skb), | |
1020 | PCI_DMA_FROMDEVICE); | |
1021 | pci_unmap_single(sc->pdev, | |
1022 | bf->bf_buf_addr, | |
1023 | sc->sc_rxbufsize, | |
1024 | PCI_DMA_FROMDEVICE); | |
1025 | ||
1026 | /* XXX: Ah! make me more readable, use a helper */ | |
60b67f51 | 1027 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { |
f078f209 LR |
1028 | if (ds->ds_rxstat.rs_moreaggr == 0) { |
1029 | rx_status.rssictl[0] = | |
1030 | ds->ds_rxstat.rs_rssi_ctl0; | |
1031 | rx_status.rssictl[1] = | |
1032 | ds->ds_rxstat.rs_rssi_ctl1; | |
1033 | rx_status.rssictl[2] = | |
1034 | ds->ds_rxstat.rs_rssi_ctl2; | |
1035 | rx_status.rssi = ds->ds_rxstat.rs_rssi; | |
1036 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) { | |
1037 | rx_status.rssiextn[0] = | |
1038 | ds->ds_rxstat.rs_rssi_ext0; | |
1039 | rx_status.rssiextn[1] = | |
1040 | ds->ds_rxstat.rs_rssi_ext1; | |
1041 | rx_status.rssiextn[2] = | |
1042 | ds->ds_rxstat.rs_rssi_ext2; | |
1043 | rx_status.flags |= | |
1044 | ATH_RX_RSSI_EXTN_VALID; | |
1045 | } | |
1046 | rx_status.flags |= ATH_RX_RSSI_VALID | | |
1047 | ATH_RX_CHAIN_RSSI_VALID; | |
1048 | } | |
1049 | } else { | |
1050 | /* | |
1051 | * Need to insert the "combined" rssi into the | |
1052 | * status structure for upper layer processing | |
1053 | */ | |
1054 | rx_status.rssi = ds->ds_rxstat.rs_rssi; | |
1055 | rx_status.flags |= ATH_RX_RSSI_VALID; | |
1056 | } | |
1057 | ||
1058 | /* Pass frames up to the stack. */ | |
1059 | ||
1060 | type = ath_rx_indicate(sc, skb, | |
1061 | &rx_status, ds->ds_rxstat.rs_keyix); | |
1062 | ||
1063 | /* | |
1064 | * change the default rx antenna if rx diversity chooses the | |
1065 | * other antenna 3 times in a row. | |
1066 | */ | |
1067 | if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { | |
1068 | if (++sc->sc_rxotherant >= 3) | |
1069 | ath_setdefantenna(sc, | |
1070 | ds->ds_rxstat.rs_antenna); | |
1071 | } else { | |
1072 | sc->sc_rxotherant = 0; | |
1073 | } | |
1074 | ||
1075 | #ifdef CONFIG_SLOW_ANT_DIV | |
1076 | if ((rx_status.flags & ATH_RX_RSSI_VALID) && | |
1077 | ieee80211_is_beacon(fc)) { | |
1078 | ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat); | |
1079 | } | |
1080 | #endif | |
1081 | /* | |
1082 | * For frames successfully indicated, the buffer will be | |
1083 | * returned to us by upper layers by calling | |
1084 | * ath_rx_mpdu_requeue, either synchronusly or asynchronously. | |
1085 | * So we don't want to do it here in this loop. | |
1086 | */ | |
1087 | continue; | |
1088 | ||
1089 | rx_next: | |
1090 | bf->bf_status |= ATH_BUFSTATUS_FREE; | |
1091 | } while (TRUE); | |
1092 | ||
1093 | if (chainreset) { | |
1094 | DPRINTF(sc, ATH_DBG_CONFIG, | |
1095 | "%s: Reset rx chain mask. " | |
1096 | "Do internal reset\n", __func__); | |
1097 | ASSERT(flush == 0); | |
f45144ef | 1098 | ath_reset(sc, false); |
f078f209 LR |
1099 | } |
1100 | ||
1101 | return 0; | |
1102 | #undef PA2DESC | |
1103 | } | |
1104 | ||
1105 | /* Process ADDBA request in per-TID data structure */ | |
1106 | ||
1107 | int ath_rx_aggr_start(struct ath_softc *sc, | |
1108 | const u8 *addr, | |
1109 | u16 tid, | |
1110 | u16 *ssn) | |
1111 | { | |
1112 | struct ath_arx_tid *rxtid; | |
1113 | struct ath_node *an; | |
1114 | struct ieee80211_hw *hw = sc->hw; | |
1115 | struct ieee80211_supported_band *sband; | |
1116 | u16 buffersize = 0; | |
1117 | ||
1118 | spin_lock_bh(&sc->node_lock); | |
1119 | an = ath_node_find(sc, (u8 *) addr); | |
1120 | spin_unlock_bh(&sc->node_lock); | |
1121 | ||
1122 | if (!an) { | |
1123 | DPRINTF(sc, ATH_DBG_AGGR, | |
1124 | "%s: Node not found to initialize RX aggregation\n", | |
1125 | __func__); | |
1126 | return -1; | |
1127 | } | |
1128 | ||
1129 | sband = hw->wiphy->bands[hw->conf.channel->band]; | |
1130 | buffersize = IEEE80211_MIN_AMPDU_BUF << | |
1131 | sband->ht_info.ampdu_factor; /* FIXME */ | |
1132 | ||
1133 | rxtid = &an->an_aggr.rx.tid[tid]; | |
1134 | ||
1135 | spin_lock_bh(&rxtid->tidlock); | |
672840ac | 1136 | if (sc->sc_flags & SC_OP_RXAGGR) { |
f078f209 LR |
1137 | /* Allow aggregation reception |
1138 | * Adjust rx BA window size. Peer might indicate a | |
1139 | * zero buffer size for a _dont_care_ condition. | |
1140 | */ | |
1141 | if (buffersize) | |
1142 | rxtid->baw_size = min(buffersize, rxtid->baw_size); | |
1143 | ||
1144 | /* set rx sequence number */ | |
1145 | rxtid->seq_next = *ssn; | |
1146 | ||
1147 | /* Allocate the receive buffers for this TID */ | |
1148 | DPRINTF(sc, ATH_DBG_AGGR, | |
1149 | "%s: Allcating rxbuffer for TID %d\n", __func__, tid); | |
1150 | ||
1151 | if (rxtid->rxbuf == NULL) { | |
1152 | /* | |
1153 | * If the rxbuff is not NULL at this point, we *probably* | |
1154 | * already allocated the buffer on a previous ADDBA, | |
1155 | * and this is a subsequent ADDBA that got through. | |
1156 | * Don't allocate, but use the value in the pointer, | |
1157 | * we zero it out when we de-allocate. | |
1158 | */ | |
1159 | rxtid->rxbuf = kmalloc(ATH_TID_MAX_BUFS * | |
1160 | sizeof(struct ath_rxbuf), GFP_ATOMIC); | |
1161 | } | |
1162 | if (rxtid->rxbuf == NULL) { | |
1163 | DPRINTF(sc, ATH_DBG_AGGR, | |
1164 | "%s: Unable to allocate RX buffer, " | |
1165 | "refusing ADDBA\n", __func__); | |
1166 | } else { | |
1167 | /* Ensure the memory is zeroed out (all internal | |
1168 | * pointers are null) */ | |
1169 | memzero(rxtid->rxbuf, ATH_TID_MAX_BUFS * | |
1170 | sizeof(struct ath_rxbuf)); | |
1171 | DPRINTF(sc, ATH_DBG_AGGR, | |
1172 | "%s: Allocated @%p\n", __func__, rxtid->rxbuf); | |
1173 | ||
1174 | /* Allow aggregation reception */ | |
1175 | rxtid->addba_exchangecomplete = 1; | |
1176 | } | |
1177 | } | |
1178 | spin_unlock_bh(&rxtid->tidlock); | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | /* Process DELBA */ | |
1184 | ||
1185 | int ath_rx_aggr_stop(struct ath_softc *sc, | |
1186 | const u8 *addr, | |
1187 | u16 tid) | |
1188 | { | |
1189 | struct ath_node *an; | |
1190 | ||
1191 | spin_lock_bh(&sc->node_lock); | |
1192 | an = ath_node_find(sc, (u8 *) addr); | |
1193 | spin_unlock_bh(&sc->node_lock); | |
1194 | ||
1195 | if (!an) { | |
1196 | DPRINTF(sc, ATH_DBG_AGGR, | |
1197 | "%s: RX aggr stop for non-existent node\n", __func__); | |
1198 | return -1; | |
1199 | } | |
1200 | ||
1201 | ath_rx_aggr_teardown(sc, an, tid); | |
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | /* Rx aggregation tear down */ | |
1206 | ||
1207 | void ath_rx_aggr_teardown(struct ath_softc *sc, | |
1208 | struct ath_node *an, u8 tid) | |
1209 | { | |
1210 | struct ath_arx_tid *rxtid = &an->an_aggr.rx.tid[tid]; | |
1211 | ||
1212 | if (!rxtid->addba_exchangecomplete) | |
1213 | return; | |
1214 | ||
1215 | del_timer_sync(&rxtid->timer); | |
1216 | ath_rx_flush_tid(sc, rxtid, 0); | |
1217 | rxtid->addba_exchangecomplete = 0; | |
1218 | ||
1219 | /* De-allocate the receive buffer array allocated when addba started */ | |
1220 | ||
1221 | if (rxtid->rxbuf) { | |
1222 | DPRINTF(sc, ATH_DBG_AGGR, | |
1223 | "%s: Deallocating TID %d rxbuff @%p\n", | |
1224 | __func__, tid, rxtid->rxbuf); | |
1225 | kfree(rxtid->rxbuf); | |
1226 | ||
1227 | /* Set pointer to null to avoid reuse*/ | |
1228 | rxtid->rxbuf = NULL; | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | /* Initialize per-node receive state */ | |
1233 | ||
1234 | void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an) | |
1235 | { | |
672840ac | 1236 | if (sc->sc_flags & SC_OP_RXAGGR) { |
f078f209 LR |
1237 | struct ath_arx_tid *rxtid; |
1238 | int tidno; | |
1239 | ||
1240 | /* Init per tid rx state */ | |
1241 | for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno]; | |
1242 | tidno < WME_NUM_TID; | |
1243 | tidno++, rxtid++) { | |
1244 | rxtid->an = an; | |
1245 | rxtid->seq_reset = 1; | |
1246 | rxtid->seq_next = 0; | |
1247 | rxtid->baw_size = WME_MAX_BA; | |
1248 | rxtid->baw_head = rxtid->baw_tail = 0; | |
1249 | ||
1250 | /* | |
1251 | * Ensure the buffer pointer is null at this point | |
1252 | * (needs to be allocated when addba is received) | |
1253 | */ | |
1254 | ||
1255 | rxtid->rxbuf = NULL; | |
1256 | setup_timer(&rxtid->timer, ath_rx_timer, | |
1257 | (unsigned long)rxtid); | |
1258 | spin_lock_init(&rxtid->tidlock); | |
1259 | ||
1260 | /* ADDBA state */ | |
1261 | rxtid->addba_exchangecomplete = 0; | |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an) | |
1267 | { | |
672840ac | 1268 | if (sc->sc_flags & SC_OP_RXAGGR) { |
f078f209 LR |
1269 | struct ath_arx_tid *rxtid; |
1270 | int tidno, i; | |
1271 | ||
1272 | /* Init per tid rx state */ | |
1273 | for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno]; | |
1274 | tidno < WME_NUM_TID; | |
1275 | tidno++, rxtid++) { | |
1276 | ||
1277 | if (!rxtid->addba_exchangecomplete) | |
1278 | continue; | |
1279 | ||
1280 | /* must cancel timer first */ | |
1281 | del_timer_sync(&rxtid->timer); | |
1282 | ||
1283 | /* drop any pending sub-frames */ | |
1284 | ath_rx_flush_tid(sc, rxtid, 1); | |
1285 | ||
1286 | for (i = 0; i < ATH_TID_MAX_BUFS; i++) | |
1287 | ASSERT(rxtid->rxbuf[i].rx_wbuf == NULL); | |
1288 | ||
1289 | rxtid->addba_exchangecomplete = 0; | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | } | |
1294 | ||
1295 | /* Cleanup per-node receive state */ | |
1296 | ||
1297 | void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an) | |
1298 | { | |
1299 | ath_rx_node_cleanup(sc, an); | |
1300 | } |