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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / dma.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
280d0e16 40#include <linux/etherdevice.h>
57df40d2 41#include <asm/div64.h>
280d0e16 42
e4d6b795 43
bdceeb2d
MB		 44/* Required number of TX DMA slots per TX frame.
45 * This currently is 2, because we put the header and the ieee80211 frame
46 * into separate slots. */
47#define TX_SLOTS_PER_FRAME 2
48
49
e4d6b795
MB		 50/* 32bit DMA ops. */
51static
52struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
53 int slot,
54 struct b43_dmadesc_meta **meta)
55{
56 struct b43_dmadesc32 *desc;
57
58 *meta = &(ring->meta[slot]);
59 desc = ring->descbase;
60 desc = &(desc[slot]);
61
62 return (struct b43_dmadesc_generic *)desc;
63}
64
65static void op32_fill_descriptor(struct b43_dmaring *ring,
66 struct b43_dmadesc_generic *desc,
67 dma_addr_t dmaaddr, u16 bufsize,
68 int start, int end, int irq)
69{
70 struct b43_dmadesc32 *descbase = ring->descbase;
71 int slot;
72 u32 ctl;
73 u32 addr;
74 u32 addrext;
75
76 slot = (int)(&(desc->dma32) - descbase);
77 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
78
79 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
80 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
81 >> SSB_DMA_TRANSLATION_SHIFT;
82 addr |= ssb_dma_translation(ring->dev->dev);
8eccb53f 83 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
e4d6b795
MB		 84 if (slot == ring->nr_slots - 1)
85 ctl |= B43_DMA32_DCTL_DTABLEEND;
86 if (start)
87 ctl |= B43_DMA32_DCTL_FRAMESTART;
88 if (end)
89 ctl |= B43_DMA32_DCTL_FRAMEEND;
90 if (irq)
91 ctl |= B43_DMA32_DCTL_IRQ;
92 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
93 & B43_DMA32_DCTL_ADDREXT_MASK;
94
95 desc->dma32.control = cpu_to_le32(ctl);
96 desc->dma32.address = cpu_to_le32(addr);
97}
98
99static void op32_poke_tx(struct b43_dmaring *ring, int slot)
100{
101 b43_dma_write(ring, B43_DMA32_TXINDEX,
102 (u32) (slot * sizeof(struct b43_dmadesc32)));
103}
104
105static void op32_tx_suspend(struct b43_dmaring *ring)
106{
107 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
108 | B43_DMA32_TXSUSPEND);
109}
110
111static void op32_tx_resume(struct b43_dmaring *ring)
112{
113 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
114 & ~B43_DMA32_TXSUSPEND);
115}
116
117static int op32_get_current_rxslot(struct b43_dmaring *ring)
118{
119 u32 val;
120
121 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
122 val &= B43_DMA32_RXDPTR;
123
124 return (val / sizeof(struct b43_dmadesc32));
125}
126
127static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
128{
129 b43_dma_write(ring, B43_DMA32_RXINDEX,
130 (u32) (slot * sizeof(struct b43_dmadesc32)));
131}
132
133static const struct b43_dma_ops dma32_ops = {
134 .idx2desc = op32_idx2desc,
135 .fill_descriptor = op32_fill_descriptor,
136 .poke_tx = op32_poke_tx,
137 .tx_suspend = op32_tx_suspend,
138 .tx_resume = op32_tx_resume,
139 .get_current_rxslot = op32_get_current_rxslot,
140 .set_current_rxslot = op32_set_current_rxslot,
141};
142
143/* 64bit DMA ops. */
144static
145struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
146 int slot,
147 struct b43_dmadesc_meta **meta)
148{
149 struct b43_dmadesc64 *desc;
150
151 *meta = &(ring->meta[slot]);
152 desc = ring->descbase;
153 desc = &(desc[slot]);
154
155 return (struct b43_dmadesc_generic *)desc;
156}
157
158static void op64_fill_descriptor(struct b43_dmaring *ring,
159 struct b43_dmadesc_generic *desc,
160 dma_addr_t dmaaddr, u16 bufsize,
161 int start, int end, int irq)
162{
163 struct b43_dmadesc64 *descbase = ring->descbase;
164 int slot;
165 u32 ctl0 = 0, ctl1 = 0;
166 u32 addrlo, addrhi;
167 u32 addrext;
168
169 slot = (int)(&(desc->dma64) - descbase);
170 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
171
172 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
173 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
174 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
175 >> SSB_DMA_TRANSLATION_SHIFT;
013978b6 176 addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
e4d6b795
MB		 177 if (slot == ring->nr_slots - 1)
178 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
179 if (start)
180 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
181 if (end)
182 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
183 if (irq)
184 ctl0 |= B43_DMA64_DCTL0_IRQ;
8eccb53f 185 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
e4d6b795
MB		 186 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
187 & B43_DMA64_DCTL1_ADDREXT_MASK;
188
189 desc->dma64.control0 = cpu_to_le32(ctl0);
190 desc->dma64.control1 = cpu_to_le32(ctl1);
191 desc->dma64.address_low = cpu_to_le32(addrlo);
192 desc->dma64.address_high = cpu_to_le32(addrhi);
193}
194
195static void op64_poke_tx(struct b43_dmaring *ring, int slot)
196{
197 b43_dma_write(ring, B43_DMA64_TXINDEX,
198 (u32) (slot * sizeof(struct b43_dmadesc64)));
199}
200
201static void op64_tx_suspend(struct b43_dmaring *ring)
202{
203 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
204 | B43_DMA64_TXSUSPEND);
205}
206
207static void op64_tx_resume(struct b43_dmaring *ring)
208{
209 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
210 & ~B43_DMA64_TXSUSPEND);
211}
212
213static int op64_get_current_rxslot(struct b43_dmaring *ring)
214{
215 u32 val;
216
217 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
218 val &= B43_DMA64_RXSTATDPTR;
219
220 return (val / sizeof(struct b43_dmadesc64));
221}
222
223static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
224{
225 b43_dma_write(ring, B43_DMA64_RXINDEX,
226 (u32) (slot * sizeof(struct b43_dmadesc64)));
227}
228
229static const struct b43_dma_ops dma64_ops = {
230 .idx2desc = op64_idx2desc,
231 .fill_descriptor = op64_fill_descriptor,
232 .poke_tx = op64_poke_tx,
233 .tx_suspend = op64_tx_suspend,
234 .tx_resume = op64_tx_resume,
235 .get_current_rxslot = op64_get_current_rxslot,
236 .set_current_rxslot = op64_set_current_rxslot,
237};
238
239static inline int free_slots(struct b43_dmaring *ring)
240{
241 return (ring->nr_slots - ring->used_slots);
242}
243
244static inline int next_slot(struct b43_dmaring *ring, int slot)
245{
246 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
247 if (slot == ring->nr_slots - 1)
248 return 0;
249 return slot + 1;
250}
251
252static inline int prev_slot(struct b43_dmaring *ring, int slot)
253{
254 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
255 if (slot == 0)
256 return ring->nr_slots - 1;
257 return slot - 1;
258}
259
260#ifdef CONFIG_B43_DEBUG
261static void update_max_used_slots(struct b43_dmaring *ring,
262 int current_used_slots)
263{
264 if (current_used_slots <= ring->max_used_slots)
265 return;
266 ring->max_used_slots = current_used_slots;
267 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
268 b43dbg(ring->dev->wl,
269 "max_used_slots increased to %d on %s ring %d\n",
270 ring->max_used_slots,
271 ring->tx ? "TX" : "RX", ring->index);
272 }
273}
274#else
275static inline
276 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
277{
278}
279#endif /* DEBUG */
280
281/* Request a slot for usage. */
282static inline int request_slot(struct b43_dmaring *ring)
283{
284 int slot;
285
286 B43_WARN_ON(!ring->tx);
287 B43_WARN_ON(ring->stopped);
288 B43_WARN_ON(free_slots(ring) == 0);
289
290 slot = next_slot(ring, ring->current_slot);
291 ring->current_slot = slot;
292 ring->used_slots++;
293
294 update_max_used_slots(ring, ring->used_slots);
295
296 return slot;
297}
298
b79caa68 299static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
e4d6b795
MB		 300{
301 static const u16 map64[] = {
302 B43_MMIO_DMA64_BASE0,
303 B43_MMIO_DMA64_BASE1,
304 B43_MMIO_DMA64_BASE2,
305 B43_MMIO_DMA64_BASE3,
306 B43_MMIO_DMA64_BASE4,
307 B43_MMIO_DMA64_BASE5,
308 };
309 static const u16 map32[] = {
310 B43_MMIO_DMA32_BASE0,
311 B43_MMIO_DMA32_BASE1,
312 B43_MMIO_DMA32_BASE2,
313 B43_MMIO_DMA32_BASE3,
314 B43_MMIO_DMA32_BASE4,
315 B43_MMIO_DMA32_BASE5,
316 };
317
b79caa68 318 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 319 B43_WARN_ON(!(controller_idx >= 0 &&
320 controller_idx < ARRAY_SIZE(map64)));
321 return map64[controller_idx];
322 }
323 B43_WARN_ON(!(controller_idx >= 0 &&
324 controller_idx < ARRAY_SIZE(map32)));
325 return map32[controller_idx];
326}
327
328static inline
329 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
330 unsigned char *buf, size_t len, int tx)
331{
332 dma_addr_t dmaaddr;
333
334 if (tx) {
f225763a
MB		 335 dmaaddr = ssb_dma_map_single(ring->dev->dev,
336 buf, len, DMA_TO_DEVICE);
e4d6b795 337 } else {
f225763a
MB		 338 dmaaddr = ssb_dma_map_single(ring->dev->dev,
339 buf, len, DMA_FROM_DEVICE);
e4d6b795
MB		 340 }
341
342 return dmaaddr;
343}
344
345static inline
346 void unmap_descbuffer(struct b43_dmaring *ring,
347 dma_addr_t addr, size_t len, int tx)
348{
349 if (tx) {
f225763a
MB		 350 ssb_dma_unmap_single(ring->dev->dev,
351 addr, len, DMA_TO_DEVICE);
e4d6b795 352 } else {
f225763a
MB		 353 ssb_dma_unmap_single(ring->dev->dev,
354 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 355 }
356}
357
358static inline
359 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
360 dma_addr_t addr, size_t len)
361{
362 B43_WARN_ON(ring->tx);
f225763a
MB		 363 ssb_dma_sync_single_for_cpu(ring->dev->dev,
364 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 365}
366
367static inline
368 void sync_descbuffer_for_device(struct b43_dmaring *ring,
369 dma_addr_t addr, size_t len)
370{
371 B43_WARN_ON(ring->tx);
f225763a
MB		 372 ssb_dma_sync_single_for_device(ring->dev->dev,
373 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 374}
375
376static inline
377 void free_descriptor_buffer(struct b43_dmaring *ring,
378 struct b43_dmadesc_meta *meta)
379{
380 if (meta->skb) {
381 dev_kfree_skb_any(meta->skb);
382 meta->skb = NULL;
383 }
384}
385
386static int alloc_ringmemory(struct b43_dmaring *ring)
387{
55afc80b
JL		 388 gfp_t flags = GFP_KERNEL;
389
390 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
391 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
392 * has shown that 4K is sufficient for the latter as long as the buffer
393 * does not cross an 8K boundary.
394 *
395 * For unknown reasons - possibly a hardware error - the BCM4311 rev
396 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
397 * which accounts for the GFP_DMA flag below.
398 *
399 * The flags here must match the flags in free_ringmemory below!
013978b6 400 */
b79caa68 401 if (ring->type == B43_DMA_64BIT)
55afc80b
JL		 402 flags |= GFP_DMA;
403 ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
404 B43_DMA_RINGMEMSIZE,
405 &(ring->dmabase), flags);
406 if (!ring->descbase) {
407 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
9bd568a5 408 return -ENOMEM;
e4d6b795 409 }
55afc80b 410 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
e4d6b795
MB		 411
412 return 0;
413}
414
415static void free_ringmemory(struct b43_dmaring *ring)
416{
55afc80b
JL		 417 gfp_t flags = GFP_KERNEL;
418
419 if (ring->type == B43_DMA_64BIT)
420 flags |= GFP_DMA;
421
422 ssb_dma_free_consistent(ring->dev->dev, B43_DMA_RINGMEMSIZE,
423 ring->descbase, ring->dmabase, flags);
e4d6b795
MB		 424}
425
426/* Reset the RX DMA channel */
b79caa68
MB		 427static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
428 enum b43_dmatype type)
e4d6b795
MB		 429{
430 int i;
431 u32 value;
432 u16 offset;
433
434 might_sleep();
435
b79caa68 436 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
e4d6b795
MB		 437 b43_write32(dev, mmio_base + offset, 0);
438 for (i = 0; i < 10; i++) {
b79caa68
MB		 439 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
440 B43_DMA32_RXSTATUS;
e4d6b795 441 value = b43_read32(dev, mmio_base + offset);
b79caa68 442 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 443 value &= B43_DMA64_RXSTAT;
444 if (value == B43_DMA64_RXSTAT_DISABLED) {
445 i = -1;
446 break;
447 }
448 } else {
449 value &= B43_DMA32_RXSTATE;
450 if (value == B43_DMA32_RXSTAT_DISABLED) {
451 i = -1;
452 break;
453 }
454 }
455 msleep(1);
456 }
457 if (i != -1) {
458 b43err(dev->wl, "DMA RX reset timed out\n");
459 return -ENODEV;
460 }
461
462 return 0;
463}
464
013978b6 465/* Reset the TX DMA channel */
b79caa68
MB		 466static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
467 enum b43_dmatype type)
e4d6b795
MB		 468{
469 int i;
470 u32 value;
471 u16 offset;
472
473 might_sleep();
474
475 for (i = 0; i < 10; i++) {
b79caa68
MB		 476 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
477 B43_DMA32_TXSTATUS;
e4d6b795 478 value = b43_read32(dev, mmio_base + offset);
b79caa68 479 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 480 value &= B43_DMA64_TXSTAT;
481 if (value == B43_DMA64_TXSTAT_DISABLED ||
482 value == B43_DMA64_TXSTAT_IDLEWAIT ||
483 value == B43_DMA64_TXSTAT_STOPPED)
484 break;
485 } else {
486 value &= B43_DMA32_TXSTATE;
487 if (value == B43_DMA32_TXSTAT_DISABLED ||
488 value == B43_DMA32_TXSTAT_IDLEWAIT ||
489 value == B43_DMA32_TXSTAT_STOPPED)
490 break;
491 }
492 msleep(1);
493 }
b79caa68 494 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
e4d6b795
MB		 495 b43_write32(dev, mmio_base + offset, 0);
496 for (i = 0; i < 10; i++) {
b79caa68
MB		 497 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
498 B43_DMA32_TXSTATUS;
e4d6b795 499 value = b43_read32(dev, mmio_base + offset);
b79caa68 500 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 501 value &= B43_DMA64_TXSTAT;
502 if (value == B43_DMA64_TXSTAT_DISABLED) {
503 i = -1;
504 break;
505 }
506 } else {
507 value &= B43_DMA32_TXSTATE;
508 if (value == B43_DMA32_TXSTAT_DISABLED) {
509 i = -1;
510 break;
511 }
512 }
513 msleep(1);
514 }
515 if (i != -1) {
516 b43err(dev->wl, "DMA TX reset timed out\n");
517 return -ENODEV;
518 }
519 /* ensure the reset is completed. */
520 msleep(1);
521
522 return 0;
523}
524
b79caa68
MB		 525/* Check if a DMA mapping address is invalid. */
526static bool b43_dma_mapping_error(struct b43_dmaring *ring,
527 dma_addr_t addr,
ffa9256a 528 size_t buffersize, bool dma_to_device)
b79caa68 529{
f225763a 530 if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
b79caa68
MB		 531 return 1;
532
55afc80b
JL		 533 switch (ring->type) {
534 case B43_DMA_30BIT:
535 if ((u64)addr + buffersize > (1ULL << 30))
536 goto address_error;
537 break;
538 case B43_DMA_32BIT:
539 if ((u64)addr + buffersize > (1ULL << 32))
540 goto address_error;
541 break;
542 case B43_DMA_64BIT:
543 /* Currently we can't have addresses beyond
544 * 64bit in the kernel. */
545 break;
b79caa68
MB		 546 }
547
548 /* The address is OK. */
549 return 0;
55afc80b
JL		 550
551address_error:
552 /* We can't support this address. Unmap it again. */
553 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
554
555 return 1;
b79caa68
MB		 556}
557
ec9a1d8c
MB		 558static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
559{
560 unsigned char *f = skb->data + ring->frameoffset;
561
562 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
563}
564
565static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
566{
567 struct b43_rxhdr_fw4 *rxhdr;
568 unsigned char *frame;
569
570 /* This poisons the RX buffer to detect DMA failures. */
571
572 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
573 rxhdr->frame_len = 0;
574
575 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
576 frame = skb->data + ring->frameoffset;
577 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
578}
579
e4d6b795
MB		 580static int setup_rx_descbuffer(struct b43_dmaring *ring,
581 struct b43_dmadesc_generic *desc,
582 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
583{
e4d6b795
MB		 584 dma_addr_t dmaaddr;
585 struct sk_buff *skb;
586
587 B43_WARN_ON(ring->tx);
588
589 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
590 if (unlikely(!skb))
591 return -ENOMEM;
ec9a1d8c 592 b43_poison_rx_buffer(ring, skb);
e4d6b795 593 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
ffa9256a 594 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
e4d6b795
MB		 595 /* ugh. try to realloc in zone_dma */
596 gfp_flags |= GFP_DMA;
597
598 dev_kfree_skb_any(skb);
599
600 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
601 if (unlikely(!skb))
602 return -ENOMEM;
ec9a1d8c 603 b43_poison_rx_buffer(ring, skb);
e4d6b795
MB		 604 dmaaddr = map_descbuffer(ring, skb->data,
605 ring->rx_buffersize, 0);
bdceeb2d
MB		 606 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
607 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
608 dev_kfree_skb_any(skb);
609 return -EIO;
610 }
e4d6b795
MB		 611 }
612
613 meta->skb = skb;
614 meta->dmaaddr = dmaaddr;
615 ring->ops->fill_descriptor(ring, desc, dmaaddr,
616 ring->rx_buffersize, 0, 0, 0);
617
e4d6b795
MB		 618 return 0;
619}
620
621/* Allocate the initial descbuffers.
622 * This is used for an RX ring only.
623 */
624static int alloc_initial_descbuffers(struct b43_dmaring *ring)
625{
626 int i, err = -ENOMEM;
627 struct b43_dmadesc_generic *desc;
628 struct b43_dmadesc_meta *meta;
629
630 for (i = 0; i < ring->nr_slots; i++) {
631 desc = ring->ops->idx2desc(ring, i, &meta);
632
633 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
634 if (err) {
635 b43err(ring->dev->wl,
636 "Failed to allocate initial descbuffers\n");
637 goto err_unwind;
638 }
639 }
640 mb();
641 ring->used_slots = ring->nr_slots;
642 err = 0;
643 out:
644 return err;
645
646 err_unwind:
647 for (i--; i >= 0; i--) {
648 desc = ring->ops->idx2desc(ring, i, &meta);
649
650 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
651 dev_kfree_skb(meta->skb);
652 }
653 goto out;
654}
655
656/* Do initial setup of the DMA controller.
657 * Reset the controller, write the ring busaddress
658 * and switch the "enable" bit on.
659 */
660static int dmacontroller_setup(struct b43_dmaring *ring)
661{
662 int err = 0;
663 u32 value;
664 u32 addrext;
665 u32 trans = ssb_dma_translation(ring->dev->dev);
666
667 if (ring->tx) {
b79caa68 668 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 669 u64 ringbase = (u64) (ring->dmabase);
670
671 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
672 >> SSB_DMA_TRANSLATION_SHIFT;
673 value = B43_DMA64_TXENABLE;
674 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
675 & B43_DMA64_TXADDREXT_MASK;
676 b43_dma_write(ring, B43_DMA64_TXCTL, value);
677 b43_dma_write(ring, B43_DMA64_TXRINGLO,
678 (ringbase & 0xFFFFFFFF));
679 b43_dma_write(ring, B43_DMA64_TXRINGHI,
680 ((ringbase >> 32) &
681 ~SSB_DMA_TRANSLATION_MASK)
013978b6 682 | (trans << 1));
e4d6b795
MB		 683 } else {
684 u32 ringbase = (u32) (ring->dmabase);
685
686 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
687 >> SSB_DMA_TRANSLATION_SHIFT;
688 value = B43_DMA32_TXENABLE;
689 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
690 & B43_DMA32_TXADDREXT_MASK;
691 b43_dma_write(ring, B43_DMA32_TXCTL, value);
692 b43_dma_write(ring, B43_DMA32_TXRING,
693 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
694 | trans);
695 }
696 } else {
697 err = alloc_initial_descbuffers(ring);
698 if (err)
699 goto out;
b79caa68 700 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 701 u64 ringbase = (u64) (ring->dmabase);
702
703 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
704 >> SSB_DMA_TRANSLATION_SHIFT;
705 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
706 value |= B43_DMA64_RXENABLE;
707 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
708 & B43_DMA64_RXADDREXT_MASK;
709 b43_dma_write(ring, B43_DMA64_RXCTL, value);
710 b43_dma_write(ring, B43_DMA64_RXRINGLO,
711 (ringbase & 0xFFFFFFFF));
712 b43_dma_write(ring, B43_DMA64_RXRINGHI,
713 ((ringbase >> 32) &
714 ~SSB_DMA_TRANSLATION_MASK)
013978b6
LF		 715 | (trans << 1));
716 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
717 sizeof(struct b43_dmadesc64));
e4d6b795
MB		 718 } else {
719 u32 ringbase = (u32) (ring->dmabase);
720
721 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
722 >> SSB_DMA_TRANSLATION_SHIFT;
723 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
724 value |= B43_DMA32_RXENABLE;
725 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
726 & B43_DMA32_RXADDREXT_MASK;
727 b43_dma_write(ring, B43_DMA32_RXCTL, value);
728 b43_dma_write(ring, B43_DMA32_RXRING,
729 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
730 | trans);
013978b6
LF		 731 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
732 sizeof(struct b43_dmadesc32));
e4d6b795
MB		 733 }
734 }
735
013978b6 736out:
e4d6b795
MB		 737 return err;
738}
739
740/* Shutdown the DMA controller. */
741static void dmacontroller_cleanup(struct b43_dmaring *ring)
742{
743 if (ring->tx) {
744 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 745 ring->type);
746 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 747 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
748 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
749 } else
750 b43_dma_write(ring, B43_DMA32_TXRING, 0);
751 } else {
752 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 753 ring->type);
754 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 755 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
756 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
757 } else
758 b43_dma_write(ring, B43_DMA32_RXRING, 0);
759 }
760}
761
762static void free_all_descbuffers(struct b43_dmaring *ring)
763{
764 struct b43_dmadesc_generic *desc;
765 struct b43_dmadesc_meta *meta;
766 int i;
767
768 if (!ring->used_slots)
769 return;
770 for (i = 0; i < ring->nr_slots; i++) {
771 desc = ring->ops->idx2desc(ring, i, &meta);
772
07681e21 773 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
e4d6b795
MB		 774 B43_WARN_ON(!ring->tx);
775 continue;
776 }
777 if (ring->tx) {
778 unmap_descbuffer(ring, meta->dmaaddr,
779 meta->skb->len, 1);
780 } else {
781 unmap_descbuffer(ring, meta->dmaaddr,
782 ring->rx_buffersize, 0);
783 }
784 free_descriptor_buffer(ring, meta);
785 }
786}
787
788static u64 supported_dma_mask(struct b43_wldev *dev)
789{
790 u32 tmp;
791 u16 mmio_base;
792
793 tmp = b43_read32(dev, SSB_TMSHIGH);
794 if (tmp & SSB_TMSHIGH_DMA64)
6a35528a 795 return DMA_BIT_MASK(64);
e4d6b795
MB		 796 mmio_base = b43_dmacontroller_base(0, 0);
797 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
798 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
799 if (tmp & B43_DMA32_TXADDREXT_MASK)
284901a9 800 return DMA_BIT_MASK(32);
e4d6b795 801
28b76796 802 return DMA_BIT_MASK(30);
e4d6b795
MB		 803}
804
5100d5ac
MB		 805static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
806{
28b76796 807 if (dmamask == DMA_BIT_MASK(30))
5100d5ac 808 return B43_DMA_30BIT;
284901a9 809 if (dmamask == DMA_BIT_MASK(32))
5100d5ac 810 return B43_DMA_32BIT;
6a35528a 811 if (dmamask == DMA_BIT_MASK(64))
5100d5ac
MB		 812 return B43_DMA_64BIT;
813 B43_WARN_ON(1);
814 return B43_DMA_30BIT;
815}
816
e4d6b795
MB		 817/* Main initialization function. */
818static
819struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
820 int controller_index,
b79caa68
MB		 821 int for_tx,
822 enum b43_dmatype type)
e4d6b795
MB		 823{
824 struct b43_dmaring *ring;
07681e21 825 int i, err;
e4d6b795
MB		 826 dma_addr_t dma_test;
827
828 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
829 if (!ring)
830 goto out;
831
028118a5 832 ring->nr_slots = B43_RXRING_SLOTS;
e4d6b795 833 if (for_tx)
028118a5 834 ring->nr_slots = B43_TXRING_SLOTS;
e4d6b795 835
028118a5 836 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
e4d6b795
MB		 837 GFP_KERNEL);
838 if (!ring->meta)
839 goto err_kfree_ring;
07681e21
MB		 840 for (i = 0; i < ring->nr_slots; i++)
841 ring->meta->skb = B43_DMA_PTR_POISON;
028118a5
MB		 842
843 ring->type = type;
844 ring->dev = dev;
845 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
846 ring->index = controller_index;
847 if (type == B43_DMA_64BIT)
848 ring->ops = &dma64_ops;
849 else
850 ring->ops = &dma32_ops;
e4d6b795 851 if (for_tx) {
028118a5
MB		 852 ring->tx = 1;
853 ring->current_slot = -1;
854 } else {
855 if (ring->index == 0) {
856 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
857 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
028118a5
MB		 858 } else
859 B43_WARN_ON(1);
860 }
028118a5
MB		 861#ifdef CONFIG_B43_DEBUG
862 ring->last_injected_overflow = jiffies;
863#endif
864
865 if (for_tx) {
2d071ca5
MB		 866 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
867 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
868
bdceeb2d 869 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
eb189d8b 870 b43_txhdr_size(dev),
e4d6b795
MB		 871 GFP_KERNEL);
872 if (!ring->txhdr_cache)
873 goto err_kfree_meta;
874
875 /* test for ability to dma to txhdr_cache */
f225763a
MB		 876 dma_test = ssb_dma_map_single(dev->dev,
877 ring->txhdr_cache,
878 b43_txhdr_size(dev),
879 DMA_TO_DEVICE);
e4d6b795 880
ffa9256a
MB		 881 if (b43_dma_mapping_error(ring, dma_test,
882 b43_txhdr_size(dev), 1)) {
e4d6b795
MB		 883 /* ugh realloc */
884 kfree(ring->txhdr_cache);
bdceeb2d 885 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
eb189d8b 886 b43_txhdr_size(dev),
e4d6b795
MB		 887 GFP_KERNEL | GFP_DMA);
888 if (!ring->txhdr_cache)
889 goto err_kfree_meta;
890
f225763a
MB		 891 dma_test = ssb_dma_map_single(dev->dev,
892 ring->txhdr_cache,
893 b43_txhdr_size(dev),
894 DMA_TO_DEVICE);
e4d6b795 895
b79caa68 896 if (b43_dma_mapping_error(ring, dma_test,
539e6f8c
MB		 897 b43_txhdr_size(dev), 1)) {
898
899 b43err(dev->wl,
900 "TXHDR DMA allocation failed\n");
e4d6b795 901 goto err_kfree_txhdr_cache;
539e6f8c 902 }
e4d6b795
MB		 903 }
904
f225763a
MB		 905 ssb_dma_unmap_single(dev->dev,
906 dma_test, b43_txhdr_size(dev),
907 DMA_TO_DEVICE);
e4d6b795
MB		 908 }
909
e4d6b795
MB		 910 err = alloc_ringmemory(ring);
911 if (err)
912 goto err_kfree_txhdr_cache;
913 err = dmacontroller_setup(ring);
914 if (err)
915 goto err_free_ringmemory;
916
917 out:
918 return ring;
919
920 err_free_ringmemory:
921 free_ringmemory(ring);
922 err_kfree_txhdr_cache:
923 kfree(ring->txhdr_cache);
924 err_kfree_meta:
925 kfree(ring->meta);
926 err_kfree_ring:
927 kfree(ring);
928 ring = NULL;
929 goto out;
930}
931
57df40d2
MB		 932#define divide(a, b) ({ \
933 typeof(a) __a = a; \
934 do_div(__a, b); \
935 __a; \
936 })
937
938#define modulo(a, b) ({ \
939 typeof(a) __a = a; \
940 do_div(__a, b); \
941 })
942
e4d6b795 943/* Main cleanup function. */
b27faf8e
MB		 944static void b43_destroy_dmaring(struct b43_dmaring *ring,
945 const char *ringname)
e4d6b795
MB		 946{
947 if (!ring)
948 return;
949
57df40d2
MB		 950#ifdef CONFIG_B43_DEBUG
951 {
952 /* Print some statistics. */
953 u64 failed_packets = ring->nr_failed_tx_packets;
954 u64 succeed_packets = ring->nr_succeed_tx_packets;
955 u64 nr_packets = failed_packets + succeed_packets;
956 u64 permille_failed = 0, average_tries = 0;
957
958 if (nr_packets)
959 permille_failed = divide(failed_packets * 1000, nr_packets);
960 if (nr_packets)
961 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
962
963 b43dbg(ring->dev->wl, "DMA-%u %s: "
964 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
965 "Average tries %llu.%02llu\n",
966 (unsigned int)(ring->type), ringname,
967 ring->max_used_slots,
968 ring->nr_slots,
969 (unsigned long long)failed_packets,
87d96114 970 (unsigned long long)nr_packets,
57df40d2
MB		 971 (unsigned long long)divide(permille_failed, 10),
972 (unsigned long long)modulo(permille_failed, 10),
973 (unsigned long long)divide(average_tries, 100),
974 (unsigned long long)modulo(average_tries, 100));
975 }
976#endif /* DEBUG */
977
e4d6b795
MB		 978 /* Device IRQs are disabled prior entering this function,
979 * so no need to take care of concurrency with rx handler stuff.
980 */
981 dmacontroller_cleanup(ring);
982 free_all_descbuffers(ring);
983 free_ringmemory(ring);
984
985 kfree(ring->txhdr_cache);
986 kfree(ring->meta);
987 kfree(ring);
988}
989
b27faf8e
MB		 990#define destroy_ring(dma, ring) do { \
991 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
992 (dma)->ring = NULL; \
993 } while (0)
994
e4d6b795
MB		 995void b43_dma_free(struct b43_wldev *dev)
996{
5100d5ac
MB		 997 struct b43_dma *dma;
998
999 if (b43_using_pio_transfers(dev))
1000 return;
1001 dma = &dev->dma;
e4d6b795 1002
b27faf8e
MB		 1003 destroy_ring(dma, rx_ring);
1004 destroy_ring(dma, tx_ring_AC_BK);
1005 destroy_ring(dma, tx_ring_AC_BE);
1006 destroy_ring(dma, tx_ring_AC_VI);
1007 destroy_ring(dma, tx_ring_AC_VO);
1008 destroy_ring(dma, tx_ring_mcast);
e4d6b795
MB		 1009}
1010
1033b3ea
MB		 1011static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1012{
1013 u64 orig_mask = mask;
1014 bool fallback = 0;
1015 int err;
1016
1017 /* Try to set the DMA mask. If it fails, try falling back to a
1018 * lower mask, as we can always also support a lower one. */
1019 while (1) {
1020 err = ssb_dma_set_mask(dev->dev, mask);
1021 if (!err)
1022 break;
6a35528a 1023 if (mask == DMA_BIT_MASK(64)) {
284901a9 1024 mask = DMA_BIT_MASK(32);
1033b3ea
MB		 1025 fallback = 1;
1026 continue;
1027 }
284901a9 1028 if (mask == DMA_BIT_MASK(32)) {
28b76796 1029 mask = DMA_BIT_MASK(30);
1033b3ea
MB		 1030 fallback = 1;
1031 continue;
1032 }
1033 b43err(dev->wl, "The machine/kernel does not support "
1034 "the required %u-bit DMA mask\n",
1035 (unsigned int)dma_mask_to_engine_type(orig_mask));
1036 return -EOPNOTSUPP;
1037 }
1038 if (fallback) {
1039 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1040 (unsigned int)dma_mask_to_engine_type(orig_mask),
1041 (unsigned int)dma_mask_to_engine_type(mask));
1042 }
1043
1044 return 0;
1045}
1046
e4d6b795
MB		 1047int b43_dma_init(struct b43_wldev *dev)
1048{
1049 struct b43_dma *dma = &dev->dma;
e4d6b795
MB		 1050 int err;
1051 u64 dmamask;
b79caa68 1052 enum b43_dmatype type;
e4d6b795
MB		 1053
1054 dmamask = supported_dma_mask(dev);
5100d5ac 1055 type = dma_mask_to_engine_type(dmamask);
1033b3ea
MB		 1056 err = b43_dma_set_mask(dev, dmamask);
1057 if (err)
1058 return err;
e4d6b795
MB		 1059
1060 err = -ENOMEM;
1061 /* setup TX DMA channels. */
b27faf8e
MB		 1062 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1063 if (!dma->tx_ring_AC_BK)
e4d6b795 1064 goto out;
e4d6b795 1065
b27faf8e
MB		 1066 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1067 if (!dma->tx_ring_AC_BE)
1068 goto err_destroy_bk;
e4d6b795 1069
b27faf8e
MB		 1070 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1071 if (!dma->tx_ring_AC_VI)
1072 goto err_destroy_be;
e4d6b795 1073
b27faf8e
MB		 1074 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1075 if (!dma->tx_ring_AC_VO)
1076 goto err_destroy_vi;
e4d6b795 1077
b27faf8e
MB		 1078 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1079 if (!dma->tx_ring_mcast)
1080 goto err_destroy_vo;
e4d6b795 1081
b27faf8e
MB		 1082 /* setup RX DMA channel. */
1083 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1084 if (!dma->rx_ring)
1085 goto err_destroy_mcast;
e4d6b795 1086
b27faf8e
MB		 1087 /* No support for the TX status DMA ring. */
1088 B43_WARN_ON(dev->dev->id.revision < 5);
e4d6b795 1089
b79caa68
MB		 1090 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1091 (unsigned int)type);
e4d6b795 1092 err = 0;
b27faf8e 1093out:
e4d6b795
MB		 1094 return err;
1095
b27faf8e
MB		 1096err_destroy_mcast:
1097 destroy_ring(dma, tx_ring_mcast);
1098err_destroy_vo:
1099 destroy_ring(dma, tx_ring_AC_VO);
1100err_destroy_vi:
1101 destroy_ring(dma, tx_ring_AC_VI);
1102err_destroy_be:
1103 destroy_ring(dma, tx_ring_AC_BE);
1104err_destroy_bk:
1105 destroy_ring(dma, tx_ring_AC_BK);
1106 return err;
e4d6b795
MB		 1107}
1108
1109/* Generate a cookie for the TX header. */
1110static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1111{
b27faf8e 1112 u16 cookie;
e4d6b795
MB		 1113
1114 /* Use the upper 4 bits of the cookie as
1115 * DMA controller ID and store the slot number
1116 * in the lower 12 bits.
1117 * Note that the cookie must never be 0, as this
1118 * is a special value used in RX path.
280d0e16
MB		 1119 * It can also not be 0xFFFF because that is special
1120 * for multicast frames.
e4d6b795 1121 */
b27faf8e 1122 cookie = (((u16)ring->index + 1) << 12);
e4d6b795 1123 B43_WARN_ON(slot & ~0x0FFF);
b27faf8e 1124 cookie |= (u16)slot;
e4d6b795
MB		 1125
1126 return cookie;
1127}
1128
1129/* Inspect a cookie and find out to which controller/slot it belongs. */
1130static
1131struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1132{
1133 struct b43_dma *dma = &dev->dma;
1134 struct b43_dmaring *ring = NULL;
1135
1136 switch (cookie & 0xF000) {
280d0e16 1137 case 0x1000:
b27faf8e 1138 ring = dma->tx_ring_AC_BK;
e4d6b795 1139 break;
280d0e16 1140 case 0x2000:
b27faf8e 1141 ring = dma->tx_ring_AC_BE;
e4d6b795 1142 break;
280d0e16 1143 case 0x3000:
b27faf8e 1144 ring = dma->tx_ring_AC_VI;
e4d6b795 1145 break;
280d0e16 1146 case 0x4000:
b27faf8e 1147 ring = dma->tx_ring_AC_VO;
e4d6b795 1148 break;
280d0e16 1149 case 0x5000:
b27faf8e 1150 ring = dma->tx_ring_mcast;
e4d6b795 1151 break;
e4d6b795
MB		 1152 }
1153 *slot = (cookie & 0x0FFF);
07681e21
MB		 1154 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1155 b43dbg(dev->wl, "TX-status contains "
1156 "invalid cookie: 0x%04X\n", cookie);
1157 return NULL;
1158 }
e4d6b795
MB		 1159
1160 return ring;
1161}
1162
1163static int dma_tx_fragment(struct b43_dmaring *ring,
f54a5202 1164 struct sk_buff *skb)
e4d6b795
MB		 1165{
1166 const struct b43_dma_ops *ops = ring->ops;
e039fa4a 1167 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f54a5202 1168 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
e4d6b795 1169 u8 *header;
09552ccd 1170 int slot, old_top_slot, old_used_slots;
e4d6b795
MB		 1171 int err;
1172 struct b43_dmadesc_generic *desc;
1173 struct b43_dmadesc_meta *meta;
1174 struct b43_dmadesc_meta *meta_hdr;
280d0e16 1175 u16 cookie;
eb189d8b 1176 size_t hdrsize = b43_txhdr_size(ring->dev);
e4d6b795 1177
bdceeb2d
MB		 1178 /* Important note: If the number of used DMA slots per TX frame
1179 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1180 * the file has to be updated, too!
1181 */
e4d6b795 1182
09552ccd
MB		 1183 old_top_slot = ring->current_slot;
1184 old_used_slots = ring->used_slots;
1185
e4d6b795
MB		 1186 /* Get a slot for the header. */
1187 slot = request_slot(ring);
1188 desc = ops->idx2desc(ring, slot, &meta_hdr);
1189 memset(meta_hdr, 0, sizeof(*meta_hdr));
1190
bdceeb2d 1191 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
280d0e16 1192 cookie = generate_cookie(ring, slot);
09552ccd 1193 err = b43_generate_txhdr(ring->dev, header,
035d0243 1194 skb, info, cookie);
09552ccd
MB		 1195 if (unlikely(err)) {
1196 ring->current_slot = old_top_slot;
1197 ring->used_slots = old_used_slots;
1198 return err;
1199 }
e4d6b795
MB		 1200
1201 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
eb189d8b 1202 hdrsize, 1);
ffa9256a 1203 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
09552ccd
MB		 1204 ring->current_slot = old_top_slot;
1205 ring->used_slots = old_used_slots;
e4d6b795 1206 return -EIO;
09552ccd 1207 }
e4d6b795 1208 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
eb189d8b 1209 hdrsize, 1, 0, 0);
e4d6b795
MB		 1210
1211 /* Get a slot for the payload. */
1212 slot = request_slot(ring);
1213 desc = ops->idx2desc(ring, slot, &meta);
1214 memset(meta, 0, sizeof(*meta));
1215
e4d6b795
MB		 1216 meta->skb = skb;
1217 meta->is_last_fragment = 1;
f54a5202 1218 priv_info->bouncebuffer = NULL;
e4d6b795
MB		 1219
1220 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1221 /* create a bounce buffer in zone_dma on mapping failure. */
ffa9256a 1222 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
f54a5202
MB		 1223 priv_info->bouncebuffer = kmalloc(skb->len, GFP_ATOMIC | GFP_DMA);
1224 if (!priv_info->bouncebuffer) {
09552ccd
MB		 1225 ring->current_slot = old_top_slot;
1226 ring->used_slots = old_used_slots;
e4d6b795
MB		 1227 err = -ENOMEM;
1228 goto out_unmap_hdr;
1229 }
f54a5202 1230 memcpy(priv_info->bouncebuffer, skb->data, skb->len);
e4d6b795 1231
f54a5202 1232 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
ffa9256a 1233 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
f54a5202
MB		 1234 kfree(priv_info->bouncebuffer);
1235 priv_info->bouncebuffer = NULL;
09552ccd
MB		 1236 ring->current_slot = old_top_slot;
1237 ring->used_slots = old_used_slots;
e4d6b795 1238 err = -EIO;
f54a5202 1239 goto out_unmap_hdr;
e4d6b795
MB		 1240 }
1241 }
1242
1243 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1244
e039fa4a 1245 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
280d0e16
MB		 1246 /* Tell the firmware about the cookie of the last
1247 * mcast frame, so it can clear the more-data bit in it. */
1248 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1249 B43_SHM_SH_MCASTCOOKIE, cookie);
1250 }
e4d6b795
MB		 1251 /* Now transfer the whole frame. */
1252 wmb();
1253 ops->poke_tx(ring, next_slot(ring, slot));
1254 return 0;
1255
280d0e16 1256out_unmap_hdr:
e4d6b795 1257 unmap_descbuffer(ring, meta_hdr->dmaaddr,
eb189d8b 1258 hdrsize, 1);
e4d6b795
MB		 1259 return err;
1260}
1261
1262static inline int should_inject_overflow(struct b43_dmaring *ring)
1263{
1264#ifdef CONFIG_B43_DEBUG
1265 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1266 /* Check if we should inject another ringbuffer overflow
1267 * to test handling of this situation in the stack. */
1268 unsigned long next_overflow;
1269
1270 next_overflow = ring->last_injected_overflow + HZ;
1271 if (time_after(jiffies, next_overflow)) {
1272 ring->last_injected_overflow = jiffies;
1273 b43dbg(ring->dev->wl,
1274 "Injecting TX ring overflow on "
1275 "DMA controller %d\n", ring->index);
1276 return 1;
1277 }
1278 }
1279#endif /* CONFIG_B43_DEBUG */
1280 return 0;
1281}
1282
e6f5b934 1283/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
99da185a
JD		 1284static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1285 u8 queue_prio)
e6f5b934
MB		 1286{
1287 struct b43_dmaring *ring;
1288
403a3a13 1289 if (dev->qos_enabled) {
e6f5b934
MB		 1290 /* 0 = highest priority */
1291 switch (queue_prio) {
1292 default:
1293 B43_WARN_ON(1);
1294 /* fallthrough */
1295 case 0:
b27faf8e 1296 ring = dev->dma.tx_ring_AC_VO;
e6f5b934
MB		 1297 break;
1298 case 1:
b27faf8e 1299 ring = dev->dma.tx_ring_AC_VI;
e6f5b934
MB		 1300 break;
1301 case 2:
b27faf8e 1302 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1303 break;
1304 case 3:
b27faf8e 1305 ring = dev->dma.tx_ring_AC_BK;
e6f5b934
MB		 1306 break;
1307 }
1308 } else
b27faf8e 1309 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1310
1311 return ring;
1312}
1313
e039fa4a 1314int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
e4d6b795
MB		 1315{
1316 struct b43_dmaring *ring;
280d0e16 1317 struct ieee80211_hdr *hdr;
e4d6b795 1318 int err = 0;
e039fa4a 1319 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e4d6b795 1320
280d0e16 1321 hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 1322 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
280d0e16 1323 /* The multicast ring will be sent after the DTIM */
b27faf8e 1324 ring = dev->dma.tx_ring_mcast;
280d0e16
MB		 1325 /* Set the more-data bit. Ucode will clear it on
1326 * the last frame for us. */
1327 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1328 } else {
1329 /* Decide by priority where to put this frame. */
e2530083
JB		 1330 ring = select_ring_by_priority(
1331 dev, skb_get_queue_mapping(skb));
280d0e16
MB		 1332 }
1333
e4d6b795 1334 B43_WARN_ON(!ring->tx);
ca2d559e 1335
18c69510
LF		 1336 if (unlikely(ring->stopped)) {
1337 /* We get here only because of a bug in mac80211.
1338 * Because of a race, one packet may be queued after
1339 * the queue is stopped, thus we got called when we shouldn't.
1340 * For now, just refuse the transmit. */
1341 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1342 b43err(dev->wl, "Packet after queue stopped\n");
1343 err = -ENOSPC;
637dae3f 1344 goto out;
18c69510
LF		 1345 }
1346
1347 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1348 /* If we get here, we have a real error with the queue
1349 * full, but queues not stopped. */
1350 b43err(dev->wl, "DMA queue overflow\n");
e4d6b795 1351 err = -ENOSPC;
637dae3f 1352 goto out;
e4d6b795 1353 }
e4d6b795 1354
e6f5b934
MB		 1355 /* Assign the queue number to the ring (if not already done before)
1356 * so TX status handling can use it. The queue to ring mapping is
1357 * static, so we don't need to store it per frame. */
e2530083 1358 ring->queue_prio = skb_get_queue_mapping(skb);
e6f5b934 1359
f54a5202 1360 err = dma_tx_fragment(ring, skb);
09552ccd
MB		 1361 if (unlikely(err == -ENOKEY)) {
1362 /* Drop this packet, as we don't have the encryption key
1363 * anymore and must not transmit it unencrypted. */
1364 dev_kfree_skb_any(skb);
1365 err = 0;
637dae3f 1366 goto out;
09552ccd 1367 }
e4d6b795
MB		 1368 if (unlikely(err)) {
1369 b43err(dev->wl, "DMA tx mapping failure\n");
637dae3f 1370 goto out;
e4d6b795 1371 }
bdceeb2d 1372 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
e4d6b795
MB		 1373 should_inject_overflow(ring)) {
1374 /* This TX ring is full. */
e2530083 1375 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
e4d6b795
MB		 1376 ring->stopped = 1;
1377 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1378 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1379 }
1380 }
637dae3f 1381out:
e4d6b795
MB		 1382
1383 return err;
1384}
1385
1386void b43_dma_handle_txstatus(struct b43_wldev *dev,
1387 const struct b43_txstatus *status)
1388{
1389 const struct b43_dma_ops *ops;
1390 struct b43_dmaring *ring;
1391 struct b43_dmadesc_generic *desc;
1392 struct b43_dmadesc_meta *meta;
07681e21 1393 int slot, firstused;
5100d5ac 1394 bool frame_succeed;
e4d6b795
MB		 1395
1396 ring = parse_cookie(dev, status->cookie, &slot);
1397 if (unlikely(!ring))
1398 return;
e4d6b795 1399 B43_WARN_ON(!ring->tx);
07681e21
MB		 1400
1401 /* Sanity check: TX packets are processed in-order on one ring.
1402 * Check if the slot deduced from the cookie really is the first
1403 * used slot. */
1404 firstused = ring->current_slot - ring->used_slots + 1;
1405 if (firstused < 0)
1406 firstused = ring->nr_slots + firstused;
1407 if (unlikely(slot != firstused)) {
1408 /* This possibly is a firmware bug and will result in
1409 * malfunction, memory leaks and/or stall of DMA functionality. */
1410 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1411 "Expected %d, but got %d\n",
1412 ring->index, firstused, slot);
1413 return;
1414 }
1415
e4d6b795
MB		 1416 ops = ring->ops;
1417 while (1) {
07681e21 1418 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
e4d6b795
MB		 1419 desc = ops->idx2desc(ring, slot, &meta);
1420
07681e21
MB		 1421 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1422 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1423 "on ring %d\n",
1424 slot, firstused, ring->index);
1425 break;
1426 }
f54a5202
MB		 1427 if (meta->skb) {
1428 struct b43_private_tx_info *priv_info =
1429 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1430
1431 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1432 kfree(priv_info->bouncebuffer);
1433 priv_info->bouncebuffer = NULL;
1434 } else {
e4d6b795 1435 unmap_descbuffer(ring, meta->dmaaddr,
eb189d8b 1436 b43_txhdr_size(dev), 1);
f54a5202 1437 }
e4d6b795
MB		 1438
1439 if (meta->is_last_fragment) {
e039fa4a
JB		 1440 struct ieee80211_tx_info *info;
1441
07681e21
MB		 1442 if (unlikely(!meta->skb)) {
1443 /* This is a scatter-gather fragment of a frame, so
1444 * the skb pointer must not be NULL. */
1445 b43dbg(dev->wl, "TX status unexpected NULL skb "
1446 "at slot %d (first=%d) on ring %d\n",
1447 slot, firstused, ring->index);
1448 break;
1449 }
e039fa4a
JB		 1450
1451 info = IEEE80211_SKB_CB(meta->skb);
1452
e039fa4a
JB		 1453 /*
1454 * Call back to inform the ieee80211 subsystem about
1455 * the status of the transmission.
e4d6b795 1456 */
e6a9854b 1457 frame_succeed = b43_fill_txstatus_report(dev, info, status);
5100d5ac
MB		 1458#ifdef CONFIG_B43_DEBUG
1459 if (frame_succeed)
1460 ring->nr_succeed_tx_packets++;
1461 else
1462 ring->nr_failed_tx_packets++;
1463 ring->nr_total_packet_tries += status->frame_count;
1464#endif /* DEBUG */
ce6c4a13 1465 ieee80211_tx_status(dev->wl->hw, meta->skb);
e039fa4a 1466
07681e21
MB		 1467 /* skb will be freed by ieee80211_tx_status().
1468 * Poison our pointer. */
1469 meta->skb = B43_DMA_PTR_POISON;
e4d6b795
MB		 1470 } else {
1471 /* No need to call free_descriptor_buffer here, as
1472 * this is only the txhdr, which is not allocated.
1473 */
07681e21
MB		 1474 if (unlikely(meta->skb)) {
1475 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1476 "at slot %d (first=%d) on ring %d\n",
1477 slot, firstused, ring->index);
1478 break;
1479 }
e4d6b795
MB		 1480 }
1481
1482 /* Everything unmapped and free'd. So it's not used anymore. */
1483 ring->used_slots--;
1484
07681e21
MB		 1485 if (meta->is_last_fragment) {
1486 /* This is the last scatter-gather
1487 * fragment of the frame. We are done. */
e4d6b795 1488 break;
07681e21 1489 }
e4d6b795
MB		 1490 slot = next_slot(ring, slot);
1491 }
e4d6b795 1492 if (ring->stopped) {
bdceeb2d 1493 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
e6f5b934 1494 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
e4d6b795
MB		 1495 ring->stopped = 0;
1496 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1497 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1498 }
1499 }
e4d6b795
MB		 1500}
1501
e4d6b795
MB		 1502static void dma_rx(struct b43_dmaring *ring, int *slot)
1503{
1504 const struct b43_dma_ops *ops = ring->ops;
1505 struct b43_dmadesc_generic *desc;
1506 struct b43_dmadesc_meta *meta;
1507 struct b43_rxhdr_fw4 *rxhdr;
1508 struct sk_buff *skb;
1509 u16 len;
1510 int err;
1511 dma_addr_t dmaaddr;
1512
1513 desc = ops->idx2desc(ring, *slot, &meta);
1514
1515 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1516 skb = meta->skb;
1517
e4d6b795
MB		 1518 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1519 len = le16_to_cpu(rxhdr->frame_len);
1520 if (len == 0) {
1521 int i = 0;
1522
1523 do {
1524 udelay(2);
1525 barrier();
1526 len = le16_to_cpu(rxhdr->frame_len);
1527 } while (len == 0 && i++ < 5);
1528 if (unlikely(len == 0)) {
cf68636a
MB		 1529 dmaaddr = meta->dmaaddr;
1530 goto drop_recycle_buffer;
e4d6b795
MB		 1531 }
1532 }
ec9a1d8c
MB		 1533 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1534 /* Something went wrong with the DMA.
1535 * The device did not touch the buffer and did not overwrite the poison. */
1536 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
cf68636a
MB		 1537 dmaaddr = meta->dmaaddr;
1538 goto drop_recycle_buffer;
ec9a1d8c 1539 }
e4d6b795
MB		 1540 if (unlikely(len > ring->rx_buffersize)) {
1541 /* The data did not fit into one descriptor buffer
1542 * and is split over multiple buffers.
1543 * This should never happen, as we try to allocate buffers
1544 * big enough. So simply ignore this packet.
1545 */
1546 int cnt = 0;
1547 s32 tmp = len;
1548
1549 while (1) {
1550 desc = ops->idx2desc(ring, *slot, &meta);
1551 /* recycle the descriptor buffer. */
cf68636a 1552 b43_poison_rx_buffer(ring, meta->skb);
e4d6b795
MB		 1553 sync_descbuffer_for_device(ring, meta->dmaaddr,
1554 ring->rx_buffersize);
1555 *slot = next_slot(ring, *slot);
1556 cnt++;
1557 tmp -= ring->rx_buffersize;
1558 if (tmp <= 0)
1559 break;
1560 }
1561 b43err(ring->dev->wl, "DMA RX buffer too small "
1562 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1563 len, ring->rx_buffersize, cnt);
1564 goto drop;
1565 }
1566
1567 dmaaddr = meta->dmaaddr;
1568 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1569 if (unlikely(err)) {
1570 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
cf68636a 1571 goto drop_recycle_buffer;
e4d6b795
MB		 1572 }
1573
1574 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1575 skb_put(skb, len + ring->frameoffset);
1576 skb_pull(skb, ring->frameoffset);
1577
1578 b43_rx(ring->dev, skb, rxhdr);
b27faf8e 1579drop:
e4d6b795 1580 return;
cf68636a
MB		 1581
1582drop_recycle_buffer:
1583 /* Poison and recycle the RX buffer. */
1584 b43_poison_rx_buffer(ring, skb);
1585 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
e4d6b795
MB		 1586}
1587
1588void b43_dma_rx(struct b43_dmaring *ring)
1589{
1590 const struct b43_dma_ops *ops = ring->ops;
1591 int slot, current_slot;
1592 int used_slots = 0;
1593
1594 B43_WARN_ON(ring->tx);
1595 current_slot = ops->get_current_rxslot(ring);
1596 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1597
1598 slot = ring->current_slot;
1599 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1600 dma_rx(ring, &slot);
1601 update_max_used_slots(ring, ++used_slots);
1602 }
1603 ops->set_current_rxslot(ring, slot);
1604 ring->current_slot = slot;
1605}
1606
1607static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1608{
e4d6b795
MB		 1609 B43_WARN_ON(!ring->tx);
1610 ring->ops->tx_suspend(ring);
e4d6b795
MB		 1611}
1612
1613static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1614{
e4d6b795
MB		 1615 B43_WARN_ON(!ring->tx);
1616 ring->ops->tx_resume(ring);
e4d6b795
MB		 1617}
1618
1619void b43_dma_tx_suspend(struct b43_wldev *dev)
1620{
1621 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
b27faf8e
MB		 1622 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1623 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1624 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1625 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1626 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
e4d6b795
MB		 1627}
1628
1629void b43_dma_tx_resume(struct b43_wldev *dev)
1630{
b27faf8e
MB		 1631 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1632 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1633 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1634 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1635 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
e4d6b795
MB		 1636 b43_power_saving_ctl_bits(dev, 0);
1637}
5100d5ac 1638
5100d5ac
MB		 1639static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1640 u16 mmio_base, bool enable)
1641{
1642 u32 ctl;
1643
1644 if (type == B43_DMA_64BIT) {
1645 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1646 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1647 if (enable)
1648 ctl |= B43_DMA64_RXDIRECTFIFO;
1649 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1650 } else {
1651 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1652 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1653 if (enable)
1654 ctl |= B43_DMA32_RXDIRECTFIFO;
1655 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1656 }
1657}
1658
1659/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1660 * This is called from PIO code, so DMA structures are not available. */
1661void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1662 unsigned int engine_index, bool enable)
1663{
1664 enum b43_dmatype type;
1665 u16 mmio_base;
1666
1667 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1668
1669 mmio_base = b43_dmacontroller_base(type, engine_index);
1670 direct_fifo_rx(dev, type, mmio_base, enable);
1671}
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