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e4d6b795 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | ||
5 | DMA ringbuffer and descriptor allocation/management | |
6 | ||
7 | Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> | |
8 | ||
9 | Some code in this file is derived from the b44.c driver | |
10 | Copyright (C) 2002 David S. Miller | |
11 | Copyright (C) Pekka Pietikainen | |
12 | ||
13 | This program is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2 of the License, or | |
16 | (at your option) any later version. | |
17 | ||
18 | This program is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with this program; see the file COPYING. If not, write to | |
25 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
26 | Boston, MA 02110-1301, USA. | |
27 | ||
28 | */ | |
29 | ||
30 | #include "b43.h" | |
31 | #include "dma.h" | |
32 | #include "main.h" | |
33 | #include "debugfs.h" | |
34 | #include "xmit.h" | |
35 | ||
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/skbuff.h> | |
280d0e16 MB |
40 | #include <linux/etherdevice.h> |
41 | ||
e4d6b795 MB |
42 | |
43 | /* 32bit DMA ops. */ | |
44 | static | |
45 | struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring, | |
46 | int slot, | |
47 | struct b43_dmadesc_meta **meta) | |
48 | { | |
49 | struct b43_dmadesc32 *desc; | |
50 | ||
51 | *meta = &(ring->meta[slot]); | |
52 | desc = ring->descbase; | |
53 | desc = &(desc[slot]); | |
54 | ||
55 | return (struct b43_dmadesc_generic *)desc; | |
56 | } | |
57 | ||
58 | static void op32_fill_descriptor(struct b43_dmaring *ring, | |
59 | struct b43_dmadesc_generic *desc, | |
60 | dma_addr_t dmaaddr, u16 bufsize, | |
61 | int start, int end, int irq) | |
62 | { | |
63 | struct b43_dmadesc32 *descbase = ring->descbase; | |
64 | int slot; | |
65 | u32 ctl; | |
66 | u32 addr; | |
67 | u32 addrext; | |
68 | ||
69 | slot = (int)(&(desc->dma32) - descbase); | |
70 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
71 | ||
72 | addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK); | |
73 | addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK) | |
74 | >> SSB_DMA_TRANSLATION_SHIFT; | |
75 | addr |= ssb_dma_translation(ring->dev->dev); | |
76 | ctl = (bufsize - ring->frameoffset) | |
77 | & B43_DMA32_DCTL_BYTECNT; | |
78 | if (slot == ring->nr_slots - 1) | |
79 | ctl |= B43_DMA32_DCTL_DTABLEEND; | |
80 | if (start) | |
81 | ctl |= B43_DMA32_DCTL_FRAMESTART; | |
82 | if (end) | |
83 | ctl |= B43_DMA32_DCTL_FRAMEEND; | |
84 | if (irq) | |
85 | ctl |= B43_DMA32_DCTL_IRQ; | |
86 | ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT) | |
87 | & B43_DMA32_DCTL_ADDREXT_MASK; | |
88 | ||
89 | desc->dma32.control = cpu_to_le32(ctl); | |
90 | desc->dma32.address = cpu_to_le32(addr); | |
91 | } | |
92 | ||
93 | static void op32_poke_tx(struct b43_dmaring *ring, int slot) | |
94 | { | |
95 | b43_dma_write(ring, B43_DMA32_TXINDEX, | |
96 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
97 | } | |
98 | ||
99 | static void op32_tx_suspend(struct b43_dmaring *ring) | |
100 | { | |
101 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
102 | | B43_DMA32_TXSUSPEND); | |
103 | } | |
104 | ||
105 | static void op32_tx_resume(struct b43_dmaring *ring) | |
106 | { | |
107 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
108 | & ~B43_DMA32_TXSUSPEND); | |
109 | } | |
110 | ||
111 | static int op32_get_current_rxslot(struct b43_dmaring *ring) | |
112 | { | |
113 | u32 val; | |
114 | ||
115 | val = b43_dma_read(ring, B43_DMA32_RXSTATUS); | |
116 | val &= B43_DMA32_RXDPTR; | |
117 | ||
118 | return (val / sizeof(struct b43_dmadesc32)); | |
119 | } | |
120 | ||
121 | static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
122 | { | |
123 | b43_dma_write(ring, B43_DMA32_RXINDEX, | |
124 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
125 | } | |
126 | ||
127 | static const struct b43_dma_ops dma32_ops = { | |
128 | .idx2desc = op32_idx2desc, | |
129 | .fill_descriptor = op32_fill_descriptor, | |
130 | .poke_tx = op32_poke_tx, | |
131 | .tx_suspend = op32_tx_suspend, | |
132 | .tx_resume = op32_tx_resume, | |
133 | .get_current_rxslot = op32_get_current_rxslot, | |
134 | .set_current_rxslot = op32_set_current_rxslot, | |
135 | }; | |
136 | ||
137 | /* 64bit DMA ops. */ | |
138 | static | |
139 | struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring, | |
140 | int slot, | |
141 | struct b43_dmadesc_meta **meta) | |
142 | { | |
143 | struct b43_dmadesc64 *desc; | |
144 | ||
145 | *meta = &(ring->meta[slot]); | |
146 | desc = ring->descbase; | |
147 | desc = &(desc[slot]); | |
148 | ||
149 | return (struct b43_dmadesc_generic *)desc; | |
150 | } | |
151 | ||
152 | static void op64_fill_descriptor(struct b43_dmaring *ring, | |
153 | struct b43_dmadesc_generic *desc, | |
154 | dma_addr_t dmaaddr, u16 bufsize, | |
155 | int start, int end, int irq) | |
156 | { | |
157 | struct b43_dmadesc64 *descbase = ring->descbase; | |
158 | int slot; | |
159 | u32 ctl0 = 0, ctl1 = 0; | |
160 | u32 addrlo, addrhi; | |
161 | u32 addrext; | |
162 | ||
163 | slot = (int)(&(desc->dma64) - descbase); | |
164 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
165 | ||
166 | addrlo = (u32) (dmaaddr & 0xFFFFFFFF); | |
167 | addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); | |
168 | addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) | |
169 | >> SSB_DMA_TRANSLATION_SHIFT; | |
013978b6 | 170 | addrhi |= (ssb_dma_translation(ring->dev->dev) << 1); |
e4d6b795 MB |
171 | if (slot == ring->nr_slots - 1) |
172 | ctl0 |= B43_DMA64_DCTL0_DTABLEEND; | |
173 | if (start) | |
174 | ctl0 |= B43_DMA64_DCTL0_FRAMESTART; | |
175 | if (end) | |
176 | ctl0 |= B43_DMA64_DCTL0_FRAMEEND; | |
177 | if (irq) | |
178 | ctl0 |= B43_DMA64_DCTL0_IRQ; | |
179 | ctl1 |= (bufsize - ring->frameoffset) | |
180 | & B43_DMA64_DCTL1_BYTECNT; | |
181 | ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) | |
182 | & B43_DMA64_DCTL1_ADDREXT_MASK; | |
183 | ||
184 | desc->dma64.control0 = cpu_to_le32(ctl0); | |
185 | desc->dma64.control1 = cpu_to_le32(ctl1); | |
186 | desc->dma64.address_low = cpu_to_le32(addrlo); | |
187 | desc->dma64.address_high = cpu_to_le32(addrhi); | |
188 | } | |
189 | ||
190 | static void op64_poke_tx(struct b43_dmaring *ring, int slot) | |
191 | { | |
192 | b43_dma_write(ring, B43_DMA64_TXINDEX, | |
193 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
194 | } | |
195 | ||
196 | static void op64_tx_suspend(struct b43_dmaring *ring) | |
197 | { | |
198 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
199 | | B43_DMA64_TXSUSPEND); | |
200 | } | |
201 | ||
202 | static void op64_tx_resume(struct b43_dmaring *ring) | |
203 | { | |
204 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
205 | & ~B43_DMA64_TXSUSPEND); | |
206 | } | |
207 | ||
208 | static int op64_get_current_rxslot(struct b43_dmaring *ring) | |
209 | { | |
210 | u32 val; | |
211 | ||
212 | val = b43_dma_read(ring, B43_DMA64_RXSTATUS); | |
213 | val &= B43_DMA64_RXSTATDPTR; | |
214 | ||
215 | return (val / sizeof(struct b43_dmadesc64)); | |
216 | } | |
217 | ||
218 | static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
219 | { | |
220 | b43_dma_write(ring, B43_DMA64_RXINDEX, | |
221 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
222 | } | |
223 | ||
224 | static const struct b43_dma_ops dma64_ops = { | |
225 | .idx2desc = op64_idx2desc, | |
226 | .fill_descriptor = op64_fill_descriptor, | |
227 | .poke_tx = op64_poke_tx, | |
228 | .tx_suspend = op64_tx_suspend, | |
229 | .tx_resume = op64_tx_resume, | |
230 | .get_current_rxslot = op64_get_current_rxslot, | |
231 | .set_current_rxslot = op64_set_current_rxslot, | |
232 | }; | |
233 | ||
234 | static inline int free_slots(struct b43_dmaring *ring) | |
235 | { | |
236 | return (ring->nr_slots - ring->used_slots); | |
237 | } | |
238 | ||
239 | static inline int next_slot(struct b43_dmaring *ring, int slot) | |
240 | { | |
241 | B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); | |
242 | if (slot == ring->nr_slots - 1) | |
243 | return 0; | |
244 | return slot + 1; | |
245 | } | |
246 | ||
247 | static inline int prev_slot(struct b43_dmaring *ring, int slot) | |
248 | { | |
249 | B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); | |
250 | if (slot == 0) | |
251 | return ring->nr_slots - 1; | |
252 | return slot - 1; | |
253 | } | |
254 | ||
255 | #ifdef CONFIG_B43_DEBUG | |
256 | static void update_max_used_slots(struct b43_dmaring *ring, | |
257 | int current_used_slots) | |
258 | { | |
259 | if (current_used_slots <= ring->max_used_slots) | |
260 | return; | |
261 | ring->max_used_slots = current_used_slots; | |
262 | if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) { | |
263 | b43dbg(ring->dev->wl, | |
264 | "max_used_slots increased to %d on %s ring %d\n", | |
265 | ring->max_used_slots, | |
266 | ring->tx ? "TX" : "RX", ring->index); | |
267 | } | |
268 | } | |
269 | #else | |
270 | static inline | |
271 | void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots) | |
272 | { | |
273 | } | |
274 | #endif /* DEBUG */ | |
275 | ||
276 | /* Request a slot for usage. */ | |
277 | static inline int request_slot(struct b43_dmaring *ring) | |
278 | { | |
279 | int slot; | |
280 | ||
281 | B43_WARN_ON(!ring->tx); | |
282 | B43_WARN_ON(ring->stopped); | |
283 | B43_WARN_ON(free_slots(ring) == 0); | |
284 | ||
285 | slot = next_slot(ring, ring->current_slot); | |
286 | ring->current_slot = slot; | |
287 | ring->used_slots++; | |
288 | ||
289 | update_max_used_slots(ring, ring->used_slots); | |
290 | ||
291 | return slot; | |
292 | } | |
293 | ||
294 | /* Mac80211-queue to b43-ring mapping */ | |
295 | static struct b43_dmaring *priority_to_txring(struct b43_wldev *dev, | |
296 | int queue_priority) | |
297 | { | |
298 | struct b43_dmaring *ring; | |
299 | ||
300 | /*FIXME: For now we always run on TX-ring-1 */ | |
301 | return dev->dma.tx_ring1; | |
302 | ||
303 | /* 0 = highest priority */ | |
304 | switch (queue_priority) { | |
305 | default: | |
306 | B43_WARN_ON(1); | |
307 | /* fallthrough */ | |
308 | case 0: | |
309 | ring = dev->dma.tx_ring3; | |
310 | break; | |
311 | case 1: | |
312 | ring = dev->dma.tx_ring2; | |
313 | break; | |
314 | case 2: | |
315 | ring = dev->dma.tx_ring1; | |
316 | break; | |
317 | case 3: | |
318 | ring = dev->dma.tx_ring0; | |
319 | break; | |
e4d6b795 MB |
320 | } |
321 | ||
322 | return ring; | |
323 | } | |
324 | ||
280d0e16 | 325 | /* b43-ring to mac80211-queue mapping */ |
e4d6b795 MB |
326 | static inline int txring_to_priority(struct b43_dmaring *ring) |
327 | { | |
280d0e16 MB |
328 | static const u8 idx_to_prio[] = { 3, 2, 1, 0, }; |
329 | unsigned int index; | |
e4d6b795 MB |
330 | |
331 | /*FIXME: have only one queue, for now */ | |
332 | return 0; | |
333 | ||
280d0e16 MB |
334 | index = ring->index; |
335 | if (B43_WARN_ON(index >= ARRAY_SIZE(idx_to_prio))) | |
336 | index = 0; | |
337 | return idx_to_prio[index]; | |
e4d6b795 MB |
338 | } |
339 | ||
b79caa68 | 340 | static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx) |
e4d6b795 MB |
341 | { |
342 | static const u16 map64[] = { | |
343 | B43_MMIO_DMA64_BASE0, | |
344 | B43_MMIO_DMA64_BASE1, | |
345 | B43_MMIO_DMA64_BASE2, | |
346 | B43_MMIO_DMA64_BASE3, | |
347 | B43_MMIO_DMA64_BASE4, | |
348 | B43_MMIO_DMA64_BASE5, | |
349 | }; | |
350 | static const u16 map32[] = { | |
351 | B43_MMIO_DMA32_BASE0, | |
352 | B43_MMIO_DMA32_BASE1, | |
353 | B43_MMIO_DMA32_BASE2, | |
354 | B43_MMIO_DMA32_BASE3, | |
355 | B43_MMIO_DMA32_BASE4, | |
356 | B43_MMIO_DMA32_BASE5, | |
357 | }; | |
358 | ||
b79caa68 | 359 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
360 | B43_WARN_ON(!(controller_idx >= 0 && |
361 | controller_idx < ARRAY_SIZE(map64))); | |
362 | return map64[controller_idx]; | |
363 | } | |
364 | B43_WARN_ON(!(controller_idx >= 0 && | |
365 | controller_idx < ARRAY_SIZE(map32))); | |
366 | return map32[controller_idx]; | |
367 | } | |
368 | ||
369 | static inline | |
370 | dma_addr_t map_descbuffer(struct b43_dmaring *ring, | |
371 | unsigned char *buf, size_t len, int tx) | |
372 | { | |
373 | dma_addr_t dmaaddr; | |
374 | ||
375 | if (tx) { | |
376 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
377 | buf, len, DMA_TO_DEVICE); | |
378 | } else { | |
379 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
380 | buf, len, DMA_FROM_DEVICE); | |
381 | } | |
382 | ||
383 | return dmaaddr; | |
384 | } | |
385 | ||
386 | static inline | |
387 | void unmap_descbuffer(struct b43_dmaring *ring, | |
388 | dma_addr_t addr, size_t len, int tx) | |
389 | { | |
390 | if (tx) { | |
391 | dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE); | |
392 | } else { | |
393 | dma_unmap_single(ring->dev->dev->dev, | |
394 | addr, len, DMA_FROM_DEVICE); | |
395 | } | |
396 | } | |
397 | ||
398 | static inline | |
399 | void sync_descbuffer_for_cpu(struct b43_dmaring *ring, | |
400 | dma_addr_t addr, size_t len) | |
401 | { | |
402 | B43_WARN_ON(ring->tx); | |
403 | dma_sync_single_for_cpu(ring->dev->dev->dev, | |
404 | addr, len, DMA_FROM_DEVICE); | |
405 | } | |
406 | ||
407 | static inline | |
408 | void sync_descbuffer_for_device(struct b43_dmaring *ring, | |
409 | dma_addr_t addr, size_t len) | |
410 | { | |
411 | B43_WARN_ON(ring->tx); | |
412 | dma_sync_single_for_device(ring->dev->dev->dev, | |
413 | addr, len, DMA_FROM_DEVICE); | |
414 | } | |
415 | ||
416 | static inline | |
417 | void free_descriptor_buffer(struct b43_dmaring *ring, | |
418 | struct b43_dmadesc_meta *meta) | |
419 | { | |
420 | if (meta->skb) { | |
421 | dev_kfree_skb_any(meta->skb); | |
422 | meta->skb = NULL; | |
423 | } | |
424 | } | |
425 | ||
426 | static int alloc_ringmemory(struct b43_dmaring *ring) | |
427 | { | |
428 | struct device *dev = ring->dev->dev->dev; | |
013978b6 LF |
429 | gfp_t flags = GFP_KERNEL; |
430 | ||
431 | /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K | |
432 | * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing | |
433 | * has shown that 4K is sufficient for the latter as long as the buffer | |
434 | * does not cross an 8K boundary. | |
435 | * | |
436 | * For unknown reasons - possibly a hardware error - the BCM4311 rev | |
437 | * 02, which uses 64-bit DMA, needs the ring buffer in very low memory, | |
438 | * which accounts for the GFP_DMA flag below. | |
439 | */ | |
b79caa68 | 440 | if (ring->type == B43_DMA_64BIT) |
013978b6 | 441 | flags |= GFP_DMA; |
e4d6b795 | 442 | ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE, |
013978b6 | 443 | &(ring->dmabase), flags); |
e4d6b795 MB |
444 | if (!ring->descbase) { |
445 | b43err(ring->dev->wl, "DMA ringmemory allocation failed\n"); | |
446 | return -ENOMEM; | |
447 | } | |
448 | memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE); | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static void free_ringmemory(struct b43_dmaring *ring) | |
454 | { | |
455 | struct device *dev = ring->dev->dev->dev; | |
456 | ||
457 | dma_free_coherent(dev, B43_DMA_RINGMEMSIZE, | |
458 | ring->descbase, ring->dmabase); | |
459 | } | |
460 | ||
461 | /* Reset the RX DMA channel */ | |
b79caa68 MB |
462 | static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, |
463 | enum b43_dmatype type) | |
e4d6b795 MB |
464 | { |
465 | int i; | |
466 | u32 value; | |
467 | u16 offset; | |
468 | ||
469 | might_sleep(); | |
470 | ||
b79caa68 | 471 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL; |
e4d6b795 MB |
472 | b43_write32(dev, mmio_base + offset, 0); |
473 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
474 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS : |
475 | B43_DMA32_RXSTATUS; | |
e4d6b795 | 476 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 477 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
478 | value &= B43_DMA64_RXSTAT; |
479 | if (value == B43_DMA64_RXSTAT_DISABLED) { | |
480 | i = -1; | |
481 | break; | |
482 | } | |
483 | } else { | |
484 | value &= B43_DMA32_RXSTATE; | |
485 | if (value == B43_DMA32_RXSTAT_DISABLED) { | |
486 | i = -1; | |
487 | break; | |
488 | } | |
489 | } | |
490 | msleep(1); | |
491 | } | |
492 | if (i != -1) { | |
493 | b43err(dev->wl, "DMA RX reset timed out\n"); | |
494 | return -ENODEV; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
013978b6 | 500 | /* Reset the TX DMA channel */ |
b79caa68 MB |
501 | static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, |
502 | enum b43_dmatype type) | |
e4d6b795 MB |
503 | { |
504 | int i; | |
505 | u32 value; | |
506 | u16 offset; | |
507 | ||
508 | might_sleep(); | |
509 | ||
510 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
511 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
512 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 513 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 514 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
515 | value &= B43_DMA64_TXSTAT; |
516 | if (value == B43_DMA64_TXSTAT_DISABLED || | |
517 | value == B43_DMA64_TXSTAT_IDLEWAIT || | |
518 | value == B43_DMA64_TXSTAT_STOPPED) | |
519 | break; | |
520 | } else { | |
521 | value &= B43_DMA32_TXSTATE; | |
522 | if (value == B43_DMA32_TXSTAT_DISABLED || | |
523 | value == B43_DMA32_TXSTAT_IDLEWAIT || | |
524 | value == B43_DMA32_TXSTAT_STOPPED) | |
525 | break; | |
526 | } | |
527 | msleep(1); | |
528 | } | |
b79caa68 | 529 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL; |
e4d6b795 MB |
530 | b43_write32(dev, mmio_base + offset, 0); |
531 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
532 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
533 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 534 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 535 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
536 | value &= B43_DMA64_TXSTAT; |
537 | if (value == B43_DMA64_TXSTAT_DISABLED) { | |
538 | i = -1; | |
539 | break; | |
540 | } | |
541 | } else { | |
542 | value &= B43_DMA32_TXSTATE; | |
543 | if (value == B43_DMA32_TXSTAT_DISABLED) { | |
544 | i = -1; | |
545 | break; | |
546 | } | |
547 | } | |
548 | msleep(1); | |
549 | } | |
550 | if (i != -1) { | |
551 | b43err(dev->wl, "DMA TX reset timed out\n"); | |
552 | return -ENODEV; | |
553 | } | |
554 | /* ensure the reset is completed. */ | |
555 | msleep(1); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
b79caa68 MB |
560 | /* Check if a DMA mapping address is invalid. */ |
561 | static bool b43_dma_mapping_error(struct b43_dmaring *ring, | |
562 | dma_addr_t addr, | |
ffa9256a | 563 | size_t buffersize, bool dma_to_device) |
b79caa68 MB |
564 | { |
565 | if (unlikely(dma_mapping_error(addr))) | |
566 | return 1; | |
567 | ||
568 | switch (ring->type) { | |
569 | case B43_DMA_30BIT: | |
570 | if ((u64)addr + buffersize > (1ULL << 30)) | |
ffa9256a | 571 | goto address_error; |
b79caa68 MB |
572 | break; |
573 | case B43_DMA_32BIT: | |
574 | if ((u64)addr + buffersize > (1ULL << 32)) | |
ffa9256a | 575 | goto address_error; |
b79caa68 MB |
576 | break; |
577 | case B43_DMA_64BIT: | |
578 | /* Currently we can't have addresses beyond | |
579 | * 64bit in the kernel. */ | |
580 | break; | |
581 | } | |
582 | ||
583 | /* The address is OK. */ | |
584 | return 0; | |
ffa9256a MB |
585 | |
586 | address_error: | |
587 | /* We can't support this address. Unmap it again. */ | |
588 | unmap_descbuffer(ring, addr, buffersize, dma_to_device); | |
589 | ||
590 | return 1; | |
b79caa68 MB |
591 | } |
592 | ||
e4d6b795 MB |
593 | static int setup_rx_descbuffer(struct b43_dmaring *ring, |
594 | struct b43_dmadesc_generic *desc, | |
595 | struct b43_dmadesc_meta *meta, gfp_t gfp_flags) | |
596 | { | |
597 | struct b43_rxhdr_fw4 *rxhdr; | |
598 | struct b43_hwtxstatus *txstat; | |
599 | dma_addr_t dmaaddr; | |
600 | struct sk_buff *skb; | |
601 | ||
602 | B43_WARN_ON(ring->tx); | |
603 | ||
604 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
605 | if (unlikely(!skb)) | |
606 | return -ENOMEM; | |
607 | dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0); | |
ffa9256a | 608 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
e4d6b795 MB |
609 | /* ugh. try to realloc in zone_dma */ |
610 | gfp_flags |= GFP_DMA; | |
611 | ||
612 | dev_kfree_skb_any(skb); | |
613 | ||
614 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
615 | if (unlikely(!skb)) | |
616 | return -ENOMEM; | |
617 | dmaaddr = map_descbuffer(ring, skb->data, | |
618 | ring->rx_buffersize, 0); | |
619 | } | |
620 | ||
ffa9256a | 621 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
e4d6b795 MB |
622 | dev_kfree_skb_any(skb); |
623 | return -EIO; | |
624 | } | |
625 | ||
626 | meta->skb = skb; | |
627 | meta->dmaaddr = dmaaddr; | |
628 | ring->ops->fill_descriptor(ring, desc, dmaaddr, | |
629 | ring->rx_buffersize, 0, 0, 0); | |
630 | ||
631 | rxhdr = (struct b43_rxhdr_fw4 *)(skb->data); | |
632 | rxhdr->frame_len = 0; | |
633 | txstat = (struct b43_hwtxstatus *)(skb->data); | |
634 | txstat->cookie = 0; | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | /* Allocate the initial descbuffers. | |
640 | * This is used for an RX ring only. | |
641 | */ | |
642 | static int alloc_initial_descbuffers(struct b43_dmaring *ring) | |
643 | { | |
644 | int i, err = -ENOMEM; | |
645 | struct b43_dmadesc_generic *desc; | |
646 | struct b43_dmadesc_meta *meta; | |
647 | ||
648 | for (i = 0; i < ring->nr_slots; i++) { | |
649 | desc = ring->ops->idx2desc(ring, i, &meta); | |
650 | ||
651 | err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); | |
652 | if (err) { | |
653 | b43err(ring->dev->wl, | |
654 | "Failed to allocate initial descbuffers\n"); | |
655 | goto err_unwind; | |
656 | } | |
657 | } | |
658 | mb(); | |
659 | ring->used_slots = ring->nr_slots; | |
660 | err = 0; | |
661 | out: | |
662 | return err; | |
663 | ||
664 | err_unwind: | |
665 | for (i--; i >= 0; i--) { | |
666 | desc = ring->ops->idx2desc(ring, i, &meta); | |
667 | ||
668 | unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); | |
669 | dev_kfree_skb(meta->skb); | |
670 | } | |
671 | goto out; | |
672 | } | |
673 | ||
674 | /* Do initial setup of the DMA controller. | |
675 | * Reset the controller, write the ring busaddress | |
676 | * and switch the "enable" bit on. | |
677 | */ | |
678 | static int dmacontroller_setup(struct b43_dmaring *ring) | |
679 | { | |
680 | int err = 0; | |
681 | u32 value; | |
682 | u32 addrext; | |
683 | u32 trans = ssb_dma_translation(ring->dev->dev); | |
684 | ||
685 | if (ring->tx) { | |
b79caa68 | 686 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
687 | u64 ringbase = (u64) (ring->dmabase); |
688 | ||
689 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
690 | >> SSB_DMA_TRANSLATION_SHIFT; | |
691 | value = B43_DMA64_TXENABLE; | |
692 | value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) | |
693 | & B43_DMA64_TXADDREXT_MASK; | |
694 | b43_dma_write(ring, B43_DMA64_TXCTL, value); | |
695 | b43_dma_write(ring, B43_DMA64_TXRINGLO, | |
696 | (ringbase & 0xFFFFFFFF)); | |
697 | b43_dma_write(ring, B43_DMA64_TXRINGHI, | |
698 | ((ringbase >> 32) & | |
699 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 | 700 | | (trans << 1)); |
e4d6b795 MB |
701 | } else { |
702 | u32 ringbase = (u32) (ring->dmabase); | |
703 | ||
704 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
705 | >> SSB_DMA_TRANSLATION_SHIFT; | |
706 | value = B43_DMA32_TXENABLE; | |
707 | value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) | |
708 | & B43_DMA32_TXADDREXT_MASK; | |
709 | b43_dma_write(ring, B43_DMA32_TXCTL, value); | |
710 | b43_dma_write(ring, B43_DMA32_TXRING, | |
711 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
712 | | trans); | |
713 | } | |
714 | } else { | |
715 | err = alloc_initial_descbuffers(ring); | |
716 | if (err) | |
717 | goto out; | |
b79caa68 | 718 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
719 | u64 ringbase = (u64) (ring->dmabase); |
720 | ||
721 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
722 | >> SSB_DMA_TRANSLATION_SHIFT; | |
723 | value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT); | |
724 | value |= B43_DMA64_RXENABLE; | |
725 | value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) | |
726 | & B43_DMA64_RXADDREXT_MASK; | |
727 | b43_dma_write(ring, B43_DMA64_RXCTL, value); | |
728 | b43_dma_write(ring, B43_DMA64_RXRINGLO, | |
729 | (ringbase & 0xFFFFFFFF)); | |
730 | b43_dma_write(ring, B43_DMA64_RXRINGHI, | |
731 | ((ringbase >> 32) & | |
732 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 LF |
733 | | (trans << 1)); |
734 | b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * | |
735 | sizeof(struct b43_dmadesc64)); | |
e4d6b795 MB |
736 | } else { |
737 | u32 ringbase = (u32) (ring->dmabase); | |
738 | ||
739 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
740 | >> SSB_DMA_TRANSLATION_SHIFT; | |
741 | value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT); | |
742 | value |= B43_DMA32_RXENABLE; | |
743 | value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) | |
744 | & B43_DMA32_RXADDREXT_MASK; | |
745 | b43_dma_write(ring, B43_DMA32_RXCTL, value); | |
746 | b43_dma_write(ring, B43_DMA32_RXRING, | |
747 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
748 | | trans); | |
013978b6 LF |
749 | b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots * |
750 | sizeof(struct b43_dmadesc32)); | |
e4d6b795 MB |
751 | } |
752 | } | |
753 | ||
013978b6 | 754 | out: |
e4d6b795 MB |
755 | return err; |
756 | } | |
757 | ||
758 | /* Shutdown the DMA controller. */ | |
759 | static void dmacontroller_cleanup(struct b43_dmaring *ring) | |
760 | { | |
761 | if (ring->tx) { | |
762 | b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
763 | ring->type); |
764 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
765 | b43_dma_write(ring, B43_DMA64_TXRINGLO, 0); |
766 | b43_dma_write(ring, B43_DMA64_TXRINGHI, 0); | |
767 | } else | |
768 | b43_dma_write(ring, B43_DMA32_TXRING, 0); | |
769 | } else { | |
770 | b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
771 | ring->type); |
772 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
773 | b43_dma_write(ring, B43_DMA64_RXRINGLO, 0); |
774 | b43_dma_write(ring, B43_DMA64_RXRINGHI, 0); | |
775 | } else | |
776 | b43_dma_write(ring, B43_DMA32_RXRING, 0); | |
777 | } | |
778 | } | |
779 | ||
780 | static void free_all_descbuffers(struct b43_dmaring *ring) | |
781 | { | |
782 | struct b43_dmadesc_generic *desc; | |
783 | struct b43_dmadesc_meta *meta; | |
784 | int i; | |
785 | ||
786 | if (!ring->used_slots) | |
787 | return; | |
788 | for (i = 0; i < ring->nr_slots; i++) { | |
789 | desc = ring->ops->idx2desc(ring, i, &meta); | |
790 | ||
791 | if (!meta->skb) { | |
792 | B43_WARN_ON(!ring->tx); | |
793 | continue; | |
794 | } | |
795 | if (ring->tx) { | |
796 | unmap_descbuffer(ring, meta->dmaaddr, | |
797 | meta->skb->len, 1); | |
798 | } else { | |
799 | unmap_descbuffer(ring, meta->dmaaddr, | |
800 | ring->rx_buffersize, 0); | |
801 | } | |
802 | free_descriptor_buffer(ring, meta); | |
803 | } | |
804 | } | |
805 | ||
806 | static u64 supported_dma_mask(struct b43_wldev *dev) | |
807 | { | |
808 | u32 tmp; | |
809 | u16 mmio_base; | |
810 | ||
811 | tmp = b43_read32(dev, SSB_TMSHIGH); | |
812 | if (tmp & SSB_TMSHIGH_DMA64) | |
813 | return DMA_64BIT_MASK; | |
814 | mmio_base = b43_dmacontroller_base(0, 0); | |
815 | b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK); | |
816 | tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL); | |
817 | if (tmp & B43_DMA32_TXADDREXT_MASK) | |
818 | return DMA_32BIT_MASK; | |
819 | ||
820 | return DMA_30BIT_MASK; | |
821 | } | |
822 | ||
823 | /* Main initialization function. */ | |
824 | static | |
825 | struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev, | |
826 | int controller_index, | |
b79caa68 MB |
827 | int for_tx, |
828 | enum b43_dmatype type) | |
e4d6b795 MB |
829 | { |
830 | struct b43_dmaring *ring; | |
831 | int err; | |
832 | int nr_slots; | |
833 | dma_addr_t dma_test; | |
834 | ||
835 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
836 | if (!ring) | |
837 | goto out; | |
b79caa68 | 838 | ring->type = type; |
e4d6b795 MB |
839 | |
840 | nr_slots = B43_RXRING_SLOTS; | |
841 | if (for_tx) | |
842 | nr_slots = B43_TXRING_SLOTS; | |
843 | ||
844 | ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta), | |
845 | GFP_KERNEL); | |
846 | if (!ring->meta) | |
847 | goto err_kfree_ring; | |
848 | if (for_tx) { | |
849 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 850 | b43_txhdr_size(dev), |
e4d6b795 MB |
851 | GFP_KERNEL); |
852 | if (!ring->txhdr_cache) | |
853 | goto err_kfree_meta; | |
854 | ||
855 | /* test for ability to dma to txhdr_cache */ | |
856 | dma_test = dma_map_single(dev->dev->dev, | |
857 | ring->txhdr_cache, | |
eb189d8b | 858 | b43_txhdr_size(dev), |
e4d6b795 MB |
859 | DMA_TO_DEVICE); |
860 | ||
ffa9256a MB |
861 | if (b43_dma_mapping_error(ring, dma_test, |
862 | b43_txhdr_size(dev), 1)) { | |
e4d6b795 MB |
863 | /* ugh realloc */ |
864 | kfree(ring->txhdr_cache); | |
865 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 866 | b43_txhdr_size(dev), |
e4d6b795 MB |
867 | GFP_KERNEL | GFP_DMA); |
868 | if (!ring->txhdr_cache) | |
869 | goto err_kfree_meta; | |
870 | ||
871 | dma_test = dma_map_single(dev->dev->dev, | |
872 | ring->txhdr_cache, | |
eb189d8b | 873 | b43_txhdr_size(dev), |
e4d6b795 MB |
874 | DMA_TO_DEVICE); |
875 | ||
b79caa68 | 876 | if (b43_dma_mapping_error(ring, dma_test, |
ffa9256a | 877 | b43_txhdr_size(dev), 1)) |
e4d6b795 MB |
878 | goto err_kfree_txhdr_cache; |
879 | } | |
880 | ||
881 | dma_unmap_single(dev->dev->dev, | |
eb189d8b | 882 | dma_test, b43_txhdr_size(dev), |
e4d6b795 MB |
883 | DMA_TO_DEVICE); |
884 | } | |
885 | ||
886 | ring->dev = dev; | |
887 | ring->nr_slots = nr_slots; | |
b79caa68 | 888 | ring->mmio_base = b43_dmacontroller_base(type, controller_index); |
e4d6b795 | 889 | ring->index = controller_index; |
b79caa68 | 890 | if (type == B43_DMA_64BIT) |
e4d6b795 MB |
891 | ring->ops = &dma64_ops; |
892 | else | |
893 | ring->ops = &dma32_ops; | |
894 | if (for_tx) { | |
895 | ring->tx = 1; | |
896 | ring->current_slot = -1; | |
897 | } else { | |
898 | if (ring->index == 0) { | |
899 | ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE; | |
900 | ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET; | |
901 | } else if (ring->index == 3) { | |
902 | ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE; | |
903 | ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET; | |
904 | } else | |
905 | B43_WARN_ON(1); | |
906 | } | |
907 | spin_lock_init(&ring->lock); | |
908 | #ifdef CONFIG_B43_DEBUG | |
909 | ring->last_injected_overflow = jiffies; | |
910 | #endif | |
911 | ||
912 | err = alloc_ringmemory(ring); | |
913 | if (err) | |
914 | goto err_kfree_txhdr_cache; | |
915 | err = dmacontroller_setup(ring); | |
916 | if (err) | |
917 | goto err_free_ringmemory; | |
918 | ||
919 | out: | |
920 | return ring; | |
921 | ||
922 | err_free_ringmemory: | |
923 | free_ringmemory(ring); | |
924 | err_kfree_txhdr_cache: | |
925 | kfree(ring->txhdr_cache); | |
926 | err_kfree_meta: | |
927 | kfree(ring->meta); | |
928 | err_kfree_ring: | |
929 | kfree(ring); | |
930 | ring = NULL; | |
931 | goto out; | |
932 | } | |
933 | ||
934 | /* Main cleanup function. */ | |
935 | static void b43_destroy_dmaring(struct b43_dmaring *ring) | |
936 | { | |
937 | if (!ring) | |
938 | return; | |
939 | ||
b79caa68 MB |
940 | b43dbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots: %d/%d\n", |
941 | (unsigned int)(ring->type), | |
e4d6b795 MB |
942 | ring->mmio_base, |
943 | (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots); | |
944 | /* Device IRQs are disabled prior entering this function, | |
945 | * so no need to take care of concurrency with rx handler stuff. | |
946 | */ | |
947 | dmacontroller_cleanup(ring); | |
948 | free_all_descbuffers(ring); | |
949 | free_ringmemory(ring); | |
950 | ||
951 | kfree(ring->txhdr_cache); | |
952 | kfree(ring->meta); | |
953 | kfree(ring); | |
954 | } | |
955 | ||
956 | void b43_dma_free(struct b43_wldev *dev) | |
957 | { | |
03b29773 | 958 | struct b43_dma *dma = &dev->dma; |
e4d6b795 MB |
959 | |
960 | b43_destroy_dmaring(dma->rx_ring3); | |
961 | dma->rx_ring3 = NULL; | |
962 | b43_destroy_dmaring(dma->rx_ring0); | |
963 | dma->rx_ring0 = NULL; | |
964 | ||
965 | b43_destroy_dmaring(dma->tx_ring5); | |
966 | dma->tx_ring5 = NULL; | |
967 | b43_destroy_dmaring(dma->tx_ring4); | |
968 | dma->tx_ring4 = NULL; | |
969 | b43_destroy_dmaring(dma->tx_ring3); | |
970 | dma->tx_ring3 = NULL; | |
971 | b43_destroy_dmaring(dma->tx_ring2); | |
972 | dma->tx_ring2 = NULL; | |
973 | b43_destroy_dmaring(dma->tx_ring1); | |
974 | dma->tx_ring1 = NULL; | |
975 | b43_destroy_dmaring(dma->tx_ring0); | |
976 | dma->tx_ring0 = NULL; | |
977 | } | |
978 | ||
979 | int b43_dma_init(struct b43_wldev *dev) | |
980 | { | |
981 | struct b43_dma *dma = &dev->dma; | |
982 | struct b43_dmaring *ring; | |
983 | int err; | |
984 | u64 dmamask; | |
b79caa68 | 985 | enum b43_dmatype type; |
e4d6b795 MB |
986 | |
987 | dmamask = supported_dma_mask(dev); | |
b79caa68 MB |
988 | switch (dmamask) { |
989 | default: | |
990 | B43_WARN_ON(1); | |
991 | case DMA_30BIT_MASK: | |
992 | type = B43_DMA_30BIT; | |
993 | break; | |
994 | case DMA_32BIT_MASK: | |
995 | type = B43_DMA_32BIT; | |
996 | break; | |
997 | case DMA_64BIT_MASK: | |
998 | type = B43_DMA_64BIT; | |
999 | break; | |
1000 | } | |
e4d6b795 MB |
1001 | err = ssb_dma_set_mask(dev->dev, dmamask); |
1002 | if (err) { | |
03b29773 MB |
1003 | b43err(dev->wl, "The machine/kernel does not support " |
1004 | "the required DMA mask (0x%08X%08X)\n", | |
1005 | (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32), | |
1006 | (unsigned int)(dmamask & 0x00000000FFFFFFFFULL)); | |
e4d6b795 | 1007 | return -EOPNOTSUPP; |
e4d6b795 MB |
1008 | } |
1009 | ||
1010 | err = -ENOMEM; | |
1011 | /* setup TX DMA channels. */ | |
b79caa68 | 1012 | ring = b43_setup_dmaring(dev, 0, 1, type); |
e4d6b795 MB |
1013 | if (!ring) |
1014 | goto out; | |
1015 | dma->tx_ring0 = ring; | |
1016 | ||
b79caa68 | 1017 | ring = b43_setup_dmaring(dev, 1, 1, type); |
e4d6b795 MB |
1018 | if (!ring) |
1019 | goto err_destroy_tx0; | |
1020 | dma->tx_ring1 = ring; | |
1021 | ||
b79caa68 | 1022 | ring = b43_setup_dmaring(dev, 2, 1, type); |
e4d6b795 MB |
1023 | if (!ring) |
1024 | goto err_destroy_tx1; | |
1025 | dma->tx_ring2 = ring; | |
1026 | ||
b79caa68 | 1027 | ring = b43_setup_dmaring(dev, 3, 1, type); |
e4d6b795 MB |
1028 | if (!ring) |
1029 | goto err_destroy_tx2; | |
1030 | dma->tx_ring3 = ring; | |
1031 | ||
b79caa68 | 1032 | ring = b43_setup_dmaring(dev, 4, 1, type); |
e4d6b795 MB |
1033 | if (!ring) |
1034 | goto err_destroy_tx3; | |
1035 | dma->tx_ring4 = ring; | |
1036 | ||
b79caa68 | 1037 | ring = b43_setup_dmaring(dev, 5, 1, type); |
e4d6b795 MB |
1038 | if (!ring) |
1039 | goto err_destroy_tx4; | |
1040 | dma->tx_ring5 = ring; | |
1041 | ||
1042 | /* setup RX DMA channels. */ | |
b79caa68 | 1043 | ring = b43_setup_dmaring(dev, 0, 0, type); |
e4d6b795 MB |
1044 | if (!ring) |
1045 | goto err_destroy_tx5; | |
1046 | dma->rx_ring0 = ring; | |
1047 | ||
1048 | if (dev->dev->id.revision < 5) { | |
b79caa68 | 1049 | ring = b43_setup_dmaring(dev, 3, 0, type); |
e4d6b795 MB |
1050 | if (!ring) |
1051 | goto err_destroy_rx0; | |
1052 | dma->rx_ring3 = ring; | |
1053 | } | |
1054 | ||
b79caa68 MB |
1055 | b43dbg(dev->wl, "%u-bit DMA initialized\n", |
1056 | (unsigned int)type); | |
e4d6b795 MB |
1057 | err = 0; |
1058 | out: | |
1059 | return err; | |
1060 | ||
1061 | err_destroy_rx0: | |
1062 | b43_destroy_dmaring(dma->rx_ring0); | |
1063 | dma->rx_ring0 = NULL; | |
1064 | err_destroy_tx5: | |
1065 | b43_destroy_dmaring(dma->tx_ring5); | |
1066 | dma->tx_ring5 = NULL; | |
1067 | err_destroy_tx4: | |
1068 | b43_destroy_dmaring(dma->tx_ring4); | |
1069 | dma->tx_ring4 = NULL; | |
1070 | err_destroy_tx3: | |
1071 | b43_destroy_dmaring(dma->tx_ring3); | |
1072 | dma->tx_ring3 = NULL; | |
1073 | err_destroy_tx2: | |
1074 | b43_destroy_dmaring(dma->tx_ring2); | |
1075 | dma->tx_ring2 = NULL; | |
1076 | err_destroy_tx1: | |
1077 | b43_destroy_dmaring(dma->tx_ring1); | |
1078 | dma->tx_ring1 = NULL; | |
1079 | err_destroy_tx0: | |
1080 | b43_destroy_dmaring(dma->tx_ring0); | |
1081 | dma->tx_ring0 = NULL; | |
1082 | goto out; | |
1083 | } | |
1084 | ||
1085 | /* Generate a cookie for the TX header. */ | |
1086 | static u16 generate_cookie(struct b43_dmaring *ring, int slot) | |
1087 | { | |
1088 | u16 cookie = 0x1000; | |
1089 | ||
1090 | /* Use the upper 4 bits of the cookie as | |
1091 | * DMA controller ID and store the slot number | |
1092 | * in the lower 12 bits. | |
1093 | * Note that the cookie must never be 0, as this | |
1094 | * is a special value used in RX path. | |
280d0e16 MB |
1095 | * It can also not be 0xFFFF because that is special |
1096 | * for multicast frames. | |
e4d6b795 MB |
1097 | */ |
1098 | switch (ring->index) { | |
1099 | case 0: | |
280d0e16 | 1100 | cookie = 0x1000; |
e4d6b795 MB |
1101 | break; |
1102 | case 1: | |
280d0e16 | 1103 | cookie = 0x2000; |
e4d6b795 MB |
1104 | break; |
1105 | case 2: | |
280d0e16 | 1106 | cookie = 0x3000; |
e4d6b795 MB |
1107 | break; |
1108 | case 3: | |
280d0e16 | 1109 | cookie = 0x4000; |
e4d6b795 MB |
1110 | break; |
1111 | case 4: | |
280d0e16 | 1112 | cookie = 0x5000; |
e4d6b795 MB |
1113 | break; |
1114 | case 5: | |
280d0e16 | 1115 | cookie = 0x6000; |
e4d6b795 | 1116 | break; |
280d0e16 MB |
1117 | default: |
1118 | B43_WARN_ON(1); | |
e4d6b795 MB |
1119 | } |
1120 | B43_WARN_ON(slot & ~0x0FFF); | |
1121 | cookie |= (u16) slot; | |
1122 | ||
1123 | return cookie; | |
1124 | } | |
1125 | ||
1126 | /* Inspect a cookie and find out to which controller/slot it belongs. */ | |
1127 | static | |
1128 | struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot) | |
1129 | { | |
1130 | struct b43_dma *dma = &dev->dma; | |
1131 | struct b43_dmaring *ring = NULL; | |
1132 | ||
1133 | switch (cookie & 0xF000) { | |
280d0e16 | 1134 | case 0x1000: |
e4d6b795 MB |
1135 | ring = dma->tx_ring0; |
1136 | break; | |
280d0e16 | 1137 | case 0x2000: |
e4d6b795 MB |
1138 | ring = dma->tx_ring1; |
1139 | break; | |
280d0e16 | 1140 | case 0x3000: |
e4d6b795 MB |
1141 | ring = dma->tx_ring2; |
1142 | break; | |
280d0e16 | 1143 | case 0x4000: |
e4d6b795 MB |
1144 | ring = dma->tx_ring3; |
1145 | break; | |
280d0e16 | 1146 | case 0x5000: |
e4d6b795 MB |
1147 | ring = dma->tx_ring4; |
1148 | break; | |
280d0e16 | 1149 | case 0x6000: |
e4d6b795 MB |
1150 | ring = dma->tx_ring5; |
1151 | break; | |
1152 | default: | |
1153 | B43_WARN_ON(1); | |
1154 | } | |
1155 | *slot = (cookie & 0x0FFF); | |
1156 | B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots)); | |
1157 | ||
1158 | return ring; | |
1159 | } | |
1160 | ||
1161 | static int dma_tx_fragment(struct b43_dmaring *ring, | |
1162 | struct sk_buff *skb, | |
1163 | struct ieee80211_tx_control *ctl) | |
1164 | { | |
1165 | const struct b43_dma_ops *ops = ring->ops; | |
1166 | u8 *header; | |
09552ccd | 1167 | int slot, old_top_slot, old_used_slots; |
e4d6b795 MB |
1168 | int err; |
1169 | struct b43_dmadesc_generic *desc; | |
1170 | struct b43_dmadesc_meta *meta; | |
1171 | struct b43_dmadesc_meta *meta_hdr; | |
1172 | struct sk_buff *bounce_skb; | |
280d0e16 | 1173 | u16 cookie; |
eb189d8b | 1174 | size_t hdrsize = b43_txhdr_size(ring->dev); |
e4d6b795 MB |
1175 | |
1176 | #define SLOTS_PER_PACKET 2 | |
1177 | B43_WARN_ON(skb_shinfo(skb)->nr_frags); | |
1178 | ||
09552ccd MB |
1179 | old_top_slot = ring->current_slot; |
1180 | old_used_slots = ring->used_slots; | |
1181 | ||
e4d6b795 MB |
1182 | /* Get a slot for the header. */ |
1183 | slot = request_slot(ring); | |
1184 | desc = ops->idx2desc(ring, slot, &meta_hdr); | |
1185 | memset(meta_hdr, 0, sizeof(*meta_hdr)); | |
1186 | ||
eb189d8b | 1187 | header = &(ring->txhdr_cache[slot * hdrsize]); |
280d0e16 | 1188 | cookie = generate_cookie(ring, slot); |
09552ccd MB |
1189 | err = b43_generate_txhdr(ring->dev, header, |
1190 | skb->data, skb->len, ctl, cookie); | |
1191 | if (unlikely(err)) { | |
1192 | ring->current_slot = old_top_slot; | |
1193 | ring->used_slots = old_used_slots; | |
1194 | return err; | |
1195 | } | |
e4d6b795 MB |
1196 | |
1197 | meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, | |
eb189d8b | 1198 | hdrsize, 1); |
ffa9256a | 1199 | if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) { |
09552ccd MB |
1200 | ring->current_slot = old_top_slot; |
1201 | ring->used_slots = old_used_slots; | |
e4d6b795 | 1202 | return -EIO; |
09552ccd | 1203 | } |
e4d6b795 | 1204 | ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr, |
eb189d8b | 1205 | hdrsize, 1, 0, 0); |
e4d6b795 MB |
1206 | |
1207 | /* Get a slot for the payload. */ | |
1208 | slot = request_slot(ring); | |
1209 | desc = ops->idx2desc(ring, slot, &meta); | |
1210 | memset(meta, 0, sizeof(*meta)); | |
1211 | ||
1212 | memcpy(&meta->txstat.control, ctl, sizeof(*ctl)); | |
1213 | meta->skb = skb; | |
1214 | meta->is_last_fragment = 1; | |
1215 | ||
1216 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
1217 | /* create a bounce buffer in zone_dma on mapping failure. */ | |
ffa9256a | 1218 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
e4d6b795 MB |
1219 | bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA); |
1220 | if (!bounce_skb) { | |
09552ccd MB |
1221 | ring->current_slot = old_top_slot; |
1222 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1223 | err = -ENOMEM; |
1224 | goto out_unmap_hdr; | |
1225 | } | |
1226 | ||
1227 | memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len); | |
1228 | dev_kfree_skb_any(skb); | |
1229 | skb = bounce_skb; | |
1230 | meta->skb = skb; | |
1231 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
ffa9256a | 1232 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
09552ccd MB |
1233 | ring->current_slot = old_top_slot; |
1234 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1235 | err = -EIO; |
1236 | goto out_free_bounce; | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); | |
1241 | ||
280d0e16 MB |
1242 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { |
1243 | /* Tell the firmware about the cookie of the last | |
1244 | * mcast frame, so it can clear the more-data bit in it. */ | |
1245 | b43_shm_write16(ring->dev, B43_SHM_SHARED, | |
1246 | B43_SHM_SH_MCASTCOOKIE, cookie); | |
1247 | } | |
e4d6b795 MB |
1248 | /* Now transfer the whole frame. */ |
1249 | wmb(); | |
1250 | ops->poke_tx(ring, next_slot(ring, slot)); | |
1251 | return 0; | |
1252 | ||
280d0e16 | 1253 | out_free_bounce: |
e4d6b795 | 1254 | dev_kfree_skb_any(skb); |
280d0e16 | 1255 | out_unmap_hdr: |
e4d6b795 | 1256 | unmap_descbuffer(ring, meta_hdr->dmaaddr, |
eb189d8b | 1257 | hdrsize, 1); |
e4d6b795 MB |
1258 | return err; |
1259 | } | |
1260 | ||
1261 | static inline int should_inject_overflow(struct b43_dmaring *ring) | |
1262 | { | |
1263 | #ifdef CONFIG_B43_DEBUG | |
1264 | if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) { | |
1265 | /* Check if we should inject another ringbuffer overflow | |
1266 | * to test handling of this situation in the stack. */ | |
1267 | unsigned long next_overflow; | |
1268 | ||
1269 | next_overflow = ring->last_injected_overflow + HZ; | |
1270 | if (time_after(jiffies, next_overflow)) { | |
1271 | ring->last_injected_overflow = jiffies; | |
1272 | b43dbg(ring->dev->wl, | |
1273 | "Injecting TX ring overflow on " | |
1274 | "DMA controller %d\n", ring->index); | |
1275 | return 1; | |
1276 | } | |
1277 | } | |
1278 | #endif /* CONFIG_B43_DEBUG */ | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | int b43_dma_tx(struct b43_wldev *dev, | |
1283 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) | |
1284 | { | |
1285 | struct b43_dmaring *ring; | |
280d0e16 | 1286 | struct ieee80211_hdr *hdr; |
e4d6b795 MB |
1287 | int err = 0; |
1288 | unsigned long flags; | |
1289 | ||
280d0e16 MB |
1290 | if (unlikely(skb->len < 2 + 2 + 6)) { |
1291 | /* Too short, this can't be a valid frame. */ | |
1292 | return -EINVAL; | |
1293 | } | |
1294 | ||
1295 | hdr = (struct ieee80211_hdr *)skb->data; | |
1296 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { | |
1297 | /* The multicast ring will be sent after the DTIM */ | |
1298 | ring = dev->dma.tx_ring4; | |
1299 | /* Set the more-data bit. Ucode will clear it on | |
1300 | * the last frame for us. */ | |
1301 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1302 | } else { | |
1303 | /* Decide by priority where to put this frame. */ | |
1304 | ring = priority_to_txring(dev, ctl->queue); | |
1305 | } | |
1306 | ||
e4d6b795 MB |
1307 | spin_lock_irqsave(&ring->lock, flags); |
1308 | B43_WARN_ON(!ring->tx); | |
1309 | if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) { | |
1310 | b43warn(dev->wl, "DMA queue overflow\n"); | |
1311 | err = -ENOSPC; | |
1312 | goto out_unlock; | |
1313 | } | |
1314 | /* Check if the queue was stopped in mac80211, | |
1315 | * but we got called nevertheless. | |
1316 | * That would be a mac80211 bug. */ | |
1317 | B43_WARN_ON(ring->stopped); | |
1318 | ||
1319 | err = dma_tx_fragment(ring, skb, ctl); | |
09552ccd MB |
1320 | if (unlikely(err == -ENOKEY)) { |
1321 | /* Drop this packet, as we don't have the encryption key | |
1322 | * anymore and must not transmit it unencrypted. */ | |
1323 | dev_kfree_skb_any(skb); | |
1324 | err = 0; | |
1325 | goto out_unlock; | |
1326 | } | |
e4d6b795 MB |
1327 | if (unlikely(err)) { |
1328 | b43err(dev->wl, "DMA tx mapping failure\n"); | |
1329 | goto out_unlock; | |
1330 | } | |
1331 | ring->nr_tx_packets++; | |
1332 | if ((free_slots(ring) < SLOTS_PER_PACKET) || | |
1333 | should_inject_overflow(ring)) { | |
1334 | /* This TX ring is full. */ | |
1335 | ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring)); | |
1336 | ring->stopped = 1; | |
1337 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1338 | b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); | |
1339 | } | |
1340 | } | |
280d0e16 | 1341 | out_unlock: |
e4d6b795 MB |
1342 | spin_unlock_irqrestore(&ring->lock, flags); |
1343 | ||
1344 | return err; | |
1345 | } | |
1346 | ||
1347 | void b43_dma_handle_txstatus(struct b43_wldev *dev, | |
1348 | const struct b43_txstatus *status) | |
1349 | { | |
1350 | const struct b43_dma_ops *ops; | |
1351 | struct b43_dmaring *ring; | |
1352 | struct b43_dmadesc_generic *desc; | |
1353 | struct b43_dmadesc_meta *meta; | |
1354 | int slot; | |
1355 | ||
1356 | ring = parse_cookie(dev, status->cookie, &slot); | |
1357 | if (unlikely(!ring)) | |
1358 | return; | |
1359 | B43_WARN_ON(!irqs_disabled()); | |
1360 | spin_lock(&ring->lock); | |
1361 | ||
1362 | B43_WARN_ON(!ring->tx); | |
1363 | ops = ring->ops; | |
1364 | while (1) { | |
1365 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
1366 | desc = ops->idx2desc(ring, slot, &meta); | |
1367 | ||
1368 | if (meta->skb) | |
1369 | unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, | |
1370 | 1); | |
1371 | else | |
1372 | unmap_descbuffer(ring, meta->dmaaddr, | |
eb189d8b | 1373 | b43_txhdr_size(dev), 1); |
e4d6b795 MB |
1374 | |
1375 | if (meta->is_last_fragment) { | |
1376 | B43_WARN_ON(!meta->skb); | |
1377 | /* Call back to inform the ieee80211 subsystem about the | |
1378 | * status of the transmission. | |
1379 | * Some fields of txstat are already filled in dma_tx(). | |
1380 | */ | |
1381 | if (status->acked) { | |
1382 | meta->txstat.flags |= IEEE80211_TX_STATUS_ACK; | |
1383 | } else { | |
1384 | if (!(meta->txstat.control.flags | |
1385 | & IEEE80211_TXCTL_NO_ACK)) | |
1386 | meta->txstat.excessive_retries = 1; | |
1387 | } | |
1388 | if (status->frame_count == 0) { | |
1389 | /* The frame was not transmitted at all. */ | |
1390 | meta->txstat.retry_count = 0; | |
1391 | } else | |
1392 | meta->txstat.retry_count = status->frame_count - 1; | |
1393 | ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, | |
1394 | &(meta->txstat)); | |
1395 | /* skb is freed by ieee80211_tx_status_irqsafe() */ | |
1396 | meta->skb = NULL; | |
1397 | } else { | |
1398 | /* No need to call free_descriptor_buffer here, as | |
1399 | * this is only the txhdr, which is not allocated. | |
1400 | */ | |
1401 | B43_WARN_ON(meta->skb); | |
1402 | } | |
1403 | ||
1404 | /* Everything unmapped and free'd. So it's not used anymore. */ | |
1405 | ring->used_slots--; | |
1406 | ||
1407 | if (meta->is_last_fragment) | |
1408 | break; | |
1409 | slot = next_slot(ring, slot); | |
1410 | } | |
1411 | dev->stats.last_tx = jiffies; | |
1412 | if (ring->stopped) { | |
1413 | B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET); | |
1414 | ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring)); | |
1415 | ring->stopped = 0; | |
1416 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1417 | b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index); | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | spin_unlock(&ring->lock); | |
1422 | } | |
1423 | ||
1424 | void b43_dma_get_tx_stats(struct b43_wldev *dev, | |
1425 | struct ieee80211_tx_queue_stats *stats) | |
1426 | { | |
1427 | const int nr_queues = dev->wl->hw->queues; | |
1428 | struct b43_dmaring *ring; | |
1429 | struct ieee80211_tx_queue_stats_data *data; | |
1430 | unsigned long flags; | |
1431 | int i; | |
1432 | ||
1433 | for (i = 0; i < nr_queues; i++) { | |
1434 | data = &(stats->data[i]); | |
1435 | ring = priority_to_txring(dev, i); | |
1436 | ||
1437 | spin_lock_irqsave(&ring->lock, flags); | |
1438 | data->len = ring->used_slots / SLOTS_PER_PACKET; | |
1439 | data->limit = ring->nr_slots / SLOTS_PER_PACKET; | |
1440 | data->count = ring->nr_tx_packets; | |
1441 | spin_unlock_irqrestore(&ring->lock, flags); | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | static void dma_rx(struct b43_dmaring *ring, int *slot) | |
1446 | { | |
1447 | const struct b43_dma_ops *ops = ring->ops; | |
1448 | struct b43_dmadesc_generic *desc; | |
1449 | struct b43_dmadesc_meta *meta; | |
1450 | struct b43_rxhdr_fw4 *rxhdr; | |
1451 | struct sk_buff *skb; | |
1452 | u16 len; | |
1453 | int err; | |
1454 | dma_addr_t dmaaddr; | |
1455 | ||
1456 | desc = ops->idx2desc(ring, *slot, &meta); | |
1457 | ||
1458 | sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); | |
1459 | skb = meta->skb; | |
1460 | ||
1461 | if (ring->index == 3) { | |
1462 | /* We received an xmit status. */ | |
1463 | struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data; | |
1464 | int i = 0; | |
1465 | ||
1466 | while (hw->cookie == 0) { | |
1467 | if (i > 100) | |
1468 | break; | |
1469 | i++; | |
1470 | udelay(2); | |
1471 | barrier(); | |
1472 | } | |
1473 | b43_handle_hwtxstatus(ring->dev, hw); | |
1474 | /* recycle the descriptor buffer. */ | |
1475 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1476 | ring->rx_buffersize); | |
1477 | ||
1478 | return; | |
1479 | } | |
1480 | rxhdr = (struct b43_rxhdr_fw4 *)skb->data; | |
1481 | len = le16_to_cpu(rxhdr->frame_len); | |
1482 | if (len == 0) { | |
1483 | int i = 0; | |
1484 | ||
1485 | do { | |
1486 | udelay(2); | |
1487 | barrier(); | |
1488 | len = le16_to_cpu(rxhdr->frame_len); | |
1489 | } while (len == 0 && i++ < 5); | |
1490 | if (unlikely(len == 0)) { | |
1491 | /* recycle the descriptor buffer. */ | |
1492 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1493 | ring->rx_buffersize); | |
1494 | goto drop; | |
1495 | } | |
1496 | } | |
1497 | if (unlikely(len > ring->rx_buffersize)) { | |
1498 | /* The data did not fit into one descriptor buffer | |
1499 | * and is split over multiple buffers. | |
1500 | * This should never happen, as we try to allocate buffers | |
1501 | * big enough. So simply ignore this packet. | |
1502 | */ | |
1503 | int cnt = 0; | |
1504 | s32 tmp = len; | |
1505 | ||
1506 | while (1) { | |
1507 | desc = ops->idx2desc(ring, *slot, &meta); | |
1508 | /* recycle the descriptor buffer. */ | |
1509 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1510 | ring->rx_buffersize); | |
1511 | *slot = next_slot(ring, *slot); | |
1512 | cnt++; | |
1513 | tmp -= ring->rx_buffersize; | |
1514 | if (tmp <= 0) | |
1515 | break; | |
1516 | } | |
1517 | b43err(ring->dev->wl, "DMA RX buffer too small " | |
1518 | "(len: %u, buffer: %u, nr-dropped: %d)\n", | |
1519 | len, ring->rx_buffersize, cnt); | |
1520 | goto drop; | |
1521 | } | |
1522 | ||
1523 | dmaaddr = meta->dmaaddr; | |
1524 | err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); | |
1525 | if (unlikely(err)) { | |
1526 | b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n"); | |
1527 | sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize); | |
1528 | goto drop; | |
1529 | } | |
1530 | ||
1531 | unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); | |
1532 | skb_put(skb, len + ring->frameoffset); | |
1533 | skb_pull(skb, ring->frameoffset); | |
1534 | ||
1535 | b43_rx(ring->dev, skb, rxhdr); | |
1536 | drop: | |
1537 | return; | |
1538 | } | |
1539 | ||
1540 | void b43_dma_rx(struct b43_dmaring *ring) | |
1541 | { | |
1542 | const struct b43_dma_ops *ops = ring->ops; | |
1543 | int slot, current_slot; | |
1544 | int used_slots = 0; | |
1545 | ||
1546 | B43_WARN_ON(ring->tx); | |
1547 | current_slot = ops->get_current_rxslot(ring); | |
1548 | B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots)); | |
1549 | ||
1550 | slot = ring->current_slot; | |
1551 | for (; slot != current_slot; slot = next_slot(ring, slot)) { | |
1552 | dma_rx(ring, &slot); | |
1553 | update_max_used_slots(ring, ++used_slots); | |
1554 | } | |
1555 | ops->set_current_rxslot(ring, slot); | |
1556 | ring->current_slot = slot; | |
1557 | } | |
1558 | ||
1559 | static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring) | |
1560 | { | |
1561 | unsigned long flags; | |
1562 | ||
1563 | spin_lock_irqsave(&ring->lock, flags); | |
1564 | B43_WARN_ON(!ring->tx); | |
1565 | ring->ops->tx_suspend(ring); | |
1566 | spin_unlock_irqrestore(&ring->lock, flags); | |
1567 | } | |
1568 | ||
1569 | static void b43_dma_tx_resume_ring(struct b43_dmaring *ring) | |
1570 | { | |
1571 | unsigned long flags; | |
1572 | ||
1573 | spin_lock_irqsave(&ring->lock, flags); | |
1574 | B43_WARN_ON(!ring->tx); | |
1575 | ring->ops->tx_resume(ring); | |
1576 | spin_unlock_irqrestore(&ring->lock, flags); | |
1577 | } | |
1578 | ||
1579 | void b43_dma_tx_suspend(struct b43_wldev *dev) | |
1580 | { | |
1581 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); | |
1582 | b43_dma_tx_suspend_ring(dev->dma.tx_ring0); | |
1583 | b43_dma_tx_suspend_ring(dev->dma.tx_ring1); | |
1584 | b43_dma_tx_suspend_ring(dev->dma.tx_ring2); | |
1585 | b43_dma_tx_suspend_ring(dev->dma.tx_ring3); | |
1586 | b43_dma_tx_suspend_ring(dev->dma.tx_ring4); | |
1587 | b43_dma_tx_suspend_ring(dev->dma.tx_ring5); | |
1588 | } | |
1589 | ||
1590 | void b43_dma_tx_resume(struct b43_wldev *dev) | |
1591 | { | |
1592 | b43_dma_tx_resume_ring(dev->dma.tx_ring5); | |
1593 | b43_dma_tx_resume_ring(dev->dma.tx_ring4); | |
1594 | b43_dma_tx_resume_ring(dev->dma.tx_ring3); | |
1595 | b43_dma_tx_resume_ring(dev->dma.tx_ring2); | |
1596 | b43_dma_tx_resume_ring(dev->dma.tx_ring1); | |
1597 | b43_dma_tx_resume_ring(dev->dma.tx_ring0); | |
1598 | b43_power_saving_ctl_bits(dev, 0); | |
1599 | } |