projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e4d6b795 MB |
1 | #ifndef B43_DMA_H_ |
| 2 | #define B43_DMA_H_ | |
| 3 | ||
| 4 | #include <linux/list.h> | |
| 5 | #include <linux/spinlock.h> | |
| 6 | #include <linux/workqueue.h> | |
| 7 | #include <linux/linkage.h> | |
| 8 | #include <asm/atomic.h> | |
| 9 | ||
| 10 | #include "b43.h" | |
| 11 | ||
| 12 | /* DMA-Interrupt reasons. */ | |
| 13 | #define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \ | |
| 14 | | (1 << 14) | (1 << 15)) | |
| 15 | #define B43_DMAIRQ_NONFATALMASK (1 << 13) | |
| 16 | #define B43_DMAIRQ_RX_DONE (1 << 16) | |
| 17 | ||
| 18 | /*** 32-bit DMA Engine. ***/ | |
| 19 | ||
| 20 | /* 32-bit DMA controller registers. */ | |
| 21 | #define B43_DMA32_TXCTL 0x00 | |
| 22 | #define B43_DMA32_TXENABLE 0x00000001 | |
| 23 | #define B43_DMA32_TXSUSPEND 0x00000002 | |
| 24 | #define B43_DMA32_TXLOOPBACK 0x00000004 | |
| 25 | #define B43_DMA32_TXFLUSH 0x00000010 | |
| 26 | #define B43_DMA32_TXADDREXT_MASK 0x00030000 | |
| 27 | #define B43_DMA32_TXADDREXT_SHIFT 16 | |
| 28 | #define B43_DMA32_TXRING 0x04 | |
| 29 | #define B43_DMA32_TXINDEX 0x08 | |
| 30 | #define B43_DMA32_TXSTATUS 0x0C | |
| 31 | #define B43_DMA32_TXDPTR 0x00000FFF | |
| 32 | #define B43_DMA32_TXSTATE 0x0000F000 | |
| 33 | #define B43_DMA32_TXSTAT_DISABLED 0x00000000 | |
| 34 | #define B43_DMA32_TXSTAT_ACTIVE 0x00001000 | |
| 35 | #define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000 | |
| 36 | #define B43_DMA32_TXSTAT_STOPPED 0x00003000 | |
| 37 | #define B43_DMA32_TXSTAT_SUSP 0x00004000 | |
| 38 | #define B43_DMA32_TXERROR 0x000F0000 | |
| 39 | #define B43_DMA32_TXERR_NOERR 0x00000000 | |
| 40 | #define B43_DMA32_TXERR_PROT 0x00010000 | |
| 41 | #define B43_DMA32_TXERR_UNDERRUN 0x00020000 | |
| 42 | #define B43_DMA32_TXERR_BUFREAD 0x00030000 | |
| 43 | #define B43_DMA32_TXERR_DESCREAD 0x00040000 | |
| 44 | #define B43_DMA32_TXACTIVE 0xFFF00000 | |
| 45 | #define B43_DMA32_RXCTL 0x10 | |
| 46 | #define B43_DMA32_RXENABLE 0x00000001 | |
| 47 | #define B43_DMA32_RXFROFF_MASK 0x000000FE | |
| 48 | #define B43_DMA32_RXFROFF_SHIFT 1 | |
| 49 | #define B43_DMA32_RXDIRECTFIFO 0x00000100 | |
| 50 | #define B43_DMA32_RXADDREXT_MASK 0x00030000 | |
| 51 | #define B43_DMA32_RXADDREXT_SHIFT 16 | |
| 52 | #define B43_DMA32_RXRING 0x14 | |
| 53 | #define B43_DMA32_RXINDEX 0x18 | |
| 54 | #define B43_DMA32_RXSTATUS 0x1C | |
| 55 | #define B43_DMA32_RXDPTR 0x00000FFF | |
| 56 | #define B43_DMA32_RXSTATE 0x0000F000 | |
| 57 | #define B43_DMA32_RXSTAT_DISABLED 0x00000000 | |
| 58 | #define B43_DMA32_RXSTAT_ACTIVE 0x00001000 | |
| 59 | #define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000 | |
| 60 | #define B43_DMA32_RXSTAT_STOPPED 0x00003000 | |
| 61 | #define B43_DMA32_RXERROR 0x000F0000 | |
| 62 | #define B43_DMA32_RXERR_NOERR 0x00000000 | |
| 63 | #define B43_DMA32_RXERR_PROT 0x00010000 | |
| 64 | #define B43_DMA32_RXERR_OVERFLOW 0x00020000 | |
| 65 | #define B43_DMA32_RXERR_BUFWRITE 0x00030000 | |
| 66 | #define B43_DMA32_RXERR_DESCREAD 0x00040000 | |
| 67 | #define B43_DMA32_RXACTIVE 0xFFF00000 | |
| 68 | ||
| 69 | /* 32-bit DMA descriptor. */ | |
| 70 | struct b43_dmadesc32 { | |
| 71 | __le32 control; | |
| 72 | __le32 address; | |
| 73 | } __attribute__ ((__packed__)); | |
| 74 | #define B43_DMA32_DCTL_BYTECNT 0x00001FFF | |
| 75 | #define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000 | |
| 76 | #define B43_DMA32_DCTL_ADDREXT_SHIFT 16 | |
| 77 | #define B43_DMA32_DCTL_DTABLEEND 0x10000000 | |
| 78 | #define B43_DMA32_DCTL_IRQ 0x20000000 | |
| 79 | #define B43_DMA32_DCTL_FRAMEEND 0x40000000 | |
| 80 | #define B43_DMA32_DCTL_FRAMESTART 0x80000000 | |
| 81 | ||
| 82 | /*** 64-bit DMA Engine. ***/ | |
| 83 | ||
| 84 | /* 64-bit DMA controller registers. */ | |
| 85 | #define B43_DMA64_TXCTL 0x00 | |
| 86 | #define B43_DMA64_TXENABLE 0x00000001 | |
| 87 | #define B43_DMA64_TXSUSPEND 0x00000002 | |
| 88 | #define B43_DMA64_TXLOOPBACK 0x00000004 | |
| 89 | #define B43_DMA64_TXFLUSH 0x00000010 | |
| 90 | #define B43_DMA64_TXADDREXT_MASK 0x00030000 | |
| 91 | #define B43_DMA64_TXADDREXT_SHIFT 16 | |
| 92 | #define B43_DMA64_TXINDEX 0x04 | |
| 93 | #define B43_DMA64_TXRINGLO 0x08 | |
| 94 | #define B43_DMA64_TXRINGHI 0x0C | |
| 95 | #define B43_DMA64_TXSTATUS 0x10 | |
| 96 | #define B43_DMA64_TXSTATDPTR 0x00001FFF | |
| 97 | #define B43_DMA64_TXSTAT 0xF0000000 | |
| 98 | #define B43_DMA64_TXSTAT_DISABLED 0x00000000 | |
| 99 | #define B43_DMA64_TXSTAT_ACTIVE 0x10000000 | |
| 100 | #define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000 | |
| 101 | #define B43_DMA64_TXSTAT_STOPPED 0x30000000 | |
| 102 | #define B43_DMA64_TXSTAT_SUSP 0x40000000 | |
| 103 | #define B43_DMA64_TXERROR 0x14 | |
| 104 | #define B43_DMA64_TXERRDPTR 0x0001FFFF | |
| 105 | #define B43_DMA64_TXERR 0xF0000000 | |
| 106 | #define B43_DMA64_TXERR_NOERR 0x00000000 | |
| 107 | #define B43_DMA64_TXERR_PROT 0x10000000 | |
| 108 | #define B43_DMA64_TXERR_UNDERRUN 0x20000000 | |
| 109 | #define B43_DMA64_TXERR_TRANSFER 0x30000000 | |
| 110 | #define B43_DMA64_TXERR_DESCREAD 0x40000000 | |
| 111 | #define B43_DMA64_TXERR_CORE 0x50000000 | |
| 112 | #define B43_DMA64_RXCTL 0x20 | |
| 113 | #define B43_DMA64_RXENABLE 0x00000001 | |
| 114 | #define B43_DMA64_RXFROFF_MASK 0x000000FE | |
| 115 | #define B43_DMA64_RXFROFF_SHIFT 1 | |
| 116 | #define B43_DMA64_RXDIRECTFIFO 0x00000100 | |
| 117 | #define B43_DMA64_RXADDREXT_MASK 0x00030000 | |
| 118 | #define B43_DMA64_RXADDREXT_SHIFT 16 | |
| 119 | #define B43_DMA64_RXINDEX 0x24 | |
| 120 | #define B43_DMA64_RXRINGLO 0x28 | |
| 121 | #define B43_DMA64_RXRINGHI 0x2C | |
| 122 | #define B43_DMA64_RXSTATUS 0x30 | |
| 123 | #define B43_DMA64_RXSTATDPTR 0x00001FFF | |
| 124 | #define B43_DMA64_RXSTAT 0xF0000000 | |
| 125 | #define B43_DMA64_RXSTAT_DISABLED 0x00000000 | |
| 126 | #define B43_DMA64_RXSTAT_ACTIVE 0x10000000 | |
| 127 | #define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000 | |
| 128 | #define B43_DMA64_RXSTAT_STOPPED 0x30000000 | |
| 129 | #define B43_DMA64_RXSTAT_SUSP 0x40000000 | |
| 130 | #define B43_DMA64_RXERROR 0x34 | |
| 131 | #define B43_DMA64_RXERRDPTR 0x0001FFFF | |
| 132 | #define B43_DMA64_RXERR 0xF0000000 | |
| 133 | #define B43_DMA64_RXERR_NOERR 0x00000000 | |
| 134 | #define B43_DMA64_RXERR_PROT 0x10000000 | |
| 135 | #define B43_DMA64_RXERR_UNDERRUN 0x20000000 | |
| 136 | #define B43_DMA64_RXERR_TRANSFER 0x30000000 | |
| 137 | #define B43_DMA64_RXERR_DESCREAD 0x40000000 | |
| 138 | #define B43_DMA64_RXERR_CORE 0x50000000 | |
| 139 | ||
| 140 | /* 64-bit DMA descriptor. */ | |
| 141 | struct b43_dmadesc64 { | |
| 142 | __le32 control0; | |
| 143 | __le32 control1; | |
| 144 | __le32 address_low; | |
| 145 | __le32 address_high; | |
| 146 | } __attribute__ ((__packed__)); | |
| 147 | #define B43_DMA64_DCTL0_DTABLEEND 0x10000000 | |
| 148 | #define B43_DMA64_DCTL0_IRQ 0x20000000 | |
| 149 | #define B43_DMA64_DCTL0_FRAMEEND 0x40000000 | |
| 150 | #define B43_DMA64_DCTL0_FRAMESTART 0x80000000 | |
| 151 | #define B43_DMA64_DCTL1_BYTECNT 0x00001FFF | |
| 152 | #define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000 | |
| 153 | #define B43_DMA64_DCTL1_ADDREXT_SHIFT 16 | |
| 154 | ||
| 155 | struct b43_dmadesc_generic { | |
| 156 | union { | |
| 157 | struct b43_dmadesc32 dma32; | |
| 158 | struct b43_dmadesc64 dma64; | |
| 159 | } __attribute__ ((__packed__)); | |
| 160 | } __attribute__ ((__packed__)); | |
| 161 | ||
| 162 | /* Misc DMA constants */ | |
| 163 | #define B43_DMA_RINGMEMSIZE PAGE_SIZE | |
| 164 | #define B43_DMA0_RX_FRAMEOFFSET 30 | |
| 165 | #define B43_DMA3_RX_FRAMEOFFSET 0 | |
| 166 | ||
| 167 | /* DMA engine tuning knobs */ | |
| 168 | #define B43_TXRING_SLOTS 128 | |
| 169 | #define B43_RXRING_SLOTS 64 | |
| 170 | #define B43_DMA0_RX_BUFFERSIZE (2304 + 100) | |
| 171 | #define B43_DMA3_RX_BUFFERSIZE 16 | |
| 172 | ||
| e4d6b795 MB |
173 | struct sk_buff; |
| 174 | struct b43_private; | |
| 175 | struct b43_txstatus; | |
| 176 | ||
| 177 | struct b43_dmadesc_meta { | |
| 178 | /* The kernel DMA-able buffer. */ | |
| 179 | struct sk_buff *skb; | |
| 180 | /* DMA base bus-address of the descriptor buffer. */ | |
| 181 | dma_addr_t dmaaddr; | |
| 182 | /* ieee80211 TX status. Only used once per 802.11 frag. */ | |
| 183 | bool is_last_fragment; | |
| 184 | struct ieee80211_tx_status txstat; | |
| 185 | }; | |
| 186 | ||
| 187 | struct b43_dmaring; | |
| 188 | ||
| 189 | /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */ | |
| 190 | struct b43_dma_ops { | |
| 191 | struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring, | |
| 192 | int slot, | |
| 193 | struct b43_dmadesc_meta ** | |
| 194 | meta); | |
| 195 | void (*fill_descriptor) (struct b43_dmaring * ring, | |
| 196 | struct b43_dmadesc_generic * desc, | |
| 197 | dma_addr_t dmaaddr, u16 bufsize, int start, | |
| 198 | int end, int irq); | |
| 199 | void (*poke_tx) (struct b43_dmaring * ring, int slot); | |
| 200 | void (*tx_suspend) (struct b43_dmaring * ring); | |
| 201 | void (*tx_resume) (struct b43_dmaring * ring); | |
| 202 | int (*get_current_rxslot) (struct b43_dmaring * ring); | |
| 203 | void (*set_current_rxslot) (struct b43_dmaring * ring, int slot); | |
| 204 | }; | |
| 205 | ||
| 206 | struct b43_dmaring { | |
| 207 | /* Lowlevel DMA ops. */ | |
| 208 | const struct b43_dma_ops *ops; | |
| 209 | /* Kernel virtual base address of the ring memory. */ | |
| 210 | void *descbase; | |
| 211 | /* Meta data about all descriptors. */ | |
| 212 | struct b43_dmadesc_meta *meta; | |
| 213 | /* Cache of TX headers for each slot. | |
| 214 | * This is to avoid an allocation on each TX. | |
| 215 | * This is NULL for an RX ring. | |
| 216 | */ | |
| 217 | u8 *txhdr_cache; | |
| 218 | /* (Unadjusted) DMA base bus-address of the ring memory. */ | |
| 219 | dma_addr_t dmabase; | |
| 220 | /* Number of descriptor slots in the ring. */ | |
| 221 | int nr_slots; | |
| 222 | /* Number of used descriptor slots. */ | |
| 223 | int used_slots; | |
| 224 | /* Currently used slot in the ring. */ | |
| 225 | int current_slot; | |
| 226 | /* Total number of packets sent. Statistics only. */ | |
| 227 | unsigned int nr_tx_packets; | |
| 228 | /* Frameoffset in octets. */ | |
| 229 | u32 frameoffset; | |
| 230 | /* Descriptor buffer size. */ | |
| 231 | u16 rx_buffersize; | |
| 232 | /* The MMIO base register of the DMA controller. */ | |
| 233 | u16 mmio_base; | |
| 234 | /* DMA controller index number (0-5). */ | |
| 235 | int index; | |
| 236 | /* Boolean. Is this a TX ring? */ | |
| 237 | bool tx; | |
| 238 | /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */ | |
| 239 | bool dma64; | |
| 240 | /* Boolean. Is this ring stopped at ieee80211 level? */ | |
| 241 | bool stopped; | |
| 242 | /* Lock, only used for TX. */ | |
| 243 | spinlock_t lock; | |
| 244 | struct b43_wldev *dev; | |
| 245 | #ifdef CONFIG_B43_DEBUG | |
| 246 | /* Maximum number of used slots. */ | |
| 247 | int max_used_slots; | |
| 248 | /* Last time we injected a ring overflow. */ | |
| 249 | unsigned long last_injected_overflow; | |
| 250 | #endif /* CONFIG_B43_DEBUG */ | |
| 251 | }; | |
| 252 | ||
| 253 | static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset) | |
| 254 | { | |
| 255 | return b43_read32(ring->dev, ring->mmio_base + offset); | |
| 256 | } | |
| 257 | ||
| 258 | static inline | |
| 259 | void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value) | |
| 260 | { | |
| 261 | b43_write32(ring->dev, ring->mmio_base + offset, value); | |
| 262 | } | |
| 263 | ||
| 264 | int b43_dma_init(struct b43_wldev *dev); | |
| 265 | void b43_dma_free(struct b43_wldev *dev); | |
| 266 | ||
| 267 | int b43_dmacontroller_rx_reset(struct b43_wldev *dev, | |
| 268 | u16 dmacontroller_mmio_base, int dma64); | |
| 269 | int b43_dmacontroller_tx_reset(struct b43_wldev *dev, | |
| 270 | u16 dmacontroller_mmio_base, int dma64); | |
| 271 | ||
| 272 | u16 b43_dmacontroller_base(int dma64bit, int dmacontroller_idx); | |
| 273 | ||
| 274 | void b43_dma_tx_suspend(struct b43_wldev *dev); | |
| 275 | void b43_dma_tx_resume(struct b43_wldev *dev); | |
| 276 | ||
| 277 | void b43_dma_get_tx_stats(struct b43_wldev *dev, | |
| 278 | struct ieee80211_tx_queue_stats *stats); | |
| 279 | ||
| 280 | int b43_dma_tx(struct b43_wldev *dev, | |
| 281 | struct sk_buff *skb, struct ieee80211_tx_control *ctl); | |
| 282 | void b43_dma_handle_txstatus(struct b43_wldev *dev, | |
| 283 | const struct b43_txstatus *status); | |
| 284 | ||
| 285 | void b43_dma_rx(struct b43_dmaring *ring); | |
| 286 | ||
| e4d6b795 | 287 | #endif /* B43_DMA_H_ */ |