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iwlwifi: move shared pointers to iwl_priv
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
96cf49a2 41#include <linux/io.h>
e4d6b795
MB		 42#include <linux/dma-mapping.h>
43#include <asm/unaligned.h>
44
45#include "b43.h"
46#include "main.h"
47#include "debugfs.h"
48#include "phy.h"
7b584163 49#include "nphy.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87
e4d6b795
MB		 88static const struct ssb_device_id b43_ssb_tbl[] = {
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 96 SSB_DEVTABLE_END
97};
98
99MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
100
101/* Channel and ratetables are shared for all devices.
102 * They can't be const, because ieee80211 puts some precalculated
103 * data in there. This data is the same for all devices, so we don't
104 * get concurrency issues */
105#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 106 { \
107 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
108 .hw_value = (_rateid), \
109 .flags = (_flags), \
e4d6b795 110 }
8318d78a
JB		 111
112/*
113 * NOTE: When changing this, sync with xmit.c's
114 * b43_plcp_get_bitrate_idx_* functions!
115 */
e4d6b795 116static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 117 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
118 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
122 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
123 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
124 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
125 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 129};
130
131#define b43_a_ratetable (__b43_ratetable + 4)
132#define b43_a_ratetable_size 8
133#define b43_b_ratetable (__b43_ratetable + 0)
134#define b43_b_ratetable_size 4
135#define b43_g_ratetable (__b43_ratetable + 0)
136#define b43_g_ratetable_size 12
137
bb1eeff1
MB		 138#define CHAN4G(_channel, _freq, _flags) { \
139 .band = IEEE80211_BAND_2GHZ, \
140 .center_freq = (_freq), \
141 .hw_value = (_channel), \
142 .flags = (_flags), \
143 .max_antenna_gain = 0, \
144 .max_power = 30, \
145}
96c755a3 146static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 147 CHAN4G(1, 2412, 0),
148 CHAN4G(2, 2417, 0),
149 CHAN4G(3, 2422, 0),
150 CHAN4G(4, 2427, 0),
151 CHAN4G(5, 2432, 0),
152 CHAN4G(6, 2437, 0),
153 CHAN4G(7, 2442, 0),
154 CHAN4G(8, 2447, 0),
155 CHAN4G(9, 2452, 0),
156 CHAN4G(10, 2457, 0),
157 CHAN4G(11, 2462, 0),
158 CHAN4G(12, 2467, 0),
159 CHAN4G(13, 2472, 0),
160 CHAN4G(14, 2484, 0),
161};
162#undef CHAN4G
163
164#define CHAN5G(_channel, _flags) { \
165 .band = IEEE80211_BAND_5GHZ, \
166 .center_freq = 5000 + (5 * (_channel)), \
167 .hw_value = (_channel), \
168 .flags = (_flags), \
169 .max_antenna_gain = 0, \
170 .max_power = 30, \
171}
172static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
173 CHAN5G(32, 0), CHAN5G(34, 0),
174 CHAN5G(36, 0), CHAN5G(38, 0),
175 CHAN5G(40, 0), CHAN5G(42, 0),
176 CHAN5G(44, 0), CHAN5G(46, 0),
177 CHAN5G(48, 0), CHAN5G(50, 0),
178 CHAN5G(52, 0), CHAN5G(54, 0),
179 CHAN5G(56, 0), CHAN5G(58, 0),
180 CHAN5G(60, 0), CHAN5G(62, 0),
181 CHAN5G(64, 0), CHAN5G(66, 0),
182 CHAN5G(68, 0), CHAN5G(70, 0),
183 CHAN5G(72, 0), CHAN5G(74, 0),
184 CHAN5G(76, 0), CHAN5G(78, 0),
185 CHAN5G(80, 0), CHAN5G(82, 0),
186 CHAN5G(84, 0), CHAN5G(86, 0),
187 CHAN5G(88, 0), CHAN5G(90, 0),
188 CHAN5G(92, 0), CHAN5G(94, 0),
189 CHAN5G(96, 0), CHAN5G(98, 0),
190 CHAN5G(100, 0), CHAN5G(102, 0),
191 CHAN5G(104, 0), CHAN5G(106, 0),
192 CHAN5G(108, 0), CHAN5G(110, 0),
193 CHAN5G(112, 0), CHAN5G(114, 0),
194 CHAN5G(116, 0), CHAN5G(118, 0),
195 CHAN5G(120, 0), CHAN5G(122, 0),
196 CHAN5G(124, 0), CHAN5G(126, 0),
197 CHAN5G(128, 0), CHAN5G(130, 0),
198 CHAN5G(132, 0), CHAN5G(134, 0),
199 CHAN5G(136, 0), CHAN5G(138, 0),
200 CHAN5G(140, 0), CHAN5G(142, 0),
201 CHAN5G(144, 0), CHAN5G(145, 0),
202 CHAN5G(146, 0), CHAN5G(147, 0),
203 CHAN5G(148, 0), CHAN5G(149, 0),
204 CHAN5G(150, 0), CHAN5G(151, 0),
205 CHAN5G(152, 0), CHAN5G(153, 0),
206 CHAN5G(154, 0), CHAN5G(155, 0),
207 CHAN5G(156, 0), CHAN5G(157, 0),
208 CHAN5G(158, 0), CHAN5G(159, 0),
209 CHAN5G(160, 0), CHAN5G(161, 0),
210 CHAN5G(162, 0), CHAN5G(163, 0),
211 CHAN5G(164, 0), CHAN5G(165, 0),
212 CHAN5G(166, 0), CHAN5G(168, 0),
213 CHAN5G(170, 0), CHAN5G(172, 0),
214 CHAN5G(174, 0), CHAN5G(176, 0),
215 CHAN5G(178, 0), CHAN5G(180, 0),
216 CHAN5G(182, 0), CHAN5G(184, 0),
217 CHAN5G(186, 0), CHAN5G(188, 0),
218 CHAN5G(190, 0), CHAN5G(192, 0),
219 CHAN5G(194, 0), CHAN5G(196, 0),
220 CHAN5G(198, 0), CHAN5G(200, 0),
221 CHAN5G(202, 0), CHAN5G(204, 0),
222 CHAN5G(206, 0), CHAN5G(208, 0),
223 CHAN5G(210, 0), CHAN5G(212, 0),
224 CHAN5G(214, 0), CHAN5G(216, 0),
225 CHAN5G(218, 0), CHAN5G(220, 0),
226 CHAN5G(222, 0), CHAN5G(224, 0),
227 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 228};
229
bb1eeff1
MB		 230static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
231 CHAN5G(34, 0), CHAN5G(36, 0),
232 CHAN5G(38, 0), CHAN5G(40, 0),
233 CHAN5G(42, 0), CHAN5G(44, 0),
234 CHAN5G(46, 0), CHAN5G(48, 0),
235 CHAN5G(52, 0), CHAN5G(56, 0),
236 CHAN5G(60, 0), CHAN5G(64, 0),
237 CHAN5G(100, 0), CHAN5G(104, 0),
238 CHAN5G(108, 0), CHAN5G(112, 0),
239 CHAN5G(116, 0), CHAN5G(120, 0),
240 CHAN5G(124, 0), CHAN5G(128, 0),
241 CHAN5G(132, 0), CHAN5G(136, 0),
242 CHAN5G(140, 0), CHAN5G(149, 0),
243 CHAN5G(153, 0), CHAN5G(157, 0),
244 CHAN5G(161, 0), CHAN5G(165, 0),
245 CHAN5G(184, 0), CHAN5G(188, 0),
246 CHAN5G(192, 0), CHAN5G(196, 0),
247 CHAN5G(200, 0), CHAN5G(204, 0),
248 CHAN5G(208, 0), CHAN5G(212, 0),
249 CHAN5G(216, 0),
250};
251#undef CHAN5G
252
253static struct ieee80211_supported_band b43_band_5GHz_nphy = {
254 .band = IEEE80211_BAND_5GHZ,
255 .channels = b43_5ghz_nphy_chantable,
256 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
257 .bitrates = b43_a_ratetable,
258 .n_bitrates = b43_a_ratetable_size,
e4d6b795 259};
8318d78a 260
bb1eeff1
MB		 261static struct ieee80211_supported_band b43_band_5GHz_aphy = {
262 .band = IEEE80211_BAND_5GHZ,
263 .channels = b43_5ghz_aphy_chantable,
264 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
265 .bitrates = b43_a_ratetable,
266 .n_bitrates = b43_a_ratetable_size,
8318d78a 267};
e4d6b795 268
8318d78a 269static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 270 .band = IEEE80211_BAND_2GHZ,
271 .channels = b43_2ghz_chantable,
272 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
273 .bitrates = b43_g_ratetable,
274 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 275};
276
e4d6b795
MB		 277static void b43_wireless_core_exit(struct b43_wldev *dev);
278static int b43_wireless_core_init(struct b43_wldev *dev);
279static void b43_wireless_core_stop(struct b43_wldev *dev);
280static int b43_wireless_core_start(struct b43_wldev *dev);
281
282static int b43_ratelimit(struct b43_wl *wl)
283{
284 if (!wl || !wl->current_dev)
285 return 1;
286 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
287 return 1;
288 /* We are up and running.
289 * Ratelimit the messages to avoid DoS over the net. */
290 return net_ratelimit();
291}
292
293void b43info(struct b43_wl *wl, const char *fmt, ...)
294{
295 va_list args;
296
297 if (!b43_ratelimit(wl))
298 return;
299 va_start(args, fmt);
300 printk(KERN_INFO "b43-%s: ",
301 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
302 vprintk(fmt, args);
303 va_end(args);
304}
305
306void b43err(struct b43_wl *wl, const char *fmt, ...)
307{
308 va_list args;
309
310 if (!b43_ratelimit(wl))
311 return;
312 va_start(args, fmt);
313 printk(KERN_ERR "b43-%s ERROR: ",
314 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
315 vprintk(fmt, args);
316 va_end(args);
317}
318
319void b43warn(struct b43_wl *wl, const char *fmt, ...)
320{
321 va_list args;
322
323 if (!b43_ratelimit(wl))
324 return;
325 va_start(args, fmt);
326 printk(KERN_WARNING "b43-%s warning: ",
327 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
328 vprintk(fmt, args);
329 va_end(args);
330}
331
332#if B43_DEBUG
333void b43dbg(struct b43_wl *wl, const char *fmt, ...)
334{
335 va_list args;
336
337 va_start(args, fmt);
338 printk(KERN_DEBUG "b43-%s debug: ",
339 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
340 vprintk(fmt, args);
341 va_end(args);
342}
343#endif /* DEBUG */
344
345static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
346{
347 u32 macctl;
348
349 B43_WARN_ON(offset % 4 != 0);
350
351 macctl = b43_read32(dev, B43_MMIO_MACCTL);
352 if (macctl & B43_MACCTL_BE)
353 val = swab32(val);
354
355 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
356 mmiowb();
357 b43_write32(dev, B43_MMIO_RAM_DATA, val);
358}
359
280d0e16
MB		 360static inline void b43_shm_control_word(struct b43_wldev *dev,
361 u16 routing, u16 offset)
e4d6b795
MB		 362{
363 u32 control;
364
365 /* "offset" is the WORD offset. */
e4d6b795
MB		 366 control = routing;
367 control <<= 16;
368 control |= offset;
369 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
370}
371
372u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
373{
280d0e16
MB		 374 struct b43_wl *wl = dev->wl;
375 unsigned long flags;
e4d6b795
MB		 376 u32 ret;
377
280d0e16 378 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 379 if (routing == B43_SHM_SHARED) {
380 B43_WARN_ON(offset & 0x0001);
381 if (offset & 0x0003) {
382 /* Unaligned access */
383 b43_shm_control_word(dev, routing, offset >> 2);
384 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
385 ret <<= 16;
386 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
387 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
388
280d0e16 389 goto out;
e4d6b795
MB		 390 }
391 offset >>= 2;
392 }
393 b43_shm_control_word(dev, routing, offset);
394 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 395out:
396 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 397
398 return ret;
399}
400
401u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
402{
280d0e16
MB		 403 struct b43_wl *wl = dev->wl;
404 unsigned long flags;
e4d6b795
MB		 405 u16 ret;
406
280d0e16 407 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 408 if (routing == B43_SHM_SHARED) {
409 B43_WARN_ON(offset & 0x0001);
410 if (offset & 0x0003) {
411 /* Unaligned access */
412 b43_shm_control_word(dev, routing, offset >> 2);
413 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
414
280d0e16 415 goto out;
e4d6b795
MB		 416 }
417 offset >>= 2;
418 }
419 b43_shm_control_word(dev, routing, offset);
420 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 421out:
422 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 423
424 return ret;
425}
426
427void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
428{
280d0e16
MB		 429 struct b43_wl *wl = dev->wl;
430 unsigned long flags;
431
432 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 438 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
439 (value >> 16) & 0xffff);
e4d6b795 440 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 441 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
280d0e16 442 goto out;
e4d6b795
MB		 443 }
444 offset >>= 2;
445 }
446 b43_shm_control_word(dev, routing, offset);
e4d6b795 447 b43_write32(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 448out:
449 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 450}
451
452void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
453{
280d0e16
MB		 454 struct b43_wl *wl = dev->wl;
455 unsigned long flags;
456
457 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 458 if (routing == B43_SHM_SHARED) {
459 B43_WARN_ON(offset & 0x0001);
460 if (offset & 0x0003) {
461 /* Unaligned access */
462 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 463 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
280d0e16 464 goto out;
e4d6b795
MB		 465 }
466 offset >>= 2;
467 }
468 b43_shm_control_word(dev, routing, offset);
e4d6b795 469 b43_write16(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 470out:
471 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 472}
473
474/* Read HostFlags */
35f0d354 475u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 476{
35f0d354 477 u64 ret;
e4d6b795
MB		 478
479 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
480 ret <<= 16;
35f0d354
MB		 481 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
482 ret <<= 16;
e4d6b795
MB		 483 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
484
485 return ret;
486}
487
488/* Write HostFlags */
35f0d354 489void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 490{
35f0d354
MB		 491 u16 lo, mi, hi;
492
493 lo = (value & 0x00000000FFFFULL);
494 mi = (value & 0x0000FFFF0000ULL) >> 16;
495 hi = (value & 0xFFFF00000000ULL) >> 32;
496 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
498 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 499}
500
501void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
502{
503 /* We need to be careful. As we read the TSF from multiple
504 * registers, we should take care of register overflows.
505 * In theory, the whole tsf read process should be atomic.
506 * We try to be atomic here, by restaring the read process,
507 * if any of the high registers changed (overflew).
508 */
509 if (dev->dev->id.revision >= 3) {
510 u32 low, high, high2;
511
512 do {
513 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
514 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
515 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
516 } while (unlikely(high != high2));
517
518 *tsf = high;
519 *tsf <<= 32;
520 *tsf |= low;
521 } else {
522 u64 tmp;
523 u16 v0, v1, v2, v3;
524 u16 test1, test2, test3;
525
526 do {
527 v3 = b43_read16(dev, B43_MMIO_TSF_3);
528 v2 = b43_read16(dev, B43_MMIO_TSF_2);
529 v1 = b43_read16(dev, B43_MMIO_TSF_1);
530 v0 = b43_read16(dev, B43_MMIO_TSF_0);
531
532 test3 = b43_read16(dev, B43_MMIO_TSF_3);
533 test2 = b43_read16(dev, B43_MMIO_TSF_2);
534 test1 = b43_read16(dev, B43_MMIO_TSF_1);
535 } while (v3 != test3 || v2 != test2 || v1 != test1);
536
537 *tsf = v3;
538 *tsf <<= 48;
539 tmp = v2;
540 tmp <<= 32;
541 *tsf |= tmp;
542 tmp = v1;
543 tmp <<= 16;
544 *tsf |= tmp;
545 *tsf |= v0;
546 }
547}
548
549static void b43_time_lock(struct b43_wldev *dev)
550{
551 u32 macctl;
552
553 macctl = b43_read32(dev, B43_MMIO_MACCTL);
554 macctl |= B43_MACCTL_TBTTHOLD;
555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
556 /* Commit the write */
557 b43_read32(dev, B43_MMIO_MACCTL);
558}
559
560static void b43_time_unlock(struct b43_wldev *dev)
561{
562 u32 macctl;
563
564 macctl = b43_read32(dev, B43_MMIO_MACCTL);
565 macctl &= ~B43_MACCTL_TBTTHOLD;
566 b43_write32(dev, B43_MMIO_MACCTL, macctl);
567 /* Commit the write */
568 b43_read32(dev, B43_MMIO_MACCTL);
569}
570
571static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
572{
573 /* Be careful with the in-progress timer.
574 * First zero out the low register, so we have a full
575 * register-overflow duration to complete the operation.
576 */
577 if (dev->dev->id.revision >= 3) {
578 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
579 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
580
581 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
582 mmiowb();
583 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
584 mmiowb();
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
586 } else {
587 u16 v0 = (tsf & 0x000000000000FFFFULL);
588 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
589 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
590 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
591
592 b43_write16(dev, B43_MMIO_TSF_0, 0);
593 mmiowb();
594 b43_write16(dev, B43_MMIO_TSF_3, v3);
595 mmiowb();
596 b43_write16(dev, B43_MMIO_TSF_2, v2);
597 mmiowb();
598 b43_write16(dev, B43_MMIO_TSF_1, v1);
599 mmiowb();
600 b43_write16(dev, B43_MMIO_TSF_0, v0);
601 }
602}
603
604void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
605{
606 b43_time_lock(dev);
607 b43_tsf_write_locked(dev, tsf);
608 b43_time_unlock(dev);
609}
610
611static
612void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
613{
614 static const u8 zero_addr[ETH_ALEN] = { 0 };
615 u16 data;
616
617 if (!mac)
618 mac = zero_addr;
619
620 offset |= 0x0020;
621 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
622
623 data = mac[0];
624 data |= mac[1] << 8;
625 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
626 data = mac[2];
627 data |= mac[3] << 8;
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
629 data = mac[4];
630 data |= mac[5] << 8;
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632}
633
634static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
635{
636 const u8 *mac;
637 const u8 *bssid;
638 u8 mac_bssid[ETH_ALEN * 2];
639 int i;
640 u32 tmp;
641
642 bssid = dev->wl->bssid;
643 mac = dev->wl->mac_addr;
644
645 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
646
647 memcpy(mac_bssid, mac, ETH_ALEN);
648 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
649
650 /* Write our MAC address and BSSID to template ram */
651 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
652 tmp = (u32) (mac_bssid[i + 0]);
653 tmp |= (u32) (mac_bssid[i + 1]) << 8;
654 tmp |= (u32) (mac_bssid[i + 2]) << 16;
655 tmp |= (u32) (mac_bssid[i + 3]) << 24;
656 b43_ram_write(dev, 0x20 + i, tmp);
657 }
658}
659
4150c572 660static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 661{
e4d6b795 662 b43_write_mac_bssid_templates(dev);
4150c572 663 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 664}
665
666static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
667{
668 /* slot_time is in usec. */
669 if (dev->phy.type != B43_PHYTYPE_G)
670 return;
671 b43_write16(dev, 0x684, 510 + slot_time);
672 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
673}
674
675static void b43_short_slot_timing_enable(struct b43_wldev *dev)
676{
677 b43_set_slot_time(dev, 9);
678 dev->short_slot = 1;
679}
680
681static void b43_short_slot_timing_disable(struct b43_wldev *dev)
682{
683 b43_set_slot_time(dev, 20);
684 dev->short_slot = 0;
685}
686
687/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
688 * Returns the _previously_ enabled IRQ mask.
689 */
690static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
691{
692 u32 old_mask;
693
694 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
696
697 return old_mask;
698}
699
700/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
701 * Returns the _previously_ enabled IRQ mask.
702 */
703static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
704{
705 u32 old_mask;
706
707 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
708 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
709
710 return old_mask;
711}
712
713/* Synchronize IRQ top- and bottom-half.
714 * IRQs must be masked before calling this.
715 * This must not be called with the irq_lock held.
716 */
717static void b43_synchronize_irq(struct b43_wldev *dev)
718{
719 synchronize_irq(dev->dev->irq);
720 tasklet_kill(&dev->isr_tasklet);
721}
722
723/* DummyTransmission function, as documented on
724 * http://bcm-specs.sipsolutions.net/DummyTransmission
725 */
726void b43_dummy_transmission(struct b43_wldev *dev)
727{
728 struct b43_phy *phy = &dev->phy;
729 unsigned int i, max_loop;
730 u16 value;
731 u32 buffer[5] = {
732 0x00000000,
733 0x00D40000,
734 0x00000000,
735 0x01000000,
736 0x00000000,
737 };
738
739 switch (phy->type) {
740 case B43_PHYTYPE_A:
741 max_loop = 0x1E;
742 buffer[0] = 0x000201CC;
743 break;
744 case B43_PHYTYPE_B:
745 case B43_PHYTYPE_G:
746 max_loop = 0xFA;
747 buffer[0] = 0x000B846E;
748 break;
749 default:
750 B43_WARN_ON(1);
751 return;
752 }
753
754 for (i = 0; i < 5; i++)
755 b43_ram_write(dev, i * 4, buffer[i]);
756
757 /* Commit writes */
758 b43_read32(dev, B43_MMIO_MACCTL);
759
760 b43_write16(dev, 0x0568, 0x0000);
761 b43_write16(dev, 0x07C0, 0x0000);
762 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
763 b43_write16(dev, 0x050C, value);
764 b43_write16(dev, 0x0508, 0x0000);
765 b43_write16(dev, 0x050A, 0x0000);
766 b43_write16(dev, 0x054C, 0x0000);
767 b43_write16(dev, 0x056A, 0x0014);
768 b43_write16(dev, 0x0568, 0x0826);
769 b43_write16(dev, 0x0500, 0x0000);
770 b43_write16(dev, 0x0502, 0x0030);
771
772 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
773 b43_radio_write16(dev, 0x0051, 0x0017);
774 for (i = 0x00; i < max_loop; i++) {
775 value = b43_read16(dev, 0x050E);
776 if (value & 0x0080)
777 break;
778 udelay(10);
779 }
780 for (i = 0x00; i < 0x0A; i++) {
781 value = b43_read16(dev, 0x050E);
782 if (value & 0x0400)
783 break;
784 udelay(10);
785 }
786 for (i = 0x00; i < 0x0A; i++) {
787 value = b43_read16(dev, 0x0690);
788 if (!(value & 0x0100))
789 break;
790 udelay(10);
791 }
792 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
793 b43_radio_write16(dev, 0x0051, 0x0037);
794}
795
796static void key_write(struct b43_wldev *dev,
797 u8 index, u8 algorithm, const u8 * key)
798{
799 unsigned int i;
800 u32 offset;
801 u16 value;
802 u16 kidx;
803
804 /* Key index/algo block */
805 kidx = b43_kidx_to_fw(dev, index);
806 value = ((kidx << 4) | algorithm);
807 b43_shm_write16(dev, B43_SHM_SHARED,
808 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
809
810 /* Write the key to the Key Table Pointer offset */
811 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
812 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
813 value = key[i];
814 value |= (u16) (key[i + 1]) << 8;
815 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
816 }
817}
818
819static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
820{
821 u32 addrtmp[2] = { 0, 0, };
822 u8 per_sta_keys_start = 8;
823
824 if (b43_new_kidx_api(dev))
825 per_sta_keys_start = 4;
826
827 B43_WARN_ON(index < per_sta_keys_start);
828 /* We have two default TX keys and possibly two default RX keys.
829 * Physical mac 0 is mapped to physical key 4 or 8, depending
830 * on the firmware version.
831 * So we must adjust the index here.
832 */
833 index -= per_sta_keys_start;
834
835 if (addr) {
836 addrtmp[0] = addr[0];
837 addrtmp[0] |= ((u32) (addr[1]) << 8);
838 addrtmp[0] |= ((u32) (addr[2]) << 16);
839 addrtmp[0] |= ((u32) (addr[3]) << 24);
840 addrtmp[1] = addr[4];
841 addrtmp[1] |= ((u32) (addr[5]) << 8);
842 }
843
844 if (dev->dev->id.revision >= 5) {
845 /* Receive match transmitter address mechanism */
846 b43_shm_write32(dev, B43_SHM_RCMTA,
847 (index * 2) + 0, addrtmp[0]);
848 b43_shm_write16(dev, B43_SHM_RCMTA,
849 (index * 2) + 1, addrtmp[1]);
850 } else {
851 /* RXE (Receive Engine) and
852 * PSM (Programmable State Machine) mechanism
853 */
854 if (index < 8) {
855 /* TODO write to RCM 16, 19, 22 and 25 */
856 } else {
857 b43_shm_write32(dev, B43_SHM_SHARED,
858 B43_SHM_SH_PSM + (index * 6) + 0,
859 addrtmp[0]);
860 b43_shm_write16(dev, B43_SHM_SHARED,
861 B43_SHM_SH_PSM + (index * 6) + 4,
862 addrtmp[1]);
863 }
864 }
865}
866
867static void do_key_write(struct b43_wldev *dev,
868 u8 index, u8 algorithm,
869 const u8 * key, size_t key_len, const u8 * mac_addr)
870{
871 u8 buf[B43_SEC_KEYSIZE] = { 0, };
872 u8 per_sta_keys_start = 8;
873
874 if (b43_new_kidx_api(dev))
875 per_sta_keys_start = 4;
876
877 B43_WARN_ON(index >= dev->max_nr_keys);
878 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
879
880 if (index >= per_sta_keys_start)
881 keymac_write(dev, index, NULL); /* First zero out mac. */
882 if (key)
883 memcpy(buf, key, key_len);
884 key_write(dev, index, algorithm, buf);
885 if (index >= per_sta_keys_start)
886 keymac_write(dev, index, mac_addr);
887
888 dev->key[index].algorithm = algorithm;
889}
890
891static int b43_key_write(struct b43_wldev *dev,
892 int index, u8 algorithm,
893 const u8 * key, size_t key_len,
894 const u8 * mac_addr,
895 struct ieee80211_key_conf *keyconf)
896{
897 int i;
898 int sta_keys_start;
899
900 if (key_len > B43_SEC_KEYSIZE)
901 return -EINVAL;
902 for (i = 0; i < dev->max_nr_keys; i++) {
903 /* Check that we don't already have this key. */
904 B43_WARN_ON(dev->key[i].keyconf == keyconf);
905 }
906 if (index < 0) {
907 /* Either pairwise key or address is 00:00:00:00:00:00
908 * for transmit-only keys. Search the index. */
909 if (b43_new_kidx_api(dev))
910 sta_keys_start = 4;
911 else
912 sta_keys_start = 8;
913 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
914 if (!dev->key[i].keyconf) {
915 /* found empty */
916 index = i;
917 break;
918 }
919 }
920 if (index < 0) {
921 b43err(dev->wl, "Out of hardware key memory\n");
922 return -ENOSPC;
923 }
924 } else
925 B43_WARN_ON(index > 3);
926
927 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
928 if ((index <= 3) && !b43_new_kidx_api(dev)) {
929 /* Default RX key */
930 B43_WARN_ON(mac_addr);
931 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
932 }
933 keyconf->hw_key_idx = index;
934 dev->key[index].keyconf = keyconf;
935
936 return 0;
937}
938
939static int b43_key_clear(struct b43_wldev *dev, int index)
940{
941 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
942 return -EINVAL;
943 do_key_write(dev, index, B43_SEC_ALGO_NONE,
944 NULL, B43_SEC_KEYSIZE, NULL);
945 if ((index <= 3) && !b43_new_kidx_api(dev)) {
946 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
947 NULL, B43_SEC_KEYSIZE, NULL);
948 }
949 dev->key[index].keyconf = NULL;
950
951 return 0;
952}
953
954static void b43_clear_keys(struct b43_wldev *dev)
955{
956 int i;
957
958 for (i = 0; i < dev->max_nr_keys; i++)
959 b43_key_clear(dev, i);
960}
961
962void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
963{
964 u32 macctl;
965 u16 ucstat;
966 bool hwps;
967 bool awake;
968 int i;
969
970 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
971 (ps_flags & B43_PS_DISABLED));
972 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
973
974 if (ps_flags & B43_PS_ENABLED) {
975 hwps = 1;
976 } else if (ps_flags & B43_PS_DISABLED) {
977 hwps = 0;
978 } else {
979 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
980 // and thus is not an AP and we are associated, set bit 25
981 }
982 if (ps_flags & B43_PS_AWAKE) {
983 awake = 1;
984 } else if (ps_flags & B43_PS_ASLEEP) {
985 awake = 0;
986 } else {
987 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
988 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
989 // successful, set bit26
990 }
991
992/* FIXME: For now we force awake-on and hwps-off */
993 hwps = 0;
994 awake = 1;
995
996 macctl = b43_read32(dev, B43_MMIO_MACCTL);
997 if (hwps)
998 macctl |= B43_MACCTL_HWPS;
999 else
1000 macctl &= ~B43_MACCTL_HWPS;
1001 if (awake)
1002 macctl |= B43_MACCTL_AWAKE;
1003 else
1004 macctl &= ~B43_MACCTL_AWAKE;
1005 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1006 /* Commit write */
1007 b43_read32(dev, B43_MMIO_MACCTL);
1008 if (awake && dev->dev->id.revision >= 5) {
1009 /* Wait for the microcode to wake up. */
1010 for (i = 0; i < 100; i++) {
1011 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1012 B43_SHM_SH_UCODESTAT);
1013 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1014 break;
1015 udelay(10);
1016 }
1017 }
1018}
1019
1020/* Turn the Analog ON/OFF */
1021static void b43_switch_analog(struct b43_wldev *dev, int on)
1022{
7b584163
MB		 1023 switch (dev->phy.type) {
1024 case B43_PHYTYPE_A:
1025 case B43_PHYTYPE_G:
1026 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1027 break;
1028 case B43_PHYTYPE_N:
1029 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1030 on ? 0 : 0x7FFF);
1031 break;
1032 default:
1033 B43_WARN_ON(1);
1034 }
e4d6b795
MB		 1035}
1036
1037void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1038{
1039 u32 tmslow;
1040 u32 macctl;
1041
1042 flags |= B43_TMSLOW_PHYCLKEN;
1043 flags |= B43_TMSLOW_PHYRESET;
1044 ssb_device_enable(dev->dev, flags);
1045 msleep(2); /* Wait for the PLL to turn on. */
1046
1047 /* Now take the PHY out of Reset again */
1048 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1049 tmslow |= SSB_TMSLOW_FGC;
1050 tmslow &= ~B43_TMSLOW_PHYRESET;
1051 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1052 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1053 msleep(1);
1054 tmslow &= ~SSB_TMSLOW_FGC;
1055 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1056 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1057 msleep(1);
1058
1059 /* Turn Analog ON */
1060 b43_switch_analog(dev, 1);
1061
1062 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1063 macctl &= ~B43_MACCTL_GMODE;
1064 if (flags & B43_TMSLOW_GMODE)
1065 macctl |= B43_MACCTL_GMODE;
1066 macctl |= B43_MACCTL_IHR_ENABLED;
1067 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1068}
1069
1070static void handle_irq_transmit_status(struct b43_wldev *dev)
1071{
1072 u32 v0, v1;
1073 u16 tmp;
1074 struct b43_txstatus stat;
1075
1076 while (1) {
1077 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1078 if (!(v0 & 0x00000001))
1079 break;
1080 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1081
1082 stat.cookie = (v0 >> 16);
1083 stat.seq = (v1 & 0x0000FFFF);
1084 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1085 tmp = (v0 & 0x0000FFFF);
1086 stat.frame_count = ((tmp & 0xF000) >> 12);
1087 stat.rts_count = ((tmp & 0x0F00) >> 8);
1088 stat.supp_reason = ((tmp & 0x001C) >> 2);
1089 stat.pm_indicated = !!(tmp & 0x0080);
1090 stat.intermediate = !!(tmp & 0x0040);
1091 stat.for_ampdu = !!(tmp & 0x0020);
1092 stat.acked = !!(tmp & 0x0002);
1093
1094 b43_handle_txstatus(dev, &stat);
1095 }
1096}
1097
1098static void drain_txstatus_queue(struct b43_wldev *dev)
1099{
1100 u32 dummy;
1101
1102 if (dev->dev->id.revision < 5)
1103 return;
1104 /* Read all entries from the microcode TXstatus FIFO
1105 * and throw them away.
1106 */
1107 while (1) {
1108 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1109 if (!(dummy & 0x00000001))
1110 break;
1111 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1112 }
1113}
1114
1115static u32 b43_jssi_read(struct b43_wldev *dev)
1116{
1117 u32 val = 0;
1118
1119 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1120 val <<= 16;
1121 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1122
1123 return val;
1124}
1125
1126static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1127{
1128 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1129 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1130}
1131
1132static void b43_generate_noise_sample(struct b43_wldev *dev)
1133{
1134 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1135 b43_write32(dev, B43_MMIO_MACCMD,
1136 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1137 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1138}
1139
1140static void b43_calculate_link_quality(struct b43_wldev *dev)
1141{
1142 /* Top half of Link Quality calculation. */
1143
1144 if (dev->noisecalc.calculation_running)
1145 return;
1146 dev->noisecalc.channel_at_start = dev->phy.channel;
1147 dev->noisecalc.calculation_running = 1;
1148 dev->noisecalc.nr_samples = 0;
1149
1150 b43_generate_noise_sample(dev);
1151}
1152
1153static void handle_irq_noise(struct b43_wldev *dev)
1154{
1155 struct b43_phy *phy = &dev->phy;
1156 u16 tmp;
1157 u8 noise[4];
1158 u8 i, j;
1159 s32 average;
1160
1161 /* Bottom half of Link Quality calculation. */
1162
1163 B43_WARN_ON(!dev->noisecalc.calculation_running);
1164 if (dev->noisecalc.channel_at_start != phy->channel)
1165 goto drop_calculation;
1a09404a 1166 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1167 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1168 noise[2] == 0x7F || noise[3] == 0x7F)
1169 goto generate_new;
1170
1171 /* Get the noise samples. */
1172 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1173 i = dev->noisecalc.nr_samples;
1174 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1175 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1176 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1177 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1178 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1179 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1180 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1181 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1182 dev->noisecalc.nr_samples++;
1183 if (dev->noisecalc.nr_samples == 8) {
1184 /* Calculate the Link Quality by the noise samples. */
1185 average = 0;
1186 for (i = 0; i < 8; i++) {
1187 for (j = 0; j < 4; j++)
1188 average += dev->noisecalc.samples[i][j];
1189 }
1190 average /= (8 * 4);
1191 average *= 125;
1192 average += 64;
1193 average /= 128;
1194 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1195 tmp = (tmp / 128) & 0x1F;
1196 if (tmp >= 8)
1197 average += 2;
1198 else
1199 average -= 25;
1200 if (tmp == 8)
1201 average -= 72;
1202 else
1203 average -= 48;
1204
1205 dev->stats.link_noise = average;
1206 drop_calculation:
1207 dev->noisecalc.calculation_running = 0;
1208 return;
1209 }
1210 generate_new:
1211 b43_generate_noise_sample(dev);
1212}
1213
1214static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1215{
1216 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1217 ///TODO: PS TBTT
1218 } else {
1219 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1220 b43_power_saving_ctl_bits(dev, 0);
1221 }
e4d6b795 1222 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
aa6c7ae2 1223 dev->dfq_valid = 1;
e4d6b795
MB		 1224}
1225
1226static void handle_irq_atim_end(struct b43_wldev *dev)
1227{
aa6c7ae2
MB		 1228 if (dev->dfq_valid) {
1229 b43_write32(dev, B43_MMIO_MACCMD,
1230 b43_read32(dev, B43_MMIO_MACCMD)
1231 | B43_MACCMD_DFQ_VALID);
1232 dev->dfq_valid = 0;
1233 }
e4d6b795
MB		 1234}
1235
1236static void handle_irq_pmq(struct b43_wldev *dev)
1237{
1238 u32 tmp;
1239
1240 //TODO: AP mode.
1241
1242 while (1) {
1243 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1244 if (!(tmp & 0x00000008))
1245 break;
1246 }
1247 /* 16bit write is odd, but correct. */
1248 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1249}
1250
1251static void b43_write_template_common(struct b43_wldev *dev,
1252 const u8 * data, u16 size,
1253 u16 ram_offset,
1254 u16 shm_size_offset, u8 rate)
1255{
1256 u32 i, tmp;
1257 struct b43_plcp_hdr4 plcp;
1258
1259 plcp.data = 0;
1260 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1261 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1262 ram_offset += sizeof(u32);
1263 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1264 * So leave the first two bytes of the next write blank.
1265 */
1266 tmp = (u32) (data[0]) << 16;
1267 tmp |= (u32) (data[1]) << 24;
1268 b43_ram_write(dev, ram_offset, tmp);
1269 ram_offset += sizeof(u32);
1270 for (i = 2; i < size; i += sizeof(u32)) {
1271 tmp = (u32) (data[i + 0]);
1272 if (i + 1 < size)
1273 tmp |= (u32) (data[i + 1]) << 8;
1274 if (i + 2 < size)
1275 tmp |= (u32) (data[i + 2]) << 16;
1276 if (i + 3 < size)
1277 tmp |= (u32) (data[i + 3]) << 24;
1278 b43_ram_write(dev, ram_offset + i - 2, tmp);
1279 }
1280 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1281 size + sizeof(struct b43_plcp_hdr6));
1282}
1283
5042c507
MB		 1284/* Check if the use of the antenna that ieee80211 told us to
1285 * use is possible. This will fall back to DEFAULT.
1286 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1287u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1288 u8 antenna_nr)
1289{
1290 u8 antenna_mask;
1291
1292 if (antenna_nr == 0) {
1293 /* Zero means "use default antenna". That's always OK. */
1294 return 0;
1295 }
1296
1297 /* Get the mask of available antennas. */
1298 if (dev->phy.gmode)
1299 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1300 else
1301 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1302
1303 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1304 /* This antenna is not available. Fall back to default. */
1305 return 0;
1306 }
1307
1308 return antenna_nr;
1309}
1310
1311static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1312{
1313 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1314 switch (antenna) {
1315 case 0: /* default/diversity */
1316 return B43_ANTENNA_DEFAULT;
1317 case 1: /* Antenna 0 */
1318 return B43_ANTENNA0;
1319 case 2: /* Antenna 1 */
1320 return B43_ANTENNA1;
1321 case 3: /* Antenna 2 */
1322 return B43_ANTENNA2;
1323 case 4: /* Antenna 3 */
1324 return B43_ANTENNA3;
1325 default:
1326 return B43_ANTENNA_DEFAULT;
1327 }
1328}
1329
1330/* Convert a b43 antenna number value to the PHY TX control value. */
1331static u16 b43_antenna_to_phyctl(int antenna)
1332{
1333 switch (antenna) {
1334 case B43_ANTENNA0:
1335 return B43_TXH_PHY_ANT0;
1336 case B43_ANTENNA1:
1337 return B43_TXH_PHY_ANT1;
1338 case B43_ANTENNA2:
1339 return B43_TXH_PHY_ANT2;
1340 case B43_ANTENNA3:
1341 return B43_TXH_PHY_ANT3;
1342 case B43_ANTENNA_AUTO:
1343 return B43_TXH_PHY_ANT01AUTO;
1344 }
1345 B43_WARN_ON(1);
1346 return 0;
1347}
1348
e4d6b795
MB		 1349static void b43_write_beacon_template(struct b43_wldev *dev,
1350 u16 ram_offset,
5042c507 1351 u16 shm_size_offset)
e4d6b795 1352{
47f76ca3 1353 unsigned int i, len, variable_len;
e66fee6a
MB		 1354 const struct ieee80211_mgmt *bcn;
1355 const u8 *ie;
1356 bool tim_found = 0;
5042c507
MB		 1357 unsigned int rate;
1358 u16 ctl;
1359 int antenna;
e4d6b795 1360
e66fee6a
MB		 1361 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1362 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1363 0x200 - sizeof(struct b43_plcp_hdr6));
5042c507 1364 rate = dev->wl->beacon_txctl.tx_rate->hw_value;
e66fee6a
MB		 1365
1366 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1367 len, ram_offset, shm_size_offset, rate);
e66fee6a 1368
5042c507
MB		 1369 /* Write the PHY TX control parameters. */
1370 antenna = b43_antenna_from_ieee80211(dev,
1371 dev->wl->beacon_txctl.antenna_sel_tx);
1372 antenna = b43_antenna_to_phyctl(antenna);
1373 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1374 /* We can't send beacons with short preamble. Would get PHY errors. */
1375 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1376 ctl &= ~B43_TXH_PHY_ANT;
1377 ctl &= ~B43_TXH_PHY_ENC;
1378 ctl |= antenna;
1379 if (b43_is_cck_rate(rate))
1380 ctl |= B43_TXH_PHY_ENC_CCK;
1381 else
1382 ctl |= B43_TXH_PHY_ENC_OFDM;
1383 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1384
e66fee6a
MB		 1385 /* Find the position of the TIM and the DTIM_period value
1386 * and write them to SHM. */
1387 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1388 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1389 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1390 uint8_t ie_id, ie_len;
1391
1392 ie_id = ie[i];
1393 ie_len = ie[i + 1];
1394 if (ie_id == 5) {
1395 u16 tim_position;
1396 u16 dtim_period;
1397 /* This is the TIM Information Element */
1398
1399 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1400 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1401 break;
1402 /* A valid TIM is at least 4 bytes long. */
1403 if (ie_len < 4)
1404 break;
1405 tim_found = 1;
1406
1407 tim_position = sizeof(struct b43_plcp_hdr6);
1408 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1409 tim_position += i;
1410
1411 dtim_period = ie[i + 3];
1412
1413 b43_shm_write16(dev, B43_SHM_SHARED,
1414 B43_SHM_SH_TIMBPOS, tim_position);
1415 b43_shm_write16(dev, B43_SHM_SHARED,
1416 B43_SHM_SH_DTIMPER, dtim_period);
1417 break;
1418 }
1419 i += ie_len + 2;
1420 }
1421 if (!tim_found) {
1422 b43warn(dev->wl, "Did not find a valid TIM IE in "
1423 "the beacon template packet. AP or IBSS operation "
1424 "may be broken.\n");
a82d9922
MB		 1425 } else
1426 b43dbg(dev->wl, "Updated beacon template\n");
e4d6b795
MB		 1427}
1428
1429static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1430 u16 shm_offset, u16 size,
1431 struct ieee80211_rate *rate)
e4d6b795
MB		 1432{
1433 struct b43_plcp_hdr4 plcp;
1434 u32 tmp;
1435 __le16 dur;
1436
1437 plcp.data = 0;
8318d78a 1438 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1439 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1440 dev->wl->vif, size,
8318d78a 1441 rate);
e4d6b795
MB		 1442 /* Write PLCP in two parts and timing for packet transfer */
1443 tmp = le32_to_cpu(plcp.data);
1444 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1445 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1446 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1447}
1448
1449/* Instead of using custom probe response template, this function
1450 * just patches custom beacon template by:
1451 * 1) Changing packet type
1452 * 2) Patching duration field
1453 * 3) Stripping TIM
1454 */
e66fee6a 1455static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1456 u16 *dest_size,
1457 struct ieee80211_rate *rate)
e4d6b795
MB		 1458{
1459 const u8 *src_data;
1460 u8 *dest_data;
1461 u16 src_size, elem_size, src_pos, dest_pos;
1462 __le16 dur;
1463 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1464 size_t ie_start;
1465
1466 src_size = dev->wl->current_beacon->len;
1467 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1468
e66fee6a
MB		 1469 /* Get the start offset of the variable IEs in the packet. */
1470 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1471 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1472
e66fee6a 1473 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1474 return NULL;
e4d6b795
MB		 1475
1476 dest_data = kmalloc(src_size, GFP_ATOMIC);
1477 if (unlikely(!dest_data))
1478 return NULL;
1479
e66fee6a
MB		 1480 /* Copy the static data and all Information Elements, except the TIM. */
1481 memcpy(dest_data, src_data, ie_start);
1482 src_pos = ie_start;
1483 dest_pos = ie_start;
1484 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1485 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1486 if (src_data[src_pos] == 5) {
1487 /* This is the TIM. */
1488 continue;
e4d6b795 1489 }
e66fee6a
MB		 1490 memcpy(dest_data + dest_pos, src_data + src_pos,
1491 elem_size);
1492 dest_pos += elem_size;
e4d6b795
MB		 1493 }
1494 *dest_size = dest_pos;
1495 hdr = (struct ieee80211_hdr *)dest_data;
1496
1497 /* Set the frame control. */
1498 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1499 IEEE80211_STYPE_PROBE_RESP);
1500 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1501 dev->wl->vif, *dest_size,
8318d78a 1502 rate);
e4d6b795
MB		 1503 hdr->duration_id = dur;
1504
1505 return dest_data;
1506}
1507
1508static void b43_write_probe_resp_template(struct b43_wldev *dev,
1509 u16 ram_offset,
8318d78a
JB		 1510 u16 shm_size_offset,
1511 struct ieee80211_rate *rate)
e4d6b795 1512{
e66fee6a 1513 const u8 *probe_resp_data;
e4d6b795
MB		 1514 u16 size;
1515
e66fee6a 1516 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1517 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1518 if (unlikely(!probe_resp_data))
1519 return;
1520
1521 /* Looks like PLCP headers plus packet timings are stored for
1522 * all possible basic rates
1523 */
8318d78a
JB		 1524 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1525 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1526 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1527 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1528
1529 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1530 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1531 size, ram_offset, shm_size_offset,
1532 rate->hw_value);
e4d6b795
MB		 1533 kfree(probe_resp_data);
1534}
1535
c97a4ccc
MB		 1536static void handle_irq_beacon(struct b43_wldev *dev)
1537{
1538 struct b43_wl *wl = dev->wl;
1539 u32 cmd, beacon0_valid, beacon1_valid;
1540
1541 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1542 return;
1543
1544 /* This is the bottom half of the asynchronous beacon update. */
1545
1546 /* Ignore interrupt in the future. */
1547 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1548
1549 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1550 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1551 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1552
1553 /* Schedule interrupt manually, if busy. */
1554 if (beacon0_valid && beacon1_valid) {
1555 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1556 dev->irq_savedstate |= B43_IRQ_BEACON;
1557 return;
1558 }
1559
1560 if (!beacon0_valid) {
1561 if (!wl->beacon0_uploaded) {
5042c507 1562 b43_write_beacon_template(dev, 0x68, 0x18);
c97a4ccc
MB		 1563 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1564 &__b43_ratetable[3]);
1565 wl->beacon0_uploaded = 1;
1566 }
1567 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1568 cmd |= B43_MACCMD_BEACON0_VALID;
1569 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1570 } else if (!beacon1_valid) {
1571 if (!wl->beacon1_uploaded) {
5042c507 1572 b43_write_beacon_template(dev, 0x468, 0x1A);
c97a4ccc
MB		 1573 wl->beacon1_uploaded = 1;
1574 }
1575 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1576 cmd |= B43_MACCMD_BEACON1_VALID;
1577 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1578 }
1579}
1580
a82d9922
MB		 1581static void b43_beacon_update_trigger_work(struct work_struct *work)
1582{
1583 struct b43_wl *wl = container_of(work, struct b43_wl,
1584 beacon_update_trigger);
1585 struct b43_wldev *dev;
1586
1587 mutex_lock(&wl->mutex);
1588 dev = wl->current_dev;
1589 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1590 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1591 /* update beacon right away or defer to irq */
1592 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1593 handle_irq_beacon(dev);
1594 /* The handler might have updated the IRQ mask. */
1595 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1596 dev->irq_savedstate);
1597 mmiowb();
a82d9922
MB		 1598 spin_unlock_irq(&wl->irq_lock);
1599 }
1600 mutex_unlock(&wl->mutex);
1601}
1602
d4df6f1a
MB		 1603/* Asynchronously update the packet templates in template RAM.
1604 * Locking: Requires wl->irq_lock to be locked. */
5042c507
MB		 1605static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon,
1606 const struct ieee80211_tx_control *txctl)
e4d6b795 1607{
e66fee6a
MB		 1608 /* This is the top half of the ansynchronous beacon update.
1609 * The bottom half is the beacon IRQ.
1610 * Beacon update must be asynchronous to avoid sending an
1611 * invalid beacon. This can happen for example, if the firmware
1612 * transmits a beacon while we are updating it. */
e4d6b795 1613
e66fee6a
MB		 1614 if (wl->current_beacon)
1615 dev_kfree_skb_any(wl->current_beacon);
1616 wl->current_beacon = beacon;
5042c507 1617 memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
e66fee6a
MB		 1618 wl->beacon0_uploaded = 0;
1619 wl->beacon1_uploaded = 0;
a82d9922 1620 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1621}
1622
1623static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1624{
1625 u32 tmp;
1626 u16 i, len;
1627
1628 len = min((u16) ssid_len, (u16) 0x100);
1629 for (i = 0; i < len; i += sizeof(u32)) {
1630 tmp = (u32) (ssid[i + 0]);
1631 if (i + 1 < len)
1632 tmp |= (u32) (ssid[i + 1]) << 8;
1633 if (i + 2 < len)
1634 tmp |= (u32) (ssid[i + 2]) << 16;
1635 if (i + 3 < len)
1636 tmp |= (u32) (ssid[i + 3]) << 24;
1637 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1638 }
1639 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1640}
1641
1642static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1643{
1644 b43_time_lock(dev);
1645 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1646 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1647 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1648 } else {
1649 b43_write16(dev, 0x606, (beacon_int >> 6));
1650 b43_write16(dev, 0x610, beacon_int);
1651 }
1652 b43_time_unlock(dev);
a82d9922 1653 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1654}
1655
e4d6b795
MB		 1656static void handle_irq_ucode_debug(struct b43_wldev *dev)
1657{
1658 //TODO
1659}
1660
1661/* Interrupt handler bottom-half */
1662static void b43_interrupt_tasklet(struct b43_wldev *dev)
1663{
1664 u32 reason;
1665 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1666 u32 merged_dma_reason = 0;
21954c36 1667 int i;
e4d6b795
MB		 1668 unsigned long flags;
1669
1670 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1671
1672 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1673
1674 reason = dev->irq_reason;
1675 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1676 dma_reason[i] = dev->dma_reason[i];
1677 merged_dma_reason |= dma_reason[i];
1678 }
1679
1680 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1681 b43err(dev->wl, "MAC transmission error\n");
1682
00e0b8cb 1683 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1684 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1685 rmb();
1686 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1687 atomic_set(&dev->phy.txerr_cnt,
1688 B43_PHY_TX_BADNESS_LIMIT);
1689 b43err(dev->wl, "Too many PHY TX errors, "
1690 "restarting the controller\n");
1691 b43_controller_restart(dev, "PHY TX errors");
1692 }
1693 }
e4d6b795
MB		 1694
1695 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1696 B43_DMAIRQ_NONFATALMASK))) {
1697 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1698 b43err(dev->wl, "Fatal DMA error: "
1699 "0x%08X, 0x%08X, 0x%08X, "
1700 "0x%08X, 0x%08X, 0x%08X\n",
1701 dma_reason[0], dma_reason[1],
1702 dma_reason[2], dma_reason[3],
1703 dma_reason[4], dma_reason[5]);
1704 b43_controller_restart(dev, "DMA error");
1705 mmiowb();
1706 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1707 return;
1708 }
1709 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1710 b43err(dev->wl, "DMA error: "
1711 "0x%08X, 0x%08X, 0x%08X, "
1712 "0x%08X, 0x%08X, 0x%08X\n",
1713 dma_reason[0], dma_reason[1],
1714 dma_reason[2], dma_reason[3],
1715 dma_reason[4], dma_reason[5]);
1716 }
1717 }
1718
1719 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1720 handle_irq_ucode_debug(dev);
1721 if (reason & B43_IRQ_TBTT_INDI)
1722 handle_irq_tbtt_indication(dev);
1723 if (reason & B43_IRQ_ATIM_END)
1724 handle_irq_atim_end(dev);
1725 if (reason & B43_IRQ_BEACON)
1726 handle_irq_beacon(dev);
1727 if (reason & B43_IRQ_PMQ)
1728 handle_irq_pmq(dev);
21954c36
MB		 1729 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1730 ;/* TODO */
1731 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1732 handle_irq_noise(dev);
1733
1734 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1735 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1736 if (b43_using_pio_transfers(dev))
1737 b43_pio_rx(dev->pio.rx_queue);
1738 else
1739 b43_dma_rx(dev->dma.rx_ring);
1740 }
e4d6b795
MB		 1741 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1742 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1743 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1744 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1745 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1746
21954c36 1747 if (reason & B43_IRQ_TX_OK)
e4d6b795 1748 handle_irq_transmit_status(dev);
e4d6b795 1749
e4d6b795
MB		 1750 b43_interrupt_enable(dev, dev->irq_savedstate);
1751 mmiowb();
1752 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1753}
1754
e4d6b795
MB		 1755static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1756{
e4d6b795
MB		 1757 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1758
1759 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1760 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1761 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1762 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1763 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1764 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1765}
1766
1767/* Interrupt handler top-half */
1768static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1769{
1770 irqreturn_t ret = IRQ_NONE;
1771 struct b43_wldev *dev = dev_id;
1772 u32 reason;
1773
1774 if (!dev)
1775 return IRQ_NONE;
1776
1777 spin_lock(&dev->wl->irq_lock);
1778
1779 if (b43_status(dev) < B43_STAT_STARTED)
1780 goto out;
1781 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1782 if (reason == 0xffffffff) /* shared IRQ */
1783 goto out;
1784 ret = IRQ_HANDLED;
1785 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1786 if (!reason)
1787 goto out;
1788
1789 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1790 & 0x0001DC00;
1791 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1792 & 0x0000DC00;
1793 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1794 & 0x0000DC00;
1795 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1796 & 0x0001DC00;
1797 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1798 & 0x0000DC00;
1799 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1800 & 0x0000DC00;
1801
1802 b43_interrupt_ack(dev, reason);
1803 /* disable all IRQs. They are enabled again in the bottom half. */
1804 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1805 /* save the reason code and call our bottom half. */
1806 dev->irq_reason = reason;
1807 tasklet_schedule(&dev->isr_tasklet);
1808 out:
1809 mmiowb();
1810 spin_unlock(&dev->wl->irq_lock);
1811
1812 return ret;
1813}
1814
61cb5dd6
MB		 1815static void do_release_fw(struct b43_firmware_file *fw)
1816{
1817 release_firmware(fw->data);
1818 fw->data = NULL;
1819 fw->filename = NULL;
1820}
1821
e4d6b795
MB		 1822static void b43_release_firmware(struct b43_wldev *dev)
1823{
61cb5dd6
MB		 1824 do_release_fw(&dev->fw.ucode);
1825 do_release_fw(&dev->fw.pcm);
1826 do_release_fw(&dev->fw.initvals);
1827 do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1828}
1829
eb189d8b 1830static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1831{
eb189d8b
MB		 1832 const char *text;
1833
1834 text = "You must go to "
354807e0 1835 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 1836 "and download the latest firmware (version 4).\n";
1837 if (error)
1838 b43err(wl, text);
1839 else
1840 b43warn(wl, text);
e4d6b795
MB		 1841}
1842
1843static int do_request_fw(struct b43_wldev *dev,
1844 const char *name,
61cb5dd6 1845 struct b43_firmware_file *fw)
e4d6b795 1846{
1a09404a 1847 char path[sizeof(modparam_fwpostfix) + 32];
61cb5dd6 1848 const struct firmware *blob;
e4d6b795
MB		 1849 struct b43_fw_header *hdr;
1850 u32 size;
1851 int err;
1852
61cb5dd6
MB		 1853 if (!name) {
1854 /* Don't fetch anything. Free possibly cached firmware. */
1855 do_release_fw(fw);
e4d6b795 1856 return 0;
61cb5dd6
MB		 1857 }
1858 if (fw->filename) {
1859 if (strcmp(fw->filename, name) == 0)
1860 return 0; /* Already have this fw. */
1861 /* Free the cached firmware first. */
1862 do_release_fw(fw);
1863 }
e4d6b795
MB		 1864
1865 snprintf(path, ARRAY_SIZE(path),
1866 "b43%s/%s.fw",
1867 modparam_fwpostfix, name);
61cb5dd6 1868 err = request_firmware(&blob, path, dev->dev->dev);
e4d6b795
MB		 1869 if (err) {
1870 b43err(dev->wl, "Firmware file \"%s\" not found "
1871 "or load failed.\n", path);
1872 return err;
1873 }
61cb5dd6 1874 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 1875 goto err_format;
61cb5dd6 1876 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 1877 switch (hdr->type) {
1878 case B43_FW_TYPE_UCODE:
1879 case B43_FW_TYPE_PCM:
1880 size = be32_to_cpu(hdr->size);
61cb5dd6 1881 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 1882 goto err_format;
1883 /* fallthrough */
1884 case B43_FW_TYPE_IV:
1885 if (hdr->ver != 1)
1886 goto err_format;
1887 break;
1888 default:
1889 goto err_format;
1890 }
1891
61cb5dd6
MB		 1892 fw->data = blob;
1893 fw->filename = name;
1894
1895 return 0;
e4d6b795
MB		 1896
1897err_format:
1898 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
61cb5dd6
MB		 1899 release_firmware(blob);
1900
e4d6b795
MB		 1901 return -EPROTO;
1902}
1903
1904static int b43_request_firmware(struct b43_wldev *dev)
1905{
1906 struct b43_firmware *fw = &dev->fw;
1907 const u8 rev = dev->dev->id.revision;
1908 const char *filename;
1909 u32 tmshigh;
1910 int err;
1911
61cb5dd6 1912 /* Get microcode */
e4d6b795 1913 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 1914 if ((rev >= 5) && (rev <= 10))
1915 filename = "ucode5";
1916 else if ((rev >= 11) && (rev <= 12))
1917 filename = "ucode11";
1918 else if (rev >= 13)
1919 filename = "ucode13";
1920 else
1921 goto err_no_ucode;
1922 err = do_request_fw(dev, filename, &fw->ucode);
1923 if (err)
1924 goto err_load;
1925
1926 /* Get PCM code */
1927 if ((rev >= 5) && (rev <= 10))
1928 filename = "pcm5";
1929 else if (rev >= 11)
1930 filename = NULL;
1931 else
1932 goto err_no_pcm;
1933 err = do_request_fw(dev, filename, &fw->pcm);
1934 if (err)
1935 goto err_load;
1936
1937 /* Get initvals */
1938 switch (dev->phy.type) {
1939 case B43_PHYTYPE_A:
1940 if ((rev >= 5) && (rev <= 10)) {
1941 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1942 filename = "a0g1initvals5";
1943 else
1944 filename = "a0g0initvals5";
1945 } else
1946 goto err_no_initvals;
1947 break;
1948 case B43_PHYTYPE_G:
e4d6b795 1949 if ((rev >= 5) && (rev <= 10))
61cb5dd6 1950 filename = "b0g0initvals5";
e4d6b795 1951 else if (rev >= 13)
61cb5dd6 1952 filename = "lp0initvals13";
e4d6b795 1953 else
61cb5dd6
MB		 1954 goto err_no_initvals;
1955 break;
1956 case B43_PHYTYPE_N:
1957 if ((rev >= 11) && (rev <= 12))
1958 filename = "n0initvals11";
1959 else
1960 goto err_no_initvals;
1961 break;
1962 default:
1963 goto err_no_initvals;
e4d6b795 1964 }
61cb5dd6
MB		 1965 err = do_request_fw(dev, filename, &fw->initvals);
1966 if (err)
1967 goto err_load;
1968
1969 /* Get bandswitch initvals */
1970 switch (dev->phy.type) {
1971 case B43_PHYTYPE_A:
1972 if ((rev >= 5) && (rev <= 10)) {
1973 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1974 filename = "a0g1bsinitvals5";
1975 else
1976 filename = "a0g0bsinitvals5";
1977 } else if (rev >= 11)
1978 filename = NULL;
1979 else
1980 goto err_no_initvals;
1981 break;
1982 case B43_PHYTYPE_G:
e4d6b795 1983 if ((rev >= 5) && (rev <= 10))
61cb5dd6 1984 filename = "b0g0bsinitvals5";
e4d6b795
MB		 1985 else if (rev >= 11)
1986 filename = NULL;
1987 else
e4d6b795 1988 goto err_no_initvals;
61cb5dd6
MB		 1989 break;
1990 case B43_PHYTYPE_N:
1991 if ((rev >= 11) && (rev <= 12))
1992 filename = "n0bsinitvals11";
1993 else
e4d6b795 1994 goto err_no_initvals;
61cb5dd6
MB		 1995 break;
1996 default:
1997 goto err_no_initvals;
e4d6b795 1998 }
61cb5dd6
MB		 1999 err = do_request_fw(dev, filename, &fw->initvals_band);
2000 if (err)
2001 goto err_load;
e4d6b795
MB		 2002
2003 return 0;
2004
2005err_load:
eb189d8b 2006 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2007 goto error;
2008
2009err_no_ucode:
2010 err = -ENODEV;
2011 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2012 goto error;
2013
2014err_no_pcm:
2015 err = -ENODEV;
2016 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2017 goto error;
2018
2019err_no_initvals:
2020 err = -ENODEV;
2021 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2022 "core rev %u\n", dev->phy.type, rev);
2023 goto error;
2024
2025error:
2026 b43_release_firmware(dev);
2027 return err;
2028}
2029
2030static int b43_upload_microcode(struct b43_wldev *dev)
2031{
2032 const size_t hdr_len = sizeof(struct b43_fw_header);
2033 const __be32 *data;
2034 unsigned int i, len;
2035 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2036 u32 tmp, macctl;
e4d6b795
MB		 2037 int err = 0;
2038
1f7d87b0
MB		 2039 /* Jump the microcode PSM to offset 0 */
2040 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2041 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2042 macctl |= B43_MACCTL_PSM_JMP0;
2043 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2044 /* Zero out all microcode PSM registers and shared memory. */
2045 for (i = 0; i < 64; i++)
2046 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2047 for (i = 0; i < 4096; i += 2)
2048 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2049
e4d6b795 2050 /* Upload Microcode. */
61cb5dd6
MB		 2051 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2052 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2053 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2054 for (i = 0; i < len; i++) {
2055 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2056 udelay(10);
2057 }
2058
61cb5dd6 2059 if (dev->fw.pcm.data) {
e4d6b795 2060 /* Upload PCM data. */
61cb5dd6
MB		 2061 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2062 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2063 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2064 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2065 /* No need for autoinc bit in SHM_HW */
2066 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2067 for (i = 0; i < len; i++) {
2068 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2069 udelay(10);
2070 }
2071 }
2072
2073 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2074
2075 /* Start the microcode PSM */
2076 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2077 macctl &= ~B43_MACCTL_PSM_JMP0;
2078 macctl |= B43_MACCTL_PSM_RUN;
2079 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2080
2081 /* Wait for the microcode to load and respond */
2082 i = 0;
2083 while (1) {
2084 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2085 if (tmp == B43_IRQ_MAC_SUSPENDED)
2086 break;
2087 i++;
1f7d87b0 2088 if (i >= 20) {
e4d6b795 2089 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2090 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2091 err = -ENODEV;
1f7d87b0
MB		 2092 goto error;
2093 }
2094 msleep_interruptible(50);
2095 if (signal_pending(current)) {
2096 err = -EINTR;
2097 goto error;
e4d6b795 2098 }
e4d6b795
MB		 2099 }
2100 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2101
2102 /* Get and check the revisions. */
2103 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2104 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2105 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2106 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2107
2108 if (fwrev <= 0x128) {
2109 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2110 "binary drivers older than version 4.x is unsupported. "
2111 "You must upgrade your firmware files.\n");
eb189d8b 2112 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2113 err = -EOPNOTSUPP;
1f7d87b0 2114 goto error;
e4d6b795 2115 }
588e6cdf
MB		 2116 b43info(dev->wl, "Loading firmware version %u.%u "
2117 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2118 fwrev, fwpatch,
2119 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2120 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
e4d6b795
MB		 2121
2122 dev->fw.rev = fwrev;
2123 dev->fw.patch = fwpatch;
2124
eb189d8b
MB		 2125 if (b43_is_old_txhdr_format(dev)) {
2126 b43warn(dev->wl, "You are using an old firmware image. "
2127 "Support for old firmware will be removed in July 2008.\n");
2128 b43_print_fw_helptext(dev->wl, 0);
2129 }
2130
1f7d87b0
MB		 2131 return 0;
2132
2133error:
2134 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2135 macctl &= ~B43_MACCTL_PSM_RUN;
2136 macctl |= B43_MACCTL_PSM_JMP0;
2137 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2138
e4d6b795
MB		 2139 return err;
2140}
2141
2142static int b43_write_initvals(struct b43_wldev *dev,
2143 const struct b43_iv *ivals,
2144 size_t count,
2145 size_t array_size)
2146{
2147 const struct b43_iv *iv;
2148 u16 offset;
2149 size_t i;
2150 bool bit32;
2151
2152 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2153 iv = ivals;
2154 for (i = 0; i < count; i++) {
2155 if (array_size < sizeof(iv->offset_size))
2156 goto err_format;
2157 array_size -= sizeof(iv->offset_size);
2158 offset = be16_to_cpu(iv->offset_size);
2159 bit32 = !!(offset & B43_IV_32BIT);
2160 offset &= B43_IV_OFFSET_MASK;
2161 if (offset >= 0x1000)
2162 goto err_format;
2163 if (bit32) {
2164 u32 value;
2165
2166 if (array_size < sizeof(iv->data.d32))
2167 goto err_format;
2168 array_size -= sizeof(iv->data.d32);
2169
2170 value = be32_to_cpu(get_unaligned(&iv->data.d32));
2171 b43_write32(dev, offset, value);
2172
2173 iv = (const struct b43_iv *)((const uint8_t *)iv +
2174 sizeof(__be16) +
2175 sizeof(__be32));
2176 } else {
2177 u16 value;
2178
2179 if (array_size < sizeof(iv->data.d16))
2180 goto err_format;
2181 array_size -= sizeof(iv->data.d16);
2182
2183 value = be16_to_cpu(iv->data.d16);
2184 b43_write16(dev, offset, value);
2185
2186 iv = (const struct b43_iv *)((const uint8_t *)iv +
2187 sizeof(__be16) +
2188 sizeof(__be16));
2189 }
2190 }
2191 if (array_size)
2192 goto err_format;
2193
2194 return 0;
2195
2196err_format:
2197 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2198 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2199
2200 return -EPROTO;
2201}
2202
2203static int b43_upload_initvals(struct b43_wldev *dev)
2204{
2205 const size_t hdr_len = sizeof(struct b43_fw_header);
2206 const struct b43_fw_header *hdr;
2207 struct b43_firmware *fw = &dev->fw;
2208 const struct b43_iv *ivals;
2209 size_t count;
2210 int err;
2211
61cb5dd6
MB		 2212 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2213 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2214 count = be32_to_cpu(hdr->size);
2215 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2216 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2217 if (err)
2218 goto out;
61cb5dd6
MB		 2219 if (fw->initvals_band.data) {
2220 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2221 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2222 count = be32_to_cpu(hdr->size);
2223 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2224 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2225 if (err)
2226 goto out;
2227 }
2228out:
2229
2230 return err;
2231}
2232
2233/* Initialize the GPIOs
2234 * http://bcm-specs.sipsolutions.net/GPIO
2235 */
2236static int b43_gpio_init(struct b43_wldev *dev)
2237{
2238 struct ssb_bus *bus = dev->dev->bus;
2239 struct ssb_device *gpiodev, *pcidev = NULL;
2240 u32 mask, set;
2241
2242 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2243 & ~B43_MACCTL_GPOUTSMSK);
2244
e4d6b795
MB		 2245 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2246 | 0x000F);
2247
2248 mask = 0x0000001F;
2249 set = 0x0000000F;
2250 if (dev->dev->bus->chip_id == 0x4301) {
2251 mask |= 0x0060;
2252 set |= 0x0060;
2253 }
2254 if (0 /* FIXME: conditional unknown */ ) {
2255 b43_write16(dev, B43_MMIO_GPIO_MASK,
2256 b43_read16(dev, B43_MMIO_GPIO_MASK)
2257 | 0x0100);
2258 mask |= 0x0180;
2259 set |= 0x0180;
2260 }
95de2841 2261 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2262 b43_write16(dev, B43_MMIO_GPIO_MASK,
2263 b43_read16(dev, B43_MMIO_GPIO_MASK)
2264 | 0x0200);
2265 mask |= 0x0200;
2266 set |= 0x0200;
2267 }
2268 if (dev->dev->id.revision >= 2)
2269 mask |= 0x0010; /* FIXME: This is redundant. */
2270
2271#ifdef CONFIG_SSB_DRIVER_PCICORE
2272 pcidev = bus->pcicore.dev;
2273#endif
2274 gpiodev = bus->chipco.dev ? : pcidev;
2275 if (!gpiodev)
2276 return 0;
2277 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2278 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2279 & mask) | set);
2280
2281 return 0;
2282}
2283
2284/* Turn off all GPIO stuff. Call this on module unload, for example. */
2285static void b43_gpio_cleanup(struct b43_wldev *dev)
2286{
2287 struct ssb_bus *bus = dev->dev->bus;
2288 struct ssb_device *gpiodev, *pcidev = NULL;
2289
2290#ifdef CONFIG_SSB_DRIVER_PCICORE
2291 pcidev = bus->pcicore.dev;
2292#endif
2293 gpiodev = bus->chipco.dev ? : pcidev;
2294 if (!gpiodev)
2295 return;
2296 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2297}
2298
2299/* http://bcm-specs.sipsolutions.net/EnableMac */
affe0a02 2300static void b43_mac_enable(struct b43_wldev *dev)
e4d6b795
MB		 2301{
2302 dev->mac_suspended--;
2303 B43_WARN_ON(dev->mac_suspended < 0);
2304 if (dev->mac_suspended == 0) {
2305 b43_write32(dev, B43_MMIO_MACCTL,
2306 b43_read32(dev, B43_MMIO_MACCTL)
2307 | B43_MACCTL_ENABLED);
2308 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2309 B43_IRQ_MAC_SUSPENDED);
2310 /* Commit writes */
2311 b43_read32(dev, B43_MMIO_MACCTL);
2312 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2313 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 2314
2315 /* Re-enable IRQs. */
2316 spin_lock_irq(&dev->wl->irq_lock);
2317 b43_interrupt_enable(dev, dev->irq_savedstate);
2318 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 2319 }
2320}
2321
2322/* http://bcm-specs.sipsolutions.net/SuspendMAC */
affe0a02 2323static void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2324{
2325 int i;
2326 u32 tmp;
2327
05b64b36 2328 might_sleep();
e4d6b795 2329 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2330
e4d6b795 2331 if (dev->mac_suspended == 0) {
05b64b36
MB		 2332 /* Mask IRQs before suspending MAC. Otherwise
2333 * the MAC stays busy and won't suspend. */
2334 spin_lock_irq(&dev->wl->irq_lock);
2335 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2336 spin_unlock_irq(&dev->wl->irq_lock);
2337 b43_synchronize_irq(dev);
2338 dev->irq_savedstate = tmp;
2339
e4d6b795
MB		 2340 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2341 b43_write32(dev, B43_MMIO_MACCTL,
2342 b43_read32(dev, B43_MMIO_MACCTL)
2343 & ~B43_MACCTL_ENABLED);
2344 /* force pci to flush the write */
2345 b43_read32(dev, B43_MMIO_MACCTL);
05b64b36 2346 for (i = 40; i; i--) {
e4d6b795
MB		 2347 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2348 if (tmp & B43_IRQ_MAC_SUSPENDED)
2349 goto out;
05b64b36 2350 msleep(1);
e4d6b795
MB		 2351 }
2352 b43err(dev->wl, "MAC suspend failed\n");
2353 }
05b64b36 2354out:
e4d6b795
MB		 2355 dev->mac_suspended++;
2356}
2357
2358static void b43_adjust_opmode(struct b43_wldev *dev)
2359{
2360 struct b43_wl *wl = dev->wl;
2361 u32 ctl;
2362 u16 cfp_pretbtt;
2363
2364 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2365 /* Reset status to STA infrastructure mode. */
2366 ctl &= ~B43_MACCTL_AP;
2367 ctl &= ~B43_MACCTL_KEEP_CTL;
2368 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2369 ctl &= ~B43_MACCTL_KEEP_BAD;
2370 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2371 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2372 ctl |= B43_MACCTL_INFRA;
2373
4150c572
JB		 2374 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2375 ctl |= B43_MACCTL_AP;
2376 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2377 ctl &= ~B43_MACCTL_INFRA;
2378
2379 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2380 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2381 if (wl->filter_flags & FIF_FCSFAIL)
2382 ctl |= B43_MACCTL_KEEP_BAD;
2383 if (wl->filter_flags & FIF_PLCPFAIL)
2384 ctl |= B43_MACCTL_KEEP_BADPLCP;
2385 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2386 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2387 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2388 ctl |= B43_MACCTL_BEACPROMISC;
2389
e4d6b795
MB		 2390 /* Workaround: On old hardware the HW-MAC-address-filter
2391 * doesn't work properly, so always run promisc in filter
2392 * it in software. */
2393 if (dev->dev->id.revision <= 4)
2394 ctl |= B43_MACCTL_PROMISC;
2395
2396 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2397
2398 cfp_pretbtt = 2;
2399 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2400 if (dev->dev->bus->chip_id == 0x4306 &&
2401 dev->dev->bus->chip_rev == 3)
2402 cfp_pretbtt = 100;
2403 else
2404 cfp_pretbtt = 50;
2405 }
2406 b43_write16(dev, 0x612, cfp_pretbtt);
2407}
2408
2409static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2410{
2411 u16 offset;
2412
2413 if (is_ofdm) {
2414 offset = 0x480;
2415 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2416 } else {
2417 offset = 0x4C0;
2418 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2419 }
2420 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2421 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2422}
2423
2424static void b43_rate_memory_init(struct b43_wldev *dev)
2425{
2426 switch (dev->phy.type) {
2427 case B43_PHYTYPE_A:
2428 case B43_PHYTYPE_G:
53a6e234 2429 case B43_PHYTYPE_N:
e4d6b795
MB		 2430 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2431 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2432 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2433 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2434 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2435 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2436 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2437 if (dev->phy.type == B43_PHYTYPE_A)
2438 break;
2439 /* fallthrough */
2440 case B43_PHYTYPE_B:
2441 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2442 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2443 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2444 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2445 break;
2446 default:
2447 B43_WARN_ON(1);
2448 }
2449}
2450
5042c507
MB		 2451/* Set the default values for the PHY TX Control Words. */
2452static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2453{
2454 u16 ctl = 0;
2455
2456 ctl |= B43_TXH_PHY_ENC_CCK;
2457 ctl |= B43_TXH_PHY_ANT01AUTO;
2458 ctl |= B43_TXH_PHY_TXPWR;
2459
2460 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2461 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2462 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2463}
2464
e4d6b795
MB		 2465/* Set the TX-Antenna for management frames sent by firmware. */
2466static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2467{
5042c507 2468 u16 ant;
e4d6b795
MB		 2469 u16 tmp;
2470
5042c507 2471 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2472
e4d6b795
MB		 2473 /* For ACK/CTS */
2474 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2475 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2476 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2477 /* For Probe Resposes */
2478 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2479 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2480 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2481}
2482
2483/* This is the opposite of b43_chip_init() */
2484static void b43_chip_exit(struct b43_wldev *dev)
2485{
8e9f7529 2486 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 2487 b43_gpio_cleanup(dev);
2488 /* firmware is released later */
2489}
2490
2491/* Initialize the chip
2492 * http://bcm-specs.sipsolutions.net/ChipInit
2493 */
2494static int b43_chip_init(struct b43_wldev *dev)
2495{
2496 struct b43_phy *phy = &dev->phy;
2497 int err, tmp;
1f7d87b0 2498 u32 value32, macctl;
e4d6b795
MB		 2499 u16 value16;
2500
1f7d87b0
MB		 2501 /* Initialize the MAC control */
2502 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2503 if (dev->phy.gmode)
2504 macctl |= B43_MACCTL_GMODE;
2505 macctl |= B43_MACCTL_INFRA;
2506 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2507
2508 err = b43_request_firmware(dev);
2509 if (err)
2510 goto out;
2511 err = b43_upload_microcode(dev);
2512 if (err)
2513 goto out; /* firmware is released later */
2514
2515 err = b43_gpio_init(dev);
2516 if (err)
2517 goto out; /* firmware is released later */
21954c36 2518
e4d6b795
MB		 2519 err = b43_upload_initvals(dev);
2520 if (err)
1a8d1227 2521 goto err_gpio_clean;
e4d6b795 2522 b43_radio_turn_on(dev);
e4d6b795
MB		 2523
2524 b43_write16(dev, 0x03E6, 0x0000);
2525 err = b43_phy_init(dev);
2526 if (err)
2527 goto err_radio_off;
2528
2529 /* Select initial Interference Mitigation. */
2530 tmp = phy->interfmode;
2531 phy->interfmode = B43_INTERFMODE_NONE;
2532 b43_radio_set_interference_mitigation(dev, tmp);
2533
2534 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2535 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2536
2537 if (phy->type == B43_PHYTYPE_B) {
2538 value16 = b43_read16(dev, 0x005E);
2539 value16 |= 0x0004;
2540 b43_write16(dev, 0x005E, value16);
2541 }
2542 b43_write32(dev, 0x0100, 0x01000000);
2543 if (dev->dev->id.revision < 5)
2544 b43_write32(dev, 0x010C, 0x01000000);
2545
2546 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2547 & ~B43_MACCTL_INFRA);
2548 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2549 | B43_MACCTL_INFRA);
e4d6b795 2550
e4d6b795
MB		 2551 /* Probe Response Timeout value */
2552 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2553 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2554
2555 /* Initially set the wireless operation mode. */
2556 b43_adjust_opmode(dev);
2557
2558 if (dev->dev->id.revision < 3) {
2559 b43_write16(dev, 0x060E, 0x0000);
2560 b43_write16(dev, 0x0610, 0x8000);
2561 b43_write16(dev, 0x0604, 0x0000);
2562 b43_write16(dev, 0x0606, 0x0200);
2563 } else {
2564 b43_write32(dev, 0x0188, 0x80000000);
2565 b43_write32(dev, 0x018C, 0x02000000);
2566 }
2567 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2568 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2569 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2570 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2571 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2572 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2573 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2574
2575 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2576 value32 |= 0x00100000;
2577 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2578
2579 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2580 dev->dev->bus->chipco.fast_pwrup_delay);
2581
2582 err = 0;
2583 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2584out:
e4d6b795
MB		 2585 return err;
2586
21954c36 2587err_radio_off:
8e9f7529 2588 b43_radio_turn_off(dev, 1);
1a8d1227 2589err_gpio_clean:
e4d6b795 2590 b43_gpio_cleanup(dev);
21954c36 2591 return err;
e4d6b795
MB		 2592}
2593
2594static void b43_periodic_every120sec(struct b43_wldev *dev)
2595{
2596 struct b43_phy *phy = &dev->phy;
2597
2598 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2599 return;
2600
2601 b43_mac_suspend(dev);
2602 b43_lo_g_measure(dev);
2603 b43_mac_enable(dev);
2604 if (b43_has_hardware_pctl(phy))
2605 b43_lo_g_ctl_mark_all_unused(dev);
2606}
2607
2608static void b43_periodic_every60sec(struct b43_wldev *dev)
2609{
2610 struct b43_phy *phy = &dev->phy;
2611
53a6e234
MB		 2612 if (phy->type != B43_PHYTYPE_G)
2613 return;
e4d6b795
MB		 2614 if (!b43_has_hardware_pctl(phy))
2615 b43_lo_g_ctl_mark_all_unused(dev);
95de2841 2616 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
e4d6b795
MB		 2617 b43_mac_suspend(dev);
2618 b43_calc_nrssi_slope(dev);
2619 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2620 u8 old_chan = phy->channel;
2621
2622 /* VCO Calibration */
2623 if (old_chan >= 8)
2624 b43_radio_selectchannel(dev, 1, 0);
2625 else
2626 b43_radio_selectchannel(dev, 13, 0);
2627 b43_radio_selectchannel(dev, old_chan, 0);
2628 }
2629 b43_mac_enable(dev);
2630 }
2631}
2632
2633static void b43_periodic_every30sec(struct b43_wldev *dev)
2634{
2635 /* Update device statistics. */
2636 b43_calculate_link_quality(dev);
2637}
2638
2639static void b43_periodic_every15sec(struct b43_wldev *dev)
2640{
2641 struct b43_phy *phy = &dev->phy;
2642
2643 if (phy->type == B43_PHYTYPE_G) {
2644 //TODO: update_aci_moving_average
2645 if (phy->aci_enable && phy->aci_wlan_automatic) {
2646 b43_mac_suspend(dev);
2647 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2648 if (0 /*TODO: bunch of conditions */ ) {
2649 b43_radio_set_interference_mitigation
2650 (dev, B43_INTERFMODE_MANUALWLAN);
2651 }
2652 } else if (1 /*TODO*/) {
2653 /*
2654 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2655 b43_radio_set_interference_mitigation(dev,
2656 B43_INTERFMODE_NONE);
2657 }
2658 */
2659 }
2660 b43_mac_enable(dev);
2661 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2662 phy->rev == 1) {
2663 //TODO: implement rev1 workaround
2664 }
2665 }
2666 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2667 //TODO for APHY (temperature?)
00e0b8cb
SB		 2668
2669 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2670 wmb();
e4d6b795
MB		 2671}
2672
e4d6b795
MB		 2673static void do_periodic_work(struct b43_wldev *dev)
2674{
2675 unsigned int state;
2676
2677 state = dev->periodic_state;
42bb4cd5 2678 if (state % 8 == 0)
e4d6b795 2679 b43_periodic_every120sec(dev);
42bb4cd5 2680 if (state % 4 == 0)
e4d6b795 2681 b43_periodic_every60sec(dev);
42bb4cd5 2682 if (state % 2 == 0)
e4d6b795 2683 b43_periodic_every30sec(dev);
42bb4cd5 2684 b43_periodic_every15sec(dev);
e4d6b795
MB		 2685}
2686
05b64b36
MB		 2687/* Periodic work locking policy:
2688 * The whole periodic work handler is protected by
2689 * wl->mutex. If another lock is needed somewhere in the
2690 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2691 */
e4d6b795
MB		 2692static void b43_periodic_work_handler(struct work_struct *work)
2693{
05b64b36
MB		 2694 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2695 periodic_work.work);
2696 struct b43_wl *wl = dev->wl;
2697 unsigned long delay;
e4d6b795 2698
05b64b36 2699 mutex_lock(&wl->mutex);
e4d6b795
MB		 2700
2701 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2702 goto out;
2703 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2704 goto out_requeue;
2705
05b64b36 2706 do_periodic_work(dev);
e4d6b795 2707
e4d6b795 2708 dev->periodic_state++;
42bb4cd5 2709out_requeue:
e4d6b795
MB		 2710 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2711 delay = msecs_to_jiffies(50);
2712 else
82cd682d 2713 delay = round_jiffies_relative(HZ * 15);
05b64b36 2714 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2715out:
05b64b36 2716 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2717}
2718
2719static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2720{
2721 struct delayed_work *work = &dev->periodic_work;
2722
2723 dev->periodic_state = 0;
2724 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2725 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2726}
2727
f3dd3fcc 2728/* Check if communication with the device works correctly. */
e4d6b795
MB		 2729static int b43_validate_chipaccess(struct b43_wldev *dev)
2730{
f3dd3fcc 2731 u32 v, backup;
e4d6b795 2732
f3dd3fcc
MB		 2733 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2734
2735 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2736 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2737 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2738 goto error;
f3dd3fcc
MB		 2739 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2740 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2741 goto error;
2742
f3dd3fcc
MB		 2743 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2744
2745 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2746 /* The 32bit register shadows the two 16bit registers
2747 * with update sideeffects. Validate this. */
2748 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2749 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2750 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2751 goto error;
2752 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2753 goto error;
2754 }
2755 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2756
2757 v = b43_read32(dev, B43_MMIO_MACCTL);
2758 v |= B43_MACCTL_GMODE;
2759 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2760 goto error;
2761
2762 return 0;
f3dd3fcc 2763error:
e4d6b795
MB		 2764 b43err(dev->wl, "Failed to validate the chipaccess\n");
2765 return -ENODEV;
2766}
2767
2768static void b43_security_init(struct b43_wldev *dev)
2769{
2770 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2771 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2772 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2773 /* KTP is a word address, but we address SHM bytewise.
2774 * So multiply by two.
2775 */
2776 dev->ktp *= 2;
2777 if (dev->dev->id.revision >= 5) {
2778 /* Number of RCMTA address slots */
2779 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2780 }
2781 b43_clear_keys(dev);
2782}
2783
2784static int b43_rng_read(struct hwrng *rng, u32 * data)
2785{
2786 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2787 unsigned long flags;
2788
2789 /* Don't take wl->mutex here, as it could deadlock with
2790 * hwrng internal locking. It's not needed to take
2791 * wl->mutex here, anyway. */
2792
2793 spin_lock_irqsave(&wl->irq_lock, flags);
2794 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2795 spin_unlock_irqrestore(&wl->irq_lock, flags);
2796
2797 return (sizeof(u16));
2798}
2799
3506e0c4 2800static void b43_rng_exit(struct b43_wl *wl, bool suspended)
e4d6b795
MB		 2801{
2802 if (wl->rng_initialized)
3506e0c4 2803 __hwrng_unregister(&wl->rng, suspended);
e4d6b795
MB		 2804}
2805
2806static int b43_rng_init(struct b43_wl *wl)
2807{
2808 int err;
2809
2810 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2811 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2812 wl->rng.name = wl->rng_name;
2813 wl->rng.data_read = b43_rng_read;
2814 wl->rng.priv = (unsigned long)wl;
2815 wl->rng_initialized = 1;
2816 err = hwrng_register(&wl->rng);
2817 if (err) {
2818 wl->rng_initialized = 0;
2819 b43err(wl, "Failed to register the random "
2820 "number generator (%d)\n", err);
2821 }
2822
2823 return err;
2824}
2825
40faacc4
MB		 2826static int b43_op_tx(struct ieee80211_hw *hw,
2827 struct sk_buff *skb,
2828 struct ieee80211_tx_control *ctl)
e4d6b795
MB		 2829{
2830 struct b43_wl *wl = hw_to_b43_wl(hw);
2831 struct b43_wldev *dev = wl->current_dev;
2832 int err = -ENODEV;
e4d6b795 2833
5100d5ac
MB		 2834 if (unlikely(skb->len < 2 + 2 + 6)) {
2835 /* Too short, this can't be a valid frame. */
2836 return -EINVAL;
2837 }
2838 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2839
e4d6b795
MB		 2840 if (unlikely(!dev))
2841 goto out;
2842 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2843 goto out;
5100d5ac
MB		 2844 /* TX is done without a global lock. */
2845 if (b43_using_pio_transfers(dev))
2846 err = b43_pio_tx(dev, skb, ctl);
2847 else
2848 err = b43_dma_tx(dev, skb, ctl);
40faacc4 2849out:
e4d6b795
MB		 2850 if (unlikely(err))
2851 return NETDEV_TX_BUSY;
2852 return NETDEV_TX_OK;
2853}
2854
e6f5b934
MB		 2855/* Locking: wl->irq_lock */
2856static void b43_qos_params_upload(struct b43_wldev *dev,
2857 const struct ieee80211_tx_queue_params *p,
2858 u16 shm_offset)
2859{
2860 u16 params[B43_NR_QOSPARAMS];
2861 int cw_min, cw_max, aifs, bslots, tmp;
2862 unsigned int i;
2863
2864 const u16 aCWmin = 0x0001;
2865 const u16 aCWmax = 0x03FF;
2866
2867 /* Calculate the default values for the parameters, if needed. */
2868 switch (shm_offset) {
2869 case B43_QOS_VOICE:
2870 aifs = (p->aifs == -1) ? 2 : p->aifs;
2871 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2872 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2873 break;
2874 case B43_QOS_VIDEO:
2875 aifs = (p->aifs == -1) ? 2 : p->aifs;
2876 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2877 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2878 break;
2879 case B43_QOS_BESTEFFORT:
2880 aifs = (p->aifs == -1) ? 3 : p->aifs;
2881 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2882 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2883 break;
2884 case B43_QOS_BACKGROUND:
2885 aifs = (p->aifs == -1) ? 7 : p->aifs;
2886 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2887 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2888 break;
2889 default:
2890 B43_WARN_ON(1);
2891 return;
2892 }
2893 if (cw_min <= 0)
2894 cw_min = aCWmin;
2895 if (cw_max <= 0)
2896 cw_max = aCWmin;
2897 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2898
2899 memset(&params, 0, sizeof(params));
2900
2901 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2902 params[B43_QOSPARAM_CWMIN] = cw_min;
2903 params[B43_QOSPARAM_CWMAX] = cw_max;
2904 params[B43_QOSPARAM_CWCUR] = cw_min;
2905 params[B43_QOSPARAM_AIFS] = aifs;
2906 params[B43_QOSPARAM_BSLOTS] = bslots;
2907 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2908
2909 for (i = 0; i < ARRAY_SIZE(params); i++) {
2910 if (i == B43_QOSPARAM_STATUS) {
2911 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2912 shm_offset + (i * 2));
2913 /* Mark the parameters as updated. */
2914 tmp |= 0x100;
2915 b43_shm_write16(dev, B43_SHM_SHARED,
2916 shm_offset + (i * 2),
2917 tmp);
2918 } else {
2919 b43_shm_write16(dev, B43_SHM_SHARED,
2920 shm_offset + (i * 2),
2921 params[i]);
2922 }
2923 }
2924}
2925
2926/* Update the QOS parameters in hardware. */
2927static void b43_qos_update(struct b43_wldev *dev)
2928{
2929 struct b43_wl *wl = dev->wl;
2930 struct b43_qos_params *params;
2931 unsigned long flags;
2932 unsigned int i;
2933
2934 /* Mapping of mac80211 queues to b43 SHM offsets. */
2935 static const u16 qos_shm_offsets[] = {
2936 [0] = B43_QOS_VOICE,
2937 [1] = B43_QOS_VIDEO,
2938 [2] = B43_QOS_BESTEFFORT,
2939 [3] = B43_QOS_BACKGROUND,
2940 };
2941 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
2942
2943 b43_mac_suspend(dev);
2944 spin_lock_irqsave(&wl->irq_lock, flags);
2945
2946 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2947 params = &(wl->qos_params[i]);
2948 if (params->need_hw_update) {
2949 b43_qos_params_upload(dev, &(params->p),
2950 qos_shm_offsets[i]);
2951 params->need_hw_update = 0;
2952 }
2953 }
2954
2955 spin_unlock_irqrestore(&wl->irq_lock, flags);
2956 b43_mac_enable(dev);
2957}
2958
2959static void b43_qos_clear(struct b43_wl *wl)
2960{
2961 struct b43_qos_params *params;
2962 unsigned int i;
2963
2964 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2965 params = &(wl->qos_params[i]);
2966
2967 memset(&(params->p), 0, sizeof(params->p));
2968 params->p.aifs = -1;
2969 params->need_hw_update = 1;
2970 }
2971}
2972
2973/* Initialize the core's QOS capabilities */
2974static void b43_qos_init(struct b43_wldev *dev)
2975{
2976 struct b43_wl *wl = dev->wl;
2977 unsigned int i;
2978
2979 /* Upload the current QOS parameters. */
2980 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
2981 wl->qos_params[i].need_hw_update = 1;
2982 b43_qos_update(dev);
2983
2984 /* Enable QOS support. */
2985 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
2986 b43_write16(dev, B43_MMIO_IFSCTL,
2987 b43_read16(dev, B43_MMIO_IFSCTL)
2988 | B43_MMIO_IFSCTL_USE_EDCF);
2989}
2990
2991static void b43_qos_update_work(struct work_struct *work)
2992{
2993 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
2994 struct b43_wldev *dev;
2995
2996 mutex_lock(&wl->mutex);
2997 dev = wl->current_dev;
2998 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
2999 b43_qos_update(dev);
3000 mutex_unlock(&wl->mutex);
3001}
3002
40faacc4 3003static int b43_op_conf_tx(struct ieee80211_hw *hw,
e6f5b934 3004 int _queue,
40faacc4 3005 const struct ieee80211_tx_queue_params *params)
e4d6b795 3006{
e6f5b934
MB		 3007 struct b43_wl *wl = hw_to_b43_wl(hw);
3008 unsigned long flags;
3009 unsigned int queue = (unsigned int)_queue;
3010 struct b43_qos_params *p;
3011
3012 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3013 /* Queue not available or don't support setting
3014 * params on this queue. Return success to not
3015 * confuse mac80211. */
3016 return 0;
3017 }
3018
3019 spin_lock_irqsave(&wl->irq_lock, flags);
3020 p = &(wl->qos_params[queue]);
3021 memcpy(&(p->p), params, sizeof(p->p));
3022 p->need_hw_update = 1;
3023 spin_unlock_irqrestore(&wl->irq_lock, flags);
3024
3025 queue_work(hw->workqueue, &wl->qos_update_work);
3026
e4d6b795
MB		 3027 return 0;
3028}
3029
40faacc4
MB		 3030static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3031 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3032{
3033 struct b43_wl *wl = hw_to_b43_wl(hw);
3034 struct b43_wldev *dev = wl->current_dev;
3035 unsigned long flags;
3036 int err = -ENODEV;
3037
3038 if (!dev)
3039 goto out;
3040 spin_lock_irqsave(&wl->irq_lock, flags);
3041 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3042 if (b43_using_pio_transfers(dev))
3043 b43_pio_get_tx_stats(dev, stats);
3044 else
3045 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3046 err = 0;
3047 }
3048 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3049out:
e4d6b795
MB		 3050 return err;
3051}
3052
40faacc4
MB		 3053static int b43_op_get_stats(struct ieee80211_hw *hw,
3054 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3055{
3056 struct b43_wl *wl = hw_to_b43_wl(hw);
3057 unsigned long flags;
3058
3059 spin_lock_irqsave(&wl->irq_lock, flags);
3060 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3061 spin_unlock_irqrestore(&wl->irq_lock, flags);
3062
3063 return 0;
3064}
3065
e4d6b795
MB		 3066static void b43_put_phy_into_reset(struct b43_wldev *dev)
3067{
3068 struct ssb_device *sdev = dev->dev;
3069 u32 tmslow;
3070
3071 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3072 tmslow &= ~B43_TMSLOW_GMODE;
3073 tmslow |= B43_TMSLOW_PHYRESET;
3074 tmslow |= SSB_TMSLOW_FGC;
3075 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3076 msleep(1);
3077
3078 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3079 tmslow &= ~SSB_TMSLOW_FGC;
3080 tmslow |= B43_TMSLOW_PHYRESET;
3081 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3082 msleep(1);
3083}
3084
bb1eeff1
MB		 3085static const char * band_to_string(enum ieee80211_band band)
3086{
3087 switch (band) {
3088 case IEEE80211_BAND_5GHZ:
3089 return "5";
3090 case IEEE80211_BAND_2GHZ:
3091 return "2.4";
3092 default:
3093 break;
3094 }
3095 B43_WARN_ON(1);
3096 return "";
3097}
3098
e4d6b795 3099/* Expects wl->mutex locked */
bb1eeff1 3100static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3101{
bb1eeff1 3102 struct b43_wldev *up_dev = NULL;
e4d6b795 3103 struct b43_wldev *down_dev;
bb1eeff1 3104 struct b43_wldev *d;
e4d6b795 3105 int err;
bb1eeff1 3106 bool gmode;
e4d6b795
MB		 3107 int prev_status;
3108
bb1eeff1
MB		 3109 /* Find a device and PHY which supports the band. */
3110 list_for_each_entry(d, &wl->devlist, list) {
3111 switch (chan->band) {
3112 case IEEE80211_BAND_5GHZ:
3113 if (d->phy.supports_5ghz) {
3114 up_dev = d;
3115 gmode = 0;
3116 }
3117 break;
3118 case IEEE80211_BAND_2GHZ:
3119 if (d->phy.supports_2ghz) {
3120 up_dev = d;
3121 gmode = 1;
3122 }
3123 break;
3124 default:
3125 B43_WARN_ON(1);
3126 return -EINVAL;
3127 }
3128 if (up_dev)
3129 break;
3130 }
3131 if (!up_dev) {
3132 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3133 band_to_string(chan->band));
3134 return -ENODEV;
e4d6b795
MB		 3135 }
3136 if ((up_dev == wl->current_dev) &&
3137 (!!wl->current_dev->phy.gmode == !!gmode)) {
3138 /* This device is already running. */
3139 return 0;
3140 }
bb1eeff1
MB		 3141 b43dbg(wl, "Switching to %s-GHz band\n",
3142 band_to_string(chan->band));
e4d6b795
MB		 3143 down_dev = wl->current_dev;
3144
3145 prev_status = b43_status(down_dev);
3146 /* Shutdown the currently running core. */
3147 if (prev_status >= B43_STAT_STARTED)
3148 b43_wireless_core_stop(down_dev);
3149 if (prev_status >= B43_STAT_INITIALIZED)
3150 b43_wireless_core_exit(down_dev);
3151
3152 if (down_dev != up_dev) {
3153 /* We switch to a different core, so we put PHY into
3154 * RESET on the old core. */
3155 b43_put_phy_into_reset(down_dev);
3156 }
3157
3158 /* Now start the new core. */
3159 up_dev->phy.gmode = gmode;
3160 if (prev_status >= B43_STAT_INITIALIZED) {
3161 err = b43_wireless_core_init(up_dev);
3162 if (err) {
3163 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3164 "selected %s-GHz band\n",
3165 band_to_string(chan->band));
e4d6b795
MB		 3166 goto init_failure;
3167 }
3168 }
3169 if (prev_status >= B43_STAT_STARTED) {
3170 err = b43_wireless_core_start(up_dev);
3171 if (err) {
3172 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3173 "selected %s-GHz band\n",
3174 band_to_string(chan->band));
e4d6b795
MB		 3175 b43_wireless_core_exit(up_dev);
3176 goto init_failure;
3177 }
3178 }
3179 B43_WARN_ON(b43_status(up_dev) != prev_status);
3180
3181 wl->current_dev = up_dev;
3182
3183 return 0;
bb1eeff1 3184init_failure:
e4d6b795
MB		 3185 /* Whoops, failed to init the new core. No core is operating now. */
3186 wl->current_dev = NULL;
3187 return err;
3188}
3189
40faacc4 3190static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
e4d6b795
MB		 3191{
3192 struct b43_wl *wl = hw_to_b43_wl(hw);
3193 struct b43_wldev *dev;
3194 struct b43_phy *phy;
3195 unsigned long flags;
9db1f6d7 3196 int antenna;
e4d6b795
MB		 3197 int err = 0;
3198 u32 savedirqs;
3199
e4d6b795
MB		 3200 mutex_lock(&wl->mutex);
3201
bb1eeff1
MB		 3202 /* Switch the band (if necessary). This might change the active core. */
3203 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3204 if (err)
3205 goto out_unlock_mutex;
3206 dev = wl->current_dev;
3207 phy = &dev->phy;
3208
3209 /* Disable IRQs while reconfiguring the device.
3210 * This makes it possible to drop the spinlock throughout
3211 * the reconfiguration process. */
3212 spin_lock_irqsave(&wl->irq_lock, flags);
3213 if (b43_status(dev) < B43_STAT_STARTED) {
3214 spin_unlock_irqrestore(&wl->irq_lock, flags);
3215 goto out_unlock_mutex;
3216 }
3217 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3218 spin_unlock_irqrestore(&wl->irq_lock, flags);
3219 b43_synchronize_irq(dev);
3220
3221 /* Switch to the requested channel.
3222 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 3223 if (conf->channel->hw_value != phy->channel)
3224 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
e4d6b795
MB		 3225
3226 /* Enable/Disable ShortSlot timing. */
3227 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3228 dev->short_slot) {
3229 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3230 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3231 b43_short_slot_timing_enable(dev);
3232 else
3233 b43_short_slot_timing_disable(dev);
3234 }
3235
d42ce84a
JB		 3236 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3237
e4d6b795
MB		 3238 /* Adjust the desired TX power level. */
3239 if (conf->power_level != 0) {
3240 if (conf->power_level != phy->power_level) {
3241 phy->power_level = conf->power_level;
3242 b43_phy_xmitpower(dev);
3243 }
3244 }
3245
3246 /* Antennas for RX and management frame TX. */
9db1f6d7
MB		 3247 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3248 b43_mgmtframe_txantenna(dev, antenna);
3249 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3250 b43_set_rx_antenna(dev, antenna);
e4d6b795
MB		 3251
3252 /* Update templates for AP mode. */
3253 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3254 b43_set_beacon_int(dev, conf->beacon_int);
3255
fda9abcf
MB		 3256 if (!!conf->radio_enabled != phy->radio_on) {
3257 if (conf->radio_enabled) {
3258 b43_radio_turn_on(dev);
3259 b43info(dev->wl, "Radio turned on by software\n");
3260 if (!dev->radio_hw_enable) {
3261 b43info(dev->wl, "The hardware RF-kill button "
3262 "still turns the radio physically off. "
3263 "Press the button to turn it on.\n");
3264 }
3265 } else {
8e9f7529 3266 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 3267 b43info(dev->wl, "Radio turned off by software\n");
3268 }
3269 }
3270
e4d6b795
MB		 3271 spin_lock_irqsave(&wl->irq_lock, flags);
3272 b43_interrupt_enable(dev, savedirqs);
3273 mmiowb();
3274 spin_unlock_irqrestore(&wl->irq_lock, flags);
3275 out_unlock_mutex:
3276 mutex_unlock(&wl->mutex);
3277
3278 return err;
3279}
3280
40faacc4 3281static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 3282 const u8 *local_addr, const u8 *addr,
3283 struct ieee80211_key_conf *key)
e4d6b795
MB		 3284{
3285 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3286 struct b43_wldev *dev;
e4d6b795
MB		 3287 unsigned long flags;
3288 u8 algorithm;
3289 u8 index;
c6dfc9a8 3290 int err;
0795af57 3291 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 3292
3293 if (modparam_nohwcrypt)
3294 return -ENOSPC; /* User disabled HW-crypto */
3295
c6dfc9a8
MB		 3296 mutex_lock(&wl->mutex);
3297 spin_lock_irqsave(&wl->irq_lock, flags);
3298
3299 dev = wl->current_dev;
3300 err = -ENODEV;
3301 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3302 goto out_unlock;
3303
3304 err = -EINVAL;
e4d6b795 3305 switch (key->alg) {
e4d6b795
MB		 3306 case ALG_WEP:
3307 if (key->keylen == 5)
3308 algorithm = B43_SEC_ALGO_WEP40;
3309 else
3310 algorithm = B43_SEC_ALGO_WEP104;
3311 break;
3312 case ALG_TKIP:
3313 algorithm = B43_SEC_ALGO_TKIP;
3314 break;
3315 case ALG_CCMP:
3316 algorithm = B43_SEC_ALGO_AES;
3317 break;
3318 default:
3319 B43_WARN_ON(1);
c6dfc9a8 3320 goto out_unlock;
e4d6b795 3321 }
e4d6b795
MB		 3322 index = (u8) (key->keyidx);
3323 if (index > 3)
e4d6b795 3324 goto out_unlock;
e4d6b795
MB		 3325
3326 switch (cmd) {
3327 case SET_KEY:
3328 if (algorithm == B43_SEC_ALGO_TKIP) {
3329 /* FIXME: No TKIP hardware encryption for now. */
3330 err = -EOPNOTSUPP;
3331 goto out_unlock;
3332 }
3333
3334 if (is_broadcast_ether_addr(addr)) {
3335 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3336 err = b43_key_write(dev, index, algorithm,
3337 key->key, key->keylen, NULL, key);
3338 } else {
3339 /*
3340 * either pairwise key or address is 00:00:00:00:00:00
3341 * for transmit-only keys
3342 */
3343 err = b43_key_write(dev, -1, algorithm,
3344 key->key, key->keylen, addr, key);
3345 }
3346 if (err)
3347 goto out_unlock;
3348
3349 if (algorithm == B43_SEC_ALGO_WEP40 ||
3350 algorithm == B43_SEC_ALGO_WEP104) {
3351 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3352 } else {
3353 b43_hf_write(dev,
3354 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3355 }
3356 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3357 break;
3358 case DISABLE_KEY: {
3359 err = b43_key_clear(dev, key->hw_key_idx);
3360 if (err)
3361 goto out_unlock;
3362 break;
3363 }
3364 default:
3365 B43_WARN_ON(1);
3366 }
3367out_unlock:
3368 spin_unlock_irqrestore(&wl->irq_lock, flags);
3369 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3370 if (!err) {
3371 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 3372 "mac: %s\n",
e4d6b795 3373 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 3374 print_mac(mac, addr));
e4d6b795
MB		 3375 }
3376 return err;
3377}
3378
40faacc4
MB		 3379static void b43_op_configure_filter(struct ieee80211_hw *hw,
3380 unsigned int changed, unsigned int *fflags,
3381 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3382{
3383 struct b43_wl *wl = hw_to_b43_wl(hw);
3384 struct b43_wldev *dev = wl->current_dev;
3385 unsigned long flags;
3386
4150c572
JB		 3387 if (!dev) {
3388 *fflags = 0;
e4d6b795 3389 return;
e4d6b795 3390 }
4150c572
JB		 3391
3392 spin_lock_irqsave(&wl->irq_lock, flags);
3393 *fflags &= FIF_PROMISC_IN_BSS |
3394 FIF_ALLMULTI |
3395 FIF_FCSFAIL |
3396 FIF_PLCPFAIL |
3397 FIF_CONTROL |
3398 FIF_OTHER_BSS |
3399 FIF_BCN_PRBRESP_PROMISC;
3400
3401 changed &= FIF_PROMISC_IN_BSS |
3402 FIF_ALLMULTI |
3403 FIF_FCSFAIL |
3404 FIF_PLCPFAIL |
3405 FIF_CONTROL |
3406 FIF_OTHER_BSS |
3407 FIF_BCN_PRBRESP_PROMISC;
3408
3409 wl->filter_flags = *fflags;
3410
3411 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3412 b43_adjust_opmode(dev);
e4d6b795
MB		 3413 spin_unlock_irqrestore(&wl->irq_lock, flags);
3414}
3415
40faacc4 3416static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3417 struct ieee80211_vif *vif,
40faacc4 3418 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3419{
3420 struct b43_wl *wl = hw_to_b43_wl(hw);
3421 struct b43_wldev *dev = wl->current_dev;
3422 unsigned long flags;
3423
3424 if (!dev)
3425 return -ENODEV;
3426 mutex_lock(&wl->mutex);
3427 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3428 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3429 if (conf->bssid)
3430 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3431 else
3432 memset(wl->bssid, 0, ETH_ALEN);
3433 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3434 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3435 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3436 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
5042c507
MB		 3437 if (conf->beacon) {
3438 b43_update_templates(wl, conf->beacon,
3439 conf->beacon_control);
3440 }
e4d6b795 3441 }
4150c572 3442 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3443 }
3444 spin_unlock_irqrestore(&wl->irq_lock, flags);
3445 mutex_unlock(&wl->mutex);
3446
3447 return 0;
3448}
3449
3450/* Locking: wl->mutex */
3451static void b43_wireless_core_stop(struct b43_wldev *dev)
3452{
3453 struct b43_wl *wl = dev->wl;
3454 unsigned long flags;
3455
3456 if (b43_status(dev) < B43_STAT_STARTED)
3457 return;
a19d12d7
SB		 3458
3459 /* Disable and sync interrupts. We must do this before than
3460 * setting the status to INITIALIZED, as the interrupt handler
3461 * won't care about IRQs then. */
3462 spin_lock_irqsave(&wl->irq_lock, flags);
3463 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3464 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3465 spin_unlock_irqrestore(&wl->irq_lock, flags);
3466 b43_synchronize_irq(dev);
3467
e4d6b795
MB		 3468 b43_set_status(dev, B43_STAT_INITIALIZED);
3469
5100d5ac 3470 b43_pio_stop(dev);
e4d6b795
MB		 3471 mutex_unlock(&wl->mutex);
3472 /* Must unlock as it would otherwise deadlock. No races here.
3473 * Cancel the possibly running self-rearming periodic work. */
3474 cancel_delayed_work_sync(&dev->periodic_work);
3475 mutex_lock(&wl->mutex);
3476
3477 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3478
e4d6b795
MB		 3479 b43_mac_suspend(dev);
3480 free_irq(dev->dev->irq, dev);
3481 b43dbg(wl, "Wireless interface stopped\n");
3482}
3483
3484/* Locking: wl->mutex */
3485static int b43_wireless_core_start(struct b43_wldev *dev)
3486{
3487 int err;
3488
3489 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3490
3491 drain_txstatus_queue(dev);
3492 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3493 IRQF_SHARED, KBUILD_MODNAME, dev);
3494 if (err) {
3495 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3496 goto out;
3497 }
3498
3499 /* We are ready to run. */
3500 b43_set_status(dev, B43_STAT_STARTED);
3501
3502 /* Start data flow (TX/RX). */
3503 b43_mac_enable(dev);
3504 b43_interrupt_enable(dev, dev->irq_savedstate);
3505 ieee80211_start_queues(dev->wl->hw);
3506
3507 /* Start maintainance work */
3508 b43_periodic_tasks_setup(dev);
3509
3510 b43dbg(dev->wl, "Wireless interface started\n");
3511 out:
3512 return err;
3513}
3514
3515/* Get PHY and RADIO versioning numbers */
3516static int b43_phy_versioning(struct b43_wldev *dev)
3517{
3518 struct b43_phy *phy = &dev->phy;
3519 u32 tmp;
3520 u8 analog_type;
3521 u8 phy_type;
3522 u8 phy_rev;
3523 u16 radio_manuf;
3524 u16 radio_ver;
3525 u16 radio_rev;
3526 int unsupported = 0;
3527
3528 /* Get PHY versioning */
3529 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3530 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3531 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3532 phy_rev = (tmp & B43_PHYVER_VERSION);
3533 switch (phy_type) {
3534 case B43_PHYTYPE_A:
3535 if (phy_rev >= 4)
3536 unsupported = 1;
3537 break;
3538 case B43_PHYTYPE_B:
3539 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3540 && phy_rev != 7)
3541 unsupported = 1;
3542 break;
3543 case B43_PHYTYPE_G:
013978b6 3544 if (phy_rev > 9)
e4d6b795
MB		 3545 unsupported = 1;
3546 break;
d5c71e46
MB		 3547#ifdef CONFIG_B43_NPHY
3548 case B43_PHYTYPE_N:
3549 if (phy_rev > 1)
3550 unsupported = 1;
3551 break;
3552#endif
e4d6b795
MB		 3553 default:
3554 unsupported = 1;
3555 };
3556 if (unsupported) {
3557 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3558 "(Analog %u, Type %u, Revision %u)\n",
3559 analog_type, phy_type, phy_rev);
3560 return -EOPNOTSUPP;
3561 }
3562 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3563 analog_type, phy_type, phy_rev);
3564
3565 /* Get RADIO versioning */
3566 if (dev->dev->bus->chip_id == 0x4317) {
3567 if (dev->dev->bus->chip_rev == 0)
3568 tmp = 0x3205017F;
3569 else if (dev->dev->bus->chip_rev == 1)
3570 tmp = 0x4205017F;
3571 else
3572 tmp = 0x5205017F;
3573 } else {
3574 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3575 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3576 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3577 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3578 }
3579 radio_manuf = (tmp & 0x00000FFF);
3580 radio_ver = (tmp & 0x0FFFF000) >> 12;
3581 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3582 if (radio_manuf != 0x17F /* Broadcom */)
3583 unsupported = 1;
e4d6b795
MB		 3584 switch (phy_type) {
3585 case B43_PHYTYPE_A:
3586 if (radio_ver != 0x2060)
3587 unsupported = 1;
3588 if (radio_rev != 1)
3589 unsupported = 1;
3590 if (radio_manuf != 0x17F)
3591 unsupported = 1;
3592 break;
3593 case B43_PHYTYPE_B:
3594 if ((radio_ver & 0xFFF0) != 0x2050)
3595 unsupported = 1;
3596 break;
3597 case B43_PHYTYPE_G:
3598 if (radio_ver != 0x2050)
3599 unsupported = 1;
3600 break;
96c755a3 3601 case B43_PHYTYPE_N:
243dcfcc 3602 if (radio_ver != 0x2055)
96c755a3
MB		 3603 unsupported = 1;
3604 break;
e4d6b795
MB		 3605 default:
3606 B43_WARN_ON(1);
3607 }
3608 if (unsupported) {
3609 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3610 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3611 radio_manuf, radio_ver, radio_rev);
3612 return -EOPNOTSUPP;
3613 }
3614 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3615 radio_manuf, radio_ver, radio_rev);
3616
3617 phy->radio_manuf = radio_manuf;
3618 phy->radio_ver = radio_ver;
3619 phy->radio_rev = radio_rev;
3620
3621 phy->analog = analog_type;
3622 phy->type = phy_type;
3623 phy->rev = phy_rev;
3624
3625 return 0;
3626}
3627
3628static void setup_struct_phy_for_init(struct b43_wldev *dev,
3629 struct b43_phy *phy)
3630{
3631 struct b43_txpower_lo_control *lo;
3632 int i;
3633
3634 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3635 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3636
e4d6b795
MB		 3637 phy->aci_enable = 0;
3638 phy->aci_wlan_automatic = 0;
3639 phy->aci_hw_rssi = 0;
3640
fda9abcf
MB		 3641 phy->radio_off_context.valid = 0;
3642
e4d6b795
MB		 3643 lo = phy->lo_control;
3644 if (lo) {
3645 memset(lo, 0, sizeof(*(phy->lo_control)));
3646 lo->rebuild = 1;
3647 lo->tx_bias = 0xFF;
3648 }
3649 phy->max_lb_gain = 0;
3650 phy->trsw_rx_gain = 0;
3651 phy->txpwr_offset = 0;
3652
3653 /* NRSSI */
3654 phy->nrssislope = 0;
3655 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3656 phy->nrssi[i] = -1000;
3657 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3658 phy->nrssi_lt[i] = i;
3659
3660 phy->lofcal = 0xFFFF;
3661 phy->initval = 0xFFFF;
3662
e4d6b795
MB		 3663 phy->interfmode = B43_INTERFMODE_NONE;
3664 phy->channel = 0xFF;
3665
3666 phy->hardware_power_control = !!modparam_hwpctl;
8ed7fc48
MB		 3667
3668 /* PHY TX errors counter. */
3669 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3670
3671 /* OFDM-table address caching. */
3672 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
e4d6b795
MB		 3673}
3674
3675static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3676{
aa6c7ae2
MB		 3677 dev->dfq_valid = 0;
3678
6a724d68
MB		 3679 /* Assume the radio is enabled. If it's not enabled, the state will
3680 * immediately get fixed on the first periodic work run. */
3681 dev->radio_hw_enable = 1;
e4d6b795
MB		 3682
3683 /* Stats */
3684 memset(&dev->stats, 0, sizeof(dev->stats));
3685
3686 setup_struct_phy_for_init(dev, &dev->phy);
3687
3688 /* IRQ related flags */
3689 dev->irq_reason = 0;
3690 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3691 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3692
3693 dev->mac_suspended = 1;
3694
3695 /* Noise calculation context */
3696 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3697}
3698
3699static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3700{
3701 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3702 u32 hf;
3703
95de2841 3704 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3705 return;
3706 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3707 return;
3708
3709 hf = b43_hf_read(dev);
95de2841 3710 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3711 hf |= B43_HF_BTCOEXALT;
3712 else
3713 hf |= B43_HF_BTCOEX;
3714 b43_hf_write(dev, hf);
3715 //TODO
3716}
3717
3718static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3719{ //TODO
3720}
3721
3722static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3723{
3724#ifdef CONFIG_SSB_DRIVER_PCICORE
3725 struct ssb_bus *bus = dev->dev->bus;
3726 u32 tmp;
3727
3728 if (bus->pcicore.dev &&
3729 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3730 bus->pcicore.dev->id.revision <= 5) {
3731 /* IMCFGLO timeouts workaround. */
3732 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3733 tmp &= ~SSB_IMCFGLO_REQTO;
3734 tmp &= ~SSB_IMCFGLO_SERTO;
3735 switch (bus->bustype) {
3736 case SSB_BUSTYPE_PCI:
3737 case SSB_BUSTYPE_PCMCIA:
3738 tmp |= 0x32;
3739 break;
3740 case SSB_BUSTYPE_SSB:
3741 tmp |= 0x53;
3742 break;
3743 }
3744 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3745 }
3746#endif /* CONFIG_SSB_DRIVER_PCICORE */
3747}
3748
74cfdba7
MB		 3749/* Write the short and long frame retry limit values. */
3750static void b43_set_retry_limits(struct b43_wldev *dev,
3751 unsigned int short_retry,
3752 unsigned int long_retry)
3753{
3754 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3755 * the chip-internal counter. */
3756 short_retry = min(short_retry, (unsigned int)0xF);
3757 long_retry = min(long_retry, (unsigned int)0xF);
3758
3759 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3760 short_retry);
3761 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3762 long_retry);
3763}
3764
d59f720d
MB		 3765static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3766{
3767 u16 pu_delay;
3768
3769 /* The time value is in microseconds. */
3770 if (dev->phy.type == B43_PHYTYPE_A)
3771 pu_delay = 3700;
3772 else
3773 pu_delay = 1050;
8cf6a31e 3774 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
d59f720d
MB		 3775 pu_delay = 500;
3776 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3777 pu_delay = max(pu_delay, (u16)2400);
3778
3779 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3780}
3781
3782/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3783static void b43_set_pretbtt(struct b43_wldev *dev)
3784{
3785 u16 pretbtt;
3786
3787 /* The time value is in microseconds. */
8cf6a31e 3788 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
d59f720d
MB		 3789 pretbtt = 2;
3790 } else {
3791 if (dev->phy.type == B43_PHYTYPE_A)
3792 pretbtt = 120;
3793 else
3794 pretbtt = 250;
3795 }
3796 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3797 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3798}
3799
e4d6b795
MB		 3800/* Shutdown a wireless core */
3801/* Locking: wl->mutex */
3802static void b43_wireless_core_exit(struct b43_wldev *dev)
3803{
3804 struct b43_phy *phy = &dev->phy;
1f7d87b0 3805 u32 macctl;
e4d6b795
MB		 3806
3807 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3808 if (b43_status(dev) != B43_STAT_INITIALIZED)
3809 return;
3810 b43_set_status(dev, B43_STAT_UNINIT);
3811
1f7d87b0
MB		 3812 /* Stop the microcode PSM. */
3813 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3814 macctl &= ~B43_MACCTL_PSM_RUN;
3815 macctl |= B43_MACCTL_PSM_JMP0;
3816 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3817
3506e0c4
RW		 3818 if (!dev->suspend_in_progress) {
3819 b43_leds_exit(dev);
3820 b43_rng_exit(dev->wl, false);
3821 }
e4d6b795 3822 b43_dma_free(dev);
5100d5ac 3823 b43_pio_free(dev);
e4d6b795 3824 b43_chip_exit(dev);
8e9f7529 3825 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3826 b43_switch_analog(dev, 0);
3827 if (phy->dyn_tssi_tbl)
3828 kfree(phy->tssi2dbm);
3829 kfree(phy->lo_control);
3830 phy->lo_control = NULL;
e66fee6a
MB		 3831 if (dev->wl->current_beacon) {
3832 dev_kfree_skb_any(dev->wl->current_beacon);
3833 dev->wl->current_beacon = NULL;
3834 }
3835
e4d6b795
MB		 3836 ssb_device_disable(dev->dev, 0);
3837 ssb_bus_may_powerdown(dev->dev->bus);
3838}
3839
3840/* Initialize a wireless core */
3841static int b43_wireless_core_init(struct b43_wldev *dev)
3842{
3843 struct b43_wl *wl = dev->wl;
3844 struct ssb_bus *bus = dev->dev->bus;
3845 struct ssb_sprom *sprom = &bus->sprom;
3846 struct b43_phy *phy = &dev->phy;
3847 int err;
3848 u32 hf, tmp;
3849
3850 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3851
3852 err = ssb_bus_powerup(bus, 0);
3853 if (err)
3854 goto out;
3855 if (!ssb_device_is_enabled(dev->dev)) {
3856 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3857 b43_wireless_core_reset(dev, tmp);
3858 }
3859
3860 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3861 phy->lo_control =
3862 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3863 if (!phy->lo_control) {
3864 err = -ENOMEM;
3865 goto err_busdown;
3866 }
3867 }
3868 setup_struct_wldev_for_init(dev);
3869
3870 err = b43_phy_init_tssi2dbm_table(dev);
3871 if (err)
3872 goto err_kfree_lo_control;
3873
3874 /* Enable IRQ routing to this device. */
3875 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3876
3877 b43_imcfglo_timeouts_workaround(dev);
3878 b43_bluetooth_coext_disable(dev);
3879 b43_phy_early_init(dev);
3880 err = b43_chip_init(dev);
3881 if (err)
3882 goto err_kfree_tssitbl;
3883 b43_shm_write16(dev, B43_SHM_SHARED,
3884 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3885 hf = b43_hf_read(dev);
3886 if (phy->type == B43_PHYTYPE_G) {
3887 hf |= B43_HF_SYMW;
3888 if (phy->rev == 1)
3889 hf |= B43_HF_GDCW;
95de2841 3890 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3891 hf |= B43_HF_OFDMPABOOST;
3892 } else if (phy->type == B43_PHYTYPE_B) {
3893 hf |= B43_HF_SYMW;
3894 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3895 hf &= ~B43_HF_GDCW;
3896 }
3897 b43_hf_write(dev, hf);
3898
74cfdba7
MB		 3899 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3900 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 3901 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3902 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3903
3904 /* Disable sending probe responses from firmware.
3905 * Setting the MaxTime to one usec will always trigger
3906 * a timeout, so we never send any probe resp.
3907 * A timeout of zero is infinite. */
3908 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3909
3910 b43_rate_memory_init(dev);
5042c507 3911 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 3912
3913 /* Minimum Contention Window */
3914 if (phy->type == B43_PHYTYPE_B) {
3915 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3916 } else {
3917 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3918 }
3919 /* Maximum Contention Window */
3920 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3921
5100d5ac
MB		 3922 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3923 dev->__using_pio_transfers = 1;
3924 err = b43_pio_init(dev);
3925 } else {
3926 dev->__using_pio_transfers = 0;
3927 err = b43_dma_init(dev);
3928 }
e4d6b795
MB		 3929 if (err)
3930 goto err_chip_exit;
03b29773 3931 b43_qos_init(dev);
d59f720d 3932 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 3933 b43_bluetooth_coext_enable(dev);
3934
3935 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3936 b43_upload_card_macaddress(dev);
e4d6b795 3937 b43_security_init(dev);
3506e0c4
RW		 3938 if (!dev->suspend_in_progress)
3939 b43_rng_init(wl);
e4d6b795
MB		 3940
3941 b43_set_status(dev, B43_STAT_INITIALIZED);
3942
3506e0c4
RW		 3943 if (!dev->suspend_in_progress)
3944 b43_leds_init(dev);
1a8d1227 3945out:
e4d6b795
MB		 3946 return err;
3947
3948 err_chip_exit:
3949 b43_chip_exit(dev);
3950 err_kfree_tssitbl:
3951 if (phy->dyn_tssi_tbl)
3952 kfree(phy->tssi2dbm);
3953 err_kfree_lo_control:
3954 kfree(phy->lo_control);
3955 phy->lo_control = NULL;
3956 err_busdown:
3957 ssb_bus_may_powerdown(bus);
3958 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3959 return err;
3960}
3961
40faacc4
MB		 3962static int b43_op_add_interface(struct ieee80211_hw *hw,
3963 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 3964{
3965 struct b43_wl *wl = hw_to_b43_wl(hw);
3966 struct b43_wldev *dev;
3967 unsigned long flags;
3968 int err = -EOPNOTSUPP;
4150c572
JB		 3969
3970 /* TODO: allow WDS/AP devices to coexist */
3971
3972 if (conf->type != IEEE80211_IF_TYPE_AP &&
3973 conf->type != IEEE80211_IF_TYPE_STA &&
3974 conf->type != IEEE80211_IF_TYPE_WDS &&
3975 conf->type != IEEE80211_IF_TYPE_IBSS)
3976 return -EOPNOTSUPP;
e4d6b795
MB		 3977
3978 mutex_lock(&wl->mutex);
4150c572 3979 if (wl->operating)
e4d6b795
MB		 3980 goto out_mutex_unlock;
3981
3982 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3983
3984 dev = wl->current_dev;
4150c572 3985 wl->operating = 1;
32bfd35d 3986 wl->vif = conf->vif;
4150c572
JB		 3987 wl->if_type = conf->type;
3988 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3989
3990 spin_lock_irqsave(&wl->irq_lock, flags);
3991 b43_adjust_opmode(dev);
d59f720d
MB		 3992 b43_set_pretbtt(dev);
3993 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 3994 b43_upload_card_macaddress(dev);
3995 spin_unlock_irqrestore(&wl->irq_lock, flags);
3996
3997 err = 0;
3998 out_mutex_unlock:
3999 mutex_unlock(&wl->mutex);
4000
4001 return err;
4002}
4003
40faacc4
MB		 4004static void b43_op_remove_interface(struct ieee80211_hw *hw,
4005 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4006{
4007 struct b43_wl *wl = hw_to_b43_wl(hw);
4008 struct b43_wldev *dev = wl->current_dev;
4009 unsigned long flags;
4010
4011 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4012
4013 mutex_lock(&wl->mutex);
4014
4015 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4016 B43_WARN_ON(wl->vif != conf->vif);
4017 wl->vif = NULL;
4150c572
JB		 4018
4019 wl->operating = 0;
4020
4021 spin_lock_irqsave(&wl->irq_lock, flags);
4022 b43_adjust_opmode(dev);
4023 memset(wl->mac_addr, 0, ETH_ALEN);
4024 b43_upload_card_macaddress(dev);
4025 spin_unlock_irqrestore(&wl->irq_lock, flags);
4026
4027 mutex_unlock(&wl->mutex);
4028}
4029
40faacc4 4030static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4031{
4032 struct b43_wl *wl = hw_to_b43_wl(hw);
4033 struct b43_wldev *dev = wl->current_dev;
4034 int did_init = 0;
923403b8 4035 int err = 0;
1946a2c3 4036 bool do_rfkill_exit = 0;
4150c572 4037
7be1bb6b
MB		 4038 /* Kill all old instance specific information to make sure
4039 * the card won't use it in the short timeframe between start
4040 * and mac80211 reconfiguring it. */
4041 memset(wl->bssid, 0, ETH_ALEN);
4042 memset(wl->mac_addr, 0, ETH_ALEN);
4043 wl->filter_flags = 0;
4044 wl->radiotap_enabled = 0;
e6f5b934 4045 b43_qos_clear(wl);
7be1bb6b 4046
1a8d1227
LF		 4047 /* First register RFkill.
4048 * LEDs that are registered later depend on it. */
4049 b43_rfkill_init(dev);
4050
4150c572
JB		 4051 mutex_lock(&wl->mutex);
4052
e4d6b795
MB		 4053 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4054 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4055 if (err) {
4056 do_rfkill_exit = 1;
e4d6b795 4057 goto out_mutex_unlock;
1946a2c3 4058 }
e4d6b795
MB		 4059 did_init = 1;
4060 }
4150c572 4061
e4d6b795
MB		 4062 if (b43_status(dev) < B43_STAT_STARTED) {
4063 err = b43_wireless_core_start(dev);
4064 if (err) {
4065 if (did_init)
4066 b43_wireless_core_exit(dev);
1946a2c3 4067 do_rfkill_exit = 1;
e4d6b795
MB		 4068 goto out_mutex_unlock;
4069 }
4070 }
4071
4150c572 4072 out_mutex_unlock:
e4d6b795
MB		 4073 mutex_unlock(&wl->mutex);
4074
1946a2c3
MB		 4075 if (do_rfkill_exit)
4076 b43_rfkill_exit(dev);
4077
e4d6b795
MB		 4078 return err;
4079}
4080
40faacc4 4081static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4082{
4083 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4084 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4085
1a8d1227 4086 b43_rfkill_exit(dev);
e6f5b934 4087 cancel_work_sync(&(wl->qos_update_work));
a82d9922 4088 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4089
e4d6b795 4090 mutex_lock(&wl->mutex);
4150c572
JB		 4091 if (b43_status(dev) >= B43_STAT_STARTED)
4092 b43_wireless_core_stop(dev);
4093 b43_wireless_core_exit(dev);
e4d6b795
MB		 4094 mutex_unlock(&wl->mutex);
4095}
4096
74cfdba7
MB		 4097static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4098 u32 short_retry_limit, u32 long_retry_limit)
4099{
4100 struct b43_wl *wl = hw_to_b43_wl(hw);
4101 struct b43_wldev *dev;
4102 int err = 0;
4103
4104 mutex_lock(&wl->mutex);
4105 dev = wl->current_dev;
4106 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4107 err = -ENODEV;
4108 goto out_unlock;
4109 }
4110 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4111out_unlock:
4112 mutex_unlock(&wl->mutex);
4113
4114 return err;
4115}
4116
e66fee6a
MB		 4117static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4118{
4119 struct b43_wl *wl = hw_to_b43_wl(hw);
4120 struct sk_buff *beacon;
d4df6f1a 4121 unsigned long flags;
5042c507 4122 struct ieee80211_tx_control txctl;
e66fee6a
MB		 4123
4124 /* We could modify the existing beacon and set the aid bit in
4125 * the TIM field, but that would probably require resizing and
4126 * moving of data within the beacon template.
4127 * Simply request a new beacon and let mac80211 do the hard work. */
5042c507 4128 beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
e66fee6a
MB		 4129 if (unlikely(!beacon))
4130 return -ENOMEM;
d4df6f1a 4131 spin_lock_irqsave(&wl->irq_lock, flags);
5042c507 4132 b43_update_templates(wl, beacon, &txctl);
d4df6f1a 4133 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4134
4135 return 0;
4136}
4137
4138static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4139 struct sk_buff *beacon,
4140 struct ieee80211_tx_control *ctl)
4141{
4142 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4143 unsigned long flags;
e66fee6a 4144
d4df6f1a 4145 spin_lock_irqsave(&wl->irq_lock, flags);
5042c507 4146 b43_update_templates(wl, beacon, ctl);
d4df6f1a 4147 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4148
4149 return 0;
4150}
4151
38968d09
JB		 4152static void b43_op_sta_notify(struct ieee80211_hw *hw,
4153 struct ieee80211_vif *vif,
4154 enum sta_notify_cmd notify_cmd,
4155 const u8 *addr)
4156{
4157 struct b43_wl *wl = hw_to_b43_wl(hw);
4158
4159 B43_WARN_ON(!vif || wl->vif != vif);
4160}
4161
e4d6b795 4162static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4163 .tx = b43_op_tx,
4164 .conf_tx = b43_op_conf_tx,
4165 .add_interface = b43_op_add_interface,
4166 .remove_interface = b43_op_remove_interface,
4167 .config = b43_op_config,
4168 .config_interface = b43_op_config_interface,
4169 .configure_filter = b43_op_configure_filter,
4170 .set_key = b43_op_set_key,
4171 .get_stats = b43_op_get_stats,
4172 .get_tx_stats = b43_op_get_tx_stats,
4173 .start = b43_op_start,
4174 .stop = b43_op_stop,
74cfdba7 4175 .set_retry_limit = b43_op_set_retry_limit,
e66fee6a
MB		 4176 .set_tim = b43_op_beacon_set_tim,
4177 .beacon_update = b43_op_ibss_beacon_update,
38968d09 4178 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4179};
4180
4181/* Hard-reset the chip. Do not call this directly.
4182 * Use b43_controller_restart()
4183 */
4184static void b43_chip_reset(struct work_struct *work)
4185{
4186 struct b43_wldev *dev =
4187 container_of(work, struct b43_wldev, restart_work);
4188 struct b43_wl *wl = dev->wl;
4189 int err = 0;
4190 int prev_status;
4191
4192 mutex_lock(&wl->mutex);
4193
4194 prev_status = b43_status(dev);
4195 /* Bring the device down... */
4196 if (prev_status >= B43_STAT_STARTED)
4197 b43_wireless_core_stop(dev);
4198 if (prev_status >= B43_STAT_INITIALIZED)
4199 b43_wireless_core_exit(dev);
4200
4201 /* ...and up again. */
4202 if (prev_status >= B43_STAT_INITIALIZED) {
4203 err = b43_wireless_core_init(dev);
4204 if (err)
4205 goto out;
4206 }
4207 if (prev_status >= B43_STAT_STARTED) {
4208 err = b43_wireless_core_start(dev);
4209 if (err) {
4210 b43_wireless_core_exit(dev);
4211 goto out;
4212 }
4213 }
4214 out:
4215 mutex_unlock(&wl->mutex);
4216 if (err)
4217 b43err(wl, "Controller restart FAILED\n");
4218 else
4219 b43info(wl, "Controller restarted\n");
4220}
4221
bb1eeff1 4222static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4223 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4224{
4225 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4226
bb1eeff1
MB		 4227 if (have_2ghz_phy)
4228 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4229 if (dev->phy.type == B43_PHYTYPE_N) {
4230 if (have_5ghz_phy)
4231 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4232 } else {
4233 if (have_5ghz_phy)
4234 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4235 }
96c755a3 4236
bb1eeff1
MB		 4237 dev->phy.supports_2ghz = have_2ghz_phy;
4238 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4239
4240 return 0;
4241}
4242
4243static void b43_wireless_core_detach(struct b43_wldev *dev)
4244{
4245 /* We release firmware that late to not be required to re-request
4246 * is all the time when we reinit the core. */
4247 b43_release_firmware(dev);
4248}
4249
4250static int b43_wireless_core_attach(struct b43_wldev *dev)
4251{
4252 struct b43_wl *wl = dev->wl;
4253 struct ssb_bus *bus = dev->dev->bus;
4254 struct pci_dev *pdev = bus->host_pci;
4255 int err;
96c755a3 4256 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4257 u32 tmp;
4258
4259 /* Do NOT do any device initialization here.
4260 * Do it in wireless_core_init() instead.
4261 * This function is for gathering basic information about the HW, only.
4262 * Also some structs may be set up here. But most likely you want to have
4263 * that in core_init(), too.
4264 */
4265
4266 err = ssb_bus_powerup(bus, 0);
4267 if (err) {
4268 b43err(wl, "Bus powerup failed\n");
4269 goto out;
4270 }
4271 /* Get the PHY type. */
4272 if (dev->dev->id.revision >= 5) {
4273 u32 tmshigh;
4274
4275 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4276 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4277 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4278 } else
96c755a3 4279 B43_WARN_ON(1);
e4d6b795 4280
96c755a3 4281 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4282 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4283 b43_wireless_core_reset(dev, tmp);
4284
4285 err = b43_phy_versioning(dev);
4286 if (err)
21954c36 4287 goto err_powerdown;
e4d6b795
MB		 4288 /* Check if this device supports multiband. */
4289 if (!pdev ||
4290 (pdev->device != 0x4312 &&
4291 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4292 /* No multiband support. */
96c755a3
MB		 4293 have_2ghz_phy = 0;
4294 have_5ghz_phy = 0;
e4d6b795
MB		 4295 switch (dev->phy.type) {
4296 case B43_PHYTYPE_A:
96c755a3 4297 have_5ghz_phy = 1;
e4d6b795
MB		 4298 break;
4299 case B43_PHYTYPE_G:
96c755a3
MB		 4300 case B43_PHYTYPE_N:
4301 have_2ghz_phy = 1;
e4d6b795
MB		 4302 break;
4303 default:
4304 B43_WARN_ON(1);
4305 }
4306 }
96c755a3
MB		 4307 if (dev->phy.type == B43_PHYTYPE_A) {
4308 /* FIXME */
4309 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4310 err = -EOPNOTSUPP;
4311 goto err_powerdown;
4312 }
4313 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4314 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4315 b43_wireless_core_reset(dev, tmp);
4316
4317 err = b43_validate_chipaccess(dev);
4318 if (err)
21954c36 4319 goto err_powerdown;
bb1eeff1 4320 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4321 if (err)
21954c36 4322 goto err_powerdown;
e4d6b795
MB		 4323
4324 /* Now set some default "current_dev" */
4325 if (!wl->current_dev)
4326 wl->current_dev = dev;
4327 INIT_WORK(&dev->restart_work, b43_chip_reset);
4328
8e9f7529 4329 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 4330 b43_switch_analog(dev, 0);
4331 ssb_device_disable(dev->dev, 0);
4332 ssb_bus_may_powerdown(bus);
4333
4334out:
4335 return err;
4336
e4d6b795
MB		 4337err_powerdown:
4338 ssb_bus_may_powerdown(bus);
4339 return err;
4340}
4341
4342static void b43_one_core_detach(struct ssb_device *dev)
4343{
4344 struct b43_wldev *wldev;
4345 struct b43_wl *wl;
4346
4347 wldev = ssb_get_drvdata(dev);
4348 wl = wldev->wl;
4349 cancel_work_sync(&wldev->restart_work);
4350 b43_debugfs_remove_device(wldev);
4351 b43_wireless_core_detach(wldev);
4352 list_del(&wldev->list);
4353 wl->nr_devs--;
4354 ssb_set_drvdata(dev, NULL);
4355 kfree(wldev);
4356}
4357
4358static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4359{
4360 struct b43_wldev *wldev;
4361 struct pci_dev *pdev;
4362 int err = -ENOMEM;
4363
4364 if (!list_empty(&wl->devlist)) {
4365 /* We are not the first core on this chip. */
4366 pdev = dev->bus->host_pci;
4367 /* Only special chips support more than one wireless
4368 * core, although some of the other chips have more than
4369 * one wireless core as well. Check for this and
4370 * bail out early.
4371 */
4372 if (!pdev ||
4373 ((pdev->device != 0x4321) &&
4374 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4375 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4376 return -ENODEV;
4377 }
4378 }
4379
4380 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4381 if (!wldev)
4382 goto out;
4383
4384 wldev->dev = dev;
4385 wldev->wl = wl;
4386 b43_set_status(wldev, B43_STAT_UNINIT);
4387 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4388 tasklet_init(&wldev->isr_tasklet,
4389 (void (*)(unsigned long))b43_interrupt_tasklet,
4390 (unsigned long)wldev);
e4d6b795
MB		 4391 INIT_LIST_HEAD(&wldev->list);
4392
4393 err = b43_wireless_core_attach(wldev);
4394 if (err)
4395 goto err_kfree_wldev;
4396
4397 list_add(&wldev->list, &wl->devlist);
4398 wl->nr_devs++;
4399 ssb_set_drvdata(dev, wldev);
4400 b43_debugfs_add_device(wldev);
4401
4402 out:
4403 return err;
4404
4405 err_kfree_wldev:
4406 kfree(wldev);
4407 return err;
4408}
4409
4410static void b43_sprom_fixup(struct ssb_bus *bus)
4411{
4412 /* boardflags workarounds */
4413 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4414 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4415 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4416 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4417 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4418 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
e4d6b795
MB		 4419}
4420
4421static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4422{
4423 struct ieee80211_hw *hw = wl->hw;
4424
4425 ssb_set_devtypedata(dev, NULL);
4426 ieee80211_free_hw(hw);
4427}
4428
4429static int b43_wireless_init(struct ssb_device *dev)
4430{
4431 struct ssb_sprom *sprom = &dev->bus->sprom;
4432 struct ieee80211_hw *hw;
4433 struct b43_wl *wl;
4434 int err = -ENOMEM;
4435
4436 b43_sprom_fixup(dev->bus);
4437
4438 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4439 if (!hw) {
4440 b43err(NULL, "Could not allocate ieee80211 device\n");
4441 goto out;
4442 }
4443
4444 /* fill hw info */
d8be11ee
JB		 4445 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4446 IEEE80211_HW_RX_INCLUDES_FCS;
e4d6b795
MB		 4447 hw->max_signal = 100;
4448 hw->max_rssi = -110;
4449 hw->max_noise = -110;
e6f5b934 4450 hw->queues = b43_modparam_qos ? 4 : 1;
e4d6b795 4451 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4452 if (is_valid_ether_addr(sprom->et1mac))
4453 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4454 else
95de2841 4455 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4456
4457 /* Get and initialize struct b43_wl */
4458 wl = hw_to_b43_wl(hw);
4459 memset(wl, 0, sizeof(*wl));
4460 wl->hw = hw;
4461 spin_lock_init(&wl->irq_lock);
4462 spin_lock_init(&wl->leds_lock);
280d0e16 4463 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4464 mutex_init(&wl->mutex);
4465 INIT_LIST_HEAD(&wl->devlist);
e6f5b934 4466 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
a82d9922 4467 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
e4d6b795
MB		 4468
4469 ssb_set_devtypedata(dev, wl);
4470 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4471 err = 0;
4472 out:
4473 return err;
4474}
4475
4476static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4477{
4478 struct b43_wl *wl;
4479 int err;
4480 int first = 0;
4481
4482 wl = ssb_get_devtypedata(dev);
4483 if (!wl) {
4484 /* Probing the first core. Must setup common struct b43_wl */
4485 first = 1;
4486 err = b43_wireless_init(dev);
4487 if (err)
4488 goto out;
4489 wl = ssb_get_devtypedata(dev);
4490 B43_WARN_ON(!wl);
4491 }
4492 err = b43_one_core_attach(dev, wl);
4493 if (err)
4494 goto err_wireless_exit;
4495
4496 if (first) {
4497 err = ieee80211_register_hw(wl->hw);
4498 if (err)
4499 goto err_one_core_detach;
4500 }
4501
4502 out:
4503 return err;
4504
4505 err_one_core_detach:
4506 b43_one_core_detach(dev);
4507 err_wireless_exit:
4508 if (first)
4509 b43_wireless_exit(dev, wl);
4510 return err;
4511}
4512
4513static void b43_remove(struct ssb_device *dev)
4514{
4515 struct b43_wl *wl = ssb_get_devtypedata(dev);
4516 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4517
4518 B43_WARN_ON(!wl);
4519 if (wl->current_dev == wldev)
4520 ieee80211_unregister_hw(wl->hw);
4521
4522 b43_one_core_detach(dev);
4523
4524 if (list_empty(&wl->devlist)) {
4525 /* Last core on the chip unregistered.
4526 * We can destroy common struct b43_wl.
4527 */
4528 b43_wireless_exit(dev, wl);
4529 }
4530}
4531
4532/* Perform a hardware reset. This can be called from any context. */
4533void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4534{
4535 /* Must avoid requeueing, if we are in shutdown. */
4536 if (b43_status(dev) < B43_STAT_INITIALIZED)
4537 return;
4538 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4539 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4540}
4541
4542#ifdef CONFIG_PM
4543
4544static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4545{
4546 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4547 struct b43_wl *wl = wldev->wl;
4548
4549 b43dbg(wl, "Suspending...\n");
4550
4551 mutex_lock(&wl->mutex);
3506e0c4 4552 wldev->suspend_in_progress = true;
e4d6b795
MB		 4553 wldev->suspend_init_status = b43_status(wldev);
4554 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4555 b43_wireless_core_stop(wldev);
4556 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4557 b43_wireless_core_exit(wldev);
4558 mutex_unlock(&wl->mutex);
4559
4560 b43dbg(wl, "Device suspended.\n");
4561
4562 return 0;
4563}
4564
4565static int b43_resume(struct ssb_device *dev)
4566{
4567 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4568 struct b43_wl *wl = wldev->wl;
4569 int err = 0;
4570
4571 b43dbg(wl, "Resuming...\n");
4572
4573 mutex_lock(&wl->mutex);
4574 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4575 err = b43_wireless_core_init(wldev);
4576 if (err) {
4577 b43err(wl, "Resume failed at core init\n");
4578 goto out;
4579 }
4580 }
4581 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4582 err = b43_wireless_core_start(wldev);
4583 if (err) {
3506e0c4
RW		 4584 b43_leds_exit(wldev);
4585 b43_rng_exit(wldev->wl, true);
e4d6b795
MB		 4586 b43_wireless_core_exit(wldev);
4587 b43err(wl, "Resume failed at core start\n");
4588 goto out;
4589 }
4590 }
e4d6b795 4591 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4592 out:
4593 wldev->suspend_in_progress = false;
4594 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4595 return err;
4596}
4597
4598#else /* CONFIG_PM */
4599# define b43_suspend NULL
4600# define b43_resume NULL
4601#endif /* CONFIG_PM */
4602
4603static struct ssb_driver b43_ssb_driver = {
4604 .name = KBUILD_MODNAME,
4605 .id_table = b43_ssb_tbl,
4606 .probe = b43_probe,
4607 .remove = b43_remove,
4608 .suspend = b43_suspend,
4609 .resume = b43_resume,
4610};
4611
26bc783f
MB		 4612static void b43_print_driverinfo(void)
4613{
4614 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4615 *feat_leds = "", *feat_rfkill = "";
4616
4617#ifdef CONFIG_B43_PCI_AUTOSELECT
4618 feat_pci = "P";
4619#endif
4620#ifdef CONFIG_B43_PCMCIA
4621 feat_pcmcia = "M";
4622#endif
4623#ifdef CONFIG_B43_NPHY
4624 feat_nphy = "N";
4625#endif
4626#ifdef CONFIG_B43_LEDS
4627 feat_leds = "L";
4628#endif
4629#ifdef CONFIG_B43_RFKILL
4630 feat_rfkill = "R";
4631#endif
4632 printk(KERN_INFO "Broadcom 43xx driver loaded "
4633 "[ Features: %s%s%s%s%s, Firmware-ID: "
4634 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4635 feat_pci, feat_pcmcia, feat_nphy,
4636 feat_leds, feat_rfkill);
4637}
4638
e4d6b795
MB		 4639static int __init b43_init(void)
4640{
4641 int err;
4642
4643 b43_debugfs_init();
4644 err = b43_pcmcia_init();
4645 if (err)
4646 goto err_dfs_exit;
4647 err = ssb_driver_register(&b43_ssb_driver);
4648 if (err)
4649 goto err_pcmcia_exit;
26bc783f 4650 b43_print_driverinfo();
e4d6b795
MB		 4651
4652 return err;
4653
4654err_pcmcia_exit:
4655 b43_pcmcia_exit();
4656err_dfs_exit:
4657 b43_debugfs_exit();
4658 return err;
4659}
4660
4661static void __exit b43_exit(void)
4662{
4663 ssb_driver_unregister(&b43_ssb_driver);
4664 b43_pcmcia_exit();
4665 b43_debugfs_exit();
4666}
4667
4668module_init(b43_init)
4669module_exit(b43_exit)
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