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b43: Fix IRQ sync for SDIO
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
3dbba8e2
AH		 11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
e4d6b795
MB		 14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32*/
33
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/moduleparam.h>
37#include <linux/if_arp.h>
38#include <linux/etherdevice.h>
e4d6b795
MB		 39#include <linux/firmware.h>
40#include <linux/wireless.h>
41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795
MB		 44#include <linux/dma-mapping.h>
45#include <asm/unaligned.h>
46
47#include "b43.h"
48#include "main.h"
49#include "debugfs.h"
ef1a628d
MB		 50#include "phy_common.h"
51#include "phy_g.h"
3d0da751 52#include "phy_n.h"
e4d6b795 53#include "dma.h"
5100d5ac 54#include "pio.h"
e4d6b795
MB		 55#include "sysfs.h"
56#include "xmit.h"
e4d6b795
MB		 57#include "lo.h"
58#include "pcmcia.h"
3dbba8e2
AH		 59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
0136e51e 66MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 67MODULE_LICENSE("GPL");
68
9c7d99d6
MB		 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
70
e4d6b795
MB		 71
72static int modparam_bad_frames_preempt;
73module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
74MODULE_PARM_DESC(bad_frames_preempt,
75 "enable(1) / disable(0) Bad Frames Preemption");
76
e4d6b795
MB		 77static char modparam_fwpostfix[16];
78module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
79MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
80
e4d6b795
MB		 81static int modparam_hwpctl;
82module_param_named(hwpctl, modparam_hwpctl, int, 0444);
83MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
84
85static int modparam_nohwcrypt;
86module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
87MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
88
035d0243 89static int modparam_hwtkip;
90module_param_named(hwtkip, modparam_hwtkip, int, 0444);
91MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
92
403a3a13
MB		 93static int modparam_qos = 1;
94module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 95MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
96
1855ba78
MB		 97static int modparam_btcoex = 1;
98module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 99MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 100
060210f9
MB		 101int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
102module_param_named(verbose, b43_modparam_verbose, int, 0644);
103MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
104
e6f5b934 105
e4d6b795
MB		 106static const struct ssb_device_id b43_ssb_tbl[] = {
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
111 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 112 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 113 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 114 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 116 SSB_DEVTABLE_END
117};
118
119MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
120
121/* Channel and ratetables are shared for all devices.
122 * They can't be const, because ieee80211 puts some precalculated
123 * data in there. This data is the same for all devices, so we don't
124 * get concurrency issues */
125#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 126 { \
127 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
128 .hw_value = (_rateid), \
129 .flags = (_flags), \
e4d6b795 130 }
8318d78a
JB		 131
132/*
133 * NOTE: When changing this, sync with xmit.c's
134 * b43_plcp_get_bitrate_idx_* functions!
135 */
e4d6b795 136static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 137 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
138 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
139 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
140 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
141 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
144 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
145 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
146 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
147 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
148 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 149};
150
151#define b43_a_ratetable (__b43_ratetable + 4)
152#define b43_a_ratetable_size 8
153#define b43_b_ratetable (__b43_ratetable + 0)
154#define b43_b_ratetable_size 4
155#define b43_g_ratetable (__b43_ratetable + 0)
156#define b43_g_ratetable_size 12
157
bb1eeff1
MB		 158#define CHAN4G(_channel, _freq, _flags) { \
159 .band = IEEE80211_BAND_2GHZ, \
160 .center_freq = (_freq), \
161 .hw_value = (_channel), \
162 .flags = (_flags), \
163 .max_antenna_gain = 0, \
164 .max_power = 30, \
165}
96c755a3 166static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 167 CHAN4G(1, 2412, 0),
168 CHAN4G(2, 2417, 0),
169 CHAN4G(3, 2422, 0),
170 CHAN4G(4, 2427, 0),
171 CHAN4G(5, 2432, 0),
172 CHAN4G(6, 2437, 0),
173 CHAN4G(7, 2442, 0),
174 CHAN4G(8, 2447, 0),
175 CHAN4G(9, 2452, 0),
176 CHAN4G(10, 2457, 0),
177 CHAN4G(11, 2462, 0),
178 CHAN4G(12, 2467, 0),
179 CHAN4G(13, 2472, 0),
180 CHAN4G(14, 2484, 0),
181};
182#undef CHAN4G
183
184#define CHAN5G(_channel, _flags) { \
185 .band = IEEE80211_BAND_5GHZ, \
186 .center_freq = 5000 + (5 * (_channel)), \
187 .hw_value = (_channel), \
188 .flags = (_flags), \
189 .max_antenna_gain = 0, \
190 .max_power = 30, \
191}
192static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
193 CHAN5G(32, 0), CHAN5G(34, 0),
194 CHAN5G(36, 0), CHAN5G(38, 0),
195 CHAN5G(40, 0), CHAN5G(42, 0),
196 CHAN5G(44, 0), CHAN5G(46, 0),
197 CHAN5G(48, 0), CHAN5G(50, 0),
198 CHAN5G(52, 0), CHAN5G(54, 0),
199 CHAN5G(56, 0), CHAN5G(58, 0),
200 CHAN5G(60, 0), CHAN5G(62, 0),
201 CHAN5G(64, 0), CHAN5G(66, 0),
202 CHAN5G(68, 0), CHAN5G(70, 0),
203 CHAN5G(72, 0), CHAN5G(74, 0),
204 CHAN5G(76, 0), CHAN5G(78, 0),
205 CHAN5G(80, 0), CHAN5G(82, 0),
206 CHAN5G(84, 0), CHAN5G(86, 0),
207 CHAN5G(88, 0), CHAN5G(90, 0),
208 CHAN5G(92, 0), CHAN5G(94, 0),
209 CHAN5G(96, 0), CHAN5G(98, 0),
210 CHAN5G(100, 0), CHAN5G(102, 0),
211 CHAN5G(104, 0), CHAN5G(106, 0),
212 CHAN5G(108, 0), CHAN5G(110, 0),
213 CHAN5G(112, 0), CHAN5G(114, 0),
214 CHAN5G(116, 0), CHAN5G(118, 0),
215 CHAN5G(120, 0), CHAN5G(122, 0),
216 CHAN5G(124, 0), CHAN5G(126, 0),
217 CHAN5G(128, 0), CHAN5G(130, 0),
218 CHAN5G(132, 0), CHAN5G(134, 0),
219 CHAN5G(136, 0), CHAN5G(138, 0),
220 CHAN5G(140, 0), CHAN5G(142, 0),
221 CHAN5G(144, 0), CHAN5G(145, 0),
222 CHAN5G(146, 0), CHAN5G(147, 0),
223 CHAN5G(148, 0), CHAN5G(149, 0),
224 CHAN5G(150, 0), CHAN5G(151, 0),
225 CHAN5G(152, 0), CHAN5G(153, 0),
226 CHAN5G(154, 0), CHAN5G(155, 0),
227 CHAN5G(156, 0), CHAN5G(157, 0),
228 CHAN5G(158, 0), CHAN5G(159, 0),
229 CHAN5G(160, 0), CHAN5G(161, 0),
230 CHAN5G(162, 0), CHAN5G(163, 0),
231 CHAN5G(164, 0), CHAN5G(165, 0),
232 CHAN5G(166, 0), CHAN5G(168, 0),
233 CHAN5G(170, 0), CHAN5G(172, 0),
234 CHAN5G(174, 0), CHAN5G(176, 0),
235 CHAN5G(178, 0), CHAN5G(180, 0),
236 CHAN5G(182, 0), CHAN5G(184, 0),
237 CHAN5G(186, 0), CHAN5G(188, 0),
238 CHAN5G(190, 0), CHAN5G(192, 0),
239 CHAN5G(194, 0), CHAN5G(196, 0),
240 CHAN5G(198, 0), CHAN5G(200, 0),
241 CHAN5G(202, 0), CHAN5G(204, 0),
242 CHAN5G(206, 0), CHAN5G(208, 0),
243 CHAN5G(210, 0), CHAN5G(212, 0),
244 CHAN5G(214, 0), CHAN5G(216, 0),
245 CHAN5G(218, 0), CHAN5G(220, 0),
246 CHAN5G(222, 0), CHAN5G(224, 0),
247 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 248};
249
bb1eeff1
MB		 250static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
251 CHAN5G(34, 0), CHAN5G(36, 0),
252 CHAN5G(38, 0), CHAN5G(40, 0),
253 CHAN5G(42, 0), CHAN5G(44, 0),
254 CHAN5G(46, 0), CHAN5G(48, 0),
255 CHAN5G(52, 0), CHAN5G(56, 0),
256 CHAN5G(60, 0), CHAN5G(64, 0),
257 CHAN5G(100, 0), CHAN5G(104, 0),
258 CHAN5G(108, 0), CHAN5G(112, 0),
259 CHAN5G(116, 0), CHAN5G(120, 0),
260 CHAN5G(124, 0), CHAN5G(128, 0),
261 CHAN5G(132, 0), CHAN5G(136, 0),
262 CHAN5G(140, 0), CHAN5G(149, 0),
263 CHAN5G(153, 0), CHAN5G(157, 0),
264 CHAN5G(161, 0), CHAN5G(165, 0),
265 CHAN5G(184, 0), CHAN5G(188, 0),
266 CHAN5G(192, 0), CHAN5G(196, 0),
267 CHAN5G(200, 0), CHAN5G(204, 0),
268 CHAN5G(208, 0), CHAN5G(212, 0),
269 CHAN5G(216, 0),
270};
271#undef CHAN5G
272
273static struct ieee80211_supported_band b43_band_5GHz_nphy = {
274 .band = IEEE80211_BAND_5GHZ,
275 .channels = b43_5ghz_nphy_chantable,
276 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
277 .bitrates = b43_a_ratetable,
278 .n_bitrates = b43_a_ratetable_size,
e4d6b795 279};
8318d78a 280
bb1eeff1
MB		 281static struct ieee80211_supported_band b43_band_5GHz_aphy = {
282 .band = IEEE80211_BAND_5GHZ,
283 .channels = b43_5ghz_aphy_chantable,
284 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
285 .bitrates = b43_a_ratetable,
286 .n_bitrates = b43_a_ratetable_size,
8318d78a 287};
e4d6b795 288
8318d78a 289static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 290 .band = IEEE80211_BAND_2GHZ,
291 .channels = b43_2ghz_chantable,
292 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
293 .bitrates = b43_g_ratetable,
294 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 295};
296
e4d6b795
MB		 297static void b43_wireless_core_exit(struct b43_wldev *dev);
298static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 299static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795
MB		 300static int b43_wireless_core_start(struct b43_wldev *dev);
301
302static int b43_ratelimit(struct b43_wl *wl)
303{
304 if (!wl || !wl->current_dev)
305 return 1;
306 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
307 return 1;
308 /* We are up and running.
309 * Ratelimit the messages to avoid DoS over the net. */
310 return net_ratelimit();
311}
312
313void b43info(struct b43_wl *wl, const char *fmt, ...)
314{
315 va_list args;
316
060210f9
MB		 317 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
318 return;
e4d6b795
MB		 319 if (!b43_ratelimit(wl))
320 return;
321 va_start(args, fmt);
322 printk(KERN_INFO "b43-%s: ",
323 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
324 vprintk(fmt, args);
325 va_end(args);
326}
327
328void b43err(struct b43_wl *wl, const char *fmt, ...)
329{
330 va_list args;
331
060210f9
MB		 332 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
333 return;
e4d6b795
MB		 334 if (!b43_ratelimit(wl))
335 return;
336 va_start(args, fmt);
337 printk(KERN_ERR "b43-%s ERROR: ",
338 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
339 vprintk(fmt, args);
340 va_end(args);
341}
342
343void b43warn(struct b43_wl *wl, const char *fmt, ...)
344{
345 va_list args;
346
060210f9
MB		 347 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
348 return;
e4d6b795
MB		 349 if (!b43_ratelimit(wl))
350 return;
351 va_start(args, fmt);
352 printk(KERN_WARNING "b43-%s warning: ",
353 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
354 vprintk(fmt, args);
355 va_end(args);
356}
357
e4d6b795
MB		 358void b43dbg(struct b43_wl *wl, const char *fmt, ...)
359{
360 va_list args;
361
060210f9
MB		 362 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
363 return;
e4d6b795
MB		 364 va_start(args, fmt);
365 printk(KERN_DEBUG "b43-%s debug: ",
366 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
367 vprintk(fmt, args);
368 va_end(args);
369}
e4d6b795
MB		 370
371static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
372{
373 u32 macctl;
374
375 B43_WARN_ON(offset % 4 != 0);
376
377 macctl = b43_read32(dev, B43_MMIO_MACCTL);
378 if (macctl & B43_MACCTL_BE)
379 val = swab32(val);
380
381 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
382 mmiowb();
383 b43_write32(dev, B43_MMIO_RAM_DATA, val);
384}
385
280d0e16
MB		 386static inline void b43_shm_control_word(struct b43_wldev *dev,
387 u16 routing, u16 offset)
e4d6b795
MB		 388{
389 u32 control;
390
391 /* "offset" is the WORD offset. */
e4d6b795
MB		 392 control = routing;
393 control <<= 16;
394 control |= offset;
395 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
396}
397
69eddc8a 398u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 399{
400 u32 ret;
401
402 if (routing == B43_SHM_SHARED) {
403 B43_WARN_ON(offset & 0x0001);
404 if (offset & 0x0003) {
405 /* Unaligned access */
406 b43_shm_control_word(dev, routing, offset >> 2);
407 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 408 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 409 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 410
280d0e16 411 goto out;
e4d6b795
MB		 412 }
413 offset >>= 2;
414 }
415 b43_shm_control_word(dev, routing, offset);
416 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 417out:
e4d6b795
MB		 418 return ret;
419}
420
69eddc8a 421u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 422{
423 u16 ret;
424
e4d6b795
MB		 425 if (routing == B43_SHM_SHARED) {
426 B43_WARN_ON(offset & 0x0001);
427 if (offset & 0x0003) {
428 /* Unaligned access */
429 b43_shm_control_word(dev, routing, offset >> 2);
430 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
431
280d0e16 432 goto out;
e4d6b795
MB		 433 }
434 offset >>= 2;
435 }
436 b43_shm_control_word(dev, routing, offset);
437 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 438out:
e4d6b795
MB		 439 return ret;
440}
441
69eddc8a 442void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 443{
e4d6b795
MB		 444 if (routing == B43_SHM_SHARED) {
445 B43_WARN_ON(offset & 0x0001);
446 if (offset & 0x0003) {
447 /* Unaligned access */
448 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 449 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 450 value & 0xFFFF);
e4d6b795 451 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 452 b43_write16(dev, B43_MMIO_SHM_DATA,
453 (value >> 16) & 0xFFFF);
6bbc321a 454 return;
e4d6b795
MB		 455 }
456 offset >>= 2;
457 }
458 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 459 b43_write32(dev, B43_MMIO_SHM_DATA, value);
460}
461
69eddc8a 462void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 463{
e4d6b795
MB		 464 if (routing == B43_SHM_SHARED) {
465 B43_WARN_ON(offset & 0x0001);
466 if (offset & 0x0003) {
467 /* Unaligned access */
468 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 469 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 470 return;
e4d6b795
MB		 471 }
472 offset >>= 2;
473 }
474 b43_shm_control_word(dev, routing, offset);
e4d6b795 475 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 476}
477
e4d6b795 478/* Read HostFlags */
99da185a 479u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 480{
35f0d354 481 u64 ret;
e4d6b795
MB		 482
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
484 ret <<= 16;
35f0d354
MB		 485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
486 ret <<= 16;
e4d6b795
MB		 487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488
489 return ret;
490}
491
492/* Write HostFlags */
35f0d354 493void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 494{
35f0d354
MB		 495 u16 lo, mi, hi;
496
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 503}
504
403a3a13
MB		 505/* Read the firmware capabilities bitmask (Opensource firmware only) */
506static u16 b43_fwcapa_read(struct b43_wldev *dev)
507{
508 B43_WARN_ON(!dev->fw.opensource);
509 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
510}
511
3ebbbb56 512void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 513{
3ebbbb56
MB		 514 u32 low, high;
515
516 B43_WARN_ON(dev->dev->id.revision < 3);
517
518 /* The hardware guarantees us an atomic read, if we
519 * read the low register first. */
520 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
521 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
522
523 *tsf = high;
524 *tsf <<= 32;
525 *tsf |= low;
e4d6b795
MB		 526}
527
528static void b43_time_lock(struct b43_wldev *dev)
529{
530 u32 macctl;
531
532 macctl = b43_read32(dev, B43_MMIO_MACCTL);
533 macctl |= B43_MACCTL_TBTTHOLD;
534 b43_write32(dev, B43_MMIO_MACCTL, macctl);
535 /* Commit the write */
536 b43_read32(dev, B43_MMIO_MACCTL);
537}
538
539static void b43_time_unlock(struct b43_wldev *dev)
540{
541 u32 macctl;
542
543 macctl = b43_read32(dev, B43_MMIO_MACCTL);
544 macctl &= ~B43_MACCTL_TBTTHOLD;
545 b43_write32(dev, B43_MMIO_MACCTL, macctl);
546 /* Commit the write */
547 b43_read32(dev, B43_MMIO_MACCTL);
548}
549
550static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
551{
3ebbbb56
MB		 552 u32 low, high;
553
554 B43_WARN_ON(dev->dev->id.revision < 3);
555
556 low = tsf;
557 high = (tsf >> 32);
558 /* The hardware guarantees us an atomic write, if we
559 * write the low register first. */
560 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
561 mmiowb();
562 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
563 mmiowb();
e4d6b795
MB		 564}
565
566void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
567{
568 b43_time_lock(dev);
569 b43_tsf_write_locked(dev, tsf);
570 b43_time_unlock(dev);
571}
572
573static
99da185a 574void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 575{
576 static const u8 zero_addr[ETH_ALEN] = { 0 };
577 u16 data;
578
579 if (!mac)
580 mac = zero_addr;
581
582 offset |= 0x0020;
583 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
584
585 data = mac[0];
586 data |= mac[1] << 8;
587 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
588 data = mac[2];
589 data |= mac[3] << 8;
590 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
591 data = mac[4];
592 data |= mac[5] << 8;
593 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
594}
595
596static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
597{
598 const u8 *mac;
599 const u8 *bssid;
600 u8 mac_bssid[ETH_ALEN * 2];
601 int i;
602 u32 tmp;
603
604 bssid = dev->wl->bssid;
605 mac = dev->wl->mac_addr;
606
607 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
608
609 memcpy(mac_bssid, mac, ETH_ALEN);
610 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
611
612 /* Write our MAC address and BSSID to template ram */
613 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
614 tmp = (u32) (mac_bssid[i + 0]);
615 tmp |= (u32) (mac_bssid[i + 1]) << 8;
616 tmp |= (u32) (mac_bssid[i + 2]) << 16;
617 tmp |= (u32) (mac_bssid[i + 3]) << 24;
618 b43_ram_write(dev, 0x20 + i, tmp);
619 }
620}
621
4150c572 622static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 623{
e4d6b795 624 b43_write_mac_bssid_templates(dev);
4150c572 625 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 626}
627
628static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
629{
630 /* slot_time is in usec. */
631 if (dev->phy.type != B43_PHYTYPE_G)
632 return;
633 b43_write16(dev, 0x684, 510 + slot_time);
634 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
635}
636
637static void b43_short_slot_timing_enable(struct b43_wldev *dev)
638{
639 b43_set_slot_time(dev, 9);
e4d6b795
MB		 640}
641
642static void b43_short_slot_timing_disable(struct b43_wldev *dev)
643{
644 b43_set_slot_time(dev, 20);
e4d6b795
MB		 645}
646
e4d6b795 647/* DummyTransmission function, as documented on
2f19c287 648 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 649 */
2f19c287 650void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 651{
652 struct b43_phy *phy = &dev->phy;
653 unsigned int i, max_loop;
654 u16 value;
655 u32 buffer[5] = {
656 0x00000000,
657 0x00D40000,
658 0x00000000,
659 0x01000000,
660 0x00000000,
661 };
662
2f19c287 663 if (ofdm) {
e4d6b795
MB		 664 max_loop = 0x1E;
665 buffer[0] = 0x000201CC;
2f19c287 666 } else {
e4d6b795
MB		 667 max_loop = 0xFA;
668 buffer[0] = 0x000B846E;
e4d6b795
MB		 669 }
670
671 for (i = 0; i < 5; i++)
672 b43_ram_write(dev, i * 4, buffer[i]);
673
e4d6b795 674 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 675 if (dev->dev->id.revision < 11)
676 b43_write16(dev, 0x07C0, 0x0000);
677 else
678 b43_write16(dev, 0x07C0, 0x0100);
679 value = (ofdm ? 0x41 : 0x40);
e4d6b795 680 b43_write16(dev, 0x050C, value);
2f19c287
GS		 681 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
682 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 683 b43_write16(dev, 0x0508, 0x0000);
684 b43_write16(dev, 0x050A, 0x0000);
685 b43_write16(dev, 0x054C, 0x0000);
686 b43_write16(dev, 0x056A, 0x0014);
687 b43_write16(dev, 0x0568, 0x0826);
688 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 689 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
690 //SPEC TODO
691 }
692
693 switch (phy->type) {
694 case B43_PHYTYPE_N:
695 b43_write16(dev, 0x0502, 0x00D0);
696 break;
697 case B43_PHYTYPE_LP:
698 b43_write16(dev, 0x0502, 0x0050);
699 break;
700 default:
701 b43_write16(dev, 0x0502, 0x0030);
702 }
e4d6b795
MB		 703
704 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
705 b43_radio_write16(dev, 0x0051, 0x0017);
706 for (i = 0x00; i < max_loop; i++) {
707 value = b43_read16(dev, 0x050E);
708 if (value & 0x0080)
709 break;
710 udelay(10);
711 }
712 for (i = 0x00; i < 0x0A; i++) {
713 value = b43_read16(dev, 0x050E);
714 if (value & 0x0400)
715 break;
716 udelay(10);
717 }
1d280ddc 718 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 719 value = b43_read16(dev, 0x0690);
720 if (!(value & 0x0100))
721 break;
722 udelay(10);
723 }
724 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
725 b43_radio_write16(dev, 0x0051, 0x0037);
726}
727
728static void key_write(struct b43_wldev *dev,
99da185a 729 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 730{
731 unsigned int i;
732 u32 offset;
733 u16 value;
734 u16 kidx;
735
736 /* Key index/algo block */
737 kidx = b43_kidx_to_fw(dev, index);
738 value = ((kidx << 4) | algorithm);
739 b43_shm_write16(dev, B43_SHM_SHARED,
740 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
741
742 /* Write the key to the Key Table Pointer offset */
743 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
744 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
745 value = key[i];
746 value |= (u16) (key[i + 1]) << 8;
747 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
748 }
749}
750
99da185a 751static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 752{
753 u32 addrtmp[2] = { 0, 0, };
66d2d089 754 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 755
756 if (b43_new_kidx_api(dev))
66d2d089 757 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 758
66d2d089
MB		 759 B43_WARN_ON(index < pairwise_keys_start);
760 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 761 * Physical mac 0 is mapped to physical key 4 or 8, depending
762 * on the firmware version.
763 * So we must adjust the index here.
764 */
66d2d089
MB		 765 index -= pairwise_keys_start;
766 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 767
768 if (addr) {
769 addrtmp[0] = addr[0];
770 addrtmp[0] |= ((u32) (addr[1]) << 8);
771 addrtmp[0] |= ((u32) (addr[2]) << 16);
772 addrtmp[0] |= ((u32) (addr[3]) << 24);
773 addrtmp[1] = addr[4];
774 addrtmp[1] |= ((u32) (addr[5]) << 8);
775 }
776
66d2d089
MB		 777 /* Receive match transmitter address (RCMTA) mechanism */
778 b43_shm_write32(dev, B43_SHM_RCMTA,
779 (index * 2) + 0, addrtmp[0]);
780 b43_shm_write16(dev, B43_SHM_RCMTA,
781 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 782}
783
035d0243 784/* The ucode will use phase1 key with TEK key to decrypt rx packets.
785 * When a packet is received, the iv32 is checked.
786 * - if it doesn't the packet is returned without modification (and software
787 * decryption can be done). That's what happen when iv16 wrap.
788 * - if it does, the rc4 key is computed, and decryption is tried.
789 * Either it will success and B43_RX_MAC_DEC is returned,
790 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
791 * and the packet is not usable (it got modified by the ucode).
792 * So in order to never have B43_RX_MAC_DECERR, we should provide
793 * a iv32 and phase1key that match. Because we drop packets in case of
794 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
795 * packets will be lost without higher layer knowing (ie no resync possible
796 * until next wrap).
797 *
798 * NOTE : this should support 50 key like RCMTA because
799 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
800 */
801static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
802 u16 *phase1key)
803{
804 unsigned int i;
805 u32 offset;
806 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
807
808 if (!modparam_hwtkip)
809 return;
810
811 if (b43_new_kidx_api(dev))
812 pairwise_keys_start = B43_NR_GROUP_KEYS;
813
814 B43_WARN_ON(index < pairwise_keys_start);
815 /* We have four default TX keys and possibly four default RX keys.
816 * Physical mac 0 is mapped to physical key 4 or 8, depending
817 * on the firmware version.
818 * So we must adjust the index here.
819 */
820 index -= pairwise_keys_start;
821 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
822
823 if (b43_debug(dev, B43_DBG_KEYS)) {
824 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
825 index, iv32);
826 }
827 /* Write the key to the RX tkip shared mem */
828 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
829 for (i = 0; i < 10; i += 2) {
830 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
831 phase1key ? phase1key[i / 2] : 0);
832 }
833 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
834 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
835}
836
837static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
838 struct ieee80211_key_conf *keyconf, const u8 *addr,
839 u32 iv32, u16 *phase1key)
840{
841 struct b43_wl *wl = hw_to_b43_wl(hw);
842 struct b43_wldev *dev;
843 int index = keyconf->hw_key_idx;
844
845 if (B43_WARN_ON(!modparam_hwtkip))
846 return;
847
848 mutex_lock(&wl->mutex);
849
850 dev = wl->current_dev;
851 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
852 goto out_unlock;
853
854 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
855
856 rx_tkip_phase1_write(dev, index, iv32, phase1key);
857 keymac_write(dev, index, addr);
858
859out_unlock:
860 mutex_unlock(&wl->mutex);
861}
862
e4d6b795
MB		 863static void do_key_write(struct b43_wldev *dev,
864 u8 index, u8 algorithm,
99da185a 865 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 866{
867 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 868 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 869
870 if (b43_new_kidx_api(dev))
66d2d089 871 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 872
66d2d089 873 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 874 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
875
66d2d089 876 if (index >= pairwise_keys_start)
e4d6b795 877 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 878 if (algorithm == B43_SEC_ALGO_TKIP) {
879 /*
880 * We should provide an initial iv32, phase1key pair.
881 * We could start with iv32=0 and compute the corresponding
882 * phase1key, but this means calling ieee80211_get_tkip_key
883 * with a fake skb (or export other tkip function).
884 * Because we are lazy we hope iv32 won't start with
885 * 0xffffffff and let's b43_op_update_tkip_key provide a
886 * correct pair.
887 */
888 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
889 } else if (index >= pairwise_keys_start) /* clear it */
890 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 891 if (key)
892 memcpy(buf, key, key_len);
893 key_write(dev, index, algorithm, buf);
66d2d089 894 if (index >= pairwise_keys_start)
e4d6b795
MB		 895 keymac_write(dev, index, mac_addr);
896
897 dev->key[index].algorithm = algorithm;
898}
899
900static int b43_key_write(struct b43_wldev *dev,
901 int index, u8 algorithm,
99da185a
JD		 902 const u8 *key, size_t key_len,
903 const u8 *mac_addr,
e4d6b795
MB		 904 struct ieee80211_key_conf *keyconf)
905{
906 int i;
66d2d089 907 int pairwise_keys_start;
e4d6b795 908
035d0243 909 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
910 * - Temporal Encryption Key (128 bits)
911 * - Temporal Authenticator Tx MIC Key (64 bits)
912 * - Temporal Authenticator Rx MIC Key (64 bits)
913 *
914 * Hardware only store TEK
915 */
916 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
917 key_len = 16;
e4d6b795
MB		 918 if (key_len > B43_SEC_KEYSIZE)
919 return -EINVAL;
66d2d089 920 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 921 /* Check that we don't already have this key. */
922 B43_WARN_ON(dev->key[i].keyconf == keyconf);
923 }
924 if (index < 0) {
e808e586 925 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 926 if (b43_new_kidx_api(dev))
66d2d089 927 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 928 else
66d2d089
MB		 929 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
930 for (i = pairwise_keys_start;
931 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
932 i++) {
933 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 934 if (!dev->key[i].keyconf) {
935 /* found empty */
936 index = i;
937 break;
938 }
939 }
940 if (index < 0) {
e808e586 941 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 942 return -ENOSPC;
943 }
944 } else
945 B43_WARN_ON(index > 3);
946
947 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
948 if ((index <= 3) && !b43_new_kidx_api(dev)) {
949 /* Default RX key */
950 B43_WARN_ON(mac_addr);
951 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
952 }
953 keyconf->hw_key_idx = index;
954 dev->key[index].keyconf = keyconf;
955
956 return 0;
957}
958
959static int b43_key_clear(struct b43_wldev *dev, int index)
960{
66d2d089 961 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 962 return -EINVAL;
963 do_key_write(dev, index, B43_SEC_ALGO_NONE,
964 NULL, B43_SEC_KEYSIZE, NULL);
965 if ((index <= 3) && !b43_new_kidx_api(dev)) {
966 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
967 NULL, B43_SEC_KEYSIZE, NULL);
968 }
969 dev->key[index].keyconf = NULL;
970
971 return 0;
972}
973
974static void b43_clear_keys(struct b43_wldev *dev)
975{
66d2d089 976 int i, count;
e4d6b795 977
66d2d089
MB		 978 if (b43_new_kidx_api(dev))
979 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
980 else
981 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
982 for (i = 0; i < count; i++)
e4d6b795
MB		 983 b43_key_clear(dev, i);
984}
985
9cf7f247
MB		 986static void b43_dump_keymemory(struct b43_wldev *dev)
987{
66d2d089 988 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 989 u8 mac[ETH_ALEN];
990 u16 algo;
991 u32 rcmta0;
992 u16 rcmta1;
993 u64 hf;
994 struct b43_key *key;
995
996 if (!b43_debug(dev, B43_DBG_KEYS))
997 return;
998
999 hf = b43_hf_read(dev);
1000 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1001 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1002 if (b43_new_kidx_api(dev)) {
1003 pairwise_keys_start = B43_NR_GROUP_KEYS;
1004 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1005 } else {
1006 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1007 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1008 }
1009 for (index = 0; index < count; index++) {
9cf7f247
MB		 1010 key = &(dev->key[index]);
1011 printk(KERN_DEBUG "Key slot %02u: %s",
1012 index, (key->keyconf == NULL) ? " " : "*");
1013 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1014 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1015 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1016 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1017 }
1018
1019 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1020 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1021 printk(" Algo: %04X/%02X", algo, key->algorithm);
1022
66d2d089 1023 if (index >= pairwise_keys_start) {
035d0243 1024 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1025 printk(" TKIP: ");
1026 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1027 for (i = 0; i < 14; i += 2) {
1028 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1029 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1030 }
1031 }
9cf7f247 1032 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1033 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1034 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1035 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1036 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1037 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1038 printk(" MAC: %pM", mac);
9cf7f247
MB		 1039 } else
1040 printk(" DEFAULT KEY");
1041 printk("\n");
1042 }
1043}
1044
e4d6b795
MB		 1045void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1046{
1047 u32 macctl;
1048 u16 ucstat;
1049 bool hwps;
1050 bool awake;
1051 int i;
1052
1053 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1054 (ps_flags & B43_PS_DISABLED));
1055 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1056
1057 if (ps_flags & B43_PS_ENABLED) {
1058 hwps = 1;
1059 } else if (ps_flags & B43_PS_DISABLED) {
1060 hwps = 0;
1061 } else {
1062 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1063 // and thus is not an AP and we are associated, set bit 25
1064 }
1065 if (ps_flags & B43_PS_AWAKE) {
1066 awake = 1;
1067 } else if (ps_flags & B43_PS_ASLEEP) {
1068 awake = 0;
1069 } else {
1070 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1071 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1072 // successful, set bit26
1073 }
1074
1075/* FIXME: For now we force awake-on and hwps-off */
1076 hwps = 0;
1077 awake = 1;
1078
1079 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1080 if (hwps)
1081 macctl |= B43_MACCTL_HWPS;
1082 else
1083 macctl &= ~B43_MACCTL_HWPS;
1084 if (awake)
1085 macctl |= B43_MACCTL_AWAKE;
1086 else
1087 macctl &= ~B43_MACCTL_AWAKE;
1088 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1089 /* Commit write */
1090 b43_read32(dev, B43_MMIO_MACCTL);
1091 if (awake && dev->dev->id.revision >= 5) {
1092 /* Wait for the microcode to wake up. */
1093 for (i = 0; i < 100; i++) {
1094 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1095 B43_SHM_SH_UCODESTAT);
1096 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1097 break;
1098 udelay(10);
1099 }
1100 }
1101}
1102
e4d6b795
MB		 1103void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1104{
1105 u32 tmslow;
1106 u32 macctl;
1107
1108 flags |= B43_TMSLOW_PHYCLKEN;
1109 flags |= B43_TMSLOW_PHYRESET;
1110 ssb_device_enable(dev->dev, flags);
1111 msleep(2); /* Wait for the PLL to turn on. */
1112
1113 /* Now take the PHY out of Reset again */
1114 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1115 tmslow |= SSB_TMSLOW_FGC;
1116 tmslow &= ~B43_TMSLOW_PHYRESET;
1117 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1118 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1119 msleep(1);
1120 tmslow &= ~SSB_TMSLOW_FGC;
1121 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1122 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1123 msleep(1);
1124
fb11137a
MB		 1125 /* Turn Analog ON, but only if we already know the PHY-type.
1126 * This protects against very early setup where we don't know the
1127 * PHY-type, yet. wireless_core_reset will be called once again later,
1128 * when we know the PHY-type. */
1129 if (dev->phy.ops)
cb24f57f 1130 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1131
1132 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1133 macctl &= ~B43_MACCTL_GMODE;
1134 if (flags & B43_TMSLOW_GMODE)
1135 macctl |= B43_MACCTL_GMODE;
1136 macctl |= B43_MACCTL_IHR_ENABLED;
1137 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1138}
1139
1140static void handle_irq_transmit_status(struct b43_wldev *dev)
1141{
1142 u32 v0, v1;
1143 u16 tmp;
1144 struct b43_txstatus stat;
1145
1146 while (1) {
1147 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1148 if (!(v0 & 0x00000001))
1149 break;
1150 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1151
1152 stat.cookie = (v0 >> 16);
1153 stat.seq = (v1 & 0x0000FFFF);
1154 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1155 tmp = (v0 & 0x0000FFFF);
1156 stat.frame_count = ((tmp & 0xF000) >> 12);
1157 stat.rts_count = ((tmp & 0x0F00) >> 8);
1158 stat.supp_reason = ((tmp & 0x001C) >> 2);
1159 stat.pm_indicated = !!(tmp & 0x0080);
1160 stat.intermediate = !!(tmp & 0x0040);
1161 stat.for_ampdu = !!(tmp & 0x0020);
1162 stat.acked = !!(tmp & 0x0002);
1163
1164 b43_handle_txstatus(dev, &stat);
1165 }
1166}
1167
1168static void drain_txstatus_queue(struct b43_wldev *dev)
1169{
1170 u32 dummy;
1171
1172 if (dev->dev->id.revision < 5)
1173 return;
1174 /* Read all entries from the microcode TXstatus FIFO
1175 * and throw them away.
1176 */
1177 while (1) {
1178 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1179 if (!(dummy & 0x00000001))
1180 break;
1181 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1182 }
1183}
1184
1185static u32 b43_jssi_read(struct b43_wldev *dev)
1186{
1187 u32 val = 0;
1188
1189 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1190 val <<= 16;
1191 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1192
1193 return val;
1194}
1195
1196static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1197{
1198 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1199 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1200}
1201
1202static void b43_generate_noise_sample(struct b43_wldev *dev)
1203{
1204 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1205 b43_write32(dev, B43_MMIO_MACCMD,
1206 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1207}
1208
1209static void b43_calculate_link_quality(struct b43_wldev *dev)
1210{
1211 /* Top half of Link Quality calculation. */
1212
ef1a628d
MB		 1213 if (dev->phy.type != B43_PHYTYPE_G)
1214 return;
e4d6b795
MB		 1215 if (dev->noisecalc.calculation_running)
1216 return;
e4d6b795
MB		 1217 dev->noisecalc.calculation_running = 1;
1218 dev->noisecalc.nr_samples = 0;
1219
1220 b43_generate_noise_sample(dev);
1221}
1222
1223static void handle_irq_noise(struct b43_wldev *dev)
1224{
ef1a628d 1225 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1226 u16 tmp;
1227 u8 noise[4];
1228 u8 i, j;
1229 s32 average;
1230
1231 /* Bottom half of Link Quality calculation. */
1232
ef1a628d
MB		 1233 if (dev->phy.type != B43_PHYTYPE_G)
1234 return;
1235
98a3b2fe
MB		 1236 /* Possible race condition: It might be possible that the user
1237 * changed to a different channel in the meantime since we
1238 * started the calculation. We ignore that fact, since it's
1239 * not really that much of a problem. The background noise is
1240 * an estimation only anyway. Slightly wrong results will get damped
1241 * by the averaging of the 8 sample rounds. Additionally the
1242 * value is shortlived. So it will be replaced by the next noise
1243 * calculation round soon. */
1244
e4d6b795 1245 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1246 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1247 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1248 noise[2] == 0x7F || noise[3] == 0x7F)
1249 goto generate_new;
1250
1251 /* Get the noise samples. */
1252 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1253 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1254 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1255 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1256 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1257 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1258 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1259 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1260 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1261 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1262 dev->noisecalc.nr_samples++;
1263 if (dev->noisecalc.nr_samples == 8) {
1264 /* Calculate the Link Quality by the noise samples. */
1265 average = 0;
1266 for (i = 0; i < 8; i++) {
1267 for (j = 0; j < 4; j++)
1268 average += dev->noisecalc.samples[i][j];
1269 }
1270 average /= (8 * 4);
1271 average *= 125;
1272 average += 64;
1273 average /= 128;
1274 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1275 tmp = (tmp / 128) & 0x1F;
1276 if (tmp >= 8)
1277 average += 2;
1278 else
1279 average -= 25;
1280 if (tmp == 8)
1281 average -= 72;
1282 else
1283 average -= 48;
1284
1285 dev->stats.link_noise = average;
e4d6b795
MB		 1286 dev->noisecalc.calculation_running = 0;
1287 return;
1288 }
98a3b2fe 1289generate_new:
e4d6b795
MB		 1290 b43_generate_noise_sample(dev);
1291}
1292
1293static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1294{
05c914fe 1295 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1296 ///TODO: PS TBTT
1297 } else {
1298 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1299 b43_power_saving_ctl_bits(dev, 0);
1300 }
05c914fe 1301 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1302 dev->dfq_valid = 1;
e4d6b795
MB		 1303}
1304
1305static void handle_irq_atim_end(struct b43_wldev *dev)
1306{
aa6c7ae2
MB		 1307 if (dev->dfq_valid) {
1308 b43_write32(dev, B43_MMIO_MACCMD,
1309 b43_read32(dev, B43_MMIO_MACCMD)
1310 | B43_MACCMD_DFQ_VALID);
1311 dev->dfq_valid = 0;
1312 }
e4d6b795
MB		 1313}
1314
1315static void handle_irq_pmq(struct b43_wldev *dev)
1316{
1317 u32 tmp;
1318
1319 //TODO: AP mode.
1320
1321 while (1) {
1322 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1323 if (!(tmp & 0x00000008))
1324 break;
1325 }
1326 /* 16bit write is odd, but correct. */
1327 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1328}
1329
1330static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1331 const u8 *data, u16 size,
e4d6b795
MB		 1332 u16 ram_offset,
1333 u16 shm_size_offset, u8 rate)
1334{
1335 u32 i, tmp;
1336 struct b43_plcp_hdr4 plcp;
1337
1338 plcp.data = 0;
1339 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1340 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1341 ram_offset += sizeof(u32);
1342 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1343 * So leave the first two bytes of the next write blank.
1344 */
1345 tmp = (u32) (data[0]) << 16;
1346 tmp |= (u32) (data[1]) << 24;
1347 b43_ram_write(dev, ram_offset, tmp);
1348 ram_offset += sizeof(u32);
1349 for (i = 2; i < size; i += sizeof(u32)) {
1350 tmp = (u32) (data[i + 0]);
1351 if (i + 1 < size)
1352 tmp |= (u32) (data[i + 1]) << 8;
1353 if (i + 2 < size)
1354 tmp |= (u32) (data[i + 2]) << 16;
1355 if (i + 3 < size)
1356 tmp |= (u32) (data[i + 3]) << 24;
1357 b43_ram_write(dev, ram_offset + i - 2, tmp);
1358 }
1359 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1360 size + sizeof(struct b43_plcp_hdr6));
1361}
1362
5042c507
MB		 1363/* Check if the use of the antenna that ieee80211 told us to
1364 * use is possible. This will fall back to DEFAULT.
1365 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1366u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1367 u8 antenna_nr)
1368{
1369 u8 antenna_mask;
1370
1371 if (antenna_nr == 0) {
1372 /* Zero means "use default antenna". That's always OK. */
1373 return 0;
1374 }
1375
1376 /* Get the mask of available antennas. */
1377 if (dev->phy.gmode)
1378 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1379 else
1380 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1381
1382 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1383 /* This antenna is not available. Fall back to default. */
1384 return 0;
1385 }
1386
1387 return antenna_nr;
1388}
1389
5042c507
MB		 1390/* Convert a b43 antenna number value to the PHY TX control value. */
1391static u16 b43_antenna_to_phyctl(int antenna)
1392{
1393 switch (antenna) {
1394 case B43_ANTENNA0:
1395 return B43_TXH_PHY_ANT0;
1396 case B43_ANTENNA1:
1397 return B43_TXH_PHY_ANT1;
1398 case B43_ANTENNA2:
1399 return B43_TXH_PHY_ANT2;
1400 case B43_ANTENNA3:
1401 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1402 case B43_ANTENNA_AUTO0:
1403 case B43_ANTENNA_AUTO1:
5042c507
MB		 1404 return B43_TXH_PHY_ANT01AUTO;
1405 }
1406 B43_WARN_ON(1);
1407 return 0;
1408}
1409
e4d6b795
MB		 1410static void b43_write_beacon_template(struct b43_wldev *dev,
1411 u16 ram_offset,
5042c507 1412 u16 shm_size_offset)
e4d6b795 1413{
47f76ca3 1414 unsigned int i, len, variable_len;
e66fee6a
MB		 1415 const struct ieee80211_mgmt *bcn;
1416 const u8 *ie;
1417 bool tim_found = 0;
5042c507
MB		 1418 unsigned int rate;
1419 u16 ctl;
1420 int antenna;
e039fa4a 1421 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1422
e66fee6a
MB		 1423 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1424 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1425 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1426 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1427
1428 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1429 len, ram_offset, shm_size_offset, rate);
e66fee6a 1430
5042c507 1431 /* Write the PHY TX control parameters. */
0f4ac38b 1432 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1433 antenna = b43_antenna_to_phyctl(antenna);
1434 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1435 /* We can't send beacons with short preamble. Would get PHY errors. */
1436 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1437 ctl &= ~B43_TXH_PHY_ANT;
1438 ctl &= ~B43_TXH_PHY_ENC;
1439 ctl |= antenna;
1440 if (b43_is_cck_rate(rate))
1441 ctl |= B43_TXH_PHY_ENC_CCK;
1442 else
1443 ctl |= B43_TXH_PHY_ENC_OFDM;
1444 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1445
e66fee6a
MB		 1446 /* Find the position of the TIM and the DTIM_period value
1447 * and write them to SHM. */
1448 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1449 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1450 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1451 uint8_t ie_id, ie_len;
1452
1453 ie_id = ie[i];
1454 ie_len = ie[i + 1];
1455 if (ie_id == 5) {
1456 u16 tim_position;
1457 u16 dtim_period;
1458 /* This is the TIM Information Element */
1459
1460 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1461 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1462 break;
1463 /* A valid TIM is at least 4 bytes long. */
1464 if (ie_len < 4)
1465 break;
1466 tim_found = 1;
1467
1468 tim_position = sizeof(struct b43_plcp_hdr6);
1469 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1470 tim_position += i;
1471
1472 dtim_period = ie[i + 3];
1473
1474 b43_shm_write16(dev, B43_SHM_SHARED,
1475 B43_SHM_SH_TIMBPOS, tim_position);
1476 b43_shm_write16(dev, B43_SHM_SHARED,
1477 B43_SHM_SH_DTIMPER, dtim_period);
1478 break;
1479 }
1480 i += ie_len + 2;
1481 }
1482 if (!tim_found) {
04dea136
JB		 1483 /*
1484 * If ucode wants to modify TIM do it behind the beacon, this
1485 * will happen, for example, when doing mesh networking.
1486 */
1487 b43_shm_write16(dev, B43_SHM_SHARED,
1488 B43_SHM_SH_TIMBPOS,
1489 len + sizeof(struct b43_plcp_hdr6));
1490 b43_shm_write16(dev, B43_SHM_SHARED,
1491 B43_SHM_SH_DTIMPER, 0);
1492 }
1493 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1494}
1495
6b4bec01
MB		 1496static void b43_upload_beacon0(struct b43_wldev *dev)
1497{
1498 struct b43_wl *wl = dev->wl;
1499
1500 if (wl->beacon0_uploaded)
1501 return;
1502 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1503 wl->beacon0_uploaded = 1;
1504}
1505
1506static void b43_upload_beacon1(struct b43_wldev *dev)
1507{
1508 struct b43_wl *wl = dev->wl;
1509
1510 if (wl->beacon1_uploaded)
1511 return;
1512 b43_write_beacon_template(dev, 0x468, 0x1A);
1513 wl->beacon1_uploaded = 1;
1514}
1515
c97a4ccc
MB		 1516static void handle_irq_beacon(struct b43_wldev *dev)
1517{
1518 struct b43_wl *wl = dev->wl;
1519 u32 cmd, beacon0_valid, beacon1_valid;
1520
05c914fe
JB		 1521 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1522 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1523 return;
1524
1525 /* This is the bottom half of the asynchronous beacon update. */
1526
1527 /* Ignore interrupt in the future. */
13790728 1528 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1529
1530 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1531 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1532 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1533
1534 /* Schedule interrupt manually, if busy. */
1535 if (beacon0_valid && beacon1_valid) {
1536 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1537 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1538 return;
1539 }
1540
6b4bec01
MB		 1541 if (unlikely(wl->beacon_templates_virgin)) {
1542 /* We never uploaded a beacon before.
1543 * Upload both templates now, but only mark one valid. */
1544 wl->beacon_templates_virgin = 0;
1545 b43_upload_beacon0(dev);
1546 b43_upload_beacon1(dev);
c97a4ccc
MB		 1547 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1548 cmd |= B43_MACCMD_BEACON0_VALID;
1549 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1550 } else {
1551 if (!beacon0_valid) {
1552 b43_upload_beacon0(dev);
1553 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1554 cmd |= B43_MACCMD_BEACON0_VALID;
1555 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1556 } else if (!beacon1_valid) {
1557 b43_upload_beacon1(dev);
1558 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1559 cmd |= B43_MACCMD_BEACON1_VALID;
1560 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1561 }
c97a4ccc
MB		 1562 }
1563}
1564
36dbd954
MB		 1565static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1566{
1567 u32 old_irq_mask = dev->irq_mask;
1568
1569 /* update beacon right away or defer to irq */
1570 handle_irq_beacon(dev);
1571 if (old_irq_mask != dev->irq_mask) {
1572 /* The handler updated the IRQ mask. */
1573 B43_WARN_ON(!dev->irq_mask);
1574 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1575 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1576 } else {
1577 /* Device interrupts are currently disabled. That means
1578 * we just ran the hardirq handler and scheduled the
1579 * IRQ thread. The thread will write the IRQ mask when
1580 * it finished, so there's nothing to do here. Writing
1581 * the mask _here_ would incorrectly re-enable IRQs. */
1582 }
1583 }
1584}
1585
a82d9922
MB		 1586static void b43_beacon_update_trigger_work(struct work_struct *work)
1587{
1588 struct b43_wl *wl = container_of(work, struct b43_wl,
1589 beacon_update_trigger);
1590 struct b43_wldev *dev;
1591
1592 mutex_lock(&wl->mutex);
1593 dev = wl->current_dev;
1594 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
3dbba8e2 1595 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
36dbd954
MB		 1596 /* wl->mutex is enough. */
1597 b43_do_beacon_update_trigger_work(dev);
1598 mmiowb();
1599 } else {
1600 spin_lock_irq(&wl->hardirq_lock);
1601 b43_do_beacon_update_trigger_work(dev);
1602 mmiowb();
1603 spin_unlock_irq(&wl->hardirq_lock);
1604 }
a82d9922
MB		 1605 }
1606 mutex_unlock(&wl->mutex);
1607}
1608
d4df6f1a 1609/* Asynchronously update the packet templates in template RAM.
36dbd954 1610 * Locking: Requires wl->mutex to be locked. */
9d139c81 1611static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1612{
9d139c81
JB		 1613 struct sk_buff *beacon;
1614
e66fee6a
MB		 1615 /* This is the top half of the ansynchronous beacon update.
1616 * The bottom half is the beacon IRQ.
1617 * Beacon update must be asynchronous to avoid sending an
1618 * invalid beacon. This can happen for example, if the firmware
1619 * transmits a beacon while we are updating it. */
e4d6b795 1620
9d139c81
JB		 1621 /* We could modify the existing beacon and set the aid bit in
1622 * the TIM field, but that would probably require resizing and
1623 * moving of data within the beacon template.
1624 * Simply request a new beacon and let mac80211 do the hard work. */
1625 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1626 if (unlikely(!beacon))
1627 return;
1628
e66fee6a
MB		 1629 if (wl->current_beacon)
1630 dev_kfree_skb_any(wl->current_beacon);
1631 wl->current_beacon = beacon;
1632 wl->beacon0_uploaded = 0;
1633 wl->beacon1_uploaded = 0;
42935eca 1634 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1635}
1636
e4d6b795
MB		 1637static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1638{
1639 b43_time_lock(dev);
1640 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1641 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1642 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1643 } else {
1644 b43_write16(dev, 0x606, (beacon_int >> 6));
1645 b43_write16(dev, 0x610, beacon_int);
1646 }
1647 b43_time_unlock(dev);
a82d9922 1648 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1649}
1650
afa83e23
MB		 1651static void b43_handle_firmware_panic(struct b43_wldev *dev)
1652{
1653 u16 reason;
1654
1655 /* Read the register that contains the reason code for the panic. */
1656 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1657 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1658
1659 switch (reason) {
1660 default:
1661 b43dbg(dev->wl, "The panic reason is unknown.\n");
1662 /* fallthrough */
1663 case B43_FWPANIC_DIE:
1664 /* Do not restart the controller or firmware.
1665 * The device is nonfunctional from now on.
1666 * Restarting would result in this panic to trigger again,
1667 * so we avoid that recursion. */
1668 break;
1669 case B43_FWPANIC_RESTART:
1670 b43_controller_restart(dev, "Microcode panic");
1671 break;
1672 }
1673}
1674
e4d6b795
MB		 1675static void handle_irq_ucode_debug(struct b43_wldev *dev)
1676{
e48b0eeb 1677 unsigned int i, cnt;
53c06856 1678 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1679 __le16 *buf;
1680
1681 /* The proprietary firmware doesn't have this IRQ. */
1682 if (!dev->fw.opensource)
1683 return;
1684
afa83e23
MB		 1685 /* Read the register that contains the reason code for this IRQ. */
1686 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1687
e48b0eeb
MB		 1688 switch (reason) {
1689 case B43_DEBUGIRQ_PANIC:
afa83e23 1690 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1691 break;
1692 case B43_DEBUGIRQ_DUMP_SHM:
1693 if (!B43_DEBUG)
1694 break; /* Only with driver debugging enabled. */
1695 buf = kmalloc(4096, GFP_ATOMIC);
1696 if (!buf) {
1697 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1698 goto out;
1699 }
1700 for (i = 0; i < 4096; i += 2) {
1701 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1702 buf[i / 2] = cpu_to_le16(tmp);
1703 }
1704 b43info(dev->wl, "Shared memory dump:\n");
1705 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1706 16, 2, buf, 4096, 1);
1707 kfree(buf);
1708 break;
1709 case B43_DEBUGIRQ_DUMP_REGS:
1710 if (!B43_DEBUG)
1711 break; /* Only with driver debugging enabled. */
1712 b43info(dev->wl, "Microcode register dump:\n");
1713 for (i = 0, cnt = 0; i < 64; i++) {
1714 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1715 if (cnt == 0)
1716 printk(KERN_INFO);
1717 printk("r%02u: 0x%04X ", i, tmp);
1718 cnt++;
1719 if (cnt == 6) {
1720 printk("\n");
1721 cnt = 0;
1722 }
1723 }
1724 printk("\n");
1725 break;
53c06856
MB		 1726 case B43_DEBUGIRQ_MARKER:
1727 if (!B43_DEBUG)
1728 break; /* Only with driver debugging enabled. */
1729 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1730 B43_MARKER_ID_REG);
1731 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1732 B43_MARKER_LINE_REG);
1733 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1734 "at line number %u\n",
1735 marker_id, marker_line);
1736 break;
e48b0eeb
MB		 1737 default:
1738 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1739 reason);
1740 }
1741out:
afa83e23
MB		 1742 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1743 b43_shm_write16(dev, B43_SHM_SCRATCH,
1744 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1745}
1746
36dbd954 1747static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1748{
1749 u32 reason;
1750 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1751 u32 merged_dma_reason = 0;
21954c36 1752 int i;
e4d6b795 1753
36dbd954
MB		 1754 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1755 return;
e4d6b795
MB		 1756
1757 reason = dev->irq_reason;
1758 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1759 dma_reason[i] = dev->dma_reason[i];
1760 merged_dma_reason |= dma_reason[i];
1761 }
1762
1763 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1764 b43err(dev->wl, "MAC transmission error\n");
1765
00e0b8cb 1766 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1767 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1768 rmb();
1769 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1770 atomic_set(&dev->phy.txerr_cnt,
1771 B43_PHY_TX_BADNESS_LIMIT);
1772 b43err(dev->wl, "Too many PHY TX errors, "
1773 "restarting the controller\n");
1774 b43_controller_restart(dev, "PHY TX errors");
1775 }
1776 }
e4d6b795
MB		 1777
1778 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1779 B43_DMAIRQ_NONFATALMASK))) {
1780 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1781 b43err(dev->wl, "Fatal DMA error: "
1782 "0x%08X, 0x%08X, 0x%08X, "
1783 "0x%08X, 0x%08X, 0x%08X\n",
1784 dma_reason[0], dma_reason[1],
1785 dma_reason[2], dma_reason[3],
1786 dma_reason[4], dma_reason[5]);
1787 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1788 return;
1789 }
1790 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1791 b43err(dev->wl, "DMA error: "
1792 "0x%08X, 0x%08X, 0x%08X, "
1793 "0x%08X, 0x%08X, 0x%08X\n",
1794 dma_reason[0], dma_reason[1],
1795 dma_reason[2], dma_reason[3],
1796 dma_reason[4], dma_reason[5]);
1797 }
1798 }
1799
1800 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1801 handle_irq_ucode_debug(dev);
1802 if (reason & B43_IRQ_TBTT_INDI)
1803 handle_irq_tbtt_indication(dev);
1804 if (reason & B43_IRQ_ATIM_END)
1805 handle_irq_atim_end(dev);
1806 if (reason & B43_IRQ_BEACON)
1807 handle_irq_beacon(dev);
1808 if (reason & B43_IRQ_PMQ)
1809 handle_irq_pmq(dev);
21954c36
MB		 1810 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1811 ;/* TODO */
1812 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1813 handle_irq_noise(dev);
1814
1815 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1816 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1817 if (b43_using_pio_transfers(dev))
1818 b43_pio_rx(dev->pio.rx_queue);
1819 else
1820 b43_dma_rx(dev->dma.rx_ring);
1821 }
e4d6b795
MB		 1822 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1823 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1824 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1825 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1826 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1827
21954c36 1828 if (reason & B43_IRQ_TX_OK)
e4d6b795 1829 handle_irq_transmit_status(dev);
e4d6b795 1830
36dbd954 1831 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1832 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1833}
1834
36dbd954
MB		 1835/* Interrupt thread handler. Handles device interrupts in thread context. */
1836static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1837{
36dbd954 1838 struct b43_wldev *dev = dev_id;
e4d6b795 1839
36dbd954
MB		 1840 mutex_lock(&dev->wl->mutex);
1841 b43_do_interrupt_thread(dev);
1842 mmiowb();
1843 mutex_unlock(&dev->wl->mutex);
1844
1845 return IRQ_HANDLED;
e4d6b795
MB		 1846}
1847
36dbd954 1848static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1849{
e4d6b795
MB		 1850 u32 reason;
1851
36dbd954
MB		 1852 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1853 * On SDIO, this runs under wl->mutex. */
e4d6b795 1854
e4d6b795
MB		 1855 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1856 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1857 return IRQ_NONE;
13790728 1858 reason &= dev->irq_mask;
e4d6b795 1859 if (!reason)
36dbd954 1860 return IRQ_HANDLED;
e4d6b795
MB		 1861
1862 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1863 & 0x0001DC00;
1864 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1865 & 0x0000DC00;
1866 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1867 & 0x0000DC00;
1868 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1869 & 0x0001DC00;
1870 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1871 & 0x0000DC00;
13790728 1872/* Unused ring
e4d6b795
MB		 1873 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1874 & 0x0000DC00;
13790728 1875*/
e4d6b795 1876
36dbd954
MB		 1877 /* ACK the interrupt. */
1878 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1879 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1880 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1881 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1882 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1883 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1884/* Unused ring
1885 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1886*/
1887
1888 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 1889 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 1890 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 1891 dev->irq_reason = reason;
36dbd954
MB		 1892
1893 return IRQ_WAKE_THREAD;
1894}
1895
1896/* Interrupt handler top-half. This runs with interrupts disabled. */
1897static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1898{
1899 struct b43_wldev *dev = dev_id;
1900 irqreturn_t ret;
1901
1902 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1903 return IRQ_NONE;
1904
1905 spin_lock(&dev->wl->hardirq_lock);
1906 ret = b43_do_interrupt(dev);
e4d6b795 1907 mmiowb();
36dbd954 1908 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 1909
1910 return ret;
1911}
1912
3dbba8e2
AH		 1913/* SDIO interrupt handler. This runs in process context. */
1914static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1915{
1916 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 1917 irqreturn_t ret;
1918
3dbba8e2 1919 mutex_lock(&wl->mutex);
3dbba8e2
AH		 1920
1921 ret = b43_do_interrupt(dev);
1922 if (ret == IRQ_WAKE_THREAD)
1923 b43_do_interrupt_thread(dev);
1924
3dbba8e2
AH		 1925 mutex_unlock(&wl->mutex);
1926}
1927
1a9f5093 1928void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1929{
1930 release_firmware(fw->data);
1931 fw->data = NULL;
1932 fw->filename = NULL;
1933}
1934
e4d6b795
MB		 1935static void b43_release_firmware(struct b43_wldev *dev)
1936{
1a9f5093
MB		 1937 b43_do_release_fw(&dev->fw.ucode);
1938 b43_do_release_fw(&dev->fw.pcm);
1939 b43_do_release_fw(&dev->fw.initvals);
1940 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1941}
1942
eb189d8b 1943static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1944{
fc68ed4f
HE		 1945 const char text[] =
1946 "You must go to " \
1947 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1948 "and download the correct firmware for this driver version. " \
1949 "Please carefully read all instructions on this website.\n";
eb189d8b 1950
eb189d8b
MB		 1951 if (error)
1952 b43err(wl, text);
1953 else
1954 b43warn(wl, text);
e4d6b795
MB		 1955}
1956
1a9f5093
MB		 1957int b43_do_request_fw(struct b43_request_fw_context *ctx,
1958 const char *name,
1959 struct b43_firmware_file *fw)
e4d6b795 1960{
61cb5dd6 1961 const struct firmware *blob;
e4d6b795
MB		 1962 struct b43_fw_header *hdr;
1963 u32 size;
1964 int err;
1965
61cb5dd6
MB		 1966 if (!name) {
1967 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1968 /* FIXME: We should probably keep it anyway, to save some headache
1969 * on suspend/resume with multiband devices. */
1970 b43_do_release_fw(fw);
e4d6b795 1971 return 0;
61cb5dd6
MB		 1972 }
1973 if (fw->filename) {
1a9f5093
MB		 1974 if ((fw->type == ctx->req_type) &&
1975 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1976 return 0; /* Already have this fw. */
1977 /* Free the cached firmware first. */
1a9f5093
MB		 1978 /* FIXME: We should probably do this later after we successfully
1979 * got the new fw. This could reduce headache with multiband devices.
1980 * We could also redesign this to cache the firmware for all possible
1981 * bands all the time. */
1982 b43_do_release_fw(fw);
61cb5dd6 1983 }
e4d6b795 1984
1a9f5093
MB		 1985 switch (ctx->req_type) {
1986 case B43_FWTYPE_PROPRIETARY:
1987 snprintf(ctx->fwname, sizeof(ctx->fwname),
1988 "b43%s/%s.fw",
1989 modparam_fwpostfix, name);
1990 break;
1991 case B43_FWTYPE_OPENSOURCE:
1992 snprintf(ctx->fwname, sizeof(ctx->fwname),
1993 "b43-open%s/%s.fw",
1994 modparam_fwpostfix, name);
1995 break;
1996 default:
1997 B43_WARN_ON(1);
1998 return -ENOSYS;
1999 }
2000 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2001 if (err == -ENOENT) {
1a9f5093
MB		 2002 snprintf(ctx->errors[ctx->req_type],
2003 sizeof(ctx->errors[ctx->req_type]),
2004 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2005 return err;
2006 } else if (err) {
1a9f5093
MB		 2007 snprintf(ctx->errors[ctx->req_type],
2008 sizeof(ctx->errors[ctx->req_type]),
2009 "Firmware file \"%s\" request failed (err=%d)\n",
2010 ctx->fwname, err);
e4d6b795
MB		 2011 return err;
2012 }
61cb5dd6 2013 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2014 goto err_format;
61cb5dd6 2015 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2016 switch (hdr->type) {
2017 case B43_FW_TYPE_UCODE:
2018 case B43_FW_TYPE_PCM:
2019 size = be32_to_cpu(hdr->size);
61cb5dd6 2020 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2021 goto err_format;
2022 /* fallthrough */
2023 case B43_FW_TYPE_IV:
2024 if (hdr->ver != 1)
2025 goto err_format;
2026 break;
2027 default:
2028 goto err_format;
2029 }
2030
61cb5dd6
MB		 2031 fw->data = blob;
2032 fw->filename = name;
1a9f5093 2033 fw->type = ctx->req_type;
61cb5dd6
MB		 2034
2035 return 0;
e4d6b795
MB		 2036
2037err_format:
1a9f5093
MB		 2038 snprintf(ctx->errors[ctx->req_type],
2039 sizeof(ctx->errors[ctx->req_type]),
2040 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2041 release_firmware(blob);
2042
e4d6b795
MB		 2043 return -EPROTO;
2044}
2045
1a9f5093 2046static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2047{
1a9f5093
MB		 2048 struct b43_wldev *dev = ctx->dev;
2049 struct b43_firmware *fw = &ctx->dev->fw;
2050 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2051 const char *filename;
2052 u32 tmshigh;
2053 int err;
2054
61cb5dd6 2055 /* Get microcode */
e4d6b795 2056 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2057 if ((rev >= 5) && (rev <= 10))
2058 filename = "ucode5";
2059 else if ((rev >= 11) && (rev <= 12))
2060 filename = "ucode11";
759b973b 2061 else if (rev == 13)
61cb5dd6 2062 filename = "ucode13";
759b973b
GS		 2063 else if (rev == 14)
2064 filename = "ucode14";
2065 else if (rev >= 15)
2066 filename = "ucode15";
61cb5dd6
MB		 2067 else
2068 goto err_no_ucode;
1a9f5093 2069 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2070 if (err)
2071 goto err_load;
2072
2073 /* Get PCM code */
2074 if ((rev >= 5) && (rev <= 10))
2075 filename = "pcm5";
2076 else if (rev >= 11)
2077 filename = NULL;
2078 else
2079 goto err_no_pcm;
68217832 2080 fw->pcm_request_failed = 0;
1a9f5093 2081 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2082 if (err == -ENOENT) {
2083 /* We did not find a PCM file? Not fatal, but
2084 * core rev <= 10 must do without hwcrypto then. */
2085 fw->pcm_request_failed = 1;
2086 } else if (err)
61cb5dd6
MB		 2087 goto err_load;
2088
2089 /* Get initvals */
2090 switch (dev->phy.type) {
2091 case B43_PHYTYPE_A:
2092 if ((rev >= 5) && (rev <= 10)) {
2093 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2094 filename = "a0g1initvals5";
2095 else
2096 filename = "a0g0initvals5";
2097 } else
2098 goto err_no_initvals;
2099 break;
2100 case B43_PHYTYPE_G:
e4d6b795 2101 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2102 filename = "b0g0initvals5";
e4d6b795 2103 else if (rev >= 13)
e9304882 2104 filename = "b0g0initvals13";
e4d6b795 2105 else
61cb5dd6
MB		 2106 goto err_no_initvals;
2107 break;
2108 case B43_PHYTYPE_N:
2109 if ((rev >= 11) && (rev <= 12))
2110 filename = "n0initvals11";
2111 else
2112 goto err_no_initvals;
2113 break;
759b973b
GS		 2114 case B43_PHYTYPE_LP:
2115 if (rev == 13)
2116 filename = "lp0initvals13";
2117 else if (rev == 14)
2118 filename = "lp0initvals14";
2119 else if (rev >= 15)
2120 filename = "lp0initvals15";
2121 else
2122 goto err_no_initvals;
2123 break;
61cb5dd6
MB		 2124 default:
2125 goto err_no_initvals;
e4d6b795 2126 }
1a9f5093 2127 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2128 if (err)
2129 goto err_load;
2130
2131 /* Get bandswitch initvals */
2132 switch (dev->phy.type) {
2133 case B43_PHYTYPE_A:
2134 if ((rev >= 5) && (rev <= 10)) {
2135 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2136 filename = "a0g1bsinitvals5";
2137 else
2138 filename = "a0g0bsinitvals5";
2139 } else if (rev >= 11)
2140 filename = NULL;
2141 else
2142 goto err_no_initvals;
2143 break;
2144 case B43_PHYTYPE_G:
e4d6b795 2145 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2146 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2147 else if (rev >= 11)
2148 filename = NULL;
2149 else
e4d6b795 2150 goto err_no_initvals;
61cb5dd6
MB		 2151 break;
2152 case B43_PHYTYPE_N:
2153 if ((rev >= 11) && (rev <= 12))
2154 filename = "n0bsinitvals11";
2155 else
e4d6b795 2156 goto err_no_initvals;
61cb5dd6 2157 break;
759b973b
GS		 2158 case B43_PHYTYPE_LP:
2159 if (rev == 13)
2160 filename = "lp0bsinitvals13";
2161 else if (rev == 14)
2162 filename = "lp0bsinitvals14";
2163 else if (rev >= 15)
2164 filename = "lp0bsinitvals15";
2165 else
2166 goto err_no_initvals;
2167 break;
61cb5dd6
MB		 2168 default:
2169 goto err_no_initvals;
e4d6b795 2170 }
1a9f5093 2171 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2172 if (err)
2173 goto err_load;
e4d6b795
MB		 2174
2175 return 0;
2176
e4d6b795 2177err_no_ucode:
1a9f5093
MB		 2178 err = ctx->fatal_failure = -EOPNOTSUPP;
2179 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2180 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2181 goto error;
2182
2183err_no_pcm:
1a9f5093
MB		 2184 err = ctx->fatal_failure = -EOPNOTSUPP;
2185 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2186 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2187 goto error;
2188
2189err_no_initvals:
1a9f5093
MB		 2190 err = ctx->fatal_failure = -EOPNOTSUPP;
2191 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2192 "is required for your device (wl-core rev %u)\n", rev);
2193 goto error;
2194
2195err_load:
2196 /* We failed to load this firmware image. The error message
2197 * already is in ctx->errors. Return and let our caller decide
2198 * what to do. */
e4d6b795
MB		 2199 goto error;
2200
2201error:
2202 b43_release_firmware(dev);
2203 return err;
2204}
2205
1a9f5093
MB		 2206static int b43_request_firmware(struct b43_wldev *dev)
2207{
2208 struct b43_request_fw_context *ctx;
2209 unsigned int i;
2210 int err;
2211 const char *errmsg;
2212
2213 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2214 if (!ctx)
2215 return -ENOMEM;
2216 ctx->dev = dev;
2217
2218 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2219 err = b43_try_request_fw(ctx);
2220 if (!err)
2221 goto out; /* Successfully loaded it. */
2222 err = ctx->fatal_failure;
2223 if (err)
2224 goto out;
2225
2226 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2227 err = b43_try_request_fw(ctx);
2228 if (!err)
2229 goto out; /* Successfully loaded it. */
2230 err = ctx->fatal_failure;
2231 if (err)
2232 goto out;
2233
2234 /* Could not find a usable firmware. Print the errors. */
2235 for (i = 0; i < B43_NR_FWTYPES; i++) {
2236 errmsg = ctx->errors[i];
2237 if (strlen(errmsg))
2238 b43err(dev->wl, errmsg);
2239 }
2240 b43_print_fw_helptext(dev->wl, 1);
2241 err = -ENOENT;
2242
2243out:
2244 kfree(ctx);
2245 return err;
2246}
2247
e4d6b795
MB		 2248static int b43_upload_microcode(struct b43_wldev *dev)
2249{
2250 const size_t hdr_len = sizeof(struct b43_fw_header);
2251 const __be32 *data;
2252 unsigned int i, len;
2253 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2254 u32 tmp, macctl;
e4d6b795
MB		 2255 int err = 0;
2256
1f7d87b0
MB		 2257 /* Jump the microcode PSM to offset 0 */
2258 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2259 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2260 macctl |= B43_MACCTL_PSM_JMP0;
2261 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2262 /* Zero out all microcode PSM registers and shared memory. */
2263 for (i = 0; i < 64; i++)
2264 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2265 for (i = 0; i < 4096; i += 2)
2266 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2267
e4d6b795 2268 /* Upload Microcode. */
61cb5dd6
MB		 2269 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2270 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2271 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2272 for (i = 0; i < len; i++) {
2273 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2274 udelay(10);
2275 }
2276
61cb5dd6 2277 if (dev->fw.pcm.data) {
e4d6b795 2278 /* Upload PCM data. */
61cb5dd6
MB		 2279 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2280 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2281 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2282 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2283 /* No need for autoinc bit in SHM_HW */
2284 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2285 for (i = 0; i < len; i++) {
2286 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2287 udelay(10);
2288 }
2289 }
2290
2291 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2292
2293 /* Start the microcode PSM */
2294 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2295 macctl &= ~B43_MACCTL_PSM_JMP0;
2296 macctl |= B43_MACCTL_PSM_RUN;
2297 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2298
2299 /* Wait for the microcode to load and respond */
2300 i = 0;
2301 while (1) {
2302 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2303 if (tmp == B43_IRQ_MAC_SUSPENDED)
2304 break;
2305 i++;
1f7d87b0 2306 if (i >= 20) {
e4d6b795 2307 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2308 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2309 err = -ENODEV;
1f7d87b0
MB		 2310 goto error;
2311 }
91d372c0 2312 msleep(50);
e4d6b795
MB		 2313 }
2314 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2315
2316 /* Get and check the revisions. */
2317 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2318 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2319 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2320 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2321
2322 if (fwrev <= 0x128) {
2323 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2324 "binary drivers older than version 4.x is unsupported. "
2325 "You must upgrade your firmware files.\n");
eb189d8b 2326 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2327 err = -EOPNOTSUPP;
1f7d87b0 2328 goto error;
e4d6b795 2329 }
e4d6b795
MB		 2330 dev->fw.rev = fwrev;
2331 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2332 dev->fw.opensource = (fwdate == 0xFFFF);
2333
403a3a13
MB		 2334 /* Default to use-all-queues. */
2335 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2336 dev->qos_enabled = !!modparam_qos;
2337 /* Default to firmware/hardware crypto acceleration. */
2338 dev->hwcrypto_enabled = 1;
2339
e48b0eeb 2340 if (dev->fw.opensource) {
403a3a13
MB		 2341 u16 fwcapa;
2342
e48b0eeb
MB		 2343 /* Patchlevel info is encoded in the "time" field. */
2344 dev->fw.patch = fwtime;
403a3a13
MB		 2345 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2346 dev->fw.rev, dev->fw.patch);
2347
2348 fwcapa = b43_fwcapa_read(dev);
2349 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2350 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2351 /* Disable hardware crypto and fall back to software crypto. */
2352 dev->hwcrypto_enabled = 0;
2353 }
2354 if (!(fwcapa & B43_FWCAPA_QOS)) {
2355 b43info(dev->wl, "QoS not supported by firmware\n");
2356 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2357 * ieee80211_unregister to make sure the networking core can
2358 * properly free possible resources. */
2359 dev->wl->hw->queues = 1;
2360 dev->qos_enabled = 0;
2361 }
e48b0eeb
MB		 2362 } else {
2363 b43info(dev->wl, "Loading firmware version %u.%u "
2364 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2365 fwrev, fwpatch,
2366 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2367 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2368 if (dev->fw.pcm_request_failed) {
2369 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2370 "Hardware accelerated cryptography is disabled.\n");
2371 b43_print_fw_helptext(dev->wl, 0);
2372 }
e48b0eeb 2373 }
e4d6b795 2374
eb189d8b 2375 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2376 /* We're over the deadline, but we keep support for old fw
2377 * until it turns out to be in major conflict with something new. */
eb189d8b 2378 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2379 "Support for old firmware will be removed soon "
2380 "(official deadline was July 2008).\n");
eb189d8b
MB		 2381 b43_print_fw_helptext(dev->wl, 0);
2382 }
2383
1f7d87b0
MB		 2384 return 0;
2385
2386error:
2387 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2388 macctl &= ~B43_MACCTL_PSM_RUN;
2389 macctl |= B43_MACCTL_PSM_JMP0;
2390 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2391
e4d6b795
MB		 2392 return err;
2393}
2394
2395static int b43_write_initvals(struct b43_wldev *dev,
2396 const struct b43_iv *ivals,
2397 size_t count,
2398 size_t array_size)
2399{
2400 const struct b43_iv *iv;
2401 u16 offset;
2402 size_t i;
2403 bool bit32;
2404
2405 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2406 iv = ivals;
2407 for (i = 0; i < count; i++) {
2408 if (array_size < sizeof(iv->offset_size))
2409 goto err_format;
2410 array_size -= sizeof(iv->offset_size);
2411 offset = be16_to_cpu(iv->offset_size);
2412 bit32 = !!(offset & B43_IV_32BIT);
2413 offset &= B43_IV_OFFSET_MASK;
2414 if (offset >= 0x1000)
2415 goto err_format;
2416 if (bit32) {
2417 u32 value;
2418
2419 if (array_size < sizeof(iv->data.d32))
2420 goto err_format;
2421 array_size -= sizeof(iv->data.d32);
2422
533dd1b0 2423 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2424 b43_write32(dev, offset, value);
2425
2426 iv = (const struct b43_iv *)((const uint8_t *)iv +
2427 sizeof(__be16) +
2428 sizeof(__be32));
2429 } else {
2430 u16 value;
2431
2432 if (array_size < sizeof(iv->data.d16))
2433 goto err_format;
2434 array_size -= sizeof(iv->data.d16);
2435
2436 value = be16_to_cpu(iv->data.d16);
2437 b43_write16(dev, offset, value);
2438
2439 iv = (const struct b43_iv *)((const uint8_t *)iv +
2440 sizeof(__be16) +
2441 sizeof(__be16));
2442 }
2443 }
2444 if (array_size)
2445 goto err_format;
2446
2447 return 0;
2448
2449err_format:
2450 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2451 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2452
2453 return -EPROTO;
2454}
2455
2456static int b43_upload_initvals(struct b43_wldev *dev)
2457{
2458 const size_t hdr_len = sizeof(struct b43_fw_header);
2459 const struct b43_fw_header *hdr;
2460 struct b43_firmware *fw = &dev->fw;
2461 const struct b43_iv *ivals;
2462 size_t count;
2463 int err;
2464
61cb5dd6
MB		 2465 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2466 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2467 count = be32_to_cpu(hdr->size);
2468 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2469 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2470 if (err)
2471 goto out;
61cb5dd6
MB		 2472 if (fw->initvals_band.data) {
2473 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2474 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2475 count = be32_to_cpu(hdr->size);
2476 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2477 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2478 if (err)
2479 goto out;
2480 }
2481out:
2482
2483 return err;
2484}
2485
2486/* Initialize the GPIOs
2487 * http://bcm-specs.sipsolutions.net/GPIO
2488 */
2489static int b43_gpio_init(struct b43_wldev *dev)
2490{
2491 struct ssb_bus *bus = dev->dev->bus;
2492 struct ssb_device *gpiodev, *pcidev = NULL;
2493 u32 mask, set;
2494
2495 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2496 & ~B43_MACCTL_GPOUTSMSK);
2497
e4d6b795
MB		 2498 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2499 | 0x000F);
2500
2501 mask = 0x0000001F;
2502 set = 0x0000000F;
2503 if (dev->dev->bus->chip_id == 0x4301) {
2504 mask |= 0x0060;
2505 set |= 0x0060;
2506 }
2507 if (0 /* FIXME: conditional unknown */ ) {
2508 b43_write16(dev, B43_MMIO_GPIO_MASK,
2509 b43_read16(dev, B43_MMIO_GPIO_MASK)
2510 | 0x0100);
2511 mask |= 0x0180;
2512 set |= 0x0180;
2513 }
95de2841 2514 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2515 b43_write16(dev, B43_MMIO_GPIO_MASK,
2516 b43_read16(dev, B43_MMIO_GPIO_MASK)
2517 | 0x0200);
2518 mask |= 0x0200;
2519 set |= 0x0200;
2520 }
2521 if (dev->dev->id.revision >= 2)
2522 mask |= 0x0010; /* FIXME: This is redundant. */
2523
2524#ifdef CONFIG_SSB_DRIVER_PCICORE
2525 pcidev = bus->pcicore.dev;
2526#endif
2527 gpiodev = bus->chipco.dev ? : pcidev;
2528 if (!gpiodev)
2529 return 0;
2530 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2531 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2532 & mask) | set);
2533
2534 return 0;
2535}
2536
2537/* Turn off all GPIO stuff. Call this on module unload, for example. */
2538static void b43_gpio_cleanup(struct b43_wldev *dev)
2539{
2540 struct ssb_bus *bus = dev->dev->bus;
2541 struct ssb_device *gpiodev, *pcidev = NULL;
2542
2543#ifdef CONFIG_SSB_DRIVER_PCICORE
2544 pcidev = bus->pcicore.dev;
2545#endif
2546 gpiodev = bus->chipco.dev ? : pcidev;
2547 if (!gpiodev)
2548 return;
2549 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2550}
2551
2552/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2553void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2554{
923fd703
MB		 2555 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2556 u16 fwstate;
2557
2558 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2559 B43_SHM_SH_UCODESTAT);
2560 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2561 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2562 b43err(dev->wl, "b43_mac_enable(): The firmware "
2563 "should be suspended, but current state is %u\n",
2564 fwstate);
2565 }
2566 }
2567
e4d6b795
MB		 2568 dev->mac_suspended--;
2569 B43_WARN_ON(dev->mac_suspended < 0);
2570 if (dev->mac_suspended == 0) {
2571 b43_write32(dev, B43_MMIO_MACCTL,
2572 b43_read32(dev, B43_MMIO_MACCTL)
2573 | B43_MACCTL_ENABLED);
2574 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2575 B43_IRQ_MAC_SUSPENDED);
2576 /* Commit writes */
2577 b43_read32(dev, B43_MMIO_MACCTL);
2578 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2579 b43_power_saving_ctl_bits(dev, 0);
2580 }
2581}
2582
2583/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2584void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2585{
2586 int i;
2587 u32 tmp;
2588
05b64b36 2589 might_sleep();
e4d6b795 2590 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2591
e4d6b795
MB		 2592 if (dev->mac_suspended == 0) {
2593 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2594 b43_write32(dev, B43_MMIO_MACCTL,
2595 b43_read32(dev, B43_MMIO_MACCTL)
2596 & ~B43_MACCTL_ENABLED);
2597 /* force pci to flush the write */
2598 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2599 for (i = 35; i; i--) {
2600 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2601 if (tmp & B43_IRQ_MAC_SUSPENDED)
2602 goto out;
2603 udelay(10);
2604 }
2605 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2606 for (i = 40; i; i--) {
e4d6b795
MB		 2607 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2608 if (tmp & B43_IRQ_MAC_SUSPENDED)
2609 goto out;
05b64b36 2610 msleep(1);
e4d6b795
MB		 2611 }
2612 b43err(dev->wl, "MAC suspend failed\n");
2613 }
05b64b36 2614out:
e4d6b795
MB		 2615 dev->mac_suspended++;
2616}
2617
2618static void b43_adjust_opmode(struct b43_wldev *dev)
2619{
2620 struct b43_wl *wl = dev->wl;
2621 u32 ctl;
2622 u16 cfp_pretbtt;
2623
2624 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2625 /* Reset status to STA infrastructure mode. */
2626 ctl &= ~B43_MACCTL_AP;
2627 ctl &= ~B43_MACCTL_KEEP_CTL;
2628 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2629 ctl &= ~B43_MACCTL_KEEP_BAD;
2630 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2631 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2632 ctl |= B43_MACCTL_INFRA;
2633
05c914fe
JB		 2634 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2635 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2636 ctl |= B43_MACCTL_AP;
05c914fe 2637 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2638 ctl &= ~B43_MACCTL_INFRA;
2639
2640 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2641 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2642 if (wl->filter_flags & FIF_FCSFAIL)
2643 ctl |= B43_MACCTL_KEEP_BAD;
2644 if (wl->filter_flags & FIF_PLCPFAIL)
2645 ctl |= B43_MACCTL_KEEP_BADPLCP;
2646 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2647 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2648 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2649 ctl |= B43_MACCTL_BEACPROMISC;
2650
e4d6b795
MB		 2651 /* Workaround: On old hardware the HW-MAC-address-filter
2652 * doesn't work properly, so always run promisc in filter
2653 * it in software. */
2654 if (dev->dev->id.revision <= 4)
2655 ctl |= B43_MACCTL_PROMISC;
2656
2657 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2658
2659 cfp_pretbtt = 2;
2660 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2661 if (dev->dev->bus->chip_id == 0x4306 &&
2662 dev->dev->bus->chip_rev == 3)
2663 cfp_pretbtt = 100;
2664 else
2665 cfp_pretbtt = 50;
2666 }
2667 b43_write16(dev, 0x612, cfp_pretbtt);
2668}
2669
2670static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2671{
2672 u16 offset;
2673
2674 if (is_ofdm) {
2675 offset = 0x480;
2676 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2677 } else {
2678 offset = 0x4C0;
2679 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2680 }
2681 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2682 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2683}
2684
2685static void b43_rate_memory_init(struct b43_wldev *dev)
2686{
2687 switch (dev->phy.type) {
2688 case B43_PHYTYPE_A:
2689 case B43_PHYTYPE_G:
53a6e234 2690 case B43_PHYTYPE_N:
9d86a2d5 2691 case B43_PHYTYPE_LP:
e4d6b795
MB		 2692 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2693 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2694 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2695 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2696 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2697 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2698 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2699 if (dev->phy.type == B43_PHYTYPE_A)
2700 break;
2701 /* fallthrough */
2702 case B43_PHYTYPE_B:
2703 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2704 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2705 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2706 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2707 break;
2708 default:
2709 B43_WARN_ON(1);
2710 }
2711}
2712
5042c507
MB		 2713/* Set the default values for the PHY TX Control Words. */
2714static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2715{
2716 u16 ctl = 0;
2717
2718 ctl |= B43_TXH_PHY_ENC_CCK;
2719 ctl |= B43_TXH_PHY_ANT01AUTO;
2720 ctl |= B43_TXH_PHY_TXPWR;
2721
2722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2723 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2724 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2725}
2726
e4d6b795
MB		 2727/* Set the TX-Antenna for management frames sent by firmware. */
2728static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2729{
5042c507 2730 u16 ant;
e4d6b795
MB		 2731 u16 tmp;
2732
5042c507 2733 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2734
e4d6b795
MB		 2735 /* For ACK/CTS */
2736 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2737 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2738 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2739 /* For Probe Resposes */
2740 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2741 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2742 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2743}
2744
2745/* This is the opposite of b43_chip_init() */
2746static void b43_chip_exit(struct b43_wldev *dev)
2747{
fb11137a 2748 b43_phy_exit(dev);
e4d6b795
MB		 2749 b43_gpio_cleanup(dev);
2750 /* firmware is released later */
2751}
2752
2753/* Initialize the chip
2754 * http://bcm-specs.sipsolutions.net/ChipInit
2755 */
2756static int b43_chip_init(struct b43_wldev *dev)
2757{
2758 struct b43_phy *phy = &dev->phy;
ef1a628d 2759 int err;
1f7d87b0 2760 u32 value32, macctl;
e4d6b795
MB		 2761 u16 value16;
2762
1f7d87b0
MB		 2763 /* Initialize the MAC control */
2764 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2765 if (dev->phy.gmode)
2766 macctl |= B43_MACCTL_GMODE;
2767 macctl |= B43_MACCTL_INFRA;
2768 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2769
2770 err = b43_request_firmware(dev);
2771 if (err)
2772 goto out;
2773 err = b43_upload_microcode(dev);
2774 if (err)
2775 goto out; /* firmware is released later */
2776
2777 err = b43_gpio_init(dev);
2778 if (err)
2779 goto out; /* firmware is released later */
21954c36 2780
e4d6b795
MB		 2781 err = b43_upload_initvals(dev);
2782 if (err)
1a8d1227 2783 goto err_gpio_clean;
e4d6b795 2784
0b7dcd96
MB		 2785 /* Turn the Analog on and initialize the PHY. */
2786 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2787 err = b43_phy_init(dev);
2788 if (err)
ef1a628d 2789 goto err_gpio_clean;
e4d6b795 2790
ef1a628d
MB		 2791 /* Disable Interference Mitigation. */
2792 if (phy->ops->interf_mitigation)
2793 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2794
ef1a628d
MB		 2795 /* Select the antennae */
2796 if (phy->ops->set_rx_antenna)
2797 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2798 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2799
2800 if (phy->type == B43_PHYTYPE_B) {
2801 value16 = b43_read16(dev, 0x005E);
2802 value16 |= 0x0004;
2803 b43_write16(dev, 0x005E, value16);
2804 }
2805 b43_write32(dev, 0x0100, 0x01000000);
2806 if (dev->dev->id.revision < 5)
2807 b43_write32(dev, 0x010C, 0x01000000);
2808
2809 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2810 & ~B43_MACCTL_INFRA);
2811 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2812 | B43_MACCTL_INFRA);
e4d6b795 2813
e4d6b795
MB		 2814 /* Probe Response Timeout value */
2815 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2816 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2817
2818 /* Initially set the wireless operation mode. */
2819 b43_adjust_opmode(dev);
2820
2821 if (dev->dev->id.revision < 3) {
2822 b43_write16(dev, 0x060E, 0x0000);
2823 b43_write16(dev, 0x0610, 0x8000);
2824 b43_write16(dev, 0x0604, 0x0000);
2825 b43_write16(dev, 0x0606, 0x0200);
2826 } else {
2827 b43_write32(dev, 0x0188, 0x80000000);
2828 b43_write32(dev, 0x018C, 0x02000000);
2829 }
2830 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2831 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2832 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2833 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2834 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2835 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2836 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2837
2838 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2839 value32 |= 0x00100000;
2840 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2841
2842 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2843 dev->dev->bus->chipco.fast_pwrup_delay);
2844
2845 err = 0;
2846 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2847out:
e4d6b795
MB		 2848 return err;
2849
1a8d1227 2850err_gpio_clean:
e4d6b795 2851 b43_gpio_cleanup(dev);
21954c36 2852 return err;
e4d6b795
MB		 2853}
2854
e4d6b795
MB		 2855static void b43_periodic_every60sec(struct b43_wldev *dev)
2856{
ef1a628d 2857 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2858
ef1a628d
MB		 2859 if (ops->pwork_60sec)
2860 ops->pwork_60sec(dev);
18c8adeb
MB		 2861
2862 /* Force check the TX power emission now. */
2863 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2864}
2865
2866static void b43_periodic_every30sec(struct b43_wldev *dev)
2867{
2868 /* Update device statistics. */
2869 b43_calculate_link_quality(dev);
2870}
2871
2872static void b43_periodic_every15sec(struct b43_wldev *dev)
2873{
2874 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2875 u16 wdr;
2876
2877 if (dev->fw.opensource) {
2878 /* Check if the firmware is still alive.
2879 * It will reset the watchdog counter to 0 in its idle loop. */
2880 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2881 if (unlikely(wdr)) {
2882 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2883 b43_controller_restart(dev, "Firmware watchdog");
2884 return;
2885 } else {
2886 b43_shm_write16(dev, B43_SHM_SCRATCH,
2887 B43_WATCHDOG_REG, 1);
2888 }
2889 }
e4d6b795 2890
ef1a628d
MB		 2891 if (phy->ops->pwork_15sec)
2892 phy->ops->pwork_15sec(dev);
2893
00e0b8cb
SB		 2894 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2895 wmb();
e4d6b795
MB		 2896}
2897
e4d6b795
MB		 2898static void do_periodic_work(struct b43_wldev *dev)
2899{
2900 unsigned int state;
2901
2902 state = dev->periodic_state;
42bb4cd5 2903 if (state % 4 == 0)
e4d6b795 2904 b43_periodic_every60sec(dev);
42bb4cd5 2905 if (state % 2 == 0)
e4d6b795 2906 b43_periodic_every30sec(dev);
42bb4cd5 2907 b43_periodic_every15sec(dev);
e4d6b795
MB		 2908}
2909
05b64b36
MB		 2910/* Periodic work locking policy:
2911 * The whole periodic work handler is protected by
2912 * wl->mutex. If another lock is needed somewhere in the
2913 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2914 */
e4d6b795
MB		 2915static void b43_periodic_work_handler(struct work_struct *work)
2916{
05b64b36
MB		 2917 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2918 periodic_work.work);
2919 struct b43_wl *wl = dev->wl;
2920 unsigned long delay;
e4d6b795 2921
05b64b36 2922 mutex_lock(&wl->mutex);
e4d6b795
MB		 2923
2924 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2925 goto out;
2926 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2927 goto out_requeue;
2928
05b64b36 2929 do_periodic_work(dev);
e4d6b795 2930
e4d6b795 2931 dev->periodic_state++;
42bb4cd5 2932out_requeue:
e4d6b795
MB		 2933 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2934 delay = msecs_to_jiffies(50);
2935 else
82cd682d 2936 delay = round_jiffies_relative(HZ * 15);
42935eca 2937 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 2938out:
05b64b36 2939 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2940}
2941
2942static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2943{
2944 struct delayed_work *work = &dev->periodic_work;
2945
2946 dev->periodic_state = 0;
2947 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 2948 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 2949}
2950
f3dd3fcc 2951/* Check if communication with the device works correctly. */
e4d6b795
MB		 2952static int b43_validate_chipaccess(struct b43_wldev *dev)
2953{
f62ae6cd 2954 u32 v, backup0, backup4;
e4d6b795 2955
f62ae6cd
MB		 2956 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2957 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 2958
2959 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2960 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2961 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2962 goto error;
f3dd3fcc
MB		 2963 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2964 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2965 goto error;
2966
f62ae6cd
MB		 2967 /* Check if unaligned 32bit SHM_SHARED access works properly.
2968 * However, don't bail out on failure, because it's noncritical. */
2969 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
2970 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
2971 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
2972 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
2973 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
2974 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
2975 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
2976 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
2977 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
2978 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
2979 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
2980 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
2981
2982 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
2983 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 2984
2985 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2986 /* The 32bit register shadows the two 16bit registers
2987 * with update sideeffects. Validate this. */
2988 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2989 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2990 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2991 goto error;
2992 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2993 goto error;
2994 }
2995 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2996
2997 v = b43_read32(dev, B43_MMIO_MACCTL);
2998 v |= B43_MACCTL_GMODE;
2999 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3000 goto error;
3001
3002 return 0;
f3dd3fcc 3003error:
e4d6b795
MB		 3004 b43err(dev->wl, "Failed to validate the chipaccess\n");
3005 return -ENODEV;
3006}
3007
3008static void b43_security_init(struct b43_wldev *dev)
3009{
e4d6b795
MB		 3010 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3011 /* KTP is a word address, but we address SHM bytewise.
3012 * So multiply by two.
3013 */
3014 dev->ktp *= 2;
66d2d089
MB		 3015 /* Number of RCMTA address slots */
3016 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3017 /* Clear the key memory. */
e4d6b795
MB		 3018 b43_clear_keys(dev);
3019}
3020
616de35d 3021#ifdef CONFIG_B43_HWRNG
99da185a 3022static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3023{
3024 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3025 struct b43_wldev *dev;
3026 int count = -ENODEV;
e4d6b795 3027
a78b3bb2
MB		 3028 mutex_lock(&wl->mutex);
3029 dev = wl->current_dev;
3030 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3031 *data = b43_read16(dev, B43_MMIO_RNG);
3032 count = sizeof(u16);
3033 }
3034 mutex_unlock(&wl->mutex);
e4d6b795 3035
a78b3bb2 3036 return count;
e4d6b795 3037}
616de35d 3038#endif /* CONFIG_B43_HWRNG */
e4d6b795 3039
b844eba2 3040static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3041{
616de35d 3042#ifdef CONFIG_B43_HWRNG
e4d6b795 3043 if (wl->rng_initialized)
b844eba2 3044 hwrng_unregister(&wl->rng);
616de35d 3045#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3046}
3047
3048static int b43_rng_init(struct b43_wl *wl)
3049{
616de35d 3050 int err = 0;
e4d6b795 3051
616de35d 3052#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3053 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3054 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3055 wl->rng.name = wl->rng_name;
3056 wl->rng.data_read = b43_rng_read;
3057 wl->rng.priv = (unsigned long)wl;
3058 wl->rng_initialized = 1;
3059 err = hwrng_register(&wl->rng);
3060 if (err) {
3061 wl->rng_initialized = 0;
3062 b43err(wl, "Failed to register the random "
3063 "number generator (%d)\n", err);
3064 }
616de35d 3065#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3066
3067 return err;
3068}
3069
f5d40eed 3070static void b43_tx_work(struct work_struct *work)
e4d6b795 3071{
f5d40eed
MB		 3072 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3073 struct b43_wldev *dev;
3074 struct sk_buff *skb;
3075 int err = 0;
e4d6b795 3076
f5d40eed
MB		 3077 mutex_lock(&wl->mutex);
3078 dev = wl->current_dev;
3079 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3080 mutex_unlock(&wl->mutex);
3081 return;
5100d5ac 3082 }
21a75d77 3083
f5d40eed
MB		 3084 while (skb_queue_len(&wl->tx_queue)) {
3085 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3086
21a75d77 3087 if (b43_using_pio_transfers(dev))
e039fa4a 3088 err = b43_pio_tx(dev, skb);
21a75d77 3089 else
e039fa4a 3090 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3091 if (unlikely(err))
3092 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3093 }
3094
f5d40eed
MB		 3095 mutex_unlock(&wl->mutex);
3096}
21a75d77 3097
f5d40eed
MB		 3098static int b43_op_tx(struct ieee80211_hw *hw,
3099 struct sk_buff *skb)
3100{
3101 struct b43_wl *wl = hw_to_b43_wl(hw);
3102
3103 if (unlikely(skb->len < 2 + 2 + 6)) {
3104 /* Too short, this can't be a valid frame. */
3105 dev_kfree_skb_any(skb);
3106 return NETDEV_TX_OK;
3107 }
3108 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3109
3110 skb_queue_tail(&wl->tx_queue, skb);
3111 ieee80211_queue_work(wl->hw, &wl->tx_work);
c9e8eae0 3112
e4d6b795
MB		 3113 return NETDEV_TX_OK;
3114}
3115
e6f5b934
MB		 3116static void b43_qos_params_upload(struct b43_wldev *dev,
3117 const struct ieee80211_tx_queue_params *p,
3118 u16 shm_offset)
3119{
3120 u16 params[B43_NR_QOSPARAMS];
0b57664c 3121 int bslots, tmp;
e6f5b934
MB		 3122 unsigned int i;
3123
b0544eb6
MB		 3124 if (!dev->qos_enabled)
3125 return;
3126
0b57664c 3127 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3128
3129 memset(&params, 0, sizeof(params));
3130
3131 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3132 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3133 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3134 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3135 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3136 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3137 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3138
3139 for (i = 0; i < ARRAY_SIZE(params); i++) {
3140 if (i == B43_QOSPARAM_STATUS) {
3141 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3142 shm_offset + (i * 2));
3143 /* Mark the parameters as updated. */
3144 tmp |= 0x100;
3145 b43_shm_write16(dev, B43_SHM_SHARED,
3146 shm_offset + (i * 2),
3147 tmp);
3148 } else {
3149 b43_shm_write16(dev, B43_SHM_SHARED,
3150 shm_offset + (i * 2),
3151 params[i]);
3152 }
3153 }
3154}
3155
c40c1129
MB		 3156/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3157static const u16 b43_qos_shm_offsets[] = {
3158 /* [mac80211-queue-nr] = SHM_OFFSET, */
3159 [0] = B43_QOS_VOICE,
3160 [1] = B43_QOS_VIDEO,
3161 [2] = B43_QOS_BESTEFFORT,
3162 [3] = B43_QOS_BACKGROUND,
3163};
3164
5a5f3b40
MB		 3165/* Update all QOS parameters in hardware. */
3166static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3167{
3168 struct b43_wl *wl = dev->wl;
3169 struct b43_qos_params *params;
e6f5b934
MB		 3170 unsigned int i;
3171
b0544eb6
MB		 3172 if (!dev->qos_enabled)
3173 return;
3174
c40c1129
MB		 3175 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3176 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3177
3178 b43_mac_suspend(dev);
e6f5b934
MB		 3179 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3180 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3181 b43_qos_params_upload(dev, &(params->p),
3182 b43_qos_shm_offsets[i]);
e6f5b934 3183 }
e6f5b934
MB		 3184 b43_mac_enable(dev);
3185}
3186
3187static void b43_qos_clear(struct b43_wl *wl)
3188{
3189 struct b43_qos_params *params;
3190 unsigned int i;
3191
c40c1129
MB		 3192 /* Initialize QoS parameters to sane defaults. */
3193
3194 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3195 ARRAY_SIZE(wl->qos_params));
3196
e6f5b934
MB		 3197 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3198 params = &(wl->qos_params[i]);
3199
c40c1129
MB		 3200 switch (b43_qos_shm_offsets[i]) {
3201 case B43_QOS_VOICE:
3202 params->p.txop = 0;
3203 params->p.aifs = 2;
3204 params->p.cw_min = 0x0001;
3205 params->p.cw_max = 0x0001;
3206 break;
3207 case B43_QOS_VIDEO:
3208 params->p.txop = 0;
3209 params->p.aifs = 2;
3210 params->p.cw_min = 0x0001;
3211 params->p.cw_max = 0x0001;
3212 break;
3213 case B43_QOS_BESTEFFORT:
3214 params->p.txop = 0;
3215 params->p.aifs = 3;
3216 params->p.cw_min = 0x0001;
3217 params->p.cw_max = 0x03FF;
3218 break;
3219 case B43_QOS_BACKGROUND:
3220 params->p.txop = 0;
3221 params->p.aifs = 7;
3222 params->p.cw_min = 0x0001;
3223 params->p.cw_max = 0x03FF;
3224 break;
3225 default:
3226 B43_WARN_ON(1);
3227 }
e6f5b934
MB		 3228 }
3229}
3230
3231/* Initialize the core's QOS capabilities */
3232static void b43_qos_init(struct b43_wldev *dev)
3233{
b0544eb6
MB		 3234 if (!dev->qos_enabled) {
3235 /* Disable QOS support. */
3236 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3237 b43_write16(dev, B43_MMIO_IFSCTL,
3238 b43_read16(dev, B43_MMIO_IFSCTL)
3239 & ~B43_MMIO_IFSCTL_USE_EDCF);
3240 b43dbg(dev->wl, "QoS disabled\n");
3241 return;
3242 }
3243
e6f5b934 3244 /* Upload the current QOS parameters. */
5a5f3b40 3245 b43_qos_upload_all(dev);
e6f5b934
MB		 3246
3247 /* Enable QOS support. */
3248 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3249 b43_write16(dev, B43_MMIO_IFSCTL,
3250 b43_read16(dev, B43_MMIO_IFSCTL)
3251 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3252 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3253}
3254
e100bb64 3255static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3256 const struct ieee80211_tx_queue_params *params)
e4d6b795 3257{
e6f5b934 3258 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3259 struct b43_wldev *dev;
e6f5b934 3260 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3261 int err = -ENODEV;
e6f5b934
MB		 3262
3263 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3264 /* Queue not available or don't support setting
3265 * params on this queue. Return success to not
3266 * confuse mac80211. */
3267 return 0;
3268 }
5a5f3b40
MB		 3269 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3270 ARRAY_SIZE(wl->qos_params));
e6f5b934 3271
5a5f3b40
MB		 3272 mutex_lock(&wl->mutex);
3273 dev = wl->current_dev;
3274 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3275 goto out_unlock;
e6f5b934 3276
5a5f3b40
MB		 3277 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3278 b43_mac_suspend(dev);
3279 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3280 b43_qos_shm_offsets[queue]);
3281 b43_mac_enable(dev);
3282 err = 0;
e6f5b934 3283
5a5f3b40
MB		 3284out_unlock:
3285 mutex_unlock(&wl->mutex);
3286
3287 return err;
e4d6b795
MB		 3288}
3289
40faacc4
MB		 3290static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3291 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3292{
3293 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3294 struct b43_wldev *dev;
e4d6b795
MB		 3295 int err = -ENODEV;
3296
36dbd954
MB		 3297 mutex_lock(&wl->mutex);
3298 dev = wl->current_dev;
3299 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
5100d5ac
MB		 3300 if (b43_using_pio_transfers(dev))
3301 b43_pio_get_tx_stats(dev, stats);
3302 else
3303 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3304 err = 0;
3305 }
36dbd954
MB		 3306 mutex_unlock(&wl->mutex);
3307
e4d6b795
MB		 3308 return err;
3309}
3310
40faacc4
MB		 3311static int b43_op_get_stats(struct ieee80211_hw *hw,
3312 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3313{
3314 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3315
36dbd954 3316 mutex_lock(&wl->mutex);
e4d6b795 3317 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3318 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3319
3320 return 0;
3321}
3322
08e87a83
AF		 3323static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3324{
3325 struct b43_wl *wl = hw_to_b43_wl(hw);
3326 struct b43_wldev *dev;
3327 u64 tsf;
3328
3329 mutex_lock(&wl->mutex);
08e87a83
AF		 3330 dev = wl->current_dev;
3331
3332 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3333 b43_tsf_read(dev, &tsf);
3334 else
3335 tsf = 0;
3336
08e87a83
AF		 3337 mutex_unlock(&wl->mutex);
3338
3339 return tsf;
3340}
3341
3342static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3343{
3344 struct b43_wl *wl = hw_to_b43_wl(hw);
3345 struct b43_wldev *dev;
3346
3347 mutex_lock(&wl->mutex);
08e87a83
AF		 3348 dev = wl->current_dev;
3349
3350 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3351 b43_tsf_write(dev, tsf);
3352
08e87a83
AF		 3353 mutex_unlock(&wl->mutex);
3354}
3355
e4d6b795
MB		 3356static void b43_put_phy_into_reset(struct b43_wldev *dev)
3357{
3358 struct ssb_device *sdev = dev->dev;
3359 u32 tmslow;
3360
3361 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3362 tmslow &= ~B43_TMSLOW_GMODE;
3363 tmslow |= B43_TMSLOW_PHYRESET;
3364 tmslow |= SSB_TMSLOW_FGC;
3365 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3366 msleep(1);
3367
3368 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3369 tmslow &= ~SSB_TMSLOW_FGC;
3370 tmslow |= B43_TMSLOW_PHYRESET;
3371 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3372 msleep(1);
3373}
3374
99da185a 3375static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3376{
3377 switch (band) {
3378 case IEEE80211_BAND_5GHZ:
3379 return "5";
3380 case IEEE80211_BAND_2GHZ:
3381 return "2.4";
3382 default:
3383 break;
3384 }
3385 B43_WARN_ON(1);
3386 return "";
3387}
3388
e4d6b795 3389/* Expects wl->mutex locked */
bb1eeff1 3390static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3391{
bb1eeff1 3392 struct b43_wldev *up_dev = NULL;
e4d6b795 3393 struct b43_wldev *down_dev;
bb1eeff1 3394 struct b43_wldev *d;
e4d6b795 3395 int err;
922d8a0b 3396 bool uninitialized_var(gmode);
e4d6b795
MB		 3397 int prev_status;
3398
bb1eeff1
MB		 3399 /* Find a device and PHY which supports the band. */
3400 list_for_each_entry(d, &wl->devlist, list) {
3401 switch (chan->band) {
3402 case IEEE80211_BAND_5GHZ:
3403 if (d->phy.supports_5ghz) {
3404 up_dev = d;
3405 gmode = 0;
3406 }
3407 break;
3408 case IEEE80211_BAND_2GHZ:
3409 if (d->phy.supports_2ghz) {
3410 up_dev = d;
3411 gmode = 1;
3412 }
3413 break;
3414 default:
3415 B43_WARN_ON(1);
3416 return -EINVAL;
3417 }
3418 if (up_dev)
3419 break;
3420 }
3421 if (!up_dev) {
3422 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3423 band_to_string(chan->band));
3424 return -ENODEV;
e4d6b795
MB		 3425 }
3426 if ((up_dev == wl->current_dev) &&
3427 (!!wl->current_dev->phy.gmode == !!gmode)) {
3428 /* This device is already running. */
3429 return 0;
3430 }
bb1eeff1
MB		 3431 b43dbg(wl, "Switching to %s-GHz band\n",
3432 band_to_string(chan->band));
e4d6b795
MB		 3433 down_dev = wl->current_dev;
3434
3435 prev_status = b43_status(down_dev);
3436 /* Shutdown the currently running core. */
3437 if (prev_status >= B43_STAT_STARTED)
36dbd954 3438 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3439 if (prev_status >= B43_STAT_INITIALIZED)
3440 b43_wireless_core_exit(down_dev);
3441
3442 if (down_dev != up_dev) {
3443 /* We switch to a different core, so we put PHY into
3444 * RESET on the old core. */
3445 b43_put_phy_into_reset(down_dev);
3446 }
3447
3448 /* Now start the new core. */
3449 up_dev->phy.gmode = gmode;
3450 if (prev_status >= B43_STAT_INITIALIZED) {
3451 err = b43_wireless_core_init(up_dev);
3452 if (err) {
3453 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3454 "selected %s-GHz band\n",
3455 band_to_string(chan->band));
e4d6b795
MB		 3456 goto init_failure;
3457 }
3458 }
3459 if (prev_status >= B43_STAT_STARTED) {
3460 err = b43_wireless_core_start(up_dev);
3461 if (err) {
3462 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3463 "selected %s-GHz band\n",
3464 band_to_string(chan->band));
e4d6b795
MB		 3465 b43_wireless_core_exit(up_dev);
3466 goto init_failure;
3467 }
3468 }
3469 B43_WARN_ON(b43_status(up_dev) != prev_status);
3470
3471 wl->current_dev = up_dev;
3472
3473 return 0;
bb1eeff1 3474init_failure:
e4d6b795
MB		 3475 /* Whoops, failed to init the new core. No core is operating now. */
3476 wl->current_dev = NULL;
3477 return err;
3478}
3479
9124b077
JB		 3480/* Write the short and long frame retry limit values. */
3481static void b43_set_retry_limits(struct b43_wldev *dev,
3482 unsigned int short_retry,
3483 unsigned int long_retry)
3484{
3485 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3486 * the chip-internal counter. */
3487 short_retry = min(short_retry, (unsigned int)0xF);
3488 long_retry = min(long_retry, (unsigned int)0xF);
3489
3490 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3491 short_retry);
3492 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3493 long_retry);
3494}
3495
e8975581 3496static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3497{
3498 struct b43_wl *wl = hw_to_b43_wl(hw);
3499 struct b43_wldev *dev;
3500 struct b43_phy *phy;
e8975581 3501 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3502 int antenna;
e4d6b795 3503 int err = 0;
e4d6b795 3504
e4d6b795
MB		 3505 mutex_lock(&wl->mutex);
3506
bb1eeff1
MB		 3507 /* Switch the band (if necessary). This might change the active core. */
3508 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3509 if (err)
3510 goto out_unlock_mutex;
3511 dev = wl->current_dev;
3512 phy = &dev->phy;
3513
d10d0e57
MB		 3514 b43_mac_suspend(dev);
3515
9124b077
JB		 3516 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3517 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3518 conf->long_frame_max_tx_count);
3519 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3520 if (!changed)
d10d0e57 3521 goto out_mac_enable;
e4d6b795
MB		 3522
3523 /* Switch to the requested channel.
3524 * The firmware takes care of races with the TX handler. */
8318d78a 3525 if (conf->channel->hw_value != phy->channel)
ef1a628d 3526 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3527
d42ce84a
JB		 3528 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3529
e4d6b795
MB		 3530 /* Adjust the desired TX power level. */
3531 if (conf->power_level != 0) {
18c8adeb
MB		 3532 if (conf->power_level != phy->desired_txpower) {
3533 phy->desired_txpower = conf->power_level;
3534 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3535 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3536 }
3537 }
3538
3539 /* Antennas for RX and management frame TX. */
0f4ac38b 3540 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3541 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3542 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3543 if (phy->ops->set_rx_antenna)
3544 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3545
fd4973c5
LF		 3546 if (wl->radio_enabled != phy->radio_on) {
3547 if (wl->radio_enabled) {
19d337df 3548 b43_software_rfkill(dev, false);
fda9abcf
MB		 3549 b43info(dev->wl, "Radio turned on by software\n");
3550 if (!dev->radio_hw_enable) {
3551 b43info(dev->wl, "The hardware RF-kill button "
3552 "still turns the radio physically off. "
3553 "Press the button to turn it on.\n");
3554 }
3555 } else {
19d337df 3556 b43_software_rfkill(dev, true);
fda9abcf
MB		 3557 b43info(dev->wl, "Radio turned off by software\n");
3558 }
3559 }
3560
d10d0e57
MB		 3561out_mac_enable:
3562 b43_mac_enable(dev);
3563out_unlock_mutex:
e4d6b795
MB		 3564 mutex_unlock(&wl->mutex);
3565
3566 return err;
3567}
3568
881d948c 3569static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3570{
3571 struct ieee80211_supported_band *sband =
3572 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3573 struct ieee80211_rate *rate;
3574 int i;
3575 u16 basic, direct, offset, basic_offset, rateptr;
3576
3577 for (i = 0; i < sband->n_bitrates; i++) {
3578 rate = &sband->bitrates[i];
3579
3580 if (b43_is_cck_rate(rate->hw_value)) {
3581 direct = B43_SHM_SH_CCKDIRECT;
3582 basic = B43_SHM_SH_CCKBASIC;
3583 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3584 offset &= 0xF;
3585 } else {
3586 direct = B43_SHM_SH_OFDMDIRECT;
3587 basic = B43_SHM_SH_OFDMBASIC;
3588 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3589 offset &= 0xF;
3590 }
3591
3592 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3593
3594 if (b43_is_cck_rate(rate->hw_value)) {
3595 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3596 basic_offset &= 0xF;
3597 } else {
3598 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3599 basic_offset &= 0xF;
3600 }
3601
3602 /*
3603 * Get the pointer that we need to point to
3604 * from the direct map
3605 */
3606 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3607 direct + 2 * basic_offset);
3608 /* and write it to the basic map */
3609 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3610 rateptr);
3611 }
3612}
3613
3614static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3615 struct ieee80211_vif *vif,
3616 struct ieee80211_bss_conf *conf,
3617 u32 changed)
3618{
3619 struct b43_wl *wl = hw_to_b43_wl(hw);
3620 struct b43_wldev *dev;
c7ab5ef9
JB		 3621
3622 mutex_lock(&wl->mutex);
3623
3624 dev = wl->current_dev;
d10d0e57 3625 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3626 goto out_unlock_mutex;
2d0ddec5
JB		 3627
3628 B43_WARN_ON(wl->vif != vif);
3629
3630 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3631 if (conf->bssid)
3632 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3633 else
3634 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3635 }
2d0ddec5 3636
3f0d843b
JB		 3637 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3638 if (changed & BSS_CHANGED_BEACON &&
3639 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3640 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3641 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3642 b43_update_templates(wl);
3643
3644 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3645 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3646 }
3647
c7ab5ef9
JB		 3648 b43_mac_suspend(dev);
3649
57c4d7b4
JB		 3650 /* Update templates for AP/mesh mode. */
3651 if (changed & BSS_CHANGED_BEACON_INT &&
3652 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3653 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3654 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3655 b43_set_beacon_int(dev, conf->beacon_int);
3656
c7ab5ef9
JB		 3657 if (changed & BSS_CHANGED_BASIC_RATES)
3658 b43_update_basic_rates(dev, conf->basic_rates);
3659
3660 if (changed & BSS_CHANGED_ERP_SLOT) {
3661 if (conf->use_short_slot)
3662 b43_short_slot_timing_enable(dev);
3663 else
3664 b43_short_slot_timing_disable(dev);
3665 }
3666
3667 b43_mac_enable(dev);
d10d0e57 3668out_unlock_mutex:
c7ab5ef9 3669 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3670}
3671
40faacc4 3672static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3673 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3674 struct ieee80211_key_conf *key)
e4d6b795
MB		 3675{
3676 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3677 struct b43_wldev *dev;
e4d6b795
MB		 3678 u8 algorithm;
3679 u8 index;
c6dfc9a8 3680 int err;
060210f9 3681 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3682
3683 if (modparam_nohwcrypt)
3684 return -ENOSPC; /* User disabled HW-crypto */
3685
c6dfc9a8 3686 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3687
3688 dev = wl->current_dev;
3689 err = -ENODEV;
3690 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3691 goto out_unlock;
3692
403a3a13 3693 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3694 /* We don't have firmware for the crypto engine.
3695 * Must use software-crypto. */
3696 err = -EOPNOTSUPP;
3697 goto out_unlock;
3698 }
3699
c6dfc9a8 3700 err = -EINVAL;
e4d6b795 3701 switch (key->alg) {
e4d6b795 3702 case ALG_WEP:
e31a16d6 3703 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3704 algorithm = B43_SEC_ALGO_WEP40;
3705 else
3706 algorithm = B43_SEC_ALGO_WEP104;
3707 break;
3708 case ALG_TKIP:
3709 algorithm = B43_SEC_ALGO_TKIP;
3710 break;
3711 case ALG_CCMP:
3712 algorithm = B43_SEC_ALGO_AES;
3713 break;
3714 default:
3715 B43_WARN_ON(1);
c6dfc9a8 3716 goto out_unlock;
e4d6b795 3717 }
e4d6b795
MB		 3718 index = (u8) (key->keyidx);
3719 if (index > 3)
e4d6b795 3720 goto out_unlock;
e4d6b795
MB		 3721
3722 switch (cmd) {
3723 case SET_KEY:
035d0243 3724 if (algorithm == B43_SEC_ALGO_TKIP &&
3725 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3726 !modparam_hwtkip)) {
3727 /* We support only pairwise key */
e4d6b795
MB		 3728 err = -EOPNOTSUPP;
3729 goto out_unlock;
3730 }
3731
e808e586 3732 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3733 if (WARN_ON(!sta)) {
3734 err = -EOPNOTSUPP;
3735 goto out_unlock;
3736 }
e808e586 3737 /* Pairwise key with an assigned MAC address. */
e4d6b795 3738 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3739 key->key, key->keylen,
3740 sta->addr, key);
e808e586
MB		 3741 } else {
3742 /* Group key */
3743 err = b43_key_write(dev, index, algorithm,
3744 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3745 }
3746 if (err)
3747 goto out_unlock;
3748
3749 if (algorithm == B43_SEC_ALGO_WEP40 ||
3750 algorithm == B43_SEC_ALGO_WEP104) {
3751 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3752 } else {
3753 b43_hf_write(dev,
3754 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3755 }
3756 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3757 if (algorithm == B43_SEC_ALGO_TKIP)
3758 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3759 break;
3760 case DISABLE_KEY: {
3761 err = b43_key_clear(dev, key->hw_key_idx);
3762 if (err)
3763 goto out_unlock;
3764 break;
3765 }
3766 default:
3767 B43_WARN_ON(1);
3768 }
9cf7f247 3769
e4d6b795 3770out_unlock:
e4d6b795
MB		 3771 if (!err) {
3772 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3773 "mac: %pM\n",
e4d6b795 3774 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3775 sta ? sta->addr : bcast_addr);
9cf7f247 3776 b43_dump_keymemory(dev);
e4d6b795 3777 }
9cf7f247
MB		 3778 mutex_unlock(&wl->mutex);
3779
e4d6b795
MB		 3780 return err;
3781}
3782
40faacc4
MB		 3783static void b43_op_configure_filter(struct ieee80211_hw *hw,
3784 unsigned int changed, unsigned int *fflags,
3ac64bee 3785 u64 multicast)
e4d6b795
MB		 3786{
3787 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3788 struct b43_wldev *dev;
e4d6b795 3789
36dbd954
MB		 3790 mutex_lock(&wl->mutex);
3791 dev = wl->current_dev;
4150c572
JB		 3792 if (!dev) {
3793 *fflags = 0;
36dbd954 3794 goto out_unlock;
e4d6b795 3795 }
4150c572 3796
4150c572
JB		 3797 *fflags &= FIF_PROMISC_IN_BSS |
3798 FIF_ALLMULTI |
3799 FIF_FCSFAIL |
3800 FIF_PLCPFAIL |
3801 FIF_CONTROL |
3802 FIF_OTHER_BSS |
3803 FIF_BCN_PRBRESP_PROMISC;
3804
3805 changed &= FIF_PROMISC_IN_BSS |
3806 FIF_ALLMULTI |
3807 FIF_FCSFAIL |
3808 FIF_PLCPFAIL |
3809 FIF_CONTROL |
3810 FIF_OTHER_BSS |
3811 FIF_BCN_PRBRESP_PROMISC;
3812
3813 wl->filter_flags = *fflags;
3814
3815 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3816 b43_adjust_opmode(dev);
36dbd954
MB		 3817
3818out_unlock:
3819 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3820}
3821
36dbd954
MB		 3822/* Locking: wl->mutex
3823 * Returns the current dev. This might be different from the passed in dev,
3824 * because the core might be gone away while we unlocked the mutex. */
3825static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 3826{
3827 struct b43_wl *wl = dev->wl;
36dbd954 3828 struct b43_wldev *orig_dev;
e4d6b795 3829
36dbd954
MB		 3830redo:
3831 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3832 return dev;
a19d12d7 3833
f5d40eed 3834 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 3835 mutex_unlock(&wl->mutex);
3836 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 3837 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 3838 mutex_lock(&wl->mutex);
3839 dev = wl->current_dev;
3840 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3841 /* Whoops, aliens ate up the device while we were unlocked. */
3842 return dev;
3843 }
a19d12d7 3844
36dbd954 3845 /* Disable interrupts on the device. */
e4d6b795 3846 b43_set_status(dev, B43_STAT_INITIALIZED);
3dbba8e2 3847 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
36dbd954
MB		 3848 /* wl->mutex is locked. That is enough. */
3849 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3850 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3851 } else {
3852 spin_lock_irq(&wl->hardirq_lock);
3853 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3854 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3855 spin_unlock_irq(&wl->hardirq_lock);
3856 }
176e9f6a 3857 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 3858 orig_dev = dev;
e4d6b795 3859 mutex_unlock(&wl->mutex);
176e9f6a
MB		 3860 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3861 b43_sdio_free_irq(dev);
3862 } else {
3863 synchronize_irq(dev->dev->irq);
3864 free_irq(dev->dev->irq, dev);
3865 }
e4d6b795 3866 mutex_lock(&wl->mutex);
36dbd954
MB		 3867 dev = wl->current_dev;
3868 if (!dev)
3869 return dev;
3870 if (dev != orig_dev) {
3871 if (b43_status(dev) >= B43_STAT_STARTED)
3872 goto redo;
3873 return dev;
3874 }
3875 B43_WARN_ON(b43_read32(dev, B43_MMIO_GEN_IRQ_MASK));
e4d6b795 3876
f5d40eed
MB		 3877 /* Drain the TX queue */
3878 while (skb_queue_len(&wl->tx_queue))
3879 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3880
e4d6b795 3881 b43_mac_suspend(dev);
a78b3bb2 3882 b43_leds_exit(dev);
e4d6b795 3883 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 3884
3885 return dev;
e4d6b795
MB		 3886}
3887
3888/* Locking: wl->mutex */
3889static int b43_wireless_core_start(struct b43_wldev *dev)
3890{
3891 int err;
3892
3893 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3894
3895 drain_txstatus_queue(dev);
3dbba8e2
AH		 3896 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3897 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3898 if (err) {
3899 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3900 goto out;
3901 }
3902 } else {
3903 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3904 b43_interrupt_thread_handler,
3905 IRQF_SHARED, KBUILD_MODNAME, dev);
3906 if (err) {
3907 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3908 goto out;
3909 }
e4d6b795
MB		 3910 }
3911
3912 /* We are ready to run. */
3913 b43_set_status(dev, B43_STAT_STARTED);
3914
3915 /* Start data flow (TX/RX). */
3916 b43_mac_enable(dev);
13790728 3917 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3918
3919 /* Start maintainance work */
3920 b43_periodic_tasks_setup(dev);
3921
a78b3bb2
MB		 3922 b43_leds_init(dev);
3923
e4d6b795 3924 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 3925out:
e4d6b795
MB		 3926 return err;
3927}
3928
3929/* Get PHY and RADIO versioning numbers */
3930static int b43_phy_versioning(struct b43_wldev *dev)
3931{
3932 struct b43_phy *phy = &dev->phy;
3933 u32 tmp;
3934 u8 analog_type;
3935 u8 phy_type;
3936 u8 phy_rev;
3937 u16 radio_manuf;
3938 u16 radio_ver;
3939 u16 radio_rev;
3940 int unsupported = 0;
3941
3942 /* Get PHY versioning */
3943 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3944 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3945 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3946 phy_rev = (tmp & B43_PHYVER_VERSION);
3947 switch (phy_type) {
3948 case B43_PHYTYPE_A:
3949 if (phy_rev >= 4)
3950 unsupported = 1;
3951 break;
3952 case B43_PHYTYPE_B:
3953 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3954 && phy_rev != 7)
3955 unsupported = 1;
3956 break;
3957 case B43_PHYTYPE_G:
013978b6 3958 if (phy_rev > 9)
e4d6b795
MB		 3959 unsupported = 1;
3960 break;
d5c71e46
MB		 3961#ifdef CONFIG_B43_NPHY
3962 case B43_PHYTYPE_N:
bb519bee 3963 if (phy_rev > 4)
d5c71e46
MB		 3964 unsupported = 1;
3965 break;
6b1c7c67
MB		 3966#endif
3967#ifdef CONFIG_B43_PHY_LP
3968 case B43_PHYTYPE_LP:
9d86a2d5 3969 if (phy_rev > 2)
6b1c7c67
MB		 3970 unsupported = 1;
3971 break;
d5c71e46 3972#endif
e4d6b795
MB		 3973 default:
3974 unsupported = 1;
3975 };
3976 if (unsupported) {
3977 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3978 "(Analog %u, Type %u, Revision %u)\n",
3979 analog_type, phy_type, phy_rev);
3980 return -EOPNOTSUPP;
3981 }
3982 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3983 analog_type, phy_type, phy_rev);
3984
3985 /* Get RADIO versioning */
3986 if (dev->dev->bus->chip_id == 0x4317) {
3987 if (dev->dev->bus->chip_rev == 0)
3988 tmp = 0x3205017F;
3989 else if (dev->dev->bus->chip_rev == 1)
3990 tmp = 0x4205017F;
3991 else
3992 tmp = 0x5205017F;
3993 } else {
3994 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3995 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3996 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3997 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3998 }
3999 radio_manuf = (tmp & 0x00000FFF);
4000 radio_ver = (tmp & 0x0FFFF000) >> 12;
4001 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 4002 if (radio_manuf != 0x17F /* Broadcom */)
4003 unsupported = 1;
e4d6b795
MB		 4004 switch (phy_type) {
4005 case B43_PHYTYPE_A:
4006 if (radio_ver != 0x2060)
4007 unsupported = 1;
4008 if (radio_rev != 1)
4009 unsupported = 1;
4010 if (radio_manuf != 0x17F)
4011 unsupported = 1;
4012 break;
4013 case B43_PHYTYPE_B:
4014 if ((radio_ver & 0xFFF0) != 0x2050)
4015 unsupported = 1;
4016 break;
4017 case B43_PHYTYPE_G:
4018 if (radio_ver != 0x2050)
4019 unsupported = 1;
4020 break;
96c755a3 4021 case B43_PHYTYPE_N:
bb519bee 4022 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4023 unsupported = 1;
4024 break;
6b1c7c67 4025 case B43_PHYTYPE_LP:
9d86a2d5 4026 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4027 unsupported = 1;
4028 break;
e4d6b795
MB		 4029 default:
4030 B43_WARN_ON(1);
4031 }
4032 if (unsupported) {
4033 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4034 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4035 radio_manuf, radio_ver, radio_rev);
4036 return -EOPNOTSUPP;
4037 }
4038 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4039 radio_manuf, radio_ver, radio_rev);
4040
4041 phy->radio_manuf = radio_manuf;
4042 phy->radio_ver = radio_ver;
4043 phy->radio_rev = radio_rev;
4044
4045 phy->analog = analog_type;
4046 phy->type = phy_type;
4047 phy->rev = phy_rev;
4048
4049 return 0;
4050}
4051
4052static void setup_struct_phy_for_init(struct b43_wldev *dev,
4053 struct b43_phy *phy)
4054{
e4d6b795 4055 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4056 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4057 /* PHY TX errors counter. */
4058 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4059
4060#if B43_DEBUG
4061 phy->phy_locked = 0;
4062 phy->radio_locked = 0;
4063#endif
e4d6b795
MB		 4064}
4065
4066static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4067{
aa6c7ae2
MB		 4068 dev->dfq_valid = 0;
4069
6a724d68
MB		 4070 /* Assume the radio is enabled. If it's not enabled, the state will
4071 * immediately get fixed on the first periodic work run. */
4072 dev->radio_hw_enable = 1;
e4d6b795
MB		 4073
4074 /* Stats */
4075 memset(&dev->stats, 0, sizeof(dev->stats));
4076
4077 setup_struct_phy_for_init(dev, &dev->phy);
4078
4079 /* IRQ related flags */
4080 dev->irq_reason = 0;
4081 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4082 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4083 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4084 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4085
4086 dev->mac_suspended = 1;
4087
4088 /* Noise calculation context */
4089 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4090}
4091
4092static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4093{
4094 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4095 u64 hf;
e4d6b795 4096
1855ba78
MB		 4097 if (!modparam_btcoex)
4098 return;
95de2841 4099 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4100 return;
4101 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4102 return;
4103
4104 hf = b43_hf_read(dev);
95de2841 4105 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4106 hf |= B43_HF_BTCOEXALT;
4107 else
4108 hf |= B43_HF_BTCOEX;
4109 b43_hf_write(dev, hf);
e4d6b795
MB		 4110}
4111
4112static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4113{
4114 if (!modparam_btcoex)
4115 return;
4116 //TODO
e4d6b795
MB		 4117}
4118
4119static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4120{
4121#ifdef CONFIG_SSB_DRIVER_PCICORE
4122 struct ssb_bus *bus = dev->dev->bus;
4123 u32 tmp;
4124
4125 if (bus->pcicore.dev &&
4126 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4127 bus->pcicore.dev->id.revision <= 5) {
4128 /* IMCFGLO timeouts workaround. */
4129 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
e4d6b795
MB		 4130 switch (bus->bustype) {
4131 case SSB_BUSTYPE_PCI:
4132 case SSB_BUSTYPE_PCMCIA:
98a1e2a9
MB		 4133 tmp &= ~SSB_IMCFGLO_REQTO;
4134 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4135 tmp |= 0x32;
4136 break;
4137 case SSB_BUSTYPE_SSB:
98a1e2a9
MB		 4138 tmp &= ~SSB_IMCFGLO_REQTO;
4139 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4140 tmp |= 0x53;
4141 break;
98a1e2a9
MB		 4142 default:
4143 break;
e4d6b795
MB		 4144 }
4145 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4146 }
4147#endif /* CONFIG_SSB_DRIVER_PCICORE */
4148}
4149
d59f720d
MB		 4150static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4151{
4152 u16 pu_delay;
4153
4154 /* The time value is in microseconds. */
4155 if (dev->phy.type == B43_PHYTYPE_A)
4156 pu_delay = 3700;
4157 else
4158 pu_delay = 1050;
05c914fe 4159 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4160 pu_delay = 500;
4161 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4162 pu_delay = max(pu_delay, (u16)2400);
4163
4164 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4165}
4166
4167/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4168static void b43_set_pretbtt(struct b43_wldev *dev)
4169{
4170 u16 pretbtt;
4171
4172 /* The time value is in microseconds. */
05c914fe 4173 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4174 pretbtt = 2;
4175 } else {
4176 if (dev->phy.type == B43_PHYTYPE_A)
4177 pretbtt = 120;
4178 else
4179 pretbtt = 250;
4180 }
4181 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4182 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4183}
4184
e4d6b795
MB		 4185/* Shutdown a wireless core */
4186/* Locking: wl->mutex */
4187static void b43_wireless_core_exit(struct b43_wldev *dev)
4188{
1f7d87b0 4189 u32 macctl;
e4d6b795 4190
36dbd954
MB		 4191 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4192 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795
MB		 4193 return;
4194 b43_set_status(dev, B43_STAT_UNINIT);
4195
1f7d87b0
MB		 4196 /* Stop the microcode PSM. */
4197 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4198 macctl &= ~B43_MACCTL_PSM_RUN;
4199 macctl |= B43_MACCTL_PSM_JMP0;
4200 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4201
e4d6b795 4202 b43_dma_free(dev);
5100d5ac 4203 b43_pio_free(dev);
e4d6b795 4204 b43_chip_exit(dev);
cb24f57f 4205 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4206 if (dev->wl->current_beacon) {
4207 dev_kfree_skb_any(dev->wl->current_beacon);
4208 dev->wl->current_beacon = NULL;
4209 }
4210
e4d6b795
MB		 4211 ssb_device_disable(dev->dev, 0);
4212 ssb_bus_may_powerdown(dev->dev->bus);
4213}
4214
4215/* Initialize a wireless core */
4216static int b43_wireless_core_init(struct b43_wldev *dev)
4217{
e4d6b795
MB		 4218 struct ssb_bus *bus = dev->dev->bus;
4219 struct ssb_sprom *sprom = &bus->sprom;
4220 struct b43_phy *phy = &dev->phy;
4221 int err;
a259d6a4
MB		 4222 u64 hf;
4223 u32 tmp;
e4d6b795
MB		 4224
4225 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4226
4227 err = ssb_bus_powerup(bus, 0);
4228 if (err)
4229 goto out;
4230 if (!ssb_device_is_enabled(dev->dev)) {
4231 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4232 b43_wireless_core_reset(dev, tmp);
4233 }
4234
fb11137a 4235 /* Reset all data structures. */
e4d6b795 4236 setup_struct_wldev_for_init(dev);
fb11137a 4237 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4238
4239 /* Enable IRQ routing to this device. */
4240 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4241
4242 b43_imcfglo_timeouts_workaround(dev);
4243 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4244 if (phy->ops->prepare_hardware) {
4245 err = phy->ops->prepare_hardware(dev);
ef1a628d 4246 if (err)
fb11137a 4247 goto err_busdown;
ef1a628d 4248 }
e4d6b795
MB		 4249 err = b43_chip_init(dev);
4250 if (err)
fb11137a 4251 goto err_busdown;
e4d6b795
MB		 4252 b43_shm_write16(dev, B43_SHM_SHARED,
4253 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4254 hf = b43_hf_read(dev);
4255 if (phy->type == B43_PHYTYPE_G) {
4256 hf |= B43_HF_SYMW;
4257 if (phy->rev == 1)
4258 hf |= B43_HF_GDCW;
95de2841 4259 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4260 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4261 }
4262 if (phy->radio_ver == 0x2050) {
4263 if (phy->radio_rev == 6)
4264 hf |= B43_HF_4318TSSI;
4265 if (phy->radio_rev < 6)
4266 hf |= B43_HF_VCORECALC;
e4d6b795 4267 }
1cc8f476
MB		 4268 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4269 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4270#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4271 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4272 (bus->pcicore.dev->id.revision <= 10))
4273 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4274#endif
25d3ef59 4275 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4276 b43_hf_write(dev, hf);
4277
74cfdba7
MB		 4278 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4279 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4280 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4281 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4282
4283 /* Disable sending probe responses from firmware.
4284 * Setting the MaxTime to one usec will always trigger
4285 * a timeout, so we never send any probe resp.
4286 * A timeout of zero is infinite. */
4287 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4288
4289 b43_rate_memory_init(dev);
5042c507 4290 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4291
4292 /* Minimum Contention Window */
4293 if (phy->type == B43_PHYTYPE_B) {
4294 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4295 } else {
4296 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4297 }
4298 /* Maximum Contention Window */
4299 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4300
3dbba8e2
AH		 4301 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4302 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4303 B43_FORCE_PIO) {
5100d5ac
MB		 4304 dev->__using_pio_transfers = 1;
4305 err = b43_pio_init(dev);
4306 } else {
4307 dev->__using_pio_transfers = 0;
4308 err = b43_dma_init(dev);
4309 }
e4d6b795
MB		 4310 if (err)
4311 goto err_chip_exit;
03b29773 4312 b43_qos_init(dev);
d59f720d 4313 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4314 b43_bluetooth_coext_enable(dev);
4315
1cc8f476 4316 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4317 b43_upload_card_macaddress(dev);
e4d6b795 4318 b43_security_init(dev);
e4d6b795 4319
5ab9549a
MB		 4320 ieee80211_wake_queues(dev->wl->hw);
4321
e4d6b795
MB		 4322 b43_set_status(dev, B43_STAT_INITIALIZED);
4323
1a8d1227 4324out:
e4d6b795
MB		 4325 return err;
4326
ef1a628d 4327err_chip_exit:
e4d6b795 4328 b43_chip_exit(dev);
ef1a628d 4329err_busdown:
e4d6b795
MB		 4330 ssb_bus_may_powerdown(bus);
4331 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4332 return err;
4333}
4334
40faacc4
MB		 4335static int b43_op_add_interface(struct ieee80211_hw *hw,
4336 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4337{
4338 struct b43_wl *wl = hw_to_b43_wl(hw);
4339 struct b43_wldev *dev;
e4d6b795 4340 int err = -EOPNOTSUPP;
4150c572
JB		 4341
4342 /* TODO: allow WDS/AP devices to coexist */
4343
05c914fe
JB		 4344 if (conf->type != NL80211_IFTYPE_AP &&
4345 conf->type != NL80211_IFTYPE_MESH_POINT &&
4346 conf->type != NL80211_IFTYPE_STATION &&
4347 conf->type != NL80211_IFTYPE_WDS &&
4348 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4349 return -EOPNOTSUPP;
e4d6b795
MB		 4350
4351 mutex_lock(&wl->mutex);
4150c572 4352 if (wl->operating)
e4d6b795
MB		 4353 goto out_mutex_unlock;
4354
4355 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4356
4357 dev = wl->current_dev;
4150c572 4358 wl->operating = 1;
32bfd35d 4359 wl->vif = conf->vif;
4150c572
JB		 4360 wl->if_type = conf->type;
4361 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4362
4150c572 4363 b43_adjust_opmode(dev);
d59f720d
MB		 4364 b43_set_pretbtt(dev);
4365 b43_set_synth_pu_delay(dev, 0);
4150c572 4366 b43_upload_card_macaddress(dev);
4150c572
JB		 4367
4368 err = 0;
4369 out_mutex_unlock:
4370 mutex_unlock(&wl->mutex);
4371
4372 return err;
4373}
4374
40faacc4
MB		 4375static void b43_op_remove_interface(struct ieee80211_hw *hw,
4376 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4377{
4378 struct b43_wl *wl = hw_to_b43_wl(hw);
4379 struct b43_wldev *dev = wl->current_dev;
4150c572
JB		 4380
4381 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4382
4383 mutex_lock(&wl->mutex);
4384
4385 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4386 B43_WARN_ON(wl->vif != conf->vif);
4387 wl->vif = NULL;
4150c572
JB		 4388
4389 wl->operating = 0;
4390
4150c572
JB		 4391 b43_adjust_opmode(dev);
4392 memset(wl->mac_addr, 0, ETH_ALEN);
4393 b43_upload_card_macaddress(dev);
4150c572
JB		 4394
4395 mutex_unlock(&wl->mutex);
4396}
4397
40faacc4 4398static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4399{
4400 struct b43_wl *wl = hw_to_b43_wl(hw);
4401 struct b43_wldev *dev = wl->current_dev;
4402 int did_init = 0;
923403b8 4403 int err = 0;
4150c572 4404
7be1bb6b
MB		 4405 /* Kill all old instance specific information to make sure
4406 * the card won't use it in the short timeframe between start
4407 * and mac80211 reconfiguring it. */
4408 memset(wl->bssid, 0, ETH_ALEN);
4409 memset(wl->mac_addr, 0, ETH_ALEN);
4410 wl->filter_flags = 0;
4411 wl->radiotap_enabled = 0;
e6f5b934 4412 b43_qos_clear(wl);
6b4bec01
MB		 4413 wl->beacon0_uploaded = 0;
4414 wl->beacon1_uploaded = 0;
4415 wl->beacon_templates_virgin = 1;
fd4973c5 4416 wl->radio_enabled = 1;
7be1bb6b 4417
4150c572
JB		 4418 mutex_lock(&wl->mutex);
4419
e4d6b795
MB		 4420 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4421 err = b43_wireless_core_init(dev);
f41f3f37 4422 if (err)
e4d6b795
MB		 4423 goto out_mutex_unlock;
4424 did_init = 1;
4425 }
4150c572 4426
e4d6b795
MB		 4427 if (b43_status(dev) < B43_STAT_STARTED) {
4428 err = b43_wireless_core_start(dev);
4429 if (err) {
4430 if (did_init)
4431 b43_wireless_core_exit(dev);
4432 goto out_mutex_unlock;
4433 }
4434 }
4435
f41f3f37
JB		 4436 /* XXX: only do if device doesn't support rfkill irq */
4437 wiphy_rfkill_start_polling(hw->wiphy);
4438
4150c572 4439 out_mutex_unlock:
e4d6b795
MB		 4440 mutex_unlock(&wl->mutex);
4441
4442 return err;
4443}
4444
40faacc4 4445static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4446{
4447 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4448 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4449
a82d9922 4450 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4451
e4d6b795 4452 mutex_lock(&wl->mutex);
36dbd954
MB		 4453 if (b43_status(dev) >= B43_STAT_STARTED) {
4454 dev = b43_wireless_core_stop(dev);
4455 if (!dev)
4456 goto out_unlock;
4457 }
4150c572 4458 b43_wireless_core_exit(dev);
fd4973c5 4459 wl->radio_enabled = 0;
36dbd954
MB		 4460
4461out_unlock:
e4d6b795 4462 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4463
4464 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4465}
4466
17741cdc
JB		 4467static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4468 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4469{
4470 struct b43_wl *wl = hw_to_b43_wl(hw);
4471
36dbd954 4472 mutex_lock(&wl->mutex);
9d139c81 4473 b43_update_templates(wl);
36dbd954 4474 mutex_unlock(&wl->mutex);
e66fee6a
MB		 4475
4476 return 0;
4477}
4478
38968d09
JB		 4479static void b43_op_sta_notify(struct ieee80211_hw *hw,
4480 struct ieee80211_vif *vif,
4481 enum sta_notify_cmd notify_cmd,
17741cdc 4482 struct ieee80211_sta *sta)
38968d09
JB		 4483{
4484 struct b43_wl *wl = hw_to_b43_wl(hw);
4485
4486 B43_WARN_ON(!vif || wl->vif != vif);
4487}
4488
25d3ef59
MB		 4489static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4490{
4491 struct b43_wl *wl = hw_to_b43_wl(hw);
4492 struct b43_wldev *dev;
4493
4494 mutex_lock(&wl->mutex);
4495 dev = wl->current_dev;
4496 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4497 /* Disable CFP update during scan on other channels. */
4498 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4499 }
4500 mutex_unlock(&wl->mutex);
4501}
4502
4503static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4504{
4505 struct b43_wl *wl = hw_to_b43_wl(hw);
4506 struct b43_wldev *dev;
4507
4508 mutex_lock(&wl->mutex);
4509 dev = wl->current_dev;
4510 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4511 /* Re-enable CFP update. */
4512 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4513 }
4514 mutex_unlock(&wl->mutex);
4515}
4516
e4d6b795 4517static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4518 .tx = b43_op_tx,
4519 .conf_tx = b43_op_conf_tx,
4520 .add_interface = b43_op_add_interface,
4521 .remove_interface = b43_op_remove_interface,
4522 .config = b43_op_config,
c7ab5ef9 4523 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4524 .configure_filter = b43_op_configure_filter,
4525 .set_key = b43_op_set_key,
035d0243 4526 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4527 .get_stats = b43_op_get_stats,
4528 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4529 .get_tsf = b43_op_get_tsf,
4530 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4531 .start = b43_op_start,
4532 .stop = b43_op_stop,
e66fee6a 4533 .set_tim = b43_op_beacon_set_tim,
38968d09 4534 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4535 .sw_scan_start = b43_op_sw_scan_start_notifier,
4536 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4537 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4538};
4539
4540/* Hard-reset the chip. Do not call this directly.
4541 * Use b43_controller_restart()
4542 */
4543static void b43_chip_reset(struct work_struct *work)
4544{
4545 struct b43_wldev *dev =
4546 container_of(work, struct b43_wldev, restart_work);
4547 struct b43_wl *wl = dev->wl;
4548 int err = 0;
4549 int prev_status;
4550
4551 mutex_lock(&wl->mutex);
4552
4553 prev_status = b43_status(dev);
4554 /* Bring the device down... */
36dbd954
MB		 4555 if (prev_status >= B43_STAT_STARTED) {
4556 dev = b43_wireless_core_stop(dev);
4557 if (!dev) {
4558 err = -ENODEV;
4559 goto out;
4560 }
4561 }
e4d6b795
MB		 4562 if (prev_status >= B43_STAT_INITIALIZED)
4563 b43_wireless_core_exit(dev);
4564
4565 /* ...and up again. */
4566 if (prev_status >= B43_STAT_INITIALIZED) {
4567 err = b43_wireless_core_init(dev);
4568 if (err)
4569 goto out;
4570 }
4571 if (prev_status >= B43_STAT_STARTED) {
4572 err = b43_wireless_core_start(dev);
4573 if (err) {
4574 b43_wireless_core_exit(dev);
4575 goto out;
4576 }
4577 }
3bf0a32e
MB		 4578out:
4579 if (err)
4580 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4581 mutex_unlock(&wl->mutex);
4582 if (err)
4583 b43err(wl, "Controller restart FAILED\n");
4584 else
4585 b43info(wl, "Controller restarted\n");
4586}
4587
bb1eeff1 4588static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4589 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4590{
4591 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4592
bb1eeff1
MB		 4593 if (have_2ghz_phy)
4594 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4595 if (dev->phy.type == B43_PHYTYPE_N) {
4596 if (have_5ghz_phy)
4597 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4598 } else {
4599 if (have_5ghz_phy)
4600 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4601 }
96c755a3 4602
bb1eeff1
MB		 4603 dev->phy.supports_2ghz = have_2ghz_phy;
4604 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4605
4606 return 0;
4607}
4608
4609static void b43_wireless_core_detach(struct b43_wldev *dev)
4610{
4611 /* We release firmware that late to not be required to re-request
4612 * is all the time when we reinit the core. */
4613 b43_release_firmware(dev);
fb11137a 4614 b43_phy_free(dev);
e4d6b795
MB		 4615}
4616
4617static int b43_wireless_core_attach(struct b43_wldev *dev)
4618{
4619 struct b43_wl *wl = dev->wl;
4620 struct ssb_bus *bus = dev->dev->bus;
4621 struct pci_dev *pdev = bus->host_pci;
4622 int err;
96c755a3 4623 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4624 u32 tmp;
4625
4626 /* Do NOT do any device initialization here.
4627 * Do it in wireless_core_init() instead.
4628 * This function is for gathering basic information about the HW, only.
4629 * Also some structs may be set up here. But most likely you want to have
4630 * that in core_init(), too.
4631 */
4632
4633 err = ssb_bus_powerup(bus, 0);
4634 if (err) {
4635 b43err(wl, "Bus powerup failed\n");
4636 goto out;
4637 }
4638 /* Get the PHY type. */
4639 if (dev->dev->id.revision >= 5) {
4640 u32 tmshigh;
4641
4642 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4643 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4644 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4645 } else
96c755a3 4646 B43_WARN_ON(1);
e4d6b795 4647
96c755a3 4648 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4649 dev->phy.radio_on = 1;
e4d6b795
MB		 4650 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4651 b43_wireless_core_reset(dev, tmp);
4652
4653 err = b43_phy_versioning(dev);
4654 if (err)
21954c36 4655 goto err_powerdown;
e4d6b795
MB		 4656 /* Check if this device supports multiband. */
4657 if (!pdev ||
4658 (pdev->device != 0x4312 &&
4659 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4660 /* No multiband support. */
96c755a3
MB		 4661 have_2ghz_phy = 0;
4662 have_5ghz_phy = 0;
e4d6b795
MB		 4663 switch (dev->phy.type) {
4664 case B43_PHYTYPE_A:
96c755a3 4665 have_5ghz_phy = 1;
e4d6b795 4666 break;
9d86a2d5 4667 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4668#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4669 have_5ghz_phy = 1;
86b2892a 4670#endif
e4d6b795 4671 case B43_PHYTYPE_G:
96c755a3
MB		 4672 case B43_PHYTYPE_N:
4673 have_2ghz_phy = 1;
e4d6b795
MB		 4674 break;
4675 default:
4676 B43_WARN_ON(1);
4677 }
4678 }
96c755a3
MB		 4679 if (dev->phy.type == B43_PHYTYPE_A) {
4680 /* FIXME */
4681 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4682 err = -EOPNOTSUPP;
4683 goto err_powerdown;
4684 }
2e35af14
MB		 4685 if (1 /* disable A-PHY */) {
4686 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4687 if (dev->phy.type != B43_PHYTYPE_N &&
4688 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4689 have_2ghz_phy = 1;
4690 have_5ghz_phy = 0;
4691 }
4692 }
4693
fb11137a
MB		 4694 err = b43_phy_allocate(dev);
4695 if (err)
4696 goto err_powerdown;
4697
96c755a3 4698 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4699 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4700 b43_wireless_core_reset(dev, tmp);
4701
4702 err = b43_validate_chipaccess(dev);
4703 if (err)
fb11137a 4704 goto err_phy_free;
bb1eeff1 4705 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4706 if (err)
fb11137a 4707 goto err_phy_free;
e4d6b795
MB		 4708
4709 /* Now set some default "current_dev" */
4710 if (!wl->current_dev)
4711 wl->current_dev = dev;
4712 INIT_WORK(&dev->restart_work, b43_chip_reset);
4713
cb24f57f 4714 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4715 ssb_device_disable(dev->dev, 0);
4716 ssb_bus_may_powerdown(bus);
4717
4718out:
4719 return err;
4720
fb11137a
MB		 4721err_phy_free:
4722 b43_phy_free(dev);
e4d6b795
MB		 4723err_powerdown:
4724 ssb_bus_may_powerdown(bus);
4725 return err;
4726}
4727
4728static void b43_one_core_detach(struct ssb_device *dev)
4729{
4730 struct b43_wldev *wldev;
4731 struct b43_wl *wl;
4732
3bf0a32e
MB		 4733 /* Do not cancel ieee80211-workqueue based work here.
4734 * See comment in b43_remove(). */
4735
e4d6b795
MB		 4736 wldev = ssb_get_drvdata(dev);
4737 wl = wldev->wl;
e4d6b795
MB		 4738 b43_debugfs_remove_device(wldev);
4739 b43_wireless_core_detach(wldev);
4740 list_del(&wldev->list);
4741 wl->nr_devs--;
4742 ssb_set_drvdata(dev, NULL);
4743 kfree(wldev);
4744}
4745
4746static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4747{
4748 struct b43_wldev *wldev;
4749 struct pci_dev *pdev;
4750 int err = -ENOMEM;
4751
4752 if (!list_empty(&wl->devlist)) {
4753 /* We are not the first core on this chip. */
4754 pdev = dev->bus->host_pci;
4755 /* Only special chips support more than one wireless
4756 * core, although some of the other chips have more than
4757 * one wireless core as well. Check for this and
4758 * bail out early.
4759 */
4760 if (!pdev ||
4761 ((pdev->device != 0x4321) &&
4762 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4763 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4764 return -ENODEV;
4765 }
4766 }
4767
4768 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4769 if (!wldev)
4770 goto out;
4771
4772 wldev->dev = dev;
4773 wldev->wl = wl;
4774 b43_set_status(wldev, B43_STAT_UNINIT);
4775 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 4776 INIT_LIST_HEAD(&wldev->list);
4777
4778 err = b43_wireless_core_attach(wldev);
4779 if (err)
4780 goto err_kfree_wldev;
4781
4782 list_add(&wldev->list, &wl->devlist);
4783 wl->nr_devs++;
4784 ssb_set_drvdata(dev, wldev);
4785 b43_debugfs_add_device(wldev);
4786
4787 out:
4788 return err;
4789
4790 err_kfree_wldev:
4791 kfree(wldev);
4792 return err;
4793}
4794
9fc38458
MB		 4795#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4796 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4797 (pdev->device == _device) && \
4798 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4799 (pdev->subsystem_device == _subdevice) )
4800
e4d6b795
MB		 4801static void b43_sprom_fixup(struct ssb_bus *bus)
4802{
1855ba78
MB		 4803 struct pci_dev *pdev;
4804
e4d6b795
MB		 4805 /* boardflags workarounds */
4806 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4807 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4808 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4809 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4810 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4811 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4812 if (bus->bustype == SSB_BUSTYPE_PCI) {
4813 pdev = bus->host_pci;
9fc38458 4814 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4815 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4816 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4817 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4818 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4819 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4820 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4821 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4822 }
e4d6b795
MB		 4823}
4824
4825static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4826{
4827 struct ieee80211_hw *hw = wl->hw;
4828
4829 ssb_set_devtypedata(dev, NULL);
4830 ieee80211_free_hw(hw);
4831}
4832
4833static int b43_wireless_init(struct ssb_device *dev)
4834{
4835 struct ssb_sprom *sprom = &dev->bus->sprom;
4836 struct ieee80211_hw *hw;
4837 struct b43_wl *wl;
4838 int err = -ENOMEM;
4839
4840 b43_sprom_fixup(dev->bus);
4841
4842 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4843 if (!hw) {
4844 b43err(NULL, "Could not allocate ieee80211 device\n");
4845 goto out;
4846 }
403a3a13 4847 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4848
4849 /* fill hw info */
605a0bd6 4850 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4851 IEEE80211_HW_SIGNAL_DBM |
4852 IEEE80211_HW_NOISE_DBM;
4853
f59ac048
LR		 4854 hw->wiphy->interface_modes =
4855 BIT(NL80211_IFTYPE_AP) |
4856 BIT(NL80211_IFTYPE_MESH_POINT) |
4857 BIT(NL80211_IFTYPE_STATION) |
4858 BIT(NL80211_IFTYPE_WDS) |
4859 BIT(NL80211_IFTYPE_ADHOC);
4860
403a3a13
MB		 4861 hw->queues = modparam_qos ? 4 : 1;
4862 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4863 hw->max_rates = 2;
e4d6b795 4864 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4865 if (is_valid_ether_addr(sprom->et1mac))
4866 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4867 else
95de2841 4868 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4869
403a3a13 4870 /* Initialize struct b43_wl */
e4d6b795 4871 wl->hw = hw;
e4d6b795 4872 mutex_init(&wl->mutex);
36dbd954 4873 spin_lock_init(&wl->hardirq_lock);
e4d6b795 4874 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4875 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4876 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 4877 INIT_WORK(&wl->tx_work, b43_tx_work);
4878 skb_queue_head_init(&wl->tx_queue);
e4d6b795
MB		 4879
4880 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4881 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4882 dev->bus->chip_id, dev->id.revision);
e4d6b795 4883 err = 0;
060210f9 4884out:
e4d6b795
MB		 4885 return err;
4886}
4887
4888static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4889{
4890 struct b43_wl *wl;
4891 int err;
4892 int first = 0;
4893
4894 wl = ssb_get_devtypedata(dev);
4895 if (!wl) {
4896 /* Probing the first core. Must setup common struct b43_wl */
4897 first = 1;
4898 err = b43_wireless_init(dev);
4899 if (err)
4900 goto out;
4901 wl = ssb_get_devtypedata(dev);
4902 B43_WARN_ON(!wl);
4903 }
4904 err = b43_one_core_attach(dev, wl);
4905 if (err)
4906 goto err_wireless_exit;
4907
4908 if (first) {
4909 err = ieee80211_register_hw(wl->hw);
4910 if (err)
4911 goto err_one_core_detach;
a78b3bb2
MB		 4912 b43_leds_register(wl->current_dev);
4913 b43_rng_init(wl);
e4d6b795
MB		 4914 }
4915
4916 out:
4917 return err;
4918
4919 err_one_core_detach:
4920 b43_one_core_detach(dev);
4921 err_wireless_exit:
4922 if (first)
4923 b43_wireless_exit(dev, wl);
4924 return err;
4925}
4926
4927static void b43_remove(struct ssb_device *dev)
4928{
4929 struct b43_wl *wl = ssb_get_devtypedata(dev);
4930 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4931
3bf0a32e
MB		 4932 /* We must cancel any work here before unregistering from ieee80211,
4933 * as the ieee80211 unreg will destroy the workqueue. */
4934 cancel_work_sync(&wldev->restart_work);
4935
e4d6b795 4936 B43_WARN_ON(!wl);
403a3a13
MB		 4937 if (wl->current_dev == wldev) {
4938 /* Restore the queues count before unregistering, because firmware detect
4939 * might have modified it. Restoring is important, so the networking
4940 * stack can properly free resources. */
4941 wl->hw->queues = wl->mac80211_initially_registered_queues;
a78b3bb2
MB		 4942 wl->current_dev = NULL;
4943 cancel_work_sync(&wl->leds.work);
e4d6b795 4944 ieee80211_unregister_hw(wl->hw);
403a3a13 4945 }
e4d6b795
MB		 4946
4947 b43_one_core_detach(dev);
4948
4949 if (list_empty(&wl->devlist)) {
a78b3bb2
MB		 4950 b43_rng_exit(wl);
4951 b43_leds_unregister(wldev);
e4d6b795
MB		 4952 /* Last core on the chip unregistered.
4953 * We can destroy common struct b43_wl.
4954 */
4955 b43_wireless_exit(dev, wl);
4956 }
4957}
4958
4959/* Perform a hardware reset. This can be called from any context. */
4960void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4961{
4962 /* Must avoid requeueing, if we are in shutdown. */
4963 if (b43_status(dev) < B43_STAT_INITIALIZED)
4964 return;
4965 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 4966 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 4967}
4968
e4d6b795
MB		 4969static struct ssb_driver b43_ssb_driver = {
4970 .name = KBUILD_MODNAME,
4971 .id_table = b43_ssb_tbl,
4972 .probe = b43_probe,
4973 .remove = b43_remove,
e4d6b795
MB		 4974};
4975
26bc783f
MB		 4976static void b43_print_driverinfo(void)
4977{
4978 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 4979 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 4980
4981#ifdef CONFIG_B43_PCI_AUTOSELECT
4982 feat_pci = "P";
4983#endif
4984#ifdef CONFIG_B43_PCMCIA
4985 feat_pcmcia = "M";
4986#endif
4987#ifdef CONFIG_B43_NPHY
4988 feat_nphy = "N";
4989#endif
4990#ifdef CONFIG_B43_LEDS
4991 feat_leds = "L";
3dbba8e2
AH		 4992#endif
4993#ifdef CONFIG_B43_SDIO
4994 feat_sdio = "S";
26bc783f
MB		 4995#endif
4996 printk(KERN_INFO "Broadcom 43xx driver loaded "
3dbba8e2 4997 "[ Features: %s%s%s%s%s, Firmware-ID: "
26bc783f
MB		 4998 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4999 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5000 feat_leds, feat_sdio);
26bc783f
MB		 5001}
5002
e4d6b795
MB		 5003static int __init b43_init(void)
5004{
5005 int err;
5006
5007 b43_debugfs_init();
5008 err = b43_pcmcia_init();
5009 if (err)
5010 goto err_dfs_exit;
3dbba8e2 5011 err = b43_sdio_init();
e4d6b795
MB		 5012 if (err)
5013 goto err_pcmcia_exit;
3dbba8e2
AH		 5014 err = ssb_driver_register(&b43_ssb_driver);
5015 if (err)
5016 goto err_sdio_exit;
26bc783f 5017 b43_print_driverinfo();
e4d6b795
MB		 5018
5019 return err;
5020
3dbba8e2
AH		 5021err_sdio_exit:
5022 b43_sdio_exit();
e4d6b795
MB		 5023err_pcmcia_exit:
5024 b43_pcmcia_exit();
5025err_dfs_exit:
5026 b43_debugfs_exit();
5027 return err;
5028}
5029
5030static void __exit b43_exit(void)
5031{
5032 ssb_driver_unregister(&b43_ssb_driver);
3dbba8e2 5033 b43_sdio_exit();
e4d6b795
MB		 5034 b43_pcmcia_exit();
5035 b43_debugfs_exit();
5036}
5037
5038module_init(b43_init)
5039module_exit(b43_exit)
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