]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/wireless/b43/main.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
b43: rename TX header formats
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
3dbba8e2
AH		 11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
e4d6b795
MB		 14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32*/
33
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/moduleparam.h>
37#include <linux/if_arp.h>
38#include <linux/etherdevice.h>
e4d6b795 39#include <linux/firmware.h>
e4d6b795
MB		 40#include <linux/workqueue.h>
41#include <linux/skbuff.h>
96cf49a2 42#include <linux/io.h>
e4d6b795 43#include <linux/dma-mapping.h>
5a0e3ad6 44#include <linux/slab.h>
e4d6b795
MB		 45#include <asm/unaligned.h>
46
47#include "b43.h"
48#include "main.h"
49#include "debugfs.h"
ef1a628d
MB		 50#include "phy_common.h"
51#include "phy_g.h"
3d0da751 52#include "phy_n.h"
e4d6b795 53#include "dma.h"
5100d5ac 54#include "pio.h"
e4d6b795
MB		 55#include "sysfs.h"
56#include "xmit.h"
e4d6b795
MB		 57#include "lo.h"
58#include "pcmcia.h"
3dbba8e2
AH		 59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
0136e51e 66MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 67MODULE_LICENSE("GPL");
68
9c7d99d6 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
6021e08d
TG		 70MODULE_FIRMWARE("b43/ucode11.fw");
71MODULE_FIRMWARE("b43/ucode13.fw");
72MODULE_FIRMWARE("b43/ucode14.fw");
73MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 74MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 75MODULE_FIRMWARE("b43/ucode5.fw");
76MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 77
78static int modparam_bad_frames_preempt;
79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
82
e4d6b795
MB		 83static char modparam_fwpostfix[16];
84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
86
e4d6b795
MB		 87static int modparam_hwpctl;
88module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
90
91static int modparam_nohwcrypt;
92module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94
035d0243 95static int modparam_hwtkip;
96module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
98
403a3a13
MB		 99static int modparam_qos = 1;
100module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 101MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
102
1855ba78
MB		 103static int modparam_btcoex = 1;
104module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 105MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 106
060210f9
MB		 107int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108module_param_named(verbose, b43_modparam_verbose, int, 0644);
109MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110
41950bdf 111static int b43_modparam_pio = B43_PIO_DEFAULT;
9e3bd919
LT		 112module_param_named(pio, b43_modparam_pio, int, 0644);
113MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 114
3c65ab62
RM		 115#ifdef CONFIG_B43_BCMA
116static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 117 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
121 BCMA_CORETABLE_END
122};
123MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
124#endif
125
aec7ffdf 126#ifdef CONFIG_B43_SSB
e4d6b795
MB		 127static const struct ssb_device_id b43_ssb_tbl[] = {
128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 138 SSB_DEVTABLE_END
139};
e4d6b795 140MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 141#endif
e4d6b795
MB		 142
143/* Channel and ratetables are shared for all devices.
144 * They can't be const, because ieee80211 puts some precalculated
145 * data in there. This data is the same for all devices, so we don't
146 * get concurrency issues */
147#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 148 { \
149 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
150 .hw_value = (_rateid), \
151 .flags = (_flags), \
e4d6b795 152 }
8318d78a
JB		 153
154/*
155 * NOTE: When changing this, sync with xmit.c's
156 * b43_plcp_get_bitrate_idx_* functions!
157 */
e4d6b795 158static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 159 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
160 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
161 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
164 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 171};
172
173#define b43_a_ratetable (__b43_ratetable + 4)
174#define b43_a_ratetable_size 8
175#define b43_b_ratetable (__b43_ratetable + 0)
176#define b43_b_ratetable_size 4
177#define b43_g_ratetable (__b43_ratetable + 0)
178#define b43_g_ratetable_size 12
179
bb1eeff1
MB		 180#define CHAN4G(_channel, _freq, _flags) { \
181 .band = IEEE80211_BAND_2GHZ, \
182 .center_freq = (_freq), \
183 .hw_value = (_channel), \
184 .flags = (_flags), \
185 .max_antenna_gain = 0, \
186 .max_power = 30, \
187}
96c755a3 188static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 189 CHAN4G(1, 2412, 0),
190 CHAN4G(2, 2417, 0),
191 CHAN4G(3, 2422, 0),
192 CHAN4G(4, 2427, 0),
193 CHAN4G(5, 2432, 0),
194 CHAN4G(6, 2437, 0),
195 CHAN4G(7, 2442, 0),
196 CHAN4G(8, 2447, 0),
197 CHAN4G(9, 2452, 0),
198 CHAN4G(10, 2457, 0),
199 CHAN4G(11, 2462, 0),
200 CHAN4G(12, 2467, 0),
201 CHAN4G(13, 2472, 0),
202 CHAN4G(14, 2484, 0),
203};
204#undef CHAN4G
205
206#define CHAN5G(_channel, _flags) { \
207 .band = IEEE80211_BAND_5GHZ, \
208 .center_freq = 5000 + (5 * (_channel)), \
209 .hw_value = (_channel), \
210 .flags = (_flags), \
211 .max_antenna_gain = 0, \
212 .max_power = 30, \
213}
214static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
215 CHAN5G(32, 0), CHAN5G(34, 0),
216 CHAN5G(36, 0), CHAN5G(38, 0),
217 CHAN5G(40, 0), CHAN5G(42, 0),
218 CHAN5G(44, 0), CHAN5G(46, 0),
219 CHAN5G(48, 0), CHAN5G(50, 0),
220 CHAN5G(52, 0), CHAN5G(54, 0),
221 CHAN5G(56, 0), CHAN5G(58, 0),
222 CHAN5G(60, 0), CHAN5G(62, 0),
223 CHAN5G(64, 0), CHAN5G(66, 0),
224 CHAN5G(68, 0), CHAN5G(70, 0),
225 CHAN5G(72, 0), CHAN5G(74, 0),
226 CHAN5G(76, 0), CHAN5G(78, 0),
227 CHAN5G(80, 0), CHAN5G(82, 0),
228 CHAN5G(84, 0), CHAN5G(86, 0),
229 CHAN5G(88, 0), CHAN5G(90, 0),
230 CHAN5G(92, 0), CHAN5G(94, 0),
231 CHAN5G(96, 0), CHAN5G(98, 0),
232 CHAN5G(100, 0), CHAN5G(102, 0),
233 CHAN5G(104, 0), CHAN5G(106, 0),
234 CHAN5G(108, 0), CHAN5G(110, 0),
235 CHAN5G(112, 0), CHAN5G(114, 0),
236 CHAN5G(116, 0), CHAN5G(118, 0),
237 CHAN5G(120, 0), CHAN5G(122, 0),
238 CHAN5G(124, 0), CHAN5G(126, 0),
239 CHAN5G(128, 0), CHAN5G(130, 0),
240 CHAN5G(132, 0), CHAN5G(134, 0),
241 CHAN5G(136, 0), CHAN5G(138, 0),
242 CHAN5G(140, 0), CHAN5G(142, 0),
243 CHAN5G(144, 0), CHAN5G(145, 0),
244 CHAN5G(146, 0), CHAN5G(147, 0),
245 CHAN5G(148, 0), CHAN5G(149, 0),
246 CHAN5G(150, 0), CHAN5G(151, 0),
247 CHAN5G(152, 0), CHAN5G(153, 0),
248 CHAN5G(154, 0), CHAN5G(155, 0),
249 CHAN5G(156, 0), CHAN5G(157, 0),
250 CHAN5G(158, 0), CHAN5G(159, 0),
251 CHAN5G(160, 0), CHAN5G(161, 0),
252 CHAN5G(162, 0), CHAN5G(163, 0),
253 CHAN5G(164, 0), CHAN5G(165, 0),
254 CHAN5G(166, 0), CHAN5G(168, 0),
255 CHAN5G(170, 0), CHAN5G(172, 0),
256 CHAN5G(174, 0), CHAN5G(176, 0),
257 CHAN5G(178, 0), CHAN5G(180, 0),
258 CHAN5G(182, 0), CHAN5G(184, 0),
259 CHAN5G(186, 0), CHAN5G(188, 0),
260 CHAN5G(190, 0), CHAN5G(192, 0),
261 CHAN5G(194, 0), CHAN5G(196, 0),
262 CHAN5G(198, 0), CHAN5G(200, 0),
263 CHAN5G(202, 0), CHAN5G(204, 0),
264 CHAN5G(206, 0), CHAN5G(208, 0),
265 CHAN5G(210, 0), CHAN5G(212, 0),
266 CHAN5G(214, 0), CHAN5G(216, 0),
267 CHAN5G(218, 0), CHAN5G(220, 0),
268 CHAN5G(222, 0), CHAN5G(224, 0),
269 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 270};
271
bb1eeff1
MB		 272static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
273 CHAN5G(34, 0), CHAN5G(36, 0),
274 CHAN5G(38, 0), CHAN5G(40, 0),
275 CHAN5G(42, 0), CHAN5G(44, 0),
276 CHAN5G(46, 0), CHAN5G(48, 0),
277 CHAN5G(52, 0), CHAN5G(56, 0),
278 CHAN5G(60, 0), CHAN5G(64, 0),
279 CHAN5G(100, 0), CHAN5G(104, 0),
280 CHAN5G(108, 0), CHAN5G(112, 0),
281 CHAN5G(116, 0), CHAN5G(120, 0),
282 CHAN5G(124, 0), CHAN5G(128, 0),
283 CHAN5G(132, 0), CHAN5G(136, 0),
284 CHAN5G(140, 0), CHAN5G(149, 0),
285 CHAN5G(153, 0), CHAN5G(157, 0),
286 CHAN5G(161, 0), CHAN5G(165, 0),
287 CHAN5G(184, 0), CHAN5G(188, 0),
288 CHAN5G(192, 0), CHAN5G(196, 0),
289 CHAN5G(200, 0), CHAN5G(204, 0),
290 CHAN5G(208, 0), CHAN5G(212, 0),
291 CHAN5G(216, 0),
292};
293#undef CHAN5G
294
295static struct ieee80211_supported_band b43_band_5GHz_nphy = {
296 .band = IEEE80211_BAND_5GHZ,
297 .channels = b43_5ghz_nphy_chantable,
298 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
299 .bitrates = b43_a_ratetable,
300 .n_bitrates = b43_a_ratetable_size,
e4d6b795 301};
8318d78a 302
bb1eeff1
MB		 303static struct ieee80211_supported_band b43_band_5GHz_aphy = {
304 .band = IEEE80211_BAND_5GHZ,
305 .channels = b43_5ghz_aphy_chantable,
306 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
307 .bitrates = b43_a_ratetable,
308 .n_bitrates = b43_a_ratetable_size,
8318d78a 309};
e4d6b795 310
8318d78a 311static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 312 .band = IEEE80211_BAND_2GHZ,
313 .channels = b43_2ghz_chantable,
314 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
315 .bitrates = b43_g_ratetable,
316 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 317};
318
e4d6b795
MB		 319static void b43_wireless_core_exit(struct b43_wldev *dev);
320static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 321static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 322static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 323static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
324 struct ieee80211_vif *vif,
325 struct ieee80211_bss_conf *conf,
326 u32 changed);
e4d6b795
MB		 327
328static int b43_ratelimit(struct b43_wl *wl)
329{
330 if (!wl || !wl->current_dev)
331 return 1;
332 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
333 return 1;
334 /* We are up and running.
335 * Ratelimit the messages to avoid DoS over the net. */
336 return net_ratelimit();
337}
338
339void b43info(struct b43_wl *wl, const char *fmt, ...)
340{
5b736d42 341 struct va_format vaf;
e4d6b795
MB		 342 va_list args;
343
060210f9
MB		 344 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
345 return;
e4d6b795
MB		 346 if (!b43_ratelimit(wl))
347 return;
5b736d42 348
e4d6b795 349 va_start(args, fmt);
5b736d42
JP		 350
351 vaf.fmt = fmt;
352 vaf.va = &args;
353
354 printk(KERN_INFO "b43-%s: %pV",
355 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
356
e4d6b795
MB		 357 va_end(args);
358}
359
360void b43err(struct b43_wl *wl, const char *fmt, ...)
361{
5b736d42 362 struct va_format vaf;
e4d6b795
MB		 363 va_list args;
364
060210f9
MB		 365 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
366 return;
e4d6b795
MB		 367 if (!b43_ratelimit(wl))
368 return;
5b736d42 369
e4d6b795 370 va_start(args, fmt);
5b736d42
JP		 371
372 vaf.fmt = fmt;
373 vaf.va = &args;
374
375 printk(KERN_ERR "b43-%s ERROR: %pV",
376 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
377
e4d6b795
MB		 378 va_end(args);
379}
380
381void b43warn(struct b43_wl *wl, const char *fmt, ...)
382{
5b736d42 383 struct va_format vaf;
e4d6b795
MB		 384 va_list args;
385
060210f9
MB		 386 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
387 return;
e4d6b795
MB		 388 if (!b43_ratelimit(wl))
389 return;
5b736d42 390
e4d6b795 391 va_start(args, fmt);
5b736d42
JP		 392
393 vaf.fmt = fmt;
394 vaf.va = &args;
395
396 printk(KERN_WARNING "b43-%s warning: %pV",
397 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
398
e4d6b795
MB		 399 va_end(args);
400}
401
e4d6b795
MB		 402void b43dbg(struct b43_wl *wl, const char *fmt, ...)
403{
5b736d42 404 struct va_format vaf;
e4d6b795
MB		 405 va_list args;
406
060210f9
MB		 407 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
408 return;
5b736d42 409
e4d6b795 410 va_start(args, fmt);
5b736d42
JP		 411
412 vaf.fmt = fmt;
413 vaf.va = &args;
414
415 printk(KERN_DEBUG "b43-%s debug: %pV",
416 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
417
e4d6b795
MB		 418 va_end(args);
419}
e4d6b795
MB		 420
421static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
422{
423 u32 macctl;
424
425 B43_WARN_ON(offset % 4 != 0);
426
427 macctl = b43_read32(dev, B43_MMIO_MACCTL);
428 if (macctl & B43_MACCTL_BE)
429 val = swab32(val);
430
431 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
432 mmiowb();
433 b43_write32(dev, B43_MMIO_RAM_DATA, val);
434}
435
280d0e16
MB		 436static inline void b43_shm_control_word(struct b43_wldev *dev,
437 u16 routing, u16 offset)
e4d6b795
MB		 438{
439 u32 control;
440
441 /* "offset" is the WORD offset. */
e4d6b795
MB		 442 control = routing;
443 control <<= 16;
444 control |= offset;
445 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
446}
447
69eddc8a 448u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 449{
450 u32 ret;
451
452 if (routing == B43_SHM_SHARED) {
453 B43_WARN_ON(offset & 0x0001);
454 if (offset & 0x0003) {
455 /* Unaligned access */
456 b43_shm_control_word(dev, routing, offset >> 2);
457 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 458 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 459 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 460
280d0e16 461 goto out;
e4d6b795
MB		 462 }
463 offset >>= 2;
464 }
465 b43_shm_control_word(dev, routing, offset);
466 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 467out:
e4d6b795
MB		 468 return ret;
469}
470
69eddc8a 471u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 472{
473 u16 ret;
474
e4d6b795
MB		 475 if (routing == B43_SHM_SHARED) {
476 B43_WARN_ON(offset & 0x0001);
477 if (offset & 0x0003) {
478 /* Unaligned access */
479 b43_shm_control_word(dev, routing, offset >> 2);
480 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
481
280d0e16 482 goto out;
e4d6b795
MB		 483 }
484 offset >>= 2;
485 }
486 b43_shm_control_word(dev, routing, offset);
487 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 488out:
e4d6b795
MB		 489 return ret;
490}
491
69eddc8a 492void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 493{
e4d6b795
MB		 494 if (routing == B43_SHM_SHARED) {
495 B43_WARN_ON(offset & 0x0001);
496 if (offset & 0x0003) {
497 /* Unaligned access */
498 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 499 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 500 value & 0xFFFF);
e4d6b795 501 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 502 b43_write16(dev, B43_MMIO_SHM_DATA,
503 (value >> 16) & 0xFFFF);
6bbc321a 504 return;
e4d6b795
MB		 505 }
506 offset >>= 2;
507 }
508 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 509 b43_write32(dev, B43_MMIO_SHM_DATA, value);
510}
511
69eddc8a 512void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 513{
e4d6b795
MB		 514 if (routing == B43_SHM_SHARED) {
515 B43_WARN_ON(offset & 0x0001);
516 if (offset & 0x0003) {
517 /* Unaligned access */
518 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 519 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 520 return;
e4d6b795
MB		 521 }
522 offset >>= 2;
523 }
524 b43_shm_control_word(dev, routing, offset);
e4d6b795 525 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 526}
527
e4d6b795 528/* Read HostFlags */
99da185a 529u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 530{
35f0d354 531 u64 ret;
e4d6b795
MB		 532
533 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
534 ret <<= 16;
35f0d354
MB		 535 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
536 ret <<= 16;
e4d6b795
MB		 537 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
538
539 return ret;
540}
541
542/* Write HostFlags */
35f0d354 543void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 544{
35f0d354
MB		 545 u16 lo, mi, hi;
546
547 lo = (value & 0x00000000FFFFULL);
548 mi = (value & 0x0000FFFF0000ULL) >> 16;
549 hi = (value & 0xFFFF00000000ULL) >> 32;
550 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 553}
554
403a3a13
MB		 555/* Read the firmware capabilities bitmask (Opensource firmware only) */
556static u16 b43_fwcapa_read(struct b43_wldev *dev)
557{
558 B43_WARN_ON(!dev->fw.opensource);
559 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
560}
561
3ebbbb56 562void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 563{
3ebbbb56
MB		 564 u32 low, high;
565
21d889d4 566 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 567
568 /* The hardware guarantees us an atomic read, if we
569 * read the low register first. */
570 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
571 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
572
573 *tsf = high;
574 *tsf <<= 32;
575 *tsf |= low;
e4d6b795
MB		 576}
577
578static void b43_time_lock(struct b43_wldev *dev)
579{
580 u32 macctl;
581
582 macctl = b43_read32(dev, B43_MMIO_MACCTL);
583 macctl |= B43_MACCTL_TBTTHOLD;
584 b43_write32(dev, B43_MMIO_MACCTL, macctl);
585 /* Commit the write */
586 b43_read32(dev, B43_MMIO_MACCTL);
587}
588
589static void b43_time_unlock(struct b43_wldev *dev)
590{
591 u32 macctl;
592
593 macctl = b43_read32(dev, B43_MMIO_MACCTL);
594 macctl &= ~B43_MACCTL_TBTTHOLD;
595 b43_write32(dev, B43_MMIO_MACCTL, macctl);
596 /* Commit the write */
597 b43_read32(dev, B43_MMIO_MACCTL);
598}
599
600static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601{
3ebbbb56
MB		 602 u32 low, high;
603
21d889d4 604 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 605
606 low = tsf;
607 high = (tsf >> 32);
608 /* The hardware guarantees us an atomic write, if we
609 * write the low register first. */
610 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
611 mmiowb();
612 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
613 mmiowb();
e4d6b795
MB		 614}
615
616void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
617{
618 b43_time_lock(dev);
619 b43_tsf_write_locked(dev, tsf);
620 b43_time_unlock(dev);
621}
622
623static
99da185a 624void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 625{
626 static const u8 zero_addr[ETH_ALEN] = { 0 };
627 u16 data;
628
629 if (!mac)
630 mac = zero_addr;
631
632 offset |= 0x0020;
633 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
634
635 data = mac[0];
636 data |= mac[1] << 8;
637 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 data = mac[2];
639 data |= mac[3] << 8;
640 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 data = mac[4];
642 data |= mac[5] << 8;
643 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
644}
645
646static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
647{
648 const u8 *mac;
649 const u8 *bssid;
650 u8 mac_bssid[ETH_ALEN * 2];
651 int i;
652 u32 tmp;
653
654 bssid = dev->wl->bssid;
655 mac = dev->wl->mac_addr;
656
657 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
658
659 memcpy(mac_bssid, mac, ETH_ALEN);
660 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
661
662 /* Write our MAC address and BSSID to template ram */
663 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
664 tmp = (u32) (mac_bssid[i + 0]);
665 tmp |= (u32) (mac_bssid[i + 1]) << 8;
666 tmp |= (u32) (mac_bssid[i + 2]) << 16;
667 tmp |= (u32) (mac_bssid[i + 3]) << 24;
668 b43_ram_write(dev, 0x20 + i, tmp);
669 }
670}
671
4150c572 672static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 673{
e4d6b795 674 b43_write_mac_bssid_templates(dev);
4150c572 675 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 676}
677
678static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
679{
680 /* slot_time is in usec. */
b6c3f5be
LF		 681 /* This test used to exit for all but a G PHY. */
682 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 683 return;
b6c3f5be
LF		 684 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
685 /* Shared memory location 0x0010 is the slot time and should be
686 * set to slot_time; however, this register is initially 0 and changing
687 * the value adversely affects the transmit rate for BCM4311
688 * devices. Until this behavior is unterstood, delete this step
689 *
690 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
691 */
e4d6b795
MB		 692}
693
694static void b43_short_slot_timing_enable(struct b43_wldev *dev)
695{
696 b43_set_slot_time(dev, 9);
e4d6b795
MB		 697}
698
699static void b43_short_slot_timing_disable(struct b43_wldev *dev)
700{
701 b43_set_slot_time(dev, 20);
e4d6b795
MB		 702}
703
e4d6b795 704/* DummyTransmission function, as documented on
2f19c287 705 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 706 */
2f19c287 707void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 708{
709 struct b43_phy *phy = &dev->phy;
710 unsigned int i, max_loop;
711 u16 value;
712 u32 buffer[5] = {
713 0x00000000,
714 0x00D40000,
715 0x00000000,
716 0x01000000,
717 0x00000000,
718 };
719
2f19c287 720 if (ofdm) {
e4d6b795
MB		 721 max_loop = 0x1E;
722 buffer[0] = 0x000201CC;
2f19c287 723 } else {
e4d6b795
MB		 724 max_loop = 0xFA;
725 buffer[0] = 0x000B846E;
e4d6b795
MB		 726 }
727
728 for (i = 0; i < 5; i++)
729 b43_ram_write(dev, i * 4, buffer[i]);
730
e4d6b795 731 b43_write16(dev, 0x0568, 0x0000);
21d889d4 732 if (dev->dev->core_rev < 11)
2f19c287
GS		 733 b43_write16(dev, 0x07C0, 0x0000);
734 else
735 b43_write16(dev, 0x07C0, 0x0100);
736 value = (ofdm ? 0x41 : 0x40);
e4d6b795 737 b43_write16(dev, 0x050C, value);
2f19c287
GS		 738 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
739 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 740 b43_write16(dev, 0x0508, 0x0000);
741 b43_write16(dev, 0x050A, 0x0000);
742 b43_write16(dev, 0x054C, 0x0000);
743 b43_write16(dev, 0x056A, 0x0014);
744 b43_write16(dev, 0x0568, 0x0826);
745 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 746 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
747 //SPEC TODO
748 }
749
750 switch (phy->type) {
751 case B43_PHYTYPE_N:
752 b43_write16(dev, 0x0502, 0x00D0);
753 break;
754 case B43_PHYTYPE_LP:
755 b43_write16(dev, 0x0502, 0x0050);
756 break;
757 default:
758 b43_write16(dev, 0x0502, 0x0030);
759 }
e4d6b795
MB		 760
761 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
762 b43_radio_write16(dev, 0x0051, 0x0017);
763 for (i = 0x00; i < max_loop; i++) {
764 value = b43_read16(dev, 0x050E);
765 if (value & 0x0080)
766 break;
767 udelay(10);
768 }
769 for (i = 0x00; i < 0x0A; i++) {
770 value = b43_read16(dev, 0x050E);
771 if (value & 0x0400)
772 break;
773 udelay(10);
774 }
1d280ddc 775 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 776 value = b43_read16(dev, 0x0690);
777 if (!(value & 0x0100))
778 break;
779 udelay(10);
780 }
781 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
782 b43_radio_write16(dev, 0x0051, 0x0037);
783}
784
785static void key_write(struct b43_wldev *dev,
99da185a 786 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 787{
788 unsigned int i;
789 u32 offset;
790 u16 value;
791 u16 kidx;
792
793 /* Key index/algo block */
794 kidx = b43_kidx_to_fw(dev, index);
795 value = ((kidx << 4) | algorithm);
796 b43_shm_write16(dev, B43_SHM_SHARED,
797 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
798
799 /* Write the key to the Key Table Pointer offset */
800 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
801 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
802 value = key[i];
803 value |= (u16) (key[i + 1]) << 8;
804 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
805 }
806}
807
99da185a 808static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 809{
810 u32 addrtmp[2] = { 0, 0, };
66d2d089 811 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 812
813 if (b43_new_kidx_api(dev))
66d2d089 814 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 815
66d2d089
MB		 816 B43_WARN_ON(index < pairwise_keys_start);
817 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 818 * Physical mac 0 is mapped to physical key 4 or 8, depending
819 * on the firmware version.
820 * So we must adjust the index here.
821 */
66d2d089
MB		 822 index -= pairwise_keys_start;
823 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 824
825 if (addr) {
826 addrtmp[0] = addr[0];
827 addrtmp[0] |= ((u32) (addr[1]) << 8);
828 addrtmp[0] |= ((u32) (addr[2]) << 16);
829 addrtmp[0] |= ((u32) (addr[3]) << 24);
830 addrtmp[1] = addr[4];
831 addrtmp[1] |= ((u32) (addr[5]) << 8);
832 }
833
66d2d089
MB		 834 /* Receive match transmitter address (RCMTA) mechanism */
835 b43_shm_write32(dev, B43_SHM_RCMTA,
836 (index * 2) + 0, addrtmp[0]);
837 b43_shm_write16(dev, B43_SHM_RCMTA,
838 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 839}
840
035d0243 841/* The ucode will use phase1 key with TEK key to decrypt rx packets.
842 * When a packet is received, the iv32 is checked.
843 * - if it doesn't the packet is returned without modification (and software
844 * decryption can be done). That's what happen when iv16 wrap.
845 * - if it does, the rc4 key is computed, and decryption is tried.
846 * Either it will success and B43_RX_MAC_DEC is returned,
847 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
848 * and the packet is not usable (it got modified by the ucode).
849 * So in order to never have B43_RX_MAC_DECERR, we should provide
850 * a iv32 and phase1key that match. Because we drop packets in case of
851 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
852 * packets will be lost without higher layer knowing (ie no resync possible
853 * until next wrap).
854 *
855 * NOTE : this should support 50 key like RCMTA because
856 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
857 */
858static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
859 u16 *phase1key)
860{
861 unsigned int i;
862 u32 offset;
863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
864
865 if (!modparam_hwtkip)
866 return;
867
868 if (b43_new_kidx_api(dev))
869 pairwise_keys_start = B43_NR_GROUP_KEYS;
870
871 B43_WARN_ON(index < pairwise_keys_start);
872 /* We have four default TX keys and possibly four default RX keys.
873 * Physical mac 0 is mapped to physical key 4 or 8, depending
874 * on the firmware version.
875 * So we must adjust the index here.
876 */
877 index -= pairwise_keys_start;
878 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
879
880 if (b43_debug(dev, B43_DBG_KEYS)) {
881 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
882 index, iv32);
883 }
884 /* Write the key to the RX tkip shared mem */
885 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
886 for (i = 0; i < 10; i += 2) {
887 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
888 phase1key ? phase1key[i / 2] : 0);
889 }
890 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
892}
893
894static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 895 struct ieee80211_vif *vif,
896 struct ieee80211_key_conf *keyconf,
897 struct ieee80211_sta *sta,
898 u32 iv32, u16 *phase1key)
035d0243 899{
900 struct b43_wl *wl = hw_to_b43_wl(hw);
901 struct b43_wldev *dev;
902 int index = keyconf->hw_key_idx;
903
904 if (B43_WARN_ON(!modparam_hwtkip))
905 return;
906
96869a39
MB		 907 /* This is only called from the RX path through mac80211, where
908 * our mutex is already locked. */
909 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 910 dev = wl->current_dev;
96869a39 911 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 912
913 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
914
915 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 916 /* only pairwise TKIP keys are supported right now */
917 if (WARN_ON(!sta))
96869a39 918 return;
b3fbdcf4 919 keymac_write(dev, index, sta->addr);
035d0243 920}
921
e4d6b795
MB		 922static void do_key_write(struct b43_wldev *dev,
923 u8 index, u8 algorithm,
99da185a 924 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 925{
926 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 927 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 928
929 if (b43_new_kidx_api(dev))
66d2d089 930 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 931
66d2d089 932 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 933 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
934
66d2d089 935 if (index >= pairwise_keys_start)
e4d6b795 936 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 937 if (algorithm == B43_SEC_ALGO_TKIP) {
938 /*
939 * We should provide an initial iv32, phase1key pair.
940 * We could start with iv32=0 and compute the corresponding
941 * phase1key, but this means calling ieee80211_get_tkip_key
942 * with a fake skb (or export other tkip function).
943 * Because we are lazy we hope iv32 won't start with
944 * 0xffffffff and let's b43_op_update_tkip_key provide a
945 * correct pair.
946 */
947 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
948 } else if (index >= pairwise_keys_start) /* clear it */
949 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 950 if (key)
951 memcpy(buf, key, key_len);
952 key_write(dev, index, algorithm, buf);
66d2d089 953 if (index >= pairwise_keys_start)
e4d6b795
MB		 954 keymac_write(dev, index, mac_addr);
955
956 dev->key[index].algorithm = algorithm;
957}
958
959static int b43_key_write(struct b43_wldev *dev,
960 int index, u8 algorithm,
99da185a
JD		 961 const u8 *key, size_t key_len,
962 const u8 *mac_addr,
e4d6b795
MB		 963 struct ieee80211_key_conf *keyconf)
964{
965 int i;
66d2d089 966 int pairwise_keys_start;
e4d6b795 967
035d0243 968 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
969 * - Temporal Encryption Key (128 bits)
970 * - Temporal Authenticator Tx MIC Key (64 bits)
971 * - Temporal Authenticator Rx MIC Key (64 bits)
972 *
973 * Hardware only store TEK
974 */
975 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
976 key_len = 16;
e4d6b795
MB		 977 if (key_len > B43_SEC_KEYSIZE)
978 return -EINVAL;
66d2d089 979 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 980 /* Check that we don't already have this key. */
981 B43_WARN_ON(dev->key[i].keyconf == keyconf);
982 }
983 if (index < 0) {
e808e586 984 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 985 if (b43_new_kidx_api(dev))
66d2d089 986 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 987 else
66d2d089
MB		 988 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
989 for (i = pairwise_keys_start;
990 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
991 i++) {
992 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 993 if (!dev->key[i].keyconf) {
994 /* found empty */
995 index = i;
996 break;
997 }
998 }
999 if (index < 0) {
e808e586 1000 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1001 return -ENOSPC;
1002 }
1003 } else
1004 B43_WARN_ON(index > 3);
1005
1006 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1007 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1008 /* Default RX key */
1009 B43_WARN_ON(mac_addr);
1010 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1011 }
1012 keyconf->hw_key_idx = index;
1013 dev->key[index].keyconf = keyconf;
1014
1015 return 0;
1016}
1017
1018static int b43_key_clear(struct b43_wldev *dev, int index)
1019{
66d2d089 1020 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1021 return -EINVAL;
1022 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1023 NULL, B43_SEC_KEYSIZE, NULL);
1024 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1025 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1026 NULL, B43_SEC_KEYSIZE, NULL);
1027 }
1028 dev->key[index].keyconf = NULL;
1029
1030 return 0;
1031}
1032
1033static void b43_clear_keys(struct b43_wldev *dev)
1034{
66d2d089 1035 int i, count;
e4d6b795 1036
66d2d089
MB		 1037 if (b43_new_kidx_api(dev))
1038 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1039 else
1040 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1041 for (i = 0; i < count; i++)
e4d6b795
MB		 1042 b43_key_clear(dev, i);
1043}
1044
9cf7f247
MB		 1045static void b43_dump_keymemory(struct b43_wldev *dev)
1046{
66d2d089 1047 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1048 u8 mac[ETH_ALEN];
1049 u16 algo;
1050 u32 rcmta0;
1051 u16 rcmta1;
1052 u64 hf;
1053 struct b43_key *key;
1054
1055 if (!b43_debug(dev, B43_DBG_KEYS))
1056 return;
1057
1058 hf = b43_hf_read(dev);
1059 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1060 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1061 if (b43_new_kidx_api(dev)) {
1062 pairwise_keys_start = B43_NR_GROUP_KEYS;
1063 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1064 } else {
1065 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1066 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1067 }
1068 for (index = 0; index < count; index++) {
9cf7f247
MB		 1069 key = &(dev->key[index]);
1070 printk(KERN_DEBUG "Key slot %02u: %s",
1071 index, (key->keyconf == NULL) ? " " : "*");
1072 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1073 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1074 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1075 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1076 }
1077
1078 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1079 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1080 printk(" Algo: %04X/%02X", algo, key->algorithm);
1081
66d2d089 1082 if (index >= pairwise_keys_start) {
035d0243 1083 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1084 printk(" TKIP: ");
1085 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1086 for (i = 0; i < 14; i += 2) {
1087 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1088 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1089 }
1090 }
9cf7f247 1091 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1092 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1093 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1094 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1095 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1096 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1097 printk(" MAC: %pM", mac);
9cf7f247
MB		 1098 } else
1099 printk(" DEFAULT KEY");
1100 printk("\n");
1101 }
1102}
1103
e4d6b795
MB		 1104void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1105{
1106 u32 macctl;
1107 u16 ucstat;
1108 bool hwps;
1109 bool awake;
1110 int i;
1111
1112 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1113 (ps_flags & B43_PS_DISABLED));
1114 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1115
1116 if (ps_flags & B43_PS_ENABLED) {
1117 hwps = 1;
1118 } else if (ps_flags & B43_PS_DISABLED) {
1119 hwps = 0;
1120 } else {
1121 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1122 // and thus is not an AP and we are associated, set bit 25
1123 }
1124 if (ps_flags & B43_PS_AWAKE) {
1125 awake = 1;
1126 } else if (ps_flags & B43_PS_ASLEEP) {
1127 awake = 0;
1128 } else {
1129 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1130 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1131 // successful, set bit26
1132 }
1133
1134/* FIXME: For now we force awake-on and hwps-off */
1135 hwps = 0;
1136 awake = 1;
1137
1138 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1139 if (hwps)
1140 macctl |= B43_MACCTL_HWPS;
1141 else
1142 macctl &= ~B43_MACCTL_HWPS;
1143 if (awake)
1144 macctl |= B43_MACCTL_AWAKE;
1145 else
1146 macctl &= ~B43_MACCTL_AWAKE;
1147 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1148 /* Commit write */
1149 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1150 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1151 /* Wait for the microcode to wake up. */
1152 for (i = 0; i < 100; i++) {
1153 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1154 B43_SHM_SH_UCODESTAT);
1155 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1156 break;
1157 udelay(10);
1158 }
1159 }
1160}
1161
42c9a458 1162#ifdef CONFIG_B43_BCMA
49173592 1163static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1164{
49173592 1165 u32 flags;
42c9a458 1166
49173592
RM		 1167 /* Put PHY into reset */
1168 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1169 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1170 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1171 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1172 udelay(2);
1173
1174 /* Take PHY out of reset */
1175 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1176 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1177 flags |= BCMA_IOCTL_FGC;
1178 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1179 udelay(1);
1180
1181 /* Do not force clock anymore */
1182 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1183 flags &= ~BCMA_IOCTL_FGC;
1184 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1185 udelay(1);
1186}
42c9a458 1187
49173592
RM		 1188static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1189{
1190 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1191 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1192 b43_bcma_phy_reset(dev);
1193 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
42c9a458
RM		 1194}
1195#endif
1196
4da909e7 1197static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1198{
d48ae5c8 1199 struct ssb_device *sdev = dev->dev->sdev;
e4d6b795 1200 u32 tmslow;
4da909e7 1201 u32 flags = 0;
e4d6b795 1202
4da909e7
RM		 1203 if (gmode)
1204 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1205 flags |= B43_TMSLOW_PHYCLKEN;
1206 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1207 if (dev->phy.type == B43_PHYTYPE_N)
1208 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1209 b43_device_enable(dev, flags);
e4d6b795
MB		 1210 msleep(2); /* Wait for the PLL to turn on. */
1211
1212 /* Now take the PHY out of Reset again */
d48ae5c8 1213 tmslow = ssb_read32(sdev, SSB_TMSLOW);
e4d6b795
MB		 1214 tmslow |= SSB_TMSLOW_FGC;
1215 tmslow &= ~B43_TMSLOW_PHYRESET;
d48ae5c8
RM		 1216 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1217 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795
MB		 1218 msleep(1);
1219 tmslow &= ~SSB_TMSLOW_FGC;
d48ae5c8
RM		 1220 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1221 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795 1222 msleep(1);
1495298d
RM		 1223}
1224
4da909e7 1225void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1226{
1227 u32 macctl;
1228
6cbab0d9 1229 switch (dev->dev->bus_type) {
42c9a458
RM		 1230#ifdef CONFIG_B43_BCMA
1231 case B43_BUS_BCMA:
1232 b43_bcma_wireless_core_reset(dev, gmode);
1233 break;
1234#endif
6cbab0d9
RM		 1235#ifdef CONFIG_B43_SSB
1236 case B43_BUS_SSB:
1237 b43_ssb_wireless_core_reset(dev, gmode);
1238 break;
1239#endif
1240 }
e4d6b795 1241
fb11137a
MB		 1242 /* Turn Analog ON, but only if we already know the PHY-type.
1243 * This protects against very early setup where we don't know the
1244 * PHY-type, yet. wireless_core_reset will be called once again later,
1245 * when we know the PHY-type. */
1246 if (dev->phy.ops)
cb24f57f 1247 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1248
1249 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1250 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1251 if (gmode)
e4d6b795
MB		 1252 macctl |= B43_MACCTL_GMODE;
1253 macctl |= B43_MACCTL_IHR_ENABLED;
1254 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1255}
1256
1257static void handle_irq_transmit_status(struct b43_wldev *dev)
1258{
1259 u32 v0, v1;
1260 u16 tmp;
1261 struct b43_txstatus stat;
1262
1263 while (1) {
1264 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1265 if (!(v0 & 0x00000001))
1266 break;
1267 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1268
1269 stat.cookie = (v0 >> 16);
1270 stat.seq = (v1 & 0x0000FFFF);
1271 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1272 tmp = (v0 & 0x0000FFFF);
1273 stat.frame_count = ((tmp & 0xF000) >> 12);
1274 stat.rts_count = ((tmp & 0x0F00) >> 8);
1275 stat.supp_reason = ((tmp & 0x001C) >> 2);
1276 stat.pm_indicated = !!(tmp & 0x0080);
1277 stat.intermediate = !!(tmp & 0x0040);
1278 stat.for_ampdu = !!(tmp & 0x0020);
1279 stat.acked = !!(tmp & 0x0002);
1280
1281 b43_handle_txstatus(dev, &stat);
1282 }
1283}
1284
1285static void drain_txstatus_queue(struct b43_wldev *dev)
1286{
1287 u32 dummy;
1288
21d889d4 1289 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1290 return;
1291 /* Read all entries from the microcode TXstatus FIFO
1292 * and throw them away.
1293 */
1294 while (1) {
1295 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1296 if (!(dummy & 0x00000001))
1297 break;
1298 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1299 }
1300}
1301
1302static u32 b43_jssi_read(struct b43_wldev *dev)
1303{
1304 u32 val = 0;
1305
1306 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1307 val <<= 16;
1308 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1309
1310 return val;
1311}
1312
1313static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1314{
1315 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1317}
1318
1319static void b43_generate_noise_sample(struct b43_wldev *dev)
1320{
1321 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1322 b43_write32(dev, B43_MMIO_MACCMD,
1323 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1324}
1325
1326static void b43_calculate_link_quality(struct b43_wldev *dev)
1327{
1328 /* Top half of Link Quality calculation. */
1329
ef1a628d
MB		 1330 if (dev->phy.type != B43_PHYTYPE_G)
1331 return;
e4d6b795
MB		 1332 if (dev->noisecalc.calculation_running)
1333 return;
e4d6b795
MB		 1334 dev->noisecalc.calculation_running = 1;
1335 dev->noisecalc.nr_samples = 0;
1336
1337 b43_generate_noise_sample(dev);
1338}
1339
1340static void handle_irq_noise(struct b43_wldev *dev)
1341{
ef1a628d 1342 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1343 u16 tmp;
1344 u8 noise[4];
1345 u8 i, j;
1346 s32 average;
1347
1348 /* Bottom half of Link Quality calculation. */
1349
ef1a628d
MB		 1350 if (dev->phy.type != B43_PHYTYPE_G)
1351 return;
1352
98a3b2fe
MB		 1353 /* Possible race condition: It might be possible that the user
1354 * changed to a different channel in the meantime since we
1355 * started the calculation. We ignore that fact, since it's
1356 * not really that much of a problem. The background noise is
1357 * an estimation only anyway. Slightly wrong results will get damped
1358 * by the averaging of the 8 sample rounds. Additionally the
1359 * value is shortlived. So it will be replaced by the next noise
1360 * calculation round soon. */
1361
e4d6b795 1362 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1363 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1364 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1365 noise[2] == 0x7F || noise[3] == 0x7F)
1366 goto generate_new;
1367
1368 /* Get the noise samples. */
1369 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1370 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1371 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1372 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1373 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1375 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1376 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1377 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1378 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1379 dev->noisecalc.nr_samples++;
1380 if (dev->noisecalc.nr_samples == 8) {
1381 /* Calculate the Link Quality by the noise samples. */
1382 average = 0;
1383 for (i = 0; i < 8; i++) {
1384 for (j = 0; j < 4; j++)
1385 average += dev->noisecalc.samples[i][j];
1386 }
1387 average /= (8 * 4);
1388 average *= 125;
1389 average += 64;
1390 average /= 128;
1391 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1392 tmp = (tmp / 128) & 0x1F;
1393 if (tmp >= 8)
1394 average += 2;
1395 else
1396 average -= 25;
1397 if (tmp == 8)
1398 average -= 72;
1399 else
1400 average -= 48;
1401
1402 dev->stats.link_noise = average;
e4d6b795
MB		 1403 dev->noisecalc.calculation_running = 0;
1404 return;
1405 }
98a3b2fe 1406generate_new:
e4d6b795
MB		 1407 b43_generate_noise_sample(dev);
1408}
1409
1410static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1411{
05c914fe 1412 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1413 ///TODO: PS TBTT
1414 } else {
1415 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1416 b43_power_saving_ctl_bits(dev, 0);
1417 }
05c914fe 1418 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1419 dev->dfq_valid = 1;
e4d6b795
MB		 1420}
1421
1422static void handle_irq_atim_end(struct b43_wldev *dev)
1423{
aa6c7ae2
MB		 1424 if (dev->dfq_valid) {
1425 b43_write32(dev, B43_MMIO_MACCMD,
1426 b43_read32(dev, B43_MMIO_MACCMD)
1427 | B43_MACCMD_DFQ_VALID);
1428 dev->dfq_valid = 0;
1429 }
e4d6b795
MB		 1430}
1431
1432static void handle_irq_pmq(struct b43_wldev *dev)
1433{
1434 u32 tmp;
1435
1436 //TODO: AP mode.
1437
1438 while (1) {
1439 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1440 if (!(tmp & 0x00000008))
1441 break;
1442 }
1443 /* 16bit write is odd, but correct. */
1444 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1445}
1446
1447static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1448 const u8 *data, u16 size,
e4d6b795
MB		 1449 u16 ram_offset,
1450 u16 shm_size_offset, u8 rate)
1451{
1452 u32 i, tmp;
1453 struct b43_plcp_hdr4 plcp;
1454
1455 plcp.data = 0;
1456 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1457 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1458 ram_offset += sizeof(u32);
1459 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1460 * So leave the first two bytes of the next write blank.
1461 */
1462 tmp = (u32) (data[0]) << 16;
1463 tmp |= (u32) (data[1]) << 24;
1464 b43_ram_write(dev, ram_offset, tmp);
1465 ram_offset += sizeof(u32);
1466 for (i = 2; i < size; i += sizeof(u32)) {
1467 tmp = (u32) (data[i + 0]);
1468 if (i + 1 < size)
1469 tmp |= (u32) (data[i + 1]) << 8;
1470 if (i + 2 < size)
1471 tmp |= (u32) (data[i + 2]) << 16;
1472 if (i + 3 < size)
1473 tmp |= (u32) (data[i + 3]) << 24;
1474 b43_ram_write(dev, ram_offset + i - 2, tmp);
1475 }
1476 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1477 size + sizeof(struct b43_plcp_hdr6));
1478}
1479
5042c507
MB		 1480/* Check if the use of the antenna that ieee80211 told us to
1481 * use is possible. This will fall back to DEFAULT.
1482 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1483u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1484 u8 antenna_nr)
1485{
1486 u8 antenna_mask;
1487
1488 if (antenna_nr == 0) {
1489 /* Zero means "use default antenna". That's always OK. */
1490 return 0;
1491 }
1492
1493 /* Get the mask of available antennas. */
1494 if (dev->phy.gmode)
0581483a 1495 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1496 else
0581483a 1497 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1498
1499 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1500 /* This antenna is not available. Fall back to default. */
1501 return 0;
1502 }
1503
1504 return antenna_nr;
1505}
1506
5042c507
MB		 1507/* Convert a b43 antenna number value to the PHY TX control value. */
1508static u16 b43_antenna_to_phyctl(int antenna)
1509{
1510 switch (antenna) {
1511 case B43_ANTENNA0:
1512 return B43_TXH_PHY_ANT0;
1513 case B43_ANTENNA1:
1514 return B43_TXH_PHY_ANT1;
1515 case B43_ANTENNA2:
1516 return B43_TXH_PHY_ANT2;
1517 case B43_ANTENNA3:
1518 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1519 case B43_ANTENNA_AUTO0:
1520 case B43_ANTENNA_AUTO1:
5042c507
MB		 1521 return B43_TXH_PHY_ANT01AUTO;
1522 }
1523 B43_WARN_ON(1);
1524 return 0;
1525}
1526
e4d6b795
MB		 1527static void b43_write_beacon_template(struct b43_wldev *dev,
1528 u16 ram_offset,
5042c507 1529 u16 shm_size_offset)
e4d6b795 1530{
47f76ca3 1531 unsigned int i, len, variable_len;
e66fee6a
MB		 1532 const struct ieee80211_mgmt *bcn;
1533 const u8 *ie;
1534 bool tim_found = 0;
5042c507
MB		 1535 unsigned int rate;
1536 u16 ctl;
1537 int antenna;
e039fa4a 1538 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1539
e66fee6a
MB		 1540 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1541 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1542 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1543 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1544
1545 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1546 len, ram_offset, shm_size_offset, rate);
e66fee6a 1547
5042c507 1548 /* Write the PHY TX control parameters. */
0f4ac38b 1549 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1550 antenna = b43_antenna_to_phyctl(antenna);
1551 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1552 /* We can't send beacons with short preamble. Would get PHY errors. */
1553 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1554 ctl &= ~B43_TXH_PHY_ANT;
1555 ctl &= ~B43_TXH_PHY_ENC;
1556 ctl |= antenna;
1557 if (b43_is_cck_rate(rate))
1558 ctl |= B43_TXH_PHY_ENC_CCK;
1559 else
1560 ctl |= B43_TXH_PHY_ENC_OFDM;
1561 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1562
e66fee6a
MB		 1563 /* Find the position of the TIM and the DTIM_period value
1564 * and write them to SHM. */
1565 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1566 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1567 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1568 uint8_t ie_id, ie_len;
1569
1570 ie_id = ie[i];
1571 ie_len = ie[i + 1];
1572 if (ie_id == 5) {
1573 u16 tim_position;
1574 u16 dtim_period;
1575 /* This is the TIM Information Element */
1576
1577 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1578 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1579 break;
1580 /* A valid TIM is at least 4 bytes long. */
1581 if (ie_len < 4)
1582 break;
1583 tim_found = 1;
1584
1585 tim_position = sizeof(struct b43_plcp_hdr6);
1586 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1587 tim_position += i;
1588
1589 dtim_period = ie[i + 3];
1590
1591 b43_shm_write16(dev, B43_SHM_SHARED,
1592 B43_SHM_SH_TIMBPOS, tim_position);
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_DTIMPER, dtim_period);
1595 break;
1596 }
1597 i += ie_len + 2;
1598 }
1599 if (!tim_found) {
04dea136
JB		 1600 /*
1601 * If ucode wants to modify TIM do it behind the beacon, this
1602 * will happen, for example, when doing mesh networking.
1603 */
1604 b43_shm_write16(dev, B43_SHM_SHARED,
1605 B43_SHM_SH_TIMBPOS,
1606 len + sizeof(struct b43_plcp_hdr6));
1607 b43_shm_write16(dev, B43_SHM_SHARED,
1608 B43_SHM_SH_DTIMPER, 0);
1609 }
1610 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1611}
1612
6b4bec01
MB		 1613static void b43_upload_beacon0(struct b43_wldev *dev)
1614{
1615 struct b43_wl *wl = dev->wl;
1616
1617 if (wl->beacon0_uploaded)
1618 return;
1619 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1620 wl->beacon0_uploaded = 1;
1621}
1622
1623static void b43_upload_beacon1(struct b43_wldev *dev)
1624{
1625 struct b43_wl *wl = dev->wl;
1626
1627 if (wl->beacon1_uploaded)
1628 return;
1629 b43_write_beacon_template(dev, 0x468, 0x1A);
1630 wl->beacon1_uploaded = 1;
1631}
1632
c97a4ccc
MB		 1633static void handle_irq_beacon(struct b43_wldev *dev)
1634{
1635 struct b43_wl *wl = dev->wl;
1636 u32 cmd, beacon0_valid, beacon1_valid;
1637
05c914fe
JB		 1638 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1639 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1640 return;
1641
1642 /* This is the bottom half of the asynchronous beacon update. */
1643
1644 /* Ignore interrupt in the future. */
13790728 1645 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1646
1647 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1648 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1649 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1650
1651 /* Schedule interrupt manually, if busy. */
1652 if (beacon0_valid && beacon1_valid) {
1653 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1654 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1655 return;
1656 }
1657
6b4bec01
MB		 1658 if (unlikely(wl->beacon_templates_virgin)) {
1659 /* We never uploaded a beacon before.
1660 * Upload both templates now, but only mark one valid. */
1661 wl->beacon_templates_virgin = 0;
1662 b43_upload_beacon0(dev);
1663 b43_upload_beacon1(dev);
c97a4ccc
MB		 1664 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1665 cmd |= B43_MACCMD_BEACON0_VALID;
1666 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1667 } else {
1668 if (!beacon0_valid) {
1669 b43_upload_beacon0(dev);
1670 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1671 cmd |= B43_MACCMD_BEACON0_VALID;
1672 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1673 } else if (!beacon1_valid) {
1674 b43_upload_beacon1(dev);
1675 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1676 cmd |= B43_MACCMD_BEACON1_VALID;
1677 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1678 }
c97a4ccc
MB		 1679 }
1680}
1681
36dbd954
MB		 1682static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1683{
1684 u32 old_irq_mask = dev->irq_mask;
1685
1686 /* update beacon right away or defer to irq */
1687 handle_irq_beacon(dev);
1688 if (old_irq_mask != dev->irq_mask) {
1689 /* The handler updated the IRQ mask. */
1690 B43_WARN_ON(!dev->irq_mask);
1691 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1692 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1693 } else {
1694 /* Device interrupts are currently disabled. That means
1695 * we just ran the hardirq handler and scheduled the
1696 * IRQ thread. The thread will write the IRQ mask when
1697 * it finished, so there's nothing to do here. Writing
1698 * the mask _here_ would incorrectly re-enable IRQs. */
1699 }
1700 }
1701}
1702
a82d9922
MB		 1703static void b43_beacon_update_trigger_work(struct work_struct *work)
1704{
1705 struct b43_wl *wl = container_of(work, struct b43_wl,
1706 beacon_update_trigger);
1707 struct b43_wldev *dev;
1708
1709 mutex_lock(&wl->mutex);
1710 dev = wl->current_dev;
1711 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1712 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1713 /* wl->mutex is enough. */
1714 b43_do_beacon_update_trigger_work(dev);
1715 mmiowb();
1716 } else {
1717 spin_lock_irq(&wl->hardirq_lock);
1718 b43_do_beacon_update_trigger_work(dev);
1719 mmiowb();
1720 spin_unlock_irq(&wl->hardirq_lock);
1721 }
a82d9922
MB		 1722 }
1723 mutex_unlock(&wl->mutex);
1724}
1725
d4df6f1a 1726/* Asynchronously update the packet templates in template RAM.
36dbd954 1727 * Locking: Requires wl->mutex to be locked. */
9d139c81 1728static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1729{
9d139c81
JB		 1730 struct sk_buff *beacon;
1731
e66fee6a
MB		 1732 /* This is the top half of the ansynchronous beacon update.
1733 * The bottom half is the beacon IRQ.
1734 * Beacon update must be asynchronous to avoid sending an
1735 * invalid beacon. This can happen for example, if the firmware
1736 * transmits a beacon while we are updating it. */
e4d6b795 1737
9d139c81
JB		 1738 /* We could modify the existing beacon and set the aid bit in
1739 * the TIM field, but that would probably require resizing and
1740 * moving of data within the beacon template.
1741 * Simply request a new beacon and let mac80211 do the hard work. */
1742 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1743 if (unlikely(!beacon))
1744 return;
1745
e66fee6a
MB		 1746 if (wl->current_beacon)
1747 dev_kfree_skb_any(wl->current_beacon);
1748 wl->current_beacon = beacon;
1749 wl->beacon0_uploaded = 0;
1750 wl->beacon1_uploaded = 0;
42935eca 1751 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1752}
1753
e4d6b795
MB		 1754static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1755{
1756 b43_time_lock(dev);
21d889d4 1757 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1758 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1759 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1760 } else {
1761 b43_write16(dev, 0x606, (beacon_int >> 6));
1762 b43_write16(dev, 0x610, beacon_int);
1763 }
1764 b43_time_unlock(dev);
a82d9922 1765 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1766}
1767
afa83e23
MB		 1768static void b43_handle_firmware_panic(struct b43_wldev *dev)
1769{
1770 u16 reason;
1771
1772 /* Read the register that contains the reason code for the panic. */
1773 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1774 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1775
1776 switch (reason) {
1777 default:
1778 b43dbg(dev->wl, "The panic reason is unknown.\n");
1779 /* fallthrough */
1780 case B43_FWPANIC_DIE:
1781 /* Do not restart the controller or firmware.
1782 * The device is nonfunctional from now on.
1783 * Restarting would result in this panic to trigger again,
1784 * so we avoid that recursion. */
1785 break;
1786 case B43_FWPANIC_RESTART:
1787 b43_controller_restart(dev, "Microcode panic");
1788 break;
1789 }
1790}
1791
e4d6b795
MB		 1792static void handle_irq_ucode_debug(struct b43_wldev *dev)
1793{
e48b0eeb 1794 unsigned int i, cnt;
53c06856 1795 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1796 __le16 *buf;
1797
1798 /* The proprietary firmware doesn't have this IRQ. */
1799 if (!dev->fw.opensource)
1800 return;
1801
afa83e23
MB		 1802 /* Read the register that contains the reason code for this IRQ. */
1803 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1804
e48b0eeb
MB		 1805 switch (reason) {
1806 case B43_DEBUGIRQ_PANIC:
afa83e23 1807 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1808 break;
1809 case B43_DEBUGIRQ_DUMP_SHM:
1810 if (!B43_DEBUG)
1811 break; /* Only with driver debugging enabled. */
1812 buf = kmalloc(4096, GFP_ATOMIC);
1813 if (!buf) {
1814 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1815 goto out;
1816 }
1817 for (i = 0; i < 4096; i += 2) {
1818 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1819 buf[i / 2] = cpu_to_le16(tmp);
1820 }
1821 b43info(dev->wl, "Shared memory dump:\n");
1822 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1823 16, 2, buf, 4096, 1);
1824 kfree(buf);
1825 break;
1826 case B43_DEBUGIRQ_DUMP_REGS:
1827 if (!B43_DEBUG)
1828 break; /* Only with driver debugging enabled. */
1829 b43info(dev->wl, "Microcode register dump:\n");
1830 for (i = 0, cnt = 0; i < 64; i++) {
1831 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1832 if (cnt == 0)
1833 printk(KERN_INFO);
1834 printk("r%02u: 0x%04X ", i, tmp);
1835 cnt++;
1836 if (cnt == 6) {
1837 printk("\n");
1838 cnt = 0;
1839 }
1840 }
1841 printk("\n");
1842 break;
53c06856
MB		 1843 case B43_DEBUGIRQ_MARKER:
1844 if (!B43_DEBUG)
1845 break; /* Only with driver debugging enabled. */
1846 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1847 B43_MARKER_ID_REG);
1848 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1849 B43_MARKER_LINE_REG);
1850 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1851 "at line number %u\n",
1852 marker_id, marker_line);
1853 break;
e48b0eeb
MB		 1854 default:
1855 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1856 reason);
1857 }
1858out:
afa83e23
MB		 1859 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1860 b43_shm_write16(dev, B43_SHM_SCRATCH,
1861 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1862}
1863
36dbd954 1864static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1865{
1866 u32 reason;
1867 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1868 u32 merged_dma_reason = 0;
21954c36 1869 int i;
e4d6b795 1870
36dbd954
MB		 1871 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1872 return;
e4d6b795
MB		 1873
1874 reason = dev->irq_reason;
1875 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1876 dma_reason[i] = dev->dma_reason[i];
1877 merged_dma_reason |= dma_reason[i];
1878 }
1879
1880 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1881 b43err(dev->wl, "MAC transmission error\n");
1882
00e0b8cb 1883 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1884 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1885 rmb();
1886 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1887 atomic_set(&dev->phy.txerr_cnt,
1888 B43_PHY_TX_BADNESS_LIMIT);
1889 b43err(dev->wl, "Too many PHY TX errors, "
1890 "restarting the controller\n");
1891 b43_controller_restart(dev, "PHY TX errors");
1892 }
1893 }
e4d6b795
MB		 1894
1895 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1896 B43_DMAIRQ_NONFATALMASK))) {
1897 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1898 b43err(dev->wl, "Fatal DMA error: "
1899 "0x%08X, 0x%08X, 0x%08X, "
1900 "0x%08X, 0x%08X, 0x%08X\n",
1901 dma_reason[0], dma_reason[1],
1902 dma_reason[2], dma_reason[3],
1903 dma_reason[4], dma_reason[5]);
214ac9a4 1904 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1905 "on your system. It will now be switched to PIO.\n");
9e3bd919
LT		 1906 /* Fall back to PIO transfers if we get fatal DMA errors! */
1907 dev->use_pio = 1;
1908 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1909 return;
1910 }
1911 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1912 b43err(dev->wl, "DMA error: "
1913 "0x%08X, 0x%08X, 0x%08X, "
1914 "0x%08X, 0x%08X, 0x%08X\n",
1915 dma_reason[0], dma_reason[1],
1916 dma_reason[2], dma_reason[3],
1917 dma_reason[4], dma_reason[5]);
1918 }
1919 }
1920
1921 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1922 handle_irq_ucode_debug(dev);
1923 if (reason & B43_IRQ_TBTT_INDI)
1924 handle_irq_tbtt_indication(dev);
1925 if (reason & B43_IRQ_ATIM_END)
1926 handle_irq_atim_end(dev);
1927 if (reason & B43_IRQ_BEACON)
1928 handle_irq_beacon(dev);
1929 if (reason & B43_IRQ_PMQ)
1930 handle_irq_pmq(dev);
21954c36
MB		 1931 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1932 ;/* TODO */
1933 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1934 handle_irq_noise(dev);
1935
1936 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1937 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1938 if (b43_using_pio_transfers(dev))
1939 b43_pio_rx(dev->pio.rx_queue);
1940 else
1941 b43_dma_rx(dev->dma.rx_ring);
1942 }
e4d6b795
MB		 1943 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1944 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1945 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1946 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1948
21954c36 1949 if (reason & B43_IRQ_TX_OK)
e4d6b795 1950 handle_irq_transmit_status(dev);
e4d6b795 1951
36dbd954 1952 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1953 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1954
1955#if B43_DEBUG
1956 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1957 dev->irq_count++;
1958 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1959 if (reason & (1 << i))
1960 dev->irq_bit_count[i]++;
1961 }
1962 }
1963#endif
e4d6b795
MB		 1964}
1965
36dbd954
MB		 1966/* Interrupt thread handler. Handles device interrupts in thread context. */
1967static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1968{
36dbd954 1969 struct b43_wldev *dev = dev_id;
e4d6b795 1970
36dbd954
MB		 1971 mutex_lock(&dev->wl->mutex);
1972 b43_do_interrupt_thread(dev);
1973 mmiowb();
1974 mutex_unlock(&dev->wl->mutex);
1975
1976 return IRQ_HANDLED;
e4d6b795
MB		 1977}
1978
36dbd954 1979static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1980{
e4d6b795
MB		 1981 u32 reason;
1982
36dbd954
MB		 1983 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1984 * On SDIO, this runs under wl->mutex. */
e4d6b795 1985
e4d6b795
MB		 1986 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1987 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1988 return IRQ_NONE;
13790728 1989 reason &= dev->irq_mask;
e4d6b795 1990 if (!reason)
cae56147 1991 return IRQ_NONE;
e4d6b795
MB		 1992
1993 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1994 & 0x0001DC00;
1995 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1996 & 0x0000DC00;
1997 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1998 & 0x0000DC00;
1999 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2000 & 0x0001DC00;
2001 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2002 & 0x0000DC00;
13790728 2003/* Unused ring
e4d6b795
MB		 2004 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2005 & 0x0000DC00;
13790728 2006*/
e4d6b795 2007
36dbd954
MB		 2008 /* ACK the interrupt. */
2009 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2010 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2011 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2012 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2013 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2014 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2015/* Unused ring
2016 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2017*/
2018
2019 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2020 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2021 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2022 dev->irq_reason = reason;
36dbd954
MB		 2023
2024 return IRQ_WAKE_THREAD;
2025}
2026
2027/* Interrupt handler top-half. This runs with interrupts disabled. */
2028static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2029{
2030 struct b43_wldev *dev = dev_id;
2031 irqreturn_t ret;
2032
2033 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2034 return IRQ_NONE;
2035
2036 spin_lock(&dev->wl->hardirq_lock);
2037 ret = b43_do_interrupt(dev);
e4d6b795 2038 mmiowb();
36dbd954 2039 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2040
2041 return ret;
2042}
2043
3dbba8e2
AH		 2044/* SDIO interrupt handler. This runs in process context. */
2045static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2046{
2047 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2048 irqreturn_t ret;
2049
3dbba8e2 2050 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2051
2052 ret = b43_do_interrupt(dev);
2053 if (ret == IRQ_WAKE_THREAD)
2054 b43_do_interrupt_thread(dev);
2055
3dbba8e2
AH		 2056 mutex_unlock(&wl->mutex);
2057}
2058
1a9f5093 2059void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2060{
2061 release_firmware(fw->data);
2062 fw->data = NULL;
2063 fw->filename = NULL;
2064}
2065
e4d6b795
MB		 2066static void b43_release_firmware(struct b43_wldev *dev)
2067{
1a9f5093
MB		 2068 b43_do_release_fw(&dev->fw.ucode);
2069 b43_do_release_fw(&dev->fw.pcm);
2070 b43_do_release_fw(&dev->fw.initvals);
2071 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2072}
2073
eb189d8b 2074static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2075{
fc68ed4f
HE		 2076 const char text[] =
2077 "You must go to " \
2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2079 "and download the correct firmware for this driver version. " \
2080 "Please carefully read all instructions on this website.\n";
eb189d8b 2081
eb189d8b
MB		 2082 if (error)
2083 b43err(wl, text);
2084 else
2085 b43warn(wl, text);
e4d6b795
MB		 2086}
2087
1a9f5093
MB		 2088int b43_do_request_fw(struct b43_request_fw_context *ctx,
2089 const char *name,
2090 struct b43_firmware_file *fw)
e4d6b795 2091{
61cb5dd6 2092 const struct firmware *blob;
e4d6b795
MB		 2093 struct b43_fw_header *hdr;
2094 u32 size;
2095 int err;
2096
61cb5dd6
MB		 2097 if (!name) {
2098 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2099 /* FIXME: We should probably keep it anyway, to save some headache
2100 * on suspend/resume with multiband devices. */
2101 b43_do_release_fw(fw);
e4d6b795 2102 return 0;
61cb5dd6
MB		 2103 }
2104 if (fw->filename) {
1a9f5093
MB		 2105 if ((fw->type == ctx->req_type) &&
2106 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2107 return 0; /* Already have this fw. */
2108 /* Free the cached firmware first. */
1a9f5093
MB		 2109 /* FIXME: We should probably do this later after we successfully
2110 * got the new fw. This could reduce headache with multiband devices.
2111 * We could also redesign this to cache the firmware for all possible
2112 * bands all the time. */
2113 b43_do_release_fw(fw);
61cb5dd6 2114 }
e4d6b795 2115
1a9f5093
MB		 2116 switch (ctx->req_type) {
2117 case B43_FWTYPE_PROPRIETARY:
2118 snprintf(ctx->fwname, sizeof(ctx->fwname),
2119 "b43%s/%s.fw",
2120 modparam_fwpostfix, name);
2121 break;
2122 case B43_FWTYPE_OPENSOURCE:
2123 snprintf(ctx->fwname, sizeof(ctx->fwname),
2124 "b43-open%s/%s.fw",
2125 modparam_fwpostfix, name);
2126 break;
2127 default:
2128 B43_WARN_ON(1);
2129 return -ENOSYS;
2130 }
a18c715e 2131 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2132 if (err == -ENOENT) {
1a9f5093
MB		 2133 snprintf(ctx->errors[ctx->req_type],
2134 sizeof(ctx->errors[ctx->req_type]),
2135 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2136 return err;
2137 } else if (err) {
1a9f5093
MB		 2138 snprintf(ctx->errors[ctx->req_type],
2139 sizeof(ctx->errors[ctx->req_type]),
2140 "Firmware file \"%s\" request failed (err=%d)\n",
2141 ctx->fwname, err);
e4d6b795
MB		 2142 return err;
2143 }
61cb5dd6 2144 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2145 goto err_format;
61cb5dd6 2146 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2147 switch (hdr->type) {
2148 case B43_FW_TYPE_UCODE:
2149 case B43_FW_TYPE_PCM:
2150 size = be32_to_cpu(hdr->size);
61cb5dd6 2151 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2152 goto err_format;
2153 /* fallthrough */
2154 case B43_FW_TYPE_IV:
2155 if (hdr->ver != 1)
2156 goto err_format;
2157 break;
2158 default:
2159 goto err_format;
2160 }
2161
61cb5dd6
MB		 2162 fw->data = blob;
2163 fw->filename = name;
1a9f5093 2164 fw->type = ctx->req_type;
61cb5dd6
MB		 2165
2166 return 0;
e4d6b795
MB		 2167
2168err_format:
1a9f5093
MB		 2169 snprintf(ctx->errors[ctx->req_type],
2170 sizeof(ctx->errors[ctx->req_type]),
2171 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2172 release_firmware(blob);
2173
e4d6b795
MB		 2174 return -EPROTO;
2175}
2176
1a9f5093 2177static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2178{
1a9f5093
MB		 2179 struct b43_wldev *dev = ctx->dev;
2180 struct b43_firmware *fw = &ctx->dev->fw;
21d889d4 2181 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795
MB		 2182 const char *filename;
2183 u32 tmshigh;
2184 int err;
2185
8b9bda75
RM		 2186 /* Files for HT and LCN were found by trying one by one */
2187
61cb5dd6 2188 /* Get microcode */
6ff1e5cf 2189 if ((rev >= 5) && (rev <= 10)) {
61cb5dd6 2190 filename = "ucode5";
6ff1e5cf 2191 } else if ((rev >= 11) && (rev <= 12)) {
61cb5dd6 2192 filename = "ucode11";
6ff1e5cf 2193 } else if (rev == 13) {
61cb5dd6 2194 filename = "ucode13";
6ff1e5cf 2195 } else if (rev == 14) {
759b973b 2196 filename = "ucode14";
6ff1e5cf 2197 } else if (rev == 15) {
759b973b 2198 filename = "ucode15";
6ff1e5cf
RM		 2199 } else {
2200 switch (dev->phy.type) {
2201 case B43_PHYTYPE_N:
2202 if (rev >= 16)
2203 filename = "ucode16_mimo";
2204 else
2205 goto err_no_ucode;
2206 break;
8b9bda75
RM		 2207 case B43_PHYTYPE_HT:
2208 if (rev == 29)
2209 filename = "ucode29_mimo";
2210 else
2211 goto err_no_ucode;
2212 break;
2213 case B43_PHYTYPE_LCN:
2214 if (rev == 24)
2215 filename = "ucode24_mimo";
2216 else
2217 goto err_no_ucode;
2218 break;
6ff1e5cf
RM		 2219 default:
2220 goto err_no_ucode;
2221 }
2222 }
1a9f5093 2223 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2224 if (err)
2225 goto err_load;
2226
2227 /* Get PCM code */
2228 if ((rev >= 5) && (rev <= 10))
2229 filename = "pcm5";
2230 else if (rev >= 11)
2231 filename = NULL;
2232 else
2233 goto err_no_pcm;
68217832 2234 fw->pcm_request_failed = 0;
1a9f5093 2235 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2236 if (err == -ENOENT) {
2237 /* We did not find a PCM file? Not fatal, but
2238 * core rev <= 10 must do without hwcrypto then. */
2239 fw->pcm_request_failed = 1;
2240 } else if (err)
61cb5dd6
MB		 2241 goto err_load;
2242
2243 /* Get initvals */
2244 switch (dev->phy.type) {
2245 case B43_PHYTYPE_A:
2246 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2247 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2248 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2249 filename = "a0g1initvals5";
2250 else
2251 filename = "a0g0initvals5";
2252 } else
2253 goto err_no_initvals;
2254 break;
2255 case B43_PHYTYPE_G:
e4d6b795 2256 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2257 filename = "b0g0initvals5";
e4d6b795 2258 else if (rev >= 13)
e9304882 2259 filename = "b0g0initvals13";
e4d6b795 2260 else
61cb5dd6
MB		 2261 goto err_no_initvals;
2262 break;
2263 case B43_PHYTYPE_N:
e41596a1
RM		 2264 if (rev >= 16)
2265 filename = "n0initvals16";
2266 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2267 filename = "n0initvals11";
2268 else
2269 goto err_no_initvals;
2270 break;
759b973b
GS		 2271 case B43_PHYTYPE_LP:
2272 if (rev == 13)
2273 filename = "lp0initvals13";
2274 else if (rev == 14)
2275 filename = "lp0initvals14";
2276 else if (rev >= 15)
2277 filename = "lp0initvals15";
2278 else
2279 goto err_no_initvals;
2280 break;
8b9bda75
RM		 2281 case B43_PHYTYPE_HT:
2282 if (rev == 29)
2283 filename = "ht0initvals29";
2284 else
2285 goto err_no_initvals;
2286 break;
2287 case B43_PHYTYPE_LCN:
2288 if (rev == 24)
2289 filename = "lcn0initvals24";
2290 else
2291 goto err_no_initvals;
2292 break;
61cb5dd6
MB		 2293 default:
2294 goto err_no_initvals;
e4d6b795 2295 }
1a9f5093 2296 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2297 if (err)
2298 goto err_load;
2299
2300 /* Get bandswitch initvals */
2301 switch (dev->phy.type) {
2302 case B43_PHYTYPE_A:
2303 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2304 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2305 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2306 filename = "a0g1bsinitvals5";
2307 else
2308 filename = "a0g0bsinitvals5";
2309 } else if (rev >= 11)
2310 filename = NULL;
2311 else
2312 goto err_no_initvals;
2313 break;
2314 case B43_PHYTYPE_G:
e4d6b795 2315 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2316 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2317 else if (rev >= 11)
2318 filename = NULL;
2319 else
e4d6b795 2320 goto err_no_initvals;
61cb5dd6
MB		 2321 break;
2322 case B43_PHYTYPE_N:
e41596a1
RM		 2323 if (rev >= 16)
2324 filename = "n0bsinitvals16";
2325 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2326 filename = "n0bsinitvals11";
2327 else
e4d6b795 2328 goto err_no_initvals;
61cb5dd6 2329 break;
759b973b
GS		 2330 case B43_PHYTYPE_LP:
2331 if (rev == 13)
2332 filename = "lp0bsinitvals13";
2333 else if (rev == 14)
2334 filename = "lp0bsinitvals14";
2335 else if (rev >= 15)
2336 filename = "lp0bsinitvals15";
2337 else
2338 goto err_no_initvals;
2339 break;
8b9bda75
RM		 2340 case B43_PHYTYPE_HT:
2341 if (rev == 29)
2342 filename = "ht0bsinitvals29";
2343 else
2344 goto err_no_initvals;
2345 break;
2346 case B43_PHYTYPE_LCN:
2347 if (rev == 24)
2348 filename = "lcn0bsinitvals24";
2349 else
2350 goto err_no_initvals;
2351 break;
61cb5dd6
MB		 2352 default:
2353 goto err_no_initvals;
e4d6b795 2354 }
1a9f5093 2355 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2356 if (err)
2357 goto err_load;
e4d6b795
MB		 2358
2359 return 0;
2360
e4d6b795 2361err_no_ucode:
1a9f5093
MB		 2362 err = ctx->fatal_failure = -EOPNOTSUPP;
2363 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2364 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2365 goto error;
2366
2367err_no_pcm:
1a9f5093
MB		 2368 err = ctx->fatal_failure = -EOPNOTSUPP;
2369 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2370 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2371 goto error;
2372
2373err_no_initvals:
1a9f5093
MB		 2374 err = ctx->fatal_failure = -EOPNOTSUPP;
2375 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2376 "is required for your device (wl-core rev %u)\n", rev);
2377 goto error;
2378
2379err_load:
2380 /* We failed to load this firmware image. The error message
2381 * already is in ctx->errors. Return and let our caller decide
2382 * what to do. */
e4d6b795
MB		 2383 goto error;
2384
2385error:
2386 b43_release_firmware(dev);
2387 return err;
2388}
2389
1a9f5093
MB		 2390static int b43_request_firmware(struct b43_wldev *dev)
2391{
2392 struct b43_request_fw_context *ctx;
2393 unsigned int i;
2394 int err;
2395 const char *errmsg;
2396
2397 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2398 if (!ctx)
2399 return -ENOMEM;
2400 ctx->dev = dev;
2401
2402 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2403 err = b43_try_request_fw(ctx);
2404 if (!err)
2405 goto out; /* Successfully loaded it. */
2406 err = ctx->fatal_failure;
2407 if (err)
2408 goto out;
2409
2410 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2411 err = b43_try_request_fw(ctx);
2412 if (!err)
2413 goto out; /* Successfully loaded it. */
2414 err = ctx->fatal_failure;
2415 if (err)
2416 goto out;
2417
2418 /* Could not find a usable firmware. Print the errors. */
2419 for (i = 0; i < B43_NR_FWTYPES; i++) {
2420 errmsg = ctx->errors[i];
2421 if (strlen(errmsg))
2422 b43err(dev->wl, errmsg);
2423 }
2424 b43_print_fw_helptext(dev->wl, 1);
2425 err = -ENOENT;
2426
2427out:
2428 kfree(ctx);
2429 return err;
2430}
2431
e4d6b795
MB		 2432static int b43_upload_microcode(struct b43_wldev *dev)
2433{
652caa5b 2434 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2435 const size_t hdr_len = sizeof(struct b43_fw_header);
2436 const __be32 *data;
2437 unsigned int i, len;
2438 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2439 u32 tmp, macctl;
e4d6b795
MB		 2440 int err = 0;
2441
1f7d87b0
MB		 2442 /* Jump the microcode PSM to offset 0 */
2443 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2444 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2445 macctl |= B43_MACCTL_PSM_JMP0;
2446 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2447 /* Zero out all microcode PSM registers and shared memory. */
2448 for (i = 0; i < 64; i++)
2449 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2450 for (i = 0; i < 4096; i += 2)
2451 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2452
e4d6b795 2453 /* Upload Microcode. */
61cb5dd6
MB		 2454 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2455 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2456 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2457 for (i = 0; i < len; i++) {
2458 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2459 udelay(10);
2460 }
2461
61cb5dd6 2462 if (dev->fw.pcm.data) {
e4d6b795 2463 /* Upload PCM data. */
61cb5dd6
MB		 2464 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2465 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2466 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2467 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2468 /* No need for autoinc bit in SHM_HW */
2469 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2470 for (i = 0; i < len; i++) {
2471 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2472 udelay(10);
2473 }
2474 }
2475
2476 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2477
2478 /* Start the microcode PSM */
2479 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2480 macctl &= ~B43_MACCTL_PSM_JMP0;
2481 macctl |= B43_MACCTL_PSM_RUN;
2482 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2483
2484 /* Wait for the microcode to load and respond */
2485 i = 0;
2486 while (1) {
2487 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2488 if (tmp == B43_IRQ_MAC_SUSPENDED)
2489 break;
2490 i++;
1f7d87b0 2491 if (i >= 20) {
e4d6b795 2492 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2493 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2494 err = -ENODEV;
1f7d87b0
MB		 2495 goto error;
2496 }
e175e996 2497 msleep(50);
e4d6b795
MB		 2498 }
2499 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2500
2501 /* Get and check the revisions. */
2502 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2503 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2504 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2505 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2506
2507 if (fwrev <= 0x128) {
2508 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2509 "binary drivers older than version 4.x is unsupported. "
2510 "You must upgrade your firmware files.\n");
eb189d8b 2511 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2512 err = -EOPNOTSUPP;
1f7d87b0 2513 goto error;
e4d6b795 2514 }
e4d6b795
MB		 2515 dev->fw.rev = fwrev;
2516 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2517 dev->fw.opensource = (fwdate == 0xFFFF);
2518
403a3a13
MB		 2519 /* Default to use-all-queues. */
2520 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2521 dev->qos_enabled = !!modparam_qos;
2522 /* Default to firmware/hardware crypto acceleration. */
2523 dev->hwcrypto_enabled = 1;
2524
e48b0eeb 2525 if (dev->fw.opensource) {
403a3a13
MB		 2526 u16 fwcapa;
2527
e48b0eeb
MB		 2528 /* Patchlevel info is encoded in the "time" field. */
2529 dev->fw.patch = fwtime;
403a3a13
MB		 2530 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2531 dev->fw.rev, dev->fw.patch);
2532
2533 fwcapa = b43_fwcapa_read(dev);
2534 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2535 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2536 /* Disable hardware crypto and fall back to software crypto. */
2537 dev->hwcrypto_enabled = 0;
2538 }
2539 if (!(fwcapa & B43_FWCAPA_QOS)) {
2540 b43info(dev->wl, "QoS not supported by firmware\n");
2541 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2542 * ieee80211_unregister to make sure the networking core can
2543 * properly free possible resources. */
2544 dev->wl->hw->queues = 1;
2545 dev->qos_enabled = 0;
2546 }
e48b0eeb
MB		 2547 } else {
2548 b43info(dev->wl, "Loading firmware version %u.%u "
2549 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2550 fwrev, fwpatch,
2551 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2552 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2553 if (dev->fw.pcm_request_failed) {
2554 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2555 "Hardware accelerated cryptography is disabled.\n");
2556 b43_print_fw_helptext(dev->wl, 0);
2557 }
e48b0eeb 2558 }
e4d6b795 2559
652caa5b
JL		 2560 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2561 dev->fw.rev, dev->fw.patch);
21d889d4 2562 wiphy->hw_version = dev->dev->core_id;
652caa5b 2563
eb189d8b 2564 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2565 /* We're over the deadline, but we keep support for old fw
2566 * until it turns out to be in major conflict with something new. */
eb189d8b 2567 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2568 "Support for old firmware will be removed soon "
2569 "(official deadline was July 2008).\n");
eb189d8b
MB		 2570 b43_print_fw_helptext(dev->wl, 0);
2571 }
2572
1f7d87b0
MB		 2573 return 0;
2574
2575error:
2576 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2577 macctl &= ~B43_MACCTL_PSM_RUN;
2578 macctl |= B43_MACCTL_PSM_JMP0;
2579 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2580
e4d6b795
MB		 2581 return err;
2582}
2583
2584static int b43_write_initvals(struct b43_wldev *dev,
2585 const struct b43_iv *ivals,
2586 size_t count,
2587 size_t array_size)
2588{
2589 const struct b43_iv *iv;
2590 u16 offset;
2591 size_t i;
2592 bool bit32;
2593
2594 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2595 iv = ivals;
2596 for (i = 0; i < count; i++) {
2597 if (array_size < sizeof(iv->offset_size))
2598 goto err_format;
2599 array_size -= sizeof(iv->offset_size);
2600 offset = be16_to_cpu(iv->offset_size);
2601 bit32 = !!(offset & B43_IV_32BIT);
2602 offset &= B43_IV_OFFSET_MASK;
2603 if (offset >= 0x1000)
2604 goto err_format;
2605 if (bit32) {
2606 u32 value;
2607
2608 if (array_size < sizeof(iv->data.d32))
2609 goto err_format;
2610 array_size -= sizeof(iv->data.d32);
2611
533dd1b0 2612 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2613 b43_write32(dev, offset, value);
2614
2615 iv = (const struct b43_iv *)((const uint8_t *)iv +
2616 sizeof(__be16) +
2617 sizeof(__be32));
2618 } else {
2619 u16 value;
2620
2621 if (array_size < sizeof(iv->data.d16))
2622 goto err_format;
2623 array_size -= sizeof(iv->data.d16);
2624
2625 value = be16_to_cpu(iv->data.d16);
2626 b43_write16(dev, offset, value);
2627
2628 iv = (const struct b43_iv *)((const uint8_t *)iv +
2629 sizeof(__be16) +
2630 sizeof(__be16));
2631 }
2632 }
2633 if (array_size)
2634 goto err_format;
2635
2636 return 0;
2637
2638err_format:
2639 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2640 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2641
2642 return -EPROTO;
2643}
2644
2645static int b43_upload_initvals(struct b43_wldev *dev)
2646{
2647 const size_t hdr_len = sizeof(struct b43_fw_header);
2648 const struct b43_fw_header *hdr;
2649 struct b43_firmware *fw = &dev->fw;
2650 const struct b43_iv *ivals;
2651 size_t count;
2652 int err;
2653
61cb5dd6
MB		 2654 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2655 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2656 count = be32_to_cpu(hdr->size);
2657 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2658 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2659 if (err)
2660 goto out;
61cb5dd6
MB		 2661 if (fw->initvals_band.data) {
2662 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2663 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2664 count = be32_to_cpu(hdr->size);
2665 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2666 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2667 if (err)
2668 goto out;
2669 }
2670out:
2671
2672 return err;
2673}
2674
2675/* Initialize the GPIOs
2676 * http://bcm-specs.sipsolutions.net/GPIO
2677 */
c4a2a081 2678static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2679{
d48ae5c8 2680 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2681
2682#ifdef CONFIG_SSB_DRIVER_PCICORE
2683 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2684#else
2685 return bus->chipco.dev;
2686#endif
2687}
2688
e4d6b795
MB		 2689static int b43_gpio_init(struct b43_wldev *dev)
2690{
c4a2a081 2691 struct ssb_device *gpiodev;
e4d6b795
MB		 2692 u32 mask, set;
2693
2694 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2695 & ~B43_MACCTL_GPOUTSMSK);
2696
e4d6b795
MB		 2697 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2698 | 0x000F);
2699
2700 mask = 0x0000001F;
2701 set = 0x0000000F;
c244e08c 2702 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2703 mask |= 0x0060;
2704 set |= 0x0060;
2705 }
2706 if (0 /* FIXME: conditional unknown */ ) {
2707 b43_write16(dev, B43_MMIO_GPIO_MASK,
2708 b43_read16(dev, B43_MMIO_GPIO_MASK)
2709 | 0x0100);
2710 mask |= 0x0180;
2711 set |= 0x0180;
2712 }
0581483a 2713 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2714 b43_write16(dev, B43_MMIO_GPIO_MASK,
2715 b43_read16(dev, B43_MMIO_GPIO_MASK)
2716 | 0x0200);
2717 mask |= 0x0200;
2718 set |= 0x0200;
2719 }
21d889d4 2720 if (dev->dev->core_rev >= 2)
e4d6b795
MB		 2721 mask |= 0x0010; /* FIXME: This is redundant. */
2722
6cbab0d9 2723 switch (dev->dev->bus_type) {
42c9a458
RM		 2724#ifdef CONFIG_B43_BCMA
2725 case B43_BUS_BCMA:
2726 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2727 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2728 BCMA_CC_GPIOCTL) & mask) | set);
2729 break;
2730#endif
6cbab0d9
RM		 2731#ifdef CONFIG_B43_SSB
2732 case B43_BUS_SSB:
2733 gpiodev = b43_ssb_gpio_dev(dev);
2734 if (gpiodev)
2735 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2736 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2737 & mask) | set);
2738 break;
2739#endif
2740 }
e4d6b795
MB		 2741
2742 return 0;
2743}
2744
2745/* Turn off all GPIO stuff. Call this on module unload, for example. */
2746static void b43_gpio_cleanup(struct b43_wldev *dev)
2747{
c4a2a081 2748 struct ssb_device *gpiodev;
e4d6b795 2749
6cbab0d9 2750 switch (dev->dev->bus_type) {
42c9a458
RM		 2751#ifdef CONFIG_B43_BCMA
2752 case B43_BUS_BCMA:
2753 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2754 0);
2755 break;
2756#endif
6cbab0d9
RM		 2757#ifdef CONFIG_B43_SSB
2758 case B43_BUS_SSB:
2759 gpiodev = b43_ssb_gpio_dev(dev);
2760 if (gpiodev)
2761 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2762 break;
2763#endif
2764 }
e4d6b795
MB		 2765}
2766
2767/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2768void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2769{
923fd703
MB		 2770 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2771 u16 fwstate;
2772
2773 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2774 B43_SHM_SH_UCODESTAT);
2775 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2776 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2777 b43err(dev->wl, "b43_mac_enable(): The firmware "
2778 "should be suspended, but current state is %u\n",
2779 fwstate);
2780 }
2781 }
2782
e4d6b795
MB		 2783 dev->mac_suspended--;
2784 B43_WARN_ON(dev->mac_suspended < 0);
2785 if (dev->mac_suspended == 0) {
2786 b43_write32(dev, B43_MMIO_MACCTL,
2787 b43_read32(dev, B43_MMIO_MACCTL)
2788 | B43_MACCTL_ENABLED);
2789 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2790 B43_IRQ_MAC_SUSPENDED);
2791 /* Commit writes */
2792 b43_read32(dev, B43_MMIO_MACCTL);
2793 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2794 b43_power_saving_ctl_bits(dev, 0);
2795 }
2796}
2797
2798/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2799void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2800{
2801 int i;
2802 u32 tmp;
2803
05b64b36 2804 might_sleep();
e4d6b795 2805 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2806
e4d6b795
MB		 2807 if (dev->mac_suspended == 0) {
2808 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2809 b43_write32(dev, B43_MMIO_MACCTL,
2810 b43_read32(dev, B43_MMIO_MACCTL)
2811 & ~B43_MACCTL_ENABLED);
2812 /* force pci to flush the write */
2813 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2814 for (i = 35; i; i--) {
2815 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2816 if (tmp & B43_IRQ_MAC_SUSPENDED)
2817 goto out;
2818 udelay(10);
2819 }
2820 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2821 for (i = 40; i; i--) {
e4d6b795
MB		 2822 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2823 if (tmp & B43_IRQ_MAC_SUSPENDED)
2824 goto out;
05b64b36 2825 msleep(1);
e4d6b795
MB		 2826 }
2827 b43err(dev->wl, "MAC suspend failed\n");
2828 }
05b64b36 2829out:
e4d6b795
MB		 2830 dev->mac_suspended++;
2831}
2832
858a1652
RM		 2833/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2834void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2835{
6cbab0d9
RM		 2836 u32 tmp;
2837
2838 switch (dev->dev->bus_type) {
42c9a458
RM		 2839#ifdef CONFIG_B43_BCMA
2840 case B43_BUS_BCMA:
36677874 2841 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2842 if (on)
2843 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2844 else
2845 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2846 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2847 break;
2848#endif
6cbab0d9
RM		 2849#ifdef CONFIG_B43_SSB
2850 case B43_BUS_SSB:
2851 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2852 if (on)
2853 tmp |= B43_TMSLOW_MACPHYCLKEN;
2854 else
2855 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2856 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2857 break;
2858#endif
2859 }
858a1652
RM		 2860}
2861
e4d6b795
MB		 2862static void b43_adjust_opmode(struct b43_wldev *dev)
2863{
2864 struct b43_wl *wl = dev->wl;
2865 u32 ctl;
2866 u16 cfp_pretbtt;
2867
2868 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2869 /* Reset status to STA infrastructure mode. */
2870 ctl &= ~B43_MACCTL_AP;
2871 ctl &= ~B43_MACCTL_KEEP_CTL;
2872 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2873 ctl &= ~B43_MACCTL_KEEP_BAD;
2874 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2875 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2876 ctl |= B43_MACCTL_INFRA;
2877
05c914fe
JB		 2878 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2879 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2880 ctl |= B43_MACCTL_AP;
05c914fe 2881 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2882 ctl &= ~B43_MACCTL_INFRA;
2883
2884 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2885 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2886 if (wl->filter_flags & FIF_FCSFAIL)
2887 ctl |= B43_MACCTL_KEEP_BAD;
2888 if (wl->filter_flags & FIF_PLCPFAIL)
2889 ctl |= B43_MACCTL_KEEP_BADPLCP;
2890 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2891 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2892 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2893 ctl |= B43_MACCTL_BEACPROMISC;
2894
e4d6b795
MB		 2895 /* Workaround: On old hardware the HW-MAC-address-filter
2896 * doesn't work properly, so always run promisc in filter
2897 * it in software. */
21d889d4 2898 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2899 ctl |= B43_MACCTL_PROMISC;
2900
2901 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2902
2903 cfp_pretbtt = 2;
2904 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2905 if (dev->dev->chip_id == 0x4306 &&
2906 dev->dev->chip_rev == 3)
e4d6b795
MB		 2907 cfp_pretbtt = 100;
2908 else
2909 cfp_pretbtt = 50;
2910 }
2911 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2912
2913 /* FIXME: We don't currently implement the PMQ mechanism,
2914 * so always disable it. If we want to implement PMQ,
2915 * we need to enable it here (clear DISCPMQ) in AP mode.
2916 */
2917 if (0 /* ctl & B43_MACCTL_AP */) {
2918 b43_write32(dev, B43_MMIO_MACCTL,
2919 b43_read32(dev, B43_MMIO_MACCTL)
2920 & ~B43_MACCTL_DISCPMQ);
2921 } else {
2922 b43_write32(dev, B43_MMIO_MACCTL,
2923 b43_read32(dev, B43_MMIO_MACCTL)
2924 | B43_MACCTL_DISCPMQ);
2925 }
e4d6b795
MB		 2926}
2927
2928static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2929{
2930 u16 offset;
2931
2932 if (is_ofdm) {
2933 offset = 0x480;
2934 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2935 } else {
2936 offset = 0x4C0;
2937 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2938 }
2939 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2940 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2941}
2942
2943static void b43_rate_memory_init(struct b43_wldev *dev)
2944{
2945 switch (dev->phy.type) {
2946 case B43_PHYTYPE_A:
2947 case B43_PHYTYPE_G:
53a6e234 2948 case B43_PHYTYPE_N:
9d86a2d5 2949 case B43_PHYTYPE_LP:
e4d6b795
MB		 2950 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2951 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2952 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2953 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2954 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2955 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2956 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2957 if (dev->phy.type == B43_PHYTYPE_A)
2958 break;
2959 /* fallthrough */
2960 case B43_PHYTYPE_B:
2961 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2962 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2963 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2964 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2965 break;
2966 default:
2967 B43_WARN_ON(1);
2968 }
2969}
2970
5042c507
MB		 2971/* Set the default values for the PHY TX Control Words. */
2972static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2973{
2974 u16 ctl = 0;
2975
2976 ctl |= B43_TXH_PHY_ENC_CCK;
2977 ctl |= B43_TXH_PHY_ANT01AUTO;
2978 ctl |= B43_TXH_PHY_TXPWR;
2979
2980 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2981 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2982 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2983}
2984
e4d6b795
MB		 2985/* Set the TX-Antenna for management frames sent by firmware. */
2986static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2987{
5042c507 2988 u16 ant;
e4d6b795
MB		 2989 u16 tmp;
2990
5042c507 2991 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2992
e4d6b795
MB		 2993 /* For ACK/CTS */
2994 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2995 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2996 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2997 /* For Probe Resposes */
2998 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2999 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3000 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3001}
3002
3003/* This is the opposite of b43_chip_init() */
3004static void b43_chip_exit(struct b43_wldev *dev)
3005{
fb11137a 3006 b43_phy_exit(dev);
e4d6b795
MB		 3007 b43_gpio_cleanup(dev);
3008 /* firmware is released later */
3009}
3010
3011/* Initialize the chip
3012 * http://bcm-specs.sipsolutions.net/ChipInit
3013 */
3014static int b43_chip_init(struct b43_wldev *dev)
3015{
3016 struct b43_phy *phy = &dev->phy;
ef1a628d 3017 int err;
858a1652 3018 u32 macctl;
e4d6b795
MB		 3019 u16 value16;
3020
1f7d87b0
MB		 3021 /* Initialize the MAC control */
3022 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3023 if (dev->phy.gmode)
3024 macctl |= B43_MACCTL_GMODE;
3025 macctl |= B43_MACCTL_INFRA;
3026 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 3027
3028 err = b43_request_firmware(dev);
3029 if (err)
3030 goto out;
3031 err = b43_upload_microcode(dev);
3032 if (err)
3033 goto out; /* firmware is released later */
3034
3035 err = b43_gpio_init(dev);
3036 if (err)
3037 goto out; /* firmware is released later */
21954c36 3038
e4d6b795
MB		 3039 err = b43_upload_initvals(dev);
3040 if (err)
1a8d1227 3041 goto err_gpio_clean;
e4d6b795 3042
0b7dcd96
MB		 3043 /* Turn the Analog on and initialize the PHY. */
3044 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3045 err = b43_phy_init(dev);
3046 if (err)
ef1a628d 3047 goto err_gpio_clean;
e4d6b795 3048
ef1a628d
MB		 3049 /* Disable Interference Mitigation. */
3050 if (phy->ops->interf_mitigation)
3051 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3052
ef1a628d
MB		 3053 /* Select the antennae */
3054 if (phy->ops->set_rx_antenna)
3055 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3056 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3057
3058 if (phy->type == B43_PHYTYPE_B) {
3059 value16 = b43_read16(dev, 0x005E);
3060 value16 |= 0x0004;
3061 b43_write16(dev, 0x005E, value16);
3062 }
3063 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3064 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3065 b43_write32(dev, 0x010C, 0x01000000);
3066
3067 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3068 & ~B43_MACCTL_INFRA);
3069 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3070 | B43_MACCTL_INFRA);
e4d6b795 3071
e4d6b795
MB		 3072 /* Probe Response Timeout value */
3073 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3074 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3075
3076 /* Initially set the wireless operation mode. */
3077 b43_adjust_opmode(dev);
3078
21d889d4 3079 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3080 b43_write16(dev, 0x060E, 0x0000);
3081 b43_write16(dev, 0x0610, 0x8000);
3082 b43_write16(dev, 0x0604, 0x0000);
3083 b43_write16(dev, 0x0606, 0x0200);
3084 } else {
3085 b43_write32(dev, 0x0188, 0x80000000);
3086 b43_write32(dev, 0x018C, 0x02000000);
3087 }
3088 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3089 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3090 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3091 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3092 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3093 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3094 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3095
858a1652 3096 b43_mac_phy_clock_set(dev, true);
e4d6b795 3097
6cbab0d9 3098 switch (dev->dev->bus_type) {
42c9a458
RM		 3099#ifdef CONFIG_B43_BCMA
3100 case B43_BUS_BCMA:
3101 /* FIXME: 0xE74 is quite common, but should be read from CC */
3102 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3103 break;
3104#endif
6cbab0d9
RM		 3105#ifdef CONFIG_B43_SSB
3106 case B43_BUS_SSB:
3107 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3108 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3109 break;
3110#endif
3111 }
e4d6b795
MB		 3112
3113 err = 0;
3114 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3115out:
e4d6b795
MB		 3116 return err;
3117
1a8d1227 3118err_gpio_clean:
e4d6b795 3119 b43_gpio_cleanup(dev);
21954c36 3120 return err;
e4d6b795
MB		 3121}
3122
e4d6b795
MB		 3123static void b43_periodic_every60sec(struct b43_wldev *dev)
3124{
ef1a628d 3125 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3126
ef1a628d
MB		 3127 if (ops->pwork_60sec)
3128 ops->pwork_60sec(dev);
18c8adeb
MB		 3129
3130 /* Force check the TX power emission now. */
3131 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3132}
3133
3134static void b43_periodic_every30sec(struct b43_wldev *dev)
3135{
3136 /* Update device statistics. */
3137 b43_calculate_link_quality(dev);
3138}
3139
3140static void b43_periodic_every15sec(struct b43_wldev *dev)
3141{
3142 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3143 u16 wdr;
3144
3145 if (dev->fw.opensource) {
3146 /* Check if the firmware is still alive.
3147 * It will reset the watchdog counter to 0 in its idle loop. */
3148 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3149 if (unlikely(wdr)) {
3150 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3151 b43_controller_restart(dev, "Firmware watchdog");
3152 return;
3153 } else {
3154 b43_shm_write16(dev, B43_SHM_SCRATCH,
3155 B43_WATCHDOG_REG, 1);
3156 }
3157 }
e4d6b795 3158
ef1a628d
MB		 3159 if (phy->ops->pwork_15sec)
3160 phy->ops->pwork_15sec(dev);
3161
00e0b8cb
SB		 3162 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3163 wmb();
990b86f4
MB		 3164
3165#if B43_DEBUG
3166 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3167 unsigned int i;
3168
3169 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3170 dev->irq_count / 15,
3171 dev->tx_count / 15,
3172 dev->rx_count / 15);
3173 dev->irq_count = 0;
3174 dev->tx_count = 0;
3175 dev->rx_count = 0;
3176 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3177 if (dev->irq_bit_count[i]) {
3178 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3179 dev->irq_bit_count[i] / 15, i, (1 << i));
3180 dev->irq_bit_count[i] = 0;
3181 }
3182 }
3183 }
3184#endif
e4d6b795
MB		 3185}
3186
e4d6b795
MB		 3187static void do_periodic_work(struct b43_wldev *dev)
3188{
3189 unsigned int state;
3190
3191 state = dev->periodic_state;
42bb4cd5 3192 if (state % 4 == 0)
e4d6b795 3193 b43_periodic_every60sec(dev);
42bb4cd5 3194 if (state % 2 == 0)
e4d6b795 3195 b43_periodic_every30sec(dev);
42bb4cd5 3196 b43_periodic_every15sec(dev);
e4d6b795
MB		 3197}
3198
05b64b36
MB		 3199/* Periodic work locking policy:
3200 * The whole periodic work handler is protected by
3201 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3202 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3203 */
e4d6b795
MB		 3204static void b43_periodic_work_handler(struct work_struct *work)
3205{
05b64b36
MB		 3206 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3207 periodic_work.work);
3208 struct b43_wl *wl = dev->wl;
3209 unsigned long delay;
e4d6b795 3210
05b64b36 3211 mutex_lock(&wl->mutex);
e4d6b795
MB		 3212
3213 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3214 goto out;
3215 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3216 goto out_requeue;
3217
05b64b36 3218 do_periodic_work(dev);
e4d6b795 3219
e4d6b795 3220 dev->periodic_state++;
42bb4cd5 3221out_requeue:
e4d6b795
MB		 3222 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3223 delay = msecs_to_jiffies(50);
3224 else
82cd682d 3225 delay = round_jiffies_relative(HZ * 15);
42935eca 3226 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3227out:
05b64b36 3228 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3229}
3230
3231static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3232{
3233 struct delayed_work *work = &dev->periodic_work;
3234
3235 dev->periodic_state = 0;
3236 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3237 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3238}
3239
f3dd3fcc 3240/* Check if communication with the device works correctly. */
e4d6b795
MB		 3241static int b43_validate_chipaccess(struct b43_wldev *dev)
3242{
f62ae6cd 3243 u32 v, backup0, backup4;
e4d6b795 3244
f62ae6cd
MB		 3245 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3246 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3247
3248 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3249 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3250 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3251 goto error;
f3dd3fcc
MB		 3252 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3253 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3254 goto error;
3255
f62ae6cd
MB		 3256 /* Check if unaligned 32bit SHM_SHARED access works properly.
3257 * However, don't bail out on failure, because it's noncritical. */
3258 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3259 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3260 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3261 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3262 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3263 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3264 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3265 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3266 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3267 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3268 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3269 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3270
3271 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3272 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3273
21d889d4 3274 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3275 /* The 32bit register shadows the two 16bit registers
3276 * with update sideeffects. Validate this. */
3277 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3278 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3279 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3280 goto error;
3281 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3282 goto error;
3283 }
3284 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3285
3286 v = b43_read32(dev, B43_MMIO_MACCTL);
3287 v |= B43_MACCTL_GMODE;
3288 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3289 goto error;
3290
3291 return 0;
f3dd3fcc 3292error:
e4d6b795
MB		 3293 b43err(dev->wl, "Failed to validate the chipaccess\n");
3294 return -ENODEV;
3295}
3296
3297static void b43_security_init(struct b43_wldev *dev)
3298{
e4d6b795
MB		 3299 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3300 /* KTP is a word address, but we address SHM bytewise.
3301 * So multiply by two.
3302 */
3303 dev->ktp *= 2;
66d2d089
MB		 3304 /* Number of RCMTA address slots */
3305 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3306 /* Clear the key memory. */
e4d6b795
MB		 3307 b43_clear_keys(dev);
3308}
3309
616de35d 3310#ifdef CONFIG_B43_HWRNG
99da185a 3311static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3312{
3313 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3314 struct b43_wldev *dev;
3315 int count = -ENODEV;
e4d6b795 3316
a78b3bb2
MB		 3317 mutex_lock(&wl->mutex);
3318 dev = wl->current_dev;
3319 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3320 *data = b43_read16(dev, B43_MMIO_RNG);
3321 count = sizeof(u16);
3322 }
3323 mutex_unlock(&wl->mutex);
e4d6b795 3324
a78b3bb2 3325 return count;
e4d6b795 3326}
616de35d 3327#endif /* CONFIG_B43_HWRNG */
e4d6b795 3328
b844eba2 3329static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3330{
616de35d 3331#ifdef CONFIG_B43_HWRNG
e4d6b795 3332 if (wl->rng_initialized)
b844eba2 3333 hwrng_unregister(&wl->rng);
616de35d 3334#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3335}
3336
3337static int b43_rng_init(struct b43_wl *wl)
3338{
616de35d 3339 int err = 0;
e4d6b795 3340
616de35d 3341#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3342 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3343 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3344 wl->rng.name = wl->rng_name;
3345 wl->rng.data_read = b43_rng_read;
3346 wl->rng.priv = (unsigned long)wl;
3347 wl->rng_initialized = 1;
3348 err = hwrng_register(&wl->rng);
3349 if (err) {
3350 wl->rng_initialized = 0;
3351 b43err(wl, "Failed to register the random "
3352 "number generator (%d)\n", err);
3353 }
616de35d 3354#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3355
3356 return err;
3357}
3358
f5d40eed 3359static void b43_tx_work(struct work_struct *work)
e4d6b795 3360{
f5d40eed
MB		 3361 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3362 struct b43_wldev *dev;
3363 struct sk_buff *skb;
3364 int err = 0;
e4d6b795 3365
f5d40eed
MB		 3366 mutex_lock(&wl->mutex);
3367 dev = wl->current_dev;
3368 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3369 mutex_unlock(&wl->mutex);
3370 return;
5100d5ac 3371 }
21a75d77 3372
f5d40eed
MB		 3373 while (skb_queue_len(&wl->tx_queue)) {
3374 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3375
21a75d77 3376 if (b43_using_pio_transfers(dev))
e039fa4a 3377 err = b43_pio_tx(dev, skb);
21a75d77 3378 else
e039fa4a 3379 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3380 if (unlikely(err))
3381 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3382 }
3383
990b86f4
MB		 3384#if B43_DEBUG
3385 dev->tx_count++;
3386#endif
f5d40eed
MB		 3387 mutex_unlock(&wl->mutex);
3388}
21a75d77 3389
7bb45683 3390static void b43_op_tx(struct ieee80211_hw *hw,
f5d40eed
MB		 3391 struct sk_buff *skb)
3392{
3393 struct b43_wl *wl = hw_to_b43_wl(hw);
3394
3395 if (unlikely(skb->len < 2 + 2 + 6)) {
3396 /* Too short, this can't be a valid frame. */
3397 dev_kfree_skb_any(skb);
7bb45683 3398 return;
f5d40eed
MB		 3399 }
3400 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3401
3402 skb_queue_tail(&wl->tx_queue, skb);
3403 ieee80211_queue_work(wl->hw, &wl->tx_work);
e4d6b795
MB		 3404}
3405
e6f5b934
MB		 3406static void b43_qos_params_upload(struct b43_wldev *dev,
3407 const struct ieee80211_tx_queue_params *p,
3408 u16 shm_offset)
3409{
3410 u16 params[B43_NR_QOSPARAMS];
0b57664c 3411 int bslots, tmp;
e6f5b934
MB		 3412 unsigned int i;
3413
b0544eb6
MB		 3414 if (!dev->qos_enabled)
3415 return;
3416
0b57664c 3417 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3418
3419 memset(&params, 0, sizeof(params));
3420
3421 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3422 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3423 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3424 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3425 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3426 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3427 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3428
3429 for (i = 0; i < ARRAY_SIZE(params); i++) {
3430 if (i == B43_QOSPARAM_STATUS) {
3431 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3432 shm_offset + (i * 2));
3433 /* Mark the parameters as updated. */
3434 tmp |= 0x100;
3435 b43_shm_write16(dev, B43_SHM_SHARED,
3436 shm_offset + (i * 2),
3437 tmp);
3438 } else {
3439 b43_shm_write16(dev, B43_SHM_SHARED,
3440 shm_offset + (i * 2),
3441 params[i]);
3442 }
3443 }
3444}
3445
c40c1129
MB		 3446/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3447static const u16 b43_qos_shm_offsets[] = {
3448 /* [mac80211-queue-nr] = SHM_OFFSET, */
3449 [0] = B43_QOS_VOICE,
3450 [1] = B43_QOS_VIDEO,
3451 [2] = B43_QOS_BESTEFFORT,
3452 [3] = B43_QOS_BACKGROUND,
3453};
3454
5a5f3b40
MB		 3455/* Update all QOS parameters in hardware. */
3456static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3457{
3458 struct b43_wl *wl = dev->wl;
3459 struct b43_qos_params *params;
e6f5b934
MB		 3460 unsigned int i;
3461
b0544eb6
MB		 3462 if (!dev->qos_enabled)
3463 return;
3464
c40c1129
MB		 3465 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3466 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3467
3468 b43_mac_suspend(dev);
e6f5b934
MB		 3469 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3470 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3471 b43_qos_params_upload(dev, &(params->p),
3472 b43_qos_shm_offsets[i]);
e6f5b934 3473 }
e6f5b934
MB		 3474 b43_mac_enable(dev);
3475}
3476
3477static void b43_qos_clear(struct b43_wl *wl)
3478{
3479 struct b43_qos_params *params;
3480 unsigned int i;
3481
c40c1129
MB		 3482 /* Initialize QoS parameters to sane defaults. */
3483
3484 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3485 ARRAY_SIZE(wl->qos_params));
3486
e6f5b934
MB		 3487 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3488 params = &(wl->qos_params[i]);
3489
c40c1129
MB		 3490 switch (b43_qos_shm_offsets[i]) {
3491 case B43_QOS_VOICE:
3492 params->p.txop = 0;
3493 params->p.aifs = 2;
3494 params->p.cw_min = 0x0001;
3495 params->p.cw_max = 0x0001;
3496 break;
3497 case B43_QOS_VIDEO:
3498 params->p.txop = 0;
3499 params->p.aifs = 2;
3500 params->p.cw_min = 0x0001;
3501 params->p.cw_max = 0x0001;
3502 break;
3503 case B43_QOS_BESTEFFORT:
3504 params->p.txop = 0;
3505 params->p.aifs = 3;
3506 params->p.cw_min = 0x0001;
3507 params->p.cw_max = 0x03FF;
3508 break;
3509 case B43_QOS_BACKGROUND:
3510 params->p.txop = 0;
3511 params->p.aifs = 7;
3512 params->p.cw_min = 0x0001;
3513 params->p.cw_max = 0x03FF;
3514 break;
3515 default:
3516 B43_WARN_ON(1);
3517 }
e6f5b934
MB		 3518 }
3519}
3520
3521/* Initialize the core's QOS capabilities */
3522static void b43_qos_init(struct b43_wldev *dev)
3523{
b0544eb6
MB		 3524 if (!dev->qos_enabled) {
3525 /* Disable QOS support. */
3526 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3527 b43_write16(dev, B43_MMIO_IFSCTL,
3528 b43_read16(dev, B43_MMIO_IFSCTL)
3529 & ~B43_MMIO_IFSCTL_USE_EDCF);
3530 b43dbg(dev->wl, "QoS disabled\n");
3531 return;
3532 }
3533
e6f5b934 3534 /* Upload the current QOS parameters. */
5a5f3b40 3535 b43_qos_upload_all(dev);
e6f5b934
MB		 3536
3537 /* Enable QOS support. */
3538 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3539 b43_write16(dev, B43_MMIO_IFSCTL,
3540 b43_read16(dev, B43_MMIO_IFSCTL)
3541 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3542 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3543}
3544
e100bb64 3545static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3546 const struct ieee80211_tx_queue_params *params)
e4d6b795 3547{
e6f5b934 3548 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3549 struct b43_wldev *dev;
e6f5b934 3550 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3551 int err = -ENODEV;
e6f5b934
MB		 3552
3553 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3554 /* Queue not available or don't support setting
3555 * params on this queue. Return success to not
3556 * confuse mac80211. */
3557 return 0;
3558 }
5a5f3b40
MB		 3559 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3560 ARRAY_SIZE(wl->qos_params));
e6f5b934 3561
5a5f3b40
MB		 3562 mutex_lock(&wl->mutex);
3563 dev = wl->current_dev;
3564 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3565 goto out_unlock;
e6f5b934 3566
5a5f3b40
MB		 3567 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3568 b43_mac_suspend(dev);
3569 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3570 b43_qos_shm_offsets[queue]);
3571 b43_mac_enable(dev);
3572 err = 0;
e6f5b934 3573
5a5f3b40
MB		 3574out_unlock:
3575 mutex_unlock(&wl->mutex);
3576
3577 return err;
e4d6b795
MB		 3578}
3579
40faacc4
MB		 3580static int b43_op_get_stats(struct ieee80211_hw *hw,
3581 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3582{
3583 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3584
36dbd954 3585 mutex_lock(&wl->mutex);
e4d6b795 3586 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3587 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3588
3589 return 0;
3590}
3591
08e87a83
AF		 3592static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3593{
3594 struct b43_wl *wl = hw_to_b43_wl(hw);
3595 struct b43_wldev *dev;
3596 u64 tsf;
3597
3598 mutex_lock(&wl->mutex);
08e87a83
AF		 3599 dev = wl->current_dev;
3600
3601 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3602 b43_tsf_read(dev, &tsf);
3603 else
3604 tsf = 0;
3605
08e87a83
AF		 3606 mutex_unlock(&wl->mutex);
3607
3608 return tsf;
3609}
3610
3611static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3612{
3613 struct b43_wl *wl = hw_to_b43_wl(hw);
3614 struct b43_wldev *dev;
3615
3616 mutex_lock(&wl->mutex);
08e87a83
AF		 3617 dev = wl->current_dev;
3618
3619 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3620 b43_tsf_write(dev, tsf);
3621
08e87a83
AF		 3622 mutex_unlock(&wl->mutex);
3623}
3624
e4d6b795
MB		 3625static void b43_put_phy_into_reset(struct b43_wldev *dev)
3626{
6cbab0d9 3627 u32 tmp;
e4d6b795 3628
6cbab0d9 3629 switch (dev->dev->bus_type) {
42c9a458
RM		 3630#ifdef CONFIG_B43_BCMA
3631 case B43_BUS_BCMA:
3632 b43err(dev->wl,
3633 "Putting PHY into reset not supported on BCMA\n");
3634 break;
3635#endif
6cbab0d9
RM		 3636#ifdef CONFIG_B43_SSB
3637 case B43_BUS_SSB:
3638 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3639 tmp &= ~B43_TMSLOW_GMODE;
3640 tmp |= B43_TMSLOW_PHYRESET;
3641 tmp |= SSB_TMSLOW_FGC;
3642 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3643 msleep(1);
3644
3645 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3646 tmp &= ~SSB_TMSLOW_FGC;
3647 tmp |= B43_TMSLOW_PHYRESET;
3648 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3649 msleep(1);
e4d6b795 3650
6cbab0d9
RM		 3651 break;
3652#endif
3653 }
e4d6b795
MB		 3654}
3655
99da185a 3656static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3657{
3658 switch (band) {
3659 case IEEE80211_BAND_5GHZ:
3660 return "5";
3661 case IEEE80211_BAND_2GHZ:
3662 return "2.4";
3663 default:
3664 break;
3665 }
3666 B43_WARN_ON(1);
3667 return "";
3668}
3669
e4d6b795 3670/* Expects wl->mutex locked */
bb1eeff1 3671static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3672{
bb1eeff1 3673 struct b43_wldev *up_dev = NULL;
e4d6b795 3674 struct b43_wldev *down_dev;
bb1eeff1 3675 struct b43_wldev *d;
e4d6b795 3676 int err;
922d8a0b 3677 bool uninitialized_var(gmode);
e4d6b795
MB		 3678 int prev_status;
3679
bb1eeff1
MB		 3680 /* Find a device and PHY which supports the band. */
3681 list_for_each_entry(d, &wl->devlist, list) {
3682 switch (chan->band) {
3683 case IEEE80211_BAND_5GHZ:
3684 if (d->phy.supports_5ghz) {
3685 up_dev = d;
3686 gmode = 0;
3687 }
3688 break;
3689 case IEEE80211_BAND_2GHZ:
3690 if (d->phy.supports_2ghz) {
3691 up_dev = d;
3692 gmode = 1;
3693 }
3694 break;
3695 default:
3696 B43_WARN_ON(1);
3697 return -EINVAL;
3698 }
3699 if (up_dev)
3700 break;
3701 }
3702 if (!up_dev) {
3703 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3704 band_to_string(chan->band));
3705 return -ENODEV;
e4d6b795
MB		 3706 }
3707 if ((up_dev == wl->current_dev) &&
3708 (!!wl->current_dev->phy.gmode == !!gmode)) {
3709 /* This device is already running. */
3710 return 0;
3711 }
bb1eeff1
MB		 3712 b43dbg(wl, "Switching to %s-GHz band\n",
3713 band_to_string(chan->band));
e4d6b795
MB		 3714 down_dev = wl->current_dev;
3715
3716 prev_status = b43_status(down_dev);
3717 /* Shutdown the currently running core. */
3718 if (prev_status >= B43_STAT_STARTED)
36dbd954 3719 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3720 if (prev_status >= B43_STAT_INITIALIZED)
3721 b43_wireless_core_exit(down_dev);
3722
3723 if (down_dev != up_dev) {
3724 /* We switch to a different core, so we put PHY into
3725 * RESET on the old core. */
3726 b43_put_phy_into_reset(down_dev);
3727 }
3728
3729 /* Now start the new core. */
3730 up_dev->phy.gmode = gmode;
3731 if (prev_status >= B43_STAT_INITIALIZED) {
3732 err = b43_wireless_core_init(up_dev);
3733 if (err) {
3734 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3735 "selected %s-GHz band\n",
3736 band_to_string(chan->band));
e4d6b795
MB		 3737 goto init_failure;
3738 }
3739 }
3740 if (prev_status >= B43_STAT_STARTED) {
3741 err = b43_wireless_core_start(up_dev);
3742 if (err) {
3743 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3744 "selected %s-GHz band\n",
3745 band_to_string(chan->band));
e4d6b795
MB		 3746 b43_wireless_core_exit(up_dev);
3747 goto init_failure;
3748 }
3749 }
3750 B43_WARN_ON(b43_status(up_dev) != prev_status);
3751
3752 wl->current_dev = up_dev;
3753
3754 return 0;
bb1eeff1 3755init_failure:
e4d6b795
MB		 3756 /* Whoops, failed to init the new core. No core is operating now. */
3757 wl->current_dev = NULL;
3758 return err;
3759}
3760
9124b077
JB		 3761/* Write the short and long frame retry limit values. */
3762static void b43_set_retry_limits(struct b43_wldev *dev,
3763 unsigned int short_retry,
3764 unsigned int long_retry)
3765{
3766 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3767 * the chip-internal counter. */
3768 short_retry = min(short_retry, (unsigned int)0xF);
3769 long_retry = min(long_retry, (unsigned int)0xF);
3770
3771 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3772 short_retry);
3773 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3774 long_retry);
3775}
3776
e8975581 3777static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3778{
3779 struct b43_wl *wl = hw_to_b43_wl(hw);
3780 struct b43_wldev *dev;
3781 struct b43_phy *phy;
e8975581 3782 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3783 int antenna;
e4d6b795 3784 int err = 0;
2a190322 3785 bool reload_bss = false;
e4d6b795 3786
e4d6b795
MB		 3787 mutex_lock(&wl->mutex);
3788
2a190322
FF		 3789 dev = wl->current_dev;
3790
bb1eeff1
MB		 3791 /* Switch the band (if necessary). This might change the active core. */
3792 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3793 if (err)
3794 goto out_unlock_mutex;
2a190322
FF		 3795
3796 /* Need to reload all settings if the core changed */
3797 if (dev != wl->current_dev) {
3798 dev = wl->current_dev;
3799 changed = ~0;
3800 reload_bss = true;
3801 }
3802
e4d6b795
MB		 3803 phy = &dev->phy;
3804
aa4c7b2a
RM		 3805 if (conf_is_ht(conf))
3806 phy->is_40mhz =
3807 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3808 else
3809 phy->is_40mhz = false;
3810
d10d0e57
MB		 3811 b43_mac_suspend(dev);
3812
9124b077
JB		 3813 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3814 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3815 conf->long_frame_max_tx_count);
3816 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3817 if (!changed)
d10d0e57 3818 goto out_mac_enable;
e4d6b795
MB		 3819
3820 /* Switch to the requested channel.
3821 * The firmware takes care of races with the TX handler. */
8318d78a 3822 if (conf->channel->hw_value != phy->channel)
ef1a628d 3823 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3824
0869aea0 3825 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3826
e4d6b795
MB		 3827 /* Adjust the desired TX power level. */
3828 if (conf->power_level != 0) {
18c8adeb
MB		 3829 if (conf->power_level != phy->desired_txpower) {
3830 phy->desired_txpower = conf->power_level;
3831 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3832 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3833 }
3834 }
3835
3836 /* Antennas for RX and management frame TX. */
0f4ac38b 3837 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3838 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3839 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3840 if (phy->ops->set_rx_antenna)
3841 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3842
fd4973c5
LF		 3843 if (wl->radio_enabled != phy->radio_on) {
3844 if (wl->radio_enabled) {
19d337df 3845 b43_software_rfkill(dev, false);
fda9abcf
MB		 3846 b43info(dev->wl, "Radio turned on by software\n");
3847 if (!dev->radio_hw_enable) {
3848 b43info(dev->wl, "The hardware RF-kill button "
3849 "still turns the radio physically off. "
3850 "Press the button to turn it on.\n");
3851 }
3852 } else {
19d337df 3853 b43_software_rfkill(dev, true);
fda9abcf
MB		 3854 b43info(dev->wl, "Radio turned off by software\n");
3855 }
3856 }
3857
d10d0e57
MB		 3858out_mac_enable:
3859 b43_mac_enable(dev);
3860out_unlock_mutex:
e4d6b795
MB		 3861 mutex_unlock(&wl->mutex);
3862
2a190322
FF		 3863 if (wl->vif && reload_bss)
3864 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3865
e4d6b795
MB		 3866 return err;
3867}
3868
881d948c 3869static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3870{
3871 struct ieee80211_supported_band *sband =
3872 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3873 struct ieee80211_rate *rate;
3874 int i;
3875 u16 basic, direct, offset, basic_offset, rateptr;
3876
3877 for (i = 0; i < sband->n_bitrates; i++) {
3878 rate = &sband->bitrates[i];
3879
3880 if (b43_is_cck_rate(rate->hw_value)) {
3881 direct = B43_SHM_SH_CCKDIRECT;
3882 basic = B43_SHM_SH_CCKBASIC;
3883 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3884 offset &= 0xF;
3885 } else {
3886 direct = B43_SHM_SH_OFDMDIRECT;
3887 basic = B43_SHM_SH_OFDMBASIC;
3888 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3889 offset &= 0xF;
3890 }
3891
3892 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3893
3894 if (b43_is_cck_rate(rate->hw_value)) {
3895 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3896 basic_offset &= 0xF;
3897 } else {
3898 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3899 basic_offset &= 0xF;
3900 }
3901
3902 /*
3903 * Get the pointer that we need to point to
3904 * from the direct map
3905 */
3906 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3907 direct + 2 * basic_offset);
3908 /* and write it to the basic map */
3909 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3910 rateptr);
3911 }
3912}
3913
3914static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3915 struct ieee80211_vif *vif,
3916 struct ieee80211_bss_conf *conf,
3917 u32 changed)
3918{
3919 struct b43_wl *wl = hw_to_b43_wl(hw);
3920 struct b43_wldev *dev;
c7ab5ef9
JB		 3921
3922 mutex_lock(&wl->mutex);
3923
3924 dev = wl->current_dev;
d10d0e57 3925 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3926 goto out_unlock_mutex;
2d0ddec5
JB		 3927
3928 B43_WARN_ON(wl->vif != vif);
3929
3930 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3931 if (conf->bssid)
3932 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3933 else
3934 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3935 }
2d0ddec5 3936
3f0d843b
JB		 3937 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3938 if (changed & BSS_CHANGED_BEACON &&
3939 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3940 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3941 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3942 b43_update_templates(wl);
3943
3944 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3945 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3946 }
3947
c7ab5ef9
JB		 3948 b43_mac_suspend(dev);
3949
57c4d7b4
JB		 3950 /* Update templates for AP/mesh mode. */
3951 if (changed & BSS_CHANGED_BEACON_INT &&
3952 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3953 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3954 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3955 conf->beacon_int)
57c4d7b4
JB		 3956 b43_set_beacon_int(dev, conf->beacon_int);
3957
c7ab5ef9
JB		 3958 if (changed & BSS_CHANGED_BASIC_RATES)
3959 b43_update_basic_rates(dev, conf->basic_rates);
3960
3961 if (changed & BSS_CHANGED_ERP_SLOT) {
3962 if (conf->use_short_slot)
3963 b43_short_slot_timing_enable(dev);
3964 else
3965 b43_short_slot_timing_disable(dev);
3966 }
3967
3968 b43_mac_enable(dev);
d10d0e57 3969out_unlock_mutex:
c7ab5ef9 3970 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3971}
3972
40faacc4 3973static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3974 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3975 struct ieee80211_key_conf *key)
e4d6b795
MB		 3976{
3977 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3978 struct b43_wldev *dev;
e4d6b795
MB		 3979 u8 algorithm;
3980 u8 index;
c6dfc9a8 3981 int err;
060210f9 3982 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3983
3984 if (modparam_nohwcrypt)
3985 return -ENOSPC; /* User disabled HW-crypto */
3986
c6dfc9a8 3987 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3988
3989 dev = wl->current_dev;
3990 err = -ENODEV;
3991 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3992 goto out_unlock;
3993
403a3a13 3994 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3995 /* We don't have firmware for the crypto engine.
3996 * Must use software-crypto. */
3997 err = -EOPNOTSUPP;
3998 goto out_unlock;
3999 }
4000
c6dfc9a8 4001 err = -EINVAL;
97359d12
JB		 4002 switch (key->cipher) {
4003 case WLAN_CIPHER_SUITE_WEP40:
4004 algorithm = B43_SEC_ALGO_WEP40;
4005 break;
4006 case WLAN_CIPHER_SUITE_WEP104:
4007 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4008 break;
97359d12 4009 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4010 algorithm = B43_SEC_ALGO_TKIP;
4011 break;
97359d12 4012 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4013 algorithm = B43_SEC_ALGO_AES;
4014 break;
4015 default:
4016 B43_WARN_ON(1);
c6dfc9a8 4017 goto out_unlock;
e4d6b795 4018 }
e4d6b795
MB		 4019 index = (u8) (key->keyidx);
4020 if (index > 3)
e4d6b795 4021 goto out_unlock;
e4d6b795
MB		 4022
4023 switch (cmd) {
4024 case SET_KEY:
035d0243 4025 if (algorithm == B43_SEC_ALGO_TKIP &&
4026 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4027 !modparam_hwtkip)) {
4028 /* We support only pairwise key */
e4d6b795
MB		 4029 err = -EOPNOTSUPP;
4030 goto out_unlock;
4031 }
4032
e808e586 4033 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4034 if (WARN_ON(!sta)) {
4035 err = -EOPNOTSUPP;
4036 goto out_unlock;
4037 }
e808e586 4038 /* Pairwise key with an assigned MAC address. */
e4d6b795 4039 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4040 key->key, key->keylen,
4041 sta->addr, key);
e808e586
MB		 4042 } else {
4043 /* Group key */
4044 err = b43_key_write(dev, index, algorithm,
4045 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4046 }
4047 if (err)
4048 goto out_unlock;
4049
4050 if (algorithm == B43_SEC_ALGO_WEP40 ||
4051 algorithm == B43_SEC_ALGO_WEP104) {
4052 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4053 } else {
4054 b43_hf_write(dev,
4055 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4056 }
4057 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4058 if (algorithm == B43_SEC_ALGO_TKIP)
4059 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4060 break;
4061 case DISABLE_KEY: {
4062 err = b43_key_clear(dev, key->hw_key_idx);
4063 if (err)
4064 goto out_unlock;
4065 break;
4066 }
4067 default:
4068 B43_WARN_ON(1);
4069 }
9cf7f247 4070
e4d6b795 4071out_unlock:
e4d6b795
MB		 4072 if (!err) {
4073 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4074 "mac: %pM\n",
e4d6b795 4075 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4076 sta ? sta->addr : bcast_addr);
9cf7f247 4077 b43_dump_keymemory(dev);
e4d6b795 4078 }
9cf7f247
MB		 4079 mutex_unlock(&wl->mutex);
4080
e4d6b795
MB		 4081 return err;
4082}
4083
40faacc4
MB		 4084static void b43_op_configure_filter(struct ieee80211_hw *hw,
4085 unsigned int changed, unsigned int *fflags,
3ac64bee 4086 u64 multicast)
e4d6b795
MB		 4087{
4088 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4089 struct b43_wldev *dev;
e4d6b795 4090
36dbd954
MB		 4091 mutex_lock(&wl->mutex);
4092 dev = wl->current_dev;
4150c572
JB		 4093 if (!dev) {
4094 *fflags = 0;
36dbd954 4095 goto out_unlock;
e4d6b795 4096 }
4150c572 4097
4150c572
JB		 4098 *fflags &= FIF_PROMISC_IN_BSS |
4099 FIF_ALLMULTI |
4100 FIF_FCSFAIL |
4101 FIF_PLCPFAIL |
4102 FIF_CONTROL |
4103 FIF_OTHER_BSS |
4104 FIF_BCN_PRBRESP_PROMISC;
4105
4106 changed &= FIF_PROMISC_IN_BSS |
4107 FIF_ALLMULTI |
4108 FIF_FCSFAIL |
4109 FIF_PLCPFAIL |
4110 FIF_CONTROL |
4111 FIF_OTHER_BSS |
4112 FIF_BCN_PRBRESP_PROMISC;
4113
4114 wl->filter_flags = *fflags;
4115
4116 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4117 b43_adjust_opmode(dev);
36dbd954
MB		 4118
4119out_unlock:
4120 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4121}
4122
36dbd954
MB		 4123/* Locking: wl->mutex
4124 * Returns the current dev. This might be different from the passed in dev,
4125 * because the core might be gone away while we unlocked the mutex. */
4126static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 4127{
4128 struct b43_wl *wl = dev->wl;
36dbd954 4129 struct b43_wldev *orig_dev;
49d965c8 4130 u32 mask;
e4d6b795 4131
36dbd954
MB		 4132redo:
4133 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4134 return dev;
a19d12d7 4135
f5d40eed 4136 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4137 mutex_unlock(&wl->mutex);
4138 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4139 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4140 mutex_lock(&wl->mutex);
4141 dev = wl->current_dev;
4142 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4143 /* Whoops, aliens ate up the device while we were unlocked. */
4144 return dev;
4145 }
a19d12d7 4146
36dbd954 4147 /* Disable interrupts on the device. */
e4d6b795 4148 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4149 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4150 /* wl->mutex is locked. That is enough. */
4151 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4152 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4153 } else {
4154 spin_lock_irq(&wl->hardirq_lock);
4155 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4156 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4157 spin_unlock_irq(&wl->hardirq_lock);
4158 }
176e9f6a 4159 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4160 orig_dev = dev;
e4d6b795 4161 mutex_unlock(&wl->mutex);
505fb019 4162 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4163 b43_sdio_free_irq(dev);
4164 } else {
a18c715e
RM		 4165 synchronize_irq(dev->dev->irq);
4166 free_irq(dev->dev->irq, dev);
176e9f6a 4167 }
e4d6b795 4168 mutex_lock(&wl->mutex);
36dbd954
MB		 4169 dev = wl->current_dev;
4170 if (!dev)
4171 return dev;
4172 if (dev != orig_dev) {
4173 if (b43_status(dev) >= B43_STAT_STARTED)
4174 goto redo;
4175 return dev;
4176 }
49d965c8
MB		 4177 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4178 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4179
f5d40eed
MB		 4180 /* Drain the TX queue */
4181 while (skb_queue_len(&wl->tx_queue))
4182 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4183
e4d6b795 4184 b43_mac_suspend(dev);
a78b3bb2 4185 b43_leds_exit(dev);
e4d6b795 4186 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4187
4188 return dev;
e4d6b795
MB		 4189}
4190
4191/* Locking: wl->mutex */
4192static int b43_wireless_core_start(struct b43_wldev *dev)
4193{
4194 int err;
4195
4196 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4197
4198 drain_txstatus_queue(dev);
505fb019 4199 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4200 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4201 if (err) {
4202 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4203 goto out;
4204 }
4205 } else {
a18c715e 4206 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4207 b43_interrupt_thread_handler,
4208 IRQF_SHARED, KBUILD_MODNAME, dev);
4209 if (err) {
dedb1eb9 4210 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4211 dev->dev->irq);
3dbba8e2
AH		 4212 goto out;
4213 }
e4d6b795
MB		 4214 }
4215
4216 /* We are ready to run. */
0866b03c 4217 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4218 b43_set_status(dev, B43_STAT_STARTED);
4219
4220 /* Start data flow (TX/RX). */
4221 b43_mac_enable(dev);
13790728 4222 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4223
25985edc 4224 /* Start maintenance work */
e4d6b795
MB		 4225 b43_periodic_tasks_setup(dev);
4226
a78b3bb2
MB		 4227 b43_leds_init(dev);
4228
e4d6b795 4229 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4230out:
e4d6b795
MB		 4231 return err;
4232}
4233
4234/* Get PHY and RADIO versioning numbers */
4235static int b43_phy_versioning(struct b43_wldev *dev)
4236{
4237 struct b43_phy *phy = &dev->phy;
4238 u32 tmp;
4239 u8 analog_type;
4240 u8 phy_type;
4241 u8 phy_rev;
4242 u16 radio_manuf;
4243 u16 radio_ver;
4244 u16 radio_rev;
4245 int unsupported = 0;
4246
4247 /* Get PHY versioning */
4248 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4249 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4250 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4251 phy_rev = (tmp & B43_PHYVER_VERSION);
4252 switch (phy_type) {
4253 case B43_PHYTYPE_A:
4254 if (phy_rev >= 4)
4255 unsupported = 1;
4256 break;
4257 case B43_PHYTYPE_B:
4258 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4259 && phy_rev != 7)
4260 unsupported = 1;
4261 break;
4262 case B43_PHYTYPE_G:
013978b6 4263 if (phy_rev > 9)
e4d6b795
MB		 4264 unsupported = 1;
4265 break;
692d2c0f 4266#ifdef CONFIG_B43_PHY_N
d5c71e46 4267 case B43_PHYTYPE_N:
ab72efdf 4268 if (phy_rev > 9)
d5c71e46
MB		 4269 unsupported = 1;
4270 break;
6b1c7c67
MB		 4271#endif
4272#ifdef CONFIG_B43_PHY_LP
4273 case B43_PHYTYPE_LP:
9d86a2d5 4274 if (phy_rev > 2)
6b1c7c67
MB		 4275 unsupported = 1;
4276 break;
d7520b1d
RM		 4277#endif
4278#ifdef CONFIG_B43_PHY_HT
4279 case B43_PHYTYPE_HT:
4280 if (phy_rev > 1)
4281 unsupported = 1;
4282 break;
1d738e64
RM		 4283#endif
4284#ifdef CONFIG_B43_PHY_LCN
4285 case B43_PHYTYPE_LCN:
4286 if (phy_rev > 1)
4287 unsupported = 1;
4288 break;
d5c71e46 4289#endif
e4d6b795
MB		 4290 default:
4291 unsupported = 1;
6403eab1 4292 }
e4d6b795
MB		 4293 if (unsupported) {
4294 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4295 "(Analog %u, Type %u, Revision %u)\n",
4296 analog_type, phy_type, phy_rev);
4297 return -EOPNOTSUPP;
4298 }
4299 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4300 analog_type, phy_type, phy_rev);
4301
4302 /* Get RADIO versioning */
3fd48508 4303 if (dev->dev->core_rev >= 24) {
544e5d8b
RM		 4304 u16 radio24[3];
4305
4306 for (tmp = 0; tmp < 3; tmp++) {
4307 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4308 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4309 }
4310
4311 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4312 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4313
4314 radio_manuf = 0x17F;
4315 radio_ver = (radio24[2] << 8) | radio24[1];
4316 radio_rev = (radio24[0] & 0xF);
e4d6b795 4317 } else {
3fd48508
RM		 4318 if (dev->dev->chip_id == 0x4317) {
4319 if (dev->dev->chip_rev == 0)
4320 tmp = 0x3205017F;
4321 else if (dev->dev->chip_rev == 1)
4322 tmp = 0x4205017F;
4323 else
4324 tmp = 0x5205017F;
4325 } else {
4326 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4327 B43_RADIOCTL_ID);
4328 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4329 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4330 B43_RADIOCTL_ID);
4331 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4332 << 16;
4333 }
4334 radio_manuf = (tmp & 0x00000FFF);
4335 radio_ver = (tmp & 0x0FFFF000) >> 12;
4336 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4337 }
3fd48508 4338
96c755a3
MB		 4339 if (radio_manuf != 0x17F /* Broadcom */)
4340 unsupported = 1;
e4d6b795
MB		 4341 switch (phy_type) {
4342 case B43_PHYTYPE_A:
4343 if (radio_ver != 0x2060)
4344 unsupported = 1;
4345 if (radio_rev != 1)
4346 unsupported = 1;
4347 if (radio_manuf != 0x17F)
4348 unsupported = 1;
4349 break;
4350 case B43_PHYTYPE_B:
4351 if ((radio_ver & 0xFFF0) != 0x2050)
4352 unsupported = 1;
4353 break;
4354 case B43_PHYTYPE_G:
4355 if (radio_ver != 0x2050)
4356 unsupported = 1;
4357 break;
96c755a3 4358 case B43_PHYTYPE_N:
bb519bee 4359 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4360 unsupported = 1;
4361 break;
6b1c7c67 4362 case B43_PHYTYPE_LP:
9d86a2d5 4363 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4364 unsupported = 1;
4365 break;
d7520b1d
RM		 4366 case B43_PHYTYPE_HT:
4367 if (radio_ver != 0x2059)
4368 unsupported = 1;
4369 break;
1d738e64
RM		 4370 case B43_PHYTYPE_LCN:
4371 if (radio_ver != 0x2064)
4372 unsupported = 1;
4373 break;
e4d6b795
MB		 4374 default:
4375 B43_WARN_ON(1);
4376 }
4377 if (unsupported) {
4378 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4379 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4380 radio_manuf, radio_ver, radio_rev);
4381 return -EOPNOTSUPP;
4382 }
4383 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4384 radio_manuf, radio_ver, radio_rev);
4385
4386 phy->radio_manuf = radio_manuf;
4387 phy->radio_ver = radio_ver;
4388 phy->radio_rev = radio_rev;
4389
4390 phy->analog = analog_type;
4391 phy->type = phy_type;
4392 phy->rev = phy_rev;
4393
4394 return 0;
4395}
4396
4397static void setup_struct_phy_for_init(struct b43_wldev *dev,
4398 struct b43_phy *phy)
4399{
e4d6b795 4400 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4401 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4402 /* PHY TX errors counter. */
4403 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4404
4405#if B43_DEBUG
4406 phy->phy_locked = 0;
4407 phy->radio_locked = 0;
4408#endif
e4d6b795
MB		 4409}
4410
4411static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4412{
aa6c7ae2
MB		 4413 dev->dfq_valid = 0;
4414
6a724d68
MB		 4415 /* Assume the radio is enabled. If it's not enabled, the state will
4416 * immediately get fixed on the first periodic work run. */
4417 dev->radio_hw_enable = 1;
e4d6b795
MB		 4418
4419 /* Stats */
4420 memset(&dev->stats, 0, sizeof(dev->stats));
4421
4422 setup_struct_phy_for_init(dev, &dev->phy);
4423
4424 /* IRQ related flags */
4425 dev->irq_reason = 0;
4426 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4427 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4428 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4429 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4430
4431 dev->mac_suspended = 1;
4432
4433 /* Noise calculation context */
4434 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4435}
4436
4437static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4438{
0581483a 4439 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4440 u64 hf;
e4d6b795 4441
1855ba78
MB		 4442 if (!modparam_btcoex)
4443 return;
95de2841 4444 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4445 return;
4446 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4447 return;
4448
4449 hf = b43_hf_read(dev);
95de2841 4450 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4451 hf |= B43_HF_BTCOEXALT;
4452 else
4453 hf |= B43_HF_BTCOEX;
4454 b43_hf_write(dev, hf);
e4d6b795
MB		 4455}
4456
4457static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4458{
4459 if (!modparam_btcoex)
4460 return;
4461 //TODO
e4d6b795
MB		 4462}
4463
4464static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4465{
d48ae5c8 4466 struct ssb_bus *bus;
e4d6b795
MB		 4467 u32 tmp;
4468
d48ae5c8
RM		 4469 if (dev->dev->bus_type != B43_BUS_SSB)
4470 return;
4471
4472 bus = dev->dev->sdev->bus;
4473
0fd82eaf
RM		 4474 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4475 (bus->chip_id == 0x4312)) {
d48ae5c8 4476 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4477 tmp &= ~SSB_IMCFGLO_REQTO;
4478 tmp &= ~SSB_IMCFGLO_SERTO;
4479 tmp |= 0x3;
d48ae5c8 4480 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4481 ssb_commit_settings(bus);
e4d6b795 4482 }
e4d6b795
MB		 4483}
4484
d59f720d
MB		 4485static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4486{
4487 u16 pu_delay;
4488
4489 /* The time value is in microseconds. */
4490 if (dev->phy.type == B43_PHYTYPE_A)
4491 pu_delay = 3700;
4492 else
4493 pu_delay = 1050;
05c914fe 4494 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4495 pu_delay = 500;
4496 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4497 pu_delay = max(pu_delay, (u16)2400);
4498
4499 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4500}
4501
4502/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4503static void b43_set_pretbtt(struct b43_wldev *dev)
4504{
4505 u16 pretbtt;
4506
4507 /* The time value is in microseconds. */
05c914fe 4508 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4509 pretbtt = 2;
4510 } else {
4511 if (dev->phy.type == B43_PHYTYPE_A)
4512 pretbtt = 120;
4513 else
4514 pretbtt = 250;
4515 }
4516 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4517 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4518}
4519
e4d6b795
MB		 4520/* Shutdown a wireless core */
4521/* Locking: wl->mutex */
4522static void b43_wireless_core_exit(struct b43_wldev *dev)
4523{
1f7d87b0 4524 u32 macctl;
e4d6b795 4525
36dbd954
MB		 4526 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4527 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4528 return;
84c164a3
JL		 4529
4530 /* Unregister HW RNG driver */
4531 b43_rng_exit(dev->wl);
4532
e4d6b795
MB		 4533 b43_set_status(dev, B43_STAT_UNINIT);
4534
1f7d87b0
MB		 4535 /* Stop the microcode PSM. */
4536 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4537 macctl &= ~B43_MACCTL_PSM_RUN;
4538 macctl |= B43_MACCTL_PSM_JMP0;
4539 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4540
e4d6b795 4541 b43_dma_free(dev);
5100d5ac 4542 b43_pio_free(dev);
e4d6b795 4543 b43_chip_exit(dev);
cb24f57f 4544 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4545 if (dev->wl->current_beacon) {
4546 dev_kfree_skb_any(dev->wl->current_beacon);
4547 dev->wl->current_beacon = NULL;
4548 }
4549
24ca39d6
RM		 4550 b43_device_disable(dev, 0);
4551 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4552}
4553
4554/* Initialize a wireless core */
4555static int b43_wireless_core_init(struct b43_wldev *dev)
4556{
0581483a 4557 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4558 struct b43_phy *phy = &dev->phy;
4559 int err;
a259d6a4 4560 u64 hf;
e4d6b795
MB		 4561
4562 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4563
24ca39d6 4564 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4565 if (err)
4566 goto out;
4da909e7
RM		 4567 if (!b43_device_is_enabled(dev))
4568 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4569
fb11137a 4570 /* Reset all data structures. */
e4d6b795 4571 setup_struct_wldev_for_init(dev);
fb11137a 4572 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4573
4574 /* Enable IRQ routing to this device. */
6cbab0d9 4575 switch (dev->dev->bus_type) {
42c9a458
RM		 4576#ifdef CONFIG_B43_BCMA
4577 case B43_BUS_BCMA:
4578 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4579 dev->dev->bdev, true);
4580 break;
4581#endif
6cbab0d9
RM		 4582#ifdef CONFIG_B43_SSB
4583 case B43_BUS_SSB:
4584 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4585 dev->dev->sdev);
4586 break;
4587#endif
4588 }
e4d6b795
MB		 4589
4590 b43_imcfglo_timeouts_workaround(dev);
4591 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4592 if (phy->ops->prepare_hardware) {
4593 err = phy->ops->prepare_hardware(dev);
ef1a628d 4594 if (err)
fb11137a 4595 goto err_busdown;
ef1a628d 4596 }
e4d6b795
MB		 4597 err = b43_chip_init(dev);
4598 if (err)
fb11137a 4599 goto err_busdown;
e4d6b795 4600 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4601 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4602 hf = b43_hf_read(dev);
4603 if (phy->type == B43_PHYTYPE_G) {
4604 hf |= B43_HF_SYMW;
4605 if (phy->rev == 1)
4606 hf |= B43_HF_GDCW;
95de2841 4607 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4608 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4609 }
4610 if (phy->radio_ver == 0x2050) {
4611 if (phy->radio_rev == 6)
4612 hf |= B43_HF_4318TSSI;
4613 if (phy->radio_rev < 6)
4614 hf |= B43_HF_VCORECALC;
e4d6b795 4615 }
1cc8f476
MB		 4616 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4617 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4618#ifdef CONFIG_SSB_DRIVER_PCICORE
6cbab0d9
RM		 4619 if (dev->dev->bus_type == B43_BUS_SSB &&
4620 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4621 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4622 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4623#endif
25d3ef59 4624 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4625 b43_hf_write(dev, hf);
4626
74cfdba7
MB		 4627 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4628 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4629 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4630 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4631
4632 /* Disable sending probe responses from firmware.
4633 * Setting the MaxTime to one usec will always trigger
4634 * a timeout, so we never send any probe resp.
4635 * A timeout of zero is infinite. */
4636 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4637
4638 b43_rate_memory_init(dev);
5042c507 4639 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4640
4641 /* Minimum Contention Window */
c5a079f4 4642 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4643 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4644 else
e4d6b795 4645 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4646 /* Maximum Contention Window */
4647 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4648
505fb019
RM		 4649 if (b43_bus_host_is_pcmcia(dev->dev) ||
4650 b43_bus_host_is_sdio(dev->dev) ||
9e3bd919 4651 dev->use_pio) {
5100d5ac
MB		 4652 dev->__using_pio_transfers = 1;
4653 err = b43_pio_init(dev);
4654 } else {
4655 dev->__using_pio_transfers = 0;
4656 err = b43_dma_init(dev);
4657 }
e4d6b795
MB		 4658 if (err)
4659 goto err_chip_exit;
03b29773 4660 b43_qos_init(dev);
d59f720d 4661 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4662 b43_bluetooth_coext_enable(dev);
4663
24ca39d6 4664 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4665 b43_upload_card_macaddress(dev);
e4d6b795 4666 b43_security_init(dev);
e4d6b795 4667
5ab9549a 4668 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4669
4670 b43_set_status(dev, B43_STAT_INITIALIZED);
4671
84c164a3
JL		 4672 /* Register HW RNG driver */
4673 b43_rng_init(dev->wl);
4674
1a8d1227 4675out:
e4d6b795
MB		 4676 return err;
4677
ef1a628d 4678err_chip_exit:
e4d6b795 4679 b43_chip_exit(dev);
ef1a628d 4680err_busdown:
24ca39d6 4681 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4682 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4683 return err;
4684}
4685
40faacc4 4686static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4687 struct ieee80211_vif *vif)
e4d6b795
MB		 4688{
4689 struct b43_wl *wl = hw_to_b43_wl(hw);
4690 struct b43_wldev *dev;
e4d6b795 4691 int err = -EOPNOTSUPP;
4150c572
JB		 4692
4693 /* TODO: allow WDS/AP devices to coexist */
4694
1ed32e4f
JB		 4695 if (vif->type != NL80211_IFTYPE_AP &&
4696 vif->type != NL80211_IFTYPE_MESH_POINT &&
4697 vif->type != NL80211_IFTYPE_STATION &&
4698 vif->type != NL80211_IFTYPE_WDS &&
4699 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4700 return -EOPNOTSUPP;
e4d6b795
MB		 4701
4702 mutex_lock(&wl->mutex);
4150c572 4703 if (wl->operating)
e4d6b795
MB		 4704 goto out_mutex_unlock;
4705
1ed32e4f 4706 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4707
4708 dev = wl->current_dev;
4150c572 4709 wl->operating = 1;
1ed32e4f
JB		 4710 wl->vif = vif;
4711 wl->if_type = vif->type;
4712 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4713
4150c572 4714 b43_adjust_opmode(dev);
d59f720d
MB		 4715 b43_set_pretbtt(dev);
4716 b43_set_synth_pu_delay(dev, 0);
4150c572 4717 b43_upload_card_macaddress(dev);
4150c572
JB		 4718
4719 err = 0;
4720 out_mutex_unlock:
4721 mutex_unlock(&wl->mutex);
4722
2a190322
FF		 4723 if (err == 0)
4724 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4725
4150c572
JB		 4726 return err;
4727}
4728
40faacc4 4729static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4730 struct ieee80211_vif *vif)
4150c572
JB		 4731{
4732 struct b43_wl *wl = hw_to_b43_wl(hw);
4733 struct b43_wldev *dev = wl->current_dev;
4150c572 4734
1ed32e4f 4735 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4736
4737 mutex_lock(&wl->mutex);
4738
4739 B43_WARN_ON(!wl->operating);
1ed32e4f 4740 B43_WARN_ON(wl->vif != vif);
32bfd35d 4741 wl->vif = NULL;
4150c572
JB		 4742
4743 wl->operating = 0;
4744
4150c572
JB		 4745 b43_adjust_opmode(dev);
4746 memset(wl->mac_addr, 0, ETH_ALEN);
4747 b43_upload_card_macaddress(dev);
4150c572
JB		 4748
4749 mutex_unlock(&wl->mutex);
4750}
4751
40faacc4 4752static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4753{
4754 struct b43_wl *wl = hw_to_b43_wl(hw);
4755 struct b43_wldev *dev = wl->current_dev;
4756 int did_init = 0;
923403b8 4757 int err = 0;
4150c572 4758
7be1bb6b
MB		 4759 /* Kill all old instance specific information to make sure
4760 * the card won't use it in the short timeframe between start
4761 * and mac80211 reconfiguring it. */
4762 memset(wl->bssid, 0, ETH_ALEN);
4763 memset(wl->mac_addr, 0, ETH_ALEN);
4764 wl->filter_flags = 0;
4765 wl->radiotap_enabled = 0;
e6f5b934 4766 b43_qos_clear(wl);
6b4bec01
MB		 4767 wl->beacon0_uploaded = 0;
4768 wl->beacon1_uploaded = 0;
4769 wl->beacon_templates_virgin = 1;
fd4973c5 4770 wl->radio_enabled = 1;
7be1bb6b 4771
4150c572
JB		 4772 mutex_lock(&wl->mutex);
4773
e4d6b795
MB		 4774 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4775 err = b43_wireless_core_init(dev);
f41f3f37 4776 if (err)
e4d6b795
MB		 4777 goto out_mutex_unlock;
4778 did_init = 1;
4779 }
4150c572 4780
e4d6b795
MB		 4781 if (b43_status(dev) < B43_STAT_STARTED) {
4782 err = b43_wireless_core_start(dev);
4783 if (err) {
4784 if (did_init)
4785 b43_wireless_core_exit(dev);
4786 goto out_mutex_unlock;
4787 }
4788 }
4789
f41f3f37
JB		 4790 /* XXX: only do if device doesn't support rfkill irq */
4791 wiphy_rfkill_start_polling(hw->wiphy);
4792
4150c572 4793 out_mutex_unlock:
e4d6b795
MB		 4794 mutex_unlock(&wl->mutex);
4795
2a190322
FF		 4796 /* reload configuration */
4797 b43_op_config(hw, ~0);
4798
e4d6b795
MB		 4799 return err;
4800}
4801
40faacc4 4802static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4803{
4804 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4805 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4806
a82d9922 4807 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4808
e4d6b795 4809 mutex_lock(&wl->mutex);
36dbd954
MB		 4810 if (b43_status(dev) >= B43_STAT_STARTED) {
4811 dev = b43_wireless_core_stop(dev);
4812 if (!dev)
4813 goto out_unlock;
4814 }
4150c572 4815 b43_wireless_core_exit(dev);
fd4973c5 4816 wl->radio_enabled = 0;
36dbd954
MB		 4817
4818out_unlock:
e4d6b795 4819 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4820
4821 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4822}
4823
17741cdc
JB		 4824static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4825 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4826{
4827 struct b43_wl *wl = hw_to_b43_wl(hw);
4828
8f611288 4829 /* FIXME: add locking */
9d139c81 4830 b43_update_templates(wl);
e66fee6a
MB		 4831
4832 return 0;
4833}
4834
38968d09
JB		 4835static void b43_op_sta_notify(struct ieee80211_hw *hw,
4836 struct ieee80211_vif *vif,
4837 enum sta_notify_cmd notify_cmd,
17741cdc 4838 struct ieee80211_sta *sta)
38968d09
JB		 4839{
4840 struct b43_wl *wl = hw_to_b43_wl(hw);
4841
4842 B43_WARN_ON(!vif || wl->vif != vif);
4843}
4844
25d3ef59
MB		 4845static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4846{
4847 struct b43_wl *wl = hw_to_b43_wl(hw);
4848 struct b43_wldev *dev;
4849
4850 mutex_lock(&wl->mutex);
4851 dev = wl->current_dev;
4852 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4853 /* Disable CFP update during scan on other channels. */
4854 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4855 }
4856 mutex_unlock(&wl->mutex);
4857}
4858
4859static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4860{
4861 struct b43_wl *wl = hw_to_b43_wl(hw);
4862 struct b43_wldev *dev;
4863
4864 mutex_lock(&wl->mutex);
4865 dev = wl->current_dev;
4866 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4867 /* Re-enable CFP update. */
4868 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4869 }
4870 mutex_unlock(&wl->mutex);
4871}
4872
354b4f04
JL		 4873static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4874 struct survey_info *survey)
4875{
4876 struct b43_wl *wl = hw_to_b43_wl(hw);
4877 struct b43_wldev *dev = wl->current_dev;
4878 struct ieee80211_conf *conf = &hw->conf;
4879
4880 if (idx != 0)
4881 return -ENOENT;
4882
4883 survey->channel = conf->channel;
4884 survey->filled = SURVEY_INFO_NOISE_DBM;
4885 survey->noise = dev->stats.link_noise;
4886
4887 return 0;
4888}
4889
e4d6b795 4890static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4891 .tx = b43_op_tx,
4892 .conf_tx = b43_op_conf_tx,
4893 .add_interface = b43_op_add_interface,
4894 .remove_interface = b43_op_remove_interface,
4895 .config = b43_op_config,
c7ab5ef9 4896 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4897 .configure_filter = b43_op_configure_filter,
4898 .set_key = b43_op_set_key,
035d0243 4899 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 4900 .get_stats = b43_op_get_stats,
08e87a83
AF		 4901 .get_tsf = b43_op_get_tsf,
4902 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4903 .start = b43_op_start,
4904 .stop = b43_op_stop,
e66fee6a 4905 .set_tim = b43_op_beacon_set_tim,
38968d09 4906 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4907 .sw_scan_start = b43_op_sw_scan_start_notifier,
4908 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 4909 .get_survey = b43_op_get_survey,
f41f3f37 4910 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4911};
4912
4913/* Hard-reset the chip. Do not call this directly.
4914 * Use b43_controller_restart()
4915 */
4916static void b43_chip_reset(struct work_struct *work)
4917{
4918 struct b43_wldev *dev =
4919 container_of(work, struct b43_wldev, restart_work);
4920 struct b43_wl *wl = dev->wl;
4921 int err = 0;
4922 int prev_status;
4923
4924 mutex_lock(&wl->mutex);
4925
4926 prev_status = b43_status(dev);
4927 /* Bring the device down... */
36dbd954
MB		 4928 if (prev_status >= B43_STAT_STARTED) {
4929 dev = b43_wireless_core_stop(dev);
4930 if (!dev) {
4931 err = -ENODEV;
4932 goto out;
4933 }
4934 }
e4d6b795
MB		 4935 if (prev_status >= B43_STAT_INITIALIZED)
4936 b43_wireless_core_exit(dev);
4937
4938 /* ...and up again. */
4939 if (prev_status >= B43_STAT_INITIALIZED) {
4940 err = b43_wireless_core_init(dev);
4941 if (err)
4942 goto out;
4943 }
4944 if (prev_status >= B43_STAT_STARTED) {
4945 err = b43_wireless_core_start(dev);
4946 if (err) {
4947 b43_wireless_core_exit(dev);
4948 goto out;
4949 }
4950 }
3bf0a32e
MB		 4951out:
4952 if (err)
4953 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 4954 mutex_unlock(&wl->mutex);
2a190322
FF		 4955
4956 if (err) {
e4d6b795 4957 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 4958 return;
4959 }
4960
4961 /* reload configuration */
4962 b43_op_config(wl->hw, ~0);
4963 if (wl->vif)
4964 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4965
4966 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 4967}
4968
bb1eeff1 4969static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4970 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4971{
4972 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4973
bb1eeff1
MB		 4974 if (have_2ghz_phy)
4975 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4976 if (dev->phy.type == B43_PHYTYPE_N) {
4977 if (have_5ghz_phy)
4978 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4979 } else {
4980 if (have_5ghz_phy)
4981 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4982 }
96c755a3 4983
bb1eeff1
MB		 4984 dev->phy.supports_2ghz = have_2ghz_phy;
4985 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4986
4987 return 0;
4988}
4989
4990static void b43_wireless_core_detach(struct b43_wldev *dev)
4991{
4992 /* We release firmware that late to not be required to re-request
4993 * is all the time when we reinit the core. */
4994 b43_release_firmware(dev);
fb11137a 4995 b43_phy_free(dev);
e4d6b795
MB		 4996}
4997
4998static int b43_wireless_core_attach(struct b43_wldev *dev)
4999{
5000 struct b43_wl *wl = dev->wl;
6cbab0d9 5001 struct pci_dev *pdev = NULL;
e4d6b795 5002 int err;
40c62269 5003 u32 tmp;
96c755a3 5004 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 5005
5006 /* Do NOT do any device initialization here.
5007 * Do it in wireless_core_init() instead.
5008 * This function is for gathering basic information about the HW, only.
5009 * Also some structs may be set up here. But most likely you want to have
5010 * that in core_init(), too.
5011 */
5012
6cbab0d9
RM		 5013#ifdef CONFIG_B43_SSB
5014 if (dev->dev->bus_type == B43_BUS_SSB &&
5015 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5016 pdev = dev->dev->sdev->bus->host_pci;
5017#endif
5018
24ca39d6 5019 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5020 if (err) {
5021 b43err(wl, "Bus powerup failed\n");
5022 goto out;
5023 }
e4d6b795 5024
6cbab0d9
RM		 5025 /* Get the PHY type. */
5026 switch (dev->dev->bus_type) {
42c9a458
RM		 5027#ifdef CONFIG_B43_BCMA
5028 case B43_BUS_BCMA:
40c62269
RM		 5029 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5030 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5031 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5032 break;
5033#endif
6cbab0d9
RM		 5034#ifdef CONFIG_B43_SSB
5035 case B43_BUS_SSB:
5036 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5037 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5038 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5039 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5040 } else
5041 B43_WARN_ON(1);
5042 break;
5043#endif
5044 }
e4d6b795 5045
96c755a3 5046 dev->phy.gmode = have_2ghz_phy;
fd4973c5 5047 dev->phy.radio_on = 1;
4da909e7 5048 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5049
5050 err = b43_phy_versioning(dev);
5051 if (err)
21954c36 5052 goto err_powerdown;
e4d6b795
MB		 5053 /* Check if this device supports multiband. */
5054 if (!pdev ||
5055 (pdev->device != 0x4312 &&
5056 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5057 /* No multiband support. */
96c755a3
MB		 5058 have_2ghz_phy = 0;
5059 have_5ghz_phy = 0;
e4d6b795
MB		 5060 switch (dev->phy.type) {
5061 case B43_PHYTYPE_A:
96c755a3 5062 have_5ghz_phy = 1;
e4d6b795 5063 break;
9d86a2d5 5064 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 5065#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 5066 have_5ghz_phy = 1;
86b2892a 5067#endif
e4d6b795 5068 case B43_PHYTYPE_G:
96c755a3 5069 case B43_PHYTYPE_N:
8b9bda75
RM		 5070 case B43_PHYTYPE_HT:
5071 case B43_PHYTYPE_LCN:
96c755a3 5072 have_2ghz_phy = 1;
e4d6b795
MB		 5073 break;
5074 default:
5075 B43_WARN_ON(1);
5076 }
5077 }
96c755a3
MB		 5078 if (dev->phy.type == B43_PHYTYPE_A) {
5079 /* FIXME */
5080 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5081 err = -EOPNOTSUPP;
5082 goto err_powerdown;
5083 }
2e35af14
MB		 5084 if (1 /* disable A-PHY */) {
5085 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 5086 if (dev->phy.type != B43_PHYTYPE_N &&
5087 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 5088 have_2ghz_phy = 1;
5089 have_5ghz_phy = 0;
5090 }
5091 }
5092
fb11137a
MB		 5093 err = b43_phy_allocate(dev);
5094 if (err)
5095 goto err_powerdown;
5096
96c755a3 5097 dev->phy.gmode = have_2ghz_phy;
4da909e7 5098 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5099
5100 err = b43_validate_chipaccess(dev);
5101 if (err)
fb11137a 5102 goto err_phy_free;
bb1eeff1 5103 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5104 if (err)
fb11137a 5105 goto err_phy_free;
e4d6b795
MB		 5106
5107 /* Now set some default "current_dev" */
5108 if (!wl->current_dev)
5109 wl->current_dev = dev;
5110 INIT_WORK(&dev->restart_work, b43_chip_reset);
5111
cb24f57f 5112 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5113 b43_device_disable(dev, 0);
5114 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5115
5116out:
5117 return err;
5118
fb11137a
MB		 5119err_phy_free:
5120 b43_phy_free(dev);
e4d6b795 5121err_powerdown:
24ca39d6 5122 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5123 return err;
5124}
5125
482f0538 5126static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5127{
5128 struct b43_wldev *wldev;
5129 struct b43_wl *wl;
5130
3bf0a32e
MB		 5131 /* Do not cancel ieee80211-workqueue based work here.
5132 * See comment in b43_remove(). */
5133
74abacb6 5134 wldev = b43_bus_get_wldev(dev);
e4d6b795 5135 wl = wldev->wl;
e4d6b795
MB		 5136 b43_debugfs_remove_device(wldev);
5137 b43_wireless_core_detach(wldev);
5138 list_del(&wldev->list);
5139 wl->nr_devs--;
74abacb6 5140 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5141 kfree(wldev);
5142}
5143
482f0538 5144static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5145{
5146 struct b43_wldev *wldev;
e4d6b795
MB		 5147 int err = -ENOMEM;
5148
e4d6b795
MB		 5149 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5150 if (!wldev)
5151 goto out;
5152
9e3bd919 5153 wldev->use_pio = b43_modparam_pio;
482f0538 5154 wldev->dev = dev;
e4d6b795
MB		 5155 wldev->wl = wl;
5156 b43_set_status(wldev, B43_STAT_UNINIT);
5157 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5158 INIT_LIST_HEAD(&wldev->list);
5159
5160 err = b43_wireless_core_attach(wldev);
5161 if (err)
5162 goto err_kfree_wldev;
5163
5164 list_add(&wldev->list, &wl->devlist);
5165 wl->nr_devs++;
74abacb6 5166 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5167 b43_debugfs_add_device(wldev);
5168
5169 out:
5170 return err;
5171
5172 err_kfree_wldev:
5173 kfree(wldev);
5174 return err;
5175}
5176
9fc38458
MB		 5177#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5178 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5179 (pdev->device == _device) && \
5180 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5181 (pdev->subsystem_device == _subdevice) )
5182
e4d6b795
MB		 5183static void b43_sprom_fixup(struct ssb_bus *bus)
5184{
1855ba78
MB		 5185 struct pci_dev *pdev;
5186
e4d6b795
MB		 5187 /* boardflags workarounds */
5188 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5189 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 5190 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 5191 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5192 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 5193 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5194 if (bus->bustype == SSB_BUSTYPE_PCI) {
5195 pdev = bus->host_pci;
9fc38458 5196 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5197 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5198 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5199 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5200 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5201 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5202 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5203 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5204 }
e4d6b795
MB		 5205}
5206
482f0538 5207static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5208{
5209 struct ieee80211_hw *hw = wl->hw;
5210
482f0538 5211 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5212 ieee80211_free_hw(hw);
5213}
5214
d1507051 5215static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5216{
d1507051 5217 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5218 struct ieee80211_hw *hw;
5219 struct b43_wl *wl;
2729df25 5220 char chip_name[6];
e4d6b795
MB		 5221
5222 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5223 if (!hw) {
5224 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5225 return ERR_PTR(-ENOMEM);
e4d6b795 5226 }
403a3a13 5227 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5228
5229 /* fill hw info */
605a0bd6 5230 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5231 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5232
f59ac048
LR		 5233 hw->wiphy->interface_modes =
5234 BIT(NL80211_IFTYPE_AP) |
5235 BIT(NL80211_IFTYPE_MESH_POINT) |
5236 BIT(NL80211_IFTYPE_STATION) |
5237 BIT(NL80211_IFTYPE_WDS) |
5238 BIT(NL80211_IFTYPE_ADHOC);
5239
403a3a13
MB		 5240 hw->queues = modparam_qos ? 4 : 1;
5241 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 5242 hw->max_rates = 2;
e4d6b795 5243 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5244 if (is_valid_ether_addr(sprom->et1mac))
5245 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5246 else
95de2841 5247 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5248
403a3a13 5249 /* Initialize struct b43_wl */
e4d6b795 5250 wl->hw = hw;
e4d6b795 5251 mutex_init(&wl->mutex);
36dbd954 5252 spin_lock_init(&wl->hardirq_lock);
e4d6b795 5253 INIT_LIST_HEAD(&wl->devlist);
a82d9922 5254 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5255 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 5256 INIT_WORK(&wl->tx_work, b43_tx_work);
5257 skb_queue_head_init(&wl->tx_queue);
e4d6b795 5258
2729df25
RM		 5259 snprintf(chip_name, ARRAY_SIZE(chip_name),
5260 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5261 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5262 dev->core_rev);
0355a345 5263 return wl;
e4d6b795
MB		 5264}
5265
3c65ab62
RM		 5266#ifdef CONFIG_B43_BCMA
5267static int b43_bcma_probe(struct bcma_device *core)
5268{
397915c3 5269 struct b43_bus_dev *dev;
24aad3f4
RM		 5270 struct b43_wl *wl;
5271 int err;
397915c3
RM		 5272
5273 dev = b43_bus_dev_bcma_init(core);
5274 if (!dev)
5275 return -ENODEV;
5276
24aad3f4
RM		 5277 wl = b43_wireless_init(dev);
5278 if (IS_ERR(wl)) {
5279 err = PTR_ERR(wl);
5280 goto bcma_out;
5281 }
5282
5283 err = b43_one_core_attach(dev, wl);
5284 if (err)
5285 goto bcma_err_wireless_exit;
5286
5287 err = ieee80211_register_hw(wl->hw);
5288 if (err)
5289 goto bcma_err_one_core_detach;
5290 b43_leds_register(wl->current_dev);
5291
5292bcma_out:
5293 return err;
5294
5295bcma_err_one_core_detach:
5296 b43_one_core_detach(dev);
5297bcma_err_wireless_exit:
5298 ieee80211_free_hw(wl->hw);
5299 return err;
3c65ab62
RM		 5300}
5301
5302static void b43_bcma_remove(struct bcma_device *core)
5303{
24aad3f4
RM		 5304 struct b43_wldev *wldev = bcma_get_drvdata(core);
5305 struct b43_wl *wl = wldev->wl;
5306
5307 /* We must cancel any work here before unregistering from ieee80211,
5308 * as the ieee80211 unreg will destroy the workqueue. */
5309 cancel_work_sync(&wldev->restart_work);
5310
5311 /* Restore the queues count before unregistering, because firmware detect
5312 * might have modified it. Restoring is important, so the networking
5313 * stack can properly free resources. */
5314 wl->hw->queues = wl->mac80211_initially_registered_queues;
5315 b43_leds_stop(wldev);
5316 ieee80211_unregister_hw(wl->hw);
5317
5318 b43_one_core_detach(wldev->dev);
5319
5320 b43_leds_unregister(wl);
5321
5322 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5323}
5324
5325static struct bcma_driver b43_bcma_driver = {
5326 .name = KBUILD_MODNAME,
5327 .id_table = b43_bcma_tbl,
5328 .probe = b43_bcma_probe,
5329 .remove = b43_bcma_remove,
5330};
5331#endif
5332
aec7ffdf 5333#ifdef CONFIG_B43_SSB
aa63418a
RM		 5334static
5335int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5336{
482f0538 5337 struct b43_bus_dev *dev;
e4d6b795
MB		 5338 struct b43_wl *wl;
5339 int err;
5340 int first = 0;
5341
482f0538 5342 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5343 if (!dev)
5344 return -ENOMEM;
482f0538 5345
aa63418a 5346 wl = ssb_get_devtypedata(sdev);
e4d6b795
MB		 5347 if (!wl) {
5348 /* Probing the first core. Must setup common struct b43_wl */
5349 first = 1;
aa63418a 5350 b43_sprom_fixup(sdev->bus);
d1507051 5351 wl = b43_wireless_init(dev);
0355a345
RM		 5352 if (IS_ERR(wl)) {
5353 err = PTR_ERR(wl);
e4d6b795 5354 goto out;
0355a345 5355 }
aa63418a
RM		 5356 ssb_set_devtypedata(sdev, wl);
5357 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
e4d6b795
MB		 5358 }
5359 err = b43_one_core_attach(dev, wl);
5360 if (err)
5361 goto err_wireless_exit;
5362
5363 if (first) {
5364 err = ieee80211_register_hw(wl->hw);
5365 if (err)
5366 goto err_one_core_detach;
a78b3bb2 5367 b43_leds_register(wl->current_dev);
e4d6b795
MB		 5368 }
5369
5370 out:
5371 return err;
5372
5373 err_one_core_detach:
5374 b43_one_core_detach(dev);
5375 err_wireless_exit:
5376 if (first)
5377 b43_wireless_exit(dev, wl);
5378 return err;
5379}
5380
aa63418a 5381static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5382{
aa63418a
RM		 5383 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5384 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5385 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5386
3bf0a32e
MB		 5387 /* We must cancel any work here before unregistering from ieee80211,
5388 * as the ieee80211 unreg will destroy the workqueue. */
5389 cancel_work_sync(&wldev->restart_work);
5390
e4d6b795 5391 B43_WARN_ON(!wl);
403a3a13
MB		 5392 if (wl->current_dev == wldev) {
5393 /* Restore the queues count before unregistering, because firmware detect
5394 * might have modified it. Restoring is important, so the networking
5395 * stack can properly free resources. */
5396 wl->hw->queues = wl->mac80211_initially_registered_queues;
82905ace 5397 b43_leds_stop(wldev);
e4d6b795 5398 ieee80211_unregister_hw(wl->hw);
403a3a13 5399 }
e4d6b795 5400
e61b52d1 5401 b43_one_core_detach(dev);
e4d6b795
MB		 5402
5403 if (list_empty(&wl->devlist)) {
727c9885 5404 b43_leds_unregister(wl);
e4d6b795
MB		 5405 /* Last core on the chip unregistered.
5406 * We can destroy common struct b43_wl.
5407 */
e61b52d1 5408 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5409 }
5410}
5411
aec7ffdf
RM		 5412static struct ssb_driver b43_ssb_driver = {
5413 .name = KBUILD_MODNAME,
5414 .id_table = b43_ssb_tbl,
5415 .probe = b43_ssb_probe,
5416 .remove = b43_ssb_remove,
5417};
5418#endif /* CONFIG_B43_SSB */
5419
e4d6b795
MB		 5420/* Perform a hardware reset. This can be called from any context. */
5421void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5422{
5423 /* Must avoid requeueing, if we are in shutdown. */
5424 if (b43_status(dev) < B43_STAT_INITIALIZED)
5425 return;
5426 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5427 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5428}
5429
26bc783f
MB		 5430static void b43_print_driverinfo(void)
5431{
5432 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5433 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5434
5435#ifdef CONFIG_B43_PCI_AUTOSELECT
5436 feat_pci = "P";
5437#endif
5438#ifdef CONFIG_B43_PCMCIA
5439 feat_pcmcia = "M";
5440#endif
692d2c0f 5441#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5442 feat_nphy = "N";
5443#endif
5444#ifdef CONFIG_B43_LEDS
5445 feat_leds = "L";
3dbba8e2
AH		 5446#endif
5447#ifdef CONFIG_B43_SDIO
5448 feat_sdio = "S";
26bc783f
MB		 5449#endif
5450 printk(KERN_INFO "Broadcom 43xx driver loaded "
3dbba8e2 5451 "[ Features: %s%s%s%s%s, Firmware-ID: "
26bc783f
MB		 5452 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5453 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5454 feat_leds, feat_sdio);
26bc783f
MB		 5455}
5456
e4d6b795
MB		 5457static int __init b43_init(void)
5458{
5459 int err;
5460
5461 b43_debugfs_init();
5462 err = b43_pcmcia_init();
5463 if (err)
5464 goto err_dfs_exit;
3dbba8e2 5465 err = b43_sdio_init();
e4d6b795
MB		 5466 if (err)
5467 goto err_pcmcia_exit;
3c65ab62
RM		 5468#ifdef CONFIG_B43_BCMA
5469 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5470 if (err)
5471 goto err_sdio_exit;
3c65ab62 5472#endif
aec7ffdf 5473#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5474 err = ssb_driver_register(&b43_ssb_driver);
5475 if (err)
5476 goto err_bcma_driver_exit;
aec7ffdf 5477#endif
26bc783f 5478 b43_print_driverinfo();
e4d6b795
MB		 5479
5480 return err;
5481
aec7ffdf 5482#ifdef CONFIG_B43_SSB
3c65ab62 5483err_bcma_driver_exit:
aec7ffdf 5484#endif
3c65ab62
RM		 5485#ifdef CONFIG_B43_BCMA
5486 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5487err_sdio_exit:
3c65ab62 5488#endif
3dbba8e2 5489 b43_sdio_exit();
e4d6b795
MB		 5490err_pcmcia_exit:
5491 b43_pcmcia_exit();
5492err_dfs_exit:
5493 b43_debugfs_exit();
5494 return err;
5495}
5496
5497static void __exit b43_exit(void)
5498{
aec7ffdf 5499#ifdef CONFIG_B43_SSB
e4d6b795 5500 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5501#endif
3c65ab62
RM		 5502#ifdef CONFIG_B43_BCMA
5503 bcma_driver_unregister(&b43_bcma_driver);
5504#endif
3dbba8e2 5505 b43_sdio_exit();
e4d6b795
MB		 5506 b43_pcmcia_exit();
5507 b43_debugfs_exit();
5508}
5509
5510module_init(b43_init)
5511module_exit(b43_exit)
Ubuntu Hirsute Linux kernel mirror