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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
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e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
47#include "phy.h"
48#include "dma.h"
49#include "pio.h"
50#include "sysfs.h"
51#include "xmit.h"
e4d6b795
MB		 52#include "lo.h"
53#include "pcmcia.h"
54
55MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56MODULE_AUTHOR("Martin Langer");
57MODULE_AUTHOR("Stefano Brivio");
58MODULE_AUTHOR("Michael Buesch");
59MODULE_LICENSE("GPL");
60
61extern char *nvram_get(char *name);
62
63#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
64static int modparam_pio;
65module_param_named(pio, modparam_pio, int, 0444);
66MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67#elif defined(CONFIG_B43_DMA)
68# define modparam_pio 0
69#elif defined(CONFIG_B43_PIO)
70# define modparam_pio 1
71#endif
72
73static int modparam_bad_frames_preempt;
74module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75MODULE_PARM_DESC(bad_frames_preempt,
76 "enable(1) / disable(0) Bad Frames Preemption");
77
78static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
79module_param_named(short_retry, modparam_short_retry, int, 0444);
80MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
81
82static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
83module_param_named(long_retry, modparam_long_retry, int, 0444);
84MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
85
e4d6b795
MB		 86static char modparam_fwpostfix[16];
87module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
88MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
89
e4d6b795
MB		 90static int modparam_hwpctl;
91module_param_named(hwpctl, modparam_hwpctl, int, 0444);
92MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
93
94static int modparam_nohwcrypt;
95module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
96MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
97
98static const struct ssb_device_id b43_ssb_tbl[] = {
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
104 SSB_DEVTABLE_END
105};
106
107MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
108
109/* Channel and ratetables are shared for all devices.
110 * They can't be const, because ieee80211 puts some precalculated
111 * data in there. This data is the same for all devices, so we don't
112 * get concurrency issues */
113#define RATETAB_ENT(_rateid, _flags) \
114 { \
115 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
116 .val = (_rateid), \
117 .val2 = (_rateid), \
118 .flags = (_flags), \
119 }
120static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
133};
134
135#define b43_a_ratetable (__b43_ratetable + 4)
136#define b43_a_ratetable_size 8
137#define b43_b_ratetable (__b43_ratetable + 0)
138#define b43_b_ratetable_size 4
139#define b43_g_ratetable (__b43_ratetable + 0)
140#define b43_g_ratetable_size 12
141
142#define CHANTAB_ENT(_chanid, _freq) \
143 { \
144 .chan = (_chanid), \
145 .freq = (_freq), \
146 .val = (_chanid), \
147 .flag = IEEE80211_CHAN_W_SCAN | \
148 IEEE80211_CHAN_W_ACTIVE_SCAN | \
149 IEEE80211_CHAN_W_IBSS, \
150 .power_level = 0xFF, \
151 .antenna_max = 0xFF, \
152 }
153static struct ieee80211_channel b43_bg_chantable[] = {
154 CHANTAB_ENT(1, 2412),
155 CHANTAB_ENT(2, 2417),
156 CHANTAB_ENT(3, 2422),
157 CHANTAB_ENT(4, 2427),
158 CHANTAB_ENT(5, 2432),
159 CHANTAB_ENT(6, 2437),
160 CHANTAB_ENT(7, 2442),
161 CHANTAB_ENT(8, 2447),
162 CHANTAB_ENT(9, 2452),
163 CHANTAB_ENT(10, 2457),
164 CHANTAB_ENT(11, 2462),
165 CHANTAB_ENT(12, 2467),
166 CHANTAB_ENT(13, 2472),
167 CHANTAB_ENT(14, 2484),
168};
169
170#define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
171static struct ieee80211_channel b43_a_chantable[] = {
172 CHANTAB_ENT(36, 5180),
173 CHANTAB_ENT(40, 5200),
174 CHANTAB_ENT(44, 5220),
175 CHANTAB_ENT(48, 5240),
176 CHANTAB_ENT(52, 5260),
177 CHANTAB_ENT(56, 5280),
178 CHANTAB_ENT(60, 5300),
179 CHANTAB_ENT(64, 5320),
180 CHANTAB_ENT(149, 5745),
181 CHANTAB_ENT(153, 5765),
182 CHANTAB_ENT(157, 5785),
183 CHANTAB_ENT(161, 5805),
184 CHANTAB_ENT(165, 5825),
185};
186
187#define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
188
189static void b43_wireless_core_exit(struct b43_wldev *dev);
190static int b43_wireless_core_init(struct b43_wldev *dev);
191static void b43_wireless_core_stop(struct b43_wldev *dev);
192static int b43_wireless_core_start(struct b43_wldev *dev);
193
194static int b43_ratelimit(struct b43_wl *wl)
195{
196 if (!wl || !wl->current_dev)
197 return 1;
198 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
199 return 1;
200 /* We are up and running.
201 * Ratelimit the messages to avoid DoS over the net. */
202 return net_ratelimit();
203}
204
205void b43info(struct b43_wl *wl, const char *fmt, ...)
206{
207 va_list args;
208
209 if (!b43_ratelimit(wl))
210 return;
211 va_start(args, fmt);
212 printk(KERN_INFO "b43-%s: ",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
214 vprintk(fmt, args);
215 va_end(args);
216}
217
218void b43err(struct b43_wl *wl, const char *fmt, ...)
219{
220 va_list args;
221
222 if (!b43_ratelimit(wl))
223 return;
224 va_start(args, fmt);
225 printk(KERN_ERR "b43-%s ERROR: ",
226 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
227 vprintk(fmt, args);
228 va_end(args);
229}
230
231void b43warn(struct b43_wl *wl, const char *fmt, ...)
232{
233 va_list args;
234
235 if (!b43_ratelimit(wl))
236 return;
237 va_start(args, fmt);
238 printk(KERN_WARNING "b43-%s warning: ",
239 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
240 vprintk(fmt, args);
241 va_end(args);
242}
243
244#if B43_DEBUG
245void b43dbg(struct b43_wl *wl, const char *fmt, ...)
246{
247 va_list args;
248
249 va_start(args, fmt);
250 printk(KERN_DEBUG "b43-%s debug: ",
251 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
252 vprintk(fmt, args);
253 va_end(args);
254}
255#endif /* DEBUG */
256
257static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
258{
259 u32 macctl;
260
261 B43_WARN_ON(offset % 4 != 0);
262
263 macctl = b43_read32(dev, B43_MMIO_MACCTL);
264 if (macctl & B43_MACCTL_BE)
265 val = swab32(val);
266
267 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
268 mmiowb();
269 b43_write32(dev, B43_MMIO_RAM_DATA, val);
270}
271
272static inline
273 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
274{
275 u32 control;
276
277 /* "offset" is the WORD offset. */
278
279 control = routing;
280 control <<= 16;
281 control |= offset;
282 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
283}
284
285u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
286{
287 u32 ret;
288
289 if (routing == B43_SHM_SHARED) {
290 B43_WARN_ON(offset & 0x0001);
291 if (offset & 0x0003) {
292 /* Unaligned access */
293 b43_shm_control_word(dev, routing, offset >> 2);
294 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
295 ret <<= 16;
296 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
297 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
298
299 return ret;
300 }
301 offset >>= 2;
302 }
303 b43_shm_control_word(dev, routing, offset);
304 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
305
306 return ret;
307}
308
309u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
310{
311 u16 ret;
312
313 if (routing == B43_SHM_SHARED) {
314 B43_WARN_ON(offset & 0x0001);
315 if (offset & 0x0003) {
316 /* Unaligned access */
317 b43_shm_control_word(dev, routing, offset >> 2);
318 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
319
320 return ret;
321 }
322 offset >>= 2;
323 }
324 b43_shm_control_word(dev, routing, offset);
325 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
326
327 return ret;
328}
329
330void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
331{
332 if (routing == B43_SHM_SHARED) {
333 B43_WARN_ON(offset & 0x0001);
334 if (offset & 0x0003) {
335 /* Unaligned access */
336 b43_shm_control_word(dev, routing, offset >> 2);
337 mmiowb();
338 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
339 (value >> 16) & 0xffff);
340 mmiowb();
341 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
342 mmiowb();
343 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
344 return;
345 }
346 offset >>= 2;
347 }
348 b43_shm_control_word(dev, routing, offset);
349 mmiowb();
350 b43_write32(dev, B43_MMIO_SHM_DATA, value);
351}
352
353void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
354{
355 if (routing == B43_SHM_SHARED) {
356 B43_WARN_ON(offset & 0x0001);
357 if (offset & 0x0003) {
358 /* Unaligned access */
359 b43_shm_control_word(dev, routing, offset >> 2);
360 mmiowb();
361 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
362 return;
363 }
364 offset >>= 2;
365 }
366 b43_shm_control_word(dev, routing, offset);
367 mmiowb();
368 b43_write16(dev, B43_MMIO_SHM_DATA, value);
369}
370
371/* Read HostFlags */
372u32 b43_hf_read(struct b43_wldev * dev)
373{
374 u32 ret;
375
376 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
377 ret <<= 16;
378 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
379
380 return ret;
381}
382
383/* Write HostFlags */
384void b43_hf_write(struct b43_wldev *dev, u32 value)
385{
386 b43_shm_write16(dev, B43_SHM_SHARED,
387 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
388 b43_shm_write16(dev, B43_SHM_SHARED,
389 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
390}
391
392void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
393{
394 /* We need to be careful. As we read the TSF from multiple
395 * registers, we should take care of register overflows.
396 * In theory, the whole tsf read process should be atomic.
397 * We try to be atomic here, by restaring the read process,
398 * if any of the high registers changed (overflew).
399 */
400 if (dev->dev->id.revision >= 3) {
401 u32 low, high, high2;
402
403 do {
404 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
405 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
406 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
407 } while (unlikely(high != high2));
408
409 *tsf = high;
410 *tsf <<= 32;
411 *tsf |= low;
412 } else {
413 u64 tmp;
414 u16 v0, v1, v2, v3;
415 u16 test1, test2, test3;
416
417 do {
418 v3 = b43_read16(dev, B43_MMIO_TSF_3);
419 v2 = b43_read16(dev, B43_MMIO_TSF_2);
420 v1 = b43_read16(dev, B43_MMIO_TSF_1);
421 v0 = b43_read16(dev, B43_MMIO_TSF_0);
422
423 test3 = b43_read16(dev, B43_MMIO_TSF_3);
424 test2 = b43_read16(dev, B43_MMIO_TSF_2);
425 test1 = b43_read16(dev, B43_MMIO_TSF_1);
426 } while (v3 != test3 || v2 != test2 || v1 != test1);
427
428 *tsf = v3;
429 *tsf <<= 48;
430 tmp = v2;
431 tmp <<= 32;
432 *tsf |= tmp;
433 tmp = v1;
434 tmp <<= 16;
435 *tsf |= tmp;
436 *tsf |= v0;
437 }
438}
439
440static void b43_time_lock(struct b43_wldev *dev)
441{
442 u32 macctl;
443
444 macctl = b43_read32(dev, B43_MMIO_MACCTL);
445 macctl |= B43_MACCTL_TBTTHOLD;
446 b43_write32(dev, B43_MMIO_MACCTL, macctl);
447 /* Commit the write */
448 b43_read32(dev, B43_MMIO_MACCTL);
449}
450
451static void b43_time_unlock(struct b43_wldev *dev)
452{
453 u32 macctl;
454
455 macctl = b43_read32(dev, B43_MMIO_MACCTL);
456 macctl &= ~B43_MACCTL_TBTTHOLD;
457 b43_write32(dev, B43_MMIO_MACCTL, macctl);
458 /* Commit the write */
459 b43_read32(dev, B43_MMIO_MACCTL);
460}
461
462static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
463{
464 /* Be careful with the in-progress timer.
465 * First zero out the low register, so we have a full
466 * register-overflow duration to complete the operation.
467 */
468 if (dev->dev->id.revision >= 3) {
469 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
470 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
471
472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
473 mmiowb();
474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
475 mmiowb();
476 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
477 } else {
478 u16 v0 = (tsf & 0x000000000000FFFFULL);
479 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
480 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
481 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
482
483 b43_write16(dev, B43_MMIO_TSF_0, 0);
484 mmiowb();
485 b43_write16(dev, B43_MMIO_TSF_3, v3);
486 mmiowb();
487 b43_write16(dev, B43_MMIO_TSF_2, v2);
488 mmiowb();
489 b43_write16(dev, B43_MMIO_TSF_1, v1);
490 mmiowb();
491 b43_write16(dev, B43_MMIO_TSF_0, v0);
492 }
493}
494
495void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
496{
497 b43_time_lock(dev);
498 b43_tsf_write_locked(dev, tsf);
499 b43_time_unlock(dev);
500}
501
502static
503void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
504{
505 static const u8 zero_addr[ETH_ALEN] = { 0 };
506 u16 data;
507
508 if (!mac)
509 mac = zero_addr;
510
511 offset |= 0x0020;
512 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
513
514 data = mac[0];
515 data |= mac[1] << 8;
516 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
517 data = mac[2];
518 data |= mac[3] << 8;
519 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
520 data = mac[4];
521 data |= mac[5] << 8;
522 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
523}
524
525static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
526{
527 const u8 *mac;
528 const u8 *bssid;
529 u8 mac_bssid[ETH_ALEN * 2];
530 int i;
531 u32 tmp;
532
533 bssid = dev->wl->bssid;
534 mac = dev->wl->mac_addr;
535
536 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
537
538 memcpy(mac_bssid, mac, ETH_ALEN);
539 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
540
541 /* Write our MAC address and BSSID to template ram */
542 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
543 tmp = (u32) (mac_bssid[i + 0]);
544 tmp |= (u32) (mac_bssid[i + 1]) << 8;
545 tmp |= (u32) (mac_bssid[i + 2]) << 16;
546 tmp |= (u32) (mac_bssid[i + 3]) << 24;
547 b43_ram_write(dev, 0x20 + i, tmp);
548 }
549}
550
4150c572 551static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 552{
e4d6b795 553 b43_write_mac_bssid_templates(dev);
4150c572 554 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 555}
556
557static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
558{
559 /* slot_time is in usec. */
560 if (dev->phy.type != B43_PHYTYPE_G)
561 return;
562 b43_write16(dev, 0x684, 510 + slot_time);
563 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
564}
565
566static void b43_short_slot_timing_enable(struct b43_wldev *dev)
567{
568 b43_set_slot_time(dev, 9);
569 dev->short_slot = 1;
570}
571
572static void b43_short_slot_timing_disable(struct b43_wldev *dev)
573{
574 b43_set_slot_time(dev, 20);
575 dev->short_slot = 0;
576}
577
578/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
579 * Returns the _previously_ enabled IRQ mask.
580 */
581static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
582{
583 u32 old_mask;
584
585 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
586 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
587
588 return old_mask;
589}
590
591/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
592 * Returns the _previously_ enabled IRQ mask.
593 */
594static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
595{
596 u32 old_mask;
597
598 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
599 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
600
601 return old_mask;
602}
603
604/* Synchronize IRQ top- and bottom-half.
605 * IRQs must be masked before calling this.
606 * This must not be called with the irq_lock held.
607 */
608static void b43_synchronize_irq(struct b43_wldev *dev)
609{
610 synchronize_irq(dev->dev->irq);
611 tasklet_kill(&dev->isr_tasklet);
612}
613
614/* DummyTransmission function, as documented on
615 * http://bcm-specs.sipsolutions.net/DummyTransmission
616 */
617void b43_dummy_transmission(struct b43_wldev *dev)
618{
619 struct b43_phy *phy = &dev->phy;
620 unsigned int i, max_loop;
621 u16 value;
622 u32 buffer[5] = {
623 0x00000000,
624 0x00D40000,
625 0x00000000,
626 0x01000000,
627 0x00000000,
628 };
629
630 switch (phy->type) {
631 case B43_PHYTYPE_A:
632 max_loop = 0x1E;
633 buffer[0] = 0x000201CC;
634 break;
635 case B43_PHYTYPE_B:
636 case B43_PHYTYPE_G:
637 max_loop = 0xFA;
638 buffer[0] = 0x000B846E;
639 break;
640 default:
641 B43_WARN_ON(1);
642 return;
643 }
644
645 for (i = 0; i < 5; i++)
646 b43_ram_write(dev, i * 4, buffer[i]);
647
648 /* Commit writes */
649 b43_read32(dev, B43_MMIO_MACCTL);
650
651 b43_write16(dev, 0x0568, 0x0000);
652 b43_write16(dev, 0x07C0, 0x0000);
653 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
654 b43_write16(dev, 0x050C, value);
655 b43_write16(dev, 0x0508, 0x0000);
656 b43_write16(dev, 0x050A, 0x0000);
657 b43_write16(dev, 0x054C, 0x0000);
658 b43_write16(dev, 0x056A, 0x0014);
659 b43_write16(dev, 0x0568, 0x0826);
660 b43_write16(dev, 0x0500, 0x0000);
661 b43_write16(dev, 0x0502, 0x0030);
662
663 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
664 b43_radio_write16(dev, 0x0051, 0x0017);
665 for (i = 0x00; i < max_loop; i++) {
666 value = b43_read16(dev, 0x050E);
667 if (value & 0x0080)
668 break;
669 udelay(10);
670 }
671 for (i = 0x00; i < 0x0A; i++) {
672 value = b43_read16(dev, 0x050E);
673 if (value & 0x0400)
674 break;
675 udelay(10);
676 }
677 for (i = 0x00; i < 0x0A; i++) {
678 value = b43_read16(dev, 0x0690);
679 if (!(value & 0x0100))
680 break;
681 udelay(10);
682 }
683 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
684 b43_radio_write16(dev, 0x0051, 0x0037);
685}
686
687static void key_write(struct b43_wldev *dev,
688 u8 index, u8 algorithm, const u8 * key)
689{
690 unsigned int i;
691 u32 offset;
692 u16 value;
693 u16 kidx;
694
695 /* Key index/algo block */
696 kidx = b43_kidx_to_fw(dev, index);
697 value = ((kidx << 4) | algorithm);
698 b43_shm_write16(dev, B43_SHM_SHARED,
699 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
700
701 /* Write the key to the Key Table Pointer offset */
702 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
703 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
704 value = key[i];
705 value |= (u16) (key[i + 1]) << 8;
706 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
707 }
708}
709
710static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
711{
712 u32 addrtmp[2] = { 0, 0, };
713 u8 per_sta_keys_start = 8;
714
715 if (b43_new_kidx_api(dev))
716 per_sta_keys_start = 4;
717
718 B43_WARN_ON(index < per_sta_keys_start);
719 /* We have two default TX keys and possibly two default RX keys.
720 * Physical mac 0 is mapped to physical key 4 or 8, depending
721 * on the firmware version.
722 * So we must adjust the index here.
723 */
724 index -= per_sta_keys_start;
725
726 if (addr) {
727 addrtmp[0] = addr[0];
728 addrtmp[0] |= ((u32) (addr[1]) << 8);
729 addrtmp[0] |= ((u32) (addr[2]) << 16);
730 addrtmp[0] |= ((u32) (addr[3]) << 24);
731 addrtmp[1] = addr[4];
732 addrtmp[1] |= ((u32) (addr[5]) << 8);
733 }
734
735 if (dev->dev->id.revision >= 5) {
736 /* Receive match transmitter address mechanism */
737 b43_shm_write32(dev, B43_SHM_RCMTA,
738 (index * 2) + 0, addrtmp[0]);
739 b43_shm_write16(dev, B43_SHM_RCMTA,
740 (index * 2) + 1, addrtmp[1]);
741 } else {
742 /* RXE (Receive Engine) and
743 * PSM (Programmable State Machine) mechanism
744 */
745 if (index < 8) {
746 /* TODO write to RCM 16, 19, 22 and 25 */
747 } else {
748 b43_shm_write32(dev, B43_SHM_SHARED,
749 B43_SHM_SH_PSM + (index * 6) + 0,
750 addrtmp[0]);
751 b43_shm_write16(dev, B43_SHM_SHARED,
752 B43_SHM_SH_PSM + (index * 6) + 4,
753 addrtmp[1]);
754 }
755 }
756}
757
758static void do_key_write(struct b43_wldev *dev,
759 u8 index, u8 algorithm,
760 const u8 * key, size_t key_len, const u8 * mac_addr)
761{
762 u8 buf[B43_SEC_KEYSIZE] = { 0, };
763 u8 per_sta_keys_start = 8;
764
765 if (b43_new_kidx_api(dev))
766 per_sta_keys_start = 4;
767
768 B43_WARN_ON(index >= dev->max_nr_keys);
769 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
770
771 if (index >= per_sta_keys_start)
772 keymac_write(dev, index, NULL); /* First zero out mac. */
773 if (key)
774 memcpy(buf, key, key_len);
775 key_write(dev, index, algorithm, buf);
776 if (index >= per_sta_keys_start)
777 keymac_write(dev, index, mac_addr);
778
779 dev->key[index].algorithm = algorithm;
780}
781
782static int b43_key_write(struct b43_wldev *dev,
783 int index, u8 algorithm,
784 const u8 * key, size_t key_len,
785 const u8 * mac_addr,
786 struct ieee80211_key_conf *keyconf)
787{
788 int i;
789 int sta_keys_start;
790
791 if (key_len > B43_SEC_KEYSIZE)
792 return -EINVAL;
793 for (i = 0; i < dev->max_nr_keys; i++) {
794 /* Check that we don't already have this key. */
795 B43_WARN_ON(dev->key[i].keyconf == keyconf);
796 }
797 if (index < 0) {
798 /* Either pairwise key or address is 00:00:00:00:00:00
799 * for transmit-only keys. Search the index. */
800 if (b43_new_kidx_api(dev))
801 sta_keys_start = 4;
802 else
803 sta_keys_start = 8;
804 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
805 if (!dev->key[i].keyconf) {
806 /* found empty */
807 index = i;
808 break;
809 }
810 }
811 if (index < 0) {
812 b43err(dev->wl, "Out of hardware key memory\n");
813 return -ENOSPC;
814 }
815 } else
816 B43_WARN_ON(index > 3);
817
818 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
819 if ((index <= 3) && !b43_new_kidx_api(dev)) {
820 /* Default RX key */
821 B43_WARN_ON(mac_addr);
822 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
823 }
824 keyconf->hw_key_idx = index;
825 dev->key[index].keyconf = keyconf;
826
827 return 0;
828}
829
830static int b43_key_clear(struct b43_wldev *dev, int index)
831{
832 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
833 return -EINVAL;
834 do_key_write(dev, index, B43_SEC_ALGO_NONE,
835 NULL, B43_SEC_KEYSIZE, NULL);
836 if ((index <= 3) && !b43_new_kidx_api(dev)) {
837 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
838 NULL, B43_SEC_KEYSIZE, NULL);
839 }
840 dev->key[index].keyconf = NULL;
841
842 return 0;
843}
844
845static void b43_clear_keys(struct b43_wldev *dev)
846{
847 int i;
848
849 for (i = 0; i < dev->max_nr_keys; i++)
850 b43_key_clear(dev, i);
851}
852
853void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
854{
855 u32 macctl;
856 u16 ucstat;
857 bool hwps;
858 bool awake;
859 int i;
860
861 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
862 (ps_flags & B43_PS_DISABLED));
863 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
864
865 if (ps_flags & B43_PS_ENABLED) {
866 hwps = 1;
867 } else if (ps_flags & B43_PS_DISABLED) {
868 hwps = 0;
869 } else {
870 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
871 // and thus is not an AP and we are associated, set bit 25
872 }
873 if (ps_flags & B43_PS_AWAKE) {
874 awake = 1;
875 } else if (ps_flags & B43_PS_ASLEEP) {
876 awake = 0;
877 } else {
878 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
879 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
880 // successful, set bit26
881 }
882
883/* FIXME: For now we force awake-on and hwps-off */
884 hwps = 0;
885 awake = 1;
886
887 macctl = b43_read32(dev, B43_MMIO_MACCTL);
888 if (hwps)
889 macctl |= B43_MACCTL_HWPS;
890 else
891 macctl &= ~B43_MACCTL_HWPS;
892 if (awake)
893 macctl |= B43_MACCTL_AWAKE;
894 else
895 macctl &= ~B43_MACCTL_AWAKE;
896 b43_write32(dev, B43_MMIO_MACCTL, macctl);
897 /* Commit write */
898 b43_read32(dev, B43_MMIO_MACCTL);
899 if (awake && dev->dev->id.revision >= 5) {
900 /* Wait for the microcode to wake up. */
901 for (i = 0; i < 100; i++) {
902 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
903 B43_SHM_SH_UCODESTAT);
904 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
905 break;
906 udelay(10);
907 }
908 }
909}
910
911/* Turn the Analog ON/OFF */
912static void b43_switch_analog(struct b43_wldev *dev, int on)
913{
914 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
915}
916
917void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
918{
919 u32 tmslow;
920 u32 macctl;
921
922 flags |= B43_TMSLOW_PHYCLKEN;
923 flags |= B43_TMSLOW_PHYRESET;
924 ssb_device_enable(dev->dev, flags);
925 msleep(2); /* Wait for the PLL to turn on. */
926
927 /* Now take the PHY out of Reset again */
928 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
929 tmslow |= SSB_TMSLOW_FGC;
930 tmslow &= ~B43_TMSLOW_PHYRESET;
931 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
932 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
933 msleep(1);
934 tmslow &= ~SSB_TMSLOW_FGC;
935 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
936 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
937 msleep(1);
938
939 /* Turn Analog ON */
940 b43_switch_analog(dev, 1);
941
942 macctl = b43_read32(dev, B43_MMIO_MACCTL);
943 macctl &= ~B43_MACCTL_GMODE;
944 if (flags & B43_TMSLOW_GMODE)
945 macctl |= B43_MACCTL_GMODE;
946 macctl |= B43_MACCTL_IHR_ENABLED;
947 b43_write32(dev, B43_MMIO_MACCTL, macctl);
948}
949
950static void handle_irq_transmit_status(struct b43_wldev *dev)
951{
952 u32 v0, v1;
953 u16 tmp;
954 struct b43_txstatus stat;
955
956 while (1) {
957 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
958 if (!(v0 & 0x00000001))
959 break;
960 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
961
962 stat.cookie = (v0 >> 16);
963 stat.seq = (v1 & 0x0000FFFF);
964 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
965 tmp = (v0 & 0x0000FFFF);
966 stat.frame_count = ((tmp & 0xF000) >> 12);
967 stat.rts_count = ((tmp & 0x0F00) >> 8);
968 stat.supp_reason = ((tmp & 0x001C) >> 2);
969 stat.pm_indicated = !!(tmp & 0x0080);
970 stat.intermediate = !!(tmp & 0x0040);
971 stat.for_ampdu = !!(tmp & 0x0020);
972 stat.acked = !!(tmp & 0x0002);
973
974 b43_handle_txstatus(dev, &stat);
975 }
976}
977
978static void drain_txstatus_queue(struct b43_wldev *dev)
979{
980 u32 dummy;
981
982 if (dev->dev->id.revision < 5)
983 return;
984 /* Read all entries from the microcode TXstatus FIFO
985 * and throw them away.
986 */
987 while (1) {
988 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
989 if (!(dummy & 0x00000001))
990 break;
991 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
992 }
993}
994
995static u32 b43_jssi_read(struct b43_wldev *dev)
996{
997 u32 val = 0;
998
999 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1000 val <<= 16;
1001 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1002
1003 return val;
1004}
1005
1006static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1007{
1008 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1009 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1010}
1011
1012static void b43_generate_noise_sample(struct b43_wldev *dev)
1013{
1014 b43_jssi_write(dev, 0x7F7F7F7F);
1015 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1016 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1017 | (1 << 4));
1018 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1019}
1020
1021static void b43_calculate_link_quality(struct b43_wldev *dev)
1022{
1023 /* Top half of Link Quality calculation. */
1024
1025 if (dev->noisecalc.calculation_running)
1026 return;
1027 dev->noisecalc.channel_at_start = dev->phy.channel;
1028 dev->noisecalc.calculation_running = 1;
1029 dev->noisecalc.nr_samples = 0;
1030
1031 b43_generate_noise_sample(dev);
1032}
1033
1034static void handle_irq_noise(struct b43_wldev *dev)
1035{
1036 struct b43_phy *phy = &dev->phy;
1037 u16 tmp;
1038 u8 noise[4];
1039 u8 i, j;
1040 s32 average;
1041
1042 /* Bottom half of Link Quality calculation. */
1043
1044 B43_WARN_ON(!dev->noisecalc.calculation_running);
1045 if (dev->noisecalc.channel_at_start != phy->channel)
1046 goto drop_calculation;
1a09404a 1047 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1048 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1049 noise[2] == 0x7F || noise[3] == 0x7F)
1050 goto generate_new;
1051
1052 /* Get the noise samples. */
1053 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1054 i = dev->noisecalc.nr_samples;
1055 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1060 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1061 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1062 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1063 dev->noisecalc.nr_samples++;
1064 if (dev->noisecalc.nr_samples == 8) {
1065 /* Calculate the Link Quality by the noise samples. */
1066 average = 0;
1067 for (i = 0; i < 8; i++) {
1068 for (j = 0; j < 4; j++)
1069 average += dev->noisecalc.samples[i][j];
1070 }
1071 average /= (8 * 4);
1072 average *= 125;
1073 average += 64;
1074 average /= 128;
1075 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1076 tmp = (tmp / 128) & 0x1F;
1077 if (tmp >= 8)
1078 average += 2;
1079 else
1080 average -= 25;
1081 if (tmp == 8)
1082 average -= 72;
1083 else
1084 average -= 48;
1085
1086 dev->stats.link_noise = average;
1087 drop_calculation:
1088 dev->noisecalc.calculation_running = 0;
1089 return;
1090 }
1091 generate_new:
1092 b43_generate_noise_sample(dev);
1093}
1094
1095static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1096{
1097 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1098 ///TODO: PS TBTT
1099 } else {
1100 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1101 b43_power_saving_ctl_bits(dev, 0);
1102 }
1103 dev->reg124_set_0x4 = 0;
1104 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1105 dev->reg124_set_0x4 = 1;
1106}
1107
1108static void handle_irq_atim_end(struct b43_wldev *dev)
1109{
1110 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1111 return;
1112 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1113 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1114 | 0x4);
1115}
1116
1117static void handle_irq_pmq(struct b43_wldev *dev)
1118{
1119 u32 tmp;
1120
1121 //TODO: AP mode.
1122
1123 while (1) {
1124 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1125 if (!(tmp & 0x00000008))
1126 break;
1127 }
1128 /* 16bit write is odd, but correct. */
1129 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1130}
1131
1132static void b43_write_template_common(struct b43_wldev *dev,
1133 const u8 * data, u16 size,
1134 u16 ram_offset,
1135 u16 shm_size_offset, u8 rate)
1136{
1137 u32 i, tmp;
1138 struct b43_plcp_hdr4 plcp;
1139
1140 plcp.data = 0;
1141 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1142 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1143 ram_offset += sizeof(u32);
1144 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1145 * So leave the first two bytes of the next write blank.
1146 */
1147 tmp = (u32) (data[0]) << 16;
1148 tmp |= (u32) (data[1]) << 24;
1149 b43_ram_write(dev, ram_offset, tmp);
1150 ram_offset += sizeof(u32);
1151 for (i = 2; i < size; i += sizeof(u32)) {
1152 tmp = (u32) (data[i + 0]);
1153 if (i + 1 < size)
1154 tmp |= (u32) (data[i + 1]) << 8;
1155 if (i + 2 < size)
1156 tmp |= (u32) (data[i + 2]) << 16;
1157 if (i + 3 < size)
1158 tmp |= (u32) (data[i + 3]) << 24;
1159 b43_ram_write(dev, ram_offset + i - 2, tmp);
1160 }
1161 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1162 size + sizeof(struct b43_plcp_hdr6));
1163}
1164
1165static void b43_write_beacon_template(struct b43_wldev *dev,
1166 u16 ram_offset,
1167 u16 shm_size_offset, u8 rate)
1168{
1169 int len;
1170 const u8 *data;
1171
1172 B43_WARN_ON(!dev->cached_beacon);
1173 len = min((size_t) dev->cached_beacon->len,
1174 0x200 - sizeof(struct b43_plcp_hdr6));
1175 data = (const u8 *)(dev->cached_beacon->data);
1176 b43_write_template_common(dev, data,
1177 len, ram_offset, shm_size_offset, rate);
1178}
1179
1180static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1181 u16 shm_offset, u16 size, u8 rate)
1182{
1183 struct b43_plcp_hdr4 plcp;
1184 u32 tmp;
1185 __le16 dur;
1186
1187 plcp.data = 0;
1188 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1189 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1190 dev->wl->if_id, size,
1191 B43_RATE_TO_BASE100KBPS(rate));
1192 /* Write PLCP in two parts and timing for packet transfer */
1193 tmp = le32_to_cpu(plcp.data);
1194 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1195 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1196 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1197}
1198
1199/* Instead of using custom probe response template, this function
1200 * just patches custom beacon template by:
1201 * 1) Changing packet type
1202 * 2) Patching duration field
1203 * 3) Stripping TIM
1204 */
1205static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1206 u16 * dest_size, u8 rate)
1207{
1208 const u8 *src_data;
1209 u8 *dest_data;
1210 u16 src_size, elem_size, src_pos, dest_pos;
1211 __le16 dur;
1212 struct ieee80211_hdr *hdr;
1213
1214 B43_WARN_ON(!dev->cached_beacon);
1215 src_size = dev->cached_beacon->len;
1216 src_data = (const u8 *)dev->cached_beacon->data;
1217
1218 if (unlikely(src_size < 0x24)) {
1219 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1220 return NULL;
1221 }
1222
1223 dest_data = kmalloc(src_size, GFP_ATOMIC);
1224 if (unlikely(!dest_data))
1225 return NULL;
1226
1227 /* 0x24 is offset of first variable-len Information-Element
1228 * in beacon frame.
1229 */
1230 memcpy(dest_data, src_data, 0x24);
1231 src_pos = dest_pos = 0x24;
1232 for (; src_pos < src_size - 2; src_pos += elem_size) {
1233 elem_size = src_data[src_pos + 1] + 2;
1234 if (src_data[src_pos] != 0x05) { /* TIM */
1235 memcpy(dest_data + dest_pos, src_data + src_pos,
1236 elem_size);
1237 dest_pos += elem_size;
1238 }
1239 }
1240 *dest_size = dest_pos;
1241 hdr = (struct ieee80211_hdr *)dest_data;
1242
1243 /* Set the frame control. */
1244 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1245 IEEE80211_STYPE_PROBE_RESP);
1246 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1247 dev->wl->if_id, *dest_size,
1248 B43_RATE_TO_BASE100KBPS(rate));
1249 hdr->duration_id = dur;
1250
1251 return dest_data;
1252}
1253
1254static void b43_write_probe_resp_template(struct b43_wldev *dev,
1255 u16 ram_offset,
1256 u16 shm_size_offset, u8 rate)
1257{
1258 u8 *probe_resp_data;
1259 u16 size;
1260
1261 B43_WARN_ON(!dev->cached_beacon);
1262 size = dev->cached_beacon->len;
1263 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1264 if (unlikely(!probe_resp_data))
1265 return;
1266
1267 /* Looks like PLCP headers plus packet timings are stored for
1268 * all possible basic rates
1269 */
1270 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1271 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1272 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1273 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1274
1275 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1276 b43_write_template_common(dev, probe_resp_data,
1277 size, ram_offset, shm_size_offset, rate);
1278 kfree(probe_resp_data);
1279}
1280
1281static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1282 struct sk_buff *beacon)
1283{
1284 if (dev->cached_beacon)
1285 kfree_skb(dev->cached_beacon);
1286 dev->cached_beacon = beacon;
1287
1288 return 0;
1289}
1290
1291static void b43_update_templates(struct b43_wldev *dev)
1292{
1293 u32 status;
1294
1295 B43_WARN_ON(!dev->cached_beacon);
1296
1297 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1298 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1299 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1300
1301 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1302 status |= 0x03;
1303 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1304}
1305
1306static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1307{
1308 int err;
1309
1310 err = b43_refresh_cached_beacon(dev, beacon);
1311 if (unlikely(err))
1312 return;
1313 b43_update_templates(dev);
1314}
1315
1316static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1317{
1318 u32 tmp;
1319 u16 i, len;
1320
1321 len = min((u16) ssid_len, (u16) 0x100);
1322 for (i = 0; i < len; i += sizeof(u32)) {
1323 tmp = (u32) (ssid[i + 0]);
1324 if (i + 1 < len)
1325 tmp |= (u32) (ssid[i + 1]) << 8;
1326 if (i + 2 < len)
1327 tmp |= (u32) (ssid[i + 2]) << 16;
1328 if (i + 3 < len)
1329 tmp |= (u32) (ssid[i + 3]) << 24;
1330 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1331 }
1332 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1333}
1334
1335static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1336{
1337 b43_time_lock(dev);
1338 if (dev->dev->id.revision >= 3) {
1339 b43_write32(dev, 0x188, (beacon_int << 16));
1340 } else {
1341 b43_write16(dev, 0x606, (beacon_int >> 6));
1342 b43_write16(dev, 0x610, beacon_int);
1343 }
1344 b43_time_unlock(dev);
1345}
1346
1347static void handle_irq_beacon(struct b43_wldev *dev)
1348{
1349 u32 status;
1350
1351 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1352 return;
1353
1354 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1355 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1356
1357 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1358 /* ACK beacon IRQ. */
1359 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1360 dev->irq_savedstate |= B43_IRQ_BEACON;
1361 if (dev->cached_beacon)
1362 kfree_skb(dev->cached_beacon);
1363 dev->cached_beacon = NULL;
1364 return;
1365 }
1366 if (!(status & 0x1)) {
1367 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1368 status |= 0x1;
1369 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1370 }
1371 if (!(status & 0x2)) {
1372 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1373 status |= 0x2;
1374 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1375 }
1376}
1377
1378static void handle_irq_ucode_debug(struct b43_wldev *dev)
1379{
1380 //TODO
1381}
1382
1383/* Interrupt handler bottom-half */
1384static void b43_interrupt_tasklet(struct b43_wldev *dev)
1385{
1386 u32 reason;
1387 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1388 u32 merged_dma_reason = 0;
21954c36 1389 int i;
e4d6b795
MB		 1390 unsigned long flags;
1391
1392 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1393
1394 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1395
1396 reason = dev->irq_reason;
1397 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1398 dma_reason[i] = dev->dma_reason[i];
1399 merged_dma_reason |= dma_reason[i];
1400 }
1401
1402 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1403 b43err(dev->wl, "MAC transmission error\n");
1404
1405 if (unlikely(reason & B43_IRQ_PHY_TXERR))
1406 b43err(dev->wl, "PHY transmission error\n");
1407
1408 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1409 B43_DMAIRQ_NONFATALMASK))) {
1410 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1411 b43err(dev->wl, "Fatal DMA error: "
1412 "0x%08X, 0x%08X, 0x%08X, "
1413 "0x%08X, 0x%08X, 0x%08X\n",
1414 dma_reason[0], dma_reason[1],
1415 dma_reason[2], dma_reason[3],
1416 dma_reason[4], dma_reason[5]);
1417 b43_controller_restart(dev, "DMA error");
1418 mmiowb();
1419 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1420 return;
1421 }
1422 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1423 b43err(dev->wl, "DMA error: "
1424 "0x%08X, 0x%08X, 0x%08X, "
1425 "0x%08X, 0x%08X, 0x%08X\n",
1426 dma_reason[0], dma_reason[1],
1427 dma_reason[2], dma_reason[3],
1428 dma_reason[4], dma_reason[5]);
1429 }
1430 }
1431
1432 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1433 handle_irq_ucode_debug(dev);
1434 if (reason & B43_IRQ_TBTT_INDI)
1435 handle_irq_tbtt_indication(dev);
1436 if (reason & B43_IRQ_ATIM_END)
1437 handle_irq_atim_end(dev);
1438 if (reason & B43_IRQ_BEACON)
1439 handle_irq_beacon(dev);
1440 if (reason & B43_IRQ_PMQ)
1441 handle_irq_pmq(dev);
21954c36
MB		 1442 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1443 ;/* TODO */
1444 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1445 handle_irq_noise(dev);
1446
1447 /* Check the DMA reason registers for received data. */
1448 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1449 if (b43_using_pio(dev))
1450 b43_pio_rx(dev->pio.queue0);
1451 else
1452 b43_dma_rx(dev->dma.rx_ring0);
e4d6b795
MB		 1453 }
1454 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1455 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1456 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1457 if (b43_using_pio(dev))
1458 b43_pio_rx(dev->pio.queue3);
1459 else
1460 b43_dma_rx(dev->dma.rx_ring3);
e4d6b795
MB		 1461 }
1462 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1463 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1464
21954c36 1465 if (reason & B43_IRQ_TX_OK)
e4d6b795 1466 handle_irq_transmit_status(dev);
e4d6b795 1467
e4d6b795
MB		 1468 b43_interrupt_enable(dev, dev->irq_savedstate);
1469 mmiowb();
1470 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1471}
1472
1473static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1474{
1475 u16 rxctl;
1476
1477 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1478 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1479 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1480 else
1481 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1482}
1483
1484static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1485{
1486 if (b43_using_pio(dev) &&
1487 (dev->dev->id.revision < 3) &&
1488 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1489 /* Apply a PIO specific workaround to the dma_reasons */
1490 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1491 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1492 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1493 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1494 }
1495
1496 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1497
1498 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1499 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1500 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1501 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1502 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1503 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1504}
1505
1506/* Interrupt handler top-half */
1507static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1508{
1509 irqreturn_t ret = IRQ_NONE;
1510 struct b43_wldev *dev = dev_id;
1511 u32 reason;
1512
1513 if (!dev)
1514 return IRQ_NONE;
1515
1516 spin_lock(&dev->wl->irq_lock);
1517
1518 if (b43_status(dev) < B43_STAT_STARTED)
1519 goto out;
1520 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1521 if (reason == 0xffffffff) /* shared IRQ */
1522 goto out;
1523 ret = IRQ_HANDLED;
1524 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1525 if (!reason)
1526 goto out;
1527
1528 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1529 & 0x0001DC00;
1530 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1531 & 0x0000DC00;
1532 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1533 & 0x0000DC00;
1534 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1535 & 0x0001DC00;
1536 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1537 & 0x0000DC00;
1538 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1539 & 0x0000DC00;
1540
1541 b43_interrupt_ack(dev, reason);
1542 /* disable all IRQs. They are enabled again in the bottom half. */
1543 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1544 /* save the reason code and call our bottom half. */
1545 dev->irq_reason = reason;
1546 tasklet_schedule(&dev->isr_tasklet);
1547 out:
1548 mmiowb();
1549 spin_unlock(&dev->wl->irq_lock);
1550
1551 return ret;
1552}
1553
1554static void b43_release_firmware(struct b43_wldev *dev)
1555{
1556 release_firmware(dev->fw.ucode);
1557 dev->fw.ucode = NULL;
1558 release_firmware(dev->fw.pcm);
1559 dev->fw.pcm = NULL;
1560 release_firmware(dev->fw.initvals);
1561 dev->fw.initvals = NULL;
1562 release_firmware(dev->fw.initvals_band);
1563 dev->fw.initvals_band = NULL;
1564}
1565
1566static void b43_print_fw_helptext(struct b43_wl *wl)
1567{
1568 b43err(wl, "You must go to "
1569 "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1570 "and download the correct firmware (version 4).\n");
1571}
1572
1573static int do_request_fw(struct b43_wldev *dev,
1574 const char *name,
1575 const struct firmware **fw)
1576{
1a09404a 1577 char path[sizeof(modparam_fwpostfix) + 32];
e4d6b795
MB		 1578 struct b43_fw_header *hdr;
1579 u32 size;
1580 int err;
1581
1582 if (!name)
1583 return 0;
1584
1585 snprintf(path, ARRAY_SIZE(path),
1586 "b43%s/%s.fw",
1587 modparam_fwpostfix, name);
1588 err = request_firmware(fw, path, dev->dev->dev);
1589 if (err) {
1590 b43err(dev->wl, "Firmware file \"%s\" not found "
1591 "or load failed.\n", path);
1592 return err;
1593 }
1594 if ((*fw)->size < sizeof(struct b43_fw_header))
1595 goto err_format;
1596 hdr = (struct b43_fw_header *)((*fw)->data);
1597 switch (hdr->type) {
1598 case B43_FW_TYPE_UCODE:
1599 case B43_FW_TYPE_PCM:
1600 size = be32_to_cpu(hdr->size);
1601 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1602 goto err_format;
1603 /* fallthrough */
1604 case B43_FW_TYPE_IV:
1605 if (hdr->ver != 1)
1606 goto err_format;
1607 break;
1608 default:
1609 goto err_format;
1610 }
1611
1612 return err;
1613
1614err_format:
1615 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1616 return -EPROTO;
1617}
1618
1619static int b43_request_firmware(struct b43_wldev *dev)
1620{
1621 struct b43_firmware *fw = &dev->fw;
1622 const u8 rev = dev->dev->id.revision;
1623 const char *filename;
1624 u32 tmshigh;
1625 int err;
1626
1627 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1628 if (!fw->ucode) {
1629 if ((rev >= 5) && (rev <= 10))
1630 filename = "ucode5";
1631 else if ((rev >= 11) && (rev <= 12))
1632 filename = "ucode11";
1633 else if (rev >= 13)
1634 filename = "ucode13";
1635 else
1636 goto err_no_ucode;
1637 err = do_request_fw(dev, filename, &fw->ucode);
1638 if (err)
1639 goto err_load;
1640 }
1641 if (!fw->pcm) {
1642 if ((rev >= 5) && (rev <= 10))
1643 filename = "pcm5";
1644 else if (rev >= 11)
1645 filename = NULL;
1646 else
1647 goto err_no_pcm;
1648 err = do_request_fw(dev, filename, &fw->pcm);
1649 if (err)
1650 goto err_load;
1651 }
1652 if (!fw->initvals) {
1653 switch (dev->phy.type) {
1654 case B43_PHYTYPE_A:
1655 if ((rev >= 5) && (rev <= 10)) {
1656 if (tmshigh & B43_TMSHIGH_GPHY)
1657 filename = "a0g1initvals5";
1658 else
1659 filename = "a0g0initvals5";
1660 } else
1661 goto err_no_initvals;
1662 break;
1663 case B43_PHYTYPE_G:
1664 if ((rev >= 5) && (rev <= 10))
1665 filename = "b0g0initvals5";
1666 else if (rev >= 13)
1667 filename = "lp0initvals13";
1668 else
1669 goto err_no_initvals;
1670 break;
1671 default:
1672 goto err_no_initvals;
1673 }
1674 err = do_request_fw(dev, filename, &fw->initvals);
1675 if (err)
1676 goto err_load;
1677 }
1678 if (!fw->initvals_band) {
1679 switch (dev->phy.type) {
1680 case B43_PHYTYPE_A:
1681 if ((rev >= 5) && (rev <= 10)) {
1682 if (tmshigh & B43_TMSHIGH_GPHY)
1683 filename = "a0g1bsinitvals5";
1684 else
1685 filename = "a0g0bsinitvals5";
1686 } else if (rev >= 11)
1687 filename = NULL;
1688 else
1689 goto err_no_initvals;
1690 break;
1691 case B43_PHYTYPE_G:
1692 if ((rev >= 5) && (rev <= 10))
1693 filename = "b0g0bsinitvals5";
1694 else if (rev >= 11)
1695 filename = NULL;
1696 else
1697 goto err_no_initvals;
1698 break;
1699 default:
1700 goto err_no_initvals;
1701 }
1702 err = do_request_fw(dev, filename, &fw->initvals_band);
1703 if (err)
1704 goto err_load;
1705 }
1706
1707 return 0;
1708
1709err_load:
1710 b43_print_fw_helptext(dev->wl);
1711 goto error;
1712
1713err_no_ucode:
1714 err = -ENODEV;
1715 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1716 goto error;
1717
1718err_no_pcm:
1719 err = -ENODEV;
1720 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1721 goto error;
1722
1723err_no_initvals:
1724 err = -ENODEV;
1725 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1726 "core rev %u\n", dev->phy.type, rev);
1727 goto error;
1728
1729error:
1730 b43_release_firmware(dev);
1731 return err;
1732}
1733
1734static int b43_upload_microcode(struct b43_wldev *dev)
1735{
1736 const size_t hdr_len = sizeof(struct b43_fw_header);
1737 const __be32 *data;
1738 unsigned int i, len;
1739 u16 fwrev, fwpatch, fwdate, fwtime;
1740 u32 tmp;
1741 int err = 0;
1742
1743 /* Upload Microcode. */
1744 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1745 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1746 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1747 for (i = 0; i < len; i++) {
1748 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1749 udelay(10);
1750 }
1751
1752 if (dev->fw.pcm) {
1753 /* Upload PCM data. */
1754 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1755 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1756 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1757 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1758 /* No need for autoinc bit in SHM_HW */
1759 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1760 for (i = 0; i < len; i++) {
1761 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1762 udelay(10);
1763 }
1764 }
1765
1766 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1767 b43_write32(dev, B43_MMIO_MACCTL,
1768 B43_MACCTL_PSM_RUN |
1769 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1770
1771 /* Wait for the microcode to load and respond */
1772 i = 0;
1773 while (1) {
1774 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1775 if (tmp == B43_IRQ_MAC_SUSPENDED)
1776 break;
1777 i++;
1778 if (i >= 50) {
1779 b43err(dev->wl, "Microcode not responding\n");
1780 b43_print_fw_helptext(dev->wl);
1781 err = -ENODEV;
1782 goto out;
1783 }
1784 udelay(10);
1785 }
1786 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1787
1788 /* Get and check the revisions. */
1789 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1790 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1791 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1792 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1793
1794 if (fwrev <= 0x128) {
1795 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1796 "binary drivers older than version 4.x is unsupported. "
1797 "You must upgrade your firmware files.\n");
1798 b43_print_fw_helptext(dev->wl);
1799 b43_write32(dev, B43_MMIO_MACCTL, 0);
1800 err = -EOPNOTSUPP;
1801 goto out;
1802 }
1803 b43dbg(dev->wl, "Loading firmware version %u.%u "
1804 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1805 fwrev, fwpatch,
1806 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1807 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1808
1809 dev->fw.rev = fwrev;
1810 dev->fw.patch = fwpatch;
1811
1812 out:
1813 return err;
1814}
1815
1816static int b43_write_initvals(struct b43_wldev *dev,
1817 const struct b43_iv *ivals,
1818 size_t count,
1819 size_t array_size)
1820{
1821 const struct b43_iv *iv;
1822 u16 offset;
1823 size_t i;
1824 bool bit32;
1825
1826 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1827 iv = ivals;
1828 for (i = 0; i < count; i++) {
1829 if (array_size < sizeof(iv->offset_size))
1830 goto err_format;
1831 array_size -= sizeof(iv->offset_size);
1832 offset = be16_to_cpu(iv->offset_size);
1833 bit32 = !!(offset & B43_IV_32BIT);
1834 offset &= B43_IV_OFFSET_MASK;
1835 if (offset >= 0x1000)
1836 goto err_format;
1837 if (bit32) {
1838 u32 value;
1839
1840 if (array_size < sizeof(iv->data.d32))
1841 goto err_format;
1842 array_size -= sizeof(iv->data.d32);
1843
1844 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1845 b43_write32(dev, offset, value);
1846
1847 iv = (const struct b43_iv *)((const uint8_t *)iv +
1848 sizeof(__be16) +
1849 sizeof(__be32));
1850 } else {
1851 u16 value;
1852
1853 if (array_size < sizeof(iv->data.d16))
1854 goto err_format;
1855 array_size -= sizeof(iv->data.d16);
1856
1857 value = be16_to_cpu(iv->data.d16);
1858 b43_write16(dev, offset, value);
1859
1860 iv = (const struct b43_iv *)((const uint8_t *)iv +
1861 sizeof(__be16) +
1862 sizeof(__be16));
1863 }
1864 }
1865 if (array_size)
1866 goto err_format;
1867
1868 return 0;
1869
1870err_format:
1871 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1872 b43_print_fw_helptext(dev->wl);
1873
1874 return -EPROTO;
1875}
1876
1877static int b43_upload_initvals(struct b43_wldev *dev)
1878{
1879 const size_t hdr_len = sizeof(struct b43_fw_header);
1880 const struct b43_fw_header *hdr;
1881 struct b43_firmware *fw = &dev->fw;
1882 const struct b43_iv *ivals;
1883 size_t count;
1884 int err;
1885
1886 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1887 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1888 count = be32_to_cpu(hdr->size);
1889 err = b43_write_initvals(dev, ivals, count,
1890 fw->initvals->size - hdr_len);
1891 if (err)
1892 goto out;
1893 if (fw->initvals_band) {
1894 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1895 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1896 count = be32_to_cpu(hdr->size);
1897 err = b43_write_initvals(dev, ivals, count,
1898 fw->initvals_band->size - hdr_len);
1899 if (err)
1900 goto out;
1901 }
1902out:
1903
1904 return err;
1905}
1906
1907/* Initialize the GPIOs
1908 * http://bcm-specs.sipsolutions.net/GPIO
1909 */
1910static int b43_gpio_init(struct b43_wldev *dev)
1911{
1912 struct ssb_bus *bus = dev->dev->bus;
1913 struct ssb_device *gpiodev, *pcidev = NULL;
1914 u32 mask, set;
1915
1916 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1917 & ~B43_MACCTL_GPOUTSMSK);
1918
e4d6b795
MB		 1919 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1920 | 0x000F);
1921
1922 mask = 0x0000001F;
1923 set = 0x0000000F;
1924 if (dev->dev->bus->chip_id == 0x4301) {
1925 mask |= 0x0060;
1926 set |= 0x0060;
1927 }
1928 if (0 /* FIXME: conditional unknown */ ) {
1929 b43_write16(dev, B43_MMIO_GPIO_MASK,
1930 b43_read16(dev, B43_MMIO_GPIO_MASK)
1931 | 0x0100);
1932 mask |= 0x0180;
1933 set |= 0x0180;
1934 }
1935 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1936 b43_write16(dev, B43_MMIO_GPIO_MASK,
1937 b43_read16(dev, B43_MMIO_GPIO_MASK)
1938 | 0x0200);
1939 mask |= 0x0200;
1940 set |= 0x0200;
1941 }
1942 if (dev->dev->id.revision >= 2)
1943 mask |= 0x0010; /* FIXME: This is redundant. */
1944
1945#ifdef CONFIG_SSB_DRIVER_PCICORE
1946 pcidev = bus->pcicore.dev;
1947#endif
1948 gpiodev = bus->chipco.dev ? : pcidev;
1949 if (!gpiodev)
1950 return 0;
1951 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1952 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1953 & mask) | set);
1954
1955 return 0;
1956}
1957
1958/* Turn off all GPIO stuff. Call this on module unload, for example. */
1959static void b43_gpio_cleanup(struct b43_wldev *dev)
1960{
1961 struct ssb_bus *bus = dev->dev->bus;
1962 struct ssb_device *gpiodev, *pcidev = NULL;
1963
1964#ifdef CONFIG_SSB_DRIVER_PCICORE
1965 pcidev = bus->pcicore.dev;
1966#endif
1967 gpiodev = bus->chipco.dev ? : pcidev;
1968 if (!gpiodev)
1969 return;
1970 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1971}
1972
1973/* http://bcm-specs.sipsolutions.net/EnableMac */
1974void b43_mac_enable(struct b43_wldev *dev)
1975{
1976 dev->mac_suspended--;
1977 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 1978 B43_WARN_ON(irqs_disabled());
e4d6b795
MB		 1979 if (dev->mac_suspended == 0) {
1980 b43_write32(dev, B43_MMIO_MACCTL,
1981 b43_read32(dev, B43_MMIO_MACCTL)
1982 | B43_MACCTL_ENABLED);
1983 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1984 B43_IRQ_MAC_SUSPENDED);
1985 /* Commit writes */
1986 b43_read32(dev, B43_MMIO_MACCTL);
1987 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1988 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 1989
1990 /* Re-enable IRQs. */
1991 spin_lock_irq(&dev->wl->irq_lock);
1992 b43_interrupt_enable(dev, dev->irq_savedstate);
1993 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 1994 }
1995}
1996
1997/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1998void b43_mac_suspend(struct b43_wldev *dev)
1999{
2000 int i;
2001 u32 tmp;
2002
05b64b36
MB		 2003 might_sleep();
2004 B43_WARN_ON(irqs_disabled());
e4d6b795 2005 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2006
e4d6b795 2007 if (dev->mac_suspended == 0) {
05b64b36
MB		 2008 /* Mask IRQs before suspending MAC. Otherwise
2009 * the MAC stays busy and won't suspend. */
2010 spin_lock_irq(&dev->wl->irq_lock);
2011 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2012 spin_unlock_irq(&dev->wl->irq_lock);
2013 b43_synchronize_irq(dev);
2014 dev->irq_savedstate = tmp;
2015
e4d6b795
MB		 2016 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2017 b43_write32(dev, B43_MMIO_MACCTL,
2018 b43_read32(dev, B43_MMIO_MACCTL)
2019 & ~B43_MACCTL_ENABLED);
2020 /* force pci to flush the write */
2021 b43_read32(dev, B43_MMIO_MACCTL);
05b64b36 2022 for (i = 40; i; i--) {
e4d6b795
MB		 2023 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2024 if (tmp & B43_IRQ_MAC_SUSPENDED)
2025 goto out;
05b64b36 2026 msleep(1);
e4d6b795
MB		 2027 }
2028 b43err(dev->wl, "MAC suspend failed\n");
2029 }
05b64b36 2030out:
e4d6b795
MB		 2031 dev->mac_suspended++;
2032}
2033
2034static void b43_adjust_opmode(struct b43_wldev *dev)
2035{
2036 struct b43_wl *wl = dev->wl;
2037 u32 ctl;
2038 u16 cfp_pretbtt;
2039
2040 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2041 /* Reset status to STA infrastructure mode. */
2042 ctl &= ~B43_MACCTL_AP;
2043 ctl &= ~B43_MACCTL_KEEP_CTL;
2044 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2045 ctl &= ~B43_MACCTL_KEEP_BAD;
2046 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2047 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2048 ctl |= B43_MACCTL_INFRA;
2049
4150c572
JB		 2050 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2051 ctl |= B43_MACCTL_AP;
2052 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2053 ctl &= ~B43_MACCTL_INFRA;
2054
2055 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2056 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2057 if (wl->filter_flags & FIF_FCSFAIL)
2058 ctl |= B43_MACCTL_KEEP_BAD;
2059 if (wl->filter_flags & FIF_PLCPFAIL)
2060 ctl |= B43_MACCTL_KEEP_BADPLCP;
2061 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2062 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2063 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2064 ctl |= B43_MACCTL_BEACPROMISC;
2065
e4d6b795
MB		 2066 /* Workaround: On old hardware the HW-MAC-address-filter
2067 * doesn't work properly, so always run promisc in filter
2068 * it in software. */
2069 if (dev->dev->id.revision <= 4)
2070 ctl |= B43_MACCTL_PROMISC;
2071
2072 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2073
2074 cfp_pretbtt = 2;
2075 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2076 if (dev->dev->bus->chip_id == 0x4306 &&
2077 dev->dev->bus->chip_rev == 3)
2078 cfp_pretbtt = 100;
2079 else
2080 cfp_pretbtt = 50;
2081 }
2082 b43_write16(dev, 0x612, cfp_pretbtt);
2083}
2084
2085static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2086{
2087 u16 offset;
2088
2089 if (is_ofdm) {
2090 offset = 0x480;
2091 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2092 } else {
2093 offset = 0x4C0;
2094 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2095 }
2096 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2097 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2098}
2099
2100static void b43_rate_memory_init(struct b43_wldev *dev)
2101{
2102 switch (dev->phy.type) {
2103 case B43_PHYTYPE_A:
2104 case B43_PHYTYPE_G:
2105 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2106 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2107 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2108 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2109 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2110 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2111 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2112 if (dev->phy.type == B43_PHYTYPE_A)
2113 break;
2114 /* fallthrough */
2115 case B43_PHYTYPE_B:
2116 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2117 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2118 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2119 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2120 break;
2121 default:
2122 B43_WARN_ON(1);
2123 }
2124}
2125
2126/* Set the TX-Antenna for management frames sent by firmware. */
2127static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2128{
2129 u16 ant = 0;
2130 u16 tmp;
2131
2132 switch (antenna) {
2133 case B43_ANTENNA0:
2134 ant |= B43_TX4_PHY_ANT0;
2135 break;
2136 case B43_ANTENNA1:
2137 ant |= B43_TX4_PHY_ANT1;
2138 break;
2139 case B43_ANTENNA_AUTO:
2140 ant |= B43_TX4_PHY_ANTLAST;
2141 break;
2142 default:
2143 B43_WARN_ON(1);
2144 }
2145
2146 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2147
2148 /* For Beacons */
2149 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2150 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2151 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2152 /* For ACK/CTS */
2153 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2154 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2155 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2156 /* For Probe Resposes */
2157 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2158 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2159 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2160}
2161
2162/* This is the opposite of b43_chip_init() */
2163static void b43_chip_exit(struct b43_wldev *dev)
2164{
8e9f7529 2165 b43_radio_turn_off(dev, 1);
21954c36 2166 b43_leds_exit(dev);
e4d6b795
MB		 2167 b43_gpio_cleanup(dev);
2168 /* firmware is released later */
2169}
2170
2171/* Initialize the chip
2172 * http://bcm-specs.sipsolutions.net/ChipInit
2173 */
2174static int b43_chip_init(struct b43_wldev *dev)
2175{
2176 struct b43_phy *phy = &dev->phy;
2177 int err, tmp;
2178 u32 value32;
2179 u16 value16;
2180
2181 b43_write32(dev, B43_MMIO_MACCTL,
2182 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2183
2184 err = b43_request_firmware(dev);
2185 if (err)
2186 goto out;
2187 err = b43_upload_microcode(dev);
2188 if (err)
2189 goto out; /* firmware is released later */
2190
2191 err = b43_gpio_init(dev);
2192 if (err)
2193 goto out; /* firmware is released later */
21954c36
MB		 2194 b43_leds_init(dev);
2195
e4d6b795
MB		 2196 err = b43_upload_initvals(dev);
2197 if (err)
21954c36 2198 goto err_leds_exit;
e4d6b795 2199 b43_radio_turn_on(dev);
e4d6b795
MB		 2200
2201 b43_write16(dev, 0x03E6, 0x0000);
2202 err = b43_phy_init(dev);
2203 if (err)
2204 goto err_radio_off;
2205
2206 /* Select initial Interference Mitigation. */
2207 tmp = phy->interfmode;
2208 phy->interfmode = B43_INTERFMODE_NONE;
2209 b43_radio_set_interference_mitigation(dev, tmp);
2210
2211 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2212 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2213
2214 if (phy->type == B43_PHYTYPE_B) {
2215 value16 = b43_read16(dev, 0x005E);
2216 value16 |= 0x0004;
2217 b43_write16(dev, 0x005E, value16);
2218 }
2219 b43_write32(dev, 0x0100, 0x01000000);
2220 if (dev->dev->id.revision < 5)
2221 b43_write32(dev, 0x010C, 0x01000000);
2222
2223 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2224 & ~B43_MACCTL_INFRA);
2225 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2226 | B43_MACCTL_INFRA);
e4d6b795
MB		 2227
2228 if (b43_using_pio(dev)) {
2229 b43_write32(dev, 0x0210, 0x00000100);
2230 b43_write32(dev, 0x0230, 0x00000100);
2231 b43_write32(dev, 0x0250, 0x00000100);
2232 b43_write32(dev, 0x0270, 0x00000100);
2233 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2234 }
2235
2236 /* Probe Response Timeout value */
2237 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2238 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2239
2240 /* Initially set the wireless operation mode. */
2241 b43_adjust_opmode(dev);
2242
2243 if (dev->dev->id.revision < 3) {
2244 b43_write16(dev, 0x060E, 0x0000);
2245 b43_write16(dev, 0x0610, 0x8000);
2246 b43_write16(dev, 0x0604, 0x0000);
2247 b43_write16(dev, 0x0606, 0x0200);
2248 } else {
2249 b43_write32(dev, 0x0188, 0x80000000);
2250 b43_write32(dev, 0x018C, 0x02000000);
2251 }
2252 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2253 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2254 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2255 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2256 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2257 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2258 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2259
2260 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2261 value32 |= 0x00100000;
2262 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2263
2264 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2265 dev->dev->bus->chipco.fast_pwrup_delay);
2266
2267 err = 0;
2268 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2269out:
e4d6b795
MB		 2270 return err;
2271
21954c36 2272err_radio_off:
8e9f7529 2273 b43_radio_turn_off(dev, 1);
21954c36
MB		 2274err_leds_exit:
2275 b43_leds_exit(dev);
e4d6b795 2276 b43_gpio_cleanup(dev);
21954c36 2277 return err;
e4d6b795
MB		 2278}
2279
2280static void b43_periodic_every120sec(struct b43_wldev *dev)
2281{
2282 struct b43_phy *phy = &dev->phy;
2283
2284 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2285 return;
2286
2287 b43_mac_suspend(dev);
2288 b43_lo_g_measure(dev);
2289 b43_mac_enable(dev);
2290 if (b43_has_hardware_pctl(phy))
2291 b43_lo_g_ctl_mark_all_unused(dev);
2292}
2293
2294static void b43_periodic_every60sec(struct b43_wldev *dev)
2295{
2296 struct b43_phy *phy = &dev->phy;
2297
2298 if (!b43_has_hardware_pctl(phy))
2299 b43_lo_g_ctl_mark_all_unused(dev);
2300 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2301 b43_mac_suspend(dev);
2302 b43_calc_nrssi_slope(dev);
2303 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2304 u8 old_chan = phy->channel;
2305
2306 /* VCO Calibration */
2307 if (old_chan >= 8)
2308 b43_radio_selectchannel(dev, 1, 0);
2309 else
2310 b43_radio_selectchannel(dev, 13, 0);
2311 b43_radio_selectchannel(dev, old_chan, 0);
2312 }
2313 b43_mac_enable(dev);
2314 }
2315}
2316
2317static void b43_periodic_every30sec(struct b43_wldev *dev)
2318{
2319 /* Update device statistics. */
2320 b43_calculate_link_quality(dev);
2321}
2322
2323static void b43_periodic_every15sec(struct b43_wldev *dev)
2324{
2325 struct b43_phy *phy = &dev->phy;
2326
2327 if (phy->type == B43_PHYTYPE_G) {
2328 //TODO: update_aci_moving_average
2329 if (phy->aci_enable && phy->aci_wlan_automatic) {
2330 b43_mac_suspend(dev);
2331 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2332 if (0 /*TODO: bunch of conditions */ ) {
2333 b43_radio_set_interference_mitigation
2334 (dev, B43_INTERFMODE_MANUALWLAN);
2335 }
2336 } else if (1 /*TODO*/) {
2337 /*
2338 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2339 b43_radio_set_interference_mitigation(dev,
2340 B43_INTERFMODE_NONE);
2341 }
2342 */
2343 }
2344 b43_mac_enable(dev);
2345 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2346 phy->rev == 1) {
2347 //TODO: implement rev1 workaround
2348 }
2349 }
2350 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2351 //TODO for APHY (temperature?)
2352}
2353
e4d6b795
MB		 2354static void do_periodic_work(struct b43_wldev *dev)
2355{
2356 unsigned int state;
2357
2358 state = dev->periodic_state;
42bb4cd5 2359 if (state % 8 == 0)
e4d6b795 2360 b43_periodic_every120sec(dev);
42bb4cd5 2361 if (state % 4 == 0)
e4d6b795 2362 b43_periodic_every60sec(dev);
42bb4cd5 2363 if (state % 2 == 0)
e4d6b795 2364 b43_periodic_every30sec(dev);
42bb4cd5 2365 b43_periodic_every15sec(dev);
e4d6b795
MB		 2366}
2367
05b64b36
MB		 2368/* Periodic work locking policy:
2369 * The whole periodic work handler is protected by
2370 * wl->mutex. If another lock is needed somewhere in the
2371 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2372 */
e4d6b795
MB		 2373static void b43_periodic_work_handler(struct work_struct *work)
2374{
05b64b36
MB		 2375 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2376 periodic_work.work);
2377 struct b43_wl *wl = dev->wl;
2378 unsigned long delay;
e4d6b795 2379
05b64b36 2380 mutex_lock(&wl->mutex);
e4d6b795
MB		 2381
2382 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2383 goto out;
2384 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2385 goto out_requeue;
2386
05b64b36 2387 do_periodic_work(dev);
e4d6b795 2388
e4d6b795 2389 dev->periodic_state++;
42bb4cd5 2390out_requeue:
e4d6b795
MB		 2391 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2392 delay = msecs_to_jiffies(50);
2393 else
82cd682d 2394 delay = round_jiffies_relative(HZ * 15);
05b64b36 2395 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2396out:
05b64b36 2397 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2398}
2399
2400static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2401{
2402 struct delayed_work *work = &dev->periodic_work;
2403
2404 dev->periodic_state = 0;
2405 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2406 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2407}
2408
2409/* Validate access to the chip (SHM) */
2410static int b43_validate_chipaccess(struct b43_wldev *dev)
2411{
2412 u32 value;
2413 u32 shm_backup;
2414
2415 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2416 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2417 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2418 goto error;
2419 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2420 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2421 goto error;
2422 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2423
2424 value = b43_read32(dev, B43_MMIO_MACCTL);
2425 if ((value | B43_MACCTL_GMODE) !=
2426 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2427 goto error;
2428
2429 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2430 if (value)
2431 goto error;
2432
2433 return 0;
2434 error:
2435 b43err(dev->wl, "Failed to validate the chipaccess\n");
2436 return -ENODEV;
2437}
2438
2439static void b43_security_init(struct b43_wldev *dev)
2440{
2441 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2442 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2443 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2444 /* KTP is a word address, but we address SHM bytewise.
2445 * So multiply by two.
2446 */
2447 dev->ktp *= 2;
2448 if (dev->dev->id.revision >= 5) {
2449 /* Number of RCMTA address slots */
2450 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2451 }
2452 b43_clear_keys(dev);
2453}
2454
2455static int b43_rng_read(struct hwrng *rng, u32 * data)
2456{
2457 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2458 unsigned long flags;
2459
2460 /* Don't take wl->mutex here, as it could deadlock with
2461 * hwrng internal locking. It's not needed to take
2462 * wl->mutex here, anyway. */
2463
2464 spin_lock_irqsave(&wl->irq_lock, flags);
2465 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2466 spin_unlock_irqrestore(&wl->irq_lock, flags);
2467
2468 return (sizeof(u16));
2469}
2470
2471static void b43_rng_exit(struct b43_wl *wl)
2472{
2473 if (wl->rng_initialized)
2474 hwrng_unregister(&wl->rng);
2475}
2476
2477static int b43_rng_init(struct b43_wl *wl)
2478{
2479 int err;
2480
2481 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2482 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2483 wl->rng.name = wl->rng_name;
2484 wl->rng.data_read = b43_rng_read;
2485 wl->rng.priv = (unsigned long)wl;
2486 wl->rng_initialized = 1;
2487 err = hwrng_register(&wl->rng);
2488 if (err) {
2489 wl->rng_initialized = 0;
2490 b43err(wl, "Failed to register the random "
2491 "number generator (%d)\n", err);
2492 }
2493
2494 return err;
2495}
2496
2497static int b43_tx(struct ieee80211_hw *hw,
2498 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2499{
2500 struct b43_wl *wl = hw_to_b43_wl(hw);
2501 struct b43_wldev *dev = wl->current_dev;
2502 int err = -ENODEV;
2503 unsigned long flags;
2504
2505 if (unlikely(!dev))
2506 goto out;
2507 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2508 goto out;
2509 /* DMA-TX is done without a global lock. */
2510 if (b43_using_pio(dev)) {
2511 spin_lock_irqsave(&wl->irq_lock, flags);
2512 err = b43_pio_tx(dev, skb, ctl);
2513 spin_unlock_irqrestore(&wl->irq_lock, flags);
2514 } else
2515 err = b43_dma_tx(dev, skb, ctl);
2516 out:
2517 if (unlikely(err))
2518 return NETDEV_TX_BUSY;
2519 return NETDEV_TX_OK;
2520}
2521
2522static int b43_conf_tx(struct ieee80211_hw *hw,
2523 int queue,
2524 const struct ieee80211_tx_queue_params *params)
2525{
2526 return 0;
2527}
2528
2529static int b43_get_tx_stats(struct ieee80211_hw *hw,
2530 struct ieee80211_tx_queue_stats *stats)
2531{
2532 struct b43_wl *wl = hw_to_b43_wl(hw);
2533 struct b43_wldev *dev = wl->current_dev;
2534 unsigned long flags;
2535 int err = -ENODEV;
2536
2537 if (!dev)
2538 goto out;
2539 spin_lock_irqsave(&wl->irq_lock, flags);
2540 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2541 if (b43_using_pio(dev))
2542 b43_pio_get_tx_stats(dev, stats);
2543 else
2544 b43_dma_get_tx_stats(dev, stats);
2545 err = 0;
2546 }
2547 spin_unlock_irqrestore(&wl->irq_lock, flags);
2548 out:
2549 return err;
2550}
2551
2552static int b43_get_stats(struct ieee80211_hw *hw,
2553 struct ieee80211_low_level_stats *stats)
2554{
2555 struct b43_wl *wl = hw_to_b43_wl(hw);
2556 unsigned long flags;
2557
2558 spin_lock_irqsave(&wl->irq_lock, flags);
2559 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2560 spin_unlock_irqrestore(&wl->irq_lock, flags);
2561
2562 return 0;
2563}
2564
2565static const char *phymode_to_string(unsigned int phymode)
2566{
2567 switch (phymode) {
2568 case B43_PHYMODE_A:
2569 return "A";
2570 case B43_PHYMODE_B:
2571 return "B";
2572 case B43_PHYMODE_G:
2573 return "G";
2574 default:
2575 B43_WARN_ON(1);
2576 }
2577 return "";
2578}
2579
2580static int find_wldev_for_phymode(struct b43_wl *wl,
2581 unsigned int phymode,
2582 struct b43_wldev **dev, bool * gmode)
2583{
2584 struct b43_wldev *d;
2585
2586 list_for_each_entry(d, &wl->devlist, list) {
2587 if (d->phy.possible_phymodes & phymode) {
2588 /* Ok, this device supports the PHY-mode.
2589 * Now figure out how the gmode bit has to be
2590 * set to support it. */
2591 if (phymode == B43_PHYMODE_A)
2592 *gmode = 0;
2593 else
2594 *gmode = 1;
2595 *dev = d;
2596
2597 return 0;
2598 }
2599 }
2600
2601 return -ESRCH;
2602}
2603
2604static void b43_put_phy_into_reset(struct b43_wldev *dev)
2605{
2606 struct ssb_device *sdev = dev->dev;
2607 u32 tmslow;
2608
2609 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2610 tmslow &= ~B43_TMSLOW_GMODE;
2611 tmslow |= B43_TMSLOW_PHYRESET;
2612 tmslow |= SSB_TMSLOW_FGC;
2613 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2614 msleep(1);
2615
2616 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2617 tmslow &= ~SSB_TMSLOW_FGC;
2618 tmslow |= B43_TMSLOW_PHYRESET;
2619 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2620 msleep(1);
2621}
2622
2623/* Expects wl->mutex locked */
2624static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2625{
2626 struct b43_wldev *up_dev;
2627 struct b43_wldev *down_dev;
2628 int err;
2629 bool gmode = 0;
2630 int prev_status;
2631
2632 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2633 if (err) {
2634 b43err(wl, "Could not find a device for %s-PHY mode\n",
2635 phymode_to_string(new_mode));
2636 return err;
2637 }
2638 if ((up_dev == wl->current_dev) &&
2639 (!!wl->current_dev->phy.gmode == !!gmode)) {
2640 /* This device is already running. */
2641 return 0;
2642 }
2643 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2644 phymode_to_string(new_mode));
2645 down_dev = wl->current_dev;
2646
2647 prev_status = b43_status(down_dev);
2648 /* Shutdown the currently running core. */
2649 if (prev_status >= B43_STAT_STARTED)
2650 b43_wireless_core_stop(down_dev);
2651 if (prev_status >= B43_STAT_INITIALIZED)
2652 b43_wireless_core_exit(down_dev);
2653
2654 if (down_dev != up_dev) {
2655 /* We switch to a different core, so we put PHY into
2656 * RESET on the old core. */
2657 b43_put_phy_into_reset(down_dev);
2658 }
2659
2660 /* Now start the new core. */
2661 up_dev->phy.gmode = gmode;
2662 if (prev_status >= B43_STAT_INITIALIZED) {
2663 err = b43_wireless_core_init(up_dev);
2664 if (err) {
2665 b43err(wl, "Fatal: Could not initialize device for "
2666 "newly selected %s-PHY mode\n",
2667 phymode_to_string(new_mode));
2668 goto init_failure;
2669 }
2670 }
2671 if (prev_status >= B43_STAT_STARTED) {
2672 err = b43_wireless_core_start(up_dev);
2673 if (err) {
2674 b43err(wl, "Fatal: Coult not start device for "
2675 "newly selected %s-PHY mode\n",
2676 phymode_to_string(new_mode));
2677 b43_wireless_core_exit(up_dev);
2678 goto init_failure;
2679 }
2680 }
2681 B43_WARN_ON(b43_status(up_dev) != prev_status);
2682
2683 wl->current_dev = up_dev;
2684
2685 return 0;
2686 init_failure:
2687 /* Whoops, failed to init the new core. No core is operating now. */
2688 wl->current_dev = NULL;
2689 return err;
2690}
2691
2692static int b43_antenna_from_ieee80211(u8 antenna)
2693{
2694 switch (antenna) {
2695 case 0: /* default/diversity */
2696 return B43_ANTENNA_DEFAULT;
2697 case 1: /* Antenna 0 */
2698 return B43_ANTENNA0;
2699 case 2: /* Antenna 1 */
2700 return B43_ANTENNA1;
2701 default:
2702 return B43_ANTENNA_DEFAULT;
2703 }
2704}
2705
2706static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2707{
2708 struct b43_wl *wl = hw_to_b43_wl(hw);
2709 struct b43_wldev *dev;
2710 struct b43_phy *phy;
2711 unsigned long flags;
2712 unsigned int new_phymode = 0xFFFF;
2713 int antenna_tx;
2714 int antenna_rx;
2715 int err = 0;
2716 u32 savedirqs;
2717
2718 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2719 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2720
2721 mutex_lock(&wl->mutex);
2722
2723 /* Switch the PHY mode (if necessary). */
2724 switch (conf->phymode) {
2725 case MODE_IEEE80211A:
2726 new_phymode = B43_PHYMODE_A;
2727 break;
2728 case MODE_IEEE80211B:
2729 new_phymode = B43_PHYMODE_B;
2730 break;
2731 case MODE_IEEE80211G:
2732 new_phymode = B43_PHYMODE_G;
2733 break;
2734 default:
2735 B43_WARN_ON(1);
2736 }
2737 err = b43_switch_phymode(wl, new_phymode);
2738 if (err)
2739 goto out_unlock_mutex;
2740 dev = wl->current_dev;
2741 phy = &dev->phy;
2742
2743 /* Disable IRQs while reconfiguring the device.
2744 * This makes it possible to drop the spinlock throughout
2745 * the reconfiguration process. */
2746 spin_lock_irqsave(&wl->irq_lock, flags);
2747 if (b43_status(dev) < B43_STAT_STARTED) {
2748 spin_unlock_irqrestore(&wl->irq_lock, flags);
2749 goto out_unlock_mutex;
2750 }
2751 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2752 spin_unlock_irqrestore(&wl->irq_lock, flags);
2753 b43_synchronize_irq(dev);
2754
2755 /* Switch to the requested channel.
2756 * The firmware takes care of races with the TX handler. */
2757 if (conf->channel_val != phy->channel)
2758 b43_radio_selectchannel(dev, conf->channel_val, 0);
2759
2760 /* Enable/Disable ShortSlot timing. */
2761 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2762 dev->short_slot) {
2763 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2764 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2765 b43_short_slot_timing_enable(dev);
2766 else
2767 b43_short_slot_timing_disable(dev);
2768 }
2769
2770 /* Adjust the desired TX power level. */
2771 if (conf->power_level != 0) {
2772 if (conf->power_level != phy->power_level) {
2773 phy->power_level = conf->power_level;
2774 b43_phy_xmitpower(dev);
2775 }
2776 }
2777
2778 /* Antennas for RX and management frame TX. */
2779 b43_mgmtframe_txantenna(dev, antenna_tx);
2780 b43_set_rx_antenna(dev, antenna_rx);
2781
2782 /* Update templates for AP mode. */
2783 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2784 b43_set_beacon_int(dev, conf->beacon_int);
2785
fda9abcf
MB		 2786 if (!!conf->radio_enabled != phy->radio_on) {
2787 if (conf->radio_enabled) {
2788 b43_radio_turn_on(dev);
2789 b43info(dev->wl, "Radio turned on by software\n");
2790 if (!dev->radio_hw_enable) {
2791 b43info(dev->wl, "The hardware RF-kill button "
2792 "still turns the radio physically off. "
2793 "Press the button to turn it on.\n");
2794 }
2795 } else {
8e9f7529 2796 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 2797 b43info(dev->wl, "Radio turned off by software\n");
2798 }
2799 }
2800
e4d6b795
MB		 2801 spin_lock_irqsave(&wl->irq_lock, flags);
2802 b43_interrupt_enable(dev, savedirqs);
2803 mmiowb();
2804 spin_unlock_irqrestore(&wl->irq_lock, flags);
2805 out_unlock_mutex:
2806 mutex_unlock(&wl->mutex);
2807
2808 return err;
2809}
2810
4150c572
JB		 2811static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2812 const u8 *local_addr, const u8 *addr,
2813 struct ieee80211_key_conf *key)
e4d6b795
MB		 2814{
2815 struct b43_wl *wl = hw_to_b43_wl(hw);
2816 struct b43_wldev *dev = wl->current_dev;
2817 unsigned long flags;
2818 u8 algorithm;
2819 u8 index;
2820 int err = -EINVAL;
0795af57 2821 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 2822
2823 if (modparam_nohwcrypt)
2824 return -ENOSPC; /* User disabled HW-crypto */
2825
2826 if (!dev)
2827 return -ENODEV;
2828 switch (key->alg) {
e4d6b795
MB		 2829 case ALG_WEP:
2830 if (key->keylen == 5)
2831 algorithm = B43_SEC_ALGO_WEP40;
2832 else
2833 algorithm = B43_SEC_ALGO_WEP104;
2834 break;
2835 case ALG_TKIP:
2836 algorithm = B43_SEC_ALGO_TKIP;
2837 break;
2838 case ALG_CCMP:
2839 algorithm = B43_SEC_ALGO_AES;
2840 break;
2841 default:
2842 B43_WARN_ON(1);
2843 goto out;
2844 }
2845
2846 index = (u8) (key->keyidx);
2847 if (index > 3)
2848 goto out;
2849
2850 mutex_lock(&wl->mutex);
2851 spin_lock_irqsave(&wl->irq_lock, flags);
2852
2853 if (b43_status(dev) < B43_STAT_INITIALIZED) {
2854 err = -ENODEV;
2855 goto out_unlock;
2856 }
2857
2858 switch (cmd) {
2859 case SET_KEY:
2860 if (algorithm == B43_SEC_ALGO_TKIP) {
2861 /* FIXME: No TKIP hardware encryption for now. */
2862 err = -EOPNOTSUPP;
2863 goto out_unlock;
2864 }
2865
2866 if (is_broadcast_ether_addr(addr)) {
2867 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2868 err = b43_key_write(dev, index, algorithm,
2869 key->key, key->keylen, NULL, key);
2870 } else {
2871 /*
2872 * either pairwise key or address is 00:00:00:00:00:00
2873 * for transmit-only keys
2874 */
2875 err = b43_key_write(dev, -1, algorithm,
2876 key->key, key->keylen, addr, key);
2877 }
2878 if (err)
2879 goto out_unlock;
2880
2881 if (algorithm == B43_SEC_ALGO_WEP40 ||
2882 algorithm == B43_SEC_ALGO_WEP104) {
2883 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2884 } else {
2885 b43_hf_write(dev,
2886 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2887 }
2888 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2889 break;
2890 case DISABLE_KEY: {
2891 err = b43_key_clear(dev, key->hw_key_idx);
2892 if (err)
2893 goto out_unlock;
2894 break;
2895 }
2896 default:
2897 B43_WARN_ON(1);
2898 }
2899out_unlock:
2900 spin_unlock_irqrestore(&wl->irq_lock, flags);
2901 mutex_unlock(&wl->mutex);
2902out:
2903 if (!err) {
2904 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 2905 "mac: %s\n",
e4d6b795 2906 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 2907 print_mac(mac, addr));
e4d6b795
MB		 2908 }
2909 return err;
2910}
2911
4150c572
JB		 2912static void b43_configure_filter(struct ieee80211_hw *hw,
2913 unsigned int changed, unsigned int *fflags,
2914 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 2915{
2916 struct b43_wl *wl = hw_to_b43_wl(hw);
2917 struct b43_wldev *dev = wl->current_dev;
2918 unsigned long flags;
2919
4150c572
JB		 2920 if (!dev) {
2921 *fflags = 0;
e4d6b795 2922 return;
e4d6b795 2923 }
4150c572
JB		 2924
2925 spin_lock_irqsave(&wl->irq_lock, flags);
2926 *fflags &= FIF_PROMISC_IN_BSS |
2927 FIF_ALLMULTI |
2928 FIF_FCSFAIL |
2929 FIF_PLCPFAIL |
2930 FIF_CONTROL |
2931 FIF_OTHER_BSS |
2932 FIF_BCN_PRBRESP_PROMISC;
2933
2934 changed &= FIF_PROMISC_IN_BSS |
2935 FIF_ALLMULTI |
2936 FIF_FCSFAIL |
2937 FIF_PLCPFAIL |
2938 FIF_CONTROL |
2939 FIF_OTHER_BSS |
2940 FIF_BCN_PRBRESP_PROMISC;
2941
2942 wl->filter_flags = *fflags;
2943
2944 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2945 b43_adjust_opmode(dev);
e4d6b795
MB		 2946 spin_unlock_irqrestore(&wl->irq_lock, flags);
2947}
2948
2949static int b43_config_interface(struct ieee80211_hw *hw,
2950 int if_id, struct ieee80211_if_conf *conf)
2951{
2952 struct b43_wl *wl = hw_to_b43_wl(hw);
2953 struct b43_wldev *dev = wl->current_dev;
2954 unsigned long flags;
2955
2956 if (!dev)
2957 return -ENODEV;
2958 mutex_lock(&wl->mutex);
2959 spin_lock_irqsave(&wl->irq_lock, flags);
4150c572
JB		 2960 B43_WARN_ON(wl->if_id != if_id);
2961 if (conf->bssid)
2962 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2963 else
2964 memset(wl->bssid, 0, ETH_ALEN);
2965 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2966 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2967 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2968 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2969 if (conf->beacon)
2970 b43_refresh_templates(dev, conf->beacon);
e4d6b795 2971 }
4150c572 2972 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 2973 }
2974 spin_unlock_irqrestore(&wl->irq_lock, flags);
2975 mutex_unlock(&wl->mutex);
2976
2977 return 0;
2978}
2979
2980/* Locking: wl->mutex */
2981static void b43_wireless_core_stop(struct b43_wldev *dev)
2982{
2983 struct b43_wl *wl = dev->wl;
2984 unsigned long flags;
2985
2986 if (b43_status(dev) < B43_STAT_STARTED)
2987 return;
2988 b43_set_status(dev, B43_STAT_INITIALIZED);
2989
2990 mutex_unlock(&wl->mutex);
2991 /* Must unlock as it would otherwise deadlock. No races here.
2992 * Cancel the possibly running self-rearming periodic work. */
2993 cancel_delayed_work_sync(&dev->periodic_work);
2994 mutex_lock(&wl->mutex);
2995
2996 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2997
2998 /* Disable and sync interrupts. */
2999 spin_lock_irqsave(&wl->irq_lock, flags);
3000 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3001 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3002 spin_unlock_irqrestore(&wl->irq_lock, flags);
3003 b43_synchronize_irq(dev);
3004
3005 b43_mac_suspend(dev);
3006 free_irq(dev->dev->irq, dev);
3007 b43dbg(wl, "Wireless interface stopped\n");
3008}
3009
3010/* Locking: wl->mutex */
3011static int b43_wireless_core_start(struct b43_wldev *dev)
3012{
3013 int err;
3014
3015 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3016
3017 drain_txstatus_queue(dev);
3018 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3019 IRQF_SHARED, KBUILD_MODNAME, dev);
3020 if (err) {
3021 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3022 goto out;
3023 }
3024
3025 /* We are ready to run. */
3026 b43_set_status(dev, B43_STAT_STARTED);
3027
3028 /* Start data flow (TX/RX). */
3029 b43_mac_enable(dev);
3030 b43_interrupt_enable(dev, dev->irq_savedstate);
3031 ieee80211_start_queues(dev->wl->hw);
3032
3033 /* Start maintainance work */
3034 b43_periodic_tasks_setup(dev);
3035
3036 b43dbg(dev->wl, "Wireless interface started\n");
3037 out:
3038 return err;
3039}
3040
3041/* Get PHY and RADIO versioning numbers */
3042static int b43_phy_versioning(struct b43_wldev *dev)
3043{
3044 struct b43_phy *phy = &dev->phy;
3045 u32 tmp;
3046 u8 analog_type;
3047 u8 phy_type;
3048 u8 phy_rev;
3049 u16 radio_manuf;
3050 u16 radio_ver;
3051 u16 radio_rev;
3052 int unsupported = 0;
3053
3054 /* Get PHY versioning */
3055 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3056 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3057 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3058 phy_rev = (tmp & B43_PHYVER_VERSION);
3059 switch (phy_type) {
3060 case B43_PHYTYPE_A:
3061 if (phy_rev >= 4)
3062 unsupported = 1;
3063 break;
3064 case B43_PHYTYPE_B:
3065 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3066 && phy_rev != 7)
3067 unsupported = 1;
3068 break;
3069 case B43_PHYTYPE_G:
3070 if (phy_rev > 8)
3071 unsupported = 1;
3072 break;
3073 default:
3074 unsupported = 1;
3075 };
3076 if (unsupported) {
3077 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3078 "(Analog %u, Type %u, Revision %u)\n",
3079 analog_type, phy_type, phy_rev);
3080 return -EOPNOTSUPP;
3081 }
3082 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3083 analog_type, phy_type, phy_rev);
3084
3085 /* Get RADIO versioning */
3086 if (dev->dev->bus->chip_id == 0x4317) {
3087 if (dev->dev->bus->chip_rev == 0)
3088 tmp = 0x3205017F;
3089 else if (dev->dev->bus->chip_rev == 1)
3090 tmp = 0x4205017F;
3091 else
3092 tmp = 0x5205017F;
3093 } else {
3094 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3095 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3096 tmp <<= 16;
3097 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3098 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3099 }
3100 radio_manuf = (tmp & 0x00000FFF);
3101 radio_ver = (tmp & 0x0FFFF000) >> 12;
3102 radio_rev = (tmp & 0xF0000000) >> 28;
3103 switch (phy_type) {
3104 case B43_PHYTYPE_A:
3105 if (radio_ver != 0x2060)
3106 unsupported = 1;
3107 if (radio_rev != 1)
3108 unsupported = 1;
3109 if (radio_manuf != 0x17F)
3110 unsupported = 1;
3111 break;
3112 case B43_PHYTYPE_B:
3113 if ((radio_ver & 0xFFF0) != 0x2050)
3114 unsupported = 1;
3115 break;
3116 case B43_PHYTYPE_G:
3117 if (radio_ver != 0x2050)
3118 unsupported = 1;
3119 break;
3120 default:
3121 B43_WARN_ON(1);
3122 }
3123 if (unsupported) {
3124 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3125 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3126 radio_manuf, radio_ver, radio_rev);
3127 return -EOPNOTSUPP;
3128 }
3129 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3130 radio_manuf, radio_ver, radio_rev);
3131
3132 phy->radio_manuf = radio_manuf;
3133 phy->radio_ver = radio_ver;
3134 phy->radio_rev = radio_rev;
3135
3136 phy->analog = analog_type;
3137 phy->type = phy_type;
3138 phy->rev = phy_rev;
3139
3140 return 0;
3141}
3142
3143static void setup_struct_phy_for_init(struct b43_wldev *dev,
3144 struct b43_phy *phy)
3145{
3146 struct b43_txpower_lo_control *lo;
3147 int i;
3148
3149 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3150 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3151
3152 /* Flags */
3153 phy->locked = 0;
3154
3155 phy->aci_enable = 0;
3156 phy->aci_wlan_automatic = 0;
3157 phy->aci_hw_rssi = 0;
3158
fda9abcf
MB		 3159 phy->radio_off_context.valid = 0;
3160
e4d6b795
MB		 3161 lo = phy->lo_control;
3162 if (lo) {
3163 memset(lo, 0, sizeof(*(phy->lo_control)));
3164 lo->rebuild = 1;
3165 lo->tx_bias = 0xFF;
3166 }
3167 phy->max_lb_gain = 0;
3168 phy->trsw_rx_gain = 0;
3169 phy->txpwr_offset = 0;
3170
3171 /* NRSSI */
3172 phy->nrssislope = 0;
3173 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3174 phy->nrssi[i] = -1000;
3175 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3176 phy->nrssi_lt[i] = i;
3177
3178 phy->lofcal = 0xFFFF;
3179 phy->initval = 0xFFFF;
3180
3181 spin_lock_init(&phy->lock);
3182 phy->interfmode = B43_INTERFMODE_NONE;
3183 phy->channel = 0xFF;
3184
3185 phy->hardware_power_control = !!modparam_hwpctl;
3186}
3187
3188static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3189{
3190 /* Flags */
3191 dev->reg124_set_0x4 = 0;
6a724d68
MB		 3192 /* Assume the radio is enabled. If it's not enabled, the state will
3193 * immediately get fixed on the first periodic work run. */
3194 dev->radio_hw_enable = 1;
e4d6b795
MB		 3195
3196 /* Stats */
3197 memset(&dev->stats, 0, sizeof(dev->stats));
3198
3199 setup_struct_phy_for_init(dev, &dev->phy);
3200
3201 /* IRQ related flags */
3202 dev->irq_reason = 0;
3203 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3204 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3205
3206 dev->mac_suspended = 1;
3207
3208 /* Noise calculation context */
3209 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3210}
3211
3212static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3213{
3214 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3215 u32 hf;
3216
3217 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3218 return;
3219 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3220 return;
3221
3222 hf = b43_hf_read(dev);
3223 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3224 hf |= B43_HF_BTCOEXALT;
3225 else
3226 hf |= B43_HF_BTCOEX;
3227 b43_hf_write(dev, hf);
3228 //TODO
3229}
3230
3231static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3232{ //TODO
3233}
3234
3235static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3236{
3237#ifdef CONFIG_SSB_DRIVER_PCICORE
3238 struct ssb_bus *bus = dev->dev->bus;
3239 u32 tmp;
3240
3241 if (bus->pcicore.dev &&
3242 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3243 bus->pcicore.dev->id.revision <= 5) {
3244 /* IMCFGLO timeouts workaround. */
3245 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3246 tmp &= ~SSB_IMCFGLO_REQTO;
3247 tmp &= ~SSB_IMCFGLO_SERTO;
3248 switch (bus->bustype) {
3249 case SSB_BUSTYPE_PCI:
3250 case SSB_BUSTYPE_PCMCIA:
3251 tmp |= 0x32;
3252 break;
3253 case SSB_BUSTYPE_SSB:
3254 tmp |= 0x53;
3255 break;
3256 }
3257 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3258 }
3259#endif /* CONFIG_SSB_DRIVER_PCICORE */
3260}
3261
3262/* Shutdown a wireless core */
3263/* Locking: wl->mutex */
3264static void b43_wireless_core_exit(struct b43_wldev *dev)
3265{
3266 struct b43_phy *phy = &dev->phy;
3267
3268 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3269 if (b43_status(dev) != B43_STAT_INITIALIZED)
3270 return;
3271 b43_set_status(dev, B43_STAT_UNINIT);
3272
8e9f7529
MB		 3273 mutex_unlock(&dev->wl->mutex);
3274 b43_rfkill_exit(dev);
3275 mutex_lock(&dev->wl->mutex);
3276
e4d6b795
MB		 3277 b43_rng_exit(dev->wl);
3278 b43_pio_free(dev);
3279 b43_dma_free(dev);
3280 b43_chip_exit(dev);
8e9f7529 3281 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3282 b43_switch_analog(dev, 0);
3283 if (phy->dyn_tssi_tbl)
3284 kfree(phy->tssi2dbm);
3285 kfree(phy->lo_control);
3286 phy->lo_control = NULL;
3287 ssb_device_disable(dev->dev, 0);
3288 ssb_bus_may_powerdown(dev->dev->bus);
3289}
3290
3291/* Initialize a wireless core */
3292static int b43_wireless_core_init(struct b43_wldev *dev)
3293{
3294 struct b43_wl *wl = dev->wl;
3295 struct ssb_bus *bus = dev->dev->bus;
3296 struct ssb_sprom *sprom = &bus->sprom;
3297 struct b43_phy *phy = &dev->phy;
3298 int err;
3299 u32 hf, tmp;
3300
3301 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3302
3303 err = ssb_bus_powerup(bus, 0);
3304 if (err)
3305 goto out;
3306 if (!ssb_device_is_enabled(dev->dev)) {
3307 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3308 b43_wireless_core_reset(dev, tmp);
3309 }
3310
3311 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3312 phy->lo_control =
3313 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3314 if (!phy->lo_control) {
3315 err = -ENOMEM;
3316 goto err_busdown;
3317 }
3318 }
3319 setup_struct_wldev_for_init(dev);
3320
3321 err = b43_phy_init_tssi2dbm_table(dev);
3322 if (err)
3323 goto err_kfree_lo_control;
3324
3325 /* Enable IRQ routing to this device. */
3326 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3327
3328 b43_imcfglo_timeouts_workaround(dev);
3329 b43_bluetooth_coext_disable(dev);
3330 b43_phy_early_init(dev);
3331 err = b43_chip_init(dev);
3332 if (err)
3333 goto err_kfree_tssitbl;
3334 b43_shm_write16(dev, B43_SHM_SHARED,
3335 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3336 hf = b43_hf_read(dev);
3337 if (phy->type == B43_PHYTYPE_G) {
3338 hf |= B43_HF_SYMW;
3339 if (phy->rev == 1)
3340 hf |= B43_HF_GDCW;
3341 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3342 hf |= B43_HF_OFDMPABOOST;
3343 } else if (phy->type == B43_PHYTYPE_B) {
3344 hf |= B43_HF_SYMW;
3345 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3346 hf &= ~B43_HF_GDCW;
3347 }
3348 b43_hf_write(dev, hf);
3349
3350 /* Short/Long Retry Limit.
3351 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3352 * the chip-internal counter.
3353 */
3354 tmp = limit_value(modparam_short_retry, 0, 0xF);
3355 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3356 tmp = limit_value(modparam_long_retry, 0, 0xF);
3357 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3358
3359 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3360 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3361
3362 /* Disable sending probe responses from firmware.
3363 * Setting the MaxTime to one usec will always trigger
3364 * a timeout, so we never send any probe resp.
3365 * A timeout of zero is infinite. */
3366 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3367
3368 b43_rate_memory_init(dev);
3369
3370 /* Minimum Contention Window */
3371 if (phy->type == B43_PHYTYPE_B) {
3372 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3373 } else {
3374 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3375 }
3376 /* Maximum Contention Window */
3377 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3378
3379 do {
3380 if (b43_using_pio(dev)) {
3381 err = b43_pio_init(dev);
3382 } else {
3383 err = b43_dma_init(dev);
3384 if (!err)
3385 b43_qos_init(dev);
3386 }
3387 } while (err == -EAGAIN);
3388 if (err)
3389 goto err_chip_exit;
3390
3391//FIXME
3392#if 1
3393 b43_write16(dev, 0x0612, 0x0050);
3394 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3395 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3396#endif
3397
3398 b43_bluetooth_coext_enable(dev);
3399
3400 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3401 memset(wl->bssid, 0, ETH_ALEN);
4150c572
JB		 3402 memset(wl->mac_addr, 0, ETH_ALEN);
3403 b43_upload_card_macaddress(dev);
e4d6b795 3404 b43_security_init(dev);
8e9f7529 3405 b43_rfkill_init(dev);
e4d6b795
MB		 3406 b43_rng_init(wl);
3407
3408 b43_set_status(dev, B43_STAT_INITIALIZED);
3409
3410 out:
3411 return err;
3412
3413 err_chip_exit:
3414 b43_chip_exit(dev);
3415 err_kfree_tssitbl:
3416 if (phy->dyn_tssi_tbl)
3417 kfree(phy->tssi2dbm);
3418 err_kfree_lo_control:
3419 kfree(phy->lo_control);
3420 phy->lo_control = NULL;
3421 err_busdown:
3422 ssb_bus_may_powerdown(bus);
3423 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3424 return err;
3425}
3426
3427static int b43_add_interface(struct ieee80211_hw *hw,
3428 struct ieee80211_if_init_conf *conf)
3429{
3430 struct b43_wl *wl = hw_to_b43_wl(hw);
3431 struct b43_wldev *dev;
3432 unsigned long flags;
3433 int err = -EOPNOTSUPP;
4150c572
JB		 3434
3435 /* TODO: allow WDS/AP devices to coexist */
3436
3437 if (conf->type != IEEE80211_IF_TYPE_AP &&
3438 conf->type != IEEE80211_IF_TYPE_STA &&
3439 conf->type != IEEE80211_IF_TYPE_WDS &&
3440 conf->type != IEEE80211_IF_TYPE_IBSS)
3441 return -EOPNOTSUPP;
e4d6b795
MB		 3442
3443 mutex_lock(&wl->mutex);
4150c572 3444 if (wl->operating)
e4d6b795
MB		 3445 goto out_mutex_unlock;
3446
3447 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3448
3449 dev = wl->current_dev;
4150c572
JB		 3450 wl->operating = 1;
3451 wl->if_id = conf->if_id;
3452 wl->if_type = conf->type;
3453 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3454
3455 spin_lock_irqsave(&wl->irq_lock, flags);
3456 b43_adjust_opmode(dev);
3457 b43_upload_card_macaddress(dev);
3458 spin_unlock_irqrestore(&wl->irq_lock, flags);
3459
3460 err = 0;
3461 out_mutex_unlock:
3462 mutex_unlock(&wl->mutex);
3463
3464 return err;
3465}
3466
3467static void b43_remove_interface(struct ieee80211_hw *hw,
3468 struct ieee80211_if_init_conf *conf)
3469{
3470 struct b43_wl *wl = hw_to_b43_wl(hw);
3471 struct b43_wldev *dev = wl->current_dev;
3472 unsigned long flags;
3473
3474 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3475
3476 mutex_lock(&wl->mutex);
3477
3478 B43_WARN_ON(!wl->operating);
3479 B43_WARN_ON(wl->if_id != conf->if_id);
3480
3481 wl->operating = 0;
3482
3483 spin_lock_irqsave(&wl->irq_lock, flags);
3484 b43_adjust_opmode(dev);
3485 memset(wl->mac_addr, 0, ETH_ALEN);
3486 b43_upload_card_macaddress(dev);
3487 spin_unlock_irqrestore(&wl->irq_lock, flags);
3488
3489 mutex_unlock(&wl->mutex);
3490}
3491
3492static int b43_start(struct ieee80211_hw *hw)
3493{
3494 struct b43_wl *wl = hw_to_b43_wl(hw);
3495 struct b43_wldev *dev = wl->current_dev;
3496 int did_init = 0;
923403b8 3497 int err = 0;
4150c572
JB		 3498
3499 mutex_lock(&wl->mutex);
3500
e4d6b795
MB		 3501 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3502 err = b43_wireless_core_init(dev);
3503 if (err)
3504 goto out_mutex_unlock;
3505 did_init = 1;
3506 }
4150c572 3507
e4d6b795
MB		 3508 if (b43_status(dev) < B43_STAT_STARTED) {
3509 err = b43_wireless_core_start(dev);
3510 if (err) {
3511 if (did_init)
3512 b43_wireless_core_exit(dev);
3513 goto out_mutex_unlock;
3514 }
3515 }
3516
4150c572 3517 out_mutex_unlock:
e4d6b795
MB		 3518 mutex_unlock(&wl->mutex);
3519
3520 return err;
3521}
3522
023384fa 3523static void b43_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 3524{
3525 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 3526 struct b43_wldev *dev = wl->current_dev;
e4d6b795
MB		 3527
3528 mutex_lock(&wl->mutex);
4150c572
JB		 3529 if (b43_status(dev) >= B43_STAT_STARTED)
3530 b43_wireless_core_stop(dev);
3531 b43_wireless_core_exit(dev);
e4d6b795
MB		 3532 mutex_unlock(&wl->mutex);
3533}
3534
3535static const struct ieee80211_ops b43_hw_ops = {
3536 .tx = b43_tx,
3537 .conf_tx = b43_conf_tx,
3538 .add_interface = b43_add_interface,
3539 .remove_interface = b43_remove_interface,
3540 .config = b43_dev_config,
3541 .config_interface = b43_config_interface,
4150c572 3542 .configure_filter = b43_configure_filter,
e4d6b795
MB		 3543 .set_key = b43_dev_set_key,
3544 .get_stats = b43_get_stats,
3545 .get_tx_stats = b43_get_tx_stats,
4150c572
JB		 3546 .start = b43_start,
3547 .stop = b43_stop,
e4d6b795
MB		 3548};
3549
3550/* Hard-reset the chip. Do not call this directly.
3551 * Use b43_controller_restart()
3552 */
3553static void b43_chip_reset(struct work_struct *work)
3554{
3555 struct b43_wldev *dev =
3556 container_of(work, struct b43_wldev, restart_work);
3557 struct b43_wl *wl = dev->wl;
3558 int err = 0;
3559 int prev_status;
3560
3561 mutex_lock(&wl->mutex);
3562
3563 prev_status = b43_status(dev);
3564 /* Bring the device down... */
3565 if (prev_status >= B43_STAT_STARTED)
3566 b43_wireless_core_stop(dev);
3567 if (prev_status >= B43_STAT_INITIALIZED)
3568 b43_wireless_core_exit(dev);
3569
3570 /* ...and up again. */
3571 if (prev_status >= B43_STAT_INITIALIZED) {
3572 err = b43_wireless_core_init(dev);
3573 if (err)
3574 goto out;
3575 }
3576 if (prev_status >= B43_STAT_STARTED) {
3577 err = b43_wireless_core_start(dev);
3578 if (err) {
3579 b43_wireless_core_exit(dev);
3580 goto out;
3581 }
3582 }
3583 out:
3584 mutex_unlock(&wl->mutex);
3585 if (err)
3586 b43err(wl, "Controller restart FAILED\n");
3587 else
3588 b43info(wl, "Controller restarted\n");
3589}
3590
3591static int b43_setup_modes(struct b43_wldev *dev,
3592 int have_aphy, int have_bphy, int have_gphy)
3593{
3594 struct ieee80211_hw *hw = dev->wl->hw;
3595 struct ieee80211_hw_mode *mode;
3596 struct b43_phy *phy = &dev->phy;
3597 int cnt = 0;
3598 int err;
3599
3600/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3601 have_aphy = 0;
3602
3603 phy->possible_phymodes = 0;
3604 for (; 1; cnt++) {
3605 if (have_aphy) {
3606 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3607 mode = &phy->hwmodes[cnt];
3608
3609 mode->mode = MODE_IEEE80211A;
3610 mode->num_channels = b43_a_chantable_size;
3611 mode->channels = b43_a_chantable;
3612 mode->num_rates = b43_a_ratetable_size;
3613 mode->rates = b43_a_ratetable;
3614 err = ieee80211_register_hwmode(hw, mode);
3615 if (err)
3616 return err;
3617
3618 phy->possible_phymodes |= B43_PHYMODE_A;
3619 have_aphy = 0;
3620 continue;
3621 }
3622 if (have_bphy) {
3623 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3624 mode = &phy->hwmodes[cnt];
3625
3626 mode->mode = MODE_IEEE80211B;
3627 mode->num_channels = b43_bg_chantable_size;
3628 mode->channels = b43_bg_chantable;
3629 mode->num_rates = b43_b_ratetable_size;
3630 mode->rates = b43_b_ratetable;
3631 err = ieee80211_register_hwmode(hw, mode);
3632 if (err)
3633 return err;
3634
3635 phy->possible_phymodes |= B43_PHYMODE_B;
3636 have_bphy = 0;
3637 continue;
3638 }
3639 if (have_gphy) {
3640 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3641 mode = &phy->hwmodes[cnt];
3642
3643 mode->mode = MODE_IEEE80211G;
3644 mode->num_channels = b43_bg_chantable_size;
3645 mode->channels = b43_bg_chantable;
3646 mode->num_rates = b43_g_ratetable_size;
3647 mode->rates = b43_g_ratetable;
3648 err = ieee80211_register_hwmode(hw, mode);
3649 if (err)
3650 return err;
3651
3652 phy->possible_phymodes |= B43_PHYMODE_G;
3653 have_gphy = 0;
3654 continue;
3655 }
3656 break;
3657 }
3658
3659 return 0;
3660}
3661
3662static void b43_wireless_core_detach(struct b43_wldev *dev)
3663{
3664 /* We release firmware that late to not be required to re-request
3665 * is all the time when we reinit the core. */
3666 b43_release_firmware(dev);
3667}
3668
3669static int b43_wireless_core_attach(struct b43_wldev *dev)
3670{
3671 struct b43_wl *wl = dev->wl;
3672 struct ssb_bus *bus = dev->dev->bus;
3673 struct pci_dev *pdev = bus->host_pci;
3674 int err;
3675 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3676 u32 tmp;
3677
3678 /* Do NOT do any device initialization here.
3679 * Do it in wireless_core_init() instead.
3680 * This function is for gathering basic information about the HW, only.
3681 * Also some structs may be set up here. But most likely you want to have
3682 * that in core_init(), too.
3683 */
3684
3685 err = ssb_bus_powerup(bus, 0);
3686 if (err) {
3687 b43err(wl, "Bus powerup failed\n");
3688 goto out;
3689 }
3690 /* Get the PHY type. */
3691 if (dev->dev->id.revision >= 5) {
3692 u32 tmshigh;
3693
3694 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3695 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3696 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3697 if (!have_aphy && !have_gphy)
3698 have_bphy = 1;
3699 } else if (dev->dev->id.revision == 4) {
3700 have_gphy = 1;
3701 have_aphy = 1;
3702 } else
3703 have_bphy = 1;
3704
e4d6b795
MB		 3705 dev->phy.gmode = (have_gphy || have_bphy);
3706 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3707 b43_wireless_core_reset(dev, tmp);
3708
3709 err = b43_phy_versioning(dev);
3710 if (err)
21954c36 3711 goto err_powerdown;
e4d6b795
MB		 3712 /* Check if this device supports multiband. */
3713 if (!pdev ||
3714 (pdev->device != 0x4312 &&
3715 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3716 /* No multiband support. */
3717 have_aphy = 0;
3718 have_bphy = 0;
3719 have_gphy = 0;
3720 switch (dev->phy.type) {
3721 case B43_PHYTYPE_A:
3722 have_aphy = 1;
3723 break;
3724 case B43_PHYTYPE_B:
3725 have_bphy = 1;
3726 break;
3727 case B43_PHYTYPE_G:
3728 have_gphy = 1;
3729 break;
3730 default:
3731 B43_WARN_ON(1);
3732 }
3733 }
3734 dev->phy.gmode = (have_gphy || have_bphy);
3735 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3736 b43_wireless_core_reset(dev, tmp);
3737
3738 err = b43_validate_chipaccess(dev);
3739 if (err)
21954c36 3740 goto err_powerdown;
e4d6b795
MB		 3741 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3742 if (err)
21954c36 3743 goto err_powerdown;
e4d6b795
MB		 3744
3745 /* Now set some default "current_dev" */
3746 if (!wl->current_dev)
3747 wl->current_dev = dev;
3748 INIT_WORK(&dev->restart_work, b43_chip_reset);
3749
8e9f7529 3750 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3751 b43_switch_analog(dev, 0);
3752 ssb_device_disable(dev->dev, 0);
3753 ssb_bus_may_powerdown(bus);
3754
3755out:
3756 return err;
3757
e4d6b795
MB		 3758err_powerdown:
3759 ssb_bus_may_powerdown(bus);
3760 return err;
3761}
3762
3763static void b43_one_core_detach(struct ssb_device *dev)
3764{
3765 struct b43_wldev *wldev;
3766 struct b43_wl *wl;
3767
3768 wldev = ssb_get_drvdata(dev);
3769 wl = wldev->wl;
3770 cancel_work_sync(&wldev->restart_work);
3771 b43_debugfs_remove_device(wldev);
3772 b43_wireless_core_detach(wldev);
3773 list_del(&wldev->list);
3774 wl->nr_devs--;
3775 ssb_set_drvdata(dev, NULL);
3776 kfree(wldev);
3777}
3778
3779static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3780{
3781 struct b43_wldev *wldev;
3782 struct pci_dev *pdev;
3783 int err = -ENOMEM;
3784
3785 if (!list_empty(&wl->devlist)) {
3786 /* We are not the first core on this chip. */
3787 pdev = dev->bus->host_pci;
3788 /* Only special chips support more than one wireless
3789 * core, although some of the other chips have more than
3790 * one wireless core as well. Check for this and
3791 * bail out early.
3792 */
3793 if (!pdev ||
3794 ((pdev->device != 0x4321) &&
3795 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3796 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3797 return -ENODEV;
3798 }
3799 }
3800
3801 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3802 if (!wldev)
3803 goto out;
3804
3805 wldev->dev = dev;
3806 wldev->wl = wl;
3807 b43_set_status(wldev, B43_STAT_UNINIT);
3808 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3809 tasklet_init(&wldev->isr_tasklet,
3810 (void (*)(unsigned long))b43_interrupt_tasklet,
3811 (unsigned long)wldev);
3812 if (modparam_pio)
3813 wldev->__using_pio = 1;
3814 INIT_LIST_HEAD(&wldev->list);
3815
3816 err = b43_wireless_core_attach(wldev);
3817 if (err)
3818 goto err_kfree_wldev;
3819
3820 list_add(&wldev->list, &wl->devlist);
3821 wl->nr_devs++;
3822 ssb_set_drvdata(dev, wldev);
3823 b43_debugfs_add_device(wldev);
3824
3825 out:
3826 return err;
3827
3828 err_kfree_wldev:
3829 kfree(wldev);
3830 return err;
3831}
3832
3833static void b43_sprom_fixup(struct ssb_bus *bus)
3834{
3835 /* boardflags workarounds */
3836 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3837 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3838 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3839 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3840 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3841 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3842
3843 /* Handle case when gain is not set in sprom */
3844 if (bus->sprom.r1.antenna_gain_a == 0xFF)
3845 bus->sprom.r1.antenna_gain_a = 2;
3846 if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3847 bus->sprom.r1.antenna_gain_bg = 2;
3848
3849 /* Convert Antennagain values to Q5.2 */
3850 bus->sprom.r1.antenna_gain_a <<= 2;
3851 bus->sprom.r1.antenna_gain_bg <<= 2;
3852}
3853
3854static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3855{
3856 struct ieee80211_hw *hw = wl->hw;
3857
3858 ssb_set_devtypedata(dev, NULL);
3859 ieee80211_free_hw(hw);
3860}
3861
3862static int b43_wireless_init(struct ssb_device *dev)
3863{
3864 struct ssb_sprom *sprom = &dev->bus->sprom;
3865 struct ieee80211_hw *hw;
3866 struct b43_wl *wl;
3867 int err = -ENOMEM;
3868
3869 b43_sprom_fixup(dev->bus);
3870
3871 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3872 if (!hw) {
3873 b43err(NULL, "Could not allocate ieee80211 device\n");
3874 goto out;
3875 }
3876
3877 /* fill hw info */
4150c572 3878 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
e4d6b795
MB		 3879 hw->max_signal = 100;
3880 hw->max_rssi = -110;
3881 hw->max_noise = -110;
3882 hw->queues = 1; /* FIXME: hardware has more queues */
3883 SET_IEEE80211_DEV(hw, dev->dev);
3884 if (is_valid_ether_addr(sprom->r1.et1mac))
3885 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3886 else
3887 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3888
3889 /* Get and initialize struct b43_wl */
3890 wl = hw_to_b43_wl(hw);
3891 memset(wl, 0, sizeof(*wl));
3892 wl->hw = hw;
3893 spin_lock_init(&wl->irq_lock);
3894 spin_lock_init(&wl->leds_lock);
3895 mutex_init(&wl->mutex);
3896 INIT_LIST_HEAD(&wl->devlist);
3897
3898 ssb_set_devtypedata(dev, wl);
3899 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3900 err = 0;
3901 out:
3902 return err;
3903}
3904
3905static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3906{
3907 struct b43_wl *wl;
3908 int err;
3909 int first = 0;
3910
3911 wl = ssb_get_devtypedata(dev);
3912 if (!wl) {
3913 /* Probing the first core. Must setup common struct b43_wl */
3914 first = 1;
3915 err = b43_wireless_init(dev);
3916 if (err)
3917 goto out;
3918 wl = ssb_get_devtypedata(dev);
3919 B43_WARN_ON(!wl);
3920 }
3921 err = b43_one_core_attach(dev, wl);
3922 if (err)
3923 goto err_wireless_exit;
3924
3925 if (first) {
3926 err = ieee80211_register_hw(wl->hw);
3927 if (err)
3928 goto err_one_core_detach;
3929 }
3930
3931 out:
3932 return err;
3933
3934 err_one_core_detach:
3935 b43_one_core_detach(dev);
3936 err_wireless_exit:
3937 if (first)
3938 b43_wireless_exit(dev, wl);
3939 return err;
3940}
3941
3942static void b43_remove(struct ssb_device *dev)
3943{
3944 struct b43_wl *wl = ssb_get_devtypedata(dev);
3945 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3946
3947 B43_WARN_ON(!wl);
3948 if (wl->current_dev == wldev)
3949 ieee80211_unregister_hw(wl->hw);
3950
3951 b43_one_core_detach(dev);
3952
3953 if (list_empty(&wl->devlist)) {
3954 /* Last core on the chip unregistered.
3955 * We can destroy common struct b43_wl.
3956 */
3957 b43_wireless_exit(dev, wl);
3958 }
3959}
3960
3961/* Perform a hardware reset. This can be called from any context. */
3962void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3963{
3964 /* Must avoid requeueing, if we are in shutdown. */
3965 if (b43_status(dev) < B43_STAT_INITIALIZED)
3966 return;
3967 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3968 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3969}
3970
3971#ifdef CONFIG_PM
3972
3973static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3974{
3975 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3976 struct b43_wl *wl = wldev->wl;
3977
3978 b43dbg(wl, "Suspending...\n");
3979
3980 mutex_lock(&wl->mutex);
3981 wldev->suspend_init_status = b43_status(wldev);
3982 if (wldev->suspend_init_status >= B43_STAT_STARTED)
3983 b43_wireless_core_stop(wldev);
3984 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3985 b43_wireless_core_exit(wldev);
3986 mutex_unlock(&wl->mutex);
3987
3988 b43dbg(wl, "Device suspended.\n");
3989
3990 return 0;
3991}
3992
3993static int b43_resume(struct ssb_device *dev)
3994{
3995 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3996 struct b43_wl *wl = wldev->wl;
3997 int err = 0;
3998
3999 b43dbg(wl, "Resuming...\n");
4000
4001 mutex_lock(&wl->mutex);
4002 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4003 err = b43_wireless_core_init(wldev);
4004 if (err) {
4005 b43err(wl, "Resume failed at core init\n");
4006 goto out;
4007 }
4008 }
4009 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4010 err = b43_wireless_core_start(wldev);
4011 if (err) {
4012 b43_wireless_core_exit(wldev);
4013 b43err(wl, "Resume failed at core start\n");
4014 goto out;
4015 }
4016 }
4017 mutex_unlock(&wl->mutex);
4018
4019 b43dbg(wl, "Device resumed.\n");
4020 out:
4021 return err;
4022}
4023
4024#else /* CONFIG_PM */
4025# define b43_suspend NULL
4026# define b43_resume NULL
4027#endif /* CONFIG_PM */
4028
4029static struct ssb_driver b43_ssb_driver = {
4030 .name = KBUILD_MODNAME,
4031 .id_table = b43_ssb_tbl,
4032 .probe = b43_probe,
4033 .remove = b43_remove,
4034 .suspend = b43_suspend,
4035 .resume = b43_resume,
4036};
4037
4038static int __init b43_init(void)
4039{
4040 int err;
4041
4042 b43_debugfs_init();
4043 err = b43_pcmcia_init();
4044 if (err)
4045 goto err_dfs_exit;
4046 err = ssb_driver_register(&b43_ssb_driver);
4047 if (err)
4048 goto err_pcmcia_exit;
4049
4050 return err;
4051
4052err_pcmcia_exit:
4053 b43_pcmcia_exit();
4054err_dfs_exit:
4055 b43_debugfs_exit();
4056 return err;
4057}
4058
4059static void __exit b43_exit(void)
4060{
4061 ssb_driver_unregister(&b43_ssb_driver);
4062 b43_pcmcia_exit();
4063 b43_debugfs_exit();
4064}
4065
4066module_init(b43_init)
4067module_exit(b43_exit)
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