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iwl3945: fix station stuff in RC algorithm
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
e6f5b934 91
e4d6b795
MB		 92static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 100 SSB_DEVTABLE_END
101};
102
103MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105/* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
e4d6b795 114 }
8318d78a
JB		 115
116/*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
e4d6b795 120static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 133};
134
135#define b43_a_ratetable (__b43_ratetable + 4)
136#define b43_a_ratetable_size 8
137#define b43_b_ratetable (__b43_ratetable + 0)
138#define b43_b_ratetable_size 4
139#define b43_g_ratetable (__b43_ratetable + 0)
140#define b43_g_ratetable_size 12
141
bb1eeff1
MB		 142#define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149}
96c755a3 150static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165};
166#undef CHAN4G
167
168#define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175}
176static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 232};
233
bb1eeff1
MB		 234static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254};
255#undef CHAN5G
256
257static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
e4d6b795 263};
8318d78a 264
bb1eeff1
MB		 265static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
8318d78a 271};
e4d6b795 272
8318d78a 273static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 279};
280
e4d6b795
MB		 281static void b43_wireless_core_exit(struct b43_wldev *dev);
282static int b43_wireless_core_init(struct b43_wldev *dev);
283static void b43_wireless_core_stop(struct b43_wldev *dev);
284static int b43_wireless_core_start(struct b43_wldev *dev);
285
286static int b43_ratelimit(struct b43_wl *wl)
287{
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295}
296
297void b43info(struct b43_wl *wl, const char *fmt, ...)
298{
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308}
309
310void b43err(struct b43_wl *wl, const char *fmt, ...)
311{
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43warn(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334}
335
336#if B43_DEBUG
337void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338{
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347#endif /* DEBUG */
348
349static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350{
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362}
363
280d0e16
MB		 364static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
e4d6b795
MB		 366{
367 u32 control;
368
369 /* "offset" is the WORD offset. */
e4d6b795
MB		 370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374}
375
6bbc321a 376u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 377{
378 u32 ret;
379
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 ret <<= 16;
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
389
280d0e16 390 goto out;
e4d6b795
MB		 391 }
392 offset >>= 2;
393 }
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 396out:
e4d6b795
MB		 397 return ret;
398}
399
6bbc321a 400u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 401{
280d0e16
MB		 402 struct b43_wl *wl = dev->wl;
403 unsigned long flags;
6bbc321a 404 u32 ret;
e4d6b795 405
280d0e16 406 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
409
410 return ret;
411}
412
413u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
414{
415 u16 ret;
416
e4d6b795
MB		 417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423
280d0e16 424 goto out;
e4d6b795
MB		 425 }
426 offset >>= 2;
427 }
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 430out:
e4d6b795
MB		 431 return ret;
432}
433
6bbc321a 434u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 435{
280d0e16
MB		 436 struct b43_wl *wl = dev->wl;
437 unsigned long flags;
6bbc321a 438 u16 ret;
280d0e16
MB		 439
440 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
443
444 return ret;
445}
446
447void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
448{
e4d6b795
MB		 449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
e4d6b795 456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 458 return;
e4d6b795
MB		 459 }
460 offset >>= 2;
461 }
462 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
464}
465
6bbc321a 466void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 467{
280d0e16
MB		 468 struct b43_wl *wl = dev->wl;
469 unsigned long flags;
470
471 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
474}
475
476void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
477{
e4d6b795
MB		 478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 484 return;
e4d6b795
MB		 485 }
486 offset >>= 2;
487 }
488 b43_shm_control_word(dev, routing, offset);
e4d6b795 489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 490}
491
492void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493{
494 struct b43_wl *wl = dev->wl;
495 unsigned long flags;
496
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
280d0e16 499 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 500}
501
502/* Read HostFlags */
35f0d354 503u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 504{
35f0d354 505 u64 ret;
e4d6b795
MB		 506
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
508 ret <<= 16;
35f0d354
MB		 509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
510 ret <<= 16;
e4d6b795
MB		 511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
512
513 return ret;
514}
515
516/* Write HostFlags */
35f0d354 517void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 518{
35f0d354
MB		 519 u16 lo, mi, hi;
520
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 527}
528
529void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
530{
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
536 */
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
539
540 do {
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
545
546 *tsf = high;
547 *tsf <<= 32;
548 *tsf |= low;
549 } else {
550 u64 tmp;
551 u16 v0, v1, v2, v3;
552 u16 test1, test2, test3;
553
554 do {
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
559
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
564
565 *tsf = v3;
566 *tsf <<= 48;
567 tmp = v2;
568 tmp <<= 32;
569 *tsf |= tmp;
570 tmp = v1;
571 tmp <<= 16;
572 *tsf |= tmp;
573 *tsf |= v0;
574 }
575}
576
577static void b43_time_lock(struct b43_wldev *dev)
578{
579 u32 macctl;
580
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586}
587
588static void b43_time_unlock(struct b43_wldev *dev)
589{
590 u32 macctl;
591
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
597}
598
599static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
600{
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
604 */
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
608
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
610 mmiowb();
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
614 } else {
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
619
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
621 mmiowb();
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
623 mmiowb();
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
625 mmiowb();
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
627 mmiowb();
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
629 }
630}
631
632void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
633{
634 b43_time_lock(dev);
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
637}
638
639static
640void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
641{
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
643 u16 data;
644
645 if (!mac)
646 mac = zero_addr;
647
648 offset |= 0x0020;
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
650
651 data = mac[0];
652 data |= mac[1] << 8;
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
654 data = mac[2];
655 data |= mac[3] << 8;
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
657 data = mac[4];
658 data |= mac[5] << 8;
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
660}
661
662static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
663{
664 const u8 *mac;
665 const u8 *bssid;
666 u8 mac_bssid[ETH_ALEN * 2];
667 int i;
668 u32 tmp;
669
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
672
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
674
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
677
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
685 }
686}
687
4150c572 688static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 689{
e4d6b795 690 b43_write_mac_bssid_templates(dev);
4150c572 691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 692}
693
694static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
695{
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
698 return;
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
701}
702
703static void b43_short_slot_timing_enable(struct b43_wldev *dev)
704{
705 b43_set_slot_time(dev, 9);
706 dev->short_slot = 1;
707}
708
709static void b43_short_slot_timing_disable(struct b43_wldev *dev)
710{
711 b43_set_slot_time(dev, 20);
712 dev->short_slot = 0;
713}
714
715/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
716 * Returns the _previously_ enabled IRQ mask.
717 */
718static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
719{
720 u32 old_mask;
721
722 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
723 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
724
725 return old_mask;
726}
727
728/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
729 * Returns the _previously_ enabled IRQ mask.
730 */
731static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
732{
733 u32 old_mask;
734
735 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
736 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
737
738 return old_mask;
739}
740
741/* Synchronize IRQ top- and bottom-half.
742 * IRQs must be masked before calling this.
743 * This must not be called with the irq_lock held.
744 */
745static void b43_synchronize_irq(struct b43_wldev *dev)
746{
747 synchronize_irq(dev->dev->irq);
748 tasklet_kill(&dev->isr_tasklet);
749}
750
751/* DummyTransmission function, as documented on
752 * http://bcm-specs.sipsolutions.net/DummyTransmission
753 */
754void b43_dummy_transmission(struct b43_wldev *dev)
755{
21a75d77 756 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 757 struct b43_phy *phy = &dev->phy;
758 unsigned int i, max_loop;
759 u16 value;
760 u32 buffer[5] = {
761 0x00000000,
762 0x00D40000,
763 0x00000000,
764 0x01000000,
765 0x00000000,
766 };
767
768 switch (phy->type) {
769 case B43_PHYTYPE_A:
770 max_loop = 0x1E;
771 buffer[0] = 0x000201CC;
772 break;
773 case B43_PHYTYPE_B:
774 case B43_PHYTYPE_G:
775 max_loop = 0xFA;
776 buffer[0] = 0x000B846E;
777 break;
778 default:
779 B43_WARN_ON(1);
780 return;
781 }
782
21a75d77
MB		 783 spin_lock_irq(&wl->irq_lock);
784 write_lock(&wl->tx_lock);
785
e4d6b795
MB		 786 for (i = 0; i < 5; i++)
787 b43_ram_write(dev, i * 4, buffer[i]);
788
789 /* Commit writes */
790 b43_read32(dev, B43_MMIO_MACCTL);
791
792 b43_write16(dev, 0x0568, 0x0000);
793 b43_write16(dev, 0x07C0, 0x0000);
794 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
795 b43_write16(dev, 0x050C, value);
796 b43_write16(dev, 0x0508, 0x0000);
797 b43_write16(dev, 0x050A, 0x0000);
798 b43_write16(dev, 0x054C, 0x0000);
799 b43_write16(dev, 0x056A, 0x0014);
800 b43_write16(dev, 0x0568, 0x0826);
801 b43_write16(dev, 0x0500, 0x0000);
802 b43_write16(dev, 0x0502, 0x0030);
803
804 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
805 b43_radio_write16(dev, 0x0051, 0x0017);
806 for (i = 0x00; i < max_loop; i++) {
807 value = b43_read16(dev, 0x050E);
808 if (value & 0x0080)
809 break;
810 udelay(10);
811 }
812 for (i = 0x00; i < 0x0A; i++) {
813 value = b43_read16(dev, 0x050E);
814 if (value & 0x0400)
815 break;
816 udelay(10);
817 }
1d280ddc 818 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 819 value = b43_read16(dev, 0x0690);
820 if (!(value & 0x0100))
821 break;
822 udelay(10);
823 }
824 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
825 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 826
827 write_unlock(&wl->tx_lock);
828 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 829}
830
831static void key_write(struct b43_wldev *dev,
832 u8 index, u8 algorithm, const u8 * key)
833{
834 unsigned int i;
835 u32 offset;
836 u16 value;
837 u16 kidx;
838
839 /* Key index/algo block */
840 kidx = b43_kidx_to_fw(dev, index);
841 value = ((kidx << 4) | algorithm);
842 b43_shm_write16(dev, B43_SHM_SHARED,
843 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
844
845 /* Write the key to the Key Table Pointer offset */
846 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
847 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
848 value = key[i];
849 value |= (u16) (key[i + 1]) << 8;
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
851 }
852}
853
854static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
855{
856 u32 addrtmp[2] = { 0, 0, };
857 u8 per_sta_keys_start = 8;
858
859 if (b43_new_kidx_api(dev))
860 per_sta_keys_start = 4;
861
862 B43_WARN_ON(index < per_sta_keys_start);
863 /* We have two default TX keys and possibly two default RX keys.
864 * Physical mac 0 is mapped to physical key 4 or 8, depending
865 * on the firmware version.
866 * So we must adjust the index here.
867 */
868 index -= per_sta_keys_start;
869
870 if (addr) {
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 }
878
879 if (dev->dev->id.revision >= 5) {
880 /* Receive match transmitter address mechanism */
881 b43_shm_write32(dev, B43_SHM_RCMTA,
882 (index * 2) + 0, addrtmp[0]);
883 b43_shm_write16(dev, B43_SHM_RCMTA,
884 (index * 2) + 1, addrtmp[1]);
885 } else {
886 /* RXE (Receive Engine) and
887 * PSM (Programmable State Machine) mechanism
888 */
889 if (index < 8) {
890 /* TODO write to RCM 16, 19, 22 and 25 */
891 } else {
892 b43_shm_write32(dev, B43_SHM_SHARED,
893 B43_SHM_SH_PSM + (index * 6) + 0,
894 addrtmp[0]);
895 b43_shm_write16(dev, B43_SHM_SHARED,
896 B43_SHM_SH_PSM + (index * 6) + 4,
897 addrtmp[1]);
898 }
899 }
900}
901
902static void do_key_write(struct b43_wldev *dev,
903 u8 index, u8 algorithm,
904 const u8 * key, size_t key_len, const u8 * mac_addr)
905{
906 u8 buf[B43_SEC_KEYSIZE] = { 0, };
907 u8 per_sta_keys_start = 8;
908
909 if (b43_new_kidx_api(dev))
910 per_sta_keys_start = 4;
911
912 B43_WARN_ON(index >= dev->max_nr_keys);
913 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
914
915 if (index >= per_sta_keys_start)
916 keymac_write(dev, index, NULL); /* First zero out mac. */
917 if (key)
918 memcpy(buf, key, key_len);
919 key_write(dev, index, algorithm, buf);
920 if (index >= per_sta_keys_start)
921 keymac_write(dev, index, mac_addr);
922
923 dev->key[index].algorithm = algorithm;
924}
925
926static int b43_key_write(struct b43_wldev *dev,
927 int index, u8 algorithm,
928 const u8 * key, size_t key_len,
929 const u8 * mac_addr,
930 struct ieee80211_key_conf *keyconf)
931{
932 int i;
933 int sta_keys_start;
934
935 if (key_len > B43_SEC_KEYSIZE)
936 return -EINVAL;
937 for (i = 0; i < dev->max_nr_keys; i++) {
938 /* Check that we don't already have this key. */
939 B43_WARN_ON(dev->key[i].keyconf == keyconf);
940 }
941 if (index < 0) {
942 /* Either pairwise key or address is 00:00:00:00:00:00
943 * for transmit-only keys. Search the index. */
944 if (b43_new_kidx_api(dev))
945 sta_keys_start = 4;
946 else
947 sta_keys_start = 8;
948 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
949 if (!dev->key[i].keyconf) {
950 /* found empty */
951 index = i;
952 break;
953 }
954 }
955 if (index < 0) {
956 b43err(dev->wl, "Out of hardware key memory\n");
957 return -ENOSPC;
958 }
959 } else
960 B43_WARN_ON(index > 3);
961
962 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
963 if ((index <= 3) && !b43_new_kidx_api(dev)) {
964 /* Default RX key */
965 B43_WARN_ON(mac_addr);
966 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
967 }
968 keyconf->hw_key_idx = index;
969 dev->key[index].keyconf = keyconf;
970
971 return 0;
972}
973
974static int b43_key_clear(struct b43_wldev *dev, int index)
975{
976 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
977 return -EINVAL;
978 do_key_write(dev, index, B43_SEC_ALGO_NONE,
979 NULL, B43_SEC_KEYSIZE, NULL);
980 if ((index <= 3) && !b43_new_kidx_api(dev)) {
981 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
982 NULL, B43_SEC_KEYSIZE, NULL);
983 }
984 dev->key[index].keyconf = NULL;
985
986 return 0;
987}
988
989static void b43_clear_keys(struct b43_wldev *dev)
990{
991 int i;
992
993 for (i = 0; i < dev->max_nr_keys; i++)
994 b43_key_clear(dev, i);
995}
996
997void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
998{
999 u32 macctl;
1000 u16 ucstat;
1001 bool hwps;
1002 bool awake;
1003 int i;
1004
1005 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1006 (ps_flags & B43_PS_DISABLED));
1007 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1008
1009 if (ps_flags & B43_PS_ENABLED) {
1010 hwps = 1;
1011 } else if (ps_flags & B43_PS_DISABLED) {
1012 hwps = 0;
1013 } else {
1014 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1015 // and thus is not an AP and we are associated, set bit 25
1016 }
1017 if (ps_flags & B43_PS_AWAKE) {
1018 awake = 1;
1019 } else if (ps_flags & B43_PS_ASLEEP) {
1020 awake = 0;
1021 } else {
1022 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1023 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1024 // successful, set bit26
1025 }
1026
1027/* FIXME: For now we force awake-on and hwps-off */
1028 hwps = 0;
1029 awake = 1;
1030
1031 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1032 if (hwps)
1033 macctl |= B43_MACCTL_HWPS;
1034 else
1035 macctl &= ~B43_MACCTL_HWPS;
1036 if (awake)
1037 macctl |= B43_MACCTL_AWAKE;
1038 else
1039 macctl &= ~B43_MACCTL_AWAKE;
1040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1041 /* Commit write */
1042 b43_read32(dev, B43_MMIO_MACCTL);
1043 if (awake && dev->dev->id.revision >= 5) {
1044 /* Wait for the microcode to wake up. */
1045 for (i = 0; i < 100; i++) {
1046 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1047 B43_SHM_SH_UCODESTAT);
1048 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1049 break;
1050 udelay(10);
1051 }
1052 }
1053}
1054
e4d6b795
MB		 1055void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1056{
1057 u32 tmslow;
1058 u32 macctl;
1059
1060 flags |= B43_TMSLOW_PHYCLKEN;
1061 flags |= B43_TMSLOW_PHYRESET;
1062 ssb_device_enable(dev->dev, flags);
1063 msleep(2); /* Wait for the PLL to turn on. */
1064
1065 /* Now take the PHY out of Reset again */
1066 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1067 tmslow |= SSB_TMSLOW_FGC;
1068 tmslow &= ~B43_TMSLOW_PHYRESET;
1069 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1070 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1071 msleep(1);
1072 tmslow &= ~SSB_TMSLOW_FGC;
1073 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1074 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1075 msleep(1);
1076
fb11137a
MB		 1077 /* Turn Analog ON, but only if we already know the PHY-type.
1078 * This protects against very early setup where we don't know the
1079 * PHY-type, yet. wireless_core_reset will be called once again later,
1080 * when we know the PHY-type. */
1081 if (dev->phy.ops)
cb24f57f 1082 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1083
1084 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1085 macctl &= ~B43_MACCTL_GMODE;
1086 if (flags & B43_TMSLOW_GMODE)
1087 macctl |= B43_MACCTL_GMODE;
1088 macctl |= B43_MACCTL_IHR_ENABLED;
1089 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1090}
1091
1092static void handle_irq_transmit_status(struct b43_wldev *dev)
1093{
1094 u32 v0, v1;
1095 u16 tmp;
1096 struct b43_txstatus stat;
1097
1098 while (1) {
1099 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1100 if (!(v0 & 0x00000001))
1101 break;
1102 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1103
1104 stat.cookie = (v0 >> 16);
1105 stat.seq = (v1 & 0x0000FFFF);
1106 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1107 tmp = (v0 & 0x0000FFFF);
1108 stat.frame_count = ((tmp & 0xF000) >> 12);
1109 stat.rts_count = ((tmp & 0x0F00) >> 8);
1110 stat.supp_reason = ((tmp & 0x001C) >> 2);
1111 stat.pm_indicated = !!(tmp & 0x0080);
1112 stat.intermediate = !!(tmp & 0x0040);
1113 stat.for_ampdu = !!(tmp & 0x0020);
1114 stat.acked = !!(tmp & 0x0002);
1115
1116 b43_handle_txstatus(dev, &stat);
1117 }
1118}
1119
1120static void drain_txstatus_queue(struct b43_wldev *dev)
1121{
1122 u32 dummy;
1123
1124 if (dev->dev->id.revision < 5)
1125 return;
1126 /* Read all entries from the microcode TXstatus FIFO
1127 * and throw them away.
1128 */
1129 while (1) {
1130 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1131 if (!(dummy & 0x00000001))
1132 break;
1133 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1134 }
1135}
1136
1137static u32 b43_jssi_read(struct b43_wldev *dev)
1138{
1139 u32 val = 0;
1140
1141 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1142 val <<= 16;
1143 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1144
1145 return val;
1146}
1147
1148static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1149{
1150 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1151 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1152}
1153
1154static void b43_generate_noise_sample(struct b43_wldev *dev)
1155{
1156 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1157 b43_write32(dev, B43_MMIO_MACCMD,
1158 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1159}
1160
1161static void b43_calculate_link_quality(struct b43_wldev *dev)
1162{
1163 /* Top half of Link Quality calculation. */
1164
ef1a628d
MB		 1165 if (dev->phy.type != B43_PHYTYPE_G)
1166 return;
e4d6b795
MB		 1167 if (dev->noisecalc.calculation_running)
1168 return;
e4d6b795
MB		 1169 dev->noisecalc.calculation_running = 1;
1170 dev->noisecalc.nr_samples = 0;
1171
1172 b43_generate_noise_sample(dev);
1173}
1174
1175static void handle_irq_noise(struct b43_wldev *dev)
1176{
ef1a628d 1177 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1178 u16 tmp;
1179 u8 noise[4];
1180 u8 i, j;
1181 s32 average;
1182
1183 /* Bottom half of Link Quality calculation. */
1184
ef1a628d
MB		 1185 if (dev->phy.type != B43_PHYTYPE_G)
1186 return;
1187
98a3b2fe
MB		 1188 /* Possible race condition: It might be possible that the user
1189 * changed to a different channel in the meantime since we
1190 * started the calculation. We ignore that fact, since it's
1191 * not really that much of a problem. The background noise is
1192 * an estimation only anyway. Slightly wrong results will get damped
1193 * by the averaging of the 8 sample rounds. Additionally the
1194 * value is shortlived. So it will be replaced by the next noise
1195 * calculation round soon. */
1196
e4d6b795 1197 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1198 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1199 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1200 noise[2] == 0x7F || noise[3] == 0x7F)
1201 goto generate_new;
1202
1203 /* Get the noise samples. */
1204 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1205 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1206 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1207 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1208 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1209 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1210 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1211 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1212 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1213 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1214 dev->noisecalc.nr_samples++;
1215 if (dev->noisecalc.nr_samples == 8) {
1216 /* Calculate the Link Quality by the noise samples. */
1217 average = 0;
1218 for (i = 0; i < 8; i++) {
1219 for (j = 0; j < 4; j++)
1220 average += dev->noisecalc.samples[i][j];
1221 }
1222 average /= (8 * 4);
1223 average *= 125;
1224 average += 64;
1225 average /= 128;
1226 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1227 tmp = (tmp / 128) & 0x1F;
1228 if (tmp >= 8)
1229 average += 2;
1230 else
1231 average -= 25;
1232 if (tmp == 8)
1233 average -= 72;
1234 else
1235 average -= 48;
1236
1237 dev->stats.link_noise = average;
e4d6b795
MB		 1238 dev->noisecalc.calculation_running = 0;
1239 return;
1240 }
98a3b2fe 1241generate_new:
e4d6b795
MB		 1242 b43_generate_noise_sample(dev);
1243}
1244
1245static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1246{
05c914fe 1247 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1248 ///TODO: PS TBTT
1249 } else {
1250 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1251 b43_power_saving_ctl_bits(dev, 0);
1252 }
05c914fe 1253 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1254 dev->dfq_valid = 1;
e4d6b795
MB		 1255}
1256
1257static void handle_irq_atim_end(struct b43_wldev *dev)
1258{
aa6c7ae2
MB		 1259 if (dev->dfq_valid) {
1260 b43_write32(dev, B43_MMIO_MACCMD,
1261 b43_read32(dev, B43_MMIO_MACCMD)
1262 | B43_MACCMD_DFQ_VALID);
1263 dev->dfq_valid = 0;
1264 }
e4d6b795
MB		 1265}
1266
1267static void handle_irq_pmq(struct b43_wldev *dev)
1268{
1269 u32 tmp;
1270
1271 //TODO: AP mode.
1272
1273 while (1) {
1274 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1275 if (!(tmp & 0x00000008))
1276 break;
1277 }
1278 /* 16bit write is odd, but correct. */
1279 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1280}
1281
1282static void b43_write_template_common(struct b43_wldev *dev,
1283 const u8 * data, u16 size,
1284 u16 ram_offset,
1285 u16 shm_size_offset, u8 rate)
1286{
1287 u32 i, tmp;
1288 struct b43_plcp_hdr4 plcp;
1289
1290 plcp.data = 0;
1291 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1292 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1293 ram_offset += sizeof(u32);
1294 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1295 * So leave the first two bytes of the next write blank.
1296 */
1297 tmp = (u32) (data[0]) << 16;
1298 tmp |= (u32) (data[1]) << 24;
1299 b43_ram_write(dev, ram_offset, tmp);
1300 ram_offset += sizeof(u32);
1301 for (i = 2; i < size; i += sizeof(u32)) {
1302 tmp = (u32) (data[i + 0]);
1303 if (i + 1 < size)
1304 tmp |= (u32) (data[i + 1]) << 8;
1305 if (i + 2 < size)
1306 tmp |= (u32) (data[i + 2]) << 16;
1307 if (i + 3 < size)
1308 tmp |= (u32) (data[i + 3]) << 24;
1309 b43_ram_write(dev, ram_offset + i - 2, tmp);
1310 }
1311 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1312 size + sizeof(struct b43_plcp_hdr6));
1313}
1314
5042c507
MB		 1315/* Check if the use of the antenna that ieee80211 told us to
1316 * use is possible. This will fall back to DEFAULT.
1317 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1318u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1319 u8 antenna_nr)
1320{
1321 u8 antenna_mask;
1322
1323 if (antenna_nr == 0) {
1324 /* Zero means "use default antenna". That's always OK. */
1325 return 0;
1326 }
1327
1328 /* Get the mask of available antennas. */
1329 if (dev->phy.gmode)
1330 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1331 else
1332 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1333
1334 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1335 /* This antenna is not available. Fall back to default. */
1336 return 0;
1337 }
1338
1339 return antenna_nr;
1340}
1341
5042c507
MB		 1342/* Convert a b43 antenna number value to the PHY TX control value. */
1343static u16 b43_antenna_to_phyctl(int antenna)
1344{
1345 switch (antenna) {
1346 case B43_ANTENNA0:
1347 return B43_TXH_PHY_ANT0;
1348 case B43_ANTENNA1:
1349 return B43_TXH_PHY_ANT1;
1350 case B43_ANTENNA2:
1351 return B43_TXH_PHY_ANT2;
1352 case B43_ANTENNA3:
1353 return B43_TXH_PHY_ANT3;
1354 case B43_ANTENNA_AUTO:
1355 return B43_TXH_PHY_ANT01AUTO;
1356 }
1357 B43_WARN_ON(1);
1358 return 0;
1359}
1360
e4d6b795
MB		 1361static void b43_write_beacon_template(struct b43_wldev *dev,
1362 u16 ram_offset,
5042c507 1363 u16 shm_size_offset)
e4d6b795 1364{
47f76ca3 1365 unsigned int i, len, variable_len;
e66fee6a
MB		 1366 const struct ieee80211_mgmt *bcn;
1367 const u8 *ie;
1368 bool tim_found = 0;
5042c507
MB		 1369 unsigned int rate;
1370 u16 ctl;
1371 int antenna;
e039fa4a 1372 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1373
e66fee6a
MB		 1374 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1375 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1376 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1377 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1378
1379 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1380 len, ram_offset, shm_size_offset, rate);
e66fee6a 1381
5042c507 1382 /* Write the PHY TX control parameters. */
0f4ac38b 1383 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1384 antenna = b43_antenna_to_phyctl(antenna);
1385 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1386 /* We can't send beacons with short preamble. Would get PHY errors. */
1387 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1388 ctl &= ~B43_TXH_PHY_ANT;
1389 ctl &= ~B43_TXH_PHY_ENC;
1390 ctl |= antenna;
1391 if (b43_is_cck_rate(rate))
1392 ctl |= B43_TXH_PHY_ENC_CCK;
1393 else
1394 ctl |= B43_TXH_PHY_ENC_OFDM;
1395 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1396
e66fee6a
MB		 1397 /* Find the position of the TIM and the DTIM_period value
1398 * and write them to SHM. */
1399 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1400 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1401 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1402 uint8_t ie_id, ie_len;
1403
1404 ie_id = ie[i];
1405 ie_len = ie[i + 1];
1406 if (ie_id == 5) {
1407 u16 tim_position;
1408 u16 dtim_period;
1409 /* This is the TIM Information Element */
1410
1411 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1412 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1413 break;
1414 /* A valid TIM is at least 4 bytes long. */
1415 if (ie_len < 4)
1416 break;
1417 tim_found = 1;
1418
1419 tim_position = sizeof(struct b43_plcp_hdr6);
1420 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1421 tim_position += i;
1422
1423 dtim_period = ie[i + 3];
1424
1425 b43_shm_write16(dev, B43_SHM_SHARED,
1426 B43_SHM_SH_TIMBPOS, tim_position);
1427 b43_shm_write16(dev, B43_SHM_SHARED,
1428 B43_SHM_SH_DTIMPER, dtim_period);
1429 break;
1430 }
1431 i += ie_len + 2;
1432 }
1433 if (!tim_found) {
04dea136
JB		 1434 /*
1435 * If ucode wants to modify TIM do it behind the beacon, this
1436 * will happen, for example, when doing mesh networking.
1437 */
1438 b43_shm_write16(dev, B43_SHM_SHARED,
1439 B43_SHM_SH_TIMBPOS,
1440 len + sizeof(struct b43_plcp_hdr6));
1441 b43_shm_write16(dev, B43_SHM_SHARED,
1442 B43_SHM_SH_DTIMPER, 0);
1443 }
1444 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1445}
1446
1447static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1448 u16 shm_offset, u16 size,
1449 struct ieee80211_rate *rate)
e4d6b795
MB		 1450{
1451 struct b43_plcp_hdr4 plcp;
1452 u32 tmp;
1453 __le16 dur;
1454
1455 plcp.data = 0;
8318d78a 1456 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1457 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1458 dev->wl->vif, size,
8318d78a 1459 rate);
e4d6b795
MB		 1460 /* Write PLCP in two parts and timing for packet transfer */
1461 tmp = le32_to_cpu(plcp.data);
1462 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1463 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1464 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1465}
1466
1467/* Instead of using custom probe response template, this function
1468 * just patches custom beacon template by:
1469 * 1) Changing packet type
1470 * 2) Patching duration field
1471 * 3) Stripping TIM
1472 */
e66fee6a 1473static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1474 u16 *dest_size,
1475 struct ieee80211_rate *rate)
e4d6b795
MB		 1476{
1477 const u8 *src_data;
1478 u8 *dest_data;
1479 u16 src_size, elem_size, src_pos, dest_pos;
1480 __le16 dur;
1481 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1482 size_t ie_start;
1483
1484 src_size = dev->wl->current_beacon->len;
1485 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1486
e66fee6a
MB		 1487 /* Get the start offset of the variable IEs in the packet. */
1488 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1489 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1490
e66fee6a 1491 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1492 return NULL;
e4d6b795
MB		 1493
1494 dest_data = kmalloc(src_size, GFP_ATOMIC);
1495 if (unlikely(!dest_data))
1496 return NULL;
1497
e66fee6a
MB		 1498 /* Copy the static data and all Information Elements, except the TIM. */
1499 memcpy(dest_data, src_data, ie_start);
1500 src_pos = ie_start;
1501 dest_pos = ie_start;
1502 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1503 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1504 if (src_data[src_pos] == 5) {
1505 /* This is the TIM. */
1506 continue;
e4d6b795 1507 }
e66fee6a
MB		 1508 memcpy(dest_data + dest_pos, src_data + src_pos,
1509 elem_size);
1510 dest_pos += elem_size;
e4d6b795
MB		 1511 }
1512 *dest_size = dest_pos;
1513 hdr = (struct ieee80211_hdr *)dest_data;
1514
1515 /* Set the frame control. */
1516 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1517 IEEE80211_STYPE_PROBE_RESP);
1518 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1519 dev->wl->vif, *dest_size,
8318d78a 1520 rate);
e4d6b795
MB		 1521 hdr->duration_id = dur;
1522
1523 return dest_data;
1524}
1525
1526static void b43_write_probe_resp_template(struct b43_wldev *dev,
1527 u16 ram_offset,
8318d78a
JB		 1528 u16 shm_size_offset,
1529 struct ieee80211_rate *rate)
e4d6b795 1530{
e66fee6a 1531 const u8 *probe_resp_data;
e4d6b795
MB		 1532 u16 size;
1533
e66fee6a 1534 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1535 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1536 if (unlikely(!probe_resp_data))
1537 return;
1538
1539 /* Looks like PLCP headers plus packet timings are stored for
1540 * all possible basic rates
1541 */
8318d78a
JB		 1542 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1543 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1544 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1545 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1546
1547 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1548 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1549 size, ram_offset, shm_size_offset,
1550 rate->hw_value);
e4d6b795
MB		 1551 kfree(probe_resp_data);
1552}
1553
6b4bec01
MB		 1554static void b43_upload_beacon0(struct b43_wldev *dev)
1555{
1556 struct b43_wl *wl = dev->wl;
1557
1558 if (wl->beacon0_uploaded)
1559 return;
1560 b43_write_beacon_template(dev, 0x68, 0x18);
1561 /* FIXME: Probe resp upload doesn't really belong here,
1562 * but we don't use that feature anyway. */
1563 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1564 &__b43_ratetable[3]);
1565 wl->beacon0_uploaded = 1;
1566}
1567
1568static void b43_upload_beacon1(struct b43_wldev *dev)
1569{
1570 struct b43_wl *wl = dev->wl;
1571
1572 if (wl->beacon1_uploaded)
1573 return;
1574 b43_write_beacon_template(dev, 0x468, 0x1A);
1575 wl->beacon1_uploaded = 1;
1576}
1577
c97a4ccc
MB		 1578static void handle_irq_beacon(struct b43_wldev *dev)
1579{
1580 struct b43_wl *wl = dev->wl;
1581 u32 cmd, beacon0_valid, beacon1_valid;
1582
05c914fe
JB		 1583 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1584 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1585 return;
1586
1587 /* This is the bottom half of the asynchronous beacon update. */
1588
1589 /* Ignore interrupt in the future. */
1590 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1591
1592 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1593 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1594 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1595
1596 /* Schedule interrupt manually, if busy. */
1597 if (beacon0_valid && beacon1_valid) {
1598 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1599 dev->irq_savedstate |= B43_IRQ_BEACON;
1600 return;
1601 }
1602
6b4bec01
MB		 1603 if (unlikely(wl->beacon_templates_virgin)) {
1604 /* We never uploaded a beacon before.
1605 * Upload both templates now, but only mark one valid. */
1606 wl->beacon_templates_virgin = 0;
1607 b43_upload_beacon0(dev);
1608 b43_upload_beacon1(dev);
c97a4ccc
MB		 1609 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1610 cmd |= B43_MACCMD_BEACON0_VALID;
1611 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1612 } else {
1613 if (!beacon0_valid) {
1614 b43_upload_beacon0(dev);
1615 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1616 cmd |= B43_MACCMD_BEACON0_VALID;
1617 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1618 } else if (!beacon1_valid) {
1619 b43_upload_beacon1(dev);
1620 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1621 cmd |= B43_MACCMD_BEACON1_VALID;
1622 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1623 }
c97a4ccc
MB		 1624 }
1625}
1626
a82d9922
MB		 1627static void b43_beacon_update_trigger_work(struct work_struct *work)
1628{
1629 struct b43_wl *wl = container_of(work, struct b43_wl,
1630 beacon_update_trigger);
1631 struct b43_wldev *dev;
1632
1633 mutex_lock(&wl->mutex);
1634 dev = wl->current_dev;
1635 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1636 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1637 /* update beacon right away or defer to irq */
1638 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1639 handle_irq_beacon(dev);
1640 /* The handler might have updated the IRQ mask. */
1641 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1642 dev->irq_savedstate);
1643 mmiowb();
a82d9922
MB		 1644 spin_unlock_irq(&wl->irq_lock);
1645 }
1646 mutex_unlock(&wl->mutex);
1647}
1648
d4df6f1a
MB		 1649/* Asynchronously update the packet templates in template RAM.
1650 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1651static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1652{
9d139c81
JB		 1653 struct sk_buff *beacon;
1654
e66fee6a
MB		 1655 /* This is the top half of the ansynchronous beacon update.
1656 * The bottom half is the beacon IRQ.
1657 * Beacon update must be asynchronous to avoid sending an
1658 * invalid beacon. This can happen for example, if the firmware
1659 * transmits a beacon while we are updating it. */
e4d6b795 1660
9d139c81
JB		 1661 /* We could modify the existing beacon and set the aid bit in
1662 * the TIM field, but that would probably require resizing and
1663 * moving of data within the beacon template.
1664 * Simply request a new beacon and let mac80211 do the hard work. */
1665 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1666 if (unlikely(!beacon))
1667 return;
1668
e66fee6a
MB		 1669 if (wl->current_beacon)
1670 dev_kfree_skb_any(wl->current_beacon);
1671 wl->current_beacon = beacon;
1672 wl->beacon0_uploaded = 0;
1673 wl->beacon1_uploaded = 0;
a82d9922 1674 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1675}
1676
1677static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1678{
1679 u32 tmp;
1680 u16 i, len;
1681
1682 len = min((u16) ssid_len, (u16) 0x100);
1683 for (i = 0; i < len; i += sizeof(u32)) {
1684 tmp = (u32) (ssid[i + 0]);
1685 if (i + 1 < len)
1686 tmp |= (u32) (ssid[i + 1]) << 8;
1687 if (i + 2 < len)
1688 tmp |= (u32) (ssid[i + 2]) << 16;
1689 if (i + 3 < len)
1690 tmp |= (u32) (ssid[i + 3]) << 24;
1691 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1692 }
1693 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1694}
1695
1696static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1697{
1698 b43_time_lock(dev);
1699 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1700 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1701 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1702 } else {
1703 b43_write16(dev, 0x606, (beacon_int >> 6));
1704 b43_write16(dev, 0x610, beacon_int);
1705 }
1706 b43_time_unlock(dev);
a82d9922 1707 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1708}
1709
afa83e23
MB		 1710static void b43_handle_firmware_panic(struct b43_wldev *dev)
1711{
1712 u16 reason;
1713
1714 /* Read the register that contains the reason code for the panic. */
1715 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1716 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1717
1718 switch (reason) {
1719 default:
1720 b43dbg(dev->wl, "The panic reason is unknown.\n");
1721 /* fallthrough */
1722 case B43_FWPANIC_DIE:
1723 /* Do not restart the controller or firmware.
1724 * The device is nonfunctional from now on.
1725 * Restarting would result in this panic to trigger again,
1726 * so we avoid that recursion. */
1727 break;
1728 case B43_FWPANIC_RESTART:
1729 b43_controller_restart(dev, "Microcode panic");
1730 break;
1731 }
1732}
1733
e4d6b795
MB		 1734static void handle_irq_ucode_debug(struct b43_wldev *dev)
1735{
e48b0eeb 1736 unsigned int i, cnt;
53c06856 1737 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1738 __le16 *buf;
1739
1740 /* The proprietary firmware doesn't have this IRQ. */
1741 if (!dev->fw.opensource)
1742 return;
1743
afa83e23
MB		 1744 /* Read the register that contains the reason code for this IRQ. */
1745 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1746
e48b0eeb
MB		 1747 switch (reason) {
1748 case B43_DEBUGIRQ_PANIC:
afa83e23 1749 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1750 break;
1751 case B43_DEBUGIRQ_DUMP_SHM:
1752 if (!B43_DEBUG)
1753 break; /* Only with driver debugging enabled. */
1754 buf = kmalloc(4096, GFP_ATOMIC);
1755 if (!buf) {
1756 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1757 goto out;
1758 }
1759 for (i = 0; i < 4096; i += 2) {
1760 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1761 buf[i / 2] = cpu_to_le16(tmp);
1762 }
1763 b43info(dev->wl, "Shared memory dump:\n");
1764 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1765 16, 2, buf, 4096, 1);
1766 kfree(buf);
1767 break;
1768 case B43_DEBUGIRQ_DUMP_REGS:
1769 if (!B43_DEBUG)
1770 break; /* Only with driver debugging enabled. */
1771 b43info(dev->wl, "Microcode register dump:\n");
1772 for (i = 0, cnt = 0; i < 64; i++) {
1773 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1774 if (cnt == 0)
1775 printk(KERN_INFO);
1776 printk("r%02u: 0x%04X ", i, tmp);
1777 cnt++;
1778 if (cnt == 6) {
1779 printk("\n");
1780 cnt = 0;
1781 }
1782 }
1783 printk("\n");
1784 break;
53c06856
MB		 1785 case B43_DEBUGIRQ_MARKER:
1786 if (!B43_DEBUG)
1787 break; /* Only with driver debugging enabled. */
1788 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1789 B43_MARKER_ID_REG);
1790 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1791 B43_MARKER_LINE_REG);
1792 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1793 "at line number %u\n",
1794 marker_id, marker_line);
1795 break;
e48b0eeb
MB		 1796 default:
1797 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1798 reason);
1799 }
1800out:
afa83e23
MB		 1801 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1802 b43_shm_write16(dev, B43_SHM_SCRATCH,
1803 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1804}
1805
1806/* Interrupt handler bottom-half */
1807static void b43_interrupt_tasklet(struct b43_wldev *dev)
1808{
1809 u32 reason;
1810 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1811 u32 merged_dma_reason = 0;
21954c36 1812 int i;
e4d6b795
MB		 1813 unsigned long flags;
1814
1815 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1816
1817 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1818
1819 reason = dev->irq_reason;
1820 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1821 dma_reason[i] = dev->dma_reason[i];
1822 merged_dma_reason |= dma_reason[i];
1823 }
1824
1825 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1826 b43err(dev->wl, "MAC transmission error\n");
1827
00e0b8cb 1828 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1829 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1830 rmb();
1831 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1832 atomic_set(&dev->phy.txerr_cnt,
1833 B43_PHY_TX_BADNESS_LIMIT);
1834 b43err(dev->wl, "Too many PHY TX errors, "
1835 "restarting the controller\n");
1836 b43_controller_restart(dev, "PHY TX errors");
1837 }
1838 }
e4d6b795
MB		 1839
1840 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1841 B43_DMAIRQ_NONFATALMASK))) {
1842 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1843 b43err(dev->wl, "Fatal DMA error: "
1844 "0x%08X, 0x%08X, 0x%08X, "
1845 "0x%08X, 0x%08X, 0x%08X\n",
1846 dma_reason[0], dma_reason[1],
1847 dma_reason[2], dma_reason[3],
1848 dma_reason[4], dma_reason[5]);
1849 b43_controller_restart(dev, "DMA error");
1850 mmiowb();
1851 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1852 return;
1853 }
1854 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1855 b43err(dev->wl, "DMA error: "
1856 "0x%08X, 0x%08X, 0x%08X, "
1857 "0x%08X, 0x%08X, 0x%08X\n",
1858 dma_reason[0], dma_reason[1],
1859 dma_reason[2], dma_reason[3],
1860 dma_reason[4], dma_reason[5]);
1861 }
1862 }
1863
1864 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1865 handle_irq_ucode_debug(dev);
1866 if (reason & B43_IRQ_TBTT_INDI)
1867 handle_irq_tbtt_indication(dev);
1868 if (reason & B43_IRQ_ATIM_END)
1869 handle_irq_atim_end(dev);
1870 if (reason & B43_IRQ_BEACON)
1871 handle_irq_beacon(dev);
1872 if (reason & B43_IRQ_PMQ)
1873 handle_irq_pmq(dev);
21954c36
MB		 1874 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1875 ;/* TODO */
1876 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1877 handle_irq_noise(dev);
1878
1879 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1880 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1881 if (b43_using_pio_transfers(dev))
1882 b43_pio_rx(dev->pio.rx_queue);
1883 else
1884 b43_dma_rx(dev->dma.rx_ring);
1885 }
e4d6b795
MB		 1886 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1887 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1888 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1889 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1890 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1891
21954c36 1892 if (reason & B43_IRQ_TX_OK)
e4d6b795 1893 handle_irq_transmit_status(dev);
e4d6b795 1894
e4d6b795
MB		 1895 b43_interrupt_enable(dev, dev->irq_savedstate);
1896 mmiowb();
1897 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1898}
1899
e4d6b795
MB		 1900static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1901{
e4d6b795
MB		 1902 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1903
1904 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1905 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1906 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1907 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1908 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1909 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1910}
1911
1912/* Interrupt handler top-half */
1913static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1914{
1915 irqreturn_t ret = IRQ_NONE;
1916 struct b43_wldev *dev = dev_id;
1917 u32 reason;
1918
1919 if (!dev)
1920 return IRQ_NONE;
1921
1922 spin_lock(&dev->wl->irq_lock);
1923
1924 if (b43_status(dev) < B43_STAT_STARTED)
1925 goto out;
1926 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1927 if (reason == 0xffffffff) /* shared IRQ */
1928 goto out;
1929 ret = IRQ_HANDLED;
1930 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1931 if (!reason)
1932 goto out;
1933
1934 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1935 & 0x0001DC00;
1936 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1937 & 0x0000DC00;
1938 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1939 & 0x0000DC00;
1940 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1941 & 0x0001DC00;
1942 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1943 & 0x0000DC00;
1944 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1945 & 0x0000DC00;
1946
1947 b43_interrupt_ack(dev, reason);
1948 /* disable all IRQs. They are enabled again in the bottom half. */
1949 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1950 /* save the reason code and call our bottom half. */
1951 dev->irq_reason = reason;
1952 tasklet_schedule(&dev->isr_tasklet);
1953 out:
1954 mmiowb();
1955 spin_unlock(&dev->wl->irq_lock);
1956
1957 return ret;
1958}
1959
61cb5dd6
MB		 1960static void do_release_fw(struct b43_firmware_file *fw)
1961{
1962 release_firmware(fw->data);
1963 fw->data = NULL;
1964 fw->filename = NULL;
1965}
1966
e4d6b795
MB		 1967static void b43_release_firmware(struct b43_wldev *dev)
1968{
61cb5dd6
MB		 1969 do_release_fw(&dev->fw.ucode);
1970 do_release_fw(&dev->fw.pcm);
1971 do_release_fw(&dev->fw.initvals);
1972 do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1973}
1974
eb189d8b 1975static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1976{
eb189d8b
MB		 1977 const char *text;
1978
1979 text = "You must go to "
354807e0 1980 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 1981 "and download the latest firmware (version 4).\n";
1982 if (error)
1983 b43err(wl, text);
1984 else
1985 b43warn(wl, text);
e4d6b795
MB		 1986}
1987
1988static int do_request_fw(struct b43_wldev *dev,
1989 const char *name,
68217832
MB		 1990 struct b43_firmware_file *fw,
1991 bool silent)
e4d6b795 1992{
1a09404a 1993 char path[sizeof(modparam_fwpostfix) + 32];
61cb5dd6 1994 const struct firmware *blob;
e4d6b795
MB		 1995 struct b43_fw_header *hdr;
1996 u32 size;
1997 int err;
1998
61cb5dd6
MB		 1999 if (!name) {
2000 /* Don't fetch anything. Free possibly cached firmware. */
2001 do_release_fw(fw);
e4d6b795 2002 return 0;
61cb5dd6
MB		 2003 }
2004 if (fw->filename) {
2005 if (strcmp(fw->filename, name) == 0)
2006 return 0; /* Already have this fw. */
2007 /* Free the cached firmware first. */
2008 do_release_fw(fw);
2009 }
e4d6b795
MB		 2010
2011 snprintf(path, ARRAY_SIZE(path),
2012 "b43%s/%s.fw",
2013 modparam_fwpostfix, name);
61cb5dd6 2014 err = request_firmware(&blob, path, dev->dev->dev);
68217832
MB		 2015 if (err == -ENOENT) {
2016 if (!silent) {
2017 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2018 path);
2019 }
2020 return err;
2021 } else if (err) {
2022 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2023 path, err);
e4d6b795
MB		 2024 return err;
2025 }
61cb5dd6 2026 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2027 goto err_format;
61cb5dd6 2028 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2029 switch (hdr->type) {
2030 case B43_FW_TYPE_UCODE:
2031 case B43_FW_TYPE_PCM:
2032 size = be32_to_cpu(hdr->size);
61cb5dd6 2033 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2034 goto err_format;
2035 /* fallthrough */
2036 case B43_FW_TYPE_IV:
2037 if (hdr->ver != 1)
2038 goto err_format;
2039 break;
2040 default:
2041 goto err_format;
2042 }
2043
61cb5dd6
MB		 2044 fw->data = blob;
2045 fw->filename = name;
2046
2047 return 0;
e4d6b795
MB		 2048
2049err_format:
2050 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
61cb5dd6
MB		 2051 release_firmware(blob);
2052
e4d6b795
MB		 2053 return -EPROTO;
2054}
2055
2056static int b43_request_firmware(struct b43_wldev *dev)
2057{
2058 struct b43_firmware *fw = &dev->fw;
2059 const u8 rev = dev->dev->id.revision;
2060 const char *filename;
2061 u32 tmshigh;
2062 int err;
2063
61cb5dd6 2064 /* Get microcode */
e4d6b795 2065 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2066 if ((rev >= 5) && (rev <= 10))
2067 filename = "ucode5";
2068 else if ((rev >= 11) && (rev <= 12))
2069 filename = "ucode11";
2070 else if (rev >= 13)
2071 filename = "ucode13";
2072 else
2073 goto err_no_ucode;
68217832 2074 err = do_request_fw(dev, filename, &fw->ucode, 0);
61cb5dd6
MB		 2075 if (err)
2076 goto err_load;
2077
2078 /* Get PCM code */
2079 if ((rev >= 5) && (rev <= 10))
2080 filename = "pcm5";
2081 else if (rev >= 11)
2082 filename = NULL;
2083 else
2084 goto err_no_pcm;
68217832
MB		 2085 fw->pcm_request_failed = 0;
2086 err = do_request_fw(dev, filename, &fw->pcm, 1);
2087 if (err == -ENOENT) {
2088 /* We did not find a PCM file? Not fatal, but
2089 * core rev <= 10 must do without hwcrypto then. */
2090 fw->pcm_request_failed = 1;
2091 } else if (err)
61cb5dd6
MB		 2092 goto err_load;
2093
2094 /* Get initvals */
2095 switch (dev->phy.type) {
2096 case B43_PHYTYPE_A:
2097 if ((rev >= 5) && (rev <= 10)) {
2098 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2099 filename = "a0g1initvals5";
2100 else
2101 filename = "a0g0initvals5";
2102 } else
2103 goto err_no_initvals;
2104 break;
2105 case B43_PHYTYPE_G:
e4d6b795 2106 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2107 filename = "b0g0initvals5";
e4d6b795 2108 else if (rev >= 13)
e9304882 2109 filename = "b0g0initvals13";
e4d6b795 2110 else
61cb5dd6
MB		 2111 goto err_no_initvals;
2112 break;
2113 case B43_PHYTYPE_N:
2114 if ((rev >= 11) && (rev <= 12))
2115 filename = "n0initvals11";
2116 else
2117 goto err_no_initvals;
2118 break;
2119 default:
2120 goto err_no_initvals;
e4d6b795 2121 }
68217832 2122 err = do_request_fw(dev, filename, &fw->initvals, 0);
61cb5dd6
MB		 2123 if (err)
2124 goto err_load;
2125
2126 /* Get bandswitch initvals */
2127 switch (dev->phy.type) {
2128 case B43_PHYTYPE_A:
2129 if ((rev >= 5) && (rev <= 10)) {
2130 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2131 filename = "a0g1bsinitvals5";
2132 else
2133 filename = "a0g0bsinitvals5";
2134 } else if (rev >= 11)
2135 filename = NULL;
2136 else
2137 goto err_no_initvals;
2138 break;
2139 case B43_PHYTYPE_G:
e4d6b795 2140 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2141 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2142 else if (rev >= 11)
2143 filename = NULL;
2144 else
e4d6b795 2145 goto err_no_initvals;
61cb5dd6
MB		 2146 break;
2147 case B43_PHYTYPE_N:
2148 if ((rev >= 11) && (rev <= 12))
2149 filename = "n0bsinitvals11";
2150 else
e4d6b795 2151 goto err_no_initvals;
61cb5dd6
MB		 2152 break;
2153 default:
2154 goto err_no_initvals;
e4d6b795 2155 }
68217832 2156 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
61cb5dd6
MB		 2157 if (err)
2158 goto err_load;
e4d6b795
MB		 2159
2160 return 0;
2161
2162err_load:
eb189d8b 2163 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2164 goto error;
2165
2166err_no_ucode:
2167 err = -ENODEV;
2168 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2169 goto error;
2170
2171err_no_pcm:
2172 err = -ENODEV;
2173 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2174 goto error;
2175
2176err_no_initvals:
2177 err = -ENODEV;
2178 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2179 "core rev %u\n", dev->phy.type, rev);
2180 goto error;
2181
2182error:
2183 b43_release_firmware(dev);
2184 return err;
2185}
2186
2187static int b43_upload_microcode(struct b43_wldev *dev)
2188{
2189 const size_t hdr_len = sizeof(struct b43_fw_header);
2190 const __be32 *data;
2191 unsigned int i, len;
2192 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2193 u32 tmp, macctl;
e4d6b795
MB		 2194 int err = 0;
2195
1f7d87b0
MB		 2196 /* Jump the microcode PSM to offset 0 */
2197 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2198 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2199 macctl |= B43_MACCTL_PSM_JMP0;
2200 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2201 /* Zero out all microcode PSM registers and shared memory. */
2202 for (i = 0; i < 64; i++)
2203 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2204 for (i = 0; i < 4096; i += 2)
2205 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2206
e4d6b795 2207 /* Upload Microcode. */
61cb5dd6
MB		 2208 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2209 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2210 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2211 for (i = 0; i < len; i++) {
2212 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2213 udelay(10);
2214 }
2215
61cb5dd6 2216 if (dev->fw.pcm.data) {
e4d6b795 2217 /* Upload PCM data. */
61cb5dd6
MB		 2218 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2219 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2220 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2221 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2222 /* No need for autoinc bit in SHM_HW */
2223 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2224 for (i = 0; i < len; i++) {
2225 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2226 udelay(10);
2227 }
2228 }
2229
2230 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2231
2232 /* Start the microcode PSM */
2233 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2234 macctl &= ~B43_MACCTL_PSM_JMP0;
2235 macctl |= B43_MACCTL_PSM_RUN;
2236 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2237
2238 /* Wait for the microcode to load and respond */
2239 i = 0;
2240 while (1) {
2241 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2242 if (tmp == B43_IRQ_MAC_SUSPENDED)
2243 break;
2244 i++;
1f7d87b0 2245 if (i >= 20) {
e4d6b795 2246 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2247 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2248 err = -ENODEV;
1f7d87b0
MB		 2249 goto error;
2250 }
2251 msleep_interruptible(50);
2252 if (signal_pending(current)) {
2253 err = -EINTR;
2254 goto error;
e4d6b795 2255 }
e4d6b795
MB		 2256 }
2257 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2258
2259 /* Get and check the revisions. */
2260 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2261 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2262 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2263 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2264
2265 if (fwrev <= 0x128) {
2266 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2267 "binary drivers older than version 4.x is unsupported. "
2268 "You must upgrade your firmware files.\n");
eb189d8b 2269 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2270 err = -EOPNOTSUPP;
1f7d87b0 2271 goto error;
e4d6b795 2272 }
e4d6b795
MB		 2273 dev->fw.rev = fwrev;
2274 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2275 dev->fw.opensource = (fwdate == 0xFFFF);
2276
2277 if (dev->fw.opensource) {
2278 /* Patchlevel info is encoded in the "time" field. */
2279 dev->fw.patch = fwtime;
68217832
MB		 2280 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2281 dev->fw.rev, dev->fw.patch,
2282 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
e48b0eeb
MB		 2283 } else {
2284 b43info(dev->wl, "Loading firmware version %u.%u "
2285 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2286 fwrev, fwpatch,
2287 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2288 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2289 if (dev->fw.pcm_request_failed) {
2290 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2291 "Hardware accelerated cryptography is disabled.\n");
2292 b43_print_fw_helptext(dev->wl, 0);
2293 }
e48b0eeb 2294 }
e4d6b795 2295
eb189d8b
MB		 2296 if (b43_is_old_txhdr_format(dev)) {
2297 b43warn(dev->wl, "You are using an old firmware image. "
2298 "Support for old firmware will be removed in July 2008.\n");
2299 b43_print_fw_helptext(dev->wl, 0);
2300 }
2301
1f7d87b0
MB		 2302 return 0;
2303
2304error:
2305 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2306 macctl &= ~B43_MACCTL_PSM_RUN;
2307 macctl |= B43_MACCTL_PSM_JMP0;
2308 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2309
e4d6b795
MB		 2310 return err;
2311}
2312
2313static int b43_write_initvals(struct b43_wldev *dev,
2314 const struct b43_iv *ivals,
2315 size_t count,
2316 size_t array_size)
2317{
2318 const struct b43_iv *iv;
2319 u16 offset;
2320 size_t i;
2321 bool bit32;
2322
2323 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2324 iv = ivals;
2325 for (i = 0; i < count; i++) {
2326 if (array_size < sizeof(iv->offset_size))
2327 goto err_format;
2328 array_size -= sizeof(iv->offset_size);
2329 offset = be16_to_cpu(iv->offset_size);
2330 bit32 = !!(offset & B43_IV_32BIT);
2331 offset &= B43_IV_OFFSET_MASK;
2332 if (offset >= 0x1000)
2333 goto err_format;
2334 if (bit32) {
2335 u32 value;
2336
2337 if (array_size < sizeof(iv->data.d32))
2338 goto err_format;
2339 array_size -= sizeof(iv->data.d32);
2340
533dd1b0 2341 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2342 b43_write32(dev, offset, value);
2343
2344 iv = (const struct b43_iv *)((const uint8_t *)iv +
2345 sizeof(__be16) +
2346 sizeof(__be32));
2347 } else {
2348 u16 value;
2349
2350 if (array_size < sizeof(iv->data.d16))
2351 goto err_format;
2352 array_size -= sizeof(iv->data.d16);
2353
2354 value = be16_to_cpu(iv->data.d16);
2355 b43_write16(dev, offset, value);
2356
2357 iv = (const struct b43_iv *)((const uint8_t *)iv +
2358 sizeof(__be16) +
2359 sizeof(__be16));
2360 }
2361 }
2362 if (array_size)
2363 goto err_format;
2364
2365 return 0;
2366
2367err_format:
2368 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2369 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2370
2371 return -EPROTO;
2372}
2373
2374static int b43_upload_initvals(struct b43_wldev *dev)
2375{
2376 const size_t hdr_len = sizeof(struct b43_fw_header);
2377 const struct b43_fw_header *hdr;
2378 struct b43_firmware *fw = &dev->fw;
2379 const struct b43_iv *ivals;
2380 size_t count;
2381 int err;
2382
61cb5dd6
MB		 2383 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2384 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2385 count = be32_to_cpu(hdr->size);
2386 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2387 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2388 if (err)
2389 goto out;
61cb5dd6
MB		 2390 if (fw->initvals_band.data) {
2391 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2392 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2393 count = be32_to_cpu(hdr->size);
2394 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2395 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2396 if (err)
2397 goto out;
2398 }
2399out:
2400
2401 return err;
2402}
2403
2404/* Initialize the GPIOs
2405 * http://bcm-specs.sipsolutions.net/GPIO
2406 */
2407static int b43_gpio_init(struct b43_wldev *dev)
2408{
2409 struct ssb_bus *bus = dev->dev->bus;
2410 struct ssb_device *gpiodev, *pcidev = NULL;
2411 u32 mask, set;
2412
2413 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2414 & ~B43_MACCTL_GPOUTSMSK);
2415
e4d6b795
MB		 2416 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2417 | 0x000F);
2418
2419 mask = 0x0000001F;
2420 set = 0x0000000F;
2421 if (dev->dev->bus->chip_id == 0x4301) {
2422 mask |= 0x0060;
2423 set |= 0x0060;
2424 }
2425 if (0 /* FIXME: conditional unknown */ ) {
2426 b43_write16(dev, B43_MMIO_GPIO_MASK,
2427 b43_read16(dev, B43_MMIO_GPIO_MASK)
2428 | 0x0100);
2429 mask |= 0x0180;
2430 set |= 0x0180;
2431 }
95de2841 2432 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2433 b43_write16(dev, B43_MMIO_GPIO_MASK,
2434 b43_read16(dev, B43_MMIO_GPIO_MASK)
2435 | 0x0200);
2436 mask |= 0x0200;
2437 set |= 0x0200;
2438 }
2439 if (dev->dev->id.revision >= 2)
2440 mask |= 0x0010; /* FIXME: This is redundant. */
2441
2442#ifdef CONFIG_SSB_DRIVER_PCICORE
2443 pcidev = bus->pcicore.dev;
2444#endif
2445 gpiodev = bus->chipco.dev ? : pcidev;
2446 if (!gpiodev)
2447 return 0;
2448 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2449 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2450 & mask) | set);
2451
2452 return 0;
2453}
2454
2455/* Turn off all GPIO stuff. Call this on module unload, for example. */
2456static void b43_gpio_cleanup(struct b43_wldev *dev)
2457{
2458 struct ssb_bus *bus = dev->dev->bus;
2459 struct ssb_device *gpiodev, *pcidev = NULL;
2460
2461#ifdef CONFIG_SSB_DRIVER_PCICORE
2462 pcidev = bus->pcicore.dev;
2463#endif
2464 gpiodev = bus->chipco.dev ? : pcidev;
2465 if (!gpiodev)
2466 return;
2467 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2468}
2469
2470/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2471void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2472{
923fd703
MB		 2473 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2474 u16 fwstate;
2475
2476 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2477 B43_SHM_SH_UCODESTAT);
2478 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2479 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2480 b43err(dev->wl, "b43_mac_enable(): The firmware "
2481 "should be suspended, but current state is %u\n",
2482 fwstate);
2483 }
2484 }
2485
e4d6b795
MB		 2486 dev->mac_suspended--;
2487 B43_WARN_ON(dev->mac_suspended < 0);
2488 if (dev->mac_suspended == 0) {
2489 b43_write32(dev, B43_MMIO_MACCTL,
2490 b43_read32(dev, B43_MMIO_MACCTL)
2491 | B43_MACCTL_ENABLED);
2492 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2493 B43_IRQ_MAC_SUSPENDED);
2494 /* Commit writes */
2495 b43_read32(dev, B43_MMIO_MACCTL);
2496 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2497 b43_power_saving_ctl_bits(dev, 0);
2498 }
2499}
2500
2501/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2502void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2503{
2504 int i;
2505 u32 tmp;
2506
05b64b36 2507 might_sleep();
e4d6b795 2508 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2509
e4d6b795
MB		 2510 if (dev->mac_suspended == 0) {
2511 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2512 b43_write32(dev, B43_MMIO_MACCTL,
2513 b43_read32(dev, B43_MMIO_MACCTL)
2514 & ~B43_MACCTL_ENABLED);
2515 /* force pci to flush the write */
2516 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2517 for (i = 35; i; i--) {
2518 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2519 if (tmp & B43_IRQ_MAC_SUSPENDED)
2520 goto out;
2521 udelay(10);
2522 }
2523 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2524 for (i = 40; i; i--) {
e4d6b795
MB		 2525 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2526 if (tmp & B43_IRQ_MAC_SUSPENDED)
2527 goto out;
05b64b36 2528 msleep(1);
e4d6b795
MB		 2529 }
2530 b43err(dev->wl, "MAC suspend failed\n");
2531 }
05b64b36 2532out:
e4d6b795
MB		 2533 dev->mac_suspended++;
2534}
2535
2536static void b43_adjust_opmode(struct b43_wldev *dev)
2537{
2538 struct b43_wl *wl = dev->wl;
2539 u32 ctl;
2540 u16 cfp_pretbtt;
2541
2542 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2543 /* Reset status to STA infrastructure mode. */
2544 ctl &= ~B43_MACCTL_AP;
2545 ctl &= ~B43_MACCTL_KEEP_CTL;
2546 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2547 ctl &= ~B43_MACCTL_KEEP_BAD;
2548 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2549 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2550 ctl |= B43_MACCTL_INFRA;
2551
05c914fe
JB		 2552 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2553 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2554 ctl |= B43_MACCTL_AP;
05c914fe 2555 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2556 ctl &= ~B43_MACCTL_INFRA;
2557
2558 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2559 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2560 if (wl->filter_flags & FIF_FCSFAIL)
2561 ctl |= B43_MACCTL_KEEP_BAD;
2562 if (wl->filter_flags & FIF_PLCPFAIL)
2563 ctl |= B43_MACCTL_KEEP_BADPLCP;
2564 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2565 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2566 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2567 ctl |= B43_MACCTL_BEACPROMISC;
2568
e4d6b795
MB		 2569 /* Workaround: On old hardware the HW-MAC-address-filter
2570 * doesn't work properly, so always run promisc in filter
2571 * it in software. */
2572 if (dev->dev->id.revision <= 4)
2573 ctl |= B43_MACCTL_PROMISC;
2574
2575 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2576
2577 cfp_pretbtt = 2;
2578 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2579 if (dev->dev->bus->chip_id == 0x4306 &&
2580 dev->dev->bus->chip_rev == 3)
2581 cfp_pretbtt = 100;
2582 else
2583 cfp_pretbtt = 50;
2584 }
2585 b43_write16(dev, 0x612, cfp_pretbtt);
2586}
2587
2588static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2589{
2590 u16 offset;
2591
2592 if (is_ofdm) {
2593 offset = 0x480;
2594 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2595 } else {
2596 offset = 0x4C0;
2597 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2598 }
2599 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2600 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2601}
2602
2603static void b43_rate_memory_init(struct b43_wldev *dev)
2604{
2605 switch (dev->phy.type) {
2606 case B43_PHYTYPE_A:
2607 case B43_PHYTYPE_G:
53a6e234 2608 case B43_PHYTYPE_N:
e4d6b795
MB		 2609 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2610 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2611 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2612 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2613 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2614 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2615 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2616 if (dev->phy.type == B43_PHYTYPE_A)
2617 break;
2618 /* fallthrough */
2619 case B43_PHYTYPE_B:
2620 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2621 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2622 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2623 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2624 break;
2625 default:
2626 B43_WARN_ON(1);
2627 }
2628}
2629
5042c507
MB		 2630/* Set the default values for the PHY TX Control Words. */
2631static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2632{
2633 u16 ctl = 0;
2634
2635 ctl |= B43_TXH_PHY_ENC_CCK;
2636 ctl |= B43_TXH_PHY_ANT01AUTO;
2637 ctl |= B43_TXH_PHY_TXPWR;
2638
2639 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2640 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2641 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2642}
2643
e4d6b795
MB		 2644/* Set the TX-Antenna for management frames sent by firmware. */
2645static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2646{
5042c507 2647 u16 ant;
e4d6b795
MB		 2648 u16 tmp;
2649
5042c507 2650 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2651
e4d6b795
MB		 2652 /* For ACK/CTS */
2653 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2654 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2656 /* For Probe Resposes */
2657 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2658 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2659 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2660}
2661
2662/* This is the opposite of b43_chip_init() */
2663static void b43_chip_exit(struct b43_wldev *dev)
2664{
fb11137a 2665 b43_phy_exit(dev);
e4d6b795
MB		 2666 b43_gpio_cleanup(dev);
2667 /* firmware is released later */
2668}
2669
2670/* Initialize the chip
2671 * http://bcm-specs.sipsolutions.net/ChipInit
2672 */
2673static int b43_chip_init(struct b43_wldev *dev)
2674{
2675 struct b43_phy *phy = &dev->phy;
ef1a628d 2676 int err;
1f7d87b0 2677 u32 value32, macctl;
e4d6b795
MB		 2678 u16 value16;
2679
1f7d87b0
MB		 2680 /* Initialize the MAC control */
2681 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2682 if (dev->phy.gmode)
2683 macctl |= B43_MACCTL_GMODE;
2684 macctl |= B43_MACCTL_INFRA;
2685 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2686
2687 err = b43_request_firmware(dev);
2688 if (err)
2689 goto out;
2690 err = b43_upload_microcode(dev);
2691 if (err)
2692 goto out; /* firmware is released later */
2693
2694 err = b43_gpio_init(dev);
2695 if (err)
2696 goto out; /* firmware is released later */
21954c36 2697
e4d6b795
MB		 2698 err = b43_upload_initvals(dev);
2699 if (err)
1a8d1227 2700 goto err_gpio_clean;
e4d6b795 2701
0b7dcd96
MB		 2702 /* Turn the Analog on and initialize the PHY. */
2703 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2704 err = b43_phy_init(dev);
2705 if (err)
ef1a628d 2706 goto err_gpio_clean;
e4d6b795 2707
ef1a628d
MB		 2708 /* Disable Interference Mitigation. */
2709 if (phy->ops->interf_mitigation)
2710 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2711
ef1a628d
MB		 2712 /* Select the antennae */
2713 if (phy->ops->set_rx_antenna)
2714 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2715 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2716
2717 if (phy->type == B43_PHYTYPE_B) {
2718 value16 = b43_read16(dev, 0x005E);
2719 value16 |= 0x0004;
2720 b43_write16(dev, 0x005E, value16);
2721 }
2722 b43_write32(dev, 0x0100, 0x01000000);
2723 if (dev->dev->id.revision < 5)
2724 b43_write32(dev, 0x010C, 0x01000000);
2725
2726 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2727 & ~B43_MACCTL_INFRA);
2728 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2729 | B43_MACCTL_INFRA);
e4d6b795 2730
e4d6b795
MB		 2731 /* Probe Response Timeout value */
2732 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2733 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2734
2735 /* Initially set the wireless operation mode. */
2736 b43_adjust_opmode(dev);
2737
2738 if (dev->dev->id.revision < 3) {
2739 b43_write16(dev, 0x060E, 0x0000);
2740 b43_write16(dev, 0x0610, 0x8000);
2741 b43_write16(dev, 0x0604, 0x0000);
2742 b43_write16(dev, 0x0606, 0x0200);
2743 } else {
2744 b43_write32(dev, 0x0188, 0x80000000);
2745 b43_write32(dev, 0x018C, 0x02000000);
2746 }
2747 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2748 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2749 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2750 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2751 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2752 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2753 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2754
2755 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2756 value32 |= 0x00100000;
2757 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2758
2759 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2760 dev->dev->bus->chipco.fast_pwrup_delay);
2761
2762 err = 0;
2763 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2764out:
e4d6b795
MB		 2765 return err;
2766
1a8d1227 2767err_gpio_clean:
e4d6b795 2768 b43_gpio_cleanup(dev);
21954c36 2769 return err;
e4d6b795
MB		 2770}
2771
e4d6b795
MB		 2772static void b43_periodic_every60sec(struct b43_wldev *dev)
2773{
ef1a628d 2774 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2775
ef1a628d
MB		 2776 if (ops->pwork_60sec)
2777 ops->pwork_60sec(dev);
18c8adeb
MB		 2778
2779 /* Force check the TX power emission now. */
2780 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2781}
2782
2783static void b43_periodic_every30sec(struct b43_wldev *dev)
2784{
2785 /* Update device statistics. */
2786 b43_calculate_link_quality(dev);
2787}
2788
2789static void b43_periodic_every15sec(struct b43_wldev *dev)
2790{
2791 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2792 u16 wdr;
2793
2794 if (dev->fw.opensource) {
2795 /* Check if the firmware is still alive.
2796 * It will reset the watchdog counter to 0 in its idle loop. */
2797 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2798 if (unlikely(wdr)) {
2799 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2800 b43_controller_restart(dev, "Firmware watchdog");
2801 return;
2802 } else {
2803 b43_shm_write16(dev, B43_SHM_SCRATCH,
2804 B43_WATCHDOG_REG, 1);
2805 }
2806 }
e4d6b795 2807
ef1a628d
MB		 2808 if (phy->ops->pwork_15sec)
2809 phy->ops->pwork_15sec(dev);
2810
00e0b8cb
SB		 2811 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2812 wmb();
e4d6b795
MB		 2813}
2814
e4d6b795
MB		 2815static void do_periodic_work(struct b43_wldev *dev)
2816{
2817 unsigned int state;
2818
2819 state = dev->periodic_state;
42bb4cd5 2820 if (state % 4 == 0)
e4d6b795 2821 b43_periodic_every60sec(dev);
42bb4cd5 2822 if (state % 2 == 0)
e4d6b795 2823 b43_periodic_every30sec(dev);
42bb4cd5 2824 b43_periodic_every15sec(dev);
e4d6b795
MB		 2825}
2826
05b64b36
MB		 2827/* Periodic work locking policy:
2828 * The whole periodic work handler is protected by
2829 * wl->mutex. If another lock is needed somewhere in the
2830 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2831 */
e4d6b795
MB		 2832static void b43_periodic_work_handler(struct work_struct *work)
2833{
05b64b36
MB		 2834 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2835 periodic_work.work);
2836 struct b43_wl *wl = dev->wl;
2837 unsigned long delay;
e4d6b795 2838
05b64b36 2839 mutex_lock(&wl->mutex);
e4d6b795
MB		 2840
2841 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2842 goto out;
2843 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2844 goto out_requeue;
2845
05b64b36 2846 do_periodic_work(dev);
e4d6b795 2847
e4d6b795 2848 dev->periodic_state++;
42bb4cd5 2849out_requeue:
e4d6b795
MB		 2850 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2851 delay = msecs_to_jiffies(50);
2852 else
82cd682d 2853 delay = round_jiffies_relative(HZ * 15);
05b64b36 2854 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2855out:
05b64b36 2856 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2857}
2858
2859static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2860{
2861 struct delayed_work *work = &dev->periodic_work;
2862
2863 dev->periodic_state = 0;
2864 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2865 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2866}
2867
f3dd3fcc 2868/* Check if communication with the device works correctly. */
e4d6b795
MB		 2869static int b43_validate_chipaccess(struct b43_wldev *dev)
2870{
f3dd3fcc 2871 u32 v, backup;
e4d6b795 2872
f3dd3fcc
MB		 2873 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2874
2875 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2876 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2877 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2878 goto error;
f3dd3fcc
MB		 2879 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2880 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2881 goto error;
2882
f3dd3fcc
MB		 2883 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2884
2885 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2886 /* The 32bit register shadows the two 16bit registers
2887 * with update sideeffects. Validate this. */
2888 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2889 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2890 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2891 goto error;
2892 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2893 goto error;
2894 }
2895 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2896
2897 v = b43_read32(dev, B43_MMIO_MACCTL);
2898 v |= B43_MACCTL_GMODE;
2899 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2900 goto error;
2901
2902 return 0;
f3dd3fcc 2903error:
e4d6b795
MB		 2904 b43err(dev->wl, "Failed to validate the chipaccess\n");
2905 return -ENODEV;
2906}
2907
2908static void b43_security_init(struct b43_wldev *dev)
2909{
2910 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2911 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2912 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2913 /* KTP is a word address, but we address SHM bytewise.
2914 * So multiply by two.
2915 */
2916 dev->ktp *= 2;
2917 if (dev->dev->id.revision >= 5) {
2918 /* Number of RCMTA address slots */
2919 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2920 }
2921 b43_clear_keys(dev);
2922}
2923
2924static int b43_rng_read(struct hwrng *rng, u32 * data)
2925{
2926 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2927 unsigned long flags;
2928
2929 /* Don't take wl->mutex here, as it could deadlock with
2930 * hwrng internal locking. It's not needed to take
2931 * wl->mutex here, anyway. */
2932
2933 spin_lock_irqsave(&wl->irq_lock, flags);
2934 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2935 spin_unlock_irqrestore(&wl->irq_lock, flags);
2936
2937 return (sizeof(u16));
2938}
2939
b844eba2 2940static void b43_rng_exit(struct b43_wl *wl)
e4d6b795
MB		 2941{
2942 if (wl->rng_initialized)
b844eba2 2943 hwrng_unregister(&wl->rng);
e4d6b795
MB		 2944}
2945
2946static int b43_rng_init(struct b43_wl *wl)
2947{
2948 int err;
2949
2950 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2951 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2952 wl->rng.name = wl->rng_name;
2953 wl->rng.data_read = b43_rng_read;
2954 wl->rng.priv = (unsigned long)wl;
2955 wl->rng_initialized = 1;
2956 err = hwrng_register(&wl->rng);
2957 if (err) {
2958 wl->rng_initialized = 0;
2959 b43err(wl, "Failed to register the random "
2960 "number generator (%d)\n", err);
2961 }
2962
2963 return err;
2964}
2965
40faacc4 2966static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 2967 struct sk_buff *skb)
e4d6b795
MB		 2968{
2969 struct b43_wl *wl = hw_to_b43_wl(hw);
2970 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 2971 unsigned long flags;
2972 int err;
e4d6b795 2973
5100d5ac
MB		 2974 if (unlikely(skb->len < 2 + 2 + 6)) {
2975 /* Too short, this can't be a valid frame. */
c9e8eae0 2976 goto drop_packet;
5100d5ac
MB		 2977 }
2978 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 2979 if (unlikely(!dev))
c9e8eae0 2980 goto drop_packet;
21a75d77
MB		 2981
2982 /* Transmissions on seperate queues can run concurrently. */
2983 read_lock_irqsave(&wl->tx_lock, flags);
2984
2985 err = -ENODEV;
2986 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2987 if (b43_using_pio_transfers(dev))
e039fa4a 2988 err = b43_pio_tx(dev, skb);
21a75d77 2989 else
e039fa4a 2990 err = b43_dma_tx(dev, skb);
21a75d77
MB		 2991 }
2992
2993 read_unlock_irqrestore(&wl->tx_lock, flags);
2994
e4d6b795 2995 if (unlikely(err))
c9e8eae0
MB		 2996 goto drop_packet;
2997 return NETDEV_TX_OK;
2998
2999drop_packet:
3000 /* We can not transmit this packet. Drop it. */
3001 dev_kfree_skb_any(skb);
e4d6b795
MB		 3002 return NETDEV_TX_OK;
3003}
3004
e6f5b934
MB		 3005/* Locking: wl->irq_lock */
3006static void b43_qos_params_upload(struct b43_wldev *dev,
3007 const struct ieee80211_tx_queue_params *p,
3008 u16 shm_offset)
3009{
3010 u16 params[B43_NR_QOSPARAMS];
0b57664c 3011 int bslots, tmp;
e6f5b934
MB		 3012 unsigned int i;
3013
0b57664c 3014 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3015
3016 memset(&params, 0, sizeof(params));
3017
3018 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3019 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3020 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3021 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3022 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3023 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3024 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3025
3026 for (i = 0; i < ARRAY_SIZE(params); i++) {
3027 if (i == B43_QOSPARAM_STATUS) {
3028 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3029 shm_offset + (i * 2));
3030 /* Mark the parameters as updated. */
3031 tmp |= 0x100;
3032 b43_shm_write16(dev, B43_SHM_SHARED,
3033 shm_offset + (i * 2),
3034 tmp);
3035 } else {
3036 b43_shm_write16(dev, B43_SHM_SHARED,
3037 shm_offset + (i * 2),
3038 params[i]);
3039 }
3040 }
3041}
3042
c40c1129
MB		 3043/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3044static const u16 b43_qos_shm_offsets[] = {
3045 /* [mac80211-queue-nr] = SHM_OFFSET, */
3046 [0] = B43_QOS_VOICE,
3047 [1] = B43_QOS_VIDEO,
3048 [2] = B43_QOS_BESTEFFORT,
3049 [3] = B43_QOS_BACKGROUND,
3050};
3051
5a5f3b40
MB		 3052/* Update all QOS parameters in hardware. */
3053static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3054{
3055 struct b43_wl *wl = dev->wl;
3056 struct b43_qos_params *params;
e6f5b934
MB		 3057 unsigned int i;
3058
c40c1129
MB		 3059 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3060 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3061
3062 b43_mac_suspend(dev);
e6f5b934
MB		 3063 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3064 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3065 b43_qos_params_upload(dev, &(params->p),
3066 b43_qos_shm_offsets[i]);
e6f5b934 3067 }
e6f5b934
MB		 3068 b43_mac_enable(dev);
3069}
3070
3071static void b43_qos_clear(struct b43_wl *wl)
3072{
3073 struct b43_qos_params *params;
3074 unsigned int i;
3075
c40c1129
MB		 3076 /* Initialize QoS parameters to sane defaults. */
3077
3078 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3079 ARRAY_SIZE(wl->qos_params));
3080
e6f5b934
MB		 3081 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3082 params = &(wl->qos_params[i]);
3083
c40c1129
MB		 3084 switch (b43_qos_shm_offsets[i]) {
3085 case B43_QOS_VOICE:
3086 params->p.txop = 0;
3087 params->p.aifs = 2;
3088 params->p.cw_min = 0x0001;
3089 params->p.cw_max = 0x0001;
3090 break;
3091 case B43_QOS_VIDEO:
3092 params->p.txop = 0;
3093 params->p.aifs = 2;
3094 params->p.cw_min = 0x0001;
3095 params->p.cw_max = 0x0001;
3096 break;
3097 case B43_QOS_BESTEFFORT:
3098 params->p.txop = 0;
3099 params->p.aifs = 3;
3100 params->p.cw_min = 0x0001;
3101 params->p.cw_max = 0x03FF;
3102 break;
3103 case B43_QOS_BACKGROUND:
3104 params->p.txop = 0;
3105 params->p.aifs = 7;
3106 params->p.cw_min = 0x0001;
3107 params->p.cw_max = 0x03FF;
3108 break;
3109 default:
3110 B43_WARN_ON(1);
3111 }
e6f5b934
MB		 3112 }
3113}
3114
3115/* Initialize the core's QOS capabilities */
3116static void b43_qos_init(struct b43_wldev *dev)
3117{
e6f5b934 3118 /* Upload the current QOS parameters. */
5a5f3b40 3119 b43_qos_upload_all(dev);
e6f5b934
MB		 3120
3121 /* Enable QOS support. */
3122 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3123 b43_write16(dev, B43_MMIO_IFSCTL,
3124 b43_read16(dev, B43_MMIO_IFSCTL)
3125 | B43_MMIO_IFSCTL_USE_EDCF);
3126}
3127
e100bb64 3128static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3129 const struct ieee80211_tx_queue_params *params)
e4d6b795 3130{
e6f5b934 3131 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3132 struct b43_wldev *dev;
e6f5b934 3133 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3134 int err = -ENODEV;
e6f5b934
MB		 3135
3136 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3137 /* Queue not available or don't support setting
3138 * params on this queue. Return success to not
3139 * confuse mac80211. */
3140 return 0;
3141 }
5a5f3b40
MB		 3142 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3143 ARRAY_SIZE(wl->qos_params));
e6f5b934 3144
5a5f3b40
MB		 3145 mutex_lock(&wl->mutex);
3146 dev = wl->current_dev;
3147 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3148 goto out_unlock;
e6f5b934 3149
5a5f3b40
MB		 3150 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3151 b43_mac_suspend(dev);
3152 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3153 b43_qos_shm_offsets[queue]);
3154 b43_mac_enable(dev);
3155 err = 0;
e6f5b934 3156
5a5f3b40
MB		 3157out_unlock:
3158 mutex_unlock(&wl->mutex);
3159
3160 return err;
e4d6b795
MB		 3161}
3162
40faacc4
MB		 3163static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3164 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3165{
3166 struct b43_wl *wl = hw_to_b43_wl(hw);
3167 struct b43_wldev *dev = wl->current_dev;
3168 unsigned long flags;
3169 int err = -ENODEV;
3170
3171 if (!dev)
3172 goto out;
3173 spin_lock_irqsave(&wl->irq_lock, flags);
3174 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3175 if (b43_using_pio_transfers(dev))
3176 b43_pio_get_tx_stats(dev, stats);
3177 else
3178 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3179 err = 0;
3180 }
3181 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3182out:
e4d6b795
MB		 3183 return err;
3184}
3185
40faacc4
MB		 3186static int b43_op_get_stats(struct ieee80211_hw *hw,
3187 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3188{
3189 struct b43_wl *wl = hw_to_b43_wl(hw);
3190 unsigned long flags;
3191
3192 spin_lock_irqsave(&wl->irq_lock, flags);
3193 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3194 spin_unlock_irqrestore(&wl->irq_lock, flags);
3195
3196 return 0;
3197}
3198
e4d6b795
MB		 3199static void b43_put_phy_into_reset(struct b43_wldev *dev)
3200{
3201 struct ssb_device *sdev = dev->dev;
3202 u32 tmslow;
3203
3204 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3205 tmslow &= ~B43_TMSLOW_GMODE;
3206 tmslow |= B43_TMSLOW_PHYRESET;
3207 tmslow |= SSB_TMSLOW_FGC;
3208 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3209 msleep(1);
3210
3211 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3212 tmslow &= ~SSB_TMSLOW_FGC;
3213 tmslow |= B43_TMSLOW_PHYRESET;
3214 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3215 msleep(1);
3216}
3217
bb1eeff1
MB		 3218static const char * band_to_string(enum ieee80211_band band)
3219{
3220 switch (band) {
3221 case IEEE80211_BAND_5GHZ:
3222 return "5";
3223 case IEEE80211_BAND_2GHZ:
3224 return "2.4";
3225 default:
3226 break;
3227 }
3228 B43_WARN_ON(1);
3229 return "";
3230}
3231
e4d6b795 3232/* Expects wl->mutex locked */
bb1eeff1 3233static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3234{
bb1eeff1 3235 struct b43_wldev *up_dev = NULL;
e4d6b795 3236 struct b43_wldev *down_dev;
bb1eeff1 3237 struct b43_wldev *d;
e4d6b795 3238 int err;
bb1eeff1 3239 bool gmode;
e4d6b795
MB		 3240 int prev_status;
3241
bb1eeff1
MB		 3242 /* Find a device and PHY which supports the band. */
3243 list_for_each_entry(d, &wl->devlist, list) {
3244 switch (chan->band) {
3245 case IEEE80211_BAND_5GHZ:
3246 if (d->phy.supports_5ghz) {
3247 up_dev = d;
3248 gmode = 0;
3249 }
3250 break;
3251 case IEEE80211_BAND_2GHZ:
3252 if (d->phy.supports_2ghz) {
3253 up_dev = d;
3254 gmode = 1;
3255 }
3256 break;
3257 default:
3258 B43_WARN_ON(1);
3259 return -EINVAL;
3260 }
3261 if (up_dev)
3262 break;
3263 }
3264 if (!up_dev) {
3265 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3266 band_to_string(chan->band));
3267 return -ENODEV;
e4d6b795
MB		 3268 }
3269 if ((up_dev == wl->current_dev) &&
3270 (!!wl->current_dev->phy.gmode == !!gmode)) {
3271 /* This device is already running. */
3272 return 0;
3273 }
bb1eeff1
MB		 3274 b43dbg(wl, "Switching to %s-GHz band\n",
3275 band_to_string(chan->band));
e4d6b795
MB		 3276 down_dev = wl->current_dev;
3277
3278 prev_status = b43_status(down_dev);
3279 /* Shutdown the currently running core. */
3280 if (prev_status >= B43_STAT_STARTED)
3281 b43_wireless_core_stop(down_dev);
3282 if (prev_status >= B43_STAT_INITIALIZED)
3283 b43_wireless_core_exit(down_dev);
3284
3285 if (down_dev != up_dev) {
3286 /* We switch to a different core, so we put PHY into
3287 * RESET on the old core. */
3288 b43_put_phy_into_reset(down_dev);
3289 }
3290
3291 /* Now start the new core. */
3292 up_dev->phy.gmode = gmode;
3293 if (prev_status >= B43_STAT_INITIALIZED) {
3294 err = b43_wireless_core_init(up_dev);
3295 if (err) {
3296 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3297 "selected %s-GHz band\n",
3298 band_to_string(chan->band));
e4d6b795
MB		 3299 goto init_failure;
3300 }
3301 }
3302 if (prev_status >= B43_STAT_STARTED) {
3303 err = b43_wireless_core_start(up_dev);
3304 if (err) {
3305 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3306 "selected %s-GHz band\n",
3307 band_to_string(chan->band));
e4d6b795
MB		 3308 b43_wireless_core_exit(up_dev);
3309 goto init_failure;
3310 }
3311 }
3312 B43_WARN_ON(b43_status(up_dev) != prev_status);
3313
3314 wl->current_dev = up_dev;
3315
3316 return 0;
bb1eeff1 3317init_failure:
e4d6b795
MB		 3318 /* Whoops, failed to init the new core. No core is operating now. */
3319 wl->current_dev = NULL;
3320 return err;
3321}
3322
e8975581 3323static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3324{
3325 struct b43_wl *wl = hw_to_b43_wl(hw);
3326 struct b43_wldev *dev;
3327 struct b43_phy *phy;
e8975581 3328 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3329 unsigned long flags;
9db1f6d7 3330 int antenna;
e4d6b795
MB		 3331 int err = 0;
3332 u32 savedirqs;
3333
e4d6b795
MB		 3334 mutex_lock(&wl->mutex);
3335
bb1eeff1
MB		 3336 /* Switch the band (if necessary). This might change the active core. */
3337 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3338 if (err)
3339 goto out_unlock_mutex;
3340 dev = wl->current_dev;
3341 phy = &dev->phy;
3342
3343 /* Disable IRQs while reconfiguring the device.
3344 * This makes it possible to drop the spinlock throughout
3345 * the reconfiguration process. */
3346 spin_lock_irqsave(&wl->irq_lock, flags);
3347 if (b43_status(dev) < B43_STAT_STARTED) {
3348 spin_unlock_irqrestore(&wl->irq_lock, flags);
3349 goto out_unlock_mutex;
3350 }
3351 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3352 spin_unlock_irqrestore(&wl->irq_lock, flags);
3353 b43_synchronize_irq(dev);
3354
3355 /* Switch to the requested channel.
3356 * The firmware takes care of races with the TX handler. */
8318d78a 3357 if (conf->channel->hw_value != phy->channel)
ef1a628d 3358 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795
MB		 3359
3360 /* Enable/Disable ShortSlot timing. */
3361 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3362 dev->short_slot) {
3363 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3364 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3365 b43_short_slot_timing_enable(dev);
3366 else
3367 b43_short_slot_timing_disable(dev);
3368 }
3369
d42ce84a
JB		 3370 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3371
e4d6b795
MB		 3372 /* Adjust the desired TX power level. */
3373 if (conf->power_level != 0) {
18c8adeb
MB		 3374 spin_lock_irqsave(&wl->irq_lock, flags);
3375 if (conf->power_level != phy->desired_txpower) {
3376 phy->desired_txpower = conf->power_level;
3377 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3378 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3379 }
18c8adeb 3380 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3381 }
3382
3383 /* Antennas for RX and management frame TX. */
0f4ac38b 3384 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3385 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3386 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3387 if (phy->ops->set_rx_antenna)
3388 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3389
04dea136 3390 /* Update templates for AP/mesh mode. */
05c914fe
JB		 3391 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3392 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
e4d6b795
MB		 3393 b43_set_beacon_int(dev, conf->beacon_int);
3394
fda9abcf
MB		 3395 if (!!conf->radio_enabled != phy->radio_on) {
3396 if (conf->radio_enabled) {
ef1a628d 3397 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
fda9abcf
MB		 3398 b43info(dev->wl, "Radio turned on by software\n");
3399 if (!dev->radio_hw_enable) {
3400 b43info(dev->wl, "The hardware RF-kill button "
3401 "still turns the radio physically off. "
3402 "Press the button to turn it on.\n");
3403 }
3404 } else {
ef1a628d 3405 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
fda9abcf
MB		 3406 b43info(dev->wl, "Radio turned off by software\n");
3407 }
3408 }
3409
e4d6b795
MB		 3410 spin_lock_irqsave(&wl->irq_lock, flags);
3411 b43_interrupt_enable(dev, savedirqs);
3412 mmiowb();
3413 spin_unlock_irqrestore(&wl->irq_lock, flags);
3414 out_unlock_mutex:
3415 mutex_unlock(&wl->mutex);
3416
3417 return err;
3418}
3419
40faacc4 3420static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 3421 const u8 *local_addr, const u8 *addr,
3422 struct ieee80211_key_conf *key)
e4d6b795
MB		 3423{
3424 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3425 struct b43_wldev *dev;
e4d6b795
MB		 3426 unsigned long flags;
3427 u8 algorithm;
3428 u8 index;
c6dfc9a8 3429 int err;
e4d6b795
MB		 3430
3431 if (modparam_nohwcrypt)
3432 return -ENOSPC; /* User disabled HW-crypto */
3433
c6dfc9a8
MB		 3434 mutex_lock(&wl->mutex);
3435 spin_lock_irqsave(&wl->irq_lock, flags);
3436
3437 dev = wl->current_dev;
3438 err = -ENODEV;
3439 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3440 goto out_unlock;
3441
68217832
MB		 3442 if (dev->fw.pcm_request_failed) {
3443 /* We don't have firmware for the crypto engine.
3444 * Must use software-crypto. */
3445 err = -EOPNOTSUPP;
3446 goto out_unlock;
3447 }
3448
c6dfc9a8 3449 err = -EINVAL;
e4d6b795 3450 switch (key->alg) {
e4d6b795
MB		 3451 case ALG_WEP:
3452 if (key->keylen == 5)
3453 algorithm = B43_SEC_ALGO_WEP40;
3454 else
3455 algorithm = B43_SEC_ALGO_WEP104;
3456 break;
3457 case ALG_TKIP:
3458 algorithm = B43_SEC_ALGO_TKIP;
3459 break;
3460 case ALG_CCMP:
3461 algorithm = B43_SEC_ALGO_AES;
3462 break;
3463 default:
3464 B43_WARN_ON(1);
c6dfc9a8 3465 goto out_unlock;
e4d6b795 3466 }
e4d6b795
MB		 3467 index = (u8) (key->keyidx);
3468 if (index > 3)
e4d6b795 3469 goto out_unlock;
e4d6b795
MB		 3470
3471 switch (cmd) {
3472 case SET_KEY:
3473 if (algorithm == B43_SEC_ALGO_TKIP) {
3474 /* FIXME: No TKIP hardware encryption for now. */
3475 err = -EOPNOTSUPP;
3476 goto out_unlock;
3477 }
3478
3479 if (is_broadcast_ether_addr(addr)) {
3480 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3481 err = b43_key_write(dev, index, algorithm,
3482 key->key, key->keylen, NULL, key);
3483 } else {
3484 /*
3485 * either pairwise key or address is 00:00:00:00:00:00
3486 * for transmit-only keys
3487 */
3488 err = b43_key_write(dev, -1, algorithm,
3489 key->key, key->keylen, addr, key);
3490 }
3491 if (err)
3492 goto out_unlock;
3493
3494 if (algorithm == B43_SEC_ALGO_WEP40 ||
3495 algorithm == B43_SEC_ALGO_WEP104) {
3496 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3497 } else {
3498 b43_hf_write(dev,
3499 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3500 }
3501 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3502 break;
3503 case DISABLE_KEY: {
3504 err = b43_key_clear(dev, key->hw_key_idx);
3505 if (err)
3506 goto out_unlock;
3507 break;
3508 }
3509 default:
3510 B43_WARN_ON(1);
3511 }
3512out_unlock:
3513 spin_unlock_irqrestore(&wl->irq_lock, flags);
3514 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3515 if (!err) {
3516 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3517 "mac: %pM\n",
e4d6b795 3518 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
e174961c 3519 addr);
e4d6b795
MB		 3520 }
3521 return err;
3522}
3523
40faacc4
MB		 3524static void b43_op_configure_filter(struct ieee80211_hw *hw,
3525 unsigned int changed, unsigned int *fflags,
3526 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3527{
3528 struct b43_wl *wl = hw_to_b43_wl(hw);
3529 struct b43_wldev *dev = wl->current_dev;
3530 unsigned long flags;
3531
4150c572
JB		 3532 if (!dev) {
3533 *fflags = 0;
e4d6b795 3534 return;
e4d6b795 3535 }
4150c572
JB		 3536
3537 spin_lock_irqsave(&wl->irq_lock, flags);
3538 *fflags &= FIF_PROMISC_IN_BSS |
3539 FIF_ALLMULTI |
3540 FIF_FCSFAIL |
3541 FIF_PLCPFAIL |
3542 FIF_CONTROL |
3543 FIF_OTHER_BSS |
3544 FIF_BCN_PRBRESP_PROMISC;
3545
3546 changed &= FIF_PROMISC_IN_BSS |
3547 FIF_ALLMULTI |
3548 FIF_FCSFAIL |
3549 FIF_PLCPFAIL |
3550 FIF_CONTROL |
3551 FIF_OTHER_BSS |
3552 FIF_BCN_PRBRESP_PROMISC;
3553
3554 wl->filter_flags = *fflags;
3555
3556 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3557 b43_adjust_opmode(dev);
e4d6b795
MB		 3558 spin_unlock_irqrestore(&wl->irq_lock, flags);
3559}
3560
40faacc4 3561static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3562 struct ieee80211_vif *vif,
40faacc4 3563 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3564{
3565 struct b43_wl *wl = hw_to_b43_wl(hw);
3566 struct b43_wldev *dev = wl->current_dev;
3567 unsigned long flags;
3568
3569 if (!dev)
3570 return -ENODEV;
3571 mutex_lock(&wl->mutex);
3572 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3573 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3574 if (conf->bssid)
3575 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3576 else
3577 memset(wl->bssid, 0, ETH_ALEN);
3578 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
05c914fe
JB		 3579 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3580 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
9d139c81
JB		 3581 B43_WARN_ON(vif->type != wl->if_type);
3582 if (conf->changed & IEEE80211_IFCC_SSID)
3583 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3584 if (conf->changed & IEEE80211_IFCC_BEACON)
3585 b43_update_templates(wl);
05c914fe 3586 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 3587 if (conf->changed & IEEE80211_IFCC_BEACON)
3588 b43_update_templates(wl);
e4d6b795 3589 }
4150c572 3590 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3591 }
3592 spin_unlock_irqrestore(&wl->irq_lock, flags);
3593 mutex_unlock(&wl->mutex);
3594
3595 return 0;
3596}
3597
3598/* Locking: wl->mutex */
3599static void b43_wireless_core_stop(struct b43_wldev *dev)
3600{
3601 struct b43_wl *wl = dev->wl;
3602 unsigned long flags;
3603
3604 if (b43_status(dev) < B43_STAT_STARTED)
3605 return;
a19d12d7
SB		 3606
3607 /* Disable and sync interrupts. We must do this before than
3608 * setting the status to INITIALIZED, as the interrupt handler
3609 * won't care about IRQs then. */
3610 spin_lock_irqsave(&wl->irq_lock, flags);
3611 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3612 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3613 spin_unlock_irqrestore(&wl->irq_lock, flags);
3614 b43_synchronize_irq(dev);
3615
21a75d77 3616 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3617 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3618 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3619
5100d5ac 3620 b43_pio_stop(dev);
e4d6b795
MB		 3621 mutex_unlock(&wl->mutex);
3622 /* Must unlock as it would otherwise deadlock. No races here.
3623 * Cancel the possibly running self-rearming periodic work. */
3624 cancel_delayed_work_sync(&dev->periodic_work);
3625 mutex_lock(&wl->mutex);
3626
e4d6b795
MB		 3627 b43_mac_suspend(dev);
3628 free_irq(dev->dev->irq, dev);
3629 b43dbg(wl, "Wireless interface stopped\n");
3630}
3631
3632/* Locking: wl->mutex */
3633static int b43_wireless_core_start(struct b43_wldev *dev)
3634{
3635 int err;
3636
3637 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3638
3639 drain_txstatus_queue(dev);
3640 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3641 IRQF_SHARED, KBUILD_MODNAME, dev);
3642 if (err) {
3643 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3644 goto out;
3645 }
3646
3647 /* We are ready to run. */
3648 b43_set_status(dev, B43_STAT_STARTED);
3649
3650 /* Start data flow (TX/RX). */
3651 b43_mac_enable(dev);
3652 b43_interrupt_enable(dev, dev->irq_savedstate);
e4d6b795
MB		 3653
3654 /* Start maintainance work */
3655 b43_periodic_tasks_setup(dev);
3656
3657 b43dbg(dev->wl, "Wireless interface started\n");
3658 out:
3659 return err;
3660}
3661
3662/* Get PHY and RADIO versioning numbers */
3663static int b43_phy_versioning(struct b43_wldev *dev)
3664{
3665 struct b43_phy *phy = &dev->phy;
3666 u32 tmp;
3667 u8 analog_type;
3668 u8 phy_type;
3669 u8 phy_rev;
3670 u16 radio_manuf;
3671 u16 radio_ver;
3672 u16 radio_rev;
3673 int unsupported = 0;
3674
3675 /* Get PHY versioning */
3676 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3677 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3678 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3679 phy_rev = (tmp & B43_PHYVER_VERSION);
3680 switch (phy_type) {
3681 case B43_PHYTYPE_A:
3682 if (phy_rev >= 4)
3683 unsupported = 1;
3684 break;
3685 case B43_PHYTYPE_B:
3686 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3687 && phy_rev != 7)
3688 unsupported = 1;
3689 break;
3690 case B43_PHYTYPE_G:
013978b6 3691 if (phy_rev > 9)
e4d6b795
MB		 3692 unsupported = 1;
3693 break;
d5c71e46
MB		 3694#ifdef CONFIG_B43_NPHY
3695 case B43_PHYTYPE_N:
3696 if (phy_rev > 1)
3697 unsupported = 1;
3698 break;
3699#endif
e4d6b795
MB		 3700 default:
3701 unsupported = 1;
3702 };
3703 if (unsupported) {
3704 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3705 "(Analog %u, Type %u, Revision %u)\n",
3706 analog_type, phy_type, phy_rev);
3707 return -EOPNOTSUPP;
3708 }
3709 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3710 analog_type, phy_type, phy_rev);
3711
3712 /* Get RADIO versioning */
3713 if (dev->dev->bus->chip_id == 0x4317) {
3714 if (dev->dev->bus->chip_rev == 0)
3715 tmp = 0x3205017F;
3716 else if (dev->dev->bus->chip_rev == 1)
3717 tmp = 0x4205017F;
3718 else
3719 tmp = 0x5205017F;
3720 } else {
3721 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3722 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3723 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3724 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3725 }
3726 radio_manuf = (tmp & 0x00000FFF);
3727 radio_ver = (tmp & 0x0FFFF000) >> 12;
3728 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3729 if (radio_manuf != 0x17F /* Broadcom */)
3730 unsupported = 1;
e4d6b795
MB		 3731 switch (phy_type) {
3732 case B43_PHYTYPE_A:
3733 if (radio_ver != 0x2060)
3734 unsupported = 1;
3735 if (radio_rev != 1)
3736 unsupported = 1;
3737 if (radio_manuf != 0x17F)
3738 unsupported = 1;
3739 break;
3740 case B43_PHYTYPE_B:
3741 if ((radio_ver & 0xFFF0) != 0x2050)
3742 unsupported = 1;
3743 break;
3744 case B43_PHYTYPE_G:
3745 if (radio_ver != 0x2050)
3746 unsupported = 1;
3747 break;
96c755a3 3748 case B43_PHYTYPE_N:
243dcfcc 3749 if (radio_ver != 0x2055)
96c755a3
MB		 3750 unsupported = 1;
3751 break;
e4d6b795
MB		 3752 default:
3753 B43_WARN_ON(1);
3754 }
3755 if (unsupported) {
3756 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3757 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3758 radio_manuf, radio_ver, radio_rev);
3759 return -EOPNOTSUPP;
3760 }
3761 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3762 radio_manuf, radio_ver, radio_rev);
3763
3764 phy->radio_manuf = radio_manuf;
3765 phy->radio_ver = radio_ver;
3766 phy->radio_rev = radio_rev;
3767
3768 phy->analog = analog_type;
3769 phy->type = phy_type;
3770 phy->rev = phy_rev;
3771
3772 return 0;
3773}
3774
3775static void setup_struct_phy_for_init(struct b43_wldev *dev,
3776 struct b43_phy *phy)
3777{
e4d6b795 3778 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3779 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3780 /* PHY TX errors counter. */
3781 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
e4d6b795
MB		 3782}
3783
3784static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3785{
aa6c7ae2
MB		 3786 dev->dfq_valid = 0;
3787
6a724d68
MB		 3788 /* Assume the radio is enabled. If it's not enabled, the state will
3789 * immediately get fixed on the first periodic work run. */
3790 dev->radio_hw_enable = 1;
e4d6b795
MB		 3791
3792 /* Stats */
3793 memset(&dev->stats, 0, sizeof(dev->stats));
3794
3795 setup_struct_phy_for_init(dev, &dev->phy);
3796
3797 /* IRQ related flags */
3798 dev->irq_reason = 0;
3799 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3800 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3801
3802 dev->mac_suspended = 1;
3803
3804 /* Noise calculation context */
3805 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3806}
3807
3808static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3809{
3810 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 3811 u64 hf;
e4d6b795 3812
1855ba78
MB		 3813 if (!modparam_btcoex)
3814 return;
95de2841 3815 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3816 return;
3817 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3818 return;
3819
3820 hf = b43_hf_read(dev);
95de2841 3821 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3822 hf |= B43_HF_BTCOEXALT;
3823 else
3824 hf |= B43_HF_BTCOEX;
3825 b43_hf_write(dev, hf);
e4d6b795
MB		 3826}
3827
3828static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 3829{
3830 if (!modparam_btcoex)
3831 return;
3832 //TODO
e4d6b795
MB		 3833}
3834
3835static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3836{
3837#ifdef CONFIG_SSB_DRIVER_PCICORE
3838 struct ssb_bus *bus = dev->dev->bus;
3839 u32 tmp;
3840
3841 if (bus->pcicore.dev &&
3842 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3843 bus->pcicore.dev->id.revision <= 5) {
3844 /* IMCFGLO timeouts workaround. */
3845 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3846 tmp &= ~SSB_IMCFGLO_REQTO;
3847 tmp &= ~SSB_IMCFGLO_SERTO;
3848 switch (bus->bustype) {
3849 case SSB_BUSTYPE_PCI:
3850 case SSB_BUSTYPE_PCMCIA:
3851 tmp |= 0x32;
3852 break;
3853 case SSB_BUSTYPE_SSB:
3854 tmp |= 0x53;
3855 break;
3856 }
3857 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3858 }
3859#endif /* CONFIG_SSB_DRIVER_PCICORE */
3860}
3861
74cfdba7
MB		 3862/* Write the short and long frame retry limit values. */
3863static void b43_set_retry_limits(struct b43_wldev *dev,
3864 unsigned int short_retry,
3865 unsigned int long_retry)
3866{
3867 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3868 * the chip-internal counter. */
3869 short_retry = min(short_retry, (unsigned int)0xF);
3870 long_retry = min(long_retry, (unsigned int)0xF);
3871
3872 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3873 short_retry);
3874 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3875 long_retry);
3876}
3877
d59f720d
MB		 3878static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3879{
3880 u16 pu_delay;
3881
3882 /* The time value is in microseconds. */
3883 if (dev->phy.type == B43_PHYTYPE_A)
3884 pu_delay = 3700;
3885 else
3886 pu_delay = 1050;
05c914fe 3887 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 3888 pu_delay = 500;
3889 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3890 pu_delay = max(pu_delay, (u16)2400);
3891
3892 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3893}
3894
3895/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3896static void b43_set_pretbtt(struct b43_wldev *dev)
3897{
3898 u16 pretbtt;
3899
3900 /* The time value is in microseconds. */
05c914fe 3901 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 3902 pretbtt = 2;
3903 } else {
3904 if (dev->phy.type == B43_PHYTYPE_A)
3905 pretbtt = 120;
3906 else
3907 pretbtt = 250;
3908 }
3909 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3910 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3911}
3912
e4d6b795
MB		 3913/* Shutdown a wireless core */
3914/* Locking: wl->mutex */
3915static void b43_wireless_core_exit(struct b43_wldev *dev)
3916{
1f7d87b0 3917 u32 macctl;
e4d6b795
MB		 3918
3919 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3920 if (b43_status(dev) != B43_STAT_INITIALIZED)
3921 return;
3922 b43_set_status(dev, B43_STAT_UNINIT);
3923
1f7d87b0
MB		 3924 /* Stop the microcode PSM. */
3925 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3926 macctl &= ~B43_MACCTL_PSM_RUN;
3927 macctl |= B43_MACCTL_PSM_JMP0;
3928 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3929
3506e0c4
RW		 3930 if (!dev->suspend_in_progress) {
3931 b43_leds_exit(dev);
b844eba2 3932 b43_rng_exit(dev->wl);
3506e0c4 3933 }
e4d6b795 3934 b43_dma_free(dev);
5100d5ac 3935 b43_pio_free(dev);
e4d6b795 3936 b43_chip_exit(dev);
cb24f57f 3937 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 3938 if (dev->wl->current_beacon) {
3939 dev_kfree_skb_any(dev->wl->current_beacon);
3940 dev->wl->current_beacon = NULL;
3941 }
3942
e4d6b795
MB		 3943 ssb_device_disable(dev->dev, 0);
3944 ssb_bus_may_powerdown(dev->dev->bus);
3945}
3946
3947/* Initialize a wireless core */
3948static int b43_wireless_core_init(struct b43_wldev *dev)
3949{
3950 struct b43_wl *wl = dev->wl;
3951 struct ssb_bus *bus = dev->dev->bus;
3952 struct ssb_sprom *sprom = &bus->sprom;
3953 struct b43_phy *phy = &dev->phy;
3954 int err;
a259d6a4
MB		 3955 u64 hf;
3956 u32 tmp;
e4d6b795
MB		 3957
3958 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3959
3960 err = ssb_bus_powerup(bus, 0);
3961 if (err)
3962 goto out;
3963 if (!ssb_device_is_enabled(dev->dev)) {
3964 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3965 b43_wireless_core_reset(dev, tmp);
3966 }
3967
fb11137a 3968 /* Reset all data structures. */
e4d6b795 3969 setup_struct_wldev_for_init(dev);
fb11137a 3970 phy->ops->prepare_structs(dev);
e4d6b795
MB		 3971
3972 /* Enable IRQ routing to this device. */
3973 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3974
3975 b43_imcfglo_timeouts_workaround(dev);
3976 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 3977 if (phy->ops->prepare_hardware) {
3978 err = phy->ops->prepare_hardware(dev);
ef1a628d 3979 if (err)
fb11137a 3980 goto err_busdown;
ef1a628d 3981 }
e4d6b795
MB		 3982 err = b43_chip_init(dev);
3983 if (err)
fb11137a 3984 goto err_busdown;
e4d6b795
MB		 3985 b43_shm_write16(dev, B43_SHM_SHARED,
3986 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3987 hf = b43_hf_read(dev);
3988 if (phy->type == B43_PHYTYPE_G) {
3989 hf |= B43_HF_SYMW;
3990 if (phy->rev == 1)
3991 hf |= B43_HF_GDCW;
95de2841 3992 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3993 hf |= B43_HF_OFDMPABOOST;
3994 } else if (phy->type == B43_PHYTYPE_B) {
3995 hf |= B43_HF_SYMW;
3996 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3997 hf &= ~B43_HF_GDCW;
3998 }
3999 b43_hf_write(dev, hf);
4000
74cfdba7
MB		 4001 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4002 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4003 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4004 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4005
4006 /* Disable sending probe responses from firmware.
4007 * Setting the MaxTime to one usec will always trigger
4008 * a timeout, so we never send any probe resp.
4009 * A timeout of zero is infinite. */
4010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4011
4012 b43_rate_memory_init(dev);
5042c507 4013 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4014
4015 /* Minimum Contention Window */
4016 if (phy->type == B43_PHYTYPE_B) {
4017 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4018 } else {
4019 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4020 }
4021 /* Maximum Contention Window */
4022 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4023
5100d5ac
MB		 4024 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4025 dev->__using_pio_transfers = 1;
4026 err = b43_pio_init(dev);
4027 } else {
4028 dev->__using_pio_transfers = 0;
4029 err = b43_dma_init(dev);
4030 }
e4d6b795
MB		 4031 if (err)
4032 goto err_chip_exit;
03b29773 4033 b43_qos_init(dev);
d59f720d 4034 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4035 b43_bluetooth_coext_enable(dev);
4036
4037 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 4038 b43_upload_card_macaddress(dev);
e4d6b795 4039 b43_security_init(dev);
3506e0c4
RW		 4040 if (!dev->suspend_in_progress)
4041 b43_rng_init(wl);
e4d6b795
MB		 4042
4043 b43_set_status(dev, B43_STAT_INITIALIZED);
4044
3506e0c4
RW		 4045 if (!dev->suspend_in_progress)
4046 b43_leds_init(dev);
1a8d1227 4047out:
e4d6b795
MB		 4048 return err;
4049
ef1a628d 4050err_chip_exit:
e4d6b795 4051 b43_chip_exit(dev);
ef1a628d 4052err_busdown:
e4d6b795
MB		 4053 ssb_bus_may_powerdown(bus);
4054 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4055 return err;
4056}
4057
40faacc4
MB		 4058static int b43_op_add_interface(struct ieee80211_hw *hw,
4059 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4060{
4061 struct b43_wl *wl = hw_to_b43_wl(hw);
4062 struct b43_wldev *dev;
4063 unsigned long flags;
4064 int err = -EOPNOTSUPP;
4150c572
JB		 4065
4066 /* TODO: allow WDS/AP devices to coexist */
4067
05c914fe
JB		 4068 if (conf->type != NL80211_IFTYPE_AP &&
4069 conf->type != NL80211_IFTYPE_MESH_POINT &&
4070 conf->type != NL80211_IFTYPE_STATION &&
4071 conf->type != NL80211_IFTYPE_WDS &&
4072 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4073 return -EOPNOTSUPP;
e4d6b795
MB		 4074
4075 mutex_lock(&wl->mutex);
4150c572 4076 if (wl->operating)
e4d6b795
MB		 4077 goto out_mutex_unlock;
4078
4079 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4080
4081 dev = wl->current_dev;
4150c572 4082 wl->operating = 1;
32bfd35d 4083 wl->vif = conf->vif;
4150c572
JB		 4084 wl->if_type = conf->type;
4085 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4086
4087 spin_lock_irqsave(&wl->irq_lock, flags);
4088 b43_adjust_opmode(dev);
d59f720d
MB		 4089 b43_set_pretbtt(dev);
4090 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4091 b43_upload_card_macaddress(dev);
4092 spin_unlock_irqrestore(&wl->irq_lock, flags);
4093
4094 err = 0;
4095 out_mutex_unlock:
4096 mutex_unlock(&wl->mutex);
4097
4098 return err;
4099}
4100
40faacc4
MB		 4101static void b43_op_remove_interface(struct ieee80211_hw *hw,
4102 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4103{
4104 struct b43_wl *wl = hw_to_b43_wl(hw);
4105 struct b43_wldev *dev = wl->current_dev;
4106 unsigned long flags;
4107
4108 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4109
4110 mutex_lock(&wl->mutex);
4111
4112 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4113 B43_WARN_ON(wl->vif != conf->vif);
4114 wl->vif = NULL;
4150c572
JB		 4115
4116 wl->operating = 0;
4117
4118 spin_lock_irqsave(&wl->irq_lock, flags);
4119 b43_adjust_opmode(dev);
4120 memset(wl->mac_addr, 0, ETH_ALEN);
4121 b43_upload_card_macaddress(dev);
4122 spin_unlock_irqrestore(&wl->irq_lock, flags);
4123
4124 mutex_unlock(&wl->mutex);
4125}
4126
40faacc4 4127static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4128{
4129 struct b43_wl *wl = hw_to_b43_wl(hw);
4130 struct b43_wldev *dev = wl->current_dev;
4131 int did_init = 0;
923403b8 4132 int err = 0;
1946a2c3 4133 bool do_rfkill_exit = 0;
4150c572 4134
7be1bb6b
MB		 4135 /* Kill all old instance specific information to make sure
4136 * the card won't use it in the short timeframe between start
4137 * and mac80211 reconfiguring it. */
4138 memset(wl->bssid, 0, ETH_ALEN);
4139 memset(wl->mac_addr, 0, ETH_ALEN);
4140 wl->filter_flags = 0;
4141 wl->radiotap_enabled = 0;
e6f5b934 4142 b43_qos_clear(wl);
6b4bec01
MB		 4143 wl->beacon0_uploaded = 0;
4144 wl->beacon1_uploaded = 0;
4145 wl->beacon_templates_virgin = 1;
7be1bb6b 4146
1a8d1227
LF		 4147 /* First register RFkill.
4148 * LEDs that are registered later depend on it. */
4149 b43_rfkill_init(dev);
4150
4150c572
JB		 4151 mutex_lock(&wl->mutex);
4152
e4d6b795
MB		 4153 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4154 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4155 if (err) {
4156 do_rfkill_exit = 1;
e4d6b795 4157 goto out_mutex_unlock;
1946a2c3 4158 }
e4d6b795
MB		 4159 did_init = 1;
4160 }
4150c572 4161
e4d6b795
MB		 4162 if (b43_status(dev) < B43_STAT_STARTED) {
4163 err = b43_wireless_core_start(dev);
4164 if (err) {
4165 if (did_init)
4166 b43_wireless_core_exit(dev);
1946a2c3 4167 do_rfkill_exit = 1;
e4d6b795
MB		 4168 goto out_mutex_unlock;
4169 }
4170 }
4171
4150c572 4172 out_mutex_unlock:
e4d6b795
MB		 4173 mutex_unlock(&wl->mutex);
4174
1946a2c3
MB		 4175 if (do_rfkill_exit)
4176 b43_rfkill_exit(dev);
4177
e4d6b795
MB		 4178 return err;
4179}
4180
40faacc4 4181static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4182{
4183 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4184 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4185
1a8d1227 4186 b43_rfkill_exit(dev);
a82d9922 4187 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4188
e4d6b795 4189 mutex_lock(&wl->mutex);
4150c572
JB		 4190 if (b43_status(dev) >= B43_STAT_STARTED)
4191 b43_wireless_core_stop(dev);
4192 b43_wireless_core_exit(dev);
e4d6b795 4193 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4194
4195 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4196}
4197
74cfdba7
MB		 4198static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4199 u32 short_retry_limit, u32 long_retry_limit)
4200{
4201 struct b43_wl *wl = hw_to_b43_wl(hw);
4202 struct b43_wldev *dev;
4203 int err = 0;
4204
4205 mutex_lock(&wl->mutex);
4206 dev = wl->current_dev;
4207 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4208 err = -ENODEV;
4209 goto out_unlock;
4210 }
4211 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4212out_unlock:
4213 mutex_unlock(&wl->mutex);
4214
4215 return err;
4216}
4217
17741cdc
JB		 4218static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4219 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4220{
4221 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4222 unsigned long flags;
e66fee6a 4223
d4df6f1a 4224 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4225 b43_update_templates(wl);
d4df6f1a 4226 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4227
4228 return 0;
4229}
4230
38968d09
JB		 4231static void b43_op_sta_notify(struct ieee80211_hw *hw,
4232 struct ieee80211_vif *vif,
4233 enum sta_notify_cmd notify_cmd,
17741cdc 4234 struct ieee80211_sta *sta)
38968d09
JB		 4235{
4236 struct b43_wl *wl = hw_to_b43_wl(hw);
4237
4238 B43_WARN_ON(!vif || wl->vif != vif);
4239}
4240
e4d6b795 4241static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4242 .tx = b43_op_tx,
4243 .conf_tx = b43_op_conf_tx,
4244 .add_interface = b43_op_add_interface,
4245 .remove_interface = b43_op_remove_interface,
4246 .config = b43_op_config,
4247 .config_interface = b43_op_config_interface,
4248 .configure_filter = b43_op_configure_filter,
4249 .set_key = b43_op_set_key,
4250 .get_stats = b43_op_get_stats,
4251 .get_tx_stats = b43_op_get_tx_stats,
4252 .start = b43_op_start,
4253 .stop = b43_op_stop,
74cfdba7 4254 .set_retry_limit = b43_op_set_retry_limit,
e66fee6a 4255 .set_tim = b43_op_beacon_set_tim,
38968d09 4256 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4257};
4258
4259/* Hard-reset the chip. Do not call this directly.
4260 * Use b43_controller_restart()
4261 */
4262static void b43_chip_reset(struct work_struct *work)
4263{
4264 struct b43_wldev *dev =
4265 container_of(work, struct b43_wldev, restart_work);
4266 struct b43_wl *wl = dev->wl;
4267 int err = 0;
4268 int prev_status;
4269
4270 mutex_lock(&wl->mutex);
4271
4272 prev_status = b43_status(dev);
4273 /* Bring the device down... */
4274 if (prev_status >= B43_STAT_STARTED)
4275 b43_wireless_core_stop(dev);
4276 if (prev_status >= B43_STAT_INITIALIZED)
4277 b43_wireless_core_exit(dev);
4278
4279 /* ...and up again. */
4280 if (prev_status >= B43_STAT_INITIALIZED) {
4281 err = b43_wireless_core_init(dev);
4282 if (err)
4283 goto out;
4284 }
4285 if (prev_status >= B43_STAT_STARTED) {
4286 err = b43_wireless_core_start(dev);
4287 if (err) {
4288 b43_wireless_core_exit(dev);
4289 goto out;
4290 }
4291 }
3bf0a32e
MB		 4292out:
4293 if (err)
4294 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4295 mutex_unlock(&wl->mutex);
4296 if (err)
4297 b43err(wl, "Controller restart FAILED\n");
4298 else
4299 b43info(wl, "Controller restarted\n");
4300}
4301
bb1eeff1 4302static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4303 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4304{
4305 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4306
bb1eeff1
MB		 4307 if (have_2ghz_phy)
4308 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4309 if (dev->phy.type == B43_PHYTYPE_N) {
4310 if (have_5ghz_phy)
4311 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4312 } else {
4313 if (have_5ghz_phy)
4314 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4315 }
96c755a3 4316
bb1eeff1
MB		 4317 dev->phy.supports_2ghz = have_2ghz_phy;
4318 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4319
4320 return 0;
4321}
4322
4323static void b43_wireless_core_detach(struct b43_wldev *dev)
4324{
4325 /* We release firmware that late to not be required to re-request
4326 * is all the time when we reinit the core. */
4327 b43_release_firmware(dev);
fb11137a 4328 b43_phy_free(dev);
e4d6b795
MB		 4329}
4330
4331static int b43_wireless_core_attach(struct b43_wldev *dev)
4332{
4333 struct b43_wl *wl = dev->wl;
4334 struct ssb_bus *bus = dev->dev->bus;
4335 struct pci_dev *pdev = bus->host_pci;
4336 int err;
96c755a3 4337 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4338 u32 tmp;
4339
4340 /* Do NOT do any device initialization here.
4341 * Do it in wireless_core_init() instead.
4342 * This function is for gathering basic information about the HW, only.
4343 * Also some structs may be set up here. But most likely you want to have
4344 * that in core_init(), too.
4345 */
4346
4347 err = ssb_bus_powerup(bus, 0);
4348 if (err) {
4349 b43err(wl, "Bus powerup failed\n");
4350 goto out;
4351 }
4352 /* Get the PHY type. */
4353 if (dev->dev->id.revision >= 5) {
4354 u32 tmshigh;
4355
4356 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4357 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4358 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4359 } else
96c755a3 4360 B43_WARN_ON(1);
e4d6b795 4361
96c755a3 4362 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4363 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4364 b43_wireless_core_reset(dev, tmp);
4365
4366 err = b43_phy_versioning(dev);
4367 if (err)
21954c36 4368 goto err_powerdown;
e4d6b795
MB		 4369 /* Check if this device supports multiband. */
4370 if (!pdev ||
4371 (pdev->device != 0x4312 &&
4372 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4373 /* No multiband support. */
96c755a3
MB		 4374 have_2ghz_phy = 0;
4375 have_5ghz_phy = 0;
e4d6b795
MB		 4376 switch (dev->phy.type) {
4377 case B43_PHYTYPE_A:
96c755a3 4378 have_5ghz_phy = 1;
e4d6b795
MB		 4379 break;
4380 case B43_PHYTYPE_G:
96c755a3
MB		 4381 case B43_PHYTYPE_N:
4382 have_2ghz_phy = 1;
e4d6b795
MB		 4383 break;
4384 default:
4385 B43_WARN_ON(1);
4386 }
4387 }
96c755a3
MB		 4388 if (dev->phy.type == B43_PHYTYPE_A) {
4389 /* FIXME */
4390 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4391 err = -EOPNOTSUPP;
4392 goto err_powerdown;
4393 }
2e35af14
MB		 4394 if (1 /* disable A-PHY */) {
4395 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4396 if (dev->phy.type != B43_PHYTYPE_N) {
4397 have_2ghz_phy = 1;
4398 have_5ghz_phy = 0;
4399 }
4400 }
4401
fb11137a
MB		 4402 err = b43_phy_allocate(dev);
4403 if (err)
4404 goto err_powerdown;
4405
96c755a3 4406 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4407 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4408 b43_wireless_core_reset(dev, tmp);
4409
4410 err = b43_validate_chipaccess(dev);
4411 if (err)
fb11137a 4412 goto err_phy_free;
bb1eeff1 4413 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4414 if (err)
fb11137a 4415 goto err_phy_free;
e4d6b795
MB		 4416
4417 /* Now set some default "current_dev" */
4418 if (!wl->current_dev)
4419 wl->current_dev = dev;
4420 INIT_WORK(&dev->restart_work, b43_chip_reset);
4421
cb24f57f 4422 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4423 ssb_device_disable(dev->dev, 0);
4424 ssb_bus_may_powerdown(bus);
4425
4426out:
4427 return err;
4428
fb11137a
MB		 4429err_phy_free:
4430 b43_phy_free(dev);
e4d6b795
MB		 4431err_powerdown:
4432 ssb_bus_may_powerdown(bus);
4433 return err;
4434}
4435
4436static void b43_one_core_detach(struct ssb_device *dev)
4437{
4438 struct b43_wldev *wldev;
4439 struct b43_wl *wl;
4440
3bf0a32e
MB		 4441 /* Do not cancel ieee80211-workqueue based work here.
4442 * See comment in b43_remove(). */
4443
e4d6b795
MB		 4444 wldev = ssb_get_drvdata(dev);
4445 wl = wldev->wl;
e4d6b795
MB		 4446 b43_debugfs_remove_device(wldev);
4447 b43_wireless_core_detach(wldev);
4448 list_del(&wldev->list);
4449 wl->nr_devs--;
4450 ssb_set_drvdata(dev, NULL);
4451 kfree(wldev);
4452}
4453
4454static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4455{
4456 struct b43_wldev *wldev;
4457 struct pci_dev *pdev;
4458 int err = -ENOMEM;
4459
4460 if (!list_empty(&wl->devlist)) {
4461 /* We are not the first core on this chip. */
4462 pdev = dev->bus->host_pci;
4463 /* Only special chips support more than one wireless
4464 * core, although some of the other chips have more than
4465 * one wireless core as well. Check for this and
4466 * bail out early.
4467 */
4468 if (!pdev ||
4469 ((pdev->device != 0x4321) &&
4470 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4471 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4472 return -ENODEV;
4473 }
4474 }
4475
4476 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4477 if (!wldev)
4478 goto out;
4479
4480 wldev->dev = dev;
4481 wldev->wl = wl;
4482 b43_set_status(wldev, B43_STAT_UNINIT);
4483 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4484 tasklet_init(&wldev->isr_tasklet,
4485 (void (*)(unsigned long))b43_interrupt_tasklet,
4486 (unsigned long)wldev);
e4d6b795
MB		 4487 INIT_LIST_HEAD(&wldev->list);
4488
4489 err = b43_wireless_core_attach(wldev);
4490 if (err)
4491 goto err_kfree_wldev;
4492
4493 list_add(&wldev->list, &wl->devlist);
4494 wl->nr_devs++;
4495 ssb_set_drvdata(dev, wldev);
4496 b43_debugfs_add_device(wldev);
4497
4498 out:
4499 return err;
4500
4501 err_kfree_wldev:
4502 kfree(wldev);
4503 return err;
4504}
4505
9fc38458
MB		 4506#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4507 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4508 (pdev->device == _device) && \
4509 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4510 (pdev->subsystem_device == _subdevice) )
4511
e4d6b795
MB		 4512static void b43_sprom_fixup(struct ssb_bus *bus)
4513{
1855ba78
MB		 4514 struct pci_dev *pdev;
4515
e4d6b795
MB		 4516 /* boardflags workarounds */
4517 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4518 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4519 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4520 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4521 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4522 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4523 if (bus->bustype == SSB_BUSTYPE_PCI) {
4524 pdev = bus->host_pci;
9fc38458 4525 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4526 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4527 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4528 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4529 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4530 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4531 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4532 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4533 }
e4d6b795
MB		 4534}
4535
4536static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4537{
4538 struct ieee80211_hw *hw = wl->hw;
4539
4540 ssb_set_devtypedata(dev, NULL);
4541 ieee80211_free_hw(hw);
4542}
4543
4544static int b43_wireless_init(struct ssb_device *dev)
4545{
4546 struct ssb_sprom *sprom = &dev->bus->sprom;
4547 struct ieee80211_hw *hw;
4548 struct b43_wl *wl;
4549 int err = -ENOMEM;
4550
4551 b43_sprom_fixup(dev->bus);
4552
4553 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4554 if (!hw) {
4555 b43err(NULL, "Could not allocate ieee80211 device\n");
4556 goto out;
4557 }
4558
4559 /* fill hw info */
605a0bd6 4560 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4561 IEEE80211_HW_SIGNAL_DBM |
4562 IEEE80211_HW_NOISE_DBM;
4563
f59ac048
LR		 4564 hw->wiphy->interface_modes =
4565 BIT(NL80211_IFTYPE_AP) |
4566 BIT(NL80211_IFTYPE_MESH_POINT) |
4567 BIT(NL80211_IFTYPE_STATION) |
4568 BIT(NL80211_IFTYPE_WDS) |
4569 BIT(NL80211_IFTYPE_ADHOC);
4570
e6f5b934 4571 hw->queues = b43_modparam_qos ? 4 : 1;
870abdf6 4572 hw->max_altrates = 1;
e4d6b795 4573 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4574 if (is_valid_ether_addr(sprom->et1mac))
4575 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4576 else
95de2841 4577 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4578
4579 /* Get and initialize struct b43_wl */
4580 wl = hw_to_b43_wl(hw);
4581 memset(wl, 0, sizeof(*wl));
4582 wl->hw = hw;
4583 spin_lock_init(&wl->irq_lock);
21a75d77 4584 rwlock_init(&wl->tx_lock);
e4d6b795 4585 spin_lock_init(&wl->leds_lock);
280d0e16 4586 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4587 mutex_init(&wl->mutex);
4588 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4589 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4590 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4591
4592 ssb_set_devtypedata(dev, wl);
4593 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4594 err = 0;
4595 out:
4596 return err;
4597}
4598
4599static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4600{
4601 struct b43_wl *wl;
4602 int err;
4603 int first = 0;
4604
4605 wl = ssb_get_devtypedata(dev);
4606 if (!wl) {
4607 /* Probing the first core. Must setup common struct b43_wl */
4608 first = 1;
4609 err = b43_wireless_init(dev);
4610 if (err)
4611 goto out;
4612 wl = ssb_get_devtypedata(dev);
4613 B43_WARN_ON(!wl);
4614 }
4615 err = b43_one_core_attach(dev, wl);
4616 if (err)
4617 goto err_wireless_exit;
4618
4619 if (first) {
4620 err = ieee80211_register_hw(wl->hw);
4621 if (err)
4622 goto err_one_core_detach;
4623 }
4624
4625 out:
4626 return err;
4627
4628 err_one_core_detach:
4629 b43_one_core_detach(dev);
4630 err_wireless_exit:
4631 if (first)
4632 b43_wireless_exit(dev, wl);
4633 return err;
4634}
4635
4636static void b43_remove(struct ssb_device *dev)
4637{
4638 struct b43_wl *wl = ssb_get_devtypedata(dev);
4639 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4640
3bf0a32e
MB		 4641 /* We must cancel any work here before unregistering from ieee80211,
4642 * as the ieee80211 unreg will destroy the workqueue. */
4643 cancel_work_sync(&wldev->restart_work);
4644
e4d6b795
MB		 4645 B43_WARN_ON(!wl);
4646 if (wl->current_dev == wldev)
4647 ieee80211_unregister_hw(wl->hw);
4648
4649 b43_one_core_detach(dev);
4650
4651 if (list_empty(&wl->devlist)) {
4652 /* Last core on the chip unregistered.
4653 * We can destroy common struct b43_wl.
4654 */
4655 b43_wireless_exit(dev, wl);
4656 }
4657}
4658
4659/* Perform a hardware reset. This can be called from any context. */
4660void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4661{
4662 /* Must avoid requeueing, if we are in shutdown. */
4663 if (b43_status(dev) < B43_STAT_INITIALIZED)
4664 return;
4665 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4666 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4667}
4668
4669#ifdef CONFIG_PM
4670
4671static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4672{
4673 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4674 struct b43_wl *wl = wldev->wl;
4675
4676 b43dbg(wl, "Suspending...\n");
4677
4678 mutex_lock(&wl->mutex);
3506e0c4 4679 wldev->suspend_in_progress = true;
e4d6b795
MB		 4680 wldev->suspend_init_status = b43_status(wldev);
4681 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4682 b43_wireless_core_stop(wldev);
4683 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4684 b43_wireless_core_exit(wldev);
4685 mutex_unlock(&wl->mutex);
4686
4687 b43dbg(wl, "Device suspended.\n");
4688
4689 return 0;
4690}
4691
4692static int b43_resume(struct ssb_device *dev)
4693{
4694 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4695 struct b43_wl *wl = wldev->wl;
4696 int err = 0;
4697
4698 b43dbg(wl, "Resuming...\n");
4699
4700 mutex_lock(&wl->mutex);
4701 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4702 err = b43_wireless_core_init(wldev);
4703 if (err) {
4704 b43err(wl, "Resume failed at core init\n");
4705 goto out;
4706 }
4707 }
4708 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4709 err = b43_wireless_core_start(wldev);
4710 if (err) {
3506e0c4 4711 b43_leds_exit(wldev);
b844eba2 4712 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4713 b43_wireless_core_exit(wldev);
4714 b43err(wl, "Resume failed at core start\n");
4715 goto out;
4716 }
4717 }
e4d6b795 4718 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4719 out:
4720 wldev->suspend_in_progress = false;
4721 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4722 return err;
4723}
4724
4725#else /* CONFIG_PM */
4726# define b43_suspend NULL
4727# define b43_resume NULL
4728#endif /* CONFIG_PM */
4729
4730static struct ssb_driver b43_ssb_driver = {
4731 .name = KBUILD_MODNAME,
4732 .id_table = b43_ssb_tbl,
4733 .probe = b43_probe,
4734 .remove = b43_remove,
4735 .suspend = b43_suspend,
4736 .resume = b43_resume,
4737};
4738
26bc783f
MB		 4739static void b43_print_driverinfo(void)
4740{
4741 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4742 *feat_leds = "", *feat_rfkill = "";
4743
4744#ifdef CONFIG_B43_PCI_AUTOSELECT
4745 feat_pci = "P";
4746#endif
4747#ifdef CONFIG_B43_PCMCIA
4748 feat_pcmcia = "M";
4749#endif
4750#ifdef CONFIG_B43_NPHY
4751 feat_nphy = "N";
4752#endif
4753#ifdef CONFIG_B43_LEDS
4754 feat_leds = "L";
4755#endif
4756#ifdef CONFIG_B43_RFKILL
4757 feat_rfkill = "R";
4758#endif
4759 printk(KERN_INFO "Broadcom 43xx driver loaded "
4760 "[ Features: %s%s%s%s%s, Firmware-ID: "
4761 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4762 feat_pci, feat_pcmcia, feat_nphy,
4763 feat_leds, feat_rfkill);
4764}
4765
e4d6b795
MB		 4766static int __init b43_init(void)
4767{
4768 int err;
4769
4770 b43_debugfs_init();
4771 err = b43_pcmcia_init();
4772 if (err)
4773 goto err_dfs_exit;
4774 err = ssb_driver_register(&b43_ssb_driver);
4775 if (err)
4776 goto err_pcmcia_exit;
26bc783f 4777 b43_print_driverinfo();
e4d6b795
MB		 4778
4779 return err;
4780
4781err_pcmcia_exit:
4782 b43_pcmcia_exit();
4783err_dfs_exit:
4784 b43_debugfs_exit();
4785 return err;
4786}
4787
4788static void __exit b43_exit(void)
4789{
4790 ssb_driver_unregister(&b43_ssb_driver);
4791 b43_pcmcia_exit();
4792 b43_debugfs_exit();
4793}
4794
4795module_init(b43_init)
4796module_exit(b43_exit)
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