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ssb: Disable verbose SDIO coreswitch
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
0136e51e 61MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 62MODULE_LICENSE("GPL");
63
9c7d99d6
MB		 64MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
65
e4d6b795
MB		 66
67static int modparam_bad_frames_preempt;
68module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
69MODULE_PARM_DESC(bad_frames_preempt,
70 "enable(1) / disable(0) Bad Frames Preemption");
71
e4d6b795
MB		 72static char modparam_fwpostfix[16];
73module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
74MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75
e4d6b795
MB		 76static int modparam_hwpctl;
77module_param_named(hwpctl, modparam_hwpctl, int, 0444);
78MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79
80static int modparam_nohwcrypt;
81module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
82MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83
035d0243 84static int modparam_hwtkip;
85module_param_named(hwtkip, modparam_hwtkip, int, 0444);
86MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
87
403a3a13
MB		 88static int modparam_qos = 1;
89module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 90MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
91
1855ba78
MB		 92static int modparam_btcoex = 1;
93module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 94MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 95
060210f9
MB		 96int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
97module_param_named(verbose, b43_modparam_verbose, int, 0644);
98MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
99
e6f5b934 100
e4d6b795
MB		 101static const struct ssb_device_id b43_ssb_tbl[] = {
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 111 SSB_DEVTABLE_END
112};
113
114MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
115
116/* Channel and ratetables are shared for all devices.
117 * They can't be const, because ieee80211 puts some precalculated
118 * data in there. This data is the same for all devices, so we don't
119 * get concurrency issues */
120#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 121 { \
122 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
123 .hw_value = (_rateid), \
124 .flags = (_flags), \
e4d6b795 125 }
8318d78a
JB		 126
127/*
128 * NOTE: When changing this, sync with xmit.c's
129 * b43_plcp_get_bitrate_idx_* functions!
130 */
e4d6b795 131static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 132 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
133 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 144};
145
146#define b43_a_ratetable (__b43_ratetable + 4)
147#define b43_a_ratetable_size 8
148#define b43_b_ratetable (__b43_ratetable + 0)
149#define b43_b_ratetable_size 4
150#define b43_g_ratetable (__b43_ratetable + 0)
151#define b43_g_ratetable_size 12
152
bb1eeff1
MB		 153#define CHAN4G(_channel, _freq, _flags) { \
154 .band = IEEE80211_BAND_2GHZ, \
155 .center_freq = (_freq), \
156 .hw_value = (_channel), \
157 .flags = (_flags), \
158 .max_antenna_gain = 0, \
159 .max_power = 30, \
160}
96c755a3 161static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 162 CHAN4G(1, 2412, 0),
163 CHAN4G(2, 2417, 0),
164 CHAN4G(3, 2422, 0),
165 CHAN4G(4, 2427, 0),
166 CHAN4G(5, 2432, 0),
167 CHAN4G(6, 2437, 0),
168 CHAN4G(7, 2442, 0),
169 CHAN4G(8, 2447, 0),
170 CHAN4G(9, 2452, 0),
171 CHAN4G(10, 2457, 0),
172 CHAN4G(11, 2462, 0),
173 CHAN4G(12, 2467, 0),
174 CHAN4G(13, 2472, 0),
175 CHAN4G(14, 2484, 0),
176};
177#undef CHAN4G
178
179#define CHAN5G(_channel, _flags) { \
180 .band = IEEE80211_BAND_5GHZ, \
181 .center_freq = 5000 + (5 * (_channel)), \
182 .hw_value = (_channel), \
183 .flags = (_flags), \
184 .max_antenna_gain = 0, \
185 .max_power = 30, \
186}
187static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
188 CHAN5G(32, 0), CHAN5G(34, 0),
189 CHAN5G(36, 0), CHAN5G(38, 0),
190 CHAN5G(40, 0), CHAN5G(42, 0),
191 CHAN5G(44, 0), CHAN5G(46, 0),
192 CHAN5G(48, 0), CHAN5G(50, 0),
193 CHAN5G(52, 0), CHAN5G(54, 0),
194 CHAN5G(56, 0), CHAN5G(58, 0),
195 CHAN5G(60, 0), CHAN5G(62, 0),
196 CHAN5G(64, 0), CHAN5G(66, 0),
197 CHAN5G(68, 0), CHAN5G(70, 0),
198 CHAN5G(72, 0), CHAN5G(74, 0),
199 CHAN5G(76, 0), CHAN5G(78, 0),
200 CHAN5G(80, 0), CHAN5G(82, 0),
201 CHAN5G(84, 0), CHAN5G(86, 0),
202 CHAN5G(88, 0), CHAN5G(90, 0),
203 CHAN5G(92, 0), CHAN5G(94, 0),
204 CHAN5G(96, 0), CHAN5G(98, 0),
205 CHAN5G(100, 0), CHAN5G(102, 0),
206 CHAN5G(104, 0), CHAN5G(106, 0),
207 CHAN5G(108, 0), CHAN5G(110, 0),
208 CHAN5G(112, 0), CHAN5G(114, 0),
209 CHAN5G(116, 0), CHAN5G(118, 0),
210 CHAN5G(120, 0), CHAN5G(122, 0),
211 CHAN5G(124, 0), CHAN5G(126, 0),
212 CHAN5G(128, 0), CHAN5G(130, 0),
213 CHAN5G(132, 0), CHAN5G(134, 0),
214 CHAN5G(136, 0), CHAN5G(138, 0),
215 CHAN5G(140, 0), CHAN5G(142, 0),
216 CHAN5G(144, 0), CHAN5G(145, 0),
217 CHAN5G(146, 0), CHAN5G(147, 0),
218 CHAN5G(148, 0), CHAN5G(149, 0),
219 CHAN5G(150, 0), CHAN5G(151, 0),
220 CHAN5G(152, 0), CHAN5G(153, 0),
221 CHAN5G(154, 0), CHAN5G(155, 0),
222 CHAN5G(156, 0), CHAN5G(157, 0),
223 CHAN5G(158, 0), CHAN5G(159, 0),
224 CHAN5G(160, 0), CHAN5G(161, 0),
225 CHAN5G(162, 0), CHAN5G(163, 0),
226 CHAN5G(164, 0), CHAN5G(165, 0),
227 CHAN5G(166, 0), CHAN5G(168, 0),
228 CHAN5G(170, 0), CHAN5G(172, 0),
229 CHAN5G(174, 0), CHAN5G(176, 0),
230 CHAN5G(178, 0), CHAN5G(180, 0),
231 CHAN5G(182, 0), CHAN5G(184, 0),
232 CHAN5G(186, 0), CHAN5G(188, 0),
233 CHAN5G(190, 0), CHAN5G(192, 0),
234 CHAN5G(194, 0), CHAN5G(196, 0),
235 CHAN5G(198, 0), CHAN5G(200, 0),
236 CHAN5G(202, 0), CHAN5G(204, 0),
237 CHAN5G(206, 0), CHAN5G(208, 0),
238 CHAN5G(210, 0), CHAN5G(212, 0),
239 CHAN5G(214, 0), CHAN5G(216, 0),
240 CHAN5G(218, 0), CHAN5G(220, 0),
241 CHAN5G(222, 0), CHAN5G(224, 0),
242 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 243};
244
bb1eeff1
MB		 245static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
246 CHAN5G(34, 0), CHAN5G(36, 0),
247 CHAN5G(38, 0), CHAN5G(40, 0),
248 CHAN5G(42, 0), CHAN5G(44, 0),
249 CHAN5G(46, 0), CHAN5G(48, 0),
250 CHAN5G(52, 0), CHAN5G(56, 0),
251 CHAN5G(60, 0), CHAN5G(64, 0),
252 CHAN5G(100, 0), CHAN5G(104, 0),
253 CHAN5G(108, 0), CHAN5G(112, 0),
254 CHAN5G(116, 0), CHAN5G(120, 0),
255 CHAN5G(124, 0), CHAN5G(128, 0),
256 CHAN5G(132, 0), CHAN5G(136, 0),
257 CHAN5G(140, 0), CHAN5G(149, 0),
258 CHAN5G(153, 0), CHAN5G(157, 0),
259 CHAN5G(161, 0), CHAN5G(165, 0),
260 CHAN5G(184, 0), CHAN5G(188, 0),
261 CHAN5G(192, 0), CHAN5G(196, 0),
262 CHAN5G(200, 0), CHAN5G(204, 0),
263 CHAN5G(208, 0), CHAN5G(212, 0),
264 CHAN5G(216, 0),
265};
266#undef CHAN5G
267
268static struct ieee80211_supported_band b43_band_5GHz_nphy = {
269 .band = IEEE80211_BAND_5GHZ,
270 .channels = b43_5ghz_nphy_chantable,
271 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
272 .bitrates = b43_a_ratetable,
273 .n_bitrates = b43_a_ratetable_size,
e4d6b795 274};
8318d78a 275
bb1eeff1
MB		 276static struct ieee80211_supported_band b43_band_5GHz_aphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_aphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
8318d78a 282};
e4d6b795 283
8318d78a 284static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 285 .band = IEEE80211_BAND_2GHZ,
286 .channels = b43_2ghz_chantable,
287 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
288 .bitrates = b43_g_ratetable,
289 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 290};
291
e4d6b795
MB		 292static void b43_wireless_core_exit(struct b43_wldev *dev);
293static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 294static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795
MB		 295static int b43_wireless_core_start(struct b43_wldev *dev);
296
297static int b43_ratelimit(struct b43_wl *wl)
298{
299 if (!wl || !wl->current_dev)
300 return 1;
301 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
302 return 1;
303 /* We are up and running.
304 * Ratelimit the messages to avoid DoS over the net. */
305 return net_ratelimit();
306}
307
308void b43info(struct b43_wl *wl, const char *fmt, ...)
309{
310 va_list args;
311
060210f9
MB		 312 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
313 return;
e4d6b795
MB		 314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_INFO "b43-%s: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43err(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
060210f9
MB		 327 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
328 return;
e4d6b795
MB		 329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_ERR "b43-%s ERROR: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336}
337
338void b43warn(struct b43_wl *wl, const char *fmt, ...)
339{
340 va_list args;
341
060210f9
MB		 342 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
343 return;
e4d6b795
MB		 344 if (!b43_ratelimit(wl))
345 return;
346 va_start(args, fmt);
347 printk(KERN_WARNING "b43-%s warning: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 vprintk(fmt, args);
350 va_end(args);
351}
352
e4d6b795
MB		 353void b43dbg(struct b43_wl *wl, const char *fmt, ...)
354{
355 va_list args;
356
060210f9
MB		 357 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
358 return;
e4d6b795
MB		 359 va_start(args, fmt);
360 printk(KERN_DEBUG "b43-%s debug: ",
361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
362 vprintk(fmt, args);
363 va_end(args);
364}
e4d6b795
MB		 365
366static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
367{
368 u32 macctl;
369
370 B43_WARN_ON(offset % 4 != 0);
371
372 macctl = b43_read32(dev, B43_MMIO_MACCTL);
373 if (macctl & B43_MACCTL_BE)
374 val = swab32(val);
375
376 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
377 mmiowb();
378 b43_write32(dev, B43_MMIO_RAM_DATA, val);
379}
380
280d0e16
MB		 381static inline void b43_shm_control_word(struct b43_wldev *dev,
382 u16 routing, u16 offset)
e4d6b795
MB		 383{
384 u32 control;
385
386 /* "offset" is the WORD offset. */
e4d6b795
MB		 387 control = routing;
388 control <<= 16;
389 control |= offset;
390 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
391}
392
69eddc8a 393u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 394{
395 u32 ret;
396
397 if (routing == B43_SHM_SHARED) {
398 B43_WARN_ON(offset & 0x0001);
399 if (offset & 0x0003) {
400 /* Unaligned access */
401 b43_shm_control_word(dev, routing, offset >> 2);
402 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 403 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 404 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 405
280d0e16 406 goto out;
e4d6b795
MB		 407 }
408 offset >>= 2;
409 }
410 b43_shm_control_word(dev, routing, offset);
411 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 412out:
e4d6b795
MB		 413 return ret;
414}
415
69eddc8a 416u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 417{
418 u16 ret;
419
e4d6b795
MB		 420 if (routing == B43_SHM_SHARED) {
421 B43_WARN_ON(offset & 0x0001);
422 if (offset & 0x0003) {
423 /* Unaligned access */
424 b43_shm_control_word(dev, routing, offset >> 2);
425 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
426
280d0e16 427 goto out;
e4d6b795
MB		 428 }
429 offset >>= 2;
430 }
431 b43_shm_control_word(dev, routing, offset);
432 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 433out:
e4d6b795
MB		 434 return ret;
435}
436
69eddc8a 437void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 438{
e4d6b795
MB		 439 if (routing == B43_SHM_SHARED) {
440 B43_WARN_ON(offset & 0x0001);
441 if (offset & 0x0003) {
442 /* Unaligned access */
443 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 444 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 445 value & 0xFFFF);
e4d6b795 446 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 447 b43_write16(dev, B43_MMIO_SHM_DATA,
448 (value >> 16) & 0xFFFF);
6bbc321a 449 return;
e4d6b795
MB		 450 }
451 offset >>= 2;
452 }
453 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 454 b43_write32(dev, B43_MMIO_SHM_DATA, value);
455}
456
69eddc8a 457void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 458{
e4d6b795
MB		 459 if (routing == B43_SHM_SHARED) {
460 B43_WARN_ON(offset & 0x0001);
461 if (offset & 0x0003) {
462 /* Unaligned access */
463 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 464 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 465 return;
e4d6b795
MB		 466 }
467 offset >>= 2;
468 }
469 b43_shm_control_word(dev, routing, offset);
e4d6b795 470 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 471}
472
e4d6b795 473/* Read HostFlags */
99da185a 474u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 475{
35f0d354 476 u64 ret;
e4d6b795
MB		 477
478 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
479 ret <<= 16;
35f0d354
MB		 480 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
481 ret <<= 16;
e4d6b795
MB		 482 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
483
484 return ret;
485}
486
487/* Write HostFlags */
35f0d354 488void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 489{
35f0d354
MB		 490 u16 lo, mi, hi;
491
492 lo = (value & 0x00000000FFFFULL);
493 mi = (value & 0x0000FFFF0000ULL) >> 16;
494 hi = (value & 0xFFFF00000000ULL) >> 32;
495 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
496 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 498}
499
403a3a13
MB		 500/* Read the firmware capabilities bitmask (Opensource firmware only) */
501static u16 b43_fwcapa_read(struct b43_wldev *dev)
502{
503 B43_WARN_ON(!dev->fw.opensource);
504 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
505}
506
3ebbbb56 507void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 508{
3ebbbb56
MB		 509 u32 low, high;
510
511 B43_WARN_ON(dev->dev->id.revision < 3);
512
513 /* The hardware guarantees us an atomic read, if we
514 * read the low register first. */
515 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
516 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
517
518 *tsf = high;
519 *tsf <<= 32;
520 *tsf |= low;
e4d6b795
MB		 521}
522
523static void b43_time_lock(struct b43_wldev *dev)
524{
525 u32 macctl;
526
527 macctl = b43_read32(dev, B43_MMIO_MACCTL);
528 macctl |= B43_MACCTL_TBTTHOLD;
529 b43_write32(dev, B43_MMIO_MACCTL, macctl);
530 /* Commit the write */
531 b43_read32(dev, B43_MMIO_MACCTL);
532}
533
534static void b43_time_unlock(struct b43_wldev *dev)
535{
536 u32 macctl;
537
538 macctl = b43_read32(dev, B43_MMIO_MACCTL);
539 macctl &= ~B43_MACCTL_TBTTHOLD;
540 b43_write32(dev, B43_MMIO_MACCTL, macctl);
541 /* Commit the write */
542 b43_read32(dev, B43_MMIO_MACCTL);
543}
544
545static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
546{
3ebbbb56
MB		 547 u32 low, high;
548
549 B43_WARN_ON(dev->dev->id.revision < 3);
550
551 low = tsf;
552 high = (tsf >> 32);
553 /* The hardware guarantees us an atomic write, if we
554 * write the low register first. */
555 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
556 mmiowb();
557 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
558 mmiowb();
e4d6b795
MB		 559}
560
561void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
562{
563 b43_time_lock(dev);
564 b43_tsf_write_locked(dev, tsf);
565 b43_time_unlock(dev);
566}
567
568static
99da185a 569void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 570{
571 static const u8 zero_addr[ETH_ALEN] = { 0 };
572 u16 data;
573
574 if (!mac)
575 mac = zero_addr;
576
577 offset |= 0x0020;
578 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
579
580 data = mac[0];
581 data |= mac[1] << 8;
582 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
583 data = mac[2];
584 data |= mac[3] << 8;
585 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
586 data = mac[4];
587 data |= mac[5] << 8;
588 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
589}
590
591static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
592{
593 const u8 *mac;
594 const u8 *bssid;
595 u8 mac_bssid[ETH_ALEN * 2];
596 int i;
597 u32 tmp;
598
599 bssid = dev->wl->bssid;
600 mac = dev->wl->mac_addr;
601
602 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
603
604 memcpy(mac_bssid, mac, ETH_ALEN);
605 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
606
607 /* Write our MAC address and BSSID to template ram */
608 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
609 tmp = (u32) (mac_bssid[i + 0]);
610 tmp |= (u32) (mac_bssid[i + 1]) << 8;
611 tmp |= (u32) (mac_bssid[i + 2]) << 16;
612 tmp |= (u32) (mac_bssid[i + 3]) << 24;
613 b43_ram_write(dev, 0x20 + i, tmp);
614 }
615}
616
4150c572 617static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 618{
e4d6b795 619 b43_write_mac_bssid_templates(dev);
4150c572 620 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 621}
622
623static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
624{
625 /* slot_time is in usec. */
626 if (dev->phy.type != B43_PHYTYPE_G)
627 return;
628 b43_write16(dev, 0x684, 510 + slot_time);
629 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
630}
631
632static void b43_short_slot_timing_enable(struct b43_wldev *dev)
633{
634 b43_set_slot_time(dev, 9);
e4d6b795
MB		 635}
636
637static void b43_short_slot_timing_disable(struct b43_wldev *dev)
638{
639 b43_set_slot_time(dev, 20);
e4d6b795
MB		 640}
641
e4d6b795 642/* DummyTransmission function, as documented on
2f19c287 643 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 644 */
2f19c287 645void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 646{
647 struct b43_phy *phy = &dev->phy;
648 unsigned int i, max_loop;
649 u16 value;
650 u32 buffer[5] = {
651 0x00000000,
652 0x00D40000,
653 0x00000000,
654 0x01000000,
655 0x00000000,
656 };
657
2f19c287 658 if (ofdm) {
e4d6b795
MB		 659 max_loop = 0x1E;
660 buffer[0] = 0x000201CC;
2f19c287 661 } else {
e4d6b795
MB		 662 max_loop = 0xFA;
663 buffer[0] = 0x000B846E;
e4d6b795
MB		 664 }
665
666 for (i = 0; i < 5; i++)
667 b43_ram_write(dev, i * 4, buffer[i]);
668
e4d6b795 669 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 670 if (dev->dev->id.revision < 11)
671 b43_write16(dev, 0x07C0, 0x0000);
672 else
673 b43_write16(dev, 0x07C0, 0x0100);
674 value = (ofdm ? 0x41 : 0x40);
e4d6b795 675 b43_write16(dev, 0x050C, value);
2f19c287
GS		 676 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
677 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 678 b43_write16(dev, 0x0508, 0x0000);
679 b43_write16(dev, 0x050A, 0x0000);
680 b43_write16(dev, 0x054C, 0x0000);
681 b43_write16(dev, 0x056A, 0x0014);
682 b43_write16(dev, 0x0568, 0x0826);
683 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 684 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
685 //SPEC TODO
686 }
687
688 switch (phy->type) {
689 case B43_PHYTYPE_N:
690 b43_write16(dev, 0x0502, 0x00D0);
691 break;
692 case B43_PHYTYPE_LP:
693 b43_write16(dev, 0x0502, 0x0050);
694 break;
695 default:
696 b43_write16(dev, 0x0502, 0x0030);
697 }
e4d6b795
MB		 698
699 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
700 b43_radio_write16(dev, 0x0051, 0x0017);
701 for (i = 0x00; i < max_loop; i++) {
702 value = b43_read16(dev, 0x050E);
703 if (value & 0x0080)
704 break;
705 udelay(10);
706 }
707 for (i = 0x00; i < 0x0A; i++) {
708 value = b43_read16(dev, 0x050E);
709 if (value & 0x0400)
710 break;
711 udelay(10);
712 }
1d280ddc 713 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 714 value = b43_read16(dev, 0x0690);
715 if (!(value & 0x0100))
716 break;
717 udelay(10);
718 }
719 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
720 b43_radio_write16(dev, 0x0051, 0x0037);
721}
722
723static void key_write(struct b43_wldev *dev,
99da185a 724 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 725{
726 unsigned int i;
727 u32 offset;
728 u16 value;
729 u16 kidx;
730
731 /* Key index/algo block */
732 kidx = b43_kidx_to_fw(dev, index);
733 value = ((kidx << 4) | algorithm);
734 b43_shm_write16(dev, B43_SHM_SHARED,
735 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
736
737 /* Write the key to the Key Table Pointer offset */
738 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
739 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
740 value = key[i];
741 value |= (u16) (key[i + 1]) << 8;
742 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
743 }
744}
745
99da185a 746static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 747{
748 u32 addrtmp[2] = { 0, 0, };
66d2d089 749 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 750
751 if (b43_new_kidx_api(dev))
66d2d089 752 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 753
66d2d089
MB		 754 B43_WARN_ON(index < pairwise_keys_start);
755 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 756 * Physical mac 0 is mapped to physical key 4 or 8, depending
757 * on the firmware version.
758 * So we must adjust the index here.
759 */
66d2d089
MB		 760 index -= pairwise_keys_start;
761 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 762
763 if (addr) {
764 addrtmp[0] = addr[0];
765 addrtmp[0] |= ((u32) (addr[1]) << 8);
766 addrtmp[0] |= ((u32) (addr[2]) << 16);
767 addrtmp[0] |= ((u32) (addr[3]) << 24);
768 addrtmp[1] = addr[4];
769 addrtmp[1] |= ((u32) (addr[5]) << 8);
770 }
771
66d2d089
MB		 772 /* Receive match transmitter address (RCMTA) mechanism */
773 b43_shm_write32(dev, B43_SHM_RCMTA,
774 (index * 2) + 0, addrtmp[0]);
775 b43_shm_write16(dev, B43_SHM_RCMTA,
776 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 777}
778
035d0243 779/* The ucode will use phase1 key with TEK key to decrypt rx packets.
780 * When a packet is received, the iv32 is checked.
781 * - if it doesn't the packet is returned without modification (and software
782 * decryption can be done). That's what happen when iv16 wrap.
783 * - if it does, the rc4 key is computed, and decryption is tried.
784 * Either it will success and B43_RX_MAC_DEC is returned,
785 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
786 * and the packet is not usable (it got modified by the ucode).
787 * So in order to never have B43_RX_MAC_DECERR, we should provide
788 * a iv32 and phase1key that match. Because we drop packets in case of
789 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
790 * packets will be lost without higher layer knowing (ie no resync possible
791 * until next wrap).
792 *
793 * NOTE : this should support 50 key like RCMTA because
794 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
795 */
796static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
797 u16 *phase1key)
798{
799 unsigned int i;
800 u32 offset;
801 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
802
803 if (!modparam_hwtkip)
804 return;
805
806 if (b43_new_kidx_api(dev))
807 pairwise_keys_start = B43_NR_GROUP_KEYS;
808
809 B43_WARN_ON(index < pairwise_keys_start);
810 /* We have four default TX keys and possibly four default RX keys.
811 * Physical mac 0 is mapped to physical key 4 or 8, depending
812 * on the firmware version.
813 * So we must adjust the index here.
814 */
815 index -= pairwise_keys_start;
816 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
817
818 if (b43_debug(dev, B43_DBG_KEYS)) {
819 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
820 index, iv32);
821 }
822 /* Write the key to the RX tkip shared mem */
823 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
824 for (i = 0; i < 10; i += 2) {
825 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
826 phase1key ? phase1key[i / 2] : 0);
827 }
828 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
829 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
830}
831
832static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
833 struct ieee80211_key_conf *keyconf, const u8 *addr,
834 u32 iv32, u16 *phase1key)
835{
836 struct b43_wl *wl = hw_to_b43_wl(hw);
837 struct b43_wldev *dev;
838 int index = keyconf->hw_key_idx;
839
840 if (B43_WARN_ON(!modparam_hwtkip))
841 return;
842
843 mutex_lock(&wl->mutex);
844
845 dev = wl->current_dev;
846 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
847 goto out_unlock;
848
849 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
850
851 rx_tkip_phase1_write(dev, index, iv32, phase1key);
852 keymac_write(dev, index, addr);
853
854out_unlock:
855 mutex_unlock(&wl->mutex);
856}
857
e4d6b795
MB		 858static void do_key_write(struct b43_wldev *dev,
859 u8 index, u8 algorithm,
99da185a 860 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 861{
862 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 864
865 if (b43_new_kidx_api(dev))
66d2d089 866 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 867
66d2d089 868 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 869 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
870
66d2d089 871 if (index >= pairwise_keys_start)
e4d6b795 872 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 873 if (algorithm == B43_SEC_ALGO_TKIP) {
874 /*
875 * We should provide an initial iv32, phase1key pair.
876 * We could start with iv32=0 and compute the corresponding
877 * phase1key, but this means calling ieee80211_get_tkip_key
878 * with a fake skb (or export other tkip function).
879 * Because we are lazy we hope iv32 won't start with
880 * 0xffffffff and let's b43_op_update_tkip_key provide a
881 * correct pair.
882 */
883 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
884 } else if (index >= pairwise_keys_start) /* clear it */
885 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 886 if (key)
887 memcpy(buf, key, key_len);
888 key_write(dev, index, algorithm, buf);
66d2d089 889 if (index >= pairwise_keys_start)
e4d6b795
MB		 890 keymac_write(dev, index, mac_addr);
891
892 dev->key[index].algorithm = algorithm;
893}
894
895static int b43_key_write(struct b43_wldev *dev,
896 int index, u8 algorithm,
99da185a
JD		 897 const u8 *key, size_t key_len,
898 const u8 *mac_addr,
e4d6b795
MB		 899 struct ieee80211_key_conf *keyconf)
900{
901 int i;
66d2d089 902 int pairwise_keys_start;
e4d6b795 903
035d0243 904 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
905 * - Temporal Encryption Key (128 bits)
906 * - Temporal Authenticator Tx MIC Key (64 bits)
907 * - Temporal Authenticator Rx MIC Key (64 bits)
908 *
909 * Hardware only store TEK
910 */
911 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
912 key_len = 16;
e4d6b795
MB		 913 if (key_len > B43_SEC_KEYSIZE)
914 return -EINVAL;
66d2d089 915 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 916 /* Check that we don't already have this key. */
917 B43_WARN_ON(dev->key[i].keyconf == keyconf);
918 }
919 if (index < 0) {
e808e586 920 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 921 if (b43_new_kidx_api(dev))
66d2d089 922 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 923 else
66d2d089
MB		 924 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
925 for (i = pairwise_keys_start;
926 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
927 i++) {
928 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 929 if (!dev->key[i].keyconf) {
930 /* found empty */
931 index = i;
932 break;
933 }
934 }
935 if (index < 0) {
e808e586 936 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 937 return -ENOSPC;
938 }
939 } else
940 B43_WARN_ON(index > 3);
941
942 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
943 if ((index <= 3) && !b43_new_kidx_api(dev)) {
944 /* Default RX key */
945 B43_WARN_ON(mac_addr);
946 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
947 }
948 keyconf->hw_key_idx = index;
949 dev->key[index].keyconf = keyconf;
950
951 return 0;
952}
953
954static int b43_key_clear(struct b43_wldev *dev, int index)
955{
66d2d089 956 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 957 return -EINVAL;
958 do_key_write(dev, index, B43_SEC_ALGO_NONE,
959 NULL, B43_SEC_KEYSIZE, NULL);
960 if ((index <= 3) && !b43_new_kidx_api(dev)) {
961 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
962 NULL, B43_SEC_KEYSIZE, NULL);
963 }
964 dev->key[index].keyconf = NULL;
965
966 return 0;
967}
968
969static void b43_clear_keys(struct b43_wldev *dev)
970{
66d2d089 971 int i, count;
e4d6b795 972
66d2d089
MB		 973 if (b43_new_kidx_api(dev))
974 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
975 else
976 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
977 for (i = 0; i < count; i++)
e4d6b795
MB		 978 b43_key_clear(dev, i);
979}
980
9cf7f247
MB		 981static void b43_dump_keymemory(struct b43_wldev *dev)
982{
66d2d089 983 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 984 u8 mac[ETH_ALEN];
985 u16 algo;
986 u32 rcmta0;
987 u16 rcmta1;
988 u64 hf;
989 struct b43_key *key;
990
991 if (!b43_debug(dev, B43_DBG_KEYS))
992 return;
993
994 hf = b43_hf_read(dev);
995 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
996 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 997 if (b43_new_kidx_api(dev)) {
998 pairwise_keys_start = B43_NR_GROUP_KEYS;
999 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1000 } else {
1001 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1002 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1003 }
1004 for (index = 0; index < count; index++) {
9cf7f247
MB		 1005 key = &(dev->key[index]);
1006 printk(KERN_DEBUG "Key slot %02u: %s",
1007 index, (key->keyconf == NULL) ? " " : "*");
1008 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1009 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1010 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1011 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1012 }
1013
1014 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1015 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1016 printk(" Algo: %04X/%02X", algo, key->algorithm);
1017
66d2d089 1018 if (index >= pairwise_keys_start) {
035d0243 1019 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1020 printk(" TKIP: ");
1021 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1022 for (i = 0; i < 14; i += 2) {
1023 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1024 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1025 }
1026 }
9cf7f247 1027 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1028 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1029 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1030 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1031 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1032 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1033 printk(" MAC: %pM", mac);
9cf7f247
MB		 1034 } else
1035 printk(" DEFAULT KEY");
1036 printk("\n");
1037 }
1038}
1039
e4d6b795
MB		 1040void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1041{
1042 u32 macctl;
1043 u16 ucstat;
1044 bool hwps;
1045 bool awake;
1046 int i;
1047
1048 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1049 (ps_flags & B43_PS_DISABLED));
1050 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1051
1052 if (ps_flags & B43_PS_ENABLED) {
1053 hwps = 1;
1054 } else if (ps_flags & B43_PS_DISABLED) {
1055 hwps = 0;
1056 } else {
1057 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1058 // and thus is not an AP and we are associated, set bit 25
1059 }
1060 if (ps_flags & B43_PS_AWAKE) {
1061 awake = 1;
1062 } else if (ps_flags & B43_PS_ASLEEP) {
1063 awake = 0;
1064 } else {
1065 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1066 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1067 // successful, set bit26
1068 }
1069
1070/* FIXME: For now we force awake-on and hwps-off */
1071 hwps = 0;
1072 awake = 1;
1073
1074 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1075 if (hwps)
1076 macctl |= B43_MACCTL_HWPS;
1077 else
1078 macctl &= ~B43_MACCTL_HWPS;
1079 if (awake)
1080 macctl |= B43_MACCTL_AWAKE;
1081 else
1082 macctl &= ~B43_MACCTL_AWAKE;
1083 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1084 /* Commit write */
1085 b43_read32(dev, B43_MMIO_MACCTL);
1086 if (awake && dev->dev->id.revision >= 5) {
1087 /* Wait for the microcode to wake up. */
1088 for (i = 0; i < 100; i++) {
1089 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1090 B43_SHM_SH_UCODESTAT);
1091 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1092 break;
1093 udelay(10);
1094 }
1095 }
1096}
1097
e4d6b795
MB		 1098void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1099{
1100 u32 tmslow;
1101 u32 macctl;
1102
1103 flags |= B43_TMSLOW_PHYCLKEN;
1104 flags |= B43_TMSLOW_PHYRESET;
1105 ssb_device_enable(dev->dev, flags);
1106 msleep(2); /* Wait for the PLL to turn on. */
1107
1108 /* Now take the PHY out of Reset again */
1109 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1110 tmslow |= SSB_TMSLOW_FGC;
1111 tmslow &= ~B43_TMSLOW_PHYRESET;
1112 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1113 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1114 msleep(1);
1115 tmslow &= ~SSB_TMSLOW_FGC;
1116 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1117 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1118 msleep(1);
1119
fb11137a
MB		 1120 /* Turn Analog ON, but only if we already know the PHY-type.
1121 * This protects against very early setup where we don't know the
1122 * PHY-type, yet. wireless_core_reset will be called once again later,
1123 * when we know the PHY-type. */
1124 if (dev->phy.ops)
cb24f57f 1125 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1126
1127 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1128 macctl &= ~B43_MACCTL_GMODE;
1129 if (flags & B43_TMSLOW_GMODE)
1130 macctl |= B43_MACCTL_GMODE;
1131 macctl |= B43_MACCTL_IHR_ENABLED;
1132 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1133}
1134
1135static void handle_irq_transmit_status(struct b43_wldev *dev)
1136{
1137 u32 v0, v1;
1138 u16 tmp;
1139 struct b43_txstatus stat;
1140
1141 while (1) {
1142 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1143 if (!(v0 & 0x00000001))
1144 break;
1145 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1146
1147 stat.cookie = (v0 >> 16);
1148 stat.seq = (v1 & 0x0000FFFF);
1149 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1150 tmp = (v0 & 0x0000FFFF);
1151 stat.frame_count = ((tmp & 0xF000) >> 12);
1152 stat.rts_count = ((tmp & 0x0F00) >> 8);
1153 stat.supp_reason = ((tmp & 0x001C) >> 2);
1154 stat.pm_indicated = !!(tmp & 0x0080);
1155 stat.intermediate = !!(tmp & 0x0040);
1156 stat.for_ampdu = !!(tmp & 0x0020);
1157 stat.acked = !!(tmp & 0x0002);
1158
1159 b43_handle_txstatus(dev, &stat);
1160 }
1161}
1162
1163static void drain_txstatus_queue(struct b43_wldev *dev)
1164{
1165 u32 dummy;
1166
1167 if (dev->dev->id.revision < 5)
1168 return;
1169 /* Read all entries from the microcode TXstatus FIFO
1170 * and throw them away.
1171 */
1172 while (1) {
1173 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1174 if (!(dummy & 0x00000001))
1175 break;
1176 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1177 }
1178}
1179
1180static u32 b43_jssi_read(struct b43_wldev *dev)
1181{
1182 u32 val = 0;
1183
1184 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1185 val <<= 16;
1186 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1187
1188 return val;
1189}
1190
1191static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1192{
1193 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1194 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1195}
1196
1197static void b43_generate_noise_sample(struct b43_wldev *dev)
1198{
1199 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1200 b43_write32(dev, B43_MMIO_MACCMD,
1201 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1202}
1203
1204static void b43_calculate_link_quality(struct b43_wldev *dev)
1205{
1206 /* Top half of Link Quality calculation. */
1207
ef1a628d
MB		 1208 if (dev->phy.type != B43_PHYTYPE_G)
1209 return;
e4d6b795
MB		 1210 if (dev->noisecalc.calculation_running)
1211 return;
e4d6b795
MB		 1212 dev->noisecalc.calculation_running = 1;
1213 dev->noisecalc.nr_samples = 0;
1214
1215 b43_generate_noise_sample(dev);
1216}
1217
1218static void handle_irq_noise(struct b43_wldev *dev)
1219{
ef1a628d 1220 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1221 u16 tmp;
1222 u8 noise[4];
1223 u8 i, j;
1224 s32 average;
1225
1226 /* Bottom half of Link Quality calculation. */
1227
ef1a628d
MB		 1228 if (dev->phy.type != B43_PHYTYPE_G)
1229 return;
1230
98a3b2fe
MB		 1231 /* Possible race condition: It might be possible that the user
1232 * changed to a different channel in the meantime since we
1233 * started the calculation. We ignore that fact, since it's
1234 * not really that much of a problem. The background noise is
1235 * an estimation only anyway. Slightly wrong results will get damped
1236 * by the averaging of the 8 sample rounds. Additionally the
1237 * value is shortlived. So it will be replaced by the next noise
1238 * calculation round soon. */
1239
e4d6b795 1240 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1241 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1242 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1243 noise[2] == 0x7F || noise[3] == 0x7F)
1244 goto generate_new;
1245
1246 /* Get the noise samples. */
1247 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1248 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1249 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1250 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1251 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1252 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1253 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1254 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1255 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1256 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1257 dev->noisecalc.nr_samples++;
1258 if (dev->noisecalc.nr_samples == 8) {
1259 /* Calculate the Link Quality by the noise samples. */
1260 average = 0;
1261 for (i = 0; i < 8; i++) {
1262 for (j = 0; j < 4; j++)
1263 average += dev->noisecalc.samples[i][j];
1264 }
1265 average /= (8 * 4);
1266 average *= 125;
1267 average += 64;
1268 average /= 128;
1269 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1270 tmp = (tmp / 128) & 0x1F;
1271 if (tmp >= 8)
1272 average += 2;
1273 else
1274 average -= 25;
1275 if (tmp == 8)
1276 average -= 72;
1277 else
1278 average -= 48;
1279
1280 dev->stats.link_noise = average;
e4d6b795
MB		 1281 dev->noisecalc.calculation_running = 0;
1282 return;
1283 }
98a3b2fe 1284generate_new:
e4d6b795
MB		 1285 b43_generate_noise_sample(dev);
1286}
1287
1288static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1289{
05c914fe 1290 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1291 ///TODO: PS TBTT
1292 } else {
1293 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1294 b43_power_saving_ctl_bits(dev, 0);
1295 }
05c914fe 1296 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1297 dev->dfq_valid = 1;
e4d6b795
MB		 1298}
1299
1300static void handle_irq_atim_end(struct b43_wldev *dev)
1301{
aa6c7ae2
MB		 1302 if (dev->dfq_valid) {
1303 b43_write32(dev, B43_MMIO_MACCMD,
1304 b43_read32(dev, B43_MMIO_MACCMD)
1305 | B43_MACCMD_DFQ_VALID);
1306 dev->dfq_valid = 0;
1307 }
e4d6b795
MB		 1308}
1309
1310static void handle_irq_pmq(struct b43_wldev *dev)
1311{
1312 u32 tmp;
1313
1314 //TODO: AP mode.
1315
1316 while (1) {
1317 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1318 if (!(tmp & 0x00000008))
1319 break;
1320 }
1321 /* 16bit write is odd, but correct. */
1322 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1323}
1324
1325static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1326 const u8 *data, u16 size,
e4d6b795
MB		 1327 u16 ram_offset,
1328 u16 shm_size_offset, u8 rate)
1329{
1330 u32 i, tmp;
1331 struct b43_plcp_hdr4 plcp;
1332
1333 plcp.data = 0;
1334 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1335 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1336 ram_offset += sizeof(u32);
1337 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1338 * So leave the first two bytes of the next write blank.
1339 */
1340 tmp = (u32) (data[0]) << 16;
1341 tmp |= (u32) (data[1]) << 24;
1342 b43_ram_write(dev, ram_offset, tmp);
1343 ram_offset += sizeof(u32);
1344 for (i = 2; i < size; i += sizeof(u32)) {
1345 tmp = (u32) (data[i + 0]);
1346 if (i + 1 < size)
1347 tmp |= (u32) (data[i + 1]) << 8;
1348 if (i + 2 < size)
1349 tmp |= (u32) (data[i + 2]) << 16;
1350 if (i + 3 < size)
1351 tmp |= (u32) (data[i + 3]) << 24;
1352 b43_ram_write(dev, ram_offset + i - 2, tmp);
1353 }
1354 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1355 size + sizeof(struct b43_plcp_hdr6));
1356}
1357
5042c507
MB		 1358/* Check if the use of the antenna that ieee80211 told us to
1359 * use is possible. This will fall back to DEFAULT.
1360 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1361u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1362 u8 antenna_nr)
1363{
1364 u8 antenna_mask;
1365
1366 if (antenna_nr == 0) {
1367 /* Zero means "use default antenna". That's always OK. */
1368 return 0;
1369 }
1370
1371 /* Get the mask of available antennas. */
1372 if (dev->phy.gmode)
1373 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1374 else
1375 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1376
1377 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1378 /* This antenna is not available. Fall back to default. */
1379 return 0;
1380 }
1381
1382 return antenna_nr;
1383}
1384
5042c507
MB		 1385/* Convert a b43 antenna number value to the PHY TX control value. */
1386static u16 b43_antenna_to_phyctl(int antenna)
1387{
1388 switch (antenna) {
1389 case B43_ANTENNA0:
1390 return B43_TXH_PHY_ANT0;
1391 case B43_ANTENNA1:
1392 return B43_TXH_PHY_ANT1;
1393 case B43_ANTENNA2:
1394 return B43_TXH_PHY_ANT2;
1395 case B43_ANTENNA3:
1396 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1397 case B43_ANTENNA_AUTO0:
1398 case B43_ANTENNA_AUTO1:
5042c507
MB		 1399 return B43_TXH_PHY_ANT01AUTO;
1400 }
1401 B43_WARN_ON(1);
1402 return 0;
1403}
1404
e4d6b795
MB		 1405static void b43_write_beacon_template(struct b43_wldev *dev,
1406 u16 ram_offset,
5042c507 1407 u16 shm_size_offset)
e4d6b795 1408{
47f76ca3 1409 unsigned int i, len, variable_len;
e66fee6a
MB		 1410 const struct ieee80211_mgmt *bcn;
1411 const u8 *ie;
1412 bool tim_found = 0;
5042c507
MB		 1413 unsigned int rate;
1414 u16 ctl;
1415 int antenna;
e039fa4a 1416 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1417
e66fee6a
MB		 1418 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1419 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1420 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1421 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1422
1423 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1424 len, ram_offset, shm_size_offset, rate);
e66fee6a 1425
5042c507 1426 /* Write the PHY TX control parameters. */
0f4ac38b 1427 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1428 antenna = b43_antenna_to_phyctl(antenna);
1429 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1430 /* We can't send beacons with short preamble. Would get PHY errors. */
1431 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1432 ctl &= ~B43_TXH_PHY_ANT;
1433 ctl &= ~B43_TXH_PHY_ENC;
1434 ctl |= antenna;
1435 if (b43_is_cck_rate(rate))
1436 ctl |= B43_TXH_PHY_ENC_CCK;
1437 else
1438 ctl |= B43_TXH_PHY_ENC_OFDM;
1439 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1440
e66fee6a
MB		 1441 /* Find the position of the TIM and the DTIM_period value
1442 * and write them to SHM. */
1443 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1444 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1445 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1446 uint8_t ie_id, ie_len;
1447
1448 ie_id = ie[i];
1449 ie_len = ie[i + 1];
1450 if (ie_id == 5) {
1451 u16 tim_position;
1452 u16 dtim_period;
1453 /* This is the TIM Information Element */
1454
1455 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1456 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1457 break;
1458 /* A valid TIM is at least 4 bytes long. */
1459 if (ie_len < 4)
1460 break;
1461 tim_found = 1;
1462
1463 tim_position = sizeof(struct b43_plcp_hdr6);
1464 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1465 tim_position += i;
1466
1467 dtim_period = ie[i + 3];
1468
1469 b43_shm_write16(dev, B43_SHM_SHARED,
1470 B43_SHM_SH_TIMBPOS, tim_position);
1471 b43_shm_write16(dev, B43_SHM_SHARED,
1472 B43_SHM_SH_DTIMPER, dtim_period);
1473 break;
1474 }
1475 i += ie_len + 2;
1476 }
1477 if (!tim_found) {
04dea136
JB		 1478 /*
1479 * If ucode wants to modify TIM do it behind the beacon, this
1480 * will happen, for example, when doing mesh networking.
1481 */
1482 b43_shm_write16(dev, B43_SHM_SHARED,
1483 B43_SHM_SH_TIMBPOS,
1484 len + sizeof(struct b43_plcp_hdr6));
1485 b43_shm_write16(dev, B43_SHM_SHARED,
1486 B43_SHM_SH_DTIMPER, 0);
1487 }
1488 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1489}
1490
6b4bec01
MB		 1491static void b43_upload_beacon0(struct b43_wldev *dev)
1492{
1493 struct b43_wl *wl = dev->wl;
1494
1495 if (wl->beacon0_uploaded)
1496 return;
1497 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1498 wl->beacon0_uploaded = 1;
1499}
1500
1501static void b43_upload_beacon1(struct b43_wldev *dev)
1502{
1503 struct b43_wl *wl = dev->wl;
1504
1505 if (wl->beacon1_uploaded)
1506 return;
1507 b43_write_beacon_template(dev, 0x468, 0x1A);
1508 wl->beacon1_uploaded = 1;
1509}
1510
c97a4ccc
MB		 1511static void handle_irq_beacon(struct b43_wldev *dev)
1512{
1513 struct b43_wl *wl = dev->wl;
1514 u32 cmd, beacon0_valid, beacon1_valid;
1515
05c914fe
JB		 1516 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1517 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1518 return;
1519
1520 /* This is the bottom half of the asynchronous beacon update. */
1521
1522 /* Ignore interrupt in the future. */
13790728 1523 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1524
1525 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1526 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1527 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1528
1529 /* Schedule interrupt manually, if busy. */
1530 if (beacon0_valid && beacon1_valid) {
1531 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1532 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1533 return;
1534 }
1535
6b4bec01
MB		 1536 if (unlikely(wl->beacon_templates_virgin)) {
1537 /* We never uploaded a beacon before.
1538 * Upload both templates now, but only mark one valid. */
1539 wl->beacon_templates_virgin = 0;
1540 b43_upload_beacon0(dev);
1541 b43_upload_beacon1(dev);
c97a4ccc
MB		 1542 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1543 cmd |= B43_MACCMD_BEACON0_VALID;
1544 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1545 } else {
1546 if (!beacon0_valid) {
1547 b43_upload_beacon0(dev);
1548 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1549 cmd |= B43_MACCMD_BEACON0_VALID;
1550 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1551 } else if (!beacon1_valid) {
1552 b43_upload_beacon1(dev);
1553 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1554 cmd |= B43_MACCMD_BEACON1_VALID;
1555 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1556 }
c97a4ccc
MB		 1557 }
1558}
1559
36dbd954
MB		 1560static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1561{
1562 u32 old_irq_mask = dev->irq_mask;
1563
1564 /* update beacon right away or defer to irq */
1565 handle_irq_beacon(dev);
1566 if (old_irq_mask != dev->irq_mask) {
1567 /* The handler updated the IRQ mask. */
1568 B43_WARN_ON(!dev->irq_mask);
1569 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1570 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1571 } else {
1572 /* Device interrupts are currently disabled. That means
1573 * we just ran the hardirq handler and scheduled the
1574 * IRQ thread. The thread will write the IRQ mask when
1575 * it finished, so there's nothing to do here. Writing
1576 * the mask _here_ would incorrectly re-enable IRQs. */
1577 }
1578 }
1579}
1580
a82d9922
MB		 1581static void b43_beacon_update_trigger_work(struct work_struct *work)
1582{
1583 struct b43_wl *wl = container_of(work, struct b43_wl,
1584 beacon_update_trigger);
1585 struct b43_wldev *dev;
1586
1587 mutex_lock(&wl->mutex);
1588 dev = wl->current_dev;
1589 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
36dbd954
MB		 1590 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
1591 /* wl->mutex is enough. */
1592 b43_do_beacon_update_trigger_work(dev);
1593 mmiowb();
1594 } else {
1595 spin_lock_irq(&wl->hardirq_lock);
1596 b43_do_beacon_update_trigger_work(dev);
1597 mmiowb();
1598 spin_unlock_irq(&wl->hardirq_lock);
1599 }
a82d9922
MB		 1600 }
1601 mutex_unlock(&wl->mutex);
1602}
1603
d4df6f1a 1604/* Asynchronously update the packet templates in template RAM.
36dbd954 1605 * Locking: Requires wl->mutex to be locked. */
9d139c81 1606static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1607{
9d139c81
JB		 1608 struct sk_buff *beacon;
1609
e66fee6a
MB		 1610 /* This is the top half of the ansynchronous beacon update.
1611 * The bottom half is the beacon IRQ.
1612 * Beacon update must be asynchronous to avoid sending an
1613 * invalid beacon. This can happen for example, if the firmware
1614 * transmits a beacon while we are updating it. */
e4d6b795 1615
9d139c81
JB		 1616 /* We could modify the existing beacon and set the aid bit in
1617 * the TIM field, but that would probably require resizing and
1618 * moving of data within the beacon template.
1619 * Simply request a new beacon and let mac80211 do the hard work. */
1620 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1621 if (unlikely(!beacon))
1622 return;
1623
e66fee6a
MB		 1624 if (wl->current_beacon)
1625 dev_kfree_skb_any(wl->current_beacon);
1626 wl->current_beacon = beacon;
1627 wl->beacon0_uploaded = 0;
1628 wl->beacon1_uploaded = 0;
42935eca 1629 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1630}
1631
e4d6b795
MB		 1632static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1633{
1634 b43_time_lock(dev);
1635 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1636 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1637 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1638 } else {
1639 b43_write16(dev, 0x606, (beacon_int >> 6));
1640 b43_write16(dev, 0x610, beacon_int);
1641 }
1642 b43_time_unlock(dev);
a82d9922 1643 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1644}
1645
afa83e23
MB		 1646static void b43_handle_firmware_panic(struct b43_wldev *dev)
1647{
1648 u16 reason;
1649
1650 /* Read the register that contains the reason code for the panic. */
1651 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1652 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1653
1654 switch (reason) {
1655 default:
1656 b43dbg(dev->wl, "The panic reason is unknown.\n");
1657 /* fallthrough */
1658 case B43_FWPANIC_DIE:
1659 /* Do not restart the controller or firmware.
1660 * The device is nonfunctional from now on.
1661 * Restarting would result in this panic to trigger again,
1662 * so we avoid that recursion. */
1663 break;
1664 case B43_FWPANIC_RESTART:
1665 b43_controller_restart(dev, "Microcode panic");
1666 break;
1667 }
1668}
1669
e4d6b795
MB		 1670static void handle_irq_ucode_debug(struct b43_wldev *dev)
1671{
e48b0eeb 1672 unsigned int i, cnt;
53c06856 1673 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1674 __le16 *buf;
1675
1676 /* The proprietary firmware doesn't have this IRQ. */
1677 if (!dev->fw.opensource)
1678 return;
1679
afa83e23
MB		 1680 /* Read the register that contains the reason code for this IRQ. */
1681 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1682
e48b0eeb
MB		 1683 switch (reason) {
1684 case B43_DEBUGIRQ_PANIC:
afa83e23 1685 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1686 break;
1687 case B43_DEBUGIRQ_DUMP_SHM:
1688 if (!B43_DEBUG)
1689 break; /* Only with driver debugging enabled. */
1690 buf = kmalloc(4096, GFP_ATOMIC);
1691 if (!buf) {
1692 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1693 goto out;
1694 }
1695 for (i = 0; i < 4096; i += 2) {
1696 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1697 buf[i / 2] = cpu_to_le16(tmp);
1698 }
1699 b43info(dev->wl, "Shared memory dump:\n");
1700 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1701 16, 2, buf, 4096, 1);
1702 kfree(buf);
1703 break;
1704 case B43_DEBUGIRQ_DUMP_REGS:
1705 if (!B43_DEBUG)
1706 break; /* Only with driver debugging enabled. */
1707 b43info(dev->wl, "Microcode register dump:\n");
1708 for (i = 0, cnt = 0; i < 64; i++) {
1709 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1710 if (cnt == 0)
1711 printk(KERN_INFO);
1712 printk("r%02u: 0x%04X ", i, tmp);
1713 cnt++;
1714 if (cnt == 6) {
1715 printk("\n");
1716 cnt = 0;
1717 }
1718 }
1719 printk("\n");
1720 break;
53c06856
MB		 1721 case B43_DEBUGIRQ_MARKER:
1722 if (!B43_DEBUG)
1723 break; /* Only with driver debugging enabled. */
1724 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1725 B43_MARKER_ID_REG);
1726 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1727 B43_MARKER_LINE_REG);
1728 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1729 "at line number %u\n",
1730 marker_id, marker_line);
1731 break;
e48b0eeb
MB		 1732 default:
1733 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1734 reason);
1735 }
1736out:
afa83e23
MB		 1737 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1738 b43_shm_write16(dev, B43_SHM_SCRATCH,
1739 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1740}
1741
36dbd954 1742static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1743{
1744 u32 reason;
1745 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1746 u32 merged_dma_reason = 0;
21954c36 1747 int i;
e4d6b795 1748
36dbd954
MB		 1749 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1750 return;
e4d6b795
MB		 1751
1752 reason = dev->irq_reason;
1753 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1754 dma_reason[i] = dev->dma_reason[i];
1755 merged_dma_reason |= dma_reason[i];
1756 }
1757
1758 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1759 b43err(dev->wl, "MAC transmission error\n");
1760
00e0b8cb 1761 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1762 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1763 rmb();
1764 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1765 atomic_set(&dev->phy.txerr_cnt,
1766 B43_PHY_TX_BADNESS_LIMIT);
1767 b43err(dev->wl, "Too many PHY TX errors, "
1768 "restarting the controller\n");
1769 b43_controller_restart(dev, "PHY TX errors");
1770 }
1771 }
e4d6b795
MB		 1772
1773 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1774 B43_DMAIRQ_NONFATALMASK))) {
1775 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1776 b43err(dev->wl, "Fatal DMA error: "
1777 "0x%08X, 0x%08X, 0x%08X, "
1778 "0x%08X, 0x%08X, 0x%08X\n",
1779 dma_reason[0], dma_reason[1],
1780 dma_reason[2], dma_reason[3],
1781 dma_reason[4], dma_reason[5]);
1782 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1783 return;
1784 }
1785 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1786 b43err(dev->wl, "DMA error: "
1787 "0x%08X, 0x%08X, 0x%08X, "
1788 "0x%08X, 0x%08X, 0x%08X\n",
1789 dma_reason[0], dma_reason[1],
1790 dma_reason[2], dma_reason[3],
1791 dma_reason[4], dma_reason[5]);
1792 }
1793 }
1794
1795 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1796 handle_irq_ucode_debug(dev);
1797 if (reason & B43_IRQ_TBTT_INDI)
1798 handle_irq_tbtt_indication(dev);
1799 if (reason & B43_IRQ_ATIM_END)
1800 handle_irq_atim_end(dev);
1801 if (reason & B43_IRQ_BEACON)
1802 handle_irq_beacon(dev);
1803 if (reason & B43_IRQ_PMQ)
1804 handle_irq_pmq(dev);
21954c36
MB		 1805 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1806 ;/* TODO */
1807 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1808 handle_irq_noise(dev);
1809
1810 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1811 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1812 if (b43_using_pio_transfers(dev))
1813 b43_pio_rx(dev->pio.rx_queue);
1814 else
1815 b43_dma_rx(dev->dma.rx_ring);
1816 }
e4d6b795
MB		 1817 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1818 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1819 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1820 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1821 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1822
21954c36 1823 if (reason & B43_IRQ_TX_OK)
e4d6b795 1824 handle_irq_transmit_status(dev);
e4d6b795 1825
36dbd954 1826 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1827 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1828}
1829
36dbd954
MB		 1830/* Interrupt thread handler. Handles device interrupts in thread context. */
1831static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1832{
36dbd954 1833 struct b43_wldev *dev = dev_id;
e4d6b795 1834
36dbd954
MB		 1835 mutex_lock(&dev->wl->mutex);
1836 b43_do_interrupt_thread(dev);
1837 mmiowb();
1838 mutex_unlock(&dev->wl->mutex);
1839
1840 return IRQ_HANDLED;
e4d6b795
MB		 1841}
1842
36dbd954 1843static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1844{
e4d6b795
MB		 1845 u32 reason;
1846
36dbd954
MB		 1847 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1848 * On SDIO, this runs under wl->mutex. */
e4d6b795 1849
e4d6b795
MB		 1850 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1851 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1852 return IRQ_NONE;
13790728 1853 reason &= dev->irq_mask;
e4d6b795 1854 if (!reason)
36dbd954 1855 return IRQ_HANDLED;
e4d6b795
MB		 1856
1857 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1858 & 0x0001DC00;
1859 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1860 & 0x0000DC00;
1861 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1862 & 0x0000DC00;
1863 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1864 & 0x0001DC00;
1865 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1866 & 0x0000DC00;
13790728 1867/* Unused ring
e4d6b795
MB		 1868 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1869 & 0x0000DC00;
13790728 1870*/
e4d6b795 1871
36dbd954
MB		 1872 /* ACK the interrupt. */
1873 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1874 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1875 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1876 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1877 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1878 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1879/* Unused ring
1880 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1881*/
1882
1883 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 1884 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 1885 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 1886 dev->irq_reason = reason;
36dbd954
MB		 1887
1888 return IRQ_WAKE_THREAD;
1889}
1890
1891/* Interrupt handler top-half. This runs with interrupts disabled. */
1892static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1893{
1894 struct b43_wldev *dev = dev_id;
1895 irqreturn_t ret;
1896
1897 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1898 return IRQ_NONE;
1899
1900 spin_lock(&dev->wl->hardirq_lock);
1901 ret = b43_do_interrupt(dev);
e4d6b795 1902 mmiowb();
36dbd954 1903 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 1904
1905 return ret;
1906}
1907
1a9f5093 1908void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1909{
1910 release_firmware(fw->data);
1911 fw->data = NULL;
1912 fw->filename = NULL;
1913}
1914
e4d6b795
MB		 1915static void b43_release_firmware(struct b43_wldev *dev)
1916{
1a9f5093
MB		 1917 b43_do_release_fw(&dev->fw.ucode);
1918 b43_do_release_fw(&dev->fw.pcm);
1919 b43_do_release_fw(&dev->fw.initvals);
1920 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1921}
1922
eb189d8b 1923static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1924{
fc68ed4f
HE		 1925 const char text[] =
1926 "You must go to " \
1927 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1928 "and download the correct firmware for this driver version. " \
1929 "Please carefully read all instructions on this website.\n";
eb189d8b 1930
eb189d8b
MB		 1931 if (error)
1932 b43err(wl, text);
1933 else
1934 b43warn(wl, text);
e4d6b795
MB		 1935}
1936
1a9f5093
MB		 1937int b43_do_request_fw(struct b43_request_fw_context *ctx,
1938 const char *name,
1939 struct b43_firmware_file *fw)
e4d6b795 1940{
61cb5dd6 1941 const struct firmware *blob;
e4d6b795
MB		 1942 struct b43_fw_header *hdr;
1943 u32 size;
1944 int err;
1945
61cb5dd6
MB		 1946 if (!name) {
1947 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1948 /* FIXME: We should probably keep it anyway, to save some headache
1949 * on suspend/resume with multiband devices. */
1950 b43_do_release_fw(fw);
e4d6b795 1951 return 0;
61cb5dd6
MB		 1952 }
1953 if (fw->filename) {
1a9f5093
MB		 1954 if ((fw->type == ctx->req_type) &&
1955 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1956 return 0; /* Already have this fw. */
1957 /* Free the cached firmware first. */
1a9f5093
MB		 1958 /* FIXME: We should probably do this later after we successfully
1959 * got the new fw. This could reduce headache with multiband devices.
1960 * We could also redesign this to cache the firmware for all possible
1961 * bands all the time. */
1962 b43_do_release_fw(fw);
61cb5dd6 1963 }
e4d6b795 1964
1a9f5093
MB		 1965 switch (ctx->req_type) {
1966 case B43_FWTYPE_PROPRIETARY:
1967 snprintf(ctx->fwname, sizeof(ctx->fwname),
1968 "b43%s/%s.fw",
1969 modparam_fwpostfix, name);
1970 break;
1971 case B43_FWTYPE_OPENSOURCE:
1972 snprintf(ctx->fwname, sizeof(ctx->fwname),
1973 "b43-open%s/%s.fw",
1974 modparam_fwpostfix, name);
1975 break;
1976 default:
1977 B43_WARN_ON(1);
1978 return -ENOSYS;
1979 }
1980 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 1981 if (err == -ENOENT) {
1a9f5093
MB		 1982 snprintf(ctx->errors[ctx->req_type],
1983 sizeof(ctx->errors[ctx->req_type]),
1984 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 1985 return err;
1986 } else if (err) {
1a9f5093
MB		 1987 snprintf(ctx->errors[ctx->req_type],
1988 sizeof(ctx->errors[ctx->req_type]),
1989 "Firmware file \"%s\" request failed (err=%d)\n",
1990 ctx->fwname, err);
e4d6b795
MB		 1991 return err;
1992 }
61cb5dd6 1993 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 1994 goto err_format;
61cb5dd6 1995 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 1996 switch (hdr->type) {
1997 case B43_FW_TYPE_UCODE:
1998 case B43_FW_TYPE_PCM:
1999 size = be32_to_cpu(hdr->size);
61cb5dd6 2000 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2001 goto err_format;
2002 /* fallthrough */
2003 case B43_FW_TYPE_IV:
2004 if (hdr->ver != 1)
2005 goto err_format;
2006 break;
2007 default:
2008 goto err_format;
2009 }
2010
61cb5dd6
MB		 2011 fw->data = blob;
2012 fw->filename = name;
1a9f5093 2013 fw->type = ctx->req_type;
61cb5dd6
MB		 2014
2015 return 0;
e4d6b795
MB		 2016
2017err_format:
1a9f5093
MB		 2018 snprintf(ctx->errors[ctx->req_type],
2019 sizeof(ctx->errors[ctx->req_type]),
2020 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2021 release_firmware(blob);
2022
e4d6b795
MB		 2023 return -EPROTO;
2024}
2025
1a9f5093 2026static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2027{
1a9f5093
MB		 2028 struct b43_wldev *dev = ctx->dev;
2029 struct b43_firmware *fw = &ctx->dev->fw;
2030 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2031 const char *filename;
2032 u32 tmshigh;
2033 int err;
2034
61cb5dd6 2035 /* Get microcode */
e4d6b795 2036 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2037 if ((rev >= 5) && (rev <= 10))
2038 filename = "ucode5";
2039 else if ((rev >= 11) && (rev <= 12))
2040 filename = "ucode11";
759b973b 2041 else if (rev == 13)
61cb5dd6 2042 filename = "ucode13";
759b973b
GS		 2043 else if (rev == 14)
2044 filename = "ucode14";
2045 else if (rev >= 15)
2046 filename = "ucode15";
61cb5dd6
MB		 2047 else
2048 goto err_no_ucode;
1a9f5093 2049 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2050 if (err)
2051 goto err_load;
2052
2053 /* Get PCM code */
2054 if ((rev >= 5) && (rev <= 10))
2055 filename = "pcm5";
2056 else if (rev >= 11)
2057 filename = NULL;
2058 else
2059 goto err_no_pcm;
68217832 2060 fw->pcm_request_failed = 0;
1a9f5093 2061 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2062 if (err == -ENOENT) {
2063 /* We did not find a PCM file? Not fatal, but
2064 * core rev <= 10 must do without hwcrypto then. */
2065 fw->pcm_request_failed = 1;
2066 } else if (err)
61cb5dd6
MB		 2067 goto err_load;
2068
2069 /* Get initvals */
2070 switch (dev->phy.type) {
2071 case B43_PHYTYPE_A:
2072 if ((rev >= 5) && (rev <= 10)) {
2073 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2074 filename = "a0g1initvals5";
2075 else
2076 filename = "a0g0initvals5";
2077 } else
2078 goto err_no_initvals;
2079 break;
2080 case B43_PHYTYPE_G:
e4d6b795 2081 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2082 filename = "b0g0initvals5";
e4d6b795 2083 else if (rev >= 13)
e9304882 2084 filename = "b0g0initvals13";
e4d6b795 2085 else
61cb5dd6
MB		 2086 goto err_no_initvals;
2087 break;
2088 case B43_PHYTYPE_N:
2089 if ((rev >= 11) && (rev <= 12))
2090 filename = "n0initvals11";
2091 else
2092 goto err_no_initvals;
2093 break;
759b973b
GS		 2094 case B43_PHYTYPE_LP:
2095 if (rev == 13)
2096 filename = "lp0initvals13";
2097 else if (rev == 14)
2098 filename = "lp0initvals14";
2099 else if (rev >= 15)
2100 filename = "lp0initvals15";
2101 else
2102 goto err_no_initvals;
2103 break;
61cb5dd6
MB		 2104 default:
2105 goto err_no_initvals;
e4d6b795 2106 }
1a9f5093 2107 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2108 if (err)
2109 goto err_load;
2110
2111 /* Get bandswitch initvals */
2112 switch (dev->phy.type) {
2113 case B43_PHYTYPE_A:
2114 if ((rev >= 5) && (rev <= 10)) {
2115 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2116 filename = "a0g1bsinitvals5";
2117 else
2118 filename = "a0g0bsinitvals5";
2119 } else if (rev >= 11)
2120 filename = NULL;
2121 else
2122 goto err_no_initvals;
2123 break;
2124 case B43_PHYTYPE_G:
e4d6b795 2125 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2126 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2127 else if (rev >= 11)
2128 filename = NULL;
2129 else
e4d6b795 2130 goto err_no_initvals;
61cb5dd6
MB		 2131 break;
2132 case B43_PHYTYPE_N:
2133 if ((rev >= 11) && (rev <= 12))
2134 filename = "n0bsinitvals11";
2135 else
e4d6b795 2136 goto err_no_initvals;
61cb5dd6 2137 break;
759b973b
GS		 2138 case B43_PHYTYPE_LP:
2139 if (rev == 13)
2140 filename = "lp0bsinitvals13";
2141 else if (rev == 14)
2142 filename = "lp0bsinitvals14";
2143 else if (rev >= 15)
2144 filename = "lp0bsinitvals15";
2145 else
2146 goto err_no_initvals;
2147 break;
61cb5dd6
MB		 2148 default:
2149 goto err_no_initvals;
e4d6b795 2150 }
1a9f5093 2151 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2152 if (err)
2153 goto err_load;
e4d6b795
MB		 2154
2155 return 0;
2156
e4d6b795 2157err_no_ucode:
1a9f5093
MB		 2158 err = ctx->fatal_failure = -EOPNOTSUPP;
2159 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2160 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2161 goto error;
2162
2163err_no_pcm:
1a9f5093
MB		 2164 err = ctx->fatal_failure = -EOPNOTSUPP;
2165 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2166 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2167 goto error;
2168
2169err_no_initvals:
1a9f5093
MB		 2170 err = ctx->fatal_failure = -EOPNOTSUPP;
2171 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2172 "is required for your device (wl-core rev %u)\n", rev);
2173 goto error;
2174
2175err_load:
2176 /* We failed to load this firmware image. The error message
2177 * already is in ctx->errors. Return and let our caller decide
2178 * what to do. */
e4d6b795
MB		 2179 goto error;
2180
2181error:
2182 b43_release_firmware(dev);
2183 return err;
2184}
2185
1a9f5093
MB		 2186static int b43_request_firmware(struct b43_wldev *dev)
2187{
2188 struct b43_request_fw_context *ctx;
2189 unsigned int i;
2190 int err;
2191 const char *errmsg;
2192
2193 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2194 if (!ctx)
2195 return -ENOMEM;
2196 ctx->dev = dev;
2197
2198 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2199 err = b43_try_request_fw(ctx);
2200 if (!err)
2201 goto out; /* Successfully loaded it. */
2202 err = ctx->fatal_failure;
2203 if (err)
2204 goto out;
2205
2206 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2207 err = b43_try_request_fw(ctx);
2208 if (!err)
2209 goto out; /* Successfully loaded it. */
2210 err = ctx->fatal_failure;
2211 if (err)
2212 goto out;
2213
2214 /* Could not find a usable firmware. Print the errors. */
2215 for (i = 0; i < B43_NR_FWTYPES; i++) {
2216 errmsg = ctx->errors[i];
2217 if (strlen(errmsg))
2218 b43err(dev->wl, errmsg);
2219 }
2220 b43_print_fw_helptext(dev->wl, 1);
2221 err = -ENOENT;
2222
2223out:
2224 kfree(ctx);
2225 return err;
2226}
2227
e4d6b795
MB		 2228static int b43_upload_microcode(struct b43_wldev *dev)
2229{
2230 const size_t hdr_len = sizeof(struct b43_fw_header);
2231 const __be32 *data;
2232 unsigned int i, len;
2233 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2234 u32 tmp, macctl;
e4d6b795
MB		 2235 int err = 0;
2236
1f7d87b0
MB		 2237 /* Jump the microcode PSM to offset 0 */
2238 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2239 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2240 macctl |= B43_MACCTL_PSM_JMP0;
2241 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2242 /* Zero out all microcode PSM registers and shared memory. */
2243 for (i = 0; i < 64; i++)
2244 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2245 for (i = 0; i < 4096; i += 2)
2246 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2247
e4d6b795 2248 /* Upload Microcode. */
61cb5dd6
MB		 2249 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2250 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2251 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2252 for (i = 0; i < len; i++) {
2253 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2254 udelay(10);
2255 }
2256
61cb5dd6 2257 if (dev->fw.pcm.data) {
e4d6b795 2258 /* Upload PCM data. */
61cb5dd6
MB		 2259 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2260 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2261 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2262 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2263 /* No need for autoinc bit in SHM_HW */
2264 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2265 for (i = 0; i < len; i++) {
2266 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2267 udelay(10);
2268 }
2269 }
2270
2271 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2272
2273 /* Start the microcode PSM */
2274 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2275 macctl &= ~B43_MACCTL_PSM_JMP0;
2276 macctl |= B43_MACCTL_PSM_RUN;
2277 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2278
2279 /* Wait for the microcode to load and respond */
2280 i = 0;
2281 while (1) {
2282 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2283 if (tmp == B43_IRQ_MAC_SUSPENDED)
2284 break;
2285 i++;
1f7d87b0 2286 if (i >= 20) {
e4d6b795 2287 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2288 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2289 err = -ENODEV;
1f7d87b0
MB		 2290 goto error;
2291 }
2292 msleep_interruptible(50);
2293 if (signal_pending(current)) {
2294 err = -EINTR;
2295 goto error;
e4d6b795 2296 }
e4d6b795
MB		 2297 }
2298 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2299
2300 /* Get and check the revisions. */
2301 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2302 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2303 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2304 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2305
2306 if (fwrev <= 0x128) {
2307 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2308 "binary drivers older than version 4.x is unsupported. "
2309 "You must upgrade your firmware files.\n");
eb189d8b 2310 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2311 err = -EOPNOTSUPP;
1f7d87b0 2312 goto error;
e4d6b795 2313 }
e4d6b795
MB		 2314 dev->fw.rev = fwrev;
2315 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2316 dev->fw.opensource = (fwdate == 0xFFFF);
2317
403a3a13
MB		 2318 /* Default to use-all-queues. */
2319 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2320 dev->qos_enabled = !!modparam_qos;
2321 /* Default to firmware/hardware crypto acceleration. */
2322 dev->hwcrypto_enabled = 1;
2323
e48b0eeb 2324 if (dev->fw.opensource) {
403a3a13
MB		 2325 u16 fwcapa;
2326
e48b0eeb
MB		 2327 /* Patchlevel info is encoded in the "time" field. */
2328 dev->fw.patch = fwtime;
403a3a13
MB		 2329 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2330 dev->fw.rev, dev->fw.patch);
2331
2332 fwcapa = b43_fwcapa_read(dev);
2333 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2334 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2335 /* Disable hardware crypto and fall back to software crypto. */
2336 dev->hwcrypto_enabled = 0;
2337 }
2338 if (!(fwcapa & B43_FWCAPA_QOS)) {
2339 b43info(dev->wl, "QoS not supported by firmware\n");
2340 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2341 * ieee80211_unregister to make sure the networking core can
2342 * properly free possible resources. */
2343 dev->wl->hw->queues = 1;
2344 dev->qos_enabled = 0;
2345 }
e48b0eeb
MB		 2346 } else {
2347 b43info(dev->wl, "Loading firmware version %u.%u "
2348 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2349 fwrev, fwpatch,
2350 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2351 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2352 if (dev->fw.pcm_request_failed) {
2353 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2354 "Hardware accelerated cryptography is disabled.\n");
2355 b43_print_fw_helptext(dev->wl, 0);
2356 }
e48b0eeb 2357 }
e4d6b795 2358
eb189d8b 2359 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2360 /* We're over the deadline, but we keep support for old fw
2361 * until it turns out to be in major conflict with something new. */
eb189d8b 2362 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2363 "Support for old firmware will be removed soon "
2364 "(official deadline was July 2008).\n");
eb189d8b
MB		 2365 b43_print_fw_helptext(dev->wl, 0);
2366 }
2367
1f7d87b0
MB		 2368 return 0;
2369
2370error:
2371 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2372 macctl &= ~B43_MACCTL_PSM_RUN;
2373 macctl |= B43_MACCTL_PSM_JMP0;
2374 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2375
e4d6b795
MB		 2376 return err;
2377}
2378
2379static int b43_write_initvals(struct b43_wldev *dev,
2380 const struct b43_iv *ivals,
2381 size_t count,
2382 size_t array_size)
2383{
2384 const struct b43_iv *iv;
2385 u16 offset;
2386 size_t i;
2387 bool bit32;
2388
2389 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2390 iv = ivals;
2391 for (i = 0; i < count; i++) {
2392 if (array_size < sizeof(iv->offset_size))
2393 goto err_format;
2394 array_size -= sizeof(iv->offset_size);
2395 offset = be16_to_cpu(iv->offset_size);
2396 bit32 = !!(offset & B43_IV_32BIT);
2397 offset &= B43_IV_OFFSET_MASK;
2398 if (offset >= 0x1000)
2399 goto err_format;
2400 if (bit32) {
2401 u32 value;
2402
2403 if (array_size < sizeof(iv->data.d32))
2404 goto err_format;
2405 array_size -= sizeof(iv->data.d32);
2406
533dd1b0 2407 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2408 b43_write32(dev, offset, value);
2409
2410 iv = (const struct b43_iv *)((const uint8_t *)iv +
2411 sizeof(__be16) +
2412 sizeof(__be32));
2413 } else {
2414 u16 value;
2415
2416 if (array_size < sizeof(iv->data.d16))
2417 goto err_format;
2418 array_size -= sizeof(iv->data.d16);
2419
2420 value = be16_to_cpu(iv->data.d16);
2421 b43_write16(dev, offset, value);
2422
2423 iv = (const struct b43_iv *)((const uint8_t *)iv +
2424 sizeof(__be16) +
2425 sizeof(__be16));
2426 }
2427 }
2428 if (array_size)
2429 goto err_format;
2430
2431 return 0;
2432
2433err_format:
2434 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2435 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2436
2437 return -EPROTO;
2438}
2439
2440static int b43_upload_initvals(struct b43_wldev *dev)
2441{
2442 const size_t hdr_len = sizeof(struct b43_fw_header);
2443 const struct b43_fw_header *hdr;
2444 struct b43_firmware *fw = &dev->fw;
2445 const struct b43_iv *ivals;
2446 size_t count;
2447 int err;
2448
61cb5dd6
MB		 2449 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2450 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2451 count = be32_to_cpu(hdr->size);
2452 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2453 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2454 if (err)
2455 goto out;
61cb5dd6
MB		 2456 if (fw->initvals_band.data) {
2457 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2458 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2459 count = be32_to_cpu(hdr->size);
2460 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2461 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2462 if (err)
2463 goto out;
2464 }
2465out:
2466
2467 return err;
2468}
2469
2470/* Initialize the GPIOs
2471 * http://bcm-specs.sipsolutions.net/GPIO
2472 */
2473static int b43_gpio_init(struct b43_wldev *dev)
2474{
2475 struct ssb_bus *bus = dev->dev->bus;
2476 struct ssb_device *gpiodev, *pcidev = NULL;
2477 u32 mask, set;
2478
2479 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2480 & ~B43_MACCTL_GPOUTSMSK);
2481
e4d6b795
MB		 2482 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2483 | 0x000F);
2484
2485 mask = 0x0000001F;
2486 set = 0x0000000F;
2487 if (dev->dev->bus->chip_id == 0x4301) {
2488 mask |= 0x0060;
2489 set |= 0x0060;
2490 }
2491 if (0 /* FIXME: conditional unknown */ ) {
2492 b43_write16(dev, B43_MMIO_GPIO_MASK,
2493 b43_read16(dev, B43_MMIO_GPIO_MASK)
2494 | 0x0100);
2495 mask |= 0x0180;
2496 set |= 0x0180;
2497 }
95de2841 2498 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2499 b43_write16(dev, B43_MMIO_GPIO_MASK,
2500 b43_read16(dev, B43_MMIO_GPIO_MASK)
2501 | 0x0200);
2502 mask |= 0x0200;
2503 set |= 0x0200;
2504 }
2505 if (dev->dev->id.revision >= 2)
2506 mask |= 0x0010; /* FIXME: This is redundant. */
2507
2508#ifdef CONFIG_SSB_DRIVER_PCICORE
2509 pcidev = bus->pcicore.dev;
2510#endif
2511 gpiodev = bus->chipco.dev ? : pcidev;
2512 if (!gpiodev)
2513 return 0;
2514 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2515 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2516 & mask) | set);
2517
2518 return 0;
2519}
2520
2521/* Turn off all GPIO stuff. Call this on module unload, for example. */
2522static void b43_gpio_cleanup(struct b43_wldev *dev)
2523{
2524 struct ssb_bus *bus = dev->dev->bus;
2525 struct ssb_device *gpiodev, *pcidev = NULL;
2526
2527#ifdef CONFIG_SSB_DRIVER_PCICORE
2528 pcidev = bus->pcicore.dev;
2529#endif
2530 gpiodev = bus->chipco.dev ? : pcidev;
2531 if (!gpiodev)
2532 return;
2533 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2534}
2535
2536/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2537void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2538{
923fd703
MB		 2539 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2540 u16 fwstate;
2541
2542 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2543 B43_SHM_SH_UCODESTAT);
2544 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2545 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2546 b43err(dev->wl, "b43_mac_enable(): The firmware "
2547 "should be suspended, but current state is %u\n",
2548 fwstate);
2549 }
2550 }
2551
e4d6b795
MB		 2552 dev->mac_suspended--;
2553 B43_WARN_ON(dev->mac_suspended < 0);
2554 if (dev->mac_suspended == 0) {
2555 b43_write32(dev, B43_MMIO_MACCTL,
2556 b43_read32(dev, B43_MMIO_MACCTL)
2557 | B43_MACCTL_ENABLED);
2558 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2559 B43_IRQ_MAC_SUSPENDED);
2560 /* Commit writes */
2561 b43_read32(dev, B43_MMIO_MACCTL);
2562 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2563 b43_power_saving_ctl_bits(dev, 0);
2564 }
2565}
2566
2567/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2568void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2569{
2570 int i;
2571 u32 tmp;
2572
05b64b36 2573 might_sleep();
e4d6b795 2574 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2575
e4d6b795
MB		 2576 if (dev->mac_suspended == 0) {
2577 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2578 b43_write32(dev, B43_MMIO_MACCTL,
2579 b43_read32(dev, B43_MMIO_MACCTL)
2580 & ~B43_MACCTL_ENABLED);
2581 /* force pci to flush the write */
2582 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2583 for (i = 35; i; i--) {
2584 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2585 if (tmp & B43_IRQ_MAC_SUSPENDED)
2586 goto out;
2587 udelay(10);
2588 }
2589 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2590 for (i = 40; i; i--) {
e4d6b795
MB		 2591 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2592 if (tmp & B43_IRQ_MAC_SUSPENDED)
2593 goto out;
05b64b36 2594 msleep(1);
e4d6b795
MB		 2595 }
2596 b43err(dev->wl, "MAC suspend failed\n");
2597 }
05b64b36 2598out:
e4d6b795
MB		 2599 dev->mac_suspended++;
2600}
2601
2602static void b43_adjust_opmode(struct b43_wldev *dev)
2603{
2604 struct b43_wl *wl = dev->wl;
2605 u32 ctl;
2606 u16 cfp_pretbtt;
2607
2608 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2609 /* Reset status to STA infrastructure mode. */
2610 ctl &= ~B43_MACCTL_AP;
2611 ctl &= ~B43_MACCTL_KEEP_CTL;
2612 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2613 ctl &= ~B43_MACCTL_KEEP_BAD;
2614 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2615 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2616 ctl |= B43_MACCTL_INFRA;
2617
05c914fe
JB		 2618 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2619 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2620 ctl |= B43_MACCTL_AP;
05c914fe 2621 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2622 ctl &= ~B43_MACCTL_INFRA;
2623
2624 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2625 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2626 if (wl->filter_flags & FIF_FCSFAIL)
2627 ctl |= B43_MACCTL_KEEP_BAD;
2628 if (wl->filter_flags & FIF_PLCPFAIL)
2629 ctl |= B43_MACCTL_KEEP_BADPLCP;
2630 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2631 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2632 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2633 ctl |= B43_MACCTL_BEACPROMISC;
2634
e4d6b795
MB		 2635 /* Workaround: On old hardware the HW-MAC-address-filter
2636 * doesn't work properly, so always run promisc in filter
2637 * it in software. */
2638 if (dev->dev->id.revision <= 4)
2639 ctl |= B43_MACCTL_PROMISC;
2640
2641 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2642
2643 cfp_pretbtt = 2;
2644 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2645 if (dev->dev->bus->chip_id == 0x4306 &&
2646 dev->dev->bus->chip_rev == 3)
2647 cfp_pretbtt = 100;
2648 else
2649 cfp_pretbtt = 50;
2650 }
2651 b43_write16(dev, 0x612, cfp_pretbtt);
2652}
2653
2654static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2655{
2656 u16 offset;
2657
2658 if (is_ofdm) {
2659 offset = 0x480;
2660 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2661 } else {
2662 offset = 0x4C0;
2663 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2664 }
2665 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2666 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2667}
2668
2669static void b43_rate_memory_init(struct b43_wldev *dev)
2670{
2671 switch (dev->phy.type) {
2672 case B43_PHYTYPE_A:
2673 case B43_PHYTYPE_G:
53a6e234 2674 case B43_PHYTYPE_N:
9d86a2d5 2675 case B43_PHYTYPE_LP:
e4d6b795
MB		 2676 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2677 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2678 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2679 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2680 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2681 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2682 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2683 if (dev->phy.type == B43_PHYTYPE_A)
2684 break;
2685 /* fallthrough */
2686 case B43_PHYTYPE_B:
2687 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2688 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2689 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2690 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2691 break;
2692 default:
2693 B43_WARN_ON(1);
2694 }
2695}
2696
5042c507
MB		 2697/* Set the default values for the PHY TX Control Words. */
2698static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2699{
2700 u16 ctl = 0;
2701
2702 ctl |= B43_TXH_PHY_ENC_CCK;
2703 ctl |= B43_TXH_PHY_ANT01AUTO;
2704 ctl |= B43_TXH_PHY_TXPWR;
2705
2706 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2707 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2708 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2709}
2710
e4d6b795
MB		 2711/* Set the TX-Antenna for management frames sent by firmware. */
2712static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2713{
5042c507 2714 u16 ant;
e4d6b795
MB		 2715 u16 tmp;
2716
5042c507 2717 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2718
e4d6b795
MB		 2719 /* For ACK/CTS */
2720 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2721 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2723 /* For Probe Resposes */
2724 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2725 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2726 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2727}
2728
2729/* This is the opposite of b43_chip_init() */
2730static void b43_chip_exit(struct b43_wldev *dev)
2731{
fb11137a 2732 b43_phy_exit(dev);
e4d6b795
MB		 2733 b43_gpio_cleanup(dev);
2734 /* firmware is released later */
2735}
2736
2737/* Initialize the chip
2738 * http://bcm-specs.sipsolutions.net/ChipInit
2739 */
2740static int b43_chip_init(struct b43_wldev *dev)
2741{
2742 struct b43_phy *phy = &dev->phy;
ef1a628d 2743 int err;
1f7d87b0 2744 u32 value32, macctl;
e4d6b795
MB		 2745 u16 value16;
2746
1f7d87b0
MB		 2747 /* Initialize the MAC control */
2748 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2749 if (dev->phy.gmode)
2750 macctl |= B43_MACCTL_GMODE;
2751 macctl |= B43_MACCTL_INFRA;
2752 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2753
2754 err = b43_request_firmware(dev);
2755 if (err)
2756 goto out;
2757 err = b43_upload_microcode(dev);
2758 if (err)
2759 goto out; /* firmware is released later */
2760
2761 err = b43_gpio_init(dev);
2762 if (err)
2763 goto out; /* firmware is released later */
21954c36 2764
e4d6b795
MB		 2765 err = b43_upload_initvals(dev);
2766 if (err)
1a8d1227 2767 goto err_gpio_clean;
e4d6b795 2768
0b7dcd96
MB		 2769 /* Turn the Analog on and initialize the PHY. */
2770 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2771 err = b43_phy_init(dev);
2772 if (err)
ef1a628d 2773 goto err_gpio_clean;
e4d6b795 2774
ef1a628d
MB		 2775 /* Disable Interference Mitigation. */
2776 if (phy->ops->interf_mitigation)
2777 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2778
ef1a628d
MB		 2779 /* Select the antennae */
2780 if (phy->ops->set_rx_antenna)
2781 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2782 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2783
2784 if (phy->type == B43_PHYTYPE_B) {
2785 value16 = b43_read16(dev, 0x005E);
2786 value16 |= 0x0004;
2787 b43_write16(dev, 0x005E, value16);
2788 }
2789 b43_write32(dev, 0x0100, 0x01000000);
2790 if (dev->dev->id.revision < 5)
2791 b43_write32(dev, 0x010C, 0x01000000);
2792
2793 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2794 & ~B43_MACCTL_INFRA);
2795 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2796 | B43_MACCTL_INFRA);
e4d6b795 2797
e4d6b795
MB		 2798 /* Probe Response Timeout value */
2799 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2800 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2801
2802 /* Initially set the wireless operation mode. */
2803 b43_adjust_opmode(dev);
2804
2805 if (dev->dev->id.revision < 3) {
2806 b43_write16(dev, 0x060E, 0x0000);
2807 b43_write16(dev, 0x0610, 0x8000);
2808 b43_write16(dev, 0x0604, 0x0000);
2809 b43_write16(dev, 0x0606, 0x0200);
2810 } else {
2811 b43_write32(dev, 0x0188, 0x80000000);
2812 b43_write32(dev, 0x018C, 0x02000000);
2813 }
2814 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2815 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2816 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2817 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2818 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2819 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2820 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2821
2822 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2823 value32 |= 0x00100000;
2824 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2825
2826 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2827 dev->dev->bus->chipco.fast_pwrup_delay);
2828
2829 err = 0;
2830 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2831out:
e4d6b795
MB		 2832 return err;
2833
1a8d1227 2834err_gpio_clean:
e4d6b795 2835 b43_gpio_cleanup(dev);
21954c36 2836 return err;
e4d6b795
MB		 2837}
2838
e4d6b795
MB		 2839static void b43_periodic_every60sec(struct b43_wldev *dev)
2840{
ef1a628d 2841 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2842
ef1a628d
MB		 2843 if (ops->pwork_60sec)
2844 ops->pwork_60sec(dev);
18c8adeb
MB		 2845
2846 /* Force check the TX power emission now. */
2847 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2848}
2849
2850static void b43_periodic_every30sec(struct b43_wldev *dev)
2851{
2852 /* Update device statistics. */
2853 b43_calculate_link_quality(dev);
2854}
2855
2856static void b43_periodic_every15sec(struct b43_wldev *dev)
2857{
2858 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2859 u16 wdr;
2860
2861 if (dev->fw.opensource) {
2862 /* Check if the firmware is still alive.
2863 * It will reset the watchdog counter to 0 in its idle loop. */
2864 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2865 if (unlikely(wdr)) {
2866 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2867 b43_controller_restart(dev, "Firmware watchdog");
2868 return;
2869 } else {
2870 b43_shm_write16(dev, B43_SHM_SCRATCH,
2871 B43_WATCHDOG_REG, 1);
2872 }
2873 }
e4d6b795 2874
ef1a628d
MB		 2875 if (phy->ops->pwork_15sec)
2876 phy->ops->pwork_15sec(dev);
2877
00e0b8cb
SB		 2878 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2879 wmb();
e4d6b795
MB		 2880}
2881
e4d6b795
MB		 2882static void do_periodic_work(struct b43_wldev *dev)
2883{
2884 unsigned int state;
2885
2886 state = dev->periodic_state;
42bb4cd5 2887 if (state % 4 == 0)
e4d6b795 2888 b43_periodic_every60sec(dev);
42bb4cd5 2889 if (state % 2 == 0)
e4d6b795 2890 b43_periodic_every30sec(dev);
42bb4cd5 2891 b43_periodic_every15sec(dev);
e4d6b795
MB		 2892}
2893
05b64b36
MB		 2894/* Periodic work locking policy:
2895 * The whole periodic work handler is protected by
2896 * wl->mutex. If another lock is needed somewhere in the
2897 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2898 */
e4d6b795
MB		 2899static void b43_periodic_work_handler(struct work_struct *work)
2900{
05b64b36
MB		 2901 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2902 periodic_work.work);
2903 struct b43_wl *wl = dev->wl;
2904 unsigned long delay;
e4d6b795 2905
05b64b36 2906 mutex_lock(&wl->mutex);
e4d6b795
MB		 2907
2908 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2909 goto out;
2910 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2911 goto out_requeue;
2912
05b64b36 2913 do_periodic_work(dev);
e4d6b795 2914
e4d6b795 2915 dev->periodic_state++;
42bb4cd5 2916out_requeue:
e4d6b795
MB		 2917 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2918 delay = msecs_to_jiffies(50);
2919 else
82cd682d 2920 delay = round_jiffies_relative(HZ * 15);
42935eca 2921 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 2922out:
05b64b36 2923 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2924}
2925
2926static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2927{
2928 struct delayed_work *work = &dev->periodic_work;
2929
2930 dev->periodic_state = 0;
2931 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 2932 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 2933}
2934
f3dd3fcc 2935/* Check if communication with the device works correctly. */
e4d6b795
MB		 2936static int b43_validate_chipaccess(struct b43_wldev *dev)
2937{
f62ae6cd 2938 u32 v, backup0, backup4;
e4d6b795 2939
f62ae6cd
MB		 2940 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2941 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 2942
2943 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2944 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2945 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2946 goto error;
f3dd3fcc
MB		 2947 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2948 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2949 goto error;
2950
f62ae6cd
MB		 2951 /* Check if unaligned 32bit SHM_SHARED access works properly.
2952 * However, don't bail out on failure, because it's noncritical. */
2953 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
2954 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
2955 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
2956 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
2957 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
2958 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
2959 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
2960 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
2961 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
2962 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
2963 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
2964 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
2965
2966 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
2967 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 2968
2969 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2970 /* The 32bit register shadows the two 16bit registers
2971 * with update sideeffects. Validate this. */
2972 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2973 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2974 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2975 goto error;
2976 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2977 goto error;
2978 }
2979 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2980
2981 v = b43_read32(dev, B43_MMIO_MACCTL);
2982 v |= B43_MACCTL_GMODE;
2983 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2984 goto error;
2985
2986 return 0;
f3dd3fcc 2987error:
e4d6b795
MB		 2988 b43err(dev->wl, "Failed to validate the chipaccess\n");
2989 return -ENODEV;
2990}
2991
2992static void b43_security_init(struct b43_wldev *dev)
2993{
e4d6b795
MB		 2994 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2995 /* KTP is a word address, but we address SHM bytewise.
2996 * So multiply by two.
2997 */
2998 dev->ktp *= 2;
66d2d089
MB		 2999 /* Number of RCMTA address slots */
3000 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3001 /* Clear the key memory. */
e4d6b795
MB		 3002 b43_clear_keys(dev);
3003}
3004
616de35d 3005#ifdef CONFIG_B43_HWRNG
99da185a 3006static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3007{
3008 struct b43_wl *wl = (struct b43_wl *)rng->priv;
e4d6b795 3009
36dbd954
MB		 3010 /* FIXME: We need to take wl->mutex here to make sure the device
3011 * is not going away from under our ass. However it could deadlock
3012 * with hwrng internal locking. */
e4d6b795 3013
e4d6b795 3014 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
e4d6b795
MB		 3015
3016 return (sizeof(u16));
3017}
616de35d 3018#endif /* CONFIG_B43_HWRNG */
e4d6b795 3019
b844eba2 3020static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3021{
616de35d 3022#ifdef CONFIG_B43_HWRNG
e4d6b795 3023 if (wl->rng_initialized)
b844eba2 3024 hwrng_unregister(&wl->rng);
616de35d 3025#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3026}
3027
3028static int b43_rng_init(struct b43_wl *wl)
3029{
616de35d 3030 int err = 0;
e4d6b795 3031
616de35d 3032#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3033 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3034 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3035 wl->rng.name = wl->rng_name;
3036 wl->rng.data_read = b43_rng_read;
3037 wl->rng.priv = (unsigned long)wl;
3038 wl->rng_initialized = 1;
3039 err = hwrng_register(&wl->rng);
3040 if (err) {
3041 wl->rng_initialized = 0;
3042 b43err(wl, "Failed to register the random "
3043 "number generator (%d)\n", err);
3044 }
616de35d 3045#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3046
3047 return err;
3048}
3049
f5d40eed 3050static void b43_tx_work(struct work_struct *work)
e4d6b795 3051{
f5d40eed
MB		 3052 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3053 struct b43_wldev *dev;
3054 struct sk_buff *skb;
3055 int err = 0;
e4d6b795 3056
f5d40eed
MB		 3057 mutex_lock(&wl->mutex);
3058 dev = wl->current_dev;
3059 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3060 mutex_unlock(&wl->mutex);
3061 return;
5100d5ac 3062 }
21a75d77 3063
f5d40eed
MB		 3064 while (skb_queue_len(&wl->tx_queue)) {
3065 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3066
21a75d77 3067 if (b43_using_pio_transfers(dev))
e039fa4a 3068 err = b43_pio_tx(dev, skb);
21a75d77 3069 else
e039fa4a 3070 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3071 if (unlikely(err))
3072 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3073 }
3074
f5d40eed
MB		 3075 mutex_unlock(&wl->mutex);
3076}
21a75d77 3077
f5d40eed
MB		 3078static int b43_op_tx(struct ieee80211_hw *hw,
3079 struct sk_buff *skb)
3080{
3081 struct b43_wl *wl = hw_to_b43_wl(hw);
3082
3083 if (unlikely(skb->len < 2 + 2 + 6)) {
3084 /* Too short, this can't be a valid frame. */
3085 dev_kfree_skb_any(skb);
3086 return NETDEV_TX_OK;
3087 }
3088 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3089
3090 skb_queue_tail(&wl->tx_queue, skb);
3091 ieee80211_queue_work(wl->hw, &wl->tx_work);
c9e8eae0 3092
e4d6b795
MB		 3093 return NETDEV_TX_OK;
3094}
3095
e6f5b934
MB		 3096static void b43_qos_params_upload(struct b43_wldev *dev,
3097 const struct ieee80211_tx_queue_params *p,
3098 u16 shm_offset)
3099{
3100 u16 params[B43_NR_QOSPARAMS];
0b57664c 3101 int bslots, tmp;
e6f5b934
MB		 3102 unsigned int i;
3103
b0544eb6
MB		 3104 if (!dev->qos_enabled)
3105 return;
3106
0b57664c 3107 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3108
3109 memset(&params, 0, sizeof(params));
3110
3111 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3112 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3113 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3114 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3115 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3116 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3117 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3118
3119 for (i = 0; i < ARRAY_SIZE(params); i++) {
3120 if (i == B43_QOSPARAM_STATUS) {
3121 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3122 shm_offset + (i * 2));
3123 /* Mark the parameters as updated. */
3124 tmp |= 0x100;
3125 b43_shm_write16(dev, B43_SHM_SHARED,
3126 shm_offset + (i * 2),
3127 tmp);
3128 } else {
3129 b43_shm_write16(dev, B43_SHM_SHARED,
3130 shm_offset + (i * 2),
3131 params[i]);
3132 }
3133 }
3134}
3135
c40c1129
MB		 3136/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3137static const u16 b43_qos_shm_offsets[] = {
3138 /* [mac80211-queue-nr] = SHM_OFFSET, */
3139 [0] = B43_QOS_VOICE,
3140 [1] = B43_QOS_VIDEO,
3141 [2] = B43_QOS_BESTEFFORT,
3142 [3] = B43_QOS_BACKGROUND,
3143};
3144
5a5f3b40
MB		 3145/* Update all QOS parameters in hardware. */
3146static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3147{
3148 struct b43_wl *wl = dev->wl;
3149 struct b43_qos_params *params;
e6f5b934
MB		 3150 unsigned int i;
3151
b0544eb6
MB		 3152 if (!dev->qos_enabled)
3153 return;
3154
c40c1129
MB		 3155 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3156 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3157
3158 b43_mac_suspend(dev);
e6f5b934
MB		 3159 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3160 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3161 b43_qos_params_upload(dev, &(params->p),
3162 b43_qos_shm_offsets[i]);
e6f5b934 3163 }
e6f5b934
MB		 3164 b43_mac_enable(dev);
3165}
3166
3167static void b43_qos_clear(struct b43_wl *wl)
3168{
3169 struct b43_qos_params *params;
3170 unsigned int i;
3171
c40c1129
MB		 3172 /* Initialize QoS parameters to sane defaults. */
3173
3174 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3175 ARRAY_SIZE(wl->qos_params));
3176
e6f5b934
MB		 3177 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3178 params = &(wl->qos_params[i]);
3179
c40c1129
MB		 3180 switch (b43_qos_shm_offsets[i]) {
3181 case B43_QOS_VOICE:
3182 params->p.txop = 0;
3183 params->p.aifs = 2;
3184 params->p.cw_min = 0x0001;
3185 params->p.cw_max = 0x0001;
3186 break;
3187 case B43_QOS_VIDEO:
3188 params->p.txop = 0;
3189 params->p.aifs = 2;
3190 params->p.cw_min = 0x0001;
3191 params->p.cw_max = 0x0001;
3192 break;
3193 case B43_QOS_BESTEFFORT:
3194 params->p.txop = 0;
3195 params->p.aifs = 3;
3196 params->p.cw_min = 0x0001;
3197 params->p.cw_max = 0x03FF;
3198 break;
3199 case B43_QOS_BACKGROUND:
3200 params->p.txop = 0;
3201 params->p.aifs = 7;
3202 params->p.cw_min = 0x0001;
3203 params->p.cw_max = 0x03FF;
3204 break;
3205 default:
3206 B43_WARN_ON(1);
3207 }
e6f5b934
MB		 3208 }
3209}
3210
3211/* Initialize the core's QOS capabilities */
3212static void b43_qos_init(struct b43_wldev *dev)
3213{
b0544eb6
MB		 3214 if (!dev->qos_enabled) {
3215 /* Disable QOS support. */
3216 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3217 b43_write16(dev, B43_MMIO_IFSCTL,
3218 b43_read16(dev, B43_MMIO_IFSCTL)
3219 & ~B43_MMIO_IFSCTL_USE_EDCF);
3220 b43dbg(dev->wl, "QoS disabled\n");
3221 return;
3222 }
3223
e6f5b934 3224 /* Upload the current QOS parameters. */
5a5f3b40 3225 b43_qos_upload_all(dev);
e6f5b934
MB		 3226
3227 /* Enable QOS support. */
3228 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3229 b43_write16(dev, B43_MMIO_IFSCTL,
3230 b43_read16(dev, B43_MMIO_IFSCTL)
3231 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3232 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3233}
3234
e100bb64 3235static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3236 const struct ieee80211_tx_queue_params *params)
e4d6b795 3237{
e6f5b934 3238 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3239 struct b43_wldev *dev;
e6f5b934 3240 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3241 int err = -ENODEV;
e6f5b934
MB		 3242
3243 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3244 /* Queue not available or don't support setting
3245 * params on this queue. Return success to not
3246 * confuse mac80211. */
3247 return 0;
3248 }
5a5f3b40
MB		 3249 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3250 ARRAY_SIZE(wl->qos_params));
e6f5b934 3251
5a5f3b40
MB		 3252 mutex_lock(&wl->mutex);
3253 dev = wl->current_dev;
3254 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3255 goto out_unlock;
e6f5b934 3256
5a5f3b40
MB		 3257 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3258 b43_mac_suspend(dev);
3259 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3260 b43_qos_shm_offsets[queue]);
3261 b43_mac_enable(dev);
3262 err = 0;
e6f5b934 3263
5a5f3b40
MB		 3264out_unlock:
3265 mutex_unlock(&wl->mutex);
3266
3267 return err;
e4d6b795
MB		 3268}
3269
40faacc4
MB		 3270static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3271 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3272{
3273 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3274 struct b43_wldev *dev;
e4d6b795
MB		 3275 int err = -ENODEV;
3276
36dbd954
MB		 3277 mutex_lock(&wl->mutex);
3278 dev = wl->current_dev;
3279 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
5100d5ac
MB		 3280 if (b43_using_pio_transfers(dev))
3281 b43_pio_get_tx_stats(dev, stats);
3282 else
3283 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3284 err = 0;
3285 }
36dbd954
MB		 3286 mutex_unlock(&wl->mutex);
3287
e4d6b795
MB		 3288 return err;
3289}
3290
40faacc4
MB		 3291static int b43_op_get_stats(struct ieee80211_hw *hw,
3292 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3293{
3294 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3295
36dbd954 3296 mutex_lock(&wl->mutex);
e4d6b795 3297 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3298 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3299
3300 return 0;
3301}
3302
08e87a83
AF		 3303static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3304{
3305 struct b43_wl *wl = hw_to_b43_wl(hw);
3306 struct b43_wldev *dev;
3307 u64 tsf;
3308
3309 mutex_lock(&wl->mutex);
08e87a83
AF		 3310 dev = wl->current_dev;
3311
3312 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3313 b43_tsf_read(dev, &tsf);
3314 else
3315 tsf = 0;
3316
08e87a83
AF		 3317 mutex_unlock(&wl->mutex);
3318
3319 return tsf;
3320}
3321
3322static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3323{
3324 struct b43_wl *wl = hw_to_b43_wl(hw);
3325 struct b43_wldev *dev;
3326
3327 mutex_lock(&wl->mutex);
08e87a83
AF		 3328 dev = wl->current_dev;
3329
3330 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3331 b43_tsf_write(dev, tsf);
3332
08e87a83
AF		 3333 mutex_unlock(&wl->mutex);
3334}
3335
e4d6b795
MB		 3336static void b43_put_phy_into_reset(struct b43_wldev *dev)
3337{
3338 struct ssb_device *sdev = dev->dev;
3339 u32 tmslow;
3340
3341 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3342 tmslow &= ~B43_TMSLOW_GMODE;
3343 tmslow |= B43_TMSLOW_PHYRESET;
3344 tmslow |= SSB_TMSLOW_FGC;
3345 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3346 msleep(1);
3347
3348 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3349 tmslow &= ~SSB_TMSLOW_FGC;
3350 tmslow |= B43_TMSLOW_PHYRESET;
3351 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3352 msleep(1);
3353}
3354
99da185a 3355static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3356{
3357 switch (band) {
3358 case IEEE80211_BAND_5GHZ:
3359 return "5";
3360 case IEEE80211_BAND_2GHZ:
3361 return "2.4";
3362 default:
3363 break;
3364 }
3365 B43_WARN_ON(1);
3366 return "";
3367}
3368
e4d6b795 3369/* Expects wl->mutex locked */
bb1eeff1 3370static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3371{
bb1eeff1 3372 struct b43_wldev *up_dev = NULL;
e4d6b795 3373 struct b43_wldev *down_dev;
bb1eeff1 3374 struct b43_wldev *d;
e4d6b795 3375 int err;
922d8a0b 3376 bool uninitialized_var(gmode);
e4d6b795
MB		 3377 int prev_status;
3378
bb1eeff1
MB		 3379 /* Find a device and PHY which supports the band. */
3380 list_for_each_entry(d, &wl->devlist, list) {
3381 switch (chan->band) {
3382 case IEEE80211_BAND_5GHZ:
3383 if (d->phy.supports_5ghz) {
3384 up_dev = d;
3385 gmode = 0;
3386 }
3387 break;
3388 case IEEE80211_BAND_2GHZ:
3389 if (d->phy.supports_2ghz) {
3390 up_dev = d;
3391 gmode = 1;
3392 }
3393 break;
3394 default:
3395 B43_WARN_ON(1);
3396 return -EINVAL;
3397 }
3398 if (up_dev)
3399 break;
3400 }
3401 if (!up_dev) {
3402 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3403 band_to_string(chan->band));
3404 return -ENODEV;
e4d6b795
MB		 3405 }
3406 if ((up_dev == wl->current_dev) &&
3407 (!!wl->current_dev->phy.gmode == !!gmode)) {
3408 /* This device is already running. */
3409 return 0;
3410 }
bb1eeff1
MB		 3411 b43dbg(wl, "Switching to %s-GHz band\n",
3412 band_to_string(chan->band));
e4d6b795
MB		 3413 down_dev = wl->current_dev;
3414
3415 prev_status = b43_status(down_dev);
3416 /* Shutdown the currently running core. */
3417 if (prev_status >= B43_STAT_STARTED)
36dbd954 3418 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3419 if (prev_status >= B43_STAT_INITIALIZED)
3420 b43_wireless_core_exit(down_dev);
3421
3422 if (down_dev != up_dev) {
3423 /* We switch to a different core, so we put PHY into
3424 * RESET on the old core. */
3425 b43_put_phy_into_reset(down_dev);
3426 }
3427
3428 /* Now start the new core. */
3429 up_dev->phy.gmode = gmode;
3430 if (prev_status >= B43_STAT_INITIALIZED) {
3431 err = b43_wireless_core_init(up_dev);
3432 if (err) {
3433 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3434 "selected %s-GHz band\n",
3435 band_to_string(chan->band));
e4d6b795
MB		 3436 goto init_failure;
3437 }
3438 }
3439 if (prev_status >= B43_STAT_STARTED) {
3440 err = b43_wireless_core_start(up_dev);
3441 if (err) {
3442 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3443 "selected %s-GHz band\n",
3444 band_to_string(chan->band));
e4d6b795
MB		 3445 b43_wireless_core_exit(up_dev);
3446 goto init_failure;
3447 }
3448 }
3449 B43_WARN_ON(b43_status(up_dev) != prev_status);
3450
3451 wl->current_dev = up_dev;
3452
3453 return 0;
bb1eeff1 3454init_failure:
e4d6b795
MB		 3455 /* Whoops, failed to init the new core. No core is operating now. */
3456 wl->current_dev = NULL;
3457 return err;
3458}
3459
9124b077
JB		 3460/* Write the short and long frame retry limit values. */
3461static void b43_set_retry_limits(struct b43_wldev *dev,
3462 unsigned int short_retry,
3463 unsigned int long_retry)
3464{
3465 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3466 * the chip-internal counter. */
3467 short_retry = min(short_retry, (unsigned int)0xF);
3468 long_retry = min(long_retry, (unsigned int)0xF);
3469
3470 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3471 short_retry);
3472 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3473 long_retry);
3474}
3475
e8975581 3476static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3477{
3478 struct b43_wl *wl = hw_to_b43_wl(hw);
3479 struct b43_wldev *dev;
3480 struct b43_phy *phy;
e8975581 3481 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3482 int antenna;
e4d6b795 3483 int err = 0;
e4d6b795 3484
e4d6b795
MB		 3485 mutex_lock(&wl->mutex);
3486
bb1eeff1
MB		 3487 /* Switch the band (if necessary). This might change the active core. */
3488 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3489 if (err)
3490 goto out_unlock_mutex;
3491 dev = wl->current_dev;
3492 phy = &dev->phy;
3493
d10d0e57
MB		 3494 b43_mac_suspend(dev);
3495
9124b077
JB		 3496 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3497 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3498 conf->long_frame_max_tx_count);
3499 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3500 if (!changed)
d10d0e57 3501 goto out_mac_enable;
e4d6b795
MB		 3502
3503 /* Switch to the requested channel.
3504 * The firmware takes care of races with the TX handler. */
8318d78a 3505 if (conf->channel->hw_value != phy->channel)
ef1a628d 3506 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3507
d42ce84a
JB		 3508 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3509
e4d6b795
MB		 3510 /* Adjust the desired TX power level. */
3511 if (conf->power_level != 0) {
18c8adeb
MB		 3512 if (conf->power_level != phy->desired_txpower) {
3513 phy->desired_txpower = conf->power_level;
3514 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3515 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3516 }
3517 }
3518
3519 /* Antennas for RX and management frame TX. */
0f4ac38b 3520 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3521 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3522 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3523 if (phy->ops->set_rx_antenna)
3524 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3525
fd4973c5
LF		 3526 if (wl->radio_enabled != phy->radio_on) {
3527 if (wl->radio_enabled) {
19d337df 3528 b43_software_rfkill(dev, false);
fda9abcf
MB		 3529 b43info(dev->wl, "Radio turned on by software\n");
3530 if (!dev->radio_hw_enable) {
3531 b43info(dev->wl, "The hardware RF-kill button "
3532 "still turns the radio physically off. "
3533 "Press the button to turn it on.\n");
3534 }
3535 } else {
19d337df 3536 b43_software_rfkill(dev, true);
fda9abcf
MB		 3537 b43info(dev->wl, "Radio turned off by software\n");
3538 }
3539 }
3540
d10d0e57
MB		 3541out_mac_enable:
3542 b43_mac_enable(dev);
3543out_unlock_mutex:
e4d6b795
MB		 3544 mutex_unlock(&wl->mutex);
3545
3546 return err;
3547}
3548
881d948c 3549static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3550{
3551 struct ieee80211_supported_band *sband =
3552 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3553 struct ieee80211_rate *rate;
3554 int i;
3555 u16 basic, direct, offset, basic_offset, rateptr;
3556
3557 for (i = 0; i < sband->n_bitrates; i++) {
3558 rate = &sband->bitrates[i];
3559
3560 if (b43_is_cck_rate(rate->hw_value)) {
3561 direct = B43_SHM_SH_CCKDIRECT;
3562 basic = B43_SHM_SH_CCKBASIC;
3563 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3564 offset &= 0xF;
3565 } else {
3566 direct = B43_SHM_SH_OFDMDIRECT;
3567 basic = B43_SHM_SH_OFDMBASIC;
3568 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3569 offset &= 0xF;
3570 }
3571
3572 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3573
3574 if (b43_is_cck_rate(rate->hw_value)) {
3575 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3576 basic_offset &= 0xF;
3577 } else {
3578 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3579 basic_offset &= 0xF;
3580 }
3581
3582 /*
3583 * Get the pointer that we need to point to
3584 * from the direct map
3585 */
3586 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3587 direct + 2 * basic_offset);
3588 /* and write it to the basic map */
3589 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3590 rateptr);
3591 }
3592}
3593
3594static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3595 struct ieee80211_vif *vif,
3596 struct ieee80211_bss_conf *conf,
3597 u32 changed)
3598{
3599 struct b43_wl *wl = hw_to_b43_wl(hw);
3600 struct b43_wldev *dev;
c7ab5ef9
JB		 3601
3602 mutex_lock(&wl->mutex);
3603
3604 dev = wl->current_dev;
d10d0e57 3605 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3606 goto out_unlock_mutex;
2d0ddec5
JB		 3607
3608 B43_WARN_ON(wl->vif != vif);
3609
3610 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3611 if (conf->bssid)
3612 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3613 else
3614 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3615 }
2d0ddec5 3616
3f0d843b
JB		 3617 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3618 if (changed & BSS_CHANGED_BEACON &&
3619 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3620 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3621 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3622 b43_update_templates(wl);
3623
3624 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3625 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3626 }
3627
c7ab5ef9
JB		 3628 b43_mac_suspend(dev);
3629
57c4d7b4
JB		 3630 /* Update templates for AP/mesh mode. */
3631 if (changed & BSS_CHANGED_BEACON_INT &&
3632 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3633 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3634 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3635 b43_set_beacon_int(dev, conf->beacon_int);
3636
c7ab5ef9
JB		 3637 if (changed & BSS_CHANGED_BASIC_RATES)
3638 b43_update_basic_rates(dev, conf->basic_rates);
3639
3640 if (changed & BSS_CHANGED_ERP_SLOT) {
3641 if (conf->use_short_slot)
3642 b43_short_slot_timing_enable(dev);
3643 else
3644 b43_short_slot_timing_disable(dev);
3645 }
3646
3647 b43_mac_enable(dev);
d10d0e57 3648out_unlock_mutex:
c7ab5ef9 3649 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3650}
3651
40faacc4 3652static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3653 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3654 struct ieee80211_key_conf *key)
e4d6b795
MB		 3655{
3656 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3657 struct b43_wldev *dev;
e4d6b795
MB		 3658 u8 algorithm;
3659 u8 index;
c6dfc9a8 3660 int err;
060210f9 3661 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3662
3663 if (modparam_nohwcrypt)
3664 return -ENOSPC; /* User disabled HW-crypto */
3665
c6dfc9a8 3666 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3667
3668 dev = wl->current_dev;
3669 err = -ENODEV;
3670 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3671 goto out_unlock;
3672
403a3a13 3673 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3674 /* We don't have firmware for the crypto engine.
3675 * Must use software-crypto. */
3676 err = -EOPNOTSUPP;
3677 goto out_unlock;
3678 }
3679
c6dfc9a8 3680 err = -EINVAL;
e4d6b795 3681 switch (key->alg) {
e4d6b795 3682 case ALG_WEP:
e31a16d6 3683 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3684 algorithm = B43_SEC_ALGO_WEP40;
3685 else
3686 algorithm = B43_SEC_ALGO_WEP104;
3687 break;
3688 case ALG_TKIP:
3689 algorithm = B43_SEC_ALGO_TKIP;
3690 break;
3691 case ALG_CCMP:
3692 algorithm = B43_SEC_ALGO_AES;
3693 break;
3694 default:
3695 B43_WARN_ON(1);
c6dfc9a8 3696 goto out_unlock;
e4d6b795 3697 }
e4d6b795
MB		 3698 index = (u8) (key->keyidx);
3699 if (index > 3)
e4d6b795 3700 goto out_unlock;
e4d6b795
MB		 3701
3702 switch (cmd) {
3703 case SET_KEY:
035d0243 3704 if (algorithm == B43_SEC_ALGO_TKIP &&
3705 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3706 !modparam_hwtkip)) {
3707 /* We support only pairwise key */
e4d6b795
MB		 3708 err = -EOPNOTSUPP;
3709 goto out_unlock;
3710 }
3711
e808e586 3712 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3713 if (WARN_ON(!sta)) {
3714 err = -EOPNOTSUPP;
3715 goto out_unlock;
3716 }
e808e586 3717 /* Pairwise key with an assigned MAC address. */
e4d6b795 3718 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3719 key->key, key->keylen,
3720 sta->addr, key);
e808e586
MB		 3721 } else {
3722 /* Group key */
3723 err = b43_key_write(dev, index, algorithm,
3724 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3725 }
3726 if (err)
3727 goto out_unlock;
3728
3729 if (algorithm == B43_SEC_ALGO_WEP40 ||
3730 algorithm == B43_SEC_ALGO_WEP104) {
3731 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3732 } else {
3733 b43_hf_write(dev,
3734 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3735 }
3736 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3737 if (algorithm == B43_SEC_ALGO_TKIP)
3738 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3739 break;
3740 case DISABLE_KEY: {
3741 err = b43_key_clear(dev, key->hw_key_idx);
3742 if (err)
3743 goto out_unlock;
3744 break;
3745 }
3746 default:
3747 B43_WARN_ON(1);
3748 }
9cf7f247 3749
e4d6b795 3750out_unlock:
e4d6b795
MB		 3751 if (!err) {
3752 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3753 "mac: %pM\n",
e4d6b795 3754 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3755 sta ? sta->addr : bcast_addr);
9cf7f247 3756 b43_dump_keymemory(dev);
e4d6b795 3757 }
9cf7f247
MB		 3758 mutex_unlock(&wl->mutex);
3759
e4d6b795
MB		 3760 return err;
3761}
3762
40faacc4
MB		 3763static void b43_op_configure_filter(struct ieee80211_hw *hw,
3764 unsigned int changed, unsigned int *fflags,
3ac64bee 3765 u64 multicast)
e4d6b795
MB		 3766{
3767 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3768 struct b43_wldev *dev;
e4d6b795 3769
36dbd954
MB		 3770 mutex_lock(&wl->mutex);
3771 dev = wl->current_dev;
4150c572
JB		 3772 if (!dev) {
3773 *fflags = 0;
36dbd954 3774 goto out_unlock;
e4d6b795 3775 }
4150c572 3776
4150c572
JB		 3777 *fflags &= FIF_PROMISC_IN_BSS |
3778 FIF_ALLMULTI |
3779 FIF_FCSFAIL |
3780 FIF_PLCPFAIL |
3781 FIF_CONTROL |
3782 FIF_OTHER_BSS |
3783 FIF_BCN_PRBRESP_PROMISC;
3784
3785 changed &= FIF_PROMISC_IN_BSS |
3786 FIF_ALLMULTI |
3787 FIF_FCSFAIL |
3788 FIF_PLCPFAIL |
3789 FIF_CONTROL |
3790 FIF_OTHER_BSS |
3791 FIF_BCN_PRBRESP_PROMISC;
3792
3793 wl->filter_flags = *fflags;
3794
3795 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3796 b43_adjust_opmode(dev);
36dbd954
MB		 3797
3798out_unlock:
3799 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3800}
3801
36dbd954
MB		 3802/* Locking: wl->mutex
3803 * Returns the current dev. This might be different from the passed in dev,
3804 * because the core might be gone away while we unlocked the mutex. */
3805static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 3806{
3807 struct b43_wl *wl = dev->wl;
36dbd954 3808 struct b43_wldev *orig_dev;
e4d6b795 3809
36dbd954
MB		 3810redo:
3811 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3812 return dev;
a19d12d7 3813
f5d40eed 3814 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 3815 mutex_unlock(&wl->mutex);
3816 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 3817 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 3818 mutex_lock(&wl->mutex);
3819 dev = wl->current_dev;
3820 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3821 /* Whoops, aliens ate up the device while we were unlocked. */
3822 return dev;
3823 }
a19d12d7 3824
36dbd954 3825 /* Disable interrupts on the device. */
e4d6b795 3826 b43_set_status(dev, B43_STAT_INITIALIZED);
36dbd954
MB		 3827 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
3828 /* wl->mutex is locked. That is enough. */
3829 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3830 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3831 } else {
3832 spin_lock_irq(&wl->hardirq_lock);
3833 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3834 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3835 spin_unlock_irq(&wl->hardirq_lock);
3836 }
3837 /* Synchronize the interrupt handlers. Unlock to avoid deadlocks. */
3838 orig_dev = dev;
e4d6b795 3839 mutex_unlock(&wl->mutex);
36dbd954 3840 synchronize_irq(dev->dev->irq);
e4d6b795 3841 mutex_lock(&wl->mutex);
36dbd954
MB		 3842 dev = wl->current_dev;
3843 if (!dev)
3844 return dev;
3845 if (dev != orig_dev) {
3846 if (b43_status(dev) >= B43_STAT_STARTED)
3847 goto redo;
3848 return dev;
3849 }
3850 B43_WARN_ON(b43_read32(dev, B43_MMIO_GEN_IRQ_MASK));
e4d6b795 3851
f5d40eed
MB		 3852 /* Drain the TX queue */
3853 while (skb_queue_len(&wl->tx_queue))
3854 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3855
e4d6b795
MB		 3856 b43_mac_suspend(dev);
3857 free_irq(dev->dev->irq, dev);
3858 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 3859
3860 return dev;
e4d6b795
MB		 3861}
3862
3863/* Locking: wl->mutex */
3864static int b43_wireless_core_start(struct b43_wldev *dev)
3865{
3866 int err;
3867
3868 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3869
3870 drain_txstatus_queue(dev);
36dbd954
MB		 3871 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3872 b43_interrupt_thread_handler,
3873 IRQF_SHARED, KBUILD_MODNAME, dev);
e4d6b795
MB		 3874 if (err) {
3875 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3876 goto out;
3877 }
3878
3879 /* We are ready to run. */
3880 b43_set_status(dev, B43_STAT_STARTED);
3881
3882 /* Start data flow (TX/RX). */
3883 b43_mac_enable(dev);
13790728 3884 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3885
3886 /* Start maintainance work */
3887 b43_periodic_tasks_setup(dev);
3888
3889 b43dbg(dev->wl, "Wireless interface started\n");
3890 out:
3891 return err;
3892}
3893
3894/* Get PHY and RADIO versioning numbers */
3895static int b43_phy_versioning(struct b43_wldev *dev)
3896{
3897 struct b43_phy *phy = &dev->phy;
3898 u32 tmp;
3899 u8 analog_type;
3900 u8 phy_type;
3901 u8 phy_rev;
3902 u16 radio_manuf;
3903 u16 radio_ver;
3904 u16 radio_rev;
3905 int unsupported = 0;
3906
3907 /* Get PHY versioning */
3908 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3909 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3910 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3911 phy_rev = (tmp & B43_PHYVER_VERSION);
3912 switch (phy_type) {
3913 case B43_PHYTYPE_A:
3914 if (phy_rev >= 4)
3915 unsupported = 1;
3916 break;
3917 case B43_PHYTYPE_B:
3918 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3919 && phy_rev != 7)
3920 unsupported = 1;
3921 break;
3922 case B43_PHYTYPE_G:
013978b6 3923 if (phy_rev > 9)
e4d6b795
MB		 3924 unsupported = 1;
3925 break;
d5c71e46
MB		 3926#ifdef CONFIG_B43_NPHY
3927 case B43_PHYTYPE_N:
bb519bee 3928 if (phy_rev > 4)
d5c71e46
MB		 3929 unsupported = 1;
3930 break;
6b1c7c67
MB		 3931#endif
3932#ifdef CONFIG_B43_PHY_LP
3933 case B43_PHYTYPE_LP:
9d86a2d5 3934 if (phy_rev > 2)
6b1c7c67
MB		 3935 unsupported = 1;
3936 break;
d5c71e46 3937#endif
e4d6b795
MB		 3938 default:
3939 unsupported = 1;
3940 };
3941 if (unsupported) {
3942 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3943 "(Analog %u, Type %u, Revision %u)\n",
3944 analog_type, phy_type, phy_rev);
3945 return -EOPNOTSUPP;
3946 }
3947 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3948 analog_type, phy_type, phy_rev);
3949
3950 /* Get RADIO versioning */
3951 if (dev->dev->bus->chip_id == 0x4317) {
3952 if (dev->dev->bus->chip_rev == 0)
3953 tmp = 0x3205017F;
3954 else if (dev->dev->bus->chip_rev == 1)
3955 tmp = 0x4205017F;
3956 else
3957 tmp = 0x5205017F;
3958 } else {
3959 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3960 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3961 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3962 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3963 }
3964 radio_manuf = (tmp & 0x00000FFF);
3965 radio_ver = (tmp & 0x0FFFF000) >> 12;
3966 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3967 if (radio_manuf != 0x17F /* Broadcom */)
3968 unsupported = 1;
e4d6b795
MB		 3969 switch (phy_type) {
3970 case B43_PHYTYPE_A:
3971 if (radio_ver != 0x2060)
3972 unsupported = 1;
3973 if (radio_rev != 1)
3974 unsupported = 1;
3975 if (radio_manuf != 0x17F)
3976 unsupported = 1;
3977 break;
3978 case B43_PHYTYPE_B:
3979 if ((radio_ver & 0xFFF0) != 0x2050)
3980 unsupported = 1;
3981 break;
3982 case B43_PHYTYPE_G:
3983 if (radio_ver != 0x2050)
3984 unsupported = 1;
3985 break;
96c755a3 3986 case B43_PHYTYPE_N:
bb519bee 3987 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3988 unsupported = 1;
3989 break;
6b1c7c67 3990 case B43_PHYTYPE_LP:
9d86a2d5 3991 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 3992 unsupported = 1;
3993 break;
e4d6b795
MB		 3994 default:
3995 B43_WARN_ON(1);
3996 }
3997 if (unsupported) {
3998 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3999 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4000 radio_manuf, radio_ver, radio_rev);
4001 return -EOPNOTSUPP;
4002 }
4003 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4004 radio_manuf, radio_ver, radio_rev);
4005
4006 phy->radio_manuf = radio_manuf;
4007 phy->radio_ver = radio_ver;
4008 phy->radio_rev = radio_rev;
4009
4010 phy->analog = analog_type;
4011 phy->type = phy_type;
4012 phy->rev = phy_rev;
4013
4014 return 0;
4015}
4016
4017static void setup_struct_phy_for_init(struct b43_wldev *dev,
4018 struct b43_phy *phy)
4019{
e4d6b795 4020 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4021 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4022 /* PHY TX errors counter. */
4023 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4024
4025#if B43_DEBUG
4026 phy->phy_locked = 0;
4027 phy->radio_locked = 0;
4028#endif
e4d6b795
MB		 4029}
4030
4031static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4032{
aa6c7ae2
MB		 4033 dev->dfq_valid = 0;
4034
6a724d68
MB		 4035 /* Assume the radio is enabled. If it's not enabled, the state will
4036 * immediately get fixed on the first periodic work run. */
4037 dev->radio_hw_enable = 1;
e4d6b795
MB		 4038
4039 /* Stats */
4040 memset(&dev->stats, 0, sizeof(dev->stats));
4041
4042 setup_struct_phy_for_init(dev, &dev->phy);
4043
4044 /* IRQ related flags */
4045 dev->irq_reason = 0;
4046 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4047 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4048 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4049 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4050
4051 dev->mac_suspended = 1;
4052
4053 /* Noise calculation context */
4054 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4055}
4056
4057static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4058{
4059 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4060 u64 hf;
e4d6b795 4061
1855ba78
MB		 4062 if (!modparam_btcoex)
4063 return;
95de2841 4064 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4065 return;
4066 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4067 return;
4068
4069 hf = b43_hf_read(dev);
95de2841 4070 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4071 hf |= B43_HF_BTCOEXALT;
4072 else
4073 hf |= B43_HF_BTCOEX;
4074 b43_hf_write(dev, hf);
e4d6b795
MB		 4075}
4076
4077static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4078{
4079 if (!modparam_btcoex)
4080 return;
4081 //TODO
e4d6b795
MB		 4082}
4083
4084static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4085{
4086#ifdef CONFIG_SSB_DRIVER_PCICORE
4087 struct ssb_bus *bus = dev->dev->bus;
4088 u32 tmp;
4089
4090 if (bus->pcicore.dev &&
4091 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4092 bus->pcicore.dev->id.revision <= 5) {
4093 /* IMCFGLO timeouts workaround. */
4094 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
e4d6b795
MB		 4095 switch (bus->bustype) {
4096 case SSB_BUSTYPE_PCI:
4097 case SSB_BUSTYPE_PCMCIA:
98a1e2a9
MB		 4098 tmp &= ~SSB_IMCFGLO_REQTO;
4099 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4100 tmp |= 0x32;
4101 break;
4102 case SSB_BUSTYPE_SSB:
98a1e2a9
MB		 4103 tmp &= ~SSB_IMCFGLO_REQTO;
4104 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4105 tmp |= 0x53;
4106 break;
98a1e2a9
MB		 4107 default:
4108 break;
e4d6b795
MB		 4109 }
4110 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4111 }
4112#endif /* CONFIG_SSB_DRIVER_PCICORE */
4113}
4114
d59f720d
MB		 4115static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4116{
4117 u16 pu_delay;
4118
4119 /* The time value is in microseconds. */
4120 if (dev->phy.type == B43_PHYTYPE_A)
4121 pu_delay = 3700;
4122 else
4123 pu_delay = 1050;
05c914fe 4124 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4125 pu_delay = 500;
4126 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4127 pu_delay = max(pu_delay, (u16)2400);
4128
4129 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4130}
4131
4132/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4133static void b43_set_pretbtt(struct b43_wldev *dev)
4134{
4135 u16 pretbtt;
4136
4137 /* The time value is in microseconds. */
05c914fe 4138 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4139 pretbtt = 2;
4140 } else {
4141 if (dev->phy.type == B43_PHYTYPE_A)
4142 pretbtt = 120;
4143 else
4144 pretbtt = 250;
4145 }
4146 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4147 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4148}
4149
e4d6b795
MB		 4150/* Shutdown a wireless core */
4151/* Locking: wl->mutex */
4152static void b43_wireless_core_exit(struct b43_wldev *dev)
4153{
1f7d87b0 4154 u32 macctl;
e4d6b795 4155
36dbd954
MB		 4156 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4157 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795
MB		 4158 return;
4159 b43_set_status(dev, B43_STAT_UNINIT);
4160
1f7d87b0
MB		 4161 /* Stop the microcode PSM. */
4162 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4163 macctl &= ~B43_MACCTL_PSM_RUN;
4164 macctl |= B43_MACCTL_PSM_JMP0;
4165 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4166
3506e0c4
RW		 4167 if (!dev->suspend_in_progress) {
4168 b43_leds_exit(dev);
b844eba2 4169 b43_rng_exit(dev->wl);
3506e0c4 4170 }
e4d6b795 4171 b43_dma_free(dev);
5100d5ac 4172 b43_pio_free(dev);
e4d6b795 4173 b43_chip_exit(dev);
cb24f57f 4174 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4175 if (dev->wl->current_beacon) {
4176 dev_kfree_skb_any(dev->wl->current_beacon);
4177 dev->wl->current_beacon = NULL;
4178 }
4179
e4d6b795
MB		 4180 ssb_device_disable(dev->dev, 0);
4181 ssb_bus_may_powerdown(dev->dev->bus);
4182}
4183
4184/* Initialize a wireless core */
4185static int b43_wireless_core_init(struct b43_wldev *dev)
4186{
4187 struct b43_wl *wl = dev->wl;
4188 struct ssb_bus *bus = dev->dev->bus;
4189 struct ssb_sprom *sprom = &bus->sprom;
4190 struct b43_phy *phy = &dev->phy;
4191 int err;
a259d6a4
MB		 4192 u64 hf;
4193 u32 tmp;
e4d6b795
MB		 4194
4195 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4196
4197 err = ssb_bus_powerup(bus, 0);
4198 if (err)
4199 goto out;
4200 if (!ssb_device_is_enabled(dev->dev)) {
4201 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4202 b43_wireless_core_reset(dev, tmp);
4203 }
4204
fb11137a 4205 /* Reset all data structures. */
e4d6b795 4206 setup_struct_wldev_for_init(dev);
fb11137a 4207 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4208
4209 /* Enable IRQ routing to this device. */
4210 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4211
4212 b43_imcfglo_timeouts_workaround(dev);
4213 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4214 if (phy->ops->prepare_hardware) {
4215 err = phy->ops->prepare_hardware(dev);
ef1a628d 4216 if (err)
fb11137a 4217 goto err_busdown;
ef1a628d 4218 }
e4d6b795
MB		 4219 err = b43_chip_init(dev);
4220 if (err)
fb11137a 4221 goto err_busdown;
e4d6b795
MB		 4222 b43_shm_write16(dev, B43_SHM_SHARED,
4223 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4224 hf = b43_hf_read(dev);
4225 if (phy->type == B43_PHYTYPE_G) {
4226 hf |= B43_HF_SYMW;
4227 if (phy->rev == 1)
4228 hf |= B43_HF_GDCW;
95de2841 4229 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4230 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4231 }
4232 if (phy->radio_ver == 0x2050) {
4233 if (phy->radio_rev == 6)
4234 hf |= B43_HF_4318TSSI;
4235 if (phy->radio_rev < 6)
4236 hf |= B43_HF_VCORECALC;
e4d6b795 4237 }
1cc8f476
MB		 4238 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4239 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4240#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4241 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4242 (bus->pcicore.dev->id.revision <= 10))
4243 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4244#endif
25d3ef59 4245 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4246 b43_hf_write(dev, hf);
4247
74cfdba7
MB		 4248 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4249 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4250 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4251 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4252
4253 /* Disable sending probe responses from firmware.
4254 * Setting the MaxTime to one usec will always trigger
4255 * a timeout, so we never send any probe resp.
4256 * A timeout of zero is infinite. */
4257 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4258
4259 b43_rate_memory_init(dev);
5042c507 4260 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4261
4262 /* Minimum Contention Window */
4263 if (phy->type == B43_PHYTYPE_B) {
4264 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4265 } else {
4266 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4267 }
4268 /* Maximum Contention Window */
4269 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4270
5100d5ac
MB		 4271 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4272 dev->__using_pio_transfers = 1;
4273 err = b43_pio_init(dev);
4274 } else {
4275 dev->__using_pio_transfers = 0;
4276 err = b43_dma_init(dev);
4277 }
e4d6b795
MB		 4278 if (err)
4279 goto err_chip_exit;
03b29773 4280 b43_qos_init(dev);
d59f720d 4281 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4282 b43_bluetooth_coext_enable(dev);
4283
1cc8f476 4284 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4285 b43_upload_card_macaddress(dev);
e4d6b795 4286 b43_security_init(dev);
3506e0c4
RW		 4287 if (!dev->suspend_in_progress)
4288 b43_rng_init(wl);
e4d6b795 4289
32f6afd8
MB		 4290 ieee80211_wake_queues(dev->wl->hw);
4291
e4d6b795
MB		 4292 b43_set_status(dev, B43_STAT_INITIALIZED);
4293
3506e0c4
RW		 4294 if (!dev->suspend_in_progress)
4295 b43_leds_init(dev);
1a8d1227 4296out:
e4d6b795
MB		 4297 return err;
4298
ef1a628d 4299err_chip_exit:
e4d6b795 4300 b43_chip_exit(dev);
ef1a628d 4301err_busdown:
e4d6b795
MB		 4302 ssb_bus_may_powerdown(bus);
4303 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4304 return err;
4305}
4306
40faacc4
MB		 4307static int b43_op_add_interface(struct ieee80211_hw *hw,
4308 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4309{
4310 struct b43_wl *wl = hw_to_b43_wl(hw);
4311 struct b43_wldev *dev;
e4d6b795 4312 int err = -EOPNOTSUPP;
4150c572
JB		 4313
4314 /* TODO: allow WDS/AP devices to coexist */
4315
05c914fe
JB		 4316 if (conf->type != NL80211_IFTYPE_AP &&
4317 conf->type != NL80211_IFTYPE_MESH_POINT &&
4318 conf->type != NL80211_IFTYPE_STATION &&
4319 conf->type != NL80211_IFTYPE_WDS &&
4320 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4321 return -EOPNOTSUPP;
e4d6b795
MB		 4322
4323 mutex_lock(&wl->mutex);
4150c572 4324 if (wl->operating)
e4d6b795
MB		 4325 goto out_mutex_unlock;
4326
4327 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4328
4329 dev = wl->current_dev;
4150c572 4330 wl->operating = 1;
32bfd35d 4331 wl->vif = conf->vif;
4150c572
JB		 4332 wl->if_type = conf->type;
4333 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4334
4150c572 4335 b43_adjust_opmode(dev);
d59f720d
MB		 4336 b43_set_pretbtt(dev);
4337 b43_set_synth_pu_delay(dev, 0);
4150c572 4338 b43_upload_card_macaddress(dev);
4150c572
JB		 4339
4340 err = 0;
4341 out_mutex_unlock:
4342 mutex_unlock(&wl->mutex);
4343
4344 return err;
4345}
4346
40faacc4
MB		 4347static void b43_op_remove_interface(struct ieee80211_hw *hw,
4348 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4349{
4350 struct b43_wl *wl = hw_to_b43_wl(hw);
4351 struct b43_wldev *dev = wl->current_dev;
4150c572
JB		 4352
4353 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4354
4355 mutex_lock(&wl->mutex);
4356
4357 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4358 B43_WARN_ON(wl->vif != conf->vif);
4359 wl->vif = NULL;
4150c572
JB		 4360
4361 wl->operating = 0;
4362
4150c572
JB		 4363 b43_adjust_opmode(dev);
4364 memset(wl->mac_addr, 0, ETH_ALEN);
4365 b43_upload_card_macaddress(dev);
4150c572
JB		 4366
4367 mutex_unlock(&wl->mutex);
4368}
4369
40faacc4 4370static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4371{
4372 struct b43_wl *wl = hw_to_b43_wl(hw);
4373 struct b43_wldev *dev = wl->current_dev;
4374 int did_init = 0;
923403b8 4375 int err = 0;
4150c572 4376
7be1bb6b
MB		 4377 /* Kill all old instance specific information to make sure
4378 * the card won't use it in the short timeframe between start
4379 * and mac80211 reconfiguring it. */
4380 memset(wl->bssid, 0, ETH_ALEN);
4381 memset(wl->mac_addr, 0, ETH_ALEN);
4382 wl->filter_flags = 0;
4383 wl->radiotap_enabled = 0;
e6f5b934 4384 b43_qos_clear(wl);
6b4bec01
MB		 4385 wl->beacon0_uploaded = 0;
4386 wl->beacon1_uploaded = 0;
4387 wl->beacon_templates_virgin = 1;
fd4973c5 4388 wl->radio_enabled = 1;
7be1bb6b 4389
4150c572
JB		 4390 mutex_lock(&wl->mutex);
4391
e4d6b795
MB		 4392 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4393 err = b43_wireless_core_init(dev);
f41f3f37 4394 if (err)
e4d6b795
MB		 4395 goto out_mutex_unlock;
4396 did_init = 1;
4397 }
4150c572 4398
e4d6b795
MB		 4399 if (b43_status(dev) < B43_STAT_STARTED) {
4400 err = b43_wireless_core_start(dev);
4401 if (err) {
4402 if (did_init)
4403 b43_wireless_core_exit(dev);
4404 goto out_mutex_unlock;
4405 }
4406 }
4407
f41f3f37
JB		 4408 /* XXX: only do if device doesn't support rfkill irq */
4409 wiphy_rfkill_start_polling(hw->wiphy);
4410
4150c572 4411 out_mutex_unlock:
e4d6b795
MB		 4412 mutex_unlock(&wl->mutex);
4413
4414 return err;
4415}
4416
40faacc4 4417static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4418{
4419 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4420 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4421
a82d9922 4422 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4423
e4d6b795 4424 mutex_lock(&wl->mutex);
36dbd954
MB		 4425 if (b43_status(dev) >= B43_STAT_STARTED) {
4426 dev = b43_wireless_core_stop(dev);
4427 if (!dev)
4428 goto out_unlock;
4429 }
4150c572 4430 b43_wireless_core_exit(dev);
fd4973c5 4431 wl->radio_enabled = 0;
36dbd954
MB		 4432
4433out_unlock:
e4d6b795 4434 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4435
4436 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4437}
4438
17741cdc
JB		 4439static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4440 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4441{
4442 struct b43_wl *wl = hw_to_b43_wl(hw);
4443
36dbd954 4444 mutex_lock(&wl->mutex);
9d139c81 4445 b43_update_templates(wl);
36dbd954 4446 mutex_unlock(&wl->mutex);
e66fee6a
MB		 4447
4448 return 0;
4449}
4450
38968d09
JB		 4451static void b43_op_sta_notify(struct ieee80211_hw *hw,
4452 struct ieee80211_vif *vif,
4453 enum sta_notify_cmd notify_cmd,
17741cdc 4454 struct ieee80211_sta *sta)
38968d09
JB		 4455{
4456 struct b43_wl *wl = hw_to_b43_wl(hw);
4457
4458 B43_WARN_ON(!vif || wl->vif != vif);
4459}
4460
25d3ef59
MB		 4461static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4462{
4463 struct b43_wl *wl = hw_to_b43_wl(hw);
4464 struct b43_wldev *dev;
4465
4466 mutex_lock(&wl->mutex);
4467 dev = wl->current_dev;
4468 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4469 /* Disable CFP update during scan on other channels. */
4470 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4471 }
4472 mutex_unlock(&wl->mutex);
4473}
4474
4475static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4476{
4477 struct b43_wl *wl = hw_to_b43_wl(hw);
4478 struct b43_wldev *dev;
4479
4480 mutex_lock(&wl->mutex);
4481 dev = wl->current_dev;
4482 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4483 /* Re-enable CFP update. */
4484 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4485 }
4486 mutex_unlock(&wl->mutex);
4487}
4488
e4d6b795 4489static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4490 .tx = b43_op_tx,
4491 .conf_tx = b43_op_conf_tx,
4492 .add_interface = b43_op_add_interface,
4493 .remove_interface = b43_op_remove_interface,
4494 .config = b43_op_config,
c7ab5ef9 4495 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4496 .configure_filter = b43_op_configure_filter,
4497 .set_key = b43_op_set_key,
035d0243 4498 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4499 .get_stats = b43_op_get_stats,
4500 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4501 .get_tsf = b43_op_get_tsf,
4502 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4503 .start = b43_op_start,
4504 .stop = b43_op_stop,
e66fee6a 4505 .set_tim = b43_op_beacon_set_tim,
38968d09 4506 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4507 .sw_scan_start = b43_op_sw_scan_start_notifier,
4508 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4509 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4510};
4511
4512/* Hard-reset the chip. Do not call this directly.
4513 * Use b43_controller_restart()
4514 */
4515static void b43_chip_reset(struct work_struct *work)
4516{
4517 struct b43_wldev *dev =
4518 container_of(work, struct b43_wldev, restart_work);
4519 struct b43_wl *wl = dev->wl;
4520 int err = 0;
4521 int prev_status;
4522
4523 mutex_lock(&wl->mutex);
4524
4525 prev_status = b43_status(dev);
4526 /* Bring the device down... */
36dbd954
MB		 4527 if (prev_status >= B43_STAT_STARTED) {
4528 dev = b43_wireless_core_stop(dev);
4529 if (!dev) {
4530 err = -ENODEV;
4531 goto out;
4532 }
4533 }
e4d6b795
MB		 4534 if (prev_status >= B43_STAT_INITIALIZED)
4535 b43_wireless_core_exit(dev);
4536
4537 /* ...and up again. */
4538 if (prev_status >= B43_STAT_INITIALIZED) {
4539 err = b43_wireless_core_init(dev);
4540 if (err)
4541 goto out;
4542 }
4543 if (prev_status >= B43_STAT_STARTED) {
4544 err = b43_wireless_core_start(dev);
4545 if (err) {
4546 b43_wireless_core_exit(dev);
4547 goto out;
4548 }
4549 }
3bf0a32e
MB		 4550out:
4551 if (err)
4552 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4553 mutex_unlock(&wl->mutex);
4554 if (err)
4555 b43err(wl, "Controller restart FAILED\n");
4556 else
4557 b43info(wl, "Controller restarted\n");
4558}
4559
bb1eeff1 4560static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4561 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4562{
4563 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4564
bb1eeff1
MB		 4565 if (have_2ghz_phy)
4566 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4567 if (dev->phy.type == B43_PHYTYPE_N) {
4568 if (have_5ghz_phy)
4569 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4570 } else {
4571 if (have_5ghz_phy)
4572 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4573 }
96c755a3 4574
bb1eeff1
MB		 4575 dev->phy.supports_2ghz = have_2ghz_phy;
4576 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4577
4578 return 0;
4579}
4580
4581static void b43_wireless_core_detach(struct b43_wldev *dev)
4582{
4583 /* We release firmware that late to not be required to re-request
4584 * is all the time when we reinit the core. */
4585 b43_release_firmware(dev);
fb11137a 4586 b43_phy_free(dev);
e4d6b795
MB		 4587}
4588
4589static int b43_wireless_core_attach(struct b43_wldev *dev)
4590{
4591 struct b43_wl *wl = dev->wl;
4592 struct ssb_bus *bus = dev->dev->bus;
4593 struct pci_dev *pdev = bus->host_pci;
4594 int err;
96c755a3 4595 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4596 u32 tmp;
4597
4598 /* Do NOT do any device initialization here.
4599 * Do it in wireless_core_init() instead.
4600 * This function is for gathering basic information about the HW, only.
4601 * Also some structs may be set up here. But most likely you want to have
4602 * that in core_init(), too.
4603 */
4604
4605 err = ssb_bus_powerup(bus, 0);
4606 if (err) {
4607 b43err(wl, "Bus powerup failed\n");
4608 goto out;
4609 }
4610 /* Get the PHY type. */
4611 if (dev->dev->id.revision >= 5) {
4612 u32 tmshigh;
4613
4614 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4615 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4616 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4617 } else
96c755a3 4618 B43_WARN_ON(1);
e4d6b795 4619
96c755a3 4620 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4621 dev->phy.radio_on = 1;
e4d6b795
MB		 4622 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4623 b43_wireless_core_reset(dev, tmp);
4624
4625 err = b43_phy_versioning(dev);
4626 if (err)
21954c36 4627 goto err_powerdown;
e4d6b795
MB		 4628 /* Check if this device supports multiband. */
4629 if (!pdev ||
4630 (pdev->device != 0x4312 &&
4631 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4632 /* No multiband support. */
96c755a3
MB		 4633 have_2ghz_phy = 0;
4634 have_5ghz_phy = 0;
e4d6b795
MB		 4635 switch (dev->phy.type) {
4636 case B43_PHYTYPE_A:
96c755a3 4637 have_5ghz_phy = 1;
e4d6b795 4638 break;
9d86a2d5 4639 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4640#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4641 have_5ghz_phy = 1;
86b2892a 4642#endif
e4d6b795 4643 case B43_PHYTYPE_G:
96c755a3
MB		 4644 case B43_PHYTYPE_N:
4645 have_2ghz_phy = 1;
e4d6b795
MB		 4646 break;
4647 default:
4648 B43_WARN_ON(1);
4649 }
4650 }
96c755a3
MB		 4651 if (dev->phy.type == B43_PHYTYPE_A) {
4652 /* FIXME */
4653 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4654 err = -EOPNOTSUPP;
4655 goto err_powerdown;
4656 }
2e35af14
MB		 4657 if (1 /* disable A-PHY */) {
4658 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4659 if (dev->phy.type != B43_PHYTYPE_N &&
4660 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4661 have_2ghz_phy = 1;
4662 have_5ghz_phy = 0;
4663 }
4664 }
4665
fb11137a
MB		 4666 err = b43_phy_allocate(dev);
4667 if (err)
4668 goto err_powerdown;
4669
96c755a3 4670 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4671 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4672 b43_wireless_core_reset(dev, tmp);
4673
4674 err = b43_validate_chipaccess(dev);
4675 if (err)
fb11137a 4676 goto err_phy_free;
bb1eeff1 4677 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4678 if (err)
fb11137a 4679 goto err_phy_free;
e4d6b795
MB		 4680
4681 /* Now set some default "current_dev" */
4682 if (!wl->current_dev)
4683 wl->current_dev = dev;
4684 INIT_WORK(&dev->restart_work, b43_chip_reset);
4685
cb24f57f 4686 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4687 ssb_device_disable(dev->dev, 0);
4688 ssb_bus_may_powerdown(bus);
4689
4690out:
4691 return err;
4692
fb11137a
MB		 4693err_phy_free:
4694 b43_phy_free(dev);
e4d6b795
MB		 4695err_powerdown:
4696 ssb_bus_may_powerdown(bus);
4697 return err;
4698}
4699
4700static void b43_one_core_detach(struct ssb_device *dev)
4701{
4702 struct b43_wldev *wldev;
4703 struct b43_wl *wl;
4704
3bf0a32e
MB		 4705 /* Do not cancel ieee80211-workqueue based work here.
4706 * See comment in b43_remove(). */
4707
e4d6b795
MB		 4708 wldev = ssb_get_drvdata(dev);
4709 wl = wldev->wl;
e4d6b795
MB		 4710 b43_debugfs_remove_device(wldev);
4711 b43_wireless_core_detach(wldev);
4712 list_del(&wldev->list);
4713 wl->nr_devs--;
4714 ssb_set_drvdata(dev, NULL);
4715 kfree(wldev);
4716}
4717
4718static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4719{
4720 struct b43_wldev *wldev;
4721 struct pci_dev *pdev;
4722 int err = -ENOMEM;
4723
4724 if (!list_empty(&wl->devlist)) {
4725 /* We are not the first core on this chip. */
4726 pdev = dev->bus->host_pci;
4727 /* Only special chips support more than one wireless
4728 * core, although some of the other chips have more than
4729 * one wireless core as well. Check for this and
4730 * bail out early.
4731 */
4732 if (!pdev ||
4733 ((pdev->device != 0x4321) &&
4734 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4735 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4736 return -ENODEV;
4737 }
4738 }
4739
4740 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4741 if (!wldev)
4742 goto out;
4743
4744 wldev->dev = dev;
4745 wldev->wl = wl;
4746 b43_set_status(wldev, B43_STAT_UNINIT);
4747 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 4748 INIT_LIST_HEAD(&wldev->list);
4749
4750 err = b43_wireless_core_attach(wldev);
4751 if (err)
4752 goto err_kfree_wldev;
4753
4754 list_add(&wldev->list, &wl->devlist);
4755 wl->nr_devs++;
4756 ssb_set_drvdata(dev, wldev);
4757 b43_debugfs_add_device(wldev);
4758
4759 out:
4760 return err;
4761
4762 err_kfree_wldev:
4763 kfree(wldev);
4764 return err;
4765}
4766
9fc38458
MB		 4767#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4768 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4769 (pdev->device == _device) && \
4770 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4771 (pdev->subsystem_device == _subdevice) )
4772
e4d6b795
MB		 4773static void b43_sprom_fixup(struct ssb_bus *bus)
4774{
1855ba78
MB		 4775 struct pci_dev *pdev;
4776
e4d6b795
MB		 4777 /* boardflags workarounds */
4778 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4779 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4780 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4781 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4782 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4783 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4784 if (bus->bustype == SSB_BUSTYPE_PCI) {
4785 pdev = bus->host_pci;
9fc38458 4786 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4787 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4788 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4789 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4790 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4791 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4792 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4793 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4794 }
e4d6b795
MB		 4795}
4796
4797static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4798{
4799 struct ieee80211_hw *hw = wl->hw;
4800
4801 ssb_set_devtypedata(dev, NULL);
4802 ieee80211_free_hw(hw);
4803}
4804
4805static int b43_wireless_init(struct ssb_device *dev)
4806{
4807 struct ssb_sprom *sprom = &dev->bus->sprom;
4808 struct ieee80211_hw *hw;
4809 struct b43_wl *wl;
4810 int err = -ENOMEM;
4811
4812 b43_sprom_fixup(dev->bus);
4813
4814 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4815 if (!hw) {
4816 b43err(NULL, "Could not allocate ieee80211 device\n");
4817 goto out;
4818 }
403a3a13 4819 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4820
4821 /* fill hw info */
605a0bd6 4822 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4823 IEEE80211_HW_SIGNAL_DBM |
4824 IEEE80211_HW_NOISE_DBM;
4825
f59ac048
LR		 4826 hw->wiphy->interface_modes =
4827 BIT(NL80211_IFTYPE_AP) |
4828 BIT(NL80211_IFTYPE_MESH_POINT) |
4829 BIT(NL80211_IFTYPE_STATION) |
4830 BIT(NL80211_IFTYPE_WDS) |
4831 BIT(NL80211_IFTYPE_ADHOC);
4832
403a3a13
MB		 4833 hw->queues = modparam_qos ? 4 : 1;
4834 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4835 hw->max_rates = 2;
e4d6b795 4836 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4837 if (is_valid_ether_addr(sprom->et1mac))
4838 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4839 else
95de2841 4840 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4841
403a3a13 4842 /* Initialize struct b43_wl */
e4d6b795 4843 wl->hw = hw;
e4d6b795
MB		 4844 spin_lock_init(&wl->leds_lock);
4845 mutex_init(&wl->mutex);
36dbd954 4846 spin_lock_init(&wl->hardirq_lock);
e4d6b795 4847 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4848 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4849 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 4850 INIT_WORK(&wl->tx_work, b43_tx_work);
4851 skb_queue_head_init(&wl->tx_queue);
e4d6b795
MB		 4852
4853 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4854 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4855 dev->bus->chip_id, dev->id.revision);
e4d6b795 4856 err = 0;
060210f9 4857out:
e4d6b795
MB		 4858 return err;
4859}
4860
4861static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4862{
4863 struct b43_wl *wl;
4864 int err;
4865 int first = 0;
4866
4867 wl = ssb_get_devtypedata(dev);
4868 if (!wl) {
4869 /* Probing the first core. Must setup common struct b43_wl */
4870 first = 1;
4871 err = b43_wireless_init(dev);
4872 if (err)
4873 goto out;
4874 wl = ssb_get_devtypedata(dev);
4875 B43_WARN_ON(!wl);
4876 }
4877 err = b43_one_core_attach(dev, wl);
4878 if (err)
4879 goto err_wireless_exit;
4880
4881 if (first) {
4882 err = ieee80211_register_hw(wl->hw);
4883 if (err)
4884 goto err_one_core_detach;
4885 }
4886
4887 out:
4888 return err;
4889
4890 err_one_core_detach:
4891 b43_one_core_detach(dev);
4892 err_wireless_exit:
4893 if (first)
4894 b43_wireless_exit(dev, wl);
4895 return err;
4896}
4897
4898static void b43_remove(struct ssb_device *dev)
4899{
4900 struct b43_wl *wl = ssb_get_devtypedata(dev);
4901 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4902
3bf0a32e
MB		 4903 /* We must cancel any work here before unregistering from ieee80211,
4904 * as the ieee80211 unreg will destroy the workqueue. */
4905 cancel_work_sync(&wldev->restart_work);
4906
e4d6b795 4907 B43_WARN_ON(!wl);
403a3a13
MB		 4908 if (wl->current_dev == wldev) {
4909 /* Restore the queues count before unregistering, because firmware detect
4910 * might have modified it. Restoring is important, so the networking
4911 * stack can properly free resources. */
4912 wl->hw->queues = wl->mac80211_initially_registered_queues;
e4d6b795 4913 ieee80211_unregister_hw(wl->hw);
403a3a13 4914 }
e4d6b795
MB		 4915
4916 b43_one_core_detach(dev);
4917
4918 if (list_empty(&wl->devlist)) {
4919 /* Last core on the chip unregistered.
4920 * We can destroy common struct b43_wl.
4921 */
4922 b43_wireless_exit(dev, wl);
4923 }
4924}
4925
4926/* Perform a hardware reset. This can be called from any context. */
4927void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4928{
4929 /* Must avoid requeueing, if we are in shutdown. */
4930 if (b43_status(dev) < B43_STAT_INITIALIZED)
4931 return;
4932 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 4933 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 4934}
4935
4936#ifdef CONFIG_PM
4937
4938static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4939{
4940 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4941 struct b43_wl *wl = wldev->wl;
4942
4943 b43dbg(wl, "Suspending...\n");
4944
4945 mutex_lock(&wl->mutex);
3506e0c4 4946 wldev->suspend_in_progress = true;
e4d6b795
MB		 4947 wldev->suspend_init_status = b43_status(wldev);
4948 if (wldev->suspend_init_status >= B43_STAT_STARTED)
36dbd954
MB		 4949 wldev = b43_wireless_core_stop(wldev);
4950 if (wldev && wldev->suspend_init_status >= B43_STAT_INITIALIZED)
e4d6b795
MB		 4951 b43_wireless_core_exit(wldev);
4952 mutex_unlock(&wl->mutex);
4953
4954 b43dbg(wl, "Device suspended.\n");
4955
4956 return 0;
4957}
4958
4959static int b43_resume(struct ssb_device *dev)
4960{
4961 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4962 struct b43_wl *wl = wldev->wl;
4963 int err = 0;
4964
4965 b43dbg(wl, "Resuming...\n");
4966
4967 mutex_lock(&wl->mutex);
4968 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4969 err = b43_wireless_core_init(wldev);
4970 if (err) {
4971 b43err(wl, "Resume failed at core init\n");
4972 goto out;
4973 }
4974 }
4975 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4976 err = b43_wireless_core_start(wldev);
4977 if (err) {
3506e0c4 4978 b43_leds_exit(wldev);
b844eba2 4979 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4980 b43_wireless_core_exit(wldev);
4981 b43err(wl, "Resume failed at core start\n");
4982 goto out;
4983 }
4984 }
e4d6b795 4985 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4986 out:
4987 wldev->suspend_in_progress = false;
4988 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4989 return err;
4990}
4991
4992#else /* CONFIG_PM */
4993# define b43_suspend NULL
4994# define b43_resume NULL
4995#endif /* CONFIG_PM */
4996
4997static struct ssb_driver b43_ssb_driver = {
4998 .name = KBUILD_MODNAME,
4999 .id_table = b43_ssb_tbl,
5000 .probe = b43_probe,
5001 .remove = b43_remove,
5002 .suspend = b43_suspend,
5003 .resume = b43_resume,
5004};
5005
26bc783f
MB		 5006static void b43_print_driverinfo(void)
5007{
5008 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
f41f3f37 5009 *feat_leds = "";
26bc783f
MB		 5010
5011#ifdef CONFIG_B43_PCI_AUTOSELECT
5012 feat_pci = "P";
5013#endif
5014#ifdef CONFIG_B43_PCMCIA
5015 feat_pcmcia = "M";
5016#endif
5017#ifdef CONFIG_B43_NPHY
5018 feat_nphy = "N";
5019#endif
5020#ifdef CONFIG_B43_LEDS
5021 feat_leds = "L";
26bc783f
MB		 5022#endif
5023 printk(KERN_INFO "Broadcom 43xx driver loaded "
f41f3f37 5024 "[ Features: %s%s%s%s, Firmware-ID: "
26bc783f
MB		 5025 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5026 feat_pci, feat_pcmcia, feat_nphy,
f41f3f37 5027 feat_leds);
26bc783f
MB		 5028}
5029
e4d6b795
MB		 5030static int __init b43_init(void)
5031{
5032 int err;
5033
5034 b43_debugfs_init();
5035 err = b43_pcmcia_init();
5036 if (err)
5037 goto err_dfs_exit;
5038 err = ssb_driver_register(&b43_ssb_driver);
5039 if (err)
5040 goto err_pcmcia_exit;
26bc783f 5041 b43_print_driverinfo();
e4d6b795
MB		 5042
5043 return err;
5044
5045err_pcmcia_exit:
5046 b43_pcmcia_exit();
5047err_dfs_exit:
5048 b43_debugfs_exit();
5049 return err;
5050}
5051
5052static void __exit b43_exit(void)
5053{
5054 ssb_driver_unregister(&b43_ssb_driver);
5055 b43_pcmcia_exit();
5056 b43_debugfs_exit();
5057}
5058
5059module_init(b43_init)
5060module_exit(b43_exit)
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