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at76c50x-usb: remove unneeded flush_workqueue() at usb disconnect
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
403a3a13
MB		 83static int modparam_qos = 1;
84module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
060210f9
MB		 91int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
92module_param_named(verbose, b43_modparam_verbose, int, 0644);
93MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
94
e6f5b934 95
e4d6b795
MB		 96static const struct ssb_device_id b43_ssb_tbl[] = {
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 106 SSB_DEVTABLE_END
107};
108
109MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
110
111/* Channel and ratetables are shared for all devices.
112 * They can't be const, because ieee80211 puts some precalculated
113 * data in there. This data is the same for all devices, so we don't
114 * get concurrency issues */
115#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 116 { \
117 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
118 .hw_value = (_rateid), \
119 .flags = (_flags), \
e4d6b795 120 }
8318d78a
JB		 121
122/*
123 * NOTE: When changing this, sync with xmit.c's
124 * b43_plcp_get_bitrate_idx_* functions!
125 */
e4d6b795 126static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 127 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
128 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
129 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
130 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
131 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
135 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
136 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 139};
140
141#define b43_a_ratetable (__b43_ratetable + 4)
142#define b43_a_ratetable_size 8
143#define b43_b_ratetable (__b43_ratetable + 0)
144#define b43_b_ratetable_size 4
145#define b43_g_ratetable (__b43_ratetable + 0)
146#define b43_g_ratetable_size 12
147
bb1eeff1
MB		 148#define CHAN4G(_channel, _freq, _flags) { \
149 .band = IEEE80211_BAND_2GHZ, \
150 .center_freq = (_freq), \
151 .hw_value = (_channel), \
152 .flags = (_flags), \
153 .max_antenna_gain = 0, \
154 .max_power = 30, \
155}
96c755a3 156static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 157 CHAN4G(1, 2412, 0),
158 CHAN4G(2, 2417, 0),
159 CHAN4G(3, 2422, 0),
160 CHAN4G(4, 2427, 0),
161 CHAN4G(5, 2432, 0),
162 CHAN4G(6, 2437, 0),
163 CHAN4G(7, 2442, 0),
164 CHAN4G(8, 2447, 0),
165 CHAN4G(9, 2452, 0),
166 CHAN4G(10, 2457, 0),
167 CHAN4G(11, 2462, 0),
168 CHAN4G(12, 2467, 0),
169 CHAN4G(13, 2472, 0),
170 CHAN4G(14, 2484, 0),
171};
172#undef CHAN4G
173
174#define CHAN5G(_channel, _flags) { \
175 .band = IEEE80211_BAND_5GHZ, \
176 .center_freq = 5000 + (5 * (_channel)), \
177 .hw_value = (_channel), \
178 .flags = (_flags), \
179 .max_antenna_gain = 0, \
180 .max_power = 30, \
181}
182static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
183 CHAN5G(32, 0), CHAN5G(34, 0),
184 CHAN5G(36, 0), CHAN5G(38, 0),
185 CHAN5G(40, 0), CHAN5G(42, 0),
186 CHAN5G(44, 0), CHAN5G(46, 0),
187 CHAN5G(48, 0), CHAN5G(50, 0),
188 CHAN5G(52, 0), CHAN5G(54, 0),
189 CHAN5G(56, 0), CHAN5G(58, 0),
190 CHAN5G(60, 0), CHAN5G(62, 0),
191 CHAN5G(64, 0), CHAN5G(66, 0),
192 CHAN5G(68, 0), CHAN5G(70, 0),
193 CHAN5G(72, 0), CHAN5G(74, 0),
194 CHAN5G(76, 0), CHAN5G(78, 0),
195 CHAN5G(80, 0), CHAN5G(82, 0),
196 CHAN5G(84, 0), CHAN5G(86, 0),
197 CHAN5G(88, 0), CHAN5G(90, 0),
198 CHAN5G(92, 0), CHAN5G(94, 0),
199 CHAN5G(96, 0), CHAN5G(98, 0),
200 CHAN5G(100, 0), CHAN5G(102, 0),
201 CHAN5G(104, 0), CHAN5G(106, 0),
202 CHAN5G(108, 0), CHAN5G(110, 0),
203 CHAN5G(112, 0), CHAN5G(114, 0),
204 CHAN5G(116, 0), CHAN5G(118, 0),
205 CHAN5G(120, 0), CHAN5G(122, 0),
206 CHAN5G(124, 0), CHAN5G(126, 0),
207 CHAN5G(128, 0), CHAN5G(130, 0),
208 CHAN5G(132, 0), CHAN5G(134, 0),
209 CHAN5G(136, 0), CHAN5G(138, 0),
210 CHAN5G(140, 0), CHAN5G(142, 0),
211 CHAN5G(144, 0), CHAN5G(145, 0),
212 CHAN5G(146, 0), CHAN5G(147, 0),
213 CHAN5G(148, 0), CHAN5G(149, 0),
214 CHAN5G(150, 0), CHAN5G(151, 0),
215 CHAN5G(152, 0), CHAN5G(153, 0),
216 CHAN5G(154, 0), CHAN5G(155, 0),
217 CHAN5G(156, 0), CHAN5G(157, 0),
218 CHAN5G(158, 0), CHAN5G(159, 0),
219 CHAN5G(160, 0), CHAN5G(161, 0),
220 CHAN5G(162, 0), CHAN5G(163, 0),
221 CHAN5G(164, 0), CHAN5G(165, 0),
222 CHAN5G(166, 0), CHAN5G(168, 0),
223 CHAN5G(170, 0), CHAN5G(172, 0),
224 CHAN5G(174, 0), CHAN5G(176, 0),
225 CHAN5G(178, 0), CHAN5G(180, 0),
226 CHAN5G(182, 0), CHAN5G(184, 0),
227 CHAN5G(186, 0), CHAN5G(188, 0),
228 CHAN5G(190, 0), CHAN5G(192, 0),
229 CHAN5G(194, 0), CHAN5G(196, 0),
230 CHAN5G(198, 0), CHAN5G(200, 0),
231 CHAN5G(202, 0), CHAN5G(204, 0),
232 CHAN5G(206, 0), CHAN5G(208, 0),
233 CHAN5G(210, 0), CHAN5G(212, 0),
234 CHAN5G(214, 0), CHAN5G(216, 0),
235 CHAN5G(218, 0), CHAN5G(220, 0),
236 CHAN5G(222, 0), CHAN5G(224, 0),
237 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 238};
239
bb1eeff1
MB		 240static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
241 CHAN5G(34, 0), CHAN5G(36, 0),
242 CHAN5G(38, 0), CHAN5G(40, 0),
243 CHAN5G(42, 0), CHAN5G(44, 0),
244 CHAN5G(46, 0), CHAN5G(48, 0),
245 CHAN5G(52, 0), CHAN5G(56, 0),
246 CHAN5G(60, 0), CHAN5G(64, 0),
247 CHAN5G(100, 0), CHAN5G(104, 0),
248 CHAN5G(108, 0), CHAN5G(112, 0),
249 CHAN5G(116, 0), CHAN5G(120, 0),
250 CHAN5G(124, 0), CHAN5G(128, 0),
251 CHAN5G(132, 0), CHAN5G(136, 0),
252 CHAN5G(140, 0), CHAN5G(149, 0),
253 CHAN5G(153, 0), CHAN5G(157, 0),
254 CHAN5G(161, 0), CHAN5G(165, 0),
255 CHAN5G(184, 0), CHAN5G(188, 0),
256 CHAN5G(192, 0), CHAN5G(196, 0),
257 CHAN5G(200, 0), CHAN5G(204, 0),
258 CHAN5G(208, 0), CHAN5G(212, 0),
259 CHAN5G(216, 0),
260};
261#undef CHAN5G
262
263static struct ieee80211_supported_band b43_band_5GHz_nphy = {
264 .band = IEEE80211_BAND_5GHZ,
265 .channels = b43_5ghz_nphy_chantable,
266 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
267 .bitrates = b43_a_ratetable,
268 .n_bitrates = b43_a_ratetable_size,
e4d6b795 269};
8318d78a 270
bb1eeff1
MB		 271static struct ieee80211_supported_band b43_band_5GHz_aphy = {
272 .band = IEEE80211_BAND_5GHZ,
273 .channels = b43_5ghz_aphy_chantable,
274 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
275 .bitrates = b43_a_ratetable,
276 .n_bitrates = b43_a_ratetable_size,
8318d78a 277};
e4d6b795 278
8318d78a 279static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 280 .band = IEEE80211_BAND_2GHZ,
281 .channels = b43_2ghz_chantable,
282 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
283 .bitrates = b43_g_ratetable,
284 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 285};
286
e4d6b795
MB		 287static void b43_wireless_core_exit(struct b43_wldev *dev);
288static int b43_wireless_core_init(struct b43_wldev *dev);
289static void b43_wireless_core_stop(struct b43_wldev *dev);
290static int b43_wireless_core_start(struct b43_wldev *dev);
291
292static int b43_ratelimit(struct b43_wl *wl)
293{
294 if (!wl || !wl->current_dev)
295 return 1;
296 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
297 return 1;
298 /* We are up and running.
299 * Ratelimit the messages to avoid DoS over the net. */
300 return net_ratelimit();
301}
302
303void b43info(struct b43_wl *wl, const char *fmt, ...)
304{
305 va_list args;
306
060210f9
MB		 307 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
308 return;
e4d6b795
MB		 309 if (!b43_ratelimit(wl))
310 return;
311 va_start(args, fmt);
312 printk(KERN_INFO "b43-%s: ",
313 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
314 vprintk(fmt, args);
315 va_end(args);
316}
317
318void b43err(struct b43_wl *wl, const char *fmt, ...)
319{
320 va_list args;
321
060210f9
MB		 322 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
323 return;
e4d6b795
MB		 324 if (!b43_ratelimit(wl))
325 return;
326 va_start(args, fmt);
327 printk(KERN_ERR "b43-%s ERROR: ",
328 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
329 vprintk(fmt, args);
330 va_end(args);
331}
332
333void b43warn(struct b43_wl *wl, const char *fmt, ...)
334{
335 va_list args;
336
060210f9
MB		 337 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
338 return;
e4d6b795
MB		 339 if (!b43_ratelimit(wl))
340 return;
341 va_start(args, fmt);
342 printk(KERN_WARNING "b43-%s warning: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347
e4d6b795
MB		 348void b43dbg(struct b43_wl *wl, const char *fmt, ...)
349{
350 va_list args;
351
060210f9
MB		 352 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
353 return;
e4d6b795
MB		 354 va_start(args, fmt);
355 printk(KERN_DEBUG "b43-%s debug: ",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
357 vprintk(fmt, args);
358 va_end(args);
359}
e4d6b795
MB		 360
361static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
362{
363 u32 macctl;
364
365 B43_WARN_ON(offset % 4 != 0);
366
367 macctl = b43_read32(dev, B43_MMIO_MACCTL);
368 if (macctl & B43_MACCTL_BE)
369 val = swab32(val);
370
371 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
372 mmiowb();
373 b43_write32(dev, B43_MMIO_RAM_DATA, val);
374}
375
280d0e16
MB		 376static inline void b43_shm_control_word(struct b43_wldev *dev,
377 u16 routing, u16 offset)
e4d6b795
MB		 378{
379 u32 control;
380
381 /* "offset" is the WORD offset. */
e4d6b795
MB		 382 control = routing;
383 control <<= 16;
384 control |= offset;
385 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
386}
387
6bbc321a 388u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 389{
390 u32 ret;
391
392 if (routing == B43_SHM_SHARED) {
393 B43_WARN_ON(offset & 0x0001);
394 if (offset & 0x0003) {
395 /* Unaligned access */
396 b43_shm_control_word(dev, routing, offset >> 2);
397 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
398 ret <<= 16;
399 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
400 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
401
280d0e16 402 goto out;
e4d6b795
MB		 403 }
404 offset >>= 2;
405 }
406 b43_shm_control_word(dev, routing, offset);
407 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 408out:
e4d6b795
MB		 409 return ret;
410}
411
6bbc321a 412u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 413{
280d0e16
MB		 414 struct b43_wl *wl = dev->wl;
415 unsigned long flags;
6bbc321a 416 u32 ret;
e4d6b795 417
280d0e16 418 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 419 ret = __b43_shm_read32(dev, routing, offset);
420 spin_unlock_irqrestore(&wl->shm_lock, flags);
421
422 return ret;
423}
424
425u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
426{
427 u16 ret;
428
e4d6b795
MB		 429 if (routing == B43_SHM_SHARED) {
430 B43_WARN_ON(offset & 0x0001);
431 if (offset & 0x0003) {
432 /* Unaligned access */
433 b43_shm_control_word(dev, routing, offset >> 2);
434 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
435
280d0e16 436 goto out;
e4d6b795
MB		 437 }
438 offset >>= 2;
439 }
440 b43_shm_control_word(dev, routing, offset);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 442out:
e4d6b795
MB		 443 return ret;
444}
445
6bbc321a 446u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 447{
280d0e16
MB		 448 struct b43_wl *wl = dev->wl;
449 unsigned long flags;
6bbc321a 450 u16 ret;
280d0e16
MB		 451
452 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 453 ret = __b43_shm_read16(dev, routing, offset);
454 spin_unlock_irqrestore(&wl->shm_lock, flags);
455
456 return ret;
457}
458
459void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
460{
e4d6b795
MB		 461 if (routing == B43_SHM_SHARED) {
462 B43_WARN_ON(offset & 0x0001);
463 if (offset & 0x0003) {
464 /* Unaligned access */
465 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 466 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
467 (value >> 16) & 0xffff);
e4d6b795 468 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 469 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 470 return;
e4d6b795
MB		 471 }
472 offset >>= 2;
473 }
474 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 475 b43_write32(dev, B43_MMIO_SHM_DATA, value);
476}
477
6bbc321a 478void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 479{
280d0e16
MB		 480 struct b43_wl *wl = dev->wl;
481 unsigned long flags;
482
483 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 484 __b43_shm_write32(dev, routing, offset, value);
485 spin_unlock_irqrestore(&wl->shm_lock, flags);
486}
487
488void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
489{
e4d6b795
MB		 490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 495 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 496 return;
e4d6b795
MB		 497 }
498 offset >>= 2;
499 }
500 b43_shm_control_word(dev, routing, offset);
e4d6b795 501 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 502}
503
504void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
505{
506 struct b43_wl *wl = dev->wl;
507 unsigned long flags;
508
509 spin_lock_irqsave(&wl->shm_lock, flags);
510 __b43_shm_write16(dev, routing, offset, value);
280d0e16 511 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 512}
513
514/* Read HostFlags */
99da185a 515u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 516{
35f0d354 517 u64 ret;
e4d6b795
MB		 518
519 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
520 ret <<= 16;
35f0d354
MB		 521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
522 ret <<= 16;
e4d6b795
MB		 523 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
524
525 return ret;
526}
527
528/* Write HostFlags */
35f0d354 529void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 530{
35f0d354
MB		 531 u16 lo, mi, hi;
532
533 lo = (value & 0x00000000FFFFULL);
534 mi = (value & 0x0000FFFF0000ULL) >> 16;
535 hi = (value & 0xFFFF00000000ULL) >> 32;
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
538 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 539}
540
403a3a13
MB		 541/* Read the firmware capabilities bitmask (Opensource firmware only) */
542static u16 b43_fwcapa_read(struct b43_wldev *dev)
543{
544 B43_WARN_ON(!dev->fw.opensource);
545 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
546}
547
3ebbbb56 548void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 549{
3ebbbb56
MB		 550 u32 low, high;
551
552 B43_WARN_ON(dev->dev->id.revision < 3);
553
554 /* The hardware guarantees us an atomic read, if we
555 * read the low register first. */
556 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
557 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
558
559 *tsf = high;
560 *tsf <<= 32;
561 *tsf |= low;
e4d6b795
MB		 562}
563
564static void b43_time_lock(struct b43_wldev *dev)
565{
566 u32 macctl;
567
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl |= B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
573}
574
575static void b43_time_unlock(struct b43_wldev *dev)
576{
577 u32 macctl;
578
579 macctl = b43_read32(dev, B43_MMIO_MACCTL);
580 macctl &= ~B43_MACCTL_TBTTHOLD;
581 b43_write32(dev, B43_MMIO_MACCTL, macctl);
582 /* Commit the write */
583 b43_read32(dev, B43_MMIO_MACCTL);
584}
585
586static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
587{
3ebbbb56
MB		 588 u32 low, high;
589
590 B43_WARN_ON(dev->dev->id.revision < 3);
591
592 low = tsf;
593 high = (tsf >> 32);
594 /* The hardware guarantees us an atomic write, if we
595 * write the low register first. */
596 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
597 mmiowb();
598 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
599 mmiowb();
e4d6b795
MB		 600}
601
602void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
603{
604 b43_time_lock(dev);
605 b43_tsf_write_locked(dev, tsf);
606 b43_time_unlock(dev);
607}
608
609static
99da185a 610void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 611{
612 static const u8 zero_addr[ETH_ALEN] = { 0 };
613 u16 data;
614
615 if (!mac)
616 mac = zero_addr;
617
618 offset |= 0x0020;
619 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
620
621 data = mac[0];
622 data |= mac[1] << 8;
623 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
624 data = mac[2];
625 data |= mac[3] << 8;
626 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
627 data = mac[4];
628 data |= mac[5] << 8;
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630}
631
632static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
633{
634 const u8 *mac;
635 const u8 *bssid;
636 u8 mac_bssid[ETH_ALEN * 2];
637 int i;
638 u32 tmp;
639
640 bssid = dev->wl->bssid;
641 mac = dev->wl->mac_addr;
642
643 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
644
645 memcpy(mac_bssid, mac, ETH_ALEN);
646 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
647
648 /* Write our MAC address and BSSID to template ram */
649 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
650 tmp = (u32) (mac_bssid[i + 0]);
651 tmp |= (u32) (mac_bssid[i + 1]) << 8;
652 tmp |= (u32) (mac_bssid[i + 2]) << 16;
653 tmp |= (u32) (mac_bssid[i + 3]) << 24;
654 b43_ram_write(dev, 0x20 + i, tmp);
655 }
656}
657
4150c572 658static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 659{
e4d6b795 660 b43_write_mac_bssid_templates(dev);
4150c572 661 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 662}
663
664static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
665{
666 /* slot_time is in usec. */
667 if (dev->phy.type != B43_PHYTYPE_G)
668 return;
669 b43_write16(dev, 0x684, 510 + slot_time);
670 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
671}
672
673static void b43_short_slot_timing_enable(struct b43_wldev *dev)
674{
675 b43_set_slot_time(dev, 9);
e4d6b795
MB		 676}
677
678static void b43_short_slot_timing_disable(struct b43_wldev *dev)
679{
680 b43_set_slot_time(dev, 20);
e4d6b795
MB		 681}
682
e4d6b795
MB		 683/* Synchronize IRQ top- and bottom-half.
684 * IRQs must be masked before calling this.
685 * This must not be called with the irq_lock held.
686 */
687static void b43_synchronize_irq(struct b43_wldev *dev)
688{
689 synchronize_irq(dev->dev->irq);
690 tasklet_kill(&dev->isr_tasklet);
691}
692
693/* DummyTransmission function, as documented on
694 * http://bcm-specs.sipsolutions.net/DummyTransmission
695 */
696void b43_dummy_transmission(struct b43_wldev *dev)
697{
21a75d77 698 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 699 struct b43_phy *phy = &dev->phy;
700 unsigned int i, max_loop;
701 u16 value;
702 u32 buffer[5] = {
703 0x00000000,
704 0x00D40000,
705 0x00000000,
706 0x01000000,
707 0x00000000,
708 };
709
710 switch (phy->type) {
711 case B43_PHYTYPE_A:
712 max_loop = 0x1E;
713 buffer[0] = 0x000201CC;
714 break;
715 case B43_PHYTYPE_B:
716 case B43_PHYTYPE_G:
717 max_loop = 0xFA;
718 buffer[0] = 0x000B846E;
719 break;
720 default:
721 B43_WARN_ON(1);
722 return;
723 }
724
21a75d77
MB		 725 spin_lock_irq(&wl->irq_lock);
726 write_lock(&wl->tx_lock);
727
e4d6b795
MB		 728 for (i = 0; i < 5; i++)
729 b43_ram_write(dev, i * 4, buffer[i]);
730
731 /* Commit writes */
732 b43_read32(dev, B43_MMIO_MACCTL);
733
734 b43_write16(dev, 0x0568, 0x0000);
735 b43_write16(dev, 0x07C0, 0x0000);
736 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
737 b43_write16(dev, 0x050C, value);
738 b43_write16(dev, 0x0508, 0x0000);
739 b43_write16(dev, 0x050A, 0x0000);
740 b43_write16(dev, 0x054C, 0x0000);
741 b43_write16(dev, 0x056A, 0x0014);
742 b43_write16(dev, 0x0568, 0x0826);
743 b43_write16(dev, 0x0500, 0x0000);
744 b43_write16(dev, 0x0502, 0x0030);
745
746 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
747 b43_radio_write16(dev, 0x0051, 0x0017);
748 for (i = 0x00; i < max_loop; i++) {
749 value = b43_read16(dev, 0x050E);
750 if (value & 0x0080)
751 break;
752 udelay(10);
753 }
754 for (i = 0x00; i < 0x0A; i++) {
755 value = b43_read16(dev, 0x050E);
756 if (value & 0x0400)
757 break;
758 udelay(10);
759 }
1d280ddc 760 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 761 value = b43_read16(dev, 0x0690);
762 if (!(value & 0x0100))
763 break;
764 udelay(10);
765 }
766 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
767 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 768
769 write_unlock(&wl->tx_lock);
770 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 771}
772
773static void key_write(struct b43_wldev *dev,
99da185a 774 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 775{
776 unsigned int i;
777 u32 offset;
778 u16 value;
779 u16 kidx;
780
781 /* Key index/algo block */
782 kidx = b43_kidx_to_fw(dev, index);
783 value = ((kidx << 4) | algorithm);
784 b43_shm_write16(dev, B43_SHM_SHARED,
785 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
786
787 /* Write the key to the Key Table Pointer offset */
788 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
789 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
790 value = key[i];
791 value |= (u16) (key[i + 1]) << 8;
792 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
793 }
794}
795
99da185a 796static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 797{
798 u32 addrtmp[2] = { 0, 0, };
799 u8 per_sta_keys_start = 8;
800
801 if (b43_new_kidx_api(dev))
802 per_sta_keys_start = 4;
803
804 B43_WARN_ON(index < per_sta_keys_start);
805 /* We have two default TX keys and possibly two default RX keys.
806 * Physical mac 0 is mapped to physical key 4 or 8, depending
807 * on the firmware version.
808 * So we must adjust the index here.
809 */
810 index -= per_sta_keys_start;
811
812 if (addr) {
813 addrtmp[0] = addr[0];
814 addrtmp[0] |= ((u32) (addr[1]) << 8);
815 addrtmp[0] |= ((u32) (addr[2]) << 16);
816 addrtmp[0] |= ((u32) (addr[3]) << 24);
817 addrtmp[1] = addr[4];
818 addrtmp[1] |= ((u32) (addr[5]) << 8);
819 }
820
821 if (dev->dev->id.revision >= 5) {
822 /* Receive match transmitter address mechanism */
823 b43_shm_write32(dev, B43_SHM_RCMTA,
824 (index * 2) + 0, addrtmp[0]);
825 b43_shm_write16(dev, B43_SHM_RCMTA,
826 (index * 2) + 1, addrtmp[1]);
827 } else {
828 /* RXE (Receive Engine) and
829 * PSM (Programmable State Machine) mechanism
830 */
831 if (index < 8) {
832 /* TODO write to RCM 16, 19, 22 and 25 */
833 } else {
834 b43_shm_write32(dev, B43_SHM_SHARED,
835 B43_SHM_SH_PSM + (index * 6) + 0,
836 addrtmp[0]);
837 b43_shm_write16(dev, B43_SHM_SHARED,
838 B43_SHM_SH_PSM + (index * 6) + 4,
839 addrtmp[1]);
840 }
841 }
842}
843
844static void do_key_write(struct b43_wldev *dev,
845 u8 index, u8 algorithm,
99da185a 846 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 847{
848 u8 buf[B43_SEC_KEYSIZE] = { 0, };
849 u8 per_sta_keys_start = 8;
850
851 if (b43_new_kidx_api(dev))
852 per_sta_keys_start = 4;
853
854 B43_WARN_ON(index >= dev->max_nr_keys);
855 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
856
857 if (index >= per_sta_keys_start)
858 keymac_write(dev, index, NULL); /* First zero out mac. */
859 if (key)
860 memcpy(buf, key, key_len);
861 key_write(dev, index, algorithm, buf);
862 if (index >= per_sta_keys_start)
863 keymac_write(dev, index, mac_addr);
864
865 dev->key[index].algorithm = algorithm;
866}
867
868static int b43_key_write(struct b43_wldev *dev,
869 int index, u8 algorithm,
99da185a
JD		 870 const u8 *key, size_t key_len,
871 const u8 *mac_addr,
e4d6b795
MB		 872 struct ieee80211_key_conf *keyconf)
873{
874 int i;
875 int sta_keys_start;
876
877 if (key_len > B43_SEC_KEYSIZE)
878 return -EINVAL;
879 for (i = 0; i < dev->max_nr_keys; i++) {
880 /* Check that we don't already have this key. */
881 B43_WARN_ON(dev->key[i].keyconf == keyconf);
882 }
883 if (index < 0) {
e808e586 884 /* Pairwise key. Get an empty slot for the key. */
e4d6b795
MB		 885 if (b43_new_kidx_api(dev))
886 sta_keys_start = 4;
887 else
888 sta_keys_start = 8;
889 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
890 if (!dev->key[i].keyconf) {
891 /* found empty */
892 index = i;
893 break;
894 }
895 }
896 if (index < 0) {
e808e586 897 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 898 return -ENOSPC;
899 }
900 } else
901 B43_WARN_ON(index > 3);
902
903 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
904 if ((index <= 3) && !b43_new_kidx_api(dev)) {
905 /* Default RX key */
906 B43_WARN_ON(mac_addr);
907 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
908 }
909 keyconf->hw_key_idx = index;
910 dev->key[index].keyconf = keyconf;
911
912 return 0;
913}
914
915static int b43_key_clear(struct b43_wldev *dev, int index)
916{
917 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
918 return -EINVAL;
919 do_key_write(dev, index, B43_SEC_ALGO_NONE,
920 NULL, B43_SEC_KEYSIZE, NULL);
921 if ((index <= 3) && !b43_new_kidx_api(dev)) {
922 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
923 NULL, B43_SEC_KEYSIZE, NULL);
924 }
925 dev->key[index].keyconf = NULL;
926
927 return 0;
928}
929
930static void b43_clear_keys(struct b43_wldev *dev)
931{
932 int i;
933
934 for (i = 0; i < dev->max_nr_keys; i++)
935 b43_key_clear(dev, i);
936}
937
9cf7f247
MB		 938static void b43_dump_keymemory(struct b43_wldev *dev)
939{
940 unsigned int i, index, offset;
9cf7f247
MB		 941 u8 mac[ETH_ALEN];
942 u16 algo;
943 u32 rcmta0;
944 u16 rcmta1;
945 u64 hf;
946 struct b43_key *key;
947
948 if (!b43_debug(dev, B43_DBG_KEYS))
949 return;
950
951 hf = b43_hf_read(dev);
952 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
953 !!(hf & B43_HF_USEDEFKEYS));
954 for (index = 0; index < dev->max_nr_keys; index++) {
955 key = &(dev->key[index]);
956 printk(KERN_DEBUG "Key slot %02u: %s",
957 index, (key->keyconf == NULL) ? " " : "*");
958 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
959 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
960 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
961 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
962 }
963
964 algo = b43_shm_read16(dev, B43_SHM_SHARED,
965 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
966 printk(" Algo: %04X/%02X", algo, key->algorithm);
967
968 if (index >= 4) {
969 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
970 ((index - 4) * 2) + 0);
971 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
972 ((index - 4) * 2) + 1);
973 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
974 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 975 printk(" MAC: %pM", mac);
9cf7f247
MB		 976 } else
977 printk(" DEFAULT KEY");
978 printk("\n");
979 }
980}
981
e4d6b795
MB		 982void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
983{
984 u32 macctl;
985 u16 ucstat;
986 bool hwps;
987 bool awake;
988 int i;
989
990 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
991 (ps_flags & B43_PS_DISABLED));
992 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
993
994 if (ps_flags & B43_PS_ENABLED) {
995 hwps = 1;
996 } else if (ps_flags & B43_PS_DISABLED) {
997 hwps = 0;
998 } else {
999 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1000 // and thus is not an AP and we are associated, set bit 25
1001 }
1002 if (ps_flags & B43_PS_AWAKE) {
1003 awake = 1;
1004 } else if (ps_flags & B43_PS_ASLEEP) {
1005 awake = 0;
1006 } else {
1007 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1008 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1009 // successful, set bit26
1010 }
1011
1012/* FIXME: For now we force awake-on and hwps-off */
1013 hwps = 0;
1014 awake = 1;
1015
1016 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1017 if (hwps)
1018 macctl |= B43_MACCTL_HWPS;
1019 else
1020 macctl &= ~B43_MACCTL_HWPS;
1021 if (awake)
1022 macctl |= B43_MACCTL_AWAKE;
1023 else
1024 macctl &= ~B43_MACCTL_AWAKE;
1025 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1026 /* Commit write */
1027 b43_read32(dev, B43_MMIO_MACCTL);
1028 if (awake && dev->dev->id.revision >= 5) {
1029 /* Wait for the microcode to wake up. */
1030 for (i = 0; i < 100; i++) {
1031 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1032 B43_SHM_SH_UCODESTAT);
1033 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1034 break;
1035 udelay(10);
1036 }
1037 }
1038}
1039
e4d6b795
MB		 1040void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1041{
1042 u32 tmslow;
1043 u32 macctl;
1044
1045 flags |= B43_TMSLOW_PHYCLKEN;
1046 flags |= B43_TMSLOW_PHYRESET;
1047 ssb_device_enable(dev->dev, flags);
1048 msleep(2); /* Wait for the PLL to turn on. */
1049
1050 /* Now take the PHY out of Reset again */
1051 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1052 tmslow |= SSB_TMSLOW_FGC;
1053 tmslow &= ~B43_TMSLOW_PHYRESET;
1054 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1055 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1056 msleep(1);
1057 tmslow &= ~SSB_TMSLOW_FGC;
1058 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1059 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1060 msleep(1);
1061
fb11137a
MB		 1062 /* Turn Analog ON, but only if we already know the PHY-type.
1063 * This protects against very early setup where we don't know the
1064 * PHY-type, yet. wireless_core_reset will be called once again later,
1065 * when we know the PHY-type. */
1066 if (dev->phy.ops)
cb24f57f 1067 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1068
1069 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1070 macctl &= ~B43_MACCTL_GMODE;
1071 if (flags & B43_TMSLOW_GMODE)
1072 macctl |= B43_MACCTL_GMODE;
1073 macctl |= B43_MACCTL_IHR_ENABLED;
1074 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1075}
1076
1077static void handle_irq_transmit_status(struct b43_wldev *dev)
1078{
1079 u32 v0, v1;
1080 u16 tmp;
1081 struct b43_txstatus stat;
1082
1083 while (1) {
1084 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1085 if (!(v0 & 0x00000001))
1086 break;
1087 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1088
1089 stat.cookie = (v0 >> 16);
1090 stat.seq = (v1 & 0x0000FFFF);
1091 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1092 tmp = (v0 & 0x0000FFFF);
1093 stat.frame_count = ((tmp & 0xF000) >> 12);
1094 stat.rts_count = ((tmp & 0x0F00) >> 8);
1095 stat.supp_reason = ((tmp & 0x001C) >> 2);
1096 stat.pm_indicated = !!(tmp & 0x0080);
1097 stat.intermediate = !!(tmp & 0x0040);
1098 stat.for_ampdu = !!(tmp & 0x0020);
1099 stat.acked = !!(tmp & 0x0002);
1100
1101 b43_handle_txstatus(dev, &stat);
1102 }
1103}
1104
1105static void drain_txstatus_queue(struct b43_wldev *dev)
1106{
1107 u32 dummy;
1108
1109 if (dev->dev->id.revision < 5)
1110 return;
1111 /* Read all entries from the microcode TXstatus FIFO
1112 * and throw them away.
1113 */
1114 while (1) {
1115 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1116 if (!(dummy & 0x00000001))
1117 break;
1118 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1119 }
1120}
1121
1122static u32 b43_jssi_read(struct b43_wldev *dev)
1123{
1124 u32 val = 0;
1125
1126 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1127 val <<= 16;
1128 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1129
1130 return val;
1131}
1132
1133static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1134{
1135 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1136 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1137}
1138
1139static void b43_generate_noise_sample(struct b43_wldev *dev)
1140{
1141 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1142 b43_write32(dev, B43_MMIO_MACCMD,
1143 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1144}
1145
1146static void b43_calculate_link_quality(struct b43_wldev *dev)
1147{
1148 /* Top half of Link Quality calculation. */
1149
ef1a628d
MB		 1150 if (dev->phy.type != B43_PHYTYPE_G)
1151 return;
e4d6b795
MB		 1152 if (dev->noisecalc.calculation_running)
1153 return;
e4d6b795
MB		 1154 dev->noisecalc.calculation_running = 1;
1155 dev->noisecalc.nr_samples = 0;
1156
1157 b43_generate_noise_sample(dev);
1158}
1159
1160static void handle_irq_noise(struct b43_wldev *dev)
1161{
ef1a628d 1162 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1163 u16 tmp;
1164 u8 noise[4];
1165 u8 i, j;
1166 s32 average;
1167
1168 /* Bottom half of Link Quality calculation. */
1169
ef1a628d
MB		 1170 if (dev->phy.type != B43_PHYTYPE_G)
1171 return;
1172
98a3b2fe
MB		 1173 /* Possible race condition: It might be possible that the user
1174 * changed to a different channel in the meantime since we
1175 * started the calculation. We ignore that fact, since it's
1176 * not really that much of a problem. The background noise is
1177 * an estimation only anyway. Slightly wrong results will get damped
1178 * by the averaging of the 8 sample rounds. Additionally the
1179 * value is shortlived. So it will be replaced by the next noise
1180 * calculation round soon. */
1181
e4d6b795 1182 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1183 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1184 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1185 noise[2] == 0x7F || noise[3] == 0x7F)
1186 goto generate_new;
1187
1188 /* Get the noise samples. */
1189 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1190 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1191 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1192 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1193 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1195 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1196 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1197 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1198 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1199 dev->noisecalc.nr_samples++;
1200 if (dev->noisecalc.nr_samples == 8) {
1201 /* Calculate the Link Quality by the noise samples. */
1202 average = 0;
1203 for (i = 0; i < 8; i++) {
1204 for (j = 0; j < 4; j++)
1205 average += dev->noisecalc.samples[i][j];
1206 }
1207 average /= (8 * 4);
1208 average *= 125;
1209 average += 64;
1210 average /= 128;
1211 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1212 tmp = (tmp / 128) & 0x1F;
1213 if (tmp >= 8)
1214 average += 2;
1215 else
1216 average -= 25;
1217 if (tmp == 8)
1218 average -= 72;
1219 else
1220 average -= 48;
1221
1222 dev->stats.link_noise = average;
e4d6b795
MB		 1223 dev->noisecalc.calculation_running = 0;
1224 return;
1225 }
98a3b2fe 1226generate_new:
e4d6b795
MB		 1227 b43_generate_noise_sample(dev);
1228}
1229
1230static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1231{
05c914fe 1232 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1233 ///TODO: PS TBTT
1234 } else {
1235 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1236 b43_power_saving_ctl_bits(dev, 0);
1237 }
05c914fe 1238 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1239 dev->dfq_valid = 1;
e4d6b795
MB		 1240}
1241
1242static void handle_irq_atim_end(struct b43_wldev *dev)
1243{
aa6c7ae2
MB		 1244 if (dev->dfq_valid) {
1245 b43_write32(dev, B43_MMIO_MACCMD,
1246 b43_read32(dev, B43_MMIO_MACCMD)
1247 | B43_MACCMD_DFQ_VALID);
1248 dev->dfq_valid = 0;
1249 }
e4d6b795
MB		 1250}
1251
1252static void handle_irq_pmq(struct b43_wldev *dev)
1253{
1254 u32 tmp;
1255
1256 //TODO: AP mode.
1257
1258 while (1) {
1259 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1260 if (!(tmp & 0x00000008))
1261 break;
1262 }
1263 /* 16bit write is odd, but correct. */
1264 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1265}
1266
1267static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1268 const u8 *data, u16 size,
e4d6b795
MB		 1269 u16 ram_offset,
1270 u16 shm_size_offset, u8 rate)
1271{
1272 u32 i, tmp;
1273 struct b43_plcp_hdr4 plcp;
1274
1275 plcp.data = 0;
1276 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1277 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1278 ram_offset += sizeof(u32);
1279 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1280 * So leave the first two bytes of the next write blank.
1281 */
1282 tmp = (u32) (data[0]) << 16;
1283 tmp |= (u32) (data[1]) << 24;
1284 b43_ram_write(dev, ram_offset, tmp);
1285 ram_offset += sizeof(u32);
1286 for (i = 2; i < size; i += sizeof(u32)) {
1287 tmp = (u32) (data[i + 0]);
1288 if (i + 1 < size)
1289 tmp |= (u32) (data[i + 1]) << 8;
1290 if (i + 2 < size)
1291 tmp |= (u32) (data[i + 2]) << 16;
1292 if (i + 3 < size)
1293 tmp |= (u32) (data[i + 3]) << 24;
1294 b43_ram_write(dev, ram_offset + i - 2, tmp);
1295 }
1296 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1297 size + sizeof(struct b43_plcp_hdr6));
1298}
1299
5042c507
MB		 1300/* Check if the use of the antenna that ieee80211 told us to
1301 * use is possible. This will fall back to DEFAULT.
1302 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1303u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1304 u8 antenna_nr)
1305{
1306 u8 antenna_mask;
1307
1308 if (antenna_nr == 0) {
1309 /* Zero means "use default antenna". That's always OK. */
1310 return 0;
1311 }
1312
1313 /* Get the mask of available antennas. */
1314 if (dev->phy.gmode)
1315 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1316 else
1317 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1318
1319 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1320 /* This antenna is not available. Fall back to default. */
1321 return 0;
1322 }
1323
1324 return antenna_nr;
1325}
1326
5042c507
MB		 1327/* Convert a b43 antenna number value to the PHY TX control value. */
1328static u16 b43_antenna_to_phyctl(int antenna)
1329{
1330 switch (antenna) {
1331 case B43_ANTENNA0:
1332 return B43_TXH_PHY_ANT0;
1333 case B43_ANTENNA1:
1334 return B43_TXH_PHY_ANT1;
1335 case B43_ANTENNA2:
1336 return B43_TXH_PHY_ANT2;
1337 case B43_ANTENNA3:
1338 return B43_TXH_PHY_ANT3;
1339 case B43_ANTENNA_AUTO:
1340 return B43_TXH_PHY_ANT01AUTO;
1341 }
1342 B43_WARN_ON(1);
1343 return 0;
1344}
1345
e4d6b795
MB		 1346static void b43_write_beacon_template(struct b43_wldev *dev,
1347 u16 ram_offset,
5042c507 1348 u16 shm_size_offset)
e4d6b795 1349{
47f76ca3 1350 unsigned int i, len, variable_len;
e66fee6a
MB		 1351 const struct ieee80211_mgmt *bcn;
1352 const u8 *ie;
1353 bool tim_found = 0;
5042c507
MB		 1354 unsigned int rate;
1355 u16 ctl;
1356 int antenna;
e039fa4a 1357 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1358
e66fee6a
MB		 1359 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1360 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1361 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1362 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1363
1364 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1365 len, ram_offset, shm_size_offset, rate);
e66fee6a 1366
5042c507 1367 /* Write the PHY TX control parameters. */
0f4ac38b 1368 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1369 antenna = b43_antenna_to_phyctl(antenna);
1370 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1371 /* We can't send beacons with short preamble. Would get PHY errors. */
1372 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1373 ctl &= ~B43_TXH_PHY_ANT;
1374 ctl &= ~B43_TXH_PHY_ENC;
1375 ctl |= antenna;
1376 if (b43_is_cck_rate(rate))
1377 ctl |= B43_TXH_PHY_ENC_CCK;
1378 else
1379 ctl |= B43_TXH_PHY_ENC_OFDM;
1380 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1381
e66fee6a
MB		 1382 /* Find the position of the TIM and the DTIM_period value
1383 * and write them to SHM. */
1384 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1385 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1386 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1387 uint8_t ie_id, ie_len;
1388
1389 ie_id = ie[i];
1390 ie_len = ie[i + 1];
1391 if (ie_id == 5) {
1392 u16 tim_position;
1393 u16 dtim_period;
1394 /* This is the TIM Information Element */
1395
1396 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1397 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1398 break;
1399 /* A valid TIM is at least 4 bytes long. */
1400 if (ie_len < 4)
1401 break;
1402 tim_found = 1;
1403
1404 tim_position = sizeof(struct b43_plcp_hdr6);
1405 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1406 tim_position += i;
1407
1408 dtim_period = ie[i + 3];
1409
1410 b43_shm_write16(dev, B43_SHM_SHARED,
1411 B43_SHM_SH_TIMBPOS, tim_position);
1412 b43_shm_write16(dev, B43_SHM_SHARED,
1413 B43_SHM_SH_DTIMPER, dtim_period);
1414 break;
1415 }
1416 i += ie_len + 2;
1417 }
1418 if (!tim_found) {
04dea136
JB		 1419 /*
1420 * If ucode wants to modify TIM do it behind the beacon, this
1421 * will happen, for example, when doing mesh networking.
1422 */
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1424 B43_SHM_SH_TIMBPOS,
1425 len + sizeof(struct b43_plcp_hdr6));
1426 b43_shm_write16(dev, B43_SHM_SHARED,
1427 B43_SHM_SH_DTIMPER, 0);
1428 }
1429 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1430}
1431
1432static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1433 u16 shm_offset, u16 size,
1434 struct ieee80211_rate *rate)
e4d6b795
MB		 1435{
1436 struct b43_plcp_hdr4 plcp;
1437 u32 tmp;
1438 __le16 dur;
1439
1440 plcp.data = 0;
8318d78a 1441 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1442 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1443 dev->wl->vif, size,
8318d78a 1444 rate);
e4d6b795
MB		 1445 /* Write PLCP in two parts and timing for packet transfer */
1446 tmp = le32_to_cpu(plcp.data);
1447 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1448 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1449 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1450}
1451
1452/* Instead of using custom probe response template, this function
1453 * just patches custom beacon template by:
1454 * 1) Changing packet type
1455 * 2) Patching duration field
1456 * 3) Stripping TIM
1457 */
99da185a
JD		 1458static const u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1459 u16 *dest_size,
1460 struct ieee80211_rate *rate)
e4d6b795
MB		 1461{
1462 const u8 *src_data;
1463 u8 *dest_data;
1464 u16 src_size, elem_size, src_pos, dest_pos;
1465 __le16 dur;
1466 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1467 size_t ie_start;
1468
1469 src_size = dev->wl->current_beacon->len;
1470 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1471
e66fee6a
MB		 1472 /* Get the start offset of the variable IEs in the packet. */
1473 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1474 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1475
e66fee6a 1476 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1477 return NULL;
e4d6b795
MB		 1478
1479 dest_data = kmalloc(src_size, GFP_ATOMIC);
1480 if (unlikely(!dest_data))
1481 return NULL;
1482
e66fee6a
MB		 1483 /* Copy the static data and all Information Elements, except the TIM. */
1484 memcpy(dest_data, src_data, ie_start);
1485 src_pos = ie_start;
1486 dest_pos = ie_start;
1487 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1488 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1489 if (src_data[src_pos] == 5) {
1490 /* This is the TIM. */
1491 continue;
e4d6b795 1492 }
e66fee6a
MB		 1493 memcpy(dest_data + dest_pos, src_data + src_pos,
1494 elem_size);
1495 dest_pos += elem_size;
e4d6b795
MB		 1496 }
1497 *dest_size = dest_pos;
1498 hdr = (struct ieee80211_hdr *)dest_data;
1499
1500 /* Set the frame control. */
1501 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1502 IEEE80211_STYPE_PROBE_RESP);
1503 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1504 dev->wl->vif, *dest_size,
8318d78a 1505 rate);
e4d6b795
MB		 1506 hdr->duration_id = dur;
1507
1508 return dest_data;
1509}
1510
1511static void b43_write_probe_resp_template(struct b43_wldev *dev,
1512 u16 ram_offset,
8318d78a
JB		 1513 u16 shm_size_offset,
1514 struct ieee80211_rate *rate)
e4d6b795 1515{
e66fee6a 1516 const u8 *probe_resp_data;
e4d6b795
MB		 1517 u16 size;
1518
e66fee6a 1519 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1520 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1521 if (unlikely(!probe_resp_data))
1522 return;
1523
1524 /* Looks like PLCP headers plus packet timings are stored for
1525 * all possible basic rates
1526 */
8318d78a
JB		 1527 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1528 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1529 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1530 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1531
1532 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1533 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1534 size, ram_offset, shm_size_offset,
1535 rate->hw_value);
e4d6b795
MB		 1536 kfree(probe_resp_data);
1537}
1538
6b4bec01
MB		 1539static void b43_upload_beacon0(struct b43_wldev *dev)
1540{
1541 struct b43_wl *wl = dev->wl;
1542
1543 if (wl->beacon0_uploaded)
1544 return;
1545 b43_write_beacon_template(dev, 0x68, 0x18);
1546 /* FIXME: Probe resp upload doesn't really belong here,
1547 * but we don't use that feature anyway. */
1548 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1549 &__b43_ratetable[3]);
1550 wl->beacon0_uploaded = 1;
1551}
1552
1553static void b43_upload_beacon1(struct b43_wldev *dev)
1554{
1555 struct b43_wl *wl = dev->wl;
1556
1557 if (wl->beacon1_uploaded)
1558 return;
1559 b43_write_beacon_template(dev, 0x468, 0x1A);
1560 wl->beacon1_uploaded = 1;
1561}
1562
c97a4ccc
MB		 1563static void handle_irq_beacon(struct b43_wldev *dev)
1564{
1565 struct b43_wl *wl = dev->wl;
1566 u32 cmd, beacon0_valid, beacon1_valid;
1567
05c914fe
JB		 1568 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1569 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1570 return;
1571
1572 /* This is the bottom half of the asynchronous beacon update. */
1573
1574 /* Ignore interrupt in the future. */
13790728 1575 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1576
1577 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1578 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1579 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1580
1581 /* Schedule interrupt manually, if busy. */
1582 if (beacon0_valid && beacon1_valid) {
1583 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1584 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1585 return;
1586 }
1587
6b4bec01
MB		 1588 if (unlikely(wl->beacon_templates_virgin)) {
1589 /* We never uploaded a beacon before.
1590 * Upload both templates now, but only mark one valid. */
1591 wl->beacon_templates_virgin = 0;
1592 b43_upload_beacon0(dev);
1593 b43_upload_beacon1(dev);
c97a4ccc
MB		 1594 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1595 cmd |= B43_MACCMD_BEACON0_VALID;
1596 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1597 } else {
1598 if (!beacon0_valid) {
1599 b43_upload_beacon0(dev);
1600 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1601 cmd |= B43_MACCMD_BEACON0_VALID;
1602 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1603 } else if (!beacon1_valid) {
1604 b43_upload_beacon1(dev);
1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON1_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1608 }
c97a4ccc
MB		 1609 }
1610}
1611
a82d9922
MB		 1612static void b43_beacon_update_trigger_work(struct work_struct *work)
1613{
1614 struct b43_wl *wl = container_of(work, struct b43_wl,
1615 beacon_update_trigger);
1616 struct b43_wldev *dev;
1617
1618 mutex_lock(&wl->mutex);
1619 dev = wl->current_dev;
1620 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1621 spin_lock_irq(&wl->irq_lock);
c97a4ccc 1622 /* update beacon right away or defer to irq */
c97a4ccc
MB		 1623 handle_irq_beacon(dev);
1624 /* The handler might have updated the IRQ mask. */
13790728 1625 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
c97a4ccc 1626 mmiowb();
a82d9922
MB		 1627 spin_unlock_irq(&wl->irq_lock);
1628 }
1629 mutex_unlock(&wl->mutex);
1630}
1631
d4df6f1a
MB		 1632/* Asynchronously update the packet templates in template RAM.
1633 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1634static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1635{
9d139c81
JB		 1636 struct sk_buff *beacon;
1637
e66fee6a
MB		 1638 /* This is the top half of the ansynchronous beacon update.
1639 * The bottom half is the beacon IRQ.
1640 * Beacon update must be asynchronous to avoid sending an
1641 * invalid beacon. This can happen for example, if the firmware
1642 * transmits a beacon while we are updating it. */
e4d6b795 1643
9d139c81
JB		 1644 /* We could modify the existing beacon and set the aid bit in
1645 * the TIM field, but that would probably require resizing and
1646 * moving of data within the beacon template.
1647 * Simply request a new beacon and let mac80211 do the hard work. */
1648 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1649 if (unlikely(!beacon))
1650 return;
1651
e66fee6a
MB		 1652 if (wl->current_beacon)
1653 dev_kfree_skb_any(wl->current_beacon);
1654 wl->current_beacon = beacon;
1655 wl->beacon0_uploaded = 0;
1656 wl->beacon1_uploaded = 0;
a82d9922 1657 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1658}
1659
e4d6b795
MB		 1660static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1661{
1662 b43_time_lock(dev);
1663 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1664 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1665 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1666 } else {
1667 b43_write16(dev, 0x606, (beacon_int >> 6));
1668 b43_write16(dev, 0x610, beacon_int);
1669 }
1670 b43_time_unlock(dev);
a82d9922 1671 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1672}
1673
afa83e23
MB		 1674static void b43_handle_firmware_panic(struct b43_wldev *dev)
1675{
1676 u16 reason;
1677
1678 /* Read the register that contains the reason code for the panic. */
1679 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1680 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1681
1682 switch (reason) {
1683 default:
1684 b43dbg(dev->wl, "The panic reason is unknown.\n");
1685 /* fallthrough */
1686 case B43_FWPANIC_DIE:
1687 /* Do not restart the controller or firmware.
1688 * The device is nonfunctional from now on.
1689 * Restarting would result in this panic to trigger again,
1690 * so we avoid that recursion. */
1691 break;
1692 case B43_FWPANIC_RESTART:
1693 b43_controller_restart(dev, "Microcode panic");
1694 break;
1695 }
1696}
1697
e4d6b795
MB		 1698static void handle_irq_ucode_debug(struct b43_wldev *dev)
1699{
e48b0eeb 1700 unsigned int i, cnt;
53c06856 1701 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1702 __le16 *buf;
1703
1704 /* The proprietary firmware doesn't have this IRQ. */
1705 if (!dev->fw.opensource)
1706 return;
1707
afa83e23
MB		 1708 /* Read the register that contains the reason code for this IRQ. */
1709 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1710
e48b0eeb
MB		 1711 switch (reason) {
1712 case B43_DEBUGIRQ_PANIC:
afa83e23 1713 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1714 break;
1715 case B43_DEBUGIRQ_DUMP_SHM:
1716 if (!B43_DEBUG)
1717 break; /* Only with driver debugging enabled. */
1718 buf = kmalloc(4096, GFP_ATOMIC);
1719 if (!buf) {
1720 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1721 goto out;
1722 }
1723 for (i = 0; i < 4096; i += 2) {
1724 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1725 buf[i / 2] = cpu_to_le16(tmp);
1726 }
1727 b43info(dev->wl, "Shared memory dump:\n");
1728 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1729 16, 2, buf, 4096, 1);
1730 kfree(buf);
1731 break;
1732 case B43_DEBUGIRQ_DUMP_REGS:
1733 if (!B43_DEBUG)
1734 break; /* Only with driver debugging enabled. */
1735 b43info(dev->wl, "Microcode register dump:\n");
1736 for (i = 0, cnt = 0; i < 64; i++) {
1737 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1738 if (cnt == 0)
1739 printk(KERN_INFO);
1740 printk("r%02u: 0x%04X ", i, tmp);
1741 cnt++;
1742 if (cnt == 6) {
1743 printk("\n");
1744 cnt = 0;
1745 }
1746 }
1747 printk("\n");
1748 break;
53c06856
MB		 1749 case B43_DEBUGIRQ_MARKER:
1750 if (!B43_DEBUG)
1751 break; /* Only with driver debugging enabled. */
1752 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1753 B43_MARKER_ID_REG);
1754 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1755 B43_MARKER_LINE_REG);
1756 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1757 "at line number %u\n",
1758 marker_id, marker_line);
1759 break;
e48b0eeb
MB		 1760 default:
1761 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1762 reason);
1763 }
1764out:
afa83e23
MB		 1765 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1766 b43_shm_write16(dev, B43_SHM_SCRATCH,
1767 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1768}
1769
1770/* Interrupt handler bottom-half */
1771static void b43_interrupt_tasklet(struct b43_wldev *dev)
1772{
1773 u32 reason;
1774 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1775 u32 merged_dma_reason = 0;
21954c36 1776 int i;
e4d6b795
MB		 1777 unsigned long flags;
1778
1779 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1780
1781 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1782
1783 reason = dev->irq_reason;
1784 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1785 dma_reason[i] = dev->dma_reason[i];
1786 merged_dma_reason |= dma_reason[i];
1787 }
1788
1789 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1790 b43err(dev->wl, "MAC transmission error\n");
1791
00e0b8cb 1792 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1793 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1794 rmb();
1795 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1796 atomic_set(&dev->phy.txerr_cnt,
1797 B43_PHY_TX_BADNESS_LIMIT);
1798 b43err(dev->wl, "Too many PHY TX errors, "
1799 "restarting the controller\n");
1800 b43_controller_restart(dev, "PHY TX errors");
1801 }
1802 }
e4d6b795
MB		 1803
1804 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1805 B43_DMAIRQ_NONFATALMASK))) {
1806 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1807 b43err(dev->wl, "Fatal DMA error: "
1808 "0x%08X, 0x%08X, 0x%08X, "
1809 "0x%08X, 0x%08X, 0x%08X\n",
1810 dma_reason[0], dma_reason[1],
1811 dma_reason[2], dma_reason[3],
1812 dma_reason[4], dma_reason[5]);
1813 b43_controller_restart(dev, "DMA error");
1814 mmiowb();
1815 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1816 return;
1817 }
1818 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1819 b43err(dev->wl, "DMA error: "
1820 "0x%08X, 0x%08X, 0x%08X, "
1821 "0x%08X, 0x%08X, 0x%08X\n",
1822 dma_reason[0], dma_reason[1],
1823 dma_reason[2], dma_reason[3],
1824 dma_reason[4], dma_reason[5]);
1825 }
1826 }
1827
1828 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1829 handle_irq_ucode_debug(dev);
1830 if (reason & B43_IRQ_TBTT_INDI)
1831 handle_irq_tbtt_indication(dev);
1832 if (reason & B43_IRQ_ATIM_END)
1833 handle_irq_atim_end(dev);
1834 if (reason & B43_IRQ_BEACON)
1835 handle_irq_beacon(dev);
1836 if (reason & B43_IRQ_PMQ)
1837 handle_irq_pmq(dev);
21954c36
MB		 1838 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1839 ;/* TODO */
1840 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1841 handle_irq_noise(dev);
1842
1843 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1844 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1845 if (b43_using_pio_transfers(dev))
1846 b43_pio_rx(dev->pio.rx_queue);
1847 else
1848 b43_dma_rx(dev->dma.rx_ring);
1849 }
e4d6b795
MB		 1850 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1851 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1852 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1853 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1854 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1855
21954c36 1856 if (reason & B43_IRQ_TX_OK)
e4d6b795 1857 handle_irq_transmit_status(dev);
e4d6b795 1858
13790728 1859 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1860 mmiowb();
1861 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1862}
1863
e4d6b795
MB		 1864static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1865{
e4d6b795
MB		 1866 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1867
1868 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1869 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1870 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1871 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1872 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
13790728 1873/* Unused ring
e4d6b795 1874 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
13790728 1875*/
e4d6b795
MB		 1876}
1877
1878/* Interrupt handler top-half */
1879static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1880{
1881 irqreturn_t ret = IRQ_NONE;
1882 struct b43_wldev *dev = dev_id;
1883 u32 reason;
1884
13790728 1885 B43_WARN_ON(!dev);
e4d6b795
MB		 1886
1887 spin_lock(&dev->wl->irq_lock);
1888
13790728
MB		 1889 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1890 /* This can only happen on shared IRQ lines. */
e4d6b795 1891 goto out;
13790728 1892 }
e4d6b795
MB		 1893 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1894 if (reason == 0xffffffff) /* shared IRQ */
1895 goto out;
1896 ret = IRQ_HANDLED;
13790728 1897 reason &= dev->irq_mask;
e4d6b795
MB		 1898 if (!reason)
1899 goto out;
1900
1901 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1902 & 0x0001DC00;
1903 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1904 & 0x0000DC00;
1905 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1906 & 0x0000DC00;
1907 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1908 & 0x0001DC00;
1909 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1910 & 0x0000DC00;
13790728 1911/* Unused ring
e4d6b795
MB		 1912 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1913 & 0x0000DC00;
13790728 1914*/
e4d6b795
MB		 1915
1916 b43_interrupt_ack(dev, reason);
1917 /* disable all IRQs. They are enabled again in the bottom half. */
13790728 1918 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
e4d6b795
MB		 1919 /* save the reason code and call our bottom half. */
1920 dev->irq_reason = reason;
1921 tasklet_schedule(&dev->isr_tasklet);
13790728 1922out:
e4d6b795
MB		 1923 mmiowb();
1924 spin_unlock(&dev->wl->irq_lock);
1925
1926 return ret;
1927}
1928
1a9f5093 1929void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1930{
1931 release_firmware(fw->data);
1932 fw->data = NULL;
1933 fw->filename = NULL;
1934}
1935
e4d6b795
MB		 1936static void b43_release_firmware(struct b43_wldev *dev)
1937{
1a9f5093
MB		 1938 b43_do_release_fw(&dev->fw.ucode);
1939 b43_do_release_fw(&dev->fw.pcm);
1940 b43_do_release_fw(&dev->fw.initvals);
1941 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1942}
1943
eb189d8b 1944static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1945{
fc68ed4f
HE		 1946 const char text[] =
1947 "You must go to " \
1948 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1949 "and download the correct firmware for this driver version. " \
1950 "Please carefully read all instructions on this website.\n";
eb189d8b 1951
eb189d8b
MB		 1952 if (error)
1953 b43err(wl, text);
1954 else
1955 b43warn(wl, text);
e4d6b795
MB		 1956}
1957
1a9f5093
MB		 1958int b43_do_request_fw(struct b43_request_fw_context *ctx,
1959 const char *name,
1960 struct b43_firmware_file *fw)
e4d6b795 1961{
61cb5dd6 1962 const struct firmware *blob;
e4d6b795
MB		 1963 struct b43_fw_header *hdr;
1964 u32 size;
1965 int err;
1966
61cb5dd6
MB		 1967 if (!name) {
1968 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1969 /* FIXME: We should probably keep it anyway, to save some headache
1970 * on suspend/resume with multiband devices. */
1971 b43_do_release_fw(fw);
e4d6b795 1972 return 0;
61cb5dd6
MB		 1973 }
1974 if (fw->filename) {
1a9f5093
MB		 1975 if ((fw->type == ctx->req_type) &&
1976 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1977 return 0; /* Already have this fw. */
1978 /* Free the cached firmware first. */
1a9f5093
MB		 1979 /* FIXME: We should probably do this later after we successfully
1980 * got the new fw. This could reduce headache with multiband devices.
1981 * We could also redesign this to cache the firmware for all possible
1982 * bands all the time. */
1983 b43_do_release_fw(fw);
61cb5dd6 1984 }
e4d6b795 1985
1a9f5093
MB		 1986 switch (ctx->req_type) {
1987 case B43_FWTYPE_PROPRIETARY:
1988 snprintf(ctx->fwname, sizeof(ctx->fwname),
1989 "b43%s/%s.fw",
1990 modparam_fwpostfix, name);
1991 break;
1992 case B43_FWTYPE_OPENSOURCE:
1993 snprintf(ctx->fwname, sizeof(ctx->fwname),
1994 "b43-open%s/%s.fw",
1995 modparam_fwpostfix, name);
1996 break;
1997 default:
1998 B43_WARN_ON(1);
1999 return -ENOSYS;
2000 }
2001 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2002 if (err == -ENOENT) {
1a9f5093
MB		 2003 snprintf(ctx->errors[ctx->req_type],
2004 sizeof(ctx->errors[ctx->req_type]),
2005 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2006 return err;
2007 } else if (err) {
1a9f5093
MB		 2008 snprintf(ctx->errors[ctx->req_type],
2009 sizeof(ctx->errors[ctx->req_type]),
2010 "Firmware file \"%s\" request failed (err=%d)\n",
2011 ctx->fwname, err);
e4d6b795
MB		 2012 return err;
2013 }
61cb5dd6 2014 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2015 goto err_format;
61cb5dd6 2016 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2017 switch (hdr->type) {
2018 case B43_FW_TYPE_UCODE:
2019 case B43_FW_TYPE_PCM:
2020 size = be32_to_cpu(hdr->size);
61cb5dd6 2021 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2022 goto err_format;
2023 /* fallthrough */
2024 case B43_FW_TYPE_IV:
2025 if (hdr->ver != 1)
2026 goto err_format;
2027 break;
2028 default:
2029 goto err_format;
2030 }
2031
61cb5dd6
MB		 2032 fw->data = blob;
2033 fw->filename = name;
1a9f5093 2034 fw->type = ctx->req_type;
61cb5dd6
MB		 2035
2036 return 0;
e4d6b795
MB		 2037
2038err_format:
1a9f5093
MB		 2039 snprintf(ctx->errors[ctx->req_type],
2040 sizeof(ctx->errors[ctx->req_type]),
2041 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2042 release_firmware(blob);
2043
e4d6b795
MB		 2044 return -EPROTO;
2045}
2046
1a9f5093 2047static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2048{
1a9f5093
MB		 2049 struct b43_wldev *dev = ctx->dev;
2050 struct b43_firmware *fw = &ctx->dev->fw;
2051 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2052 const char *filename;
2053 u32 tmshigh;
2054 int err;
2055
61cb5dd6 2056 /* Get microcode */
e4d6b795 2057 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2058 if ((rev >= 5) && (rev <= 10))
2059 filename = "ucode5";
2060 else if ((rev >= 11) && (rev <= 12))
2061 filename = "ucode11";
2062 else if (rev >= 13)
2063 filename = "ucode13";
2064 else
2065 goto err_no_ucode;
1a9f5093 2066 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2067 if (err)
2068 goto err_load;
2069
2070 /* Get PCM code */
2071 if ((rev >= 5) && (rev <= 10))
2072 filename = "pcm5";
2073 else if (rev >= 11)
2074 filename = NULL;
2075 else
2076 goto err_no_pcm;
68217832 2077 fw->pcm_request_failed = 0;
1a9f5093 2078 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2079 if (err == -ENOENT) {
2080 /* We did not find a PCM file? Not fatal, but
2081 * core rev <= 10 must do without hwcrypto then. */
2082 fw->pcm_request_failed = 1;
2083 } else if (err)
61cb5dd6
MB		 2084 goto err_load;
2085
2086 /* Get initvals */
2087 switch (dev->phy.type) {
2088 case B43_PHYTYPE_A:
2089 if ((rev >= 5) && (rev <= 10)) {
2090 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2091 filename = "a0g1initvals5";
2092 else
2093 filename = "a0g0initvals5";
2094 } else
2095 goto err_no_initvals;
2096 break;
2097 case B43_PHYTYPE_G:
e4d6b795 2098 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2099 filename = "b0g0initvals5";
e4d6b795 2100 else if (rev >= 13)
e9304882 2101 filename = "b0g0initvals13";
e4d6b795 2102 else
61cb5dd6
MB		 2103 goto err_no_initvals;
2104 break;
2105 case B43_PHYTYPE_N:
2106 if ((rev >= 11) && (rev <= 12))
2107 filename = "n0initvals11";
2108 else
2109 goto err_no_initvals;
2110 break;
2111 default:
2112 goto err_no_initvals;
e4d6b795 2113 }
1a9f5093 2114 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2115 if (err)
2116 goto err_load;
2117
2118 /* Get bandswitch initvals */
2119 switch (dev->phy.type) {
2120 case B43_PHYTYPE_A:
2121 if ((rev >= 5) && (rev <= 10)) {
2122 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2123 filename = "a0g1bsinitvals5";
2124 else
2125 filename = "a0g0bsinitvals5";
2126 } else if (rev >= 11)
2127 filename = NULL;
2128 else
2129 goto err_no_initvals;
2130 break;
2131 case B43_PHYTYPE_G:
e4d6b795 2132 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2133 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2134 else if (rev >= 11)
2135 filename = NULL;
2136 else
e4d6b795 2137 goto err_no_initvals;
61cb5dd6
MB		 2138 break;
2139 case B43_PHYTYPE_N:
2140 if ((rev >= 11) && (rev <= 12))
2141 filename = "n0bsinitvals11";
2142 else
e4d6b795 2143 goto err_no_initvals;
61cb5dd6
MB		 2144 break;
2145 default:
2146 goto err_no_initvals;
e4d6b795 2147 }
1a9f5093 2148 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2149 if (err)
2150 goto err_load;
e4d6b795
MB		 2151
2152 return 0;
2153
e4d6b795 2154err_no_ucode:
1a9f5093
MB		 2155 err = ctx->fatal_failure = -EOPNOTSUPP;
2156 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2157 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2158 goto error;
2159
2160err_no_pcm:
1a9f5093
MB		 2161 err = ctx->fatal_failure = -EOPNOTSUPP;
2162 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2163 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2164 goto error;
2165
2166err_no_initvals:
1a9f5093
MB		 2167 err = ctx->fatal_failure = -EOPNOTSUPP;
2168 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2169 "is required for your device (wl-core rev %u)\n", rev);
2170 goto error;
2171
2172err_load:
2173 /* We failed to load this firmware image. The error message
2174 * already is in ctx->errors. Return and let our caller decide
2175 * what to do. */
e4d6b795
MB		 2176 goto error;
2177
2178error:
2179 b43_release_firmware(dev);
2180 return err;
2181}
2182
1a9f5093
MB		 2183static int b43_request_firmware(struct b43_wldev *dev)
2184{
2185 struct b43_request_fw_context *ctx;
2186 unsigned int i;
2187 int err;
2188 const char *errmsg;
2189
2190 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2191 if (!ctx)
2192 return -ENOMEM;
2193 ctx->dev = dev;
2194
2195 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2196 err = b43_try_request_fw(ctx);
2197 if (!err)
2198 goto out; /* Successfully loaded it. */
2199 err = ctx->fatal_failure;
2200 if (err)
2201 goto out;
2202
2203 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2204 err = b43_try_request_fw(ctx);
2205 if (!err)
2206 goto out; /* Successfully loaded it. */
2207 err = ctx->fatal_failure;
2208 if (err)
2209 goto out;
2210
2211 /* Could not find a usable firmware. Print the errors. */
2212 for (i = 0; i < B43_NR_FWTYPES; i++) {
2213 errmsg = ctx->errors[i];
2214 if (strlen(errmsg))
2215 b43err(dev->wl, errmsg);
2216 }
2217 b43_print_fw_helptext(dev->wl, 1);
2218 err = -ENOENT;
2219
2220out:
2221 kfree(ctx);
2222 return err;
2223}
2224
e4d6b795
MB		 2225static int b43_upload_microcode(struct b43_wldev *dev)
2226{
2227 const size_t hdr_len = sizeof(struct b43_fw_header);
2228 const __be32 *data;
2229 unsigned int i, len;
2230 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2231 u32 tmp, macctl;
e4d6b795
MB		 2232 int err = 0;
2233
1f7d87b0
MB		 2234 /* Jump the microcode PSM to offset 0 */
2235 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2236 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2237 macctl |= B43_MACCTL_PSM_JMP0;
2238 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2239 /* Zero out all microcode PSM registers and shared memory. */
2240 for (i = 0; i < 64; i++)
2241 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2242 for (i = 0; i < 4096; i += 2)
2243 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2244
e4d6b795 2245 /* Upload Microcode. */
61cb5dd6
MB		 2246 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2247 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2248 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2249 for (i = 0; i < len; i++) {
2250 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2251 udelay(10);
2252 }
2253
61cb5dd6 2254 if (dev->fw.pcm.data) {
e4d6b795 2255 /* Upload PCM data. */
61cb5dd6
MB		 2256 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2257 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2258 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2259 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2260 /* No need for autoinc bit in SHM_HW */
2261 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2262 for (i = 0; i < len; i++) {
2263 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2264 udelay(10);
2265 }
2266 }
2267
2268 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2269
2270 /* Start the microcode PSM */
2271 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2272 macctl &= ~B43_MACCTL_PSM_JMP0;
2273 macctl |= B43_MACCTL_PSM_RUN;
2274 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2275
2276 /* Wait for the microcode to load and respond */
2277 i = 0;
2278 while (1) {
2279 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2280 if (tmp == B43_IRQ_MAC_SUSPENDED)
2281 break;
2282 i++;
1f7d87b0 2283 if (i >= 20) {
e4d6b795 2284 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2285 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2286 err = -ENODEV;
1f7d87b0
MB		 2287 goto error;
2288 }
2289 msleep_interruptible(50);
2290 if (signal_pending(current)) {
2291 err = -EINTR;
2292 goto error;
e4d6b795 2293 }
e4d6b795
MB		 2294 }
2295 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2296
2297 /* Get and check the revisions. */
2298 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2299 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2300 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2301 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2302
2303 if (fwrev <= 0x128) {
2304 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2305 "binary drivers older than version 4.x is unsupported. "
2306 "You must upgrade your firmware files.\n");
eb189d8b 2307 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2308 err = -EOPNOTSUPP;
1f7d87b0 2309 goto error;
e4d6b795 2310 }
e4d6b795
MB		 2311 dev->fw.rev = fwrev;
2312 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2313 dev->fw.opensource = (fwdate == 0xFFFF);
2314
403a3a13
MB		 2315 /* Default to use-all-queues. */
2316 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2317 dev->qos_enabled = !!modparam_qos;
2318 /* Default to firmware/hardware crypto acceleration. */
2319 dev->hwcrypto_enabled = 1;
2320
e48b0eeb 2321 if (dev->fw.opensource) {
403a3a13
MB		 2322 u16 fwcapa;
2323
e48b0eeb
MB		 2324 /* Patchlevel info is encoded in the "time" field. */
2325 dev->fw.patch = fwtime;
403a3a13
MB		 2326 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2327 dev->fw.rev, dev->fw.patch);
2328
2329 fwcapa = b43_fwcapa_read(dev);
2330 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2331 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2332 /* Disable hardware crypto and fall back to software crypto. */
2333 dev->hwcrypto_enabled = 0;
2334 }
2335 if (!(fwcapa & B43_FWCAPA_QOS)) {
2336 b43info(dev->wl, "QoS not supported by firmware\n");
2337 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2338 * ieee80211_unregister to make sure the networking core can
2339 * properly free possible resources. */
2340 dev->wl->hw->queues = 1;
2341 dev->qos_enabled = 0;
2342 }
e48b0eeb
MB		 2343 } else {
2344 b43info(dev->wl, "Loading firmware version %u.%u "
2345 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2346 fwrev, fwpatch,
2347 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2348 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2349 if (dev->fw.pcm_request_failed) {
2350 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2351 "Hardware accelerated cryptography is disabled.\n");
2352 b43_print_fw_helptext(dev->wl, 0);
2353 }
e48b0eeb 2354 }
e4d6b795 2355
eb189d8b 2356 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2357 /* We're over the deadline, but we keep support for old fw
2358 * until it turns out to be in major conflict with something new. */
eb189d8b 2359 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2360 "Support for old firmware will be removed soon "
2361 "(official deadline was July 2008).\n");
eb189d8b
MB		 2362 b43_print_fw_helptext(dev->wl, 0);
2363 }
2364
1f7d87b0
MB		 2365 return 0;
2366
2367error:
2368 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2369 macctl &= ~B43_MACCTL_PSM_RUN;
2370 macctl |= B43_MACCTL_PSM_JMP0;
2371 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2372
e4d6b795
MB		 2373 return err;
2374}
2375
2376static int b43_write_initvals(struct b43_wldev *dev,
2377 const struct b43_iv *ivals,
2378 size_t count,
2379 size_t array_size)
2380{
2381 const struct b43_iv *iv;
2382 u16 offset;
2383 size_t i;
2384 bool bit32;
2385
2386 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2387 iv = ivals;
2388 for (i = 0; i < count; i++) {
2389 if (array_size < sizeof(iv->offset_size))
2390 goto err_format;
2391 array_size -= sizeof(iv->offset_size);
2392 offset = be16_to_cpu(iv->offset_size);
2393 bit32 = !!(offset & B43_IV_32BIT);
2394 offset &= B43_IV_OFFSET_MASK;
2395 if (offset >= 0x1000)
2396 goto err_format;
2397 if (bit32) {
2398 u32 value;
2399
2400 if (array_size < sizeof(iv->data.d32))
2401 goto err_format;
2402 array_size -= sizeof(iv->data.d32);
2403
533dd1b0 2404 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2405 b43_write32(dev, offset, value);
2406
2407 iv = (const struct b43_iv *)((const uint8_t *)iv +
2408 sizeof(__be16) +
2409 sizeof(__be32));
2410 } else {
2411 u16 value;
2412
2413 if (array_size < sizeof(iv->data.d16))
2414 goto err_format;
2415 array_size -= sizeof(iv->data.d16);
2416
2417 value = be16_to_cpu(iv->data.d16);
2418 b43_write16(dev, offset, value);
2419
2420 iv = (const struct b43_iv *)((const uint8_t *)iv +
2421 sizeof(__be16) +
2422 sizeof(__be16));
2423 }
2424 }
2425 if (array_size)
2426 goto err_format;
2427
2428 return 0;
2429
2430err_format:
2431 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2432 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2433
2434 return -EPROTO;
2435}
2436
2437static int b43_upload_initvals(struct b43_wldev *dev)
2438{
2439 const size_t hdr_len = sizeof(struct b43_fw_header);
2440 const struct b43_fw_header *hdr;
2441 struct b43_firmware *fw = &dev->fw;
2442 const struct b43_iv *ivals;
2443 size_t count;
2444 int err;
2445
61cb5dd6
MB		 2446 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2447 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2448 count = be32_to_cpu(hdr->size);
2449 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2450 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2451 if (err)
2452 goto out;
61cb5dd6
MB		 2453 if (fw->initvals_band.data) {
2454 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2455 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2456 count = be32_to_cpu(hdr->size);
2457 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2458 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2459 if (err)
2460 goto out;
2461 }
2462out:
2463
2464 return err;
2465}
2466
2467/* Initialize the GPIOs
2468 * http://bcm-specs.sipsolutions.net/GPIO
2469 */
2470static int b43_gpio_init(struct b43_wldev *dev)
2471{
2472 struct ssb_bus *bus = dev->dev->bus;
2473 struct ssb_device *gpiodev, *pcidev = NULL;
2474 u32 mask, set;
2475
2476 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2477 & ~B43_MACCTL_GPOUTSMSK);
2478
e4d6b795
MB		 2479 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2480 | 0x000F);
2481
2482 mask = 0x0000001F;
2483 set = 0x0000000F;
2484 if (dev->dev->bus->chip_id == 0x4301) {
2485 mask |= 0x0060;
2486 set |= 0x0060;
2487 }
2488 if (0 /* FIXME: conditional unknown */ ) {
2489 b43_write16(dev, B43_MMIO_GPIO_MASK,
2490 b43_read16(dev, B43_MMIO_GPIO_MASK)
2491 | 0x0100);
2492 mask |= 0x0180;
2493 set |= 0x0180;
2494 }
95de2841 2495 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2496 b43_write16(dev, B43_MMIO_GPIO_MASK,
2497 b43_read16(dev, B43_MMIO_GPIO_MASK)
2498 | 0x0200);
2499 mask |= 0x0200;
2500 set |= 0x0200;
2501 }
2502 if (dev->dev->id.revision >= 2)
2503 mask |= 0x0010; /* FIXME: This is redundant. */
2504
2505#ifdef CONFIG_SSB_DRIVER_PCICORE
2506 pcidev = bus->pcicore.dev;
2507#endif
2508 gpiodev = bus->chipco.dev ? : pcidev;
2509 if (!gpiodev)
2510 return 0;
2511 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2512 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2513 & mask) | set);
2514
2515 return 0;
2516}
2517
2518/* Turn off all GPIO stuff. Call this on module unload, for example. */
2519static void b43_gpio_cleanup(struct b43_wldev *dev)
2520{
2521 struct ssb_bus *bus = dev->dev->bus;
2522 struct ssb_device *gpiodev, *pcidev = NULL;
2523
2524#ifdef CONFIG_SSB_DRIVER_PCICORE
2525 pcidev = bus->pcicore.dev;
2526#endif
2527 gpiodev = bus->chipco.dev ? : pcidev;
2528 if (!gpiodev)
2529 return;
2530 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2531}
2532
2533/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2534void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2535{
923fd703
MB		 2536 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2537 u16 fwstate;
2538
2539 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2540 B43_SHM_SH_UCODESTAT);
2541 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2542 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2543 b43err(dev->wl, "b43_mac_enable(): The firmware "
2544 "should be suspended, but current state is %u\n",
2545 fwstate);
2546 }
2547 }
2548
e4d6b795
MB		 2549 dev->mac_suspended--;
2550 B43_WARN_ON(dev->mac_suspended < 0);
2551 if (dev->mac_suspended == 0) {
2552 b43_write32(dev, B43_MMIO_MACCTL,
2553 b43_read32(dev, B43_MMIO_MACCTL)
2554 | B43_MACCTL_ENABLED);
2555 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2556 B43_IRQ_MAC_SUSPENDED);
2557 /* Commit writes */
2558 b43_read32(dev, B43_MMIO_MACCTL);
2559 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2560 b43_power_saving_ctl_bits(dev, 0);
2561 }
2562}
2563
2564/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2565void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2566{
2567 int i;
2568 u32 tmp;
2569
05b64b36 2570 might_sleep();
e4d6b795 2571 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2572
e4d6b795
MB		 2573 if (dev->mac_suspended == 0) {
2574 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2575 b43_write32(dev, B43_MMIO_MACCTL,
2576 b43_read32(dev, B43_MMIO_MACCTL)
2577 & ~B43_MACCTL_ENABLED);
2578 /* force pci to flush the write */
2579 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2580 for (i = 35; i; i--) {
2581 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2582 if (tmp & B43_IRQ_MAC_SUSPENDED)
2583 goto out;
2584 udelay(10);
2585 }
2586 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2587 for (i = 40; i; i--) {
e4d6b795
MB		 2588 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2589 if (tmp & B43_IRQ_MAC_SUSPENDED)
2590 goto out;
05b64b36 2591 msleep(1);
e4d6b795
MB		 2592 }
2593 b43err(dev->wl, "MAC suspend failed\n");
2594 }
05b64b36 2595out:
e4d6b795
MB		 2596 dev->mac_suspended++;
2597}
2598
2599static void b43_adjust_opmode(struct b43_wldev *dev)
2600{
2601 struct b43_wl *wl = dev->wl;
2602 u32 ctl;
2603 u16 cfp_pretbtt;
2604
2605 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2606 /* Reset status to STA infrastructure mode. */
2607 ctl &= ~B43_MACCTL_AP;
2608 ctl &= ~B43_MACCTL_KEEP_CTL;
2609 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2610 ctl &= ~B43_MACCTL_KEEP_BAD;
2611 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2612 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2613 ctl |= B43_MACCTL_INFRA;
2614
05c914fe
JB		 2615 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2616 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2617 ctl |= B43_MACCTL_AP;
05c914fe 2618 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2619 ctl &= ~B43_MACCTL_INFRA;
2620
2621 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2622 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2623 if (wl->filter_flags & FIF_FCSFAIL)
2624 ctl |= B43_MACCTL_KEEP_BAD;
2625 if (wl->filter_flags & FIF_PLCPFAIL)
2626 ctl |= B43_MACCTL_KEEP_BADPLCP;
2627 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2628 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2629 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2630 ctl |= B43_MACCTL_BEACPROMISC;
2631
e4d6b795
MB		 2632 /* Workaround: On old hardware the HW-MAC-address-filter
2633 * doesn't work properly, so always run promisc in filter
2634 * it in software. */
2635 if (dev->dev->id.revision <= 4)
2636 ctl |= B43_MACCTL_PROMISC;
2637
2638 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2639
2640 cfp_pretbtt = 2;
2641 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2642 if (dev->dev->bus->chip_id == 0x4306 &&
2643 dev->dev->bus->chip_rev == 3)
2644 cfp_pretbtt = 100;
2645 else
2646 cfp_pretbtt = 50;
2647 }
2648 b43_write16(dev, 0x612, cfp_pretbtt);
2649}
2650
2651static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2652{
2653 u16 offset;
2654
2655 if (is_ofdm) {
2656 offset = 0x480;
2657 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2658 } else {
2659 offset = 0x4C0;
2660 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2661 }
2662 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2663 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2664}
2665
2666static void b43_rate_memory_init(struct b43_wldev *dev)
2667{
2668 switch (dev->phy.type) {
2669 case B43_PHYTYPE_A:
2670 case B43_PHYTYPE_G:
53a6e234 2671 case B43_PHYTYPE_N:
e4d6b795
MB		 2672 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2673 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2674 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2675 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2676 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2677 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2678 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2679 if (dev->phy.type == B43_PHYTYPE_A)
2680 break;
2681 /* fallthrough */
2682 case B43_PHYTYPE_B:
2683 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2684 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2685 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2686 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2687 break;
2688 default:
2689 B43_WARN_ON(1);
2690 }
2691}
2692
5042c507
MB		 2693/* Set the default values for the PHY TX Control Words. */
2694static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2695{
2696 u16 ctl = 0;
2697
2698 ctl |= B43_TXH_PHY_ENC_CCK;
2699 ctl |= B43_TXH_PHY_ANT01AUTO;
2700 ctl |= B43_TXH_PHY_TXPWR;
2701
2702 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2703 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2704 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2705}
2706
e4d6b795
MB		 2707/* Set the TX-Antenna for management frames sent by firmware. */
2708static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2709{
5042c507 2710 u16 ant;
e4d6b795
MB		 2711 u16 tmp;
2712
5042c507 2713 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2714
e4d6b795
MB		 2715 /* For ACK/CTS */
2716 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2717 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2718 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2719 /* For Probe Resposes */
2720 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2721 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2723}
2724
2725/* This is the opposite of b43_chip_init() */
2726static void b43_chip_exit(struct b43_wldev *dev)
2727{
fb11137a 2728 b43_phy_exit(dev);
e4d6b795
MB		 2729 b43_gpio_cleanup(dev);
2730 /* firmware is released later */
2731}
2732
2733/* Initialize the chip
2734 * http://bcm-specs.sipsolutions.net/ChipInit
2735 */
2736static int b43_chip_init(struct b43_wldev *dev)
2737{
2738 struct b43_phy *phy = &dev->phy;
ef1a628d 2739 int err;
1f7d87b0 2740 u32 value32, macctl;
e4d6b795
MB		 2741 u16 value16;
2742
1f7d87b0
MB		 2743 /* Initialize the MAC control */
2744 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2745 if (dev->phy.gmode)
2746 macctl |= B43_MACCTL_GMODE;
2747 macctl |= B43_MACCTL_INFRA;
2748 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2749
2750 err = b43_request_firmware(dev);
2751 if (err)
2752 goto out;
2753 err = b43_upload_microcode(dev);
2754 if (err)
2755 goto out; /* firmware is released later */
2756
2757 err = b43_gpio_init(dev);
2758 if (err)
2759 goto out; /* firmware is released later */
21954c36 2760
e4d6b795
MB		 2761 err = b43_upload_initvals(dev);
2762 if (err)
1a8d1227 2763 goto err_gpio_clean;
e4d6b795 2764
0b7dcd96
MB		 2765 /* Turn the Analog on and initialize the PHY. */
2766 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2767 err = b43_phy_init(dev);
2768 if (err)
ef1a628d 2769 goto err_gpio_clean;
e4d6b795 2770
ef1a628d
MB		 2771 /* Disable Interference Mitigation. */
2772 if (phy->ops->interf_mitigation)
2773 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2774
ef1a628d
MB		 2775 /* Select the antennae */
2776 if (phy->ops->set_rx_antenna)
2777 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2778 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2779
2780 if (phy->type == B43_PHYTYPE_B) {
2781 value16 = b43_read16(dev, 0x005E);
2782 value16 |= 0x0004;
2783 b43_write16(dev, 0x005E, value16);
2784 }
2785 b43_write32(dev, 0x0100, 0x01000000);
2786 if (dev->dev->id.revision < 5)
2787 b43_write32(dev, 0x010C, 0x01000000);
2788
2789 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2790 & ~B43_MACCTL_INFRA);
2791 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2792 | B43_MACCTL_INFRA);
e4d6b795 2793
e4d6b795
MB		 2794 /* Probe Response Timeout value */
2795 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2796 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2797
2798 /* Initially set the wireless operation mode. */
2799 b43_adjust_opmode(dev);
2800
2801 if (dev->dev->id.revision < 3) {
2802 b43_write16(dev, 0x060E, 0x0000);
2803 b43_write16(dev, 0x0610, 0x8000);
2804 b43_write16(dev, 0x0604, 0x0000);
2805 b43_write16(dev, 0x0606, 0x0200);
2806 } else {
2807 b43_write32(dev, 0x0188, 0x80000000);
2808 b43_write32(dev, 0x018C, 0x02000000);
2809 }
2810 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2811 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2812 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2813 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2814 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2815 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2816 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2817
2818 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2819 value32 |= 0x00100000;
2820 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2821
2822 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2823 dev->dev->bus->chipco.fast_pwrup_delay);
2824
2825 err = 0;
2826 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2827out:
e4d6b795
MB		 2828 return err;
2829
1a8d1227 2830err_gpio_clean:
e4d6b795 2831 b43_gpio_cleanup(dev);
21954c36 2832 return err;
e4d6b795
MB		 2833}
2834
e4d6b795
MB		 2835static void b43_periodic_every60sec(struct b43_wldev *dev)
2836{
ef1a628d 2837 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2838
ef1a628d
MB		 2839 if (ops->pwork_60sec)
2840 ops->pwork_60sec(dev);
18c8adeb
MB		 2841
2842 /* Force check the TX power emission now. */
2843 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2844}
2845
2846static void b43_periodic_every30sec(struct b43_wldev *dev)
2847{
2848 /* Update device statistics. */
2849 b43_calculate_link_quality(dev);
2850}
2851
2852static void b43_periodic_every15sec(struct b43_wldev *dev)
2853{
2854 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2855 u16 wdr;
2856
2857 if (dev->fw.opensource) {
2858 /* Check if the firmware is still alive.
2859 * It will reset the watchdog counter to 0 in its idle loop. */
2860 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2861 if (unlikely(wdr)) {
2862 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2863 b43_controller_restart(dev, "Firmware watchdog");
2864 return;
2865 } else {
2866 b43_shm_write16(dev, B43_SHM_SCRATCH,
2867 B43_WATCHDOG_REG, 1);
2868 }
2869 }
e4d6b795 2870
ef1a628d
MB		 2871 if (phy->ops->pwork_15sec)
2872 phy->ops->pwork_15sec(dev);
2873
00e0b8cb
SB		 2874 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2875 wmb();
e4d6b795
MB		 2876}
2877
e4d6b795
MB		 2878static void do_periodic_work(struct b43_wldev *dev)
2879{
2880 unsigned int state;
2881
2882 state = dev->periodic_state;
42bb4cd5 2883 if (state % 4 == 0)
e4d6b795 2884 b43_periodic_every60sec(dev);
42bb4cd5 2885 if (state % 2 == 0)
e4d6b795 2886 b43_periodic_every30sec(dev);
42bb4cd5 2887 b43_periodic_every15sec(dev);
e4d6b795
MB		 2888}
2889
05b64b36
MB		 2890/* Periodic work locking policy:
2891 * The whole periodic work handler is protected by
2892 * wl->mutex. If another lock is needed somewhere in the
2893 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2894 */
e4d6b795
MB		 2895static void b43_periodic_work_handler(struct work_struct *work)
2896{
05b64b36
MB		 2897 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2898 periodic_work.work);
2899 struct b43_wl *wl = dev->wl;
2900 unsigned long delay;
e4d6b795 2901
05b64b36 2902 mutex_lock(&wl->mutex);
e4d6b795
MB		 2903
2904 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2905 goto out;
2906 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2907 goto out_requeue;
2908
05b64b36 2909 do_periodic_work(dev);
e4d6b795 2910
e4d6b795 2911 dev->periodic_state++;
42bb4cd5 2912out_requeue:
e4d6b795
MB		 2913 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2914 delay = msecs_to_jiffies(50);
2915 else
82cd682d 2916 delay = round_jiffies_relative(HZ * 15);
05b64b36 2917 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2918out:
05b64b36 2919 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2920}
2921
2922static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2923{
2924 struct delayed_work *work = &dev->periodic_work;
2925
2926 dev->periodic_state = 0;
2927 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2928 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2929}
2930
f3dd3fcc 2931/* Check if communication with the device works correctly. */
e4d6b795
MB		 2932static int b43_validate_chipaccess(struct b43_wldev *dev)
2933{
f3dd3fcc 2934 u32 v, backup;
e4d6b795 2935
f3dd3fcc
MB		 2936 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2937
2938 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2939 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2940 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2941 goto error;
f3dd3fcc
MB		 2942 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2943 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2944 goto error;
2945
f3dd3fcc
MB		 2946 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2947
2948 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2949 /* The 32bit register shadows the two 16bit registers
2950 * with update sideeffects. Validate this. */
2951 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2952 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2953 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2954 goto error;
2955 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2956 goto error;
2957 }
2958 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2959
2960 v = b43_read32(dev, B43_MMIO_MACCTL);
2961 v |= B43_MACCTL_GMODE;
2962 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2963 goto error;
2964
2965 return 0;
f3dd3fcc 2966error:
e4d6b795
MB		 2967 b43err(dev->wl, "Failed to validate the chipaccess\n");
2968 return -ENODEV;
2969}
2970
2971static void b43_security_init(struct b43_wldev *dev)
2972{
2973 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2974 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2975 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2976 /* KTP is a word address, but we address SHM bytewise.
2977 * So multiply by two.
2978 */
2979 dev->ktp *= 2;
2980 if (dev->dev->id.revision >= 5) {
2981 /* Number of RCMTA address slots */
2982 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2983 }
2984 b43_clear_keys(dev);
2985}
2986
616de35d 2987#ifdef CONFIG_B43_HWRNG
99da185a 2988static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 2989{
2990 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2991 unsigned long flags;
2992
2993 /* Don't take wl->mutex here, as it could deadlock with
2994 * hwrng internal locking. It's not needed to take
2995 * wl->mutex here, anyway. */
2996
2997 spin_lock_irqsave(&wl->irq_lock, flags);
2998 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2999 spin_unlock_irqrestore(&wl->irq_lock, flags);
3000
3001 return (sizeof(u16));
3002}
616de35d 3003#endif /* CONFIG_B43_HWRNG */
e4d6b795 3004
b844eba2 3005static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3006{
616de35d 3007#ifdef CONFIG_B43_HWRNG
e4d6b795 3008 if (wl->rng_initialized)
b844eba2 3009 hwrng_unregister(&wl->rng);
616de35d 3010#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3011}
3012
3013static int b43_rng_init(struct b43_wl *wl)
3014{
616de35d 3015 int err = 0;
e4d6b795 3016
616de35d 3017#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3018 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3019 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3020 wl->rng.name = wl->rng_name;
3021 wl->rng.data_read = b43_rng_read;
3022 wl->rng.priv = (unsigned long)wl;
3023 wl->rng_initialized = 1;
3024 err = hwrng_register(&wl->rng);
3025 if (err) {
3026 wl->rng_initialized = 0;
3027 b43err(wl, "Failed to register the random "
3028 "number generator (%d)\n", err);
3029 }
616de35d 3030#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3031
3032 return err;
3033}
3034
40faacc4 3035static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 3036 struct sk_buff *skb)
e4d6b795
MB		 3037{
3038 struct b43_wl *wl = hw_to_b43_wl(hw);
3039 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 3040 unsigned long flags;
3041 int err;
e4d6b795 3042
5100d5ac
MB		 3043 if (unlikely(skb->len < 2 + 2 + 6)) {
3044 /* Too short, this can't be a valid frame. */
c9e8eae0 3045 goto drop_packet;
5100d5ac
MB		 3046 }
3047 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 3048 if (unlikely(!dev))
c9e8eae0 3049 goto drop_packet;
21a75d77
MB		 3050
3051 /* Transmissions on seperate queues can run concurrently. */
3052 read_lock_irqsave(&wl->tx_lock, flags);
3053
3054 err = -ENODEV;
3055 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3056 if (b43_using_pio_transfers(dev))
e039fa4a 3057 err = b43_pio_tx(dev, skb);
21a75d77 3058 else
e039fa4a 3059 err = b43_dma_tx(dev, skb);
21a75d77
MB		 3060 }
3061
3062 read_unlock_irqrestore(&wl->tx_lock, flags);
3063
e4d6b795 3064 if (unlikely(err))
c9e8eae0
MB		 3065 goto drop_packet;
3066 return NETDEV_TX_OK;
3067
3068drop_packet:
3069 /* We can not transmit this packet. Drop it. */
3070 dev_kfree_skb_any(skb);
e4d6b795
MB		 3071 return NETDEV_TX_OK;
3072}
3073
e6f5b934
MB		 3074/* Locking: wl->irq_lock */
3075static void b43_qos_params_upload(struct b43_wldev *dev,
3076 const struct ieee80211_tx_queue_params *p,
3077 u16 shm_offset)
3078{
3079 u16 params[B43_NR_QOSPARAMS];
0b57664c 3080 int bslots, tmp;
e6f5b934
MB		 3081 unsigned int i;
3082
0b57664c 3083 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3084
3085 memset(&params, 0, sizeof(params));
3086
3087 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3088 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3089 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3090 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3091 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3092 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3093 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3094
3095 for (i = 0; i < ARRAY_SIZE(params); i++) {
3096 if (i == B43_QOSPARAM_STATUS) {
3097 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3098 shm_offset + (i * 2));
3099 /* Mark the parameters as updated. */
3100 tmp |= 0x100;
3101 b43_shm_write16(dev, B43_SHM_SHARED,
3102 shm_offset + (i * 2),
3103 tmp);
3104 } else {
3105 b43_shm_write16(dev, B43_SHM_SHARED,
3106 shm_offset + (i * 2),
3107 params[i]);
3108 }
3109 }
3110}
3111
c40c1129
MB		 3112/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3113static const u16 b43_qos_shm_offsets[] = {
3114 /* [mac80211-queue-nr] = SHM_OFFSET, */
3115 [0] = B43_QOS_VOICE,
3116 [1] = B43_QOS_VIDEO,
3117 [2] = B43_QOS_BESTEFFORT,
3118 [3] = B43_QOS_BACKGROUND,
3119};
3120
5a5f3b40
MB		 3121/* Update all QOS parameters in hardware. */
3122static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3123{
3124 struct b43_wl *wl = dev->wl;
3125 struct b43_qos_params *params;
e6f5b934
MB		 3126 unsigned int i;
3127
c40c1129
MB		 3128 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3129 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3130
3131 b43_mac_suspend(dev);
e6f5b934
MB		 3132 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3133 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3134 b43_qos_params_upload(dev, &(params->p),
3135 b43_qos_shm_offsets[i]);
e6f5b934 3136 }
e6f5b934
MB		 3137 b43_mac_enable(dev);
3138}
3139
3140static void b43_qos_clear(struct b43_wl *wl)
3141{
3142 struct b43_qos_params *params;
3143 unsigned int i;
3144
c40c1129
MB		 3145 /* Initialize QoS parameters to sane defaults. */
3146
3147 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3148 ARRAY_SIZE(wl->qos_params));
3149
e6f5b934
MB		 3150 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3151 params = &(wl->qos_params[i]);
3152
c40c1129
MB		 3153 switch (b43_qos_shm_offsets[i]) {
3154 case B43_QOS_VOICE:
3155 params->p.txop = 0;
3156 params->p.aifs = 2;
3157 params->p.cw_min = 0x0001;
3158 params->p.cw_max = 0x0001;
3159 break;
3160 case B43_QOS_VIDEO:
3161 params->p.txop = 0;
3162 params->p.aifs = 2;
3163 params->p.cw_min = 0x0001;
3164 params->p.cw_max = 0x0001;
3165 break;
3166 case B43_QOS_BESTEFFORT:
3167 params->p.txop = 0;
3168 params->p.aifs = 3;
3169 params->p.cw_min = 0x0001;
3170 params->p.cw_max = 0x03FF;
3171 break;
3172 case B43_QOS_BACKGROUND:
3173 params->p.txop = 0;
3174 params->p.aifs = 7;
3175 params->p.cw_min = 0x0001;
3176 params->p.cw_max = 0x03FF;
3177 break;
3178 default:
3179 B43_WARN_ON(1);
3180 }
e6f5b934
MB		 3181 }
3182}
3183
3184/* Initialize the core's QOS capabilities */
3185static void b43_qos_init(struct b43_wldev *dev)
3186{
e6f5b934 3187 /* Upload the current QOS parameters. */
5a5f3b40 3188 b43_qos_upload_all(dev);
e6f5b934
MB		 3189
3190 /* Enable QOS support. */
3191 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3192 b43_write16(dev, B43_MMIO_IFSCTL,
3193 b43_read16(dev, B43_MMIO_IFSCTL)
3194 | B43_MMIO_IFSCTL_USE_EDCF);
3195}
3196
e100bb64 3197static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3198 const struct ieee80211_tx_queue_params *params)
e4d6b795 3199{
e6f5b934 3200 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3201 struct b43_wldev *dev;
e6f5b934 3202 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3203 int err = -ENODEV;
e6f5b934
MB		 3204
3205 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3206 /* Queue not available or don't support setting
3207 * params on this queue. Return success to not
3208 * confuse mac80211. */
3209 return 0;
3210 }
5a5f3b40
MB		 3211 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3212 ARRAY_SIZE(wl->qos_params));
e6f5b934 3213
5a5f3b40
MB		 3214 mutex_lock(&wl->mutex);
3215 dev = wl->current_dev;
3216 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3217 goto out_unlock;
e6f5b934 3218
5a5f3b40
MB		 3219 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3220 b43_mac_suspend(dev);
3221 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3222 b43_qos_shm_offsets[queue]);
3223 b43_mac_enable(dev);
3224 err = 0;
e6f5b934 3225
5a5f3b40
MB		 3226out_unlock:
3227 mutex_unlock(&wl->mutex);
3228
3229 return err;
e4d6b795
MB		 3230}
3231
40faacc4
MB		 3232static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3233 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3234{
3235 struct b43_wl *wl = hw_to_b43_wl(hw);
3236 struct b43_wldev *dev = wl->current_dev;
3237 unsigned long flags;
3238 int err = -ENODEV;
3239
3240 if (!dev)
3241 goto out;
3242 spin_lock_irqsave(&wl->irq_lock, flags);
3243 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3244 if (b43_using_pio_transfers(dev))
3245 b43_pio_get_tx_stats(dev, stats);
3246 else
3247 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3248 err = 0;
3249 }
3250 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3251out:
e4d6b795
MB		 3252 return err;
3253}
3254
40faacc4
MB		 3255static int b43_op_get_stats(struct ieee80211_hw *hw,
3256 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3257{
3258 struct b43_wl *wl = hw_to_b43_wl(hw);
3259 unsigned long flags;
3260
3261 spin_lock_irqsave(&wl->irq_lock, flags);
3262 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3263 spin_unlock_irqrestore(&wl->irq_lock, flags);
3264
3265 return 0;
3266}
3267
08e87a83
AF		 3268static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3269{
3270 struct b43_wl *wl = hw_to_b43_wl(hw);
3271 struct b43_wldev *dev;
3272 u64 tsf;
3273
3274 mutex_lock(&wl->mutex);
3275 spin_lock_irq(&wl->irq_lock);
3276 dev = wl->current_dev;
3277
3278 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3279 b43_tsf_read(dev, &tsf);
3280 else
3281 tsf = 0;
3282
3283 spin_unlock_irq(&wl->irq_lock);
3284 mutex_unlock(&wl->mutex);
3285
3286 return tsf;
3287}
3288
3289static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3290{
3291 struct b43_wl *wl = hw_to_b43_wl(hw);
3292 struct b43_wldev *dev;
3293
3294 mutex_lock(&wl->mutex);
3295 spin_lock_irq(&wl->irq_lock);
3296 dev = wl->current_dev;
3297
3298 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3299 b43_tsf_write(dev, tsf);
3300
3301 spin_unlock_irq(&wl->irq_lock);
3302 mutex_unlock(&wl->mutex);
3303}
3304
e4d6b795
MB		 3305static void b43_put_phy_into_reset(struct b43_wldev *dev)
3306{
3307 struct ssb_device *sdev = dev->dev;
3308 u32 tmslow;
3309
3310 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3311 tmslow &= ~B43_TMSLOW_GMODE;
3312 tmslow |= B43_TMSLOW_PHYRESET;
3313 tmslow |= SSB_TMSLOW_FGC;
3314 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3315 msleep(1);
3316
3317 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3318 tmslow &= ~SSB_TMSLOW_FGC;
3319 tmslow |= B43_TMSLOW_PHYRESET;
3320 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3321 msleep(1);
3322}
3323
99da185a 3324static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3325{
3326 switch (band) {
3327 case IEEE80211_BAND_5GHZ:
3328 return "5";
3329 case IEEE80211_BAND_2GHZ:
3330 return "2.4";
3331 default:
3332 break;
3333 }
3334 B43_WARN_ON(1);
3335 return "";
3336}
3337
e4d6b795 3338/* Expects wl->mutex locked */
bb1eeff1 3339static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3340{
bb1eeff1 3341 struct b43_wldev *up_dev = NULL;
e4d6b795 3342 struct b43_wldev *down_dev;
bb1eeff1 3343 struct b43_wldev *d;
e4d6b795 3344 int err;
922d8a0b 3345 bool uninitialized_var(gmode);
e4d6b795
MB		 3346 int prev_status;
3347
bb1eeff1
MB		 3348 /* Find a device and PHY which supports the band. */
3349 list_for_each_entry(d, &wl->devlist, list) {
3350 switch (chan->band) {
3351 case IEEE80211_BAND_5GHZ:
3352 if (d->phy.supports_5ghz) {
3353 up_dev = d;
3354 gmode = 0;
3355 }
3356 break;
3357 case IEEE80211_BAND_2GHZ:
3358 if (d->phy.supports_2ghz) {
3359 up_dev = d;
3360 gmode = 1;
3361 }
3362 break;
3363 default:
3364 B43_WARN_ON(1);
3365 return -EINVAL;
3366 }
3367 if (up_dev)
3368 break;
3369 }
3370 if (!up_dev) {
3371 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3372 band_to_string(chan->band));
3373 return -ENODEV;
e4d6b795
MB		 3374 }
3375 if ((up_dev == wl->current_dev) &&
3376 (!!wl->current_dev->phy.gmode == !!gmode)) {
3377 /* This device is already running. */
3378 return 0;
3379 }
bb1eeff1
MB		 3380 b43dbg(wl, "Switching to %s-GHz band\n",
3381 band_to_string(chan->band));
e4d6b795
MB		 3382 down_dev = wl->current_dev;
3383
3384 prev_status = b43_status(down_dev);
3385 /* Shutdown the currently running core. */
3386 if (prev_status >= B43_STAT_STARTED)
3387 b43_wireless_core_stop(down_dev);
3388 if (prev_status >= B43_STAT_INITIALIZED)
3389 b43_wireless_core_exit(down_dev);
3390
3391 if (down_dev != up_dev) {
3392 /* We switch to a different core, so we put PHY into
3393 * RESET on the old core. */
3394 b43_put_phy_into_reset(down_dev);
3395 }
3396
3397 /* Now start the new core. */
3398 up_dev->phy.gmode = gmode;
3399 if (prev_status >= B43_STAT_INITIALIZED) {
3400 err = b43_wireless_core_init(up_dev);
3401 if (err) {
3402 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3403 "selected %s-GHz band\n",
3404 band_to_string(chan->band));
e4d6b795
MB		 3405 goto init_failure;
3406 }
3407 }
3408 if (prev_status >= B43_STAT_STARTED) {
3409 err = b43_wireless_core_start(up_dev);
3410 if (err) {
3411 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3412 "selected %s-GHz band\n",
3413 band_to_string(chan->band));
e4d6b795
MB		 3414 b43_wireless_core_exit(up_dev);
3415 goto init_failure;
3416 }
3417 }
3418 B43_WARN_ON(b43_status(up_dev) != prev_status);
3419
3420 wl->current_dev = up_dev;
3421
3422 return 0;
bb1eeff1 3423init_failure:
e4d6b795
MB		 3424 /* Whoops, failed to init the new core. No core is operating now. */
3425 wl->current_dev = NULL;
3426 return err;
3427}
3428
9124b077
JB		 3429/* Write the short and long frame retry limit values. */
3430static void b43_set_retry_limits(struct b43_wldev *dev,
3431 unsigned int short_retry,
3432 unsigned int long_retry)
3433{
3434 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3435 * the chip-internal counter. */
3436 short_retry = min(short_retry, (unsigned int)0xF);
3437 long_retry = min(long_retry, (unsigned int)0xF);
3438
3439 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3440 short_retry);
3441 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3442 long_retry);
3443}
3444
e8975581 3445static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3446{
3447 struct b43_wl *wl = hw_to_b43_wl(hw);
3448 struct b43_wldev *dev;
3449 struct b43_phy *phy;
e8975581 3450 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3451 unsigned long flags;
9db1f6d7 3452 int antenna;
e4d6b795 3453 int err = 0;
e4d6b795 3454
e4d6b795
MB		 3455 mutex_lock(&wl->mutex);
3456
bb1eeff1
MB		 3457 /* Switch the band (if necessary). This might change the active core. */
3458 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3459 if (err)
3460 goto out_unlock_mutex;
3461 dev = wl->current_dev;
3462 phy = &dev->phy;
3463
d10d0e57
MB		 3464 b43_mac_suspend(dev);
3465
9124b077
JB		 3466 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3467 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3468 conf->long_frame_max_tx_count);
3469 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3470 if (!changed)
d10d0e57 3471 goto out_mac_enable;
e4d6b795
MB		 3472
3473 /* Switch to the requested channel.
3474 * The firmware takes care of races with the TX handler. */
8318d78a 3475 if (conf->channel->hw_value != phy->channel)
ef1a628d 3476 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3477
d42ce84a
JB		 3478 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3479
e4d6b795
MB		 3480 /* Adjust the desired TX power level. */
3481 if (conf->power_level != 0) {
18c8adeb
MB		 3482 spin_lock_irqsave(&wl->irq_lock, flags);
3483 if (conf->power_level != phy->desired_txpower) {
3484 phy->desired_txpower = conf->power_level;
3485 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3486 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3487 }
18c8adeb 3488 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3489 }
3490
3491 /* Antennas for RX and management frame TX. */
0f4ac38b 3492 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3493 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3494 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3495 if (phy->ops->set_rx_antenna)
3496 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3497
fd4973c5
LF		 3498 if (wl->radio_enabled != phy->radio_on) {
3499 if (wl->radio_enabled) {
19d337df 3500 b43_software_rfkill(dev, false);
fda9abcf
MB		 3501 b43info(dev->wl, "Radio turned on by software\n");
3502 if (!dev->radio_hw_enable) {
3503 b43info(dev->wl, "The hardware RF-kill button "
3504 "still turns the radio physically off. "
3505 "Press the button to turn it on.\n");
3506 }
3507 } else {
19d337df 3508 b43_software_rfkill(dev, true);
fda9abcf
MB		 3509 b43info(dev->wl, "Radio turned off by software\n");
3510 }
3511 }
3512
d10d0e57
MB		 3513out_mac_enable:
3514 b43_mac_enable(dev);
3515out_unlock_mutex:
e4d6b795
MB		 3516 mutex_unlock(&wl->mutex);
3517
3518 return err;
3519}
3520
881d948c 3521static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3522{
3523 struct ieee80211_supported_band *sband =
3524 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3525 struct ieee80211_rate *rate;
3526 int i;
3527 u16 basic, direct, offset, basic_offset, rateptr;
3528
3529 for (i = 0; i < sband->n_bitrates; i++) {
3530 rate = &sband->bitrates[i];
3531
3532 if (b43_is_cck_rate(rate->hw_value)) {
3533 direct = B43_SHM_SH_CCKDIRECT;
3534 basic = B43_SHM_SH_CCKBASIC;
3535 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3536 offset &= 0xF;
3537 } else {
3538 direct = B43_SHM_SH_OFDMDIRECT;
3539 basic = B43_SHM_SH_OFDMBASIC;
3540 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3541 offset &= 0xF;
3542 }
3543
3544 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3545
3546 if (b43_is_cck_rate(rate->hw_value)) {
3547 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3548 basic_offset &= 0xF;
3549 } else {
3550 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3551 basic_offset &= 0xF;
3552 }
3553
3554 /*
3555 * Get the pointer that we need to point to
3556 * from the direct map
3557 */
3558 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3559 direct + 2 * basic_offset);
3560 /* and write it to the basic map */
3561 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3562 rateptr);
3563 }
3564}
3565
3566static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3567 struct ieee80211_vif *vif,
3568 struct ieee80211_bss_conf *conf,
3569 u32 changed)
3570{
3571 struct b43_wl *wl = hw_to_b43_wl(hw);
3572 struct b43_wldev *dev;
2d0ddec5 3573 unsigned long flags;
c7ab5ef9
JB		 3574
3575 mutex_lock(&wl->mutex);
3576
3577 dev = wl->current_dev;
d10d0e57 3578 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3579 goto out_unlock_mutex;
2d0ddec5
JB		 3580
3581 B43_WARN_ON(wl->vif != vif);
3582
3f0d843b 3583 spin_lock_irqsave(&wl->irq_lock, flags);
2d0ddec5 3584 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3585 if (conf->bssid)
3586 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3587 else
3588 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3589 }
2d0ddec5 3590
3f0d843b
JB		 3591 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3592 if (changed & BSS_CHANGED_BEACON &&
3593 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3594 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3595 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3596 b43_update_templates(wl);
3597
3598 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3599 b43_write_mac_bssid_templates(dev);
2d0ddec5 3600 }
3f0d843b 3601 spin_unlock_irqrestore(&wl->irq_lock, flags);
2d0ddec5 3602
c7ab5ef9
JB		 3603 b43_mac_suspend(dev);
3604
57c4d7b4
JB		 3605 /* Update templates for AP/mesh mode. */
3606 if (changed & BSS_CHANGED_BEACON_INT &&
3607 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3608 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3609 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3610 b43_set_beacon_int(dev, conf->beacon_int);
3611
c7ab5ef9
JB		 3612 if (changed & BSS_CHANGED_BASIC_RATES)
3613 b43_update_basic_rates(dev, conf->basic_rates);
3614
3615 if (changed & BSS_CHANGED_ERP_SLOT) {
3616 if (conf->use_short_slot)
3617 b43_short_slot_timing_enable(dev);
3618 else
3619 b43_short_slot_timing_disable(dev);
3620 }
3621
3622 b43_mac_enable(dev);
d10d0e57 3623out_unlock_mutex:
c7ab5ef9 3624 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3625}
3626
40faacc4 3627static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3628 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3629 struct ieee80211_key_conf *key)
e4d6b795
MB		 3630{
3631 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3632 struct b43_wldev *dev;
e4d6b795
MB		 3633 u8 algorithm;
3634 u8 index;
c6dfc9a8 3635 int err;
060210f9 3636 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3637
3638 if (modparam_nohwcrypt)
3639 return -ENOSPC; /* User disabled HW-crypto */
3640
c6dfc9a8 3641 mutex_lock(&wl->mutex);
e808e586
MB		 3642 spin_lock_irq(&wl->irq_lock);
3643 write_lock(&wl->tx_lock);
3644 /* Why do we need all this locking here?
3645 * mutex -> Every config operation must take it.
3646 * irq_lock -> We modify the dev->key array, which is accessed
3647 * in the IRQ handlers.
3648 * tx_lock -> We modify the dev->key array, which is accessed
3649 * in the TX handler.
3650 */
c6dfc9a8
MB		 3651
3652 dev = wl->current_dev;
3653 err = -ENODEV;
3654 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3655 goto out_unlock;
3656
403a3a13 3657 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3658 /* We don't have firmware for the crypto engine.
3659 * Must use software-crypto. */
3660 err = -EOPNOTSUPP;
3661 goto out_unlock;
3662 }
3663
c6dfc9a8 3664 err = -EINVAL;
e4d6b795 3665 switch (key->alg) {
e4d6b795 3666 case ALG_WEP:
e31a16d6 3667 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3668 algorithm = B43_SEC_ALGO_WEP40;
3669 else
3670 algorithm = B43_SEC_ALGO_WEP104;
3671 break;
3672 case ALG_TKIP:
3673 algorithm = B43_SEC_ALGO_TKIP;
3674 break;
3675 case ALG_CCMP:
3676 algorithm = B43_SEC_ALGO_AES;
3677 break;
3678 default:
3679 B43_WARN_ON(1);
c6dfc9a8 3680 goto out_unlock;
e4d6b795 3681 }
e4d6b795
MB		 3682 index = (u8) (key->keyidx);
3683 if (index > 3)
e4d6b795 3684 goto out_unlock;
e4d6b795
MB		 3685
3686 switch (cmd) {
3687 case SET_KEY:
3688 if (algorithm == B43_SEC_ALGO_TKIP) {
3689 /* FIXME: No TKIP hardware encryption for now. */
3690 err = -EOPNOTSUPP;
3691 goto out_unlock;
3692 }
3693
e808e586 3694 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3695 if (WARN_ON(!sta)) {
3696 err = -EOPNOTSUPP;
3697 goto out_unlock;
3698 }
e808e586 3699 /* Pairwise key with an assigned MAC address. */
e4d6b795 3700 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3701 key->key, key->keylen,
3702 sta->addr, key);
e808e586
MB		 3703 } else {
3704 /* Group key */
3705 err = b43_key_write(dev, index, algorithm,
3706 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3707 }
3708 if (err)
3709 goto out_unlock;
3710
3711 if (algorithm == B43_SEC_ALGO_WEP40 ||
3712 algorithm == B43_SEC_ALGO_WEP104) {
3713 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3714 } else {
3715 b43_hf_write(dev,
3716 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3717 }
3718 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3719 break;
3720 case DISABLE_KEY: {
3721 err = b43_key_clear(dev, key->hw_key_idx);
3722 if (err)
3723 goto out_unlock;
3724 break;
3725 }
3726 default:
3727 B43_WARN_ON(1);
3728 }
9cf7f247 3729
e4d6b795 3730out_unlock:
e4d6b795
MB		 3731 if (!err) {
3732 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3733 "mac: %pM\n",
e4d6b795 3734 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3735 sta ? sta->addr : bcast_addr);
9cf7f247 3736 b43_dump_keymemory(dev);
e4d6b795 3737 }
e808e586
MB		 3738 write_unlock(&wl->tx_lock);
3739 spin_unlock_irq(&wl->irq_lock);
9cf7f247
MB		 3740 mutex_unlock(&wl->mutex);
3741
e4d6b795
MB		 3742 return err;
3743}
3744
40faacc4
MB		 3745static void b43_op_configure_filter(struct ieee80211_hw *hw,
3746 unsigned int changed, unsigned int *fflags,
3747 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3748{
3749 struct b43_wl *wl = hw_to_b43_wl(hw);
3750 struct b43_wldev *dev = wl->current_dev;
3751 unsigned long flags;
3752
4150c572
JB		 3753 if (!dev) {
3754 *fflags = 0;
e4d6b795 3755 return;
e4d6b795 3756 }
4150c572
JB		 3757
3758 spin_lock_irqsave(&wl->irq_lock, flags);
3759 *fflags &= FIF_PROMISC_IN_BSS |
3760 FIF_ALLMULTI |
3761 FIF_FCSFAIL |
3762 FIF_PLCPFAIL |
3763 FIF_CONTROL |
3764 FIF_OTHER_BSS |
3765 FIF_BCN_PRBRESP_PROMISC;
3766
3767 changed &= FIF_PROMISC_IN_BSS |
3768 FIF_ALLMULTI |
3769 FIF_FCSFAIL |
3770 FIF_PLCPFAIL |
3771 FIF_CONTROL |
3772 FIF_OTHER_BSS |
3773 FIF_BCN_PRBRESP_PROMISC;
3774
3775 wl->filter_flags = *fflags;
3776
3777 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3778 b43_adjust_opmode(dev);
e4d6b795
MB		 3779 spin_unlock_irqrestore(&wl->irq_lock, flags);
3780}
3781
e4d6b795
MB		 3782/* Locking: wl->mutex */
3783static void b43_wireless_core_stop(struct b43_wldev *dev)
3784{
3785 struct b43_wl *wl = dev->wl;
3786 unsigned long flags;
3787
3788 if (b43_status(dev) < B43_STAT_STARTED)
3789 return;
a19d12d7
SB		 3790
3791 /* Disable and sync interrupts. We must do this before than
3792 * setting the status to INITIALIZED, as the interrupt handler
3793 * won't care about IRQs then. */
3794 spin_lock_irqsave(&wl->irq_lock, flags);
13790728 3795 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
a19d12d7
SB		 3796 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3797 spin_unlock_irqrestore(&wl->irq_lock, flags);
3798 b43_synchronize_irq(dev);
3799
21a75d77 3800 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3801 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3802 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3803
5100d5ac 3804 b43_pio_stop(dev);
e4d6b795
MB		 3805 mutex_unlock(&wl->mutex);
3806 /* Must unlock as it would otherwise deadlock. No races here.
3807 * Cancel the possibly running self-rearming periodic work. */
3808 cancel_delayed_work_sync(&dev->periodic_work);
3809 mutex_lock(&wl->mutex);
3810
e4d6b795
MB		 3811 b43_mac_suspend(dev);
3812 free_irq(dev->dev->irq, dev);
3813 b43dbg(wl, "Wireless interface stopped\n");
3814}
3815
3816/* Locking: wl->mutex */
3817static int b43_wireless_core_start(struct b43_wldev *dev)
3818{
3819 int err;
3820
3821 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3822
3823 drain_txstatus_queue(dev);
3824 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3825 IRQF_SHARED, KBUILD_MODNAME, dev);
3826 if (err) {
3827 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3828 goto out;
3829 }
3830
3831 /* We are ready to run. */
3832 b43_set_status(dev, B43_STAT_STARTED);
3833
3834 /* Start data flow (TX/RX). */
3835 b43_mac_enable(dev);
13790728 3836 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3837
3838 /* Start maintainance work */
3839 b43_periodic_tasks_setup(dev);
3840
3841 b43dbg(dev->wl, "Wireless interface started\n");
3842 out:
3843 return err;
3844}
3845
3846/* Get PHY and RADIO versioning numbers */
3847static int b43_phy_versioning(struct b43_wldev *dev)
3848{
3849 struct b43_phy *phy = &dev->phy;
3850 u32 tmp;
3851 u8 analog_type;
3852 u8 phy_type;
3853 u8 phy_rev;
3854 u16 radio_manuf;
3855 u16 radio_ver;
3856 u16 radio_rev;
3857 int unsupported = 0;
3858
3859 /* Get PHY versioning */
3860 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3861 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3862 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3863 phy_rev = (tmp & B43_PHYVER_VERSION);
3864 switch (phy_type) {
3865 case B43_PHYTYPE_A:
3866 if (phy_rev >= 4)
3867 unsupported = 1;
3868 break;
3869 case B43_PHYTYPE_B:
3870 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3871 && phy_rev != 7)
3872 unsupported = 1;
3873 break;
3874 case B43_PHYTYPE_G:
013978b6 3875 if (phy_rev > 9)
e4d6b795
MB		 3876 unsupported = 1;
3877 break;
d5c71e46
MB		 3878#ifdef CONFIG_B43_NPHY
3879 case B43_PHYTYPE_N:
bb519bee 3880 if (phy_rev > 4)
d5c71e46
MB		 3881 unsupported = 1;
3882 break;
6b1c7c67
MB		 3883#endif
3884#ifdef CONFIG_B43_PHY_LP
3885 case B43_PHYTYPE_LP:
3886 if (phy_rev > 1)
3887 unsupported = 1;
3888 break;
d5c71e46 3889#endif
e4d6b795
MB		 3890 default:
3891 unsupported = 1;
3892 };
3893 if (unsupported) {
3894 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3895 "(Analog %u, Type %u, Revision %u)\n",
3896 analog_type, phy_type, phy_rev);
3897 return -EOPNOTSUPP;
3898 }
3899 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3900 analog_type, phy_type, phy_rev);
3901
3902 /* Get RADIO versioning */
3903 if (dev->dev->bus->chip_id == 0x4317) {
3904 if (dev->dev->bus->chip_rev == 0)
3905 tmp = 0x3205017F;
3906 else if (dev->dev->bus->chip_rev == 1)
3907 tmp = 0x4205017F;
3908 else
3909 tmp = 0x5205017F;
3910 } else {
3911 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3912 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3913 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3914 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3915 }
3916 radio_manuf = (tmp & 0x00000FFF);
3917 radio_ver = (tmp & 0x0FFFF000) >> 12;
3918 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3919 if (radio_manuf != 0x17F /* Broadcom */)
3920 unsupported = 1;
e4d6b795
MB		 3921 switch (phy_type) {
3922 case B43_PHYTYPE_A:
3923 if (radio_ver != 0x2060)
3924 unsupported = 1;
3925 if (radio_rev != 1)
3926 unsupported = 1;
3927 if (radio_manuf != 0x17F)
3928 unsupported = 1;
3929 break;
3930 case B43_PHYTYPE_B:
3931 if ((radio_ver & 0xFFF0) != 0x2050)
3932 unsupported = 1;
3933 break;
3934 case B43_PHYTYPE_G:
3935 if (radio_ver != 0x2050)
3936 unsupported = 1;
3937 break;
96c755a3 3938 case B43_PHYTYPE_N:
bb519bee 3939 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3940 unsupported = 1;
3941 break;
6b1c7c67
MB		 3942 case B43_PHYTYPE_LP:
3943 if (radio_ver != 0x2062)
3944 unsupported = 1;
3945 break;
e4d6b795
MB		 3946 default:
3947 B43_WARN_ON(1);
3948 }
3949 if (unsupported) {
3950 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3951 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3952 radio_manuf, radio_ver, radio_rev);
3953 return -EOPNOTSUPP;
3954 }
3955 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3956 radio_manuf, radio_ver, radio_rev);
3957
3958 phy->radio_manuf = radio_manuf;
3959 phy->radio_ver = radio_ver;
3960 phy->radio_rev = radio_rev;
3961
3962 phy->analog = analog_type;
3963 phy->type = phy_type;
3964 phy->rev = phy_rev;
3965
3966 return 0;
3967}
3968
3969static void setup_struct_phy_for_init(struct b43_wldev *dev,
3970 struct b43_phy *phy)
3971{
e4d6b795 3972 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3973 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3974 /* PHY TX errors counter. */
3975 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 3976
3977#if B43_DEBUG
3978 phy->phy_locked = 0;
3979 phy->radio_locked = 0;
3980#endif
e4d6b795
MB		 3981}
3982
3983static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3984{
aa6c7ae2
MB		 3985 dev->dfq_valid = 0;
3986
6a724d68
MB		 3987 /* Assume the radio is enabled. If it's not enabled, the state will
3988 * immediately get fixed on the first periodic work run. */
3989 dev->radio_hw_enable = 1;
e4d6b795
MB		 3990
3991 /* Stats */
3992 memset(&dev->stats, 0, sizeof(dev->stats));
3993
3994 setup_struct_phy_for_init(dev, &dev->phy);
3995
3996 /* IRQ related flags */
3997 dev->irq_reason = 0;
3998 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 3999 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4000 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4001 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4002
4003 dev->mac_suspended = 1;
4004
4005 /* Noise calculation context */
4006 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4007}
4008
4009static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4010{
4011 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4012 u64 hf;
e4d6b795 4013
1855ba78
MB		 4014 if (!modparam_btcoex)
4015 return;
95de2841 4016 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4017 return;
4018 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4019 return;
4020
4021 hf = b43_hf_read(dev);
95de2841 4022 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4023 hf |= B43_HF_BTCOEXALT;
4024 else
4025 hf |= B43_HF_BTCOEX;
4026 b43_hf_write(dev, hf);
e4d6b795
MB		 4027}
4028
4029static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4030{
4031 if (!modparam_btcoex)
4032 return;
4033 //TODO
e4d6b795
MB		 4034}
4035
4036static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4037{
4038#ifdef CONFIG_SSB_DRIVER_PCICORE
4039 struct ssb_bus *bus = dev->dev->bus;
4040 u32 tmp;
4041
4042 if (bus->pcicore.dev &&
4043 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4044 bus->pcicore.dev->id.revision <= 5) {
4045 /* IMCFGLO timeouts workaround. */
4046 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4047 tmp &= ~SSB_IMCFGLO_REQTO;
4048 tmp &= ~SSB_IMCFGLO_SERTO;
4049 switch (bus->bustype) {
4050 case SSB_BUSTYPE_PCI:
4051 case SSB_BUSTYPE_PCMCIA:
4052 tmp |= 0x32;
4053 break;
4054 case SSB_BUSTYPE_SSB:
4055 tmp |= 0x53;
4056 break;
4057 }
4058 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4059 }
4060#endif /* CONFIG_SSB_DRIVER_PCICORE */
4061}
4062
d59f720d
MB		 4063static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4064{
4065 u16 pu_delay;
4066
4067 /* The time value is in microseconds. */
4068 if (dev->phy.type == B43_PHYTYPE_A)
4069 pu_delay = 3700;
4070 else
4071 pu_delay = 1050;
05c914fe 4072 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4073 pu_delay = 500;
4074 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4075 pu_delay = max(pu_delay, (u16)2400);
4076
4077 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4078}
4079
4080/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4081static void b43_set_pretbtt(struct b43_wldev *dev)
4082{
4083 u16 pretbtt;
4084
4085 /* The time value is in microseconds. */
05c914fe 4086 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4087 pretbtt = 2;
4088 } else {
4089 if (dev->phy.type == B43_PHYTYPE_A)
4090 pretbtt = 120;
4091 else
4092 pretbtt = 250;
4093 }
4094 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4095 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4096}
4097
e4d6b795
MB		 4098/* Shutdown a wireless core */
4099/* Locking: wl->mutex */
4100static void b43_wireless_core_exit(struct b43_wldev *dev)
4101{
1f7d87b0 4102 u32 macctl;
e4d6b795
MB		 4103
4104 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4105 if (b43_status(dev) != B43_STAT_INITIALIZED)
4106 return;
4107 b43_set_status(dev, B43_STAT_UNINIT);
4108
1f7d87b0
MB		 4109 /* Stop the microcode PSM. */
4110 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4111 macctl &= ~B43_MACCTL_PSM_RUN;
4112 macctl |= B43_MACCTL_PSM_JMP0;
4113 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4114
3506e0c4
RW		 4115 if (!dev->suspend_in_progress) {
4116 b43_leds_exit(dev);
b844eba2 4117 b43_rng_exit(dev->wl);
3506e0c4 4118 }
e4d6b795 4119 b43_dma_free(dev);
5100d5ac 4120 b43_pio_free(dev);
e4d6b795 4121 b43_chip_exit(dev);
cb24f57f 4122 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4123 if (dev->wl->current_beacon) {
4124 dev_kfree_skb_any(dev->wl->current_beacon);
4125 dev->wl->current_beacon = NULL;
4126 }
4127
e4d6b795
MB		 4128 ssb_device_disable(dev->dev, 0);
4129 ssb_bus_may_powerdown(dev->dev->bus);
4130}
4131
4132/* Initialize a wireless core */
4133static int b43_wireless_core_init(struct b43_wldev *dev)
4134{
4135 struct b43_wl *wl = dev->wl;
4136 struct ssb_bus *bus = dev->dev->bus;
4137 struct ssb_sprom *sprom = &bus->sprom;
4138 struct b43_phy *phy = &dev->phy;
4139 int err;
a259d6a4
MB		 4140 u64 hf;
4141 u32 tmp;
e4d6b795
MB		 4142
4143 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4144
4145 err = ssb_bus_powerup(bus, 0);
4146 if (err)
4147 goto out;
4148 if (!ssb_device_is_enabled(dev->dev)) {
4149 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4150 b43_wireless_core_reset(dev, tmp);
4151 }
4152
fb11137a 4153 /* Reset all data structures. */
e4d6b795 4154 setup_struct_wldev_for_init(dev);
fb11137a 4155 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4156
4157 /* Enable IRQ routing to this device. */
4158 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4159
4160 b43_imcfglo_timeouts_workaround(dev);
4161 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4162 if (phy->ops->prepare_hardware) {
4163 err = phy->ops->prepare_hardware(dev);
ef1a628d 4164 if (err)
fb11137a 4165 goto err_busdown;
ef1a628d 4166 }
e4d6b795
MB		 4167 err = b43_chip_init(dev);
4168 if (err)
fb11137a 4169 goto err_busdown;
e4d6b795
MB		 4170 b43_shm_write16(dev, B43_SHM_SHARED,
4171 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4172 hf = b43_hf_read(dev);
4173 if (phy->type == B43_PHYTYPE_G) {
4174 hf |= B43_HF_SYMW;
4175 if (phy->rev == 1)
4176 hf |= B43_HF_GDCW;
95de2841 4177 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4178 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4179 }
4180 if (phy->radio_ver == 0x2050) {
4181 if (phy->radio_rev == 6)
4182 hf |= B43_HF_4318TSSI;
4183 if (phy->radio_rev < 6)
4184 hf |= B43_HF_VCORECALC;
e4d6b795 4185 }
1cc8f476
MB		 4186 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4187 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4188#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4189 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4190 (bus->pcicore.dev->id.revision <= 10))
4191 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4192#endif
25d3ef59 4193 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4194 b43_hf_write(dev, hf);
4195
74cfdba7
MB		 4196 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4197 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4198 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4199 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4200
4201 /* Disable sending probe responses from firmware.
4202 * Setting the MaxTime to one usec will always trigger
4203 * a timeout, so we never send any probe resp.
4204 * A timeout of zero is infinite. */
4205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4206
4207 b43_rate_memory_init(dev);
5042c507 4208 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4209
4210 /* Minimum Contention Window */
4211 if (phy->type == B43_PHYTYPE_B) {
4212 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4213 } else {
4214 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4215 }
4216 /* Maximum Contention Window */
4217 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4218
5100d5ac
MB		 4219 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4220 dev->__using_pio_transfers = 1;
4221 err = b43_pio_init(dev);
4222 } else {
4223 dev->__using_pio_transfers = 0;
4224 err = b43_dma_init(dev);
4225 }
e4d6b795
MB		 4226 if (err)
4227 goto err_chip_exit;
03b29773 4228 b43_qos_init(dev);
d59f720d 4229 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4230 b43_bluetooth_coext_enable(dev);
4231
1cc8f476 4232 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4233 b43_upload_card_macaddress(dev);
e4d6b795 4234 b43_security_init(dev);
3506e0c4
RW		 4235 if (!dev->suspend_in_progress)
4236 b43_rng_init(wl);
e4d6b795
MB		 4237
4238 b43_set_status(dev, B43_STAT_INITIALIZED);
4239
3506e0c4
RW		 4240 if (!dev->suspend_in_progress)
4241 b43_leds_init(dev);
1a8d1227 4242out:
e4d6b795
MB		 4243 return err;
4244
ef1a628d 4245err_chip_exit:
e4d6b795 4246 b43_chip_exit(dev);
ef1a628d 4247err_busdown:
e4d6b795
MB		 4248 ssb_bus_may_powerdown(bus);
4249 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4250 return err;
4251}
4252
40faacc4
MB		 4253static int b43_op_add_interface(struct ieee80211_hw *hw,
4254 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4255{
4256 struct b43_wl *wl = hw_to_b43_wl(hw);
4257 struct b43_wldev *dev;
4258 unsigned long flags;
4259 int err = -EOPNOTSUPP;
4150c572
JB		 4260
4261 /* TODO: allow WDS/AP devices to coexist */
4262
05c914fe
JB		 4263 if (conf->type != NL80211_IFTYPE_AP &&
4264 conf->type != NL80211_IFTYPE_MESH_POINT &&
4265 conf->type != NL80211_IFTYPE_STATION &&
4266 conf->type != NL80211_IFTYPE_WDS &&
4267 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4268 return -EOPNOTSUPP;
e4d6b795
MB		 4269
4270 mutex_lock(&wl->mutex);
4150c572 4271 if (wl->operating)
e4d6b795
MB		 4272 goto out_mutex_unlock;
4273
4274 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4275
4276 dev = wl->current_dev;
4150c572 4277 wl->operating = 1;
32bfd35d 4278 wl->vif = conf->vif;
4150c572
JB		 4279 wl->if_type = conf->type;
4280 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4281
4282 spin_lock_irqsave(&wl->irq_lock, flags);
4283 b43_adjust_opmode(dev);
d59f720d
MB		 4284 b43_set_pretbtt(dev);
4285 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4286 b43_upload_card_macaddress(dev);
4287 spin_unlock_irqrestore(&wl->irq_lock, flags);
4288
4289 err = 0;
4290 out_mutex_unlock:
4291 mutex_unlock(&wl->mutex);
4292
4293 return err;
4294}
4295
40faacc4
MB		 4296static void b43_op_remove_interface(struct ieee80211_hw *hw,
4297 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4298{
4299 struct b43_wl *wl = hw_to_b43_wl(hw);
4300 struct b43_wldev *dev = wl->current_dev;
4301 unsigned long flags;
4302
4303 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4304
4305 mutex_lock(&wl->mutex);
4306
4307 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4308 B43_WARN_ON(wl->vif != conf->vif);
4309 wl->vif = NULL;
4150c572
JB		 4310
4311 wl->operating = 0;
4312
4313 spin_lock_irqsave(&wl->irq_lock, flags);
4314 b43_adjust_opmode(dev);
4315 memset(wl->mac_addr, 0, ETH_ALEN);
4316 b43_upload_card_macaddress(dev);
4317 spin_unlock_irqrestore(&wl->irq_lock, flags);
4318
4319 mutex_unlock(&wl->mutex);
4320}
4321
40faacc4 4322static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4323{
4324 struct b43_wl *wl = hw_to_b43_wl(hw);
4325 struct b43_wldev *dev = wl->current_dev;
4326 int did_init = 0;
923403b8 4327 int err = 0;
4150c572 4328
7be1bb6b
MB		 4329 /* Kill all old instance specific information to make sure
4330 * the card won't use it in the short timeframe between start
4331 * and mac80211 reconfiguring it. */
4332 memset(wl->bssid, 0, ETH_ALEN);
4333 memset(wl->mac_addr, 0, ETH_ALEN);
4334 wl->filter_flags = 0;
4335 wl->radiotap_enabled = 0;
e6f5b934 4336 b43_qos_clear(wl);
6b4bec01
MB		 4337 wl->beacon0_uploaded = 0;
4338 wl->beacon1_uploaded = 0;
4339 wl->beacon_templates_virgin = 1;
fd4973c5 4340 wl->radio_enabled = 1;
7be1bb6b 4341
4150c572
JB		 4342 mutex_lock(&wl->mutex);
4343
e4d6b795
MB		 4344 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4345 err = b43_wireless_core_init(dev);
f41f3f37 4346 if (err)
e4d6b795
MB		 4347 goto out_mutex_unlock;
4348 did_init = 1;
4349 }
4150c572 4350
e4d6b795
MB		 4351 if (b43_status(dev) < B43_STAT_STARTED) {
4352 err = b43_wireless_core_start(dev);
4353 if (err) {
4354 if (did_init)
4355 b43_wireless_core_exit(dev);
4356 goto out_mutex_unlock;
4357 }
4358 }
4359
f41f3f37
JB		 4360 /* XXX: only do if device doesn't support rfkill irq */
4361 wiphy_rfkill_start_polling(hw->wiphy);
4362
4150c572 4363 out_mutex_unlock:
e4d6b795
MB		 4364 mutex_unlock(&wl->mutex);
4365
4366 return err;
4367}
4368
40faacc4 4369static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4370{
4371 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4372 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4373
a82d9922 4374 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4375
e4d6b795 4376 mutex_lock(&wl->mutex);
4150c572
JB		 4377 if (b43_status(dev) >= B43_STAT_STARTED)
4378 b43_wireless_core_stop(dev);
4379 b43_wireless_core_exit(dev);
fd4973c5 4380 wl->radio_enabled = 0;
e4d6b795 4381 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4382
4383 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4384}
4385
17741cdc
JB		 4386static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4387 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4388{
4389 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4390 unsigned long flags;
e66fee6a 4391
d4df6f1a 4392 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4393 b43_update_templates(wl);
d4df6f1a 4394 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4395
4396 return 0;
4397}
4398
38968d09
JB		 4399static void b43_op_sta_notify(struct ieee80211_hw *hw,
4400 struct ieee80211_vif *vif,
4401 enum sta_notify_cmd notify_cmd,
17741cdc 4402 struct ieee80211_sta *sta)
38968d09
JB		 4403{
4404 struct b43_wl *wl = hw_to_b43_wl(hw);
4405
4406 B43_WARN_ON(!vif || wl->vif != vif);
4407}
4408
25d3ef59
MB		 4409static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4410{
4411 struct b43_wl *wl = hw_to_b43_wl(hw);
4412 struct b43_wldev *dev;
4413
4414 mutex_lock(&wl->mutex);
4415 dev = wl->current_dev;
4416 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4417 /* Disable CFP update during scan on other channels. */
4418 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4419 }
4420 mutex_unlock(&wl->mutex);
4421}
4422
4423static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4424{
4425 struct b43_wl *wl = hw_to_b43_wl(hw);
4426 struct b43_wldev *dev;
4427
4428 mutex_lock(&wl->mutex);
4429 dev = wl->current_dev;
4430 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4431 /* Re-enable CFP update. */
4432 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4433 }
4434 mutex_unlock(&wl->mutex);
4435}
4436
e4d6b795 4437static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4438 .tx = b43_op_tx,
4439 .conf_tx = b43_op_conf_tx,
4440 .add_interface = b43_op_add_interface,
4441 .remove_interface = b43_op_remove_interface,
4442 .config = b43_op_config,
c7ab5ef9 4443 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4444 .configure_filter = b43_op_configure_filter,
4445 .set_key = b43_op_set_key,
4446 .get_stats = b43_op_get_stats,
4447 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4448 .get_tsf = b43_op_get_tsf,
4449 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4450 .start = b43_op_start,
4451 .stop = b43_op_stop,
e66fee6a 4452 .set_tim = b43_op_beacon_set_tim,
38968d09 4453 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4454 .sw_scan_start = b43_op_sw_scan_start_notifier,
4455 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4456 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4457};
4458
4459/* Hard-reset the chip. Do not call this directly.
4460 * Use b43_controller_restart()
4461 */
4462static void b43_chip_reset(struct work_struct *work)
4463{
4464 struct b43_wldev *dev =
4465 container_of(work, struct b43_wldev, restart_work);
4466 struct b43_wl *wl = dev->wl;
4467 int err = 0;
4468 int prev_status;
4469
4470 mutex_lock(&wl->mutex);
4471
4472 prev_status = b43_status(dev);
4473 /* Bring the device down... */
4474 if (prev_status >= B43_STAT_STARTED)
4475 b43_wireless_core_stop(dev);
4476 if (prev_status >= B43_STAT_INITIALIZED)
4477 b43_wireless_core_exit(dev);
4478
4479 /* ...and up again. */
4480 if (prev_status >= B43_STAT_INITIALIZED) {
4481 err = b43_wireless_core_init(dev);
4482 if (err)
4483 goto out;
4484 }
4485 if (prev_status >= B43_STAT_STARTED) {
4486 err = b43_wireless_core_start(dev);
4487 if (err) {
4488 b43_wireless_core_exit(dev);
4489 goto out;
4490 }
4491 }
3bf0a32e
MB		 4492out:
4493 if (err)
4494 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4495 mutex_unlock(&wl->mutex);
4496 if (err)
4497 b43err(wl, "Controller restart FAILED\n");
4498 else
4499 b43info(wl, "Controller restarted\n");
4500}
4501
bb1eeff1 4502static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4503 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4504{
4505 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4506
bb1eeff1
MB		 4507 if (have_2ghz_phy)
4508 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4509 if (dev->phy.type == B43_PHYTYPE_N) {
4510 if (have_5ghz_phy)
4511 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4512 } else {
4513 if (have_5ghz_phy)
4514 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4515 }
96c755a3 4516
bb1eeff1
MB		 4517 dev->phy.supports_2ghz = have_2ghz_phy;
4518 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4519
4520 return 0;
4521}
4522
4523static void b43_wireless_core_detach(struct b43_wldev *dev)
4524{
4525 /* We release firmware that late to not be required to re-request
4526 * is all the time when we reinit the core. */
4527 b43_release_firmware(dev);
fb11137a 4528 b43_phy_free(dev);
e4d6b795
MB		 4529}
4530
4531static int b43_wireless_core_attach(struct b43_wldev *dev)
4532{
4533 struct b43_wl *wl = dev->wl;
4534 struct ssb_bus *bus = dev->dev->bus;
4535 struct pci_dev *pdev = bus->host_pci;
4536 int err;
96c755a3 4537 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4538 u32 tmp;
4539
4540 /* Do NOT do any device initialization here.
4541 * Do it in wireless_core_init() instead.
4542 * This function is for gathering basic information about the HW, only.
4543 * Also some structs may be set up here. But most likely you want to have
4544 * that in core_init(), too.
4545 */
4546
4547 err = ssb_bus_powerup(bus, 0);
4548 if (err) {
4549 b43err(wl, "Bus powerup failed\n");
4550 goto out;
4551 }
4552 /* Get the PHY type. */
4553 if (dev->dev->id.revision >= 5) {
4554 u32 tmshigh;
4555
4556 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4557 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4558 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4559 } else
96c755a3 4560 B43_WARN_ON(1);
e4d6b795 4561
96c755a3 4562 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4563 dev->phy.radio_on = 1;
e4d6b795
MB		 4564 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4565 b43_wireless_core_reset(dev, tmp);
4566
4567 err = b43_phy_versioning(dev);
4568 if (err)
21954c36 4569 goto err_powerdown;
e4d6b795
MB		 4570 /* Check if this device supports multiband. */
4571 if (!pdev ||
4572 (pdev->device != 0x4312 &&
4573 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4574 /* No multiband support. */
96c755a3
MB		 4575 have_2ghz_phy = 0;
4576 have_5ghz_phy = 0;
e4d6b795
MB		 4577 switch (dev->phy.type) {
4578 case B43_PHYTYPE_A:
96c755a3 4579 have_5ghz_phy = 1;
e4d6b795
MB		 4580 break;
4581 case B43_PHYTYPE_G:
96c755a3 4582 case B43_PHYTYPE_N:
6b1c7c67 4583 case B43_PHYTYPE_LP:
96c755a3 4584 have_2ghz_phy = 1;
e4d6b795
MB		 4585 break;
4586 default:
4587 B43_WARN_ON(1);
4588 }
4589 }
96c755a3
MB		 4590 if (dev->phy.type == B43_PHYTYPE_A) {
4591 /* FIXME */
4592 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4593 err = -EOPNOTSUPP;
4594 goto err_powerdown;
4595 }
2e35af14
MB		 4596 if (1 /* disable A-PHY */) {
4597 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4598 if (dev->phy.type != B43_PHYTYPE_N) {
4599 have_2ghz_phy = 1;
4600 have_5ghz_phy = 0;
4601 }
4602 }
4603
fb11137a
MB		 4604 err = b43_phy_allocate(dev);
4605 if (err)
4606 goto err_powerdown;
4607
96c755a3 4608 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4609 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4610 b43_wireless_core_reset(dev, tmp);
4611
4612 err = b43_validate_chipaccess(dev);
4613 if (err)
fb11137a 4614 goto err_phy_free;
bb1eeff1 4615 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4616 if (err)
fb11137a 4617 goto err_phy_free;
e4d6b795
MB		 4618
4619 /* Now set some default "current_dev" */
4620 if (!wl->current_dev)
4621 wl->current_dev = dev;
4622 INIT_WORK(&dev->restart_work, b43_chip_reset);
4623
cb24f57f 4624 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4625 ssb_device_disable(dev->dev, 0);
4626 ssb_bus_may_powerdown(bus);
4627
4628out:
4629 return err;
4630
fb11137a
MB		 4631err_phy_free:
4632 b43_phy_free(dev);
e4d6b795
MB		 4633err_powerdown:
4634 ssb_bus_may_powerdown(bus);
4635 return err;
4636}
4637
4638static void b43_one_core_detach(struct ssb_device *dev)
4639{
4640 struct b43_wldev *wldev;
4641 struct b43_wl *wl;
4642
3bf0a32e
MB		 4643 /* Do not cancel ieee80211-workqueue based work here.
4644 * See comment in b43_remove(). */
4645
e4d6b795
MB		 4646 wldev = ssb_get_drvdata(dev);
4647 wl = wldev->wl;
e4d6b795
MB		 4648 b43_debugfs_remove_device(wldev);
4649 b43_wireless_core_detach(wldev);
4650 list_del(&wldev->list);
4651 wl->nr_devs--;
4652 ssb_set_drvdata(dev, NULL);
4653 kfree(wldev);
4654}
4655
4656static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4657{
4658 struct b43_wldev *wldev;
4659 struct pci_dev *pdev;
4660 int err = -ENOMEM;
4661
4662 if (!list_empty(&wl->devlist)) {
4663 /* We are not the first core on this chip. */
4664 pdev = dev->bus->host_pci;
4665 /* Only special chips support more than one wireless
4666 * core, although some of the other chips have more than
4667 * one wireless core as well. Check for this and
4668 * bail out early.
4669 */
4670 if (!pdev ||
4671 ((pdev->device != 0x4321) &&
4672 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4673 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4674 return -ENODEV;
4675 }
4676 }
4677
4678 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4679 if (!wldev)
4680 goto out;
4681
4682 wldev->dev = dev;
4683 wldev->wl = wl;
4684 b43_set_status(wldev, B43_STAT_UNINIT);
4685 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4686 tasklet_init(&wldev->isr_tasklet,
4687 (void (*)(unsigned long))b43_interrupt_tasklet,
4688 (unsigned long)wldev);
e4d6b795
MB		 4689 INIT_LIST_HEAD(&wldev->list);
4690
4691 err = b43_wireless_core_attach(wldev);
4692 if (err)
4693 goto err_kfree_wldev;
4694
4695 list_add(&wldev->list, &wl->devlist);
4696 wl->nr_devs++;
4697 ssb_set_drvdata(dev, wldev);
4698 b43_debugfs_add_device(wldev);
4699
4700 out:
4701 return err;
4702
4703 err_kfree_wldev:
4704 kfree(wldev);
4705 return err;
4706}
4707
9fc38458
MB		 4708#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4709 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4710 (pdev->device == _device) && \
4711 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4712 (pdev->subsystem_device == _subdevice) )
4713
e4d6b795
MB		 4714static void b43_sprom_fixup(struct ssb_bus *bus)
4715{
1855ba78
MB		 4716 struct pci_dev *pdev;
4717
e4d6b795
MB		 4718 /* boardflags workarounds */
4719 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4720 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4721 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4722 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4723 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4724 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4725 if (bus->bustype == SSB_BUSTYPE_PCI) {
4726 pdev = bus->host_pci;
9fc38458 4727 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4728 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4729 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4730 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4731 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4732 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4733 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4734 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4735 }
e4d6b795
MB		 4736}
4737
4738static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4739{
4740 struct ieee80211_hw *hw = wl->hw;
4741
4742 ssb_set_devtypedata(dev, NULL);
4743 ieee80211_free_hw(hw);
4744}
4745
4746static int b43_wireless_init(struct ssb_device *dev)
4747{
4748 struct ssb_sprom *sprom = &dev->bus->sprom;
4749 struct ieee80211_hw *hw;
4750 struct b43_wl *wl;
4751 int err = -ENOMEM;
4752
4753 b43_sprom_fixup(dev->bus);
4754
4755 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4756 if (!hw) {
4757 b43err(NULL, "Could not allocate ieee80211 device\n");
4758 goto out;
4759 }
403a3a13 4760 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4761
4762 /* fill hw info */
605a0bd6 4763 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4764 IEEE80211_HW_SIGNAL_DBM |
4765 IEEE80211_HW_NOISE_DBM;
4766
f59ac048
LR		 4767 hw->wiphy->interface_modes =
4768 BIT(NL80211_IFTYPE_AP) |
4769 BIT(NL80211_IFTYPE_MESH_POINT) |
4770 BIT(NL80211_IFTYPE_STATION) |
4771 BIT(NL80211_IFTYPE_WDS) |
4772 BIT(NL80211_IFTYPE_ADHOC);
4773
403a3a13
MB		 4774 hw->queues = modparam_qos ? 4 : 1;
4775 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4776 hw->max_rates = 2;
e4d6b795 4777 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4778 if (is_valid_ether_addr(sprom->et1mac))
4779 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4780 else
95de2841 4781 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4782
403a3a13 4783 /* Initialize struct b43_wl */
e4d6b795
MB		 4784 wl->hw = hw;
4785 spin_lock_init(&wl->irq_lock);
21a75d77 4786 rwlock_init(&wl->tx_lock);
e4d6b795 4787 spin_lock_init(&wl->leds_lock);
280d0e16 4788 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4789 mutex_init(&wl->mutex);
4790 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4791 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4792 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4793
4794 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4795 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4796 dev->bus->chip_id, dev->id.revision);
e4d6b795 4797 err = 0;
060210f9 4798out:
e4d6b795
MB		 4799 return err;
4800}
4801
4802static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4803{
4804 struct b43_wl *wl;
4805 int err;
4806 int first = 0;
4807
4808 wl = ssb_get_devtypedata(dev);
4809 if (!wl) {
4810 /* Probing the first core. Must setup common struct b43_wl */
4811 first = 1;
4812 err = b43_wireless_init(dev);
4813 if (err)
4814 goto out;
4815 wl = ssb_get_devtypedata(dev);
4816 B43_WARN_ON(!wl);
4817 }
4818 err = b43_one_core_attach(dev, wl);
4819 if (err)
4820 goto err_wireless_exit;
4821
4822 if (first) {
4823 err = ieee80211_register_hw(wl->hw);
4824 if (err)
4825 goto err_one_core_detach;
4826 }
4827
4828 out:
4829 return err;
4830
4831 err_one_core_detach:
4832 b43_one_core_detach(dev);
4833 err_wireless_exit:
4834 if (first)
4835 b43_wireless_exit(dev, wl);
4836 return err;
4837}
4838
4839static void b43_remove(struct ssb_device *dev)
4840{
4841 struct b43_wl *wl = ssb_get_devtypedata(dev);
4842 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4843
3bf0a32e
MB		 4844 /* We must cancel any work here before unregistering from ieee80211,
4845 * as the ieee80211 unreg will destroy the workqueue. */
4846 cancel_work_sync(&wldev->restart_work);
4847
e4d6b795 4848 B43_WARN_ON(!wl);
403a3a13
MB		 4849 if (wl->current_dev == wldev) {
4850 /* Restore the queues count before unregistering, because firmware detect
4851 * might have modified it. Restoring is important, so the networking
4852 * stack can properly free resources. */
4853 wl->hw->queues = wl->mac80211_initially_registered_queues;
e4d6b795 4854 ieee80211_unregister_hw(wl->hw);
403a3a13 4855 }
e4d6b795
MB		 4856
4857 b43_one_core_detach(dev);
4858
4859 if (list_empty(&wl->devlist)) {
4860 /* Last core on the chip unregistered.
4861 * We can destroy common struct b43_wl.
4862 */
4863 b43_wireless_exit(dev, wl);
4864 }
4865}
4866
4867/* Perform a hardware reset. This can be called from any context. */
4868void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4869{
4870 /* Must avoid requeueing, if we are in shutdown. */
4871 if (b43_status(dev) < B43_STAT_INITIALIZED)
4872 return;
4873 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4874 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4875}
4876
4877#ifdef CONFIG_PM
4878
4879static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4880{
4881 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4882 struct b43_wl *wl = wldev->wl;
4883
4884 b43dbg(wl, "Suspending...\n");
4885
4886 mutex_lock(&wl->mutex);
3506e0c4 4887 wldev->suspend_in_progress = true;
e4d6b795
MB		 4888 wldev->suspend_init_status = b43_status(wldev);
4889 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4890 b43_wireless_core_stop(wldev);
4891 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4892 b43_wireless_core_exit(wldev);
4893 mutex_unlock(&wl->mutex);
4894
4895 b43dbg(wl, "Device suspended.\n");
4896
4897 return 0;
4898}
4899
4900static int b43_resume(struct ssb_device *dev)
4901{
4902 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4903 struct b43_wl *wl = wldev->wl;
4904 int err = 0;
4905
4906 b43dbg(wl, "Resuming...\n");
4907
4908 mutex_lock(&wl->mutex);
4909 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4910 err = b43_wireless_core_init(wldev);
4911 if (err) {
4912 b43err(wl, "Resume failed at core init\n");
4913 goto out;
4914 }
4915 }
4916 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4917 err = b43_wireless_core_start(wldev);
4918 if (err) {
3506e0c4 4919 b43_leds_exit(wldev);
b844eba2 4920 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4921 b43_wireless_core_exit(wldev);
4922 b43err(wl, "Resume failed at core start\n");
4923 goto out;
4924 }
4925 }
e4d6b795 4926 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4927 out:
4928 wldev->suspend_in_progress = false;
4929 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4930 return err;
4931}
4932
4933#else /* CONFIG_PM */
4934# define b43_suspend NULL
4935# define b43_resume NULL
4936#endif /* CONFIG_PM */
4937
4938static struct ssb_driver b43_ssb_driver = {
4939 .name = KBUILD_MODNAME,
4940 .id_table = b43_ssb_tbl,
4941 .probe = b43_probe,
4942 .remove = b43_remove,
4943 .suspend = b43_suspend,
4944 .resume = b43_resume,
4945};
4946
26bc783f
MB		 4947static void b43_print_driverinfo(void)
4948{
4949 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
f41f3f37 4950 *feat_leds = "";
26bc783f
MB		 4951
4952#ifdef CONFIG_B43_PCI_AUTOSELECT
4953 feat_pci = "P";
4954#endif
4955#ifdef CONFIG_B43_PCMCIA
4956 feat_pcmcia = "M";
4957#endif
4958#ifdef CONFIG_B43_NPHY
4959 feat_nphy = "N";
4960#endif
4961#ifdef CONFIG_B43_LEDS
4962 feat_leds = "L";
26bc783f
MB		 4963#endif
4964 printk(KERN_INFO "Broadcom 43xx driver loaded "
f41f3f37 4965 "[ Features: %s%s%s%s, Firmware-ID: "
26bc783f
MB		 4966 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4967 feat_pci, feat_pcmcia, feat_nphy,
f41f3f37 4968 feat_leds);
26bc783f
MB		 4969}
4970
e4d6b795
MB		 4971static int __init b43_init(void)
4972{
4973 int err;
4974
4975 b43_debugfs_init();
4976 err = b43_pcmcia_init();
4977 if (err)
4978 goto err_dfs_exit;
4979 err = ssb_driver_register(&b43_ssb_driver);
4980 if (err)
4981 goto err_pcmcia_exit;
26bc783f 4982 b43_print_driverinfo();
e4d6b795
MB		 4983
4984 return err;
4985
4986err_pcmcia_exit:
4987 b43_pcmcia_exit();
4988err_dfs_exit:
4989 b43_debugfs_exit();
4990 return err;
4991}
4992
4993static void __exit b43_exit(void)
4994{
4995 ssb_driver_unregister(&b43_ssb_driver);
4996 b43_pcmcia_exit();
4997 b43_debugfs_exit();
4998}
4999
5000module_init(b43_init)
5001module_exit(b43_exit)
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