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b43: Remove PIO RX workqueue
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
0136e51e 61MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 62MODULE_LICENSE("GPL");
63
9c7d99d6
MB		 64MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
65
e4d6b795
MB		 66
67static int modparam_bad_frames_preempt;
68module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
69MODULE_PARM_DESC(bad_frames_preempt,
70 "enable(1) / disable(0) Bad Frames Preemption");
71
e4d6b795
MB		 72static char modparam_fwpostfix[16];
73module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
74MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75
e4d6b795
MB		 76static int modparam_hwpctl;
77module_param_named(hwpctl, modparam_hwpctl, int, 0444);
78MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79
80static int modparam_nohwcrypt;
81module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
82MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83
035d0243 84static int modparam_hwtkip;
85module_param_named(hwtkip, modparam_hwtkip, int, 0444);
86MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
87
403a3a13
MB		 88static int modparam_qos = 1;
89module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 90MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
91
1855ba78
MB		 92static int modparam_btcoex = 1;
93module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 94MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 95
060210f9
MB		 96int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
97module_param_named(verbose, b43_modparam_verbose, int, 0644);
98MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
99
e6f5b934 100
e4d6b795
MB		 101static const struct ssb_device_id b43_ssb_tbl[] = {
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 111 SSB_DEVTABLE_END
112};
113
114MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
115
116/* Channel and ratetables are shared for all devices.
117 * They can't be const, because ieee80211 puts some precalculated
118 * data in there. This data is the same for all devices, so we don't
119 * get concurrency issues */
120#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 121 { \
122 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
123 .hw_value = (_rateid), \
124 .flags = (_flags), \
e4d6b795 125 }
8318d78a
JB		 126
127/*
128 * NOTE: When changing this, sync with xmit.c's
129 * b43_plcp_get_bitrate_idx_* functions!
130 */
e4d6b795 131static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 132 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
133 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 144};
145
146#define b43_a_ratetable (__b43_ratetable + 4)
147#define b43_a_ratetable_size 8
148#define b43_b_ratetable (__b43_ratetable + 0)
149#define b43_b_ratetable_size 4
150#define b43_g_ratetable (__b43_ratetable + 0)
151#define b43_g_ratetable_size 12
152
bb1eeff1
MB		 153#define CHAN4G(_channel, _freq, _flags) { \
154 .band = IEEE80211_BAND_2GHZ, \
155 .center_freq = (_freq), \
156 .hw_value = (_channel), \
157 .flags = (_flags), \
158 .max_antenna_gain = 0, \
159 .max_power = 30, \
160}
96c755a3 161static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 162 CHAN4G(1, 2412, 0),
163 CHAN4G(2, 2417, 0),
164 CHAN4G(3, 2422, 0),
165 CHAN4G(4, 2427, 0),
166 CHAN4G(5, 2432, 0),
167 CHAN4G(6, 2437, 0),
168 CHAN4G(7, 2442, 0),
169 CHAN4G(8, 2447, 0),
170 CHAN4G(9, 2452, 0),
171 CHAN4G(10, 2457, 0),
172 CHAN4G(11, 2462, 0),
173 CHAN4G(12, 2467, 0),
174 CHAN4G(13, 2472, 0),
175 CHAN4G(14, 2484, 0),
176};
177#undef CHAN4G
178
179#define CHAN5G(_channel, _flags) { \
180 .band = IEEE80211_BAND_5GHZ, \
181 .center_freq = 5000 + (5 * (_channel)), \
182 .hw_value = (_channel), \
183 .flags = (_flags), \
184 .max_antenna_gain = 0, \
185 .max_power = 30, \
186}
187static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
188 CHAN5G(32, 0), CHAN5G(34, 0),
189 CHAN5G(36, 0), CHAN5G(38, 0),
190 CHAN5G(40, 0), CHAN5G(42, 0),
191 CHAN5G(44, 0), CHAN5G(46, 0),
192 CHAN5G(48, 0), CHAN5G(50, 0),
193 CHAN5G(52, 0), CHAN5G(54, 0),
194 CHAN5G(56, 0), CHAN5G(58, 0),
195 CHAN5G(60, 0), CHAN5G(62, 0),
196 CHAN5G(64, 0), CHAN5G(66, 0),
197 CHAN5G(68, 0), CHAN5G(70, 0),
198 CHAN5G(72, 0), CHAN5G(74, 0),
199 CHAN5G(76, 0), CHAN5G(78, 0),
200 CHAN5G(80, 0), CHAN5G(82, 0),
201 CHAN5G(84, 0), CHAN5G(86, 0),
202 CHAN5G(88, 0), CHAN5G(90, 0),
203 CHAN5G(92, 0), CHAN5G(94, 0),
204 CHAN5G(96, 0), CHAN5G(98, 0),
205 CHAN5G(100, 0), CHAN5G(102, 0),
206 CHAN5G(104, 0), CHAN5G(106, 0),
207 CHAN5G(108, 0), CHAN5G(110, 0),
208 CHAN5G(112, 0), CHAN5G(114, 0),
209 CHAN5G(116, 0), CHAN5G(118, 0),
210 CHAN5G(120, 0), CHAN5G(122, 0),
211 CHAN5G(124, 0), CHAN5G(126, 0),
212 CHAN5G(128, 0), CHAN5G(130, 0),
213 CHAN5G(132, 0), CHAN5G(134, 0),
214 CHAN5G(136, 0), CHAN5G(138, 0),
215 CHAN5G(140, 0), CHAN5G(142, 0),
216 CHAN5G(144, 0), CHAN5G(145, 0),
217 CHAN5G(146, 0), CHAN5G(147, 0),
218 CHAN5G(148, 0), CHAN5G(149, 0),
219 CHAN5G(150, 0), CHAN5G(151, 0),
220 CHAN5G(152, 0), CHAN5G(153, 0),
221 CHAN5G(154, 0), CHAN5G(155, 0),
222 CHAN5G(156, 0), CHAN5G(157, 0),
223 CHAN5G(158, 0), CHAN5G(159, 0),
224 CHAN5G(160, 0), CHAN5G(161, 0),
225 CHAN5G(162, 0), CHAN5G(163, 0),
226 CHAN5G(164, 0), CHAN5G(165, 0),
227 CHAN5G(166, 0), CHAN5G(168, 0),
228 CHAN5G(170, 0), CHAN5G(172, 0),
229 CHAN5G(174, 0), CHAN5G(176, 0),
230 CHAN5G(178, 0), CHAN5G(180, 0),
231 CHAN5G(182, 0), CHAN5G(184, 0),
232 CHAN5G(186, 0), CHAN5G(188, 0),
233 CHAN5G(190, 0), CHAN5G(192, 0),
234 CHAN5G(194, 0), CHAN5G(196, 0),
235 CHAN5G(198, 0), CHAN5G(200, 0),
236 CHAN5G(202, 0), CHAN5G(204, 0),
237 CHAN5G(206, 0), CHAN5G(208, 0),
238 CHAN5G(210, 0), CHAN5G(212, 0),
239 CHAN5G(214, 0), CHAN5G(216, 0),
240 CHAN5G(218, 0), CHAN5G(220, 0),
241 CHAN5G(222, 0), CHAN5G(224, 0),
242 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 243};
244
bb1eeff1
MB		 245static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
246 CHAN5G(34, 0), CHAN5G(36, 0),
247 CHAN5G(38, 0), CHAN5G(40, 0),
248 CHAN5G(42, 0), CHAN5G(44, 0),
249 CHAN5G(46, 0), CHAN5G(48, 0),
250 CHAN5G(52, 0), CHAN5G(56, 0),
251 CHAN5G(60, 0), CHAN5G(64, 0),
252 CHAN5G(100, 0), CHAN5G(104, 0),
253 CHAN5G(108, 0), CHAN5G(112, 0),
254 CHAN5G(116, 0), CHAN5G(120, 0),
255 CHAN5G(124, 0), CHAN5G(128, 0),
256 CHAN5G(132, 0), CHAN5G(136, 0),
257 CHAN5G(140, 0), CHAN5G(149, 0),
258 CHAN5G(153, 0), CHAN5G(157, 0),
259 CHAN5G(161, 0), CHAN5G(165, 0),
260 CHAN5G(184, 0), CHAN5G(188, 0),
261 CHAN5G(192, 0), CHAN5G(196, 0),
262 CHAN5G(200, 0), CHAN5G(204, 0),
263 CHAN5G(208, 0), CHAN5G(212, 0),
264 CHAN5G(216, 0),
265};
266#undef CHAN5G
267
268static struct ieee80211_supported_band b43_band_5GHz_nphy = {
269 .band = IEEE80211_BAND_5GHZ,
270 .channels = b43_5ghz_nphy_chantable,
271 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
272 .bitrates = b43_a_ratetable,
273 .n_bitrates = b43_a_ratetable_size,
e4d6b795 274};
8318d78a 275
bb1eeff1
MB		 276static struct ieee80211_supported_band b43_band_5GHz_aphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_aphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
8318d78a 282};
e4d6b795 283
8318d78a 284static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 285 .band = IEEE80211_BAND_2GHZ,
286 .channels = b43_2ghz_chantable,
287 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
288 .bitrates = b43_g_ratetable,
289 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 290};
291
e4d6b795
MB		 292static void b43_wireless_core_exit(struct b43_wldev *dev);
293static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 294static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795
MB		 295static int b43_wireless_core_start(struct b43_wldev *dev);
296
297static int b43_ratelimit(struct b43_wl *wl)
298{
299 if (!wl || !wl->current_dev)
300 return 1;
301 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
302 return 1;
303 /* We are up and running.
304 * Ratelimit the messages to avoid DoS over the net. */
305 return net_ratelimit();
306}
307
308void b43info(struct b43_wl *wl, const char *fmt, ...)
309{
310 va_list args;
311
060210f9
MB		 312 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
313 return;
e4d6b795
MB		 314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_INFO "b43-%s: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43err(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
060210f9
MB		 327 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
328 return;
e4d6b795
MB		 329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_ERR "b43-%s ERROR: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336}
337
338void b43warn(struct b43_wl *wl, const char *fmt, ...)
339{
340 va_list args;
341
060210f9
MB		 342 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
343 return;
e4d6b795
MB		 344 if (!b43_ratelimit(wl))
345 return;
346 va_start(args, fmt);
347 printk(KERN_WARNING "b43-%s warning: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 vprintk(fmt, args);
350 va_end(args);
351}
352
e4d6b795
MB		 353void b43dbg(struct b43_wl *wl, const char *fmt, ...)
354{
355 va_list args;
356
060210f9
MB		 357 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
358 return;
e4d6b795
MB		 359 va_start(args, fmt);
360 printk(KERN_DEBUG "b43-%s debug: ",
361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
362 vprintk(fmt, args);
363 va_end(args);
364}
e4d6b795
MB		 365
366static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
367{
368 u32 macctl;
369
370 B43_WARN_ON(offset % 4 != 0);
371
372 macctl = b43_read32(dev, B43_MMIO_MACCTL);
373 if (macctl & B43_MACCTL_BE)
374 val = swab32(val);
375
376 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
377 mmiowb();
378 b43_write32(dev, B43_MMIO_RAM_DATA, val);
379}
380
280d0e16
MB		 381static inline void b43_shm_control_word(struct b43_wldev *dev,
382 u16 routing, u16 offset)
e4d6b795
MB		 383{
384 u32 control;
385
386 /* "offset" is the WORD offset. */
e4d6b795
MB		 387 control = routing;
388 control <<= 16;
389 control |= offset;
390 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
391}
392
6bbc321a 393u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 394{
395 u32 ret;
396
397 if (routing == B43_SHM_SHARED) {
398 B43_WARN_ON(offset & 0x0001);
399 if (offset & 0x0003) {
400 /* Unaligned access */
401 b43_shm_control_word(dev, routing, offset >> 2);
402 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 403 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 404 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 405
280d0e16 406 goto out;
e4d6b795
MB		 407 }
408 offset >>= 2;
409 }
410 b43_shm_control_word(dev, routing, offset);
411 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 412out:
e4d6b795
MB		 413 return ret;
414}
415
6bbc321a 416u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 417{
280d0e16
MB		 418 struct b43_wl *wl = dev->wl;
419 unsigned long flags;
6bbc321a 420 u32 ret;
e4d6b795 421
280d0e16 422 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 423 ret = __b43_shm_read32(dev, routing, offset);
424 spin_unlock_irqrestore(&wl->shm_lock, flags);
425
426 return ret;
427}
428
429u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
430{
431 u16 ret;
432
e4d6b795
MB		 433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
438 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
439
280d0e16 440 goto out;
e4d6b795
MB		 441 }
442 offset >>= 2;
443 }
444 b43_shm_control_word(dev, routing, offset);
445 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 446out:
e4d6b795
MB		 447 return ret;
448}
449
6bbc321a 450u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 451{
280d0e16
MB		 452 struct b43_wl *wl = dev->wl;
453 unsigned long flags;
6bbc321a 454 u16 ret;
280d0e16
MB		 455
456 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 457 ret = __b43_shm_read16(dev, routing, offset);
458 spin_unlock_irqrestore(&wl->shm_lock, flags);
459
460 return ret;
461}
462
463void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
464{
e4d6b795
MB		 465 if (routing == B43_SHM_SHARED) {
466 B43_WARN_ON(offset & 0x0001);
467 if (offset & 0x0003) {
468 /* Unaligned access */
469 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 470 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 471 value & 0xFFFF);
e4d6b795 472 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 473 b43_write16(dev, B43_MMIO_SHM_DATA,
474 (value >> 16) & 0xFFFF);
6bbc321a 475 return;
e4d6b795
MB		 476 }
477 offset >>= 2;
478 }
479 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 480 b43_write32(dev, B43_MMIO_SHM_DATA, value);
481}
482
6bbc321a 483void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 484{
280d0e16
MB		 485 struct b43_wl *wl = dev->wl;
486 unsigned long flags;
487
488 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 489 __b43_shm_write32(dev, routing, offset, value);
490 spin_unlock_irqrestore(&wl->shm_lock, flags);
491}
492
493void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
494{
e4d6b795
MB		 495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 501 return;
e4d6b795
MB		 502 }
503 offset >>= 2;
504 }
505 b43_shm_control_word(dev, routing, offset);
e4d6b795 506 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 507}
508
509void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
510{
511 struct b43_wl *wl = dev->wl;
512 unsigned long flags;
513
514 spin_lock_irqsave(&wl->shm_lock, flags);
515 __b43_shm_write16(dev, routing, offset, value);
280d0e16 516 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 517}
518
519/* Read HostFlags */
99da185a 520u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 521{
35f0d354 522 u64 ret;
e4d6b795
MB		 523
524 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
525 ret <<= 16;
35f0d354
MB		 526 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
527 ret <<= 16;
e4d6b795
MB		 528 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
529
530 return ret;
531}
532
533/* Write HostFlags */
35f0d354 534void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 535{
35f0d354
MB		 536 u16 lo, mi, hi;
537
538 lo = (value & 0x00000000FFFFULL);
539 mi = (value & 0x0000FFFF0000ULL) >> 16;
540 hi = (value & 0xFFFF00000000ULL) >> 32;
541 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
542 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
543 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 544}
545
403a3a13
MB		 546/* Read the firmware capabilities bitmask (Opensource firmware only) */
547static u16 b43_fwcapa_read(struct b43_wldev *dev)
548{
549 B43_WARN_ON(!dev->fw.opensource);
550 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
551}
552
3ebbbb56 553void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 554{
3ebbbb56
MB		 555 u32 low, high;
556
557 B43_WARN_ON(dev->dev->id.revision < 3);
558
559 /* The hardware guarantees us an atomic read, if we
560 * read the low register first. */
561 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
562 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
563
564 *tsf = high;
565 *tsf <<= 32;
566 *tsf |= low;
e4d6b795
MB		 567}
568
569static void b43_time_lock(struct b43_wldev *dev)
570{
571 u32 macctl;
572
573 macctl = b43_read32(dev, B43_MMIO_MACCTL);
574 macctl |= B43_MACCTL_TBTTHOLD;
575 b43_write32(dev, B43_MMIO_MACCTL, macctl);
576 /* Commit the write */
577 b43_read32(dev, B43_MMIO_MACCTL);
578}
579
580static void b43_time_unlock(struct b43_wldev *dev)
581{
582 u32 macctl;
583
584 macctl = b43_read32(dev, B43_MMIO_MACCTL);
585 macctl &= ~B43_MACCTL_TBTTHOLD;
586 b43_write32(dev, B43_MMIO_MACCTL, macctl);
587 /* Commit the write */
588 b43_read32(dev, B43_MMIO_MACCTL);
589}
590
591static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
592{
3ebbbb56
MB		 593 u32 low, high;
594
595 B43_WARN_ON(dev->dev->id.revision < 3);
596
597 low = tsf;
598 high = (tsf >> 32);
599 /* The hardware guarantees us an atomic write, if we
600 * write the low register first. */
601 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
602 mmiowb();
603 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
604 mmiowb();
e4d6b795
MB		 605}
606
607void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
608{
609 b43_time_lock(dev);
610 b43_tsf_write_locked(dev, tsf);
611 b43_time_unlock(dev);
612}
613
614static
99da185a 615void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 616{
617 static const u8 zero_addr[ETH_ALEN] = { 0 };
618 u16 data;
619
620 if (!mac)
621 mac = zero_addr;
622
623 offset |= 0x0020;
624 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
625
626 data = mac[0];
627 data |= mac[1] << 8;
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
629 data = mac[2];
630 data |= mac[3] << 8;
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632 data = mac[4];
633 data |= mac[5] << 8;
634 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635}
636
637static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
638{
639 const u8 *mac;
640 const u8 *bssid;
641 u8 mac_bssid[ETH_ALEN * 2];
642 int i;
643 u32 tmp;
644
645 bssid = dev->wl->bssid;
646 mac = dev->wl->mac_addr;
647
648 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
649
650 memcpy(mac_bssid, mac, ETH_ALEN);
651 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
652
653 /* Write our MAC address and BSSID to template ram */
654 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
655 tmp = (u32) (mac_bssid[i + 0]);
656 tmp |= (u32) (mac_bssid[i + 1]) << 8;
657 tmp |= (u32) (mac_bssid[i + 2]) << 16;
658 tmp |= (u32) (mac_bssid[i + 3]) << 24;
659 b43_ram_write(dev, 0x20 + i, tmp);
660 }
661}
662
4150c572 663static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 664{
e4d6b795 665 b43_write_mac_bssid_templates(dev);
4150c572 666 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 667}
668
669static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
670{
671 /* slot_time is in usec. */
672 if (dev->phy.type != B43_PHYTYPE_G)
673 return;
674 b43_write16(dev, 0x684, 510 + slot_time);
675 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
676}
677
678static void b43_short_slot_timing_enable(struct b43_wldev *dev)
679{
680 b43_set_slot_time(dev, 9);
e4d6b795
MB		 681}
682
683static void b43_short_slot_timing_disable(struct b43_wldev *dev)
684{
685 b43_set_slot_time(dev, 20);
e4d6b795
MB		 686}
687
e4d6b795 688/* DummyTransmission function, as documented on
2f19c287 689 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 690 */
2f19c287 691void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 692{
693 struct b43_phy *phy = &dev->phy;
694 unsigned int i, max_loop;
695 u16 value;
696 u32 buffer[5] = {
697 0x00000000,
698 0x00D40000,
699 0x00000000,
700 0x01000000,
701 0x00000000,
702 };
703
2f19c287 704 if (ofdm) {
e4d6b795
MB		 705 max_loop = 0x1E;
706 buffer[0] = 0x000201CC;
2f19c287 707 } else {
e4d6b795
MB		 708 max_loop = 0xFA;
709 buffer[0] = 0x000B846E;
e4d6b795
MB		 710 }
711
712 for (i = 0; i < 5; i++)
713 b43_ram_write(dev, i * 4, buffer[i]);
714
e4d6b795 715 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 716 if (dev->dev->id.revision < 11)
717 b43_write16(dev, 0x07C0, 0x0000);
718 else
719 b43_write16(dev, 0x07C0, 0x0100);
720 value = (ofdm ? 0x41 : 0x40);
e4d6b795 721 b43_write16(dev, 0x050C, value);
2f19c287
GS		 722 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
723 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 724 b43_write16(dev, 0x0508, 0x0000);
725 b43_write16(dev, 0x050A, 0x0000);
726 b43_write16(dev, 0x054C, 0x0000);
727 b43_write16(dev, 0x056A, 0x0014);
728 b43_write16(dev, 0x0568, 0x0826);
729 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 730 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
731 //SPEC TODO
732 }
733
734 switch (phy->type) {
735 case B43_PHYTYPE_N:
736 b43_write16(dev, 0x0502, 0x00D0);
737 break;
738 case B43_PHYTYPE_LP:
739 b43_write16(dev, 0x0502, 0x0050);
740 break;
741 default:
742 b43_write16(dev, 0x0502, 0x0030);
743 }
e4d6b795
MB		 744
745 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
746 b43_radio_write16(dev, 0x0051, 0x0017);
747 for (i = 0x00; i < max_loop; i++) {
748 value = b43_read16(dev, 0x050E);
749 if (value & 0x0080)
750 break;
751 udelay(10);
752 }
753 for (i = 0x00; i < 0x0A; i++) {
754 value = b43_read16(dev, 0x050E);
755 if (value & 0x0400)
756 break;
757 udelay(10);
758 }
1d280ddc 759 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 760 value = b43_read16(dev, 0x0690);
761 if (!(value & 0x0100))
762 break;
763 udelay(10);
764 }
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0037);
767}
768
769static void key_write(struct b43_wldev *dev,
99da185a 770 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 771{
772 unsigned int i;
773 u32 offset;
774 u16 value;
775 u16 kidx;
776
777 /* Key index/algo block */
778 kidx = b43_kidx_to_fw(dev, index);
779 value = ((kidx << 4) | algorithm);
780 b43_shm_write16(dev, B43_SHM_SHARED,
781 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
782
783 /* Write the key to the Key Table Pointer offset */
784 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
785 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
786 value = key[i];
787 value |= (u16) (key[i + 1]) << 8;
788 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
789 }
790}
791
99da185a 792static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 793{
794 u32 addrtmp[2] = { 0, 0, };
66d2d089 795 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 796
797 if (b43_new_kidx_api(dev))
66d2d089 798 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 799
66d2d089
MB		 800 B43_WARN_ON(index < pairwise_keys_start);
801 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 802 * Physical mac 0 is mapped to physical key 4 or 8, depending
803 * on the firmware version.
804 * So we must adjust the index here.
805 */
66d2d089
MB		 806 index -= pairwise_keys_start;
807 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 808
809 if (addr) {
810 addrtmp[0] = addr[0];
811 addrtmp[0] |= ((u32) (addr[1]) << 8);
812 addrtmp[0] |= ((u32) (addr[2]) << 16);
813 addrtmp[0] |= ((u32) (addr[3]) << 24);
814 addrtmp[1] = addr[4];
815 addrtmp[1] |= ((u32) (addr[5]) << 8);
816 }
817
66d2d089
MB		 818 /* Receive match transmitter address (RCMTA) mechanism */
819 b43_shm_write32(dev, B43_SHM_RCMTA,
820 (index * 2) + 0, addrtmp[0]);
821 b43_shm_write16(dev, B43_SHM_RCMTA,
822 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 823}
824
035d0243 825/* The ucode will use phase1 key with TEK key to decrypt rx packets.
826 * When a packet is received, the iv32 is checked.
827 * - if it doesn't the packet is returned without modification (and software
828 * decryption can be done). That's what happen when iv16 wrap.
829 * - if it does, the rc4 key is computed, and decryption is tried.
830 * Either it will success and B43_RX_MAC_DEC is returned,
831 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
832 * and the packet is not usable (it got modified by the ucode).
833 * So in order to never have B43_RX_MAC_DECERR, we should provide
834 * a iv32 and phase1key that match. Because we drop packets in case of
835 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
836 * packets will be lost without higher layer knowing (ie no resync possible
837 * until next wrap).
838 *
839 * NOTE : this should support 50 key like RCMTA because
840 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
841 */
842static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
843 u16 *phase1key)
844{
845 unsigned int i;
846 u32 offset;
847 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
848
849 if (!modparam_hwtkip)
850 return;
851
852 if (b43_new_kidx_api(dev))
853 pairwise_keys_start = B43_NR_GROUP_KEYS;
854
855 B43_WARN_ON(index < pairwise_keys_start);
856 /* We have four default TX keys and possibly four default RX keys.
857 * Physical mac 0 is mapped to physical key 4 or 8, depending
858 * on the firmware version.
859 * So we must adjust the index here.
860 */
861 index -= pairwise_keys_start;
862 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
863
864 if (b43_debug(dev, B43_DBG_KEYS)) {
865 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
866 index, iv32);
867 }
868 /* Write the key to the RX tkip shared mem */
869 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
870 for (i = 0; i < 10; i += 2) {
871 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
872 phase1key ? phase1key[i / 2] : 0);
873 }
874 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
876}
877
878static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
879 struct ieee80211_key_conf *keyconf, const u8 *addr,
880 u32 iv32, u16 *phase1key)
881{
882 struct b43_wl *wl = hw_to_b43_wl(hw);
883 struct b43_wldev *dev;
884 int index = keyconf->hw_key_idx;
885
886 if (B43_WARN_ON(!modparam_hwtkip))
887 return;
888
889 mutex_lock(&wl->mutex);
890
891 dev = wl->current_dev;
892 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
893 goto out_unlock;
894
895 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
896
897 rx_tkip_phase1_write(dev, index, iv32, phase1key);
898 keymac_write(dev, index, addr);
899
900out_unlock:
901 mutex_unlock(&wl->mutex);
902}
903
e4d6b795
MB		 904static void do_key_write(struct b43_wldev *dev,
905 u8 index, u8 algorithm,
99da185a 906 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 907{
908 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 909 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 910
911 if (b43_new_kidx_api(dev))
66d2d089 912 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 913
66d2d089 914 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 915 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
916
66d2d089 917 if (index >= pairwise_keys_start)
e4d6b795 918 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 919 if (algorithm == B43_SEC_ALGO_TKIP) {
920 /*
921 * We should provide an initial iv32, phase1key pair.
922 * We could start with iv32=0 and compute the corresponding
923 * phase1key, but this means calling ieee80211_get_tkip_key
924 * with a fake skb (or export other tkip function).
925 * Because we are lazy we hope iv32 won't start with
926 * 0xffffffff and let's b43_op_update_tkip_key provide a
927 * correct pair.
928 */
929 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
930 } else if (index >= pairwise_keys_start) /* clear it */
931 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 932 if (key)
933 memcpy(buf, key, key_len);
934 key_write(dev, index, algorithm, buf);
66d2d089 935 if (index >= pairwise_keys_start)
e4d6b795
MB		 936 keymac_write(dev, index, mac_addr);
937
938 dev->key[index].algorithm = algorithm;
939}
940
941static int b43_key_write(struct b43_wldev *dev,
942 int index, u8 algorithm,
99da185a
JD		 943 const u8 *key, size_t key_len,
944 const u8 *mac_addr,
e4d6b795
MB		 945 struct ieee80211_key_conf *keyconf)
946{
947 int i;
66d2d089 948 int pairwise_keys_start;
e4d6b795 949
035d0243 950 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
951 * - Temporal Encryption Key (128 bits)
952 * - Temporal Authenticator Tx MIC Key (64 bits)
953 * - Temporal Authenticator Rx MIC Key (64 bits)
954 *
955 * Hardware only store TEK
956 */
957 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
958 key_len = 16;
e4d6b795
MB		 959 if (key_len > B43_SEC_KEYSIZE)
960 return -EINVAL;
66d2d089 961 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 962 /* Check that we don't already have this key. */
963 B43_WARN_ON(dev->key[i].keyconf == keyconf);
964 }
965 if (index < 0) {
e808e586 966 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 967 if (b43_new_kidx_api(dev))
66d2d089 968 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 969 else
66d2d089
MB		 970 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
971 for (i = pairwise_keys_start;
972 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
973 i++) {
974 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 975 if (!dev->key[i].keyconf) {
976 /* found empty */
977 index = i;
978 break;
979 }
980 }
981 if (index < 0) {
e808e586 982 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 983 return -ENOSPC;
984 }
985 } else
986 B43_WARN_ON(index > 3);
987
988 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
989 if ((index <= 3) && !b43_new_kidx_api(dev)) {
990 /* Default RX key */
991 B43_WARN_ON(mac_addr);
992 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
993 }
994 keyconf->hw_key_idx = index;
995 dev->key[index].keyconf = keyconf;
996
997 return 0;
998}
999
1000static int b43_key_clear(struct b43_wldev *dev, int index)
1001{
66d2d089 1002 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1003 return -EINVAL;
1004 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1005 NULL, B43_SEC_KEYSIZE, NULL);
1006 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1007 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1008 NULL, B43_SEC_KEYSIZE, NULL);
1009 }
1010 dev->key[index].keyconf = NULL;
1011
1012 return 0;
1013}
1014
1015static void b43_clear_keys(struct b43_wldev *dev)
1016{
66d2d089 1017 int i, count;
e4d6b795 1018
66d2d089
MB		 1019 if (b43_new_kidx_api(dev))
1020 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1021 else
1022 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1023 for (i = 0; i < count; i++)
e4d6b795
MB		 1024 b43_key_clear(dev, i);
1025}
1026
9cf7f247
MB		 1027static void b43_dump_keymemory(struct b43_wldev *dev)
1028{
66d2d089 1029 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1030 u8 mac[ETH_ALEN];
1031 u16 algo;
1032 u32 rcmta0;
1033 u16 rcmta1;
1034 u64 hf;
1035 struct b43_key *key;
1036
1037 if (!b43_debug(dev, B43_DBG_KEYS))
1038 return;
1039
1040 hf = b43_hf_read(dev);
1041 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1042 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1043 if (b43_new_kidx_api(dev)) {
1044 pairwise_keys_start = B43_NR_GROUP_KEYS;
1045 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1046 } else {
1047 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1048 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1049 }
1050 for (index = 0; index < count; index++) {
9cf7f247
MB		 1051 key = &(dev->key[index]);
1052 printk(KERN_DEBUG "Key slot %02u: %s",
1053 index, (key->keyconf == NULL) ? " " : "*");
1054 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1055 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1056 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1057 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1058 }
1059
1060 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1061 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1062 printk(" Algo: %04X/%02X", algo, key->algorithm);
1063
66d2d089 1064 if (index >= pairwise_keys_start) {
035d0243 1065 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1066 printk(" TKIP: ");
1067 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1068 for (i = 0; i < 14; i += 2) {
1069 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1070 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1071 }
1072 }
9cf7f247 1073 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1074 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1075 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1076 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1077 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1078 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1079 printk(" MAC: %pM", mac);
9cf7f247
MB		 1080 } else
1081 printk(" DEFAULT KEY");
1082 printk("\n");
1083 }
1084}
1085
e4d6b795
MB		 1086void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1087{
1088 u32 macctl;
1089 u16 ucstat;
1090 bool hwps;
1091 bool awake;
1092 int i;
1093
1094 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1095 (ps_flags & B43_PS_DISABLED));
1096 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1097
1098 if (ps_flags & B43_PS_ENABLED) {
1099 hwps = 1;
1100 } else if (ps_flags & B43_PS_DISABLED) {
1101 hwps = 0;
1102 } else {
1103 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1104 // and thus is not an AP and we are associated, set bit 25
1105 }
1106 if (ps_flags & B43_PS_AWAKE) {
1107 awake = 1;
1108 } else if (ps_flags & B43_PS_ASLEEP) {
1109 awake = 0;
1110 } else {
1111 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1112 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1113 // successful, set bit26
1114 }
1115
1116/* FIXME: For now we force awake-on and hwps-off */
1117 hwps = 0;
1118 awake = 1;
1119
1120 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1121 if (hwps)
1122 macctl |= B43_MACCTL_HWPS;
1123 else
1124 macctl &= ~B43_MACCTL_HWPS;
1125 if (awake)
1126 macctl |= B43_MACCTL_AWAKE;
1127 else
1128 macctl &= ~B43_MACCTL_AWAKE;
1129 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1130 /* Commit write */
1131 b43_read32(dev, B43_MMIO_MACCTL);
1132 if (awake && dev->dev->id.revision >= 5) {
1133 /* Wait for the microcode to wake up. */
1134 for (i = 0; i < 100; i++) {
1135 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1136 B43_SHM_SH_UCODESTAT);
1137 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1138 break;
1139 udelay(10);
1140 }
1141 }
1142}
1143
e4d6b795
MB		 1144void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1145{
1146 u32 tmslow;
1147 u32 macctl;
1148
1149 flags |= B43_TMSLOW_PHYCLKEN;
1150 flags |= B43_TMSLOW_PHYRESET;
1151 ssb_device_enable(dev->dev, flags);
1152 msleep(2); /* Wait for the PLL to turn on. */
1153
1154 /* Now take the PHY out of Reset again */
1155 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1156 tmslow |= SSB_TMSLOW_FGC;
1157 tmslow &= ~B43_TMSLOW_PHYRESET;
1158 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1159 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1160 msleep(1);
1161 tmslow &= ~SSB_TMSLOW_FGC;
1162 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1163 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1164 msleep(1);
1165
fb11137a
MB		 1166 /* Turn Analog ON, but only if we already know the PHY-type.
1167 * This protects against very early setup where we don't know the
1168 * PHY-type, yet. wireless_core_reset will be called once again later,
1169 * when we know the PHY-type. */
1170 if (dev->phy.ops)
cb24f57f 1171 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1172
1173 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1174 macctl &= ~B43_MACCTL_GMODE;
1175 if (flags & B43_TMSLOW_GMODE)
1176 macctl |= B43_MACCTL_GMODE;
1177 macctl |= B43_MACCTL_IHR_ENABLED;
1178 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1179}
1180
1181static void handle_irq_transmit_status(struct b43_wldev *dev)
1182{
1183 u32 v0, v1;
1184 u16 tmp;
1185 struct b43_txstatus stat;
1186
1187 while (1) {
1188 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1189 if (!(v0 & 0x00000001))
1190 break;
1191 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1192
1193 stat.cookie = (v0 >> 16);
1194 stat.seq = (v1 & 0x0000FFFF);
1195 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1196 tmp = (v0 & 0x0000FFFF);
1197 stat.frame_count = ((tmp & 0xF000) >> 12);
1198 stat.rts_count = ((tmp & 0x0F00) >> 8);
1199 stat.supp_reason = ((tmp & 0x001C) >> 2);
1200 stat.pm_indicated = !!(tmp & 0x0080);
1201 stat.intermediate = !!(tmp & 0x0040);
1202 stat.for_ampdu = !!(tmp & 0x0020);
1203 stat.acked = !!(tmp & 0x0002);
1204
1205 b43_handle_txstatus(dev, &stat);
1206 }
1207}
1208
1209static void drain_txstatus_queue(struct b43_wldev *dev)
1210{
1211 u32 dummy;
1212
1213 if (dev->dev->id.revision < 5)
1214 return;
1215 /* Read all entries from the microcode TXstatus FIFO
1216 * and throw them away.
1217 */
1218 while (1) {
1219 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1220 if (!(dummy & 0x00000001))
1221 break;
1222 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1223 }
1224}
1225
1226static u32 b43_jssi_read(struct b43_wldev *dev)
1227{
1228 u32 val = 0;
1229
1230 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1231 val <<= 16;
1232 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1233
1234 return val;
1235}
1236
1237static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1238{
1239 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1240 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1241}
1242
1243static void b43_generate_noise_sample(struct b43_wldev *dev)
1244{
1245 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1246 b43_write32(dev, B43_MMIO_MACCMD,
1247 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1248}
1249
1250static void b43_calculate_link_quality(struct b43_wldev *dev)
1251{
1252 /* Top half of Link Quality calculation. */
1253
ef1a628d
MB		 1254 if (dev->phy.type != B43_PHYTYPE_G)
1255 return;
e4d6b795
MB		 1256 if (dev->noisecalc.calculation_running)
1257 return;
e4d6b795
MB		 1258 dev->noisecalc.calculation_running = 1;
1259 dev->noisecalc.nr_samples = 0;
1260
1261 b43_generate_noise_sample(dev);
1262}
1263
1264static void handle_irq_noise(struct b43_wldev *dev)
1265{
ef1a628d 1266 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1267 u16 tmp;
1268 u8 noise[4];
1269 u8 i, j;
1270 s32 average;
1271
1272 /* Bottom half of Link Quality calculation. */
1273
ef1a628d
MB		 1274 if (dev->phy.type != B43_PHYTYPE_G)
1275 return;
1276
98a3b2fe
MB		 1277 /* Possible race condition: It might be possible that the user
1278 * changed to a different channel in the meantime since we
1279 * started the calculation. We ignore that fact, since it's
1280 * not really that much of a problem. The background noise is
1281 * an estimation only anyway. Slightly wrong results will get damped
1282 * by the averaging of the 8 sample rounds. Additionally the
1283 * value is shortlived. So it will be replaced by the next noise
1284 * calculation round soon. */
1285
e4d6b795 1286 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1287 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1288 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1289 noise[2] == 0x7F || noise[3] == 0x7F)
1290 goto generate_new;
1291
1292 /* Get the noise samples. */
1293 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1294 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1295 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1296 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1297 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1298 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1299 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1300 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1301 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1302 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1303 dev->noisecalc.nr_samples++;
1304 if (dev->noisecalc.nr_samples == 8) {
1305 /* Calculate the Link Quality by the noise samples. */
1306 average = 0;
1307 for (i = 0; i < 8; i++) {
1308 for (j = 0; j < 4; j++)
1309 average += dev->noisecalc.samples[i][j];
1310 }
1311 average /= (8 * 4);
1312 average *= 125;
1313 average += 64;
1314 average /= 128;
1315 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1316 tmp = (tmp / 128) & 0x1F;
1317 if (tmp >= 8)
1318 average += 2;
1319 else
1320 average -= 25;
1321 if (tmp == 8)
1322 average -= 72;
1323 else
1324 average -= 48;
1325
1326 dev->stats.link_noise = average;
e4d6b795
MB		 1327 dev->noisecalc.calculation_running = 0;
1328 return;
1329 }
98a3b2fe 1330generate_new:
e4d6b795
MB		 1331 b43_generate_noise_sample(dev);
1332}
1333
1334static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1335{
05c914fe 1336 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1337 ///TODO: PS TBTT
1338 } else {
1339 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1340 b43_power_saving_ctl_bits(dev, 0);
1341 }
05c914fe 1342 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1343 dev->dfq_valid = 1;
e4d6b795
MB		 1344}
1345
1346static void handle_irq_atim_end(struct b43_wldev *dev)
1347{
aa6c7ae2
MB		 1348 if (dev->dfq_valid) {
1349 b43_write32(dev, B43_MMIO_MACCMD,
1350 b43_read32(dev, B43_MMIO_MACCMD)
1351 | B43_MACCMD_DFQ_VALID);
1352 dev->dfq_valid = 0;
1353 }
e4d6b795
MB		 1354}
1355
1356static void handle_irq_pmq(struct b43_wldev *dev)
1357{
1358 u32 tmp;
1359
1360 //TODO: AP mode.
1361
1362 while (1) {
1363 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1364 if (!(tmp & 0x00000008))
1365 break;
1366 }
1367 /* 16bit write is odd, but correct. */
1368 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1369}
1370
1371static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1372 const u8 *data, u16 size,
e4d6b795
MB		 1373 u16 ram_offset,
1374 u16 shm_size_offset, u8 rate)
1375{
1376 u32 i, tmp;
1377 struct b43_plcp_hdr4 plcp;
1378
1379 plcp.data = 0;
1380 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1381 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1382 ram_offset += sizeof(u32);
1383 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1384 * So leave the first two bytes of the next write blank.
1385 */
1386 tmp = (u32) (data[0]) << 16;
1387 tmp |= (u32) (data[1]) << 24;
1388 b43_ram_write(dev, ram_offset, tmp);
1389 ram_offset += sizeof(u32);
1390 for (i = 2; i < size; i += sizeof(u32)) {
1391 tmp = (u32) (data[i + 0]);
1392 if (i + 1 < size)
1393 tmp |= (u32) (data[i + 1]) << 8;
1394 if (i + 2 < size)
1395 tmp |= (u32) (data[i + 2]) << 16;
1396 if (i + 3 < size)
1397 tmp |= (u32) (data[i + 3]) << 24;
1398 b43_ram_write(dev, ram_offset + i - 2, tmp);
1399 }
1400 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1401 size + sizeof(struct b43_plcp_hdr6));
1402}
1403
5042c507
MB		 1404/* Check if the use of the antenna that ieee80211 told us to
1405 * use is possible. This will fall back to DEFAULT.
1406 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1407u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1408 u8 antenna_nr)
1409{
1410 u8 antenna_mask;
1411
1412 if (antenna_nr == 0) {
1413 /* Zero means "use default antenna". That's always OK. */
1414 return 0;
1415 }
1416
1417 /* Get the mask of available antennas. */
1418 if (dev->phy.gmode)
1419 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1420 else
1421 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1422
1423 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1424 /* This antenna is not available. Fall back to default. */
1425 return 0;
1426 }
1427
1428 return antenna_nr;
1429}
1430
5042c507
MB		 1431/* Convert a b43 antenna number value to the PHY TX control value. */
1432static u16 b43_antenna_to_phyctl(int antenna)
1433{
1434 switch (antenna) {
1435 case B43_ANTENNA0:
1436 return B43_TXH_PHY_ANT0;
1437 case B43_ANTENNA1:
1438 return B43_TXH_PHY_ANT1;
1439 case B43_ANTENNA2:
1440 return B43_TXH_PHY_ANT2;
1441 case B43_ANTENNA3:
1442 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1443 case B43_ANTENNA_AUTO0:
1444 case B43_ANTENNA_AUTO1:
5042c507
MB		 1445 return B43_TXH_PHY_ANT01AUTO;
1446 }
1447 B43_WARN_ON(1);
1448 return 0;
1449}
1450
e4d6b795
MB		 1451static void b43_write_beacon_template(struct b43_wldev *dev,
1452 u16 ram_offset,
5042c507 1453 u16 shm_size_offset)
e4d6b795 1454{
47f76ca3 1455 unsigned int i, len, variable_len;
e66fee6a
MB		 1456 const struct ieee80211_mgmt *bcn;
1457 const u8 *ie;
1458 bool tim_found = 0;
5042c507
MB		 1459 unsigned int rate;
1460 u16 ctl;
1461 int antenna;
e039fa4a 1462 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1463
e66fee6a
MB		 1464 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1465 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1466 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1467 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1468
1469 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1470 len, ram_offset, shm_size_offset, rate);
e66fee6a 1471
5042c507 1472 /* Write the PHY TX control parameters. */
0f4ac38b 1473 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1474 antenna = b43_antenna_to_phyctl(antenna);
1475 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1476 /* We can't send beacons with short preamble. Would get PHY errors. */
1477 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1478 ctl &= ~B43_TXH_PHY_ANT;
1479 ctl &= ~B43_TXH_PHY_ENC;
1480 ctl |= antenna;
1481 if (b43_is_cck_rate(rate))
1482 ctl |= B43_TXH_PHY_ENC_CCK;
1483 else
1484 ctl |= B43_TXH_PHY_ENC_OFDM;
1485 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1486
e66fee6a
MB		 1487 /* Find the position of the TIM and the DTIM_period value
1488 * and write them to SHM. */
1489 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1490 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1491 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1492 uint8_t ie_id, ie_len;
1493
1494 ie_id = ie[i];
1495 ie_len = ie[i + 1];
1496 if (ie_id == 5) {
1497 u16 tim_position;
1498 u16 dtim_period;
1499 /* This is the TIM Information Element */
1500
1501 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1502 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1503 break;
1504 /* A valid TIM is at least 4 bytes long. */
1505 if (ie_len < 4)
1506 break;
1507 tim_found = 1;
1508
1509 tim_position = sizeof(struct b43_plcp_hdr6);
1510 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1511 tim_position += i;
1512
1513 dtim_period = ie[i + 3];
1514
1515 b43_shm_write16(dev, B43_SHM_SHARED,
1516 B43_SHM_SH_TIMBPOS, tim_position);
1517 b43_shm_write16(dev, B43_SHM_SHARED,
1518 B43_SHM_SH_DTIMPER, dtim_period);
1519 break;
1520 }
1521 i += ie_len + 2;
1522 }
1523 if (!tim_found) {
04dea136
JB		 1524 /*
1525 * If ucode wants to modify TIM do it behind the beacon, this
1526 * will happen, for example, when doing mesh networking.
1527 */
1528 b43_shm_write16(dev, B43_SHM_SHARED,
1529 B43_SHM_SH_TIMBPOS,
1530 len + sizeof(struct b43_plcp_hdr6));
1531 b43_shm_write16(dev, B43_SHM_SHARED,
1532 B43_SHM_SH_DTIMPER, 0);
1533 }
1534 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1535}
1536
6b4bec01
MB		 1537static void b43_upload_beacon0(struct b43_wldev *dev)
1538{
1539 struct b43_wl *wl = dev->wl;
1540
1541 if (wl->beacon0_uploaded)
1542 return;
1543 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1544 wl->beacon0_uploaded = 1;
1545}
1546
1547static void b43_upload_beacon1(struct b43_wldev *dev)
1548{
1549 struct b43_wl *wl = dev->wl;
1550
1551 if (wl->beacon1_uploaded)
1552 return;
1553 b43_write_beacon_template(dev, 0x468, 0x1A);
1554 wl->beacon1_uploaded = 1;
1555}
1556
c97a4ccc
MB		 1557static void handle_irq_beacon(struct b43_wldev *dev)
1558{
1559 struct b43_wl *wl = dev->wl;
1560 u32 cmd, beacon0_valid, beacon1_valid;
1561
05c914fe
JB		 1562 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1563 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1564 return;
1565
1566 /* This is the bottom half of the asynchronous beacon update. */
1567
1568 /* Ignore interrupt in the future. */
13790728 1569 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1570
1571 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1572 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1573 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1574
1575 /* Schedule interrupt manually, if busy. */
1576 if (beacon0_valid && beacon1_valid) {
1577 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1578 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1579 return;
1580 }
1581
6b4bec01
MB		 1582 if (unlikely(wl->beacon_templates_virgin)) {
1583 /* We never uploaded a beacon before.
1584 * Upload both templates now, but only mark one valid. */
1585 wl->beacon_templates_virgin = 0;
1586 b43_upload_beacon0(dev);
1587 b43_upload_beacon1(dev);
c97a4ccc
MB		 1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 cmd |= B43_MACCMD_BEACON0_VALID;
1590 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1591 } else {
1592 if (!beacon0_valid) {
1593 b43_upload_beacon0(dev);
1594 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1595 cmd |= B43_MACCMD_BEACON0_VALID;
1596 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1597 } else if (!beacon1_valid) {
1598 b43_upload_beacon1(dev);
1599 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1600 cmd |= B43_MACCMD_BEACON1_VALID;
1601 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1602 }
c97a4ccc
MB		 1603 }
1604}
1605
36dbd954
MB		 1606static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1607{
1608 u32 old_irq_mask = dev->irq_mask;
1609
1610 /* update beacon right away or defer to irq */
1611 handle_irq_beacon(dev);
1612 if (old_irq_mask != dev->irq_mask) {
1613 /* The handler updated the IRQ mask. */
1614 B43_WARN_ON(!dev->irq_mask);
1615 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1616 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1617 } else {
1618 /* Device interrupts are currently disabled. That means
1619 * we just ran the hardirq handler and scheduled the
1620 * IRQ thread. The thread will write the IRQ mask when
1621 * it finished, so there's nothing to do here. Writing
1622 * the mask _here_ would incorrectly re-enable IRQs. */
1623 }
1624 }
1625}
1626
a82d9922
MB		 1627static void b43_beacon_update_trigger_work(struct work_struct *work)
1628{
1629 struct b43_wl *wl = container_of(work, struct b43_wl,
1630 beacon_update_trigger);
1631 struct b43_wldev *dev;
1632
1633 mutex_lock(&wl->mutex);
1634 dev = wl->current_dev;
1635 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
36dbd954
MB		 1636 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
1637 /* wl->mutex is enough. */
1638 b43_do_beacon_update_trigger_work(dev);
1639 mmiowb();
1640 } else {
1641 spin_lock_irq(&wl->hardirq_lock);
1642 b43_do_beacon_update_trigger_work(dev);
1643 mmiowb();
1644 spin_unlock_irq(&wl->hardirq_lock);
1645 }
a82d9922
MB		 1646 }
1647 mutex_unlock(&wl->mutex);
1648}
1649
d4df6f1a 1650/* Asynchronously update the packet templates in template RAM.
36dbd954 1651 * Locking: Requires wl->mutex to be locked. */
9d139c81 1652static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1653{
9d139c81
JB		 1654 struct sk_buff *beacon;
1655
e66fee6a
MB		 1656 /* This is the top half of the ansynchronous beacon update.
1657 * The bottom half is the beacon IRQ.
1658 * Beacon update must be asynchronous to avoid sending an
1659 * invalid beacon. This can happen for example, if the firmware
1660 * transmits a beacon while we are updating it. */
e4d6b795 1661
9d139c81
JB		 1662 /* We could modify the existing beacon and set the aid bit in
1663 * the TIM field, but that would probably require resizing and
1664 * moving of data within the beacon template.
1665 * Simply request a new beacon and let mac80211 do the hard work. */
1666 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1667 if (unlikely(!beacon))
1668 return;
1669
e66fee6a
MB		 1670 if (wl->current_beacon)
1671 dev_kfree_skb_any(wl->current_beacon);
1672 wl->current_beacon = beacon;
1673 wl->beacon0_uploaded = 0;
1674 wl->beacon1_uploaded = 0;
42935eca 1675 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1676}
1677
e4d6b795
MB		 1678static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1679{
1680 b43_time_lock(dev);
1681 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1682 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1683 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1684 } else {
1685 b43_write16(dev, 0x606, (beacon_int >> 6));
1686 b43_write16(dev, 0x610, beacon_int);
1687 }
1688 b43_time_unlock(dev);
a82d9922 1689 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1690}
1691
afa83e23
MB		 1692static void b43_handle_firmware_panic(struct b43_wldev *dev)
1693{
1694 u16 reason;
1695
1696 /* Read the register that contains the reason code for the panic. */
1697 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1698 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1699
1700 switch (reason) {
1701 default:
1702 b43dbg(dev->wl, "The panic reason is unknown.\n");
1703 /* fallthrough */
1704 case B43_FWPANIC_DIE:
1705 /* Do not restart the controller or firmware.
1706 * The device is nonfunctional from now on.
1707 * Restarting would result in this panic to trigger again,
1708 * so we avoid that recursion. */
1709 break;
1710 case B43_FWPANIC_RESTART:
1711 b43_controller_restart(dev, "Microcode panic");
1712 break;
1713 }
1714}
1715
e4d6b795
MB		 1716static void handle_irq_ucode_debug(struct b43_wldev *dev)
1717{
e48b0eeb 1718 unsigned int i, cnt;
53c06856 1719 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1720 __le16 *buf;
1721
1722 /* The proprietary firmware doesn't have this IRQ. */
1723 if (!dev->fw.opensource)
1724 return;
1725
afa83e23
MB		 1726 /* Read the register that contains the reason code for this IRQ. */
1727 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1728
e48b0eeb
MB		 1729 switch (reason) {
1730 case B43_DEBUGIRQ_PANIC:
afa83e23 1731 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1732 break;
1733 case B43_DEBUGIRQ_DUMP_SHM:
1734 if (!B43_DEBUG)
1735 break; /* Only with driver debugging enabled. */
1736 buf = kmalloc(4096, GFP_ATOMIC);
1737 if (!buf) {
1738 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1739 goto out;
1740 }
1741 for (i = 0; i < 4096; i += 2) {
1742 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1743 buf[i / 2] = cpu_to_le16(tmp);
1744 }
1745 b43info(dev->wl, "Shared memory dump:\n");
1746 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1747 16, 2, buf, 4096, 1);
1748 kfree(buf);
1749 break;
1750 case B43_DEBUGIRQ_DUMP_REGS:
1751 if (!B43_DEBUG)
1752 break; /* Only with driver debugging enabled. */
1753 b43info(dev->wl, "Microcode register dump:\n");
1754 for (i = 0, cnt = 0; i < 64; i++) {
1755 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1756 if (cnt == 0)
1757 printk(KERN_INFO);
1758 printk("r%02u: 0x%04X ", i, tmp);
1759 cnt++;
1760 if (cnt == 6) {
1761 printk("\n");
1762 cnt = 0;
1763 }
1764 }
1765 printk("\n");
1766 break;
53c06856
MB		 1767 case B43_DEBUGIRQ_MARKER:
1768 if (!B43_DEBUG)
1769 break; /* Only with driver debugging enabled. */
1770 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1771 B43_MARKER_ID_REG);
1772 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1773 B43_MARKER_LINE_REG);
1774 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1775 "at line number %u\n",
1776 marker_id, marker_line);
1777 break;
e48b0eeb
MB		 1778 default:
1779 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1780 reason);
1781 }
1782out:
afa83e23
MB		 1783 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1784 b43_shm_write16(dev, B43_SHM_SCRATCH,
1785 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1786}
1787
36dbd954 1788static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1789{
1790 u32 reason;
1791 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1792 u32 merged_dma_reason = 0;
21954c36 1793 int i;
e4d6b795 1794
36dbd954
MB		 1795 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1796 return;
e4d6b795
MB		 1797
1798 reason = dev->irq_reason;
1799 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1800 dma_reason[i] = dev->dma_reason[i];
1801 merged_dma_reason |= dma_reason[i];
1802 }
1803
1804 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1805 b43err(dev->wl, "MAC transmission error\n");
1806
00e0b8cb 1807 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1808 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1809 rmb();
1810 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1811 atomic_set(&dev->phy.txerr_cnt,
1812 B43_PHY_TX_BADNESS_LIMIT);
1813 b43err(dev->wl, "Too many PHY TX errors, "
1814 "restarting the controller\n");
1815 b43_controller_restart(dev, "PHY TX errors");
1816 }
1817 }
e4d6b795
MB		 1818
1819 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1820 B43_DMAIRQ_NONFATALMASK))) {
1821 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1822 b43err(dev->wl, "Fatal DMA error: "
1823 "0x%08X, 0x%08X, 0x%08X, "
1824 "0x%08X, 0x%08X, 0x%08X\n",
1825 dma_reason[0], dma_reason[1],
1826 dma_reason[2], dma_reason[3],
1827 dma_reason[4], dma_reason[5]);
1828 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1829 return;
1830 }
1831 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1832 b43err(dev->wl, "DMA error: "
1833 "0x%08X, 0x%08X, 0x%08X, "
1834 "0x%08X, 0x%08X, 0x%08X\n",
1835 dma_reason[0], dma_reason[1],
1836 dma_reason[2], dma_reason[3],
1837 dma_reason[4], dma_reason[5]);
1838 }
1839 }
1840
1841 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1842 handle_irq_ucode_debug(dev);
1843 if (reason & B43_IRQ_TBTT_INDI)
1844 handle_irq_tbtt_indication(dev);
1845 if (reason & B43_IRQ_ATIM_END)
1846 handle_irq_atim_end(dev);
1847 if (reason & B43_IRQ_BEACON)
1848 handle_irq_beacon(dev);
1849 if (reason & B43_IRQ_PMQ)
1850 handle_irq_pmq(dev);
21954c36
MB		 1851 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1852 ;/* TODO */
1853 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1854 handle_irq_noise(dev);
1855
1856 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1857 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1858 if (b43_using_pio_transfers(dev))
1859 b43_pio_rx(dev->pio.rx_queue);
1860 else
1861 b43_dma_rx(dev->dma.rx_ring);
1862 }
e4d6b795
MB		 1863 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1864 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1865 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1866 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1867 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1868
21954c36 1869 if (reason & B43_IRQ_TX_OK)
e4d6b795 1870 handle_irq_transmit_status(dev);
e4d6b795 1871
36dbd954 1872 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1873 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1874}
1875
36dbd954
MB		 1876/* Interrupt thread handler. Handles device interrupts in thread context. */
1877static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1878{
36dbd954 1879 struct b43_wldev *dev = dev_id;
e4d6b795 1880
36dbd954
MB		 1881 mutex_lock(&dev->wl->mutex);
1882 b43_do_interrupt_thread(dev);
1883 mmiowb();
1884 mutex_unlock(&dev->wl->mutex);
1885
1886 return IRQ_HANDLED;
e4d6b795
MB		 1887}
1888
36dbd954 1889static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1890{
e4d6b795
MB		 1891 u32 reason;
1892
36dbd954
MB		 1893 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1894 * On SDIO, this runs under wl->mutex. */
e4d6b795 1895
e4d6b795
MB		 1896 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1897 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1898 return IRQ_NONE;
13790728 1899 reason &= dev->irq_mask;
e4d6b795 1900 if (!reason)
36dbd954 1901 return IRQ_HANDLED;
e4d6b795
MB		 1902
1903 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1904 & 0x0001DC00;
1905 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1906 & 0x0000DC00;
1907 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1908 & 0x0000DC00;
1909 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1910 & 0x0001DC00;
1911 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1912 & 0x0000DC00;
13790728 1913/* Unused ring
e4d6b795
MB		 1914 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1915 & 0x0000DC00;
13790728 1916*/
e4d6b795 1917
36dbd954
MB		 1918 /* ACK the interrupt. */
1919 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1920 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1921 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1922 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1923 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1924 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1925/* Unused ring
1926 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1927*/
1928
1929 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 1930 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 1931 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 1932 dev->irq_reason = reason;
36dbd954
MB		 1933
1934 return IRQ_WAKE_THREAD;
1935}
1936
1937/* Interrupt handler top-half. This runs with interrupts disabled. */
1938static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1939{
1940 struct b43_wldev *dev = dev_id;
1941 irqreturn_t ret;
1942
1943 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1944 return IRQ_NONE;
1945
1946 spin_lock(&dev->wl->hardirq_lock);
1947 ret = b43_do_interrupt(dev);
e4d6b795 1948 mmiowb();
36dbd954 1949 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 1950
1951 return ret;
1952}
1953
1a9f5093 1954void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1955{
1956 release_firmware(fw->data);
1957 fw->data = NULL;
1958 fw->filename = NULL;
1959}
1960
e4d6b795
MB		 1961static void b43_release_firmware(struct b43_wldev *dev)
1962{
1a9f5093
MB		 1963 b43_do_release_fw(&dev->fw.ucode);
1964 b43_do_release_fw(&dev->fw.pcm);
1965 b43_do_release_fw(&dev->fw.initvals);
1966 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1967}
1968
eb189d8b 1969static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1970{
fc68ed4f
HE		 1971 const char text[] =
1972 "You must go to " \
1973 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1974 "and download the correct firmware for this driver version. " \
1975 "Please carefully read all instructions on this website.\n";
eb189d8b 1976
eb189d8b
MB		 1977 if (error)
1978 b43err(wl, text);
1979 else
1980 b43warn(wl, text);
e4d6b795
MB		 1981}
1982
1a9f5093
MB		 1983int b43_do_request_fw(struct b43_request_fw_context *ctx,
1984 const char *name,
1985 struct b43_firmware_file *fw)
e4d6b795 1986{
61cb5dd6 1987 const struct firmware *blob;
e4d6b795
MB		 1988 struct b43_fw_header *hdr;
1989 u32 size;
1990 int err;
1991
61cb5dd6
MB		 1992 if (!name) {
1993 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1994 /* FIXME: We should probably keep it anyway, to save some headache
1995 * on suspend/resume with multiband devices. */
1996 b43_do_release_fw(fw);
e4d6b795 1997 return 0;
61cb5dd6
MB		 1998 }
1999 if (fw->filename) {
1a9f5093
MB		 2000 if ((fw->type == ctx->req_type) &&
2001 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2002 return 0; /* Already have this fw. */
2003 /* Free the cached firmware first. */
1a9f5093
MB		 2004 /* FIXME: We should probably do this later after we successfully
2005 * got the new fw. This could reduce headache with multiband devices.
2006 * We could also redesign this to cache the firmware for all possible
2007 * bands all the time. */
2008 b43_do_release_fw(fw);
61cb5dd6 2009 }
e4d6b795 2010
1a9f5093
MB		 2011 switch (ctx->req_type) {
2012 case B43_FWTYPE_PROPRIETARY:
2013 snprintf(ctx->fwname, sizeof(ctx->fwname),
2014 "b43%s/%s.fw",
2015 modparam_fwpostfix, name);
2016 break;
2017 case B43_FWTYPE_OPENSOURCE:
2018 snprintf(ctx->fwname, sizeof(ctx->fwname),
2019 "b43-open%s/%s.fw",
2020 modparam_fwpostfix, name);
2021 break;
2022 default:
2023 B43_WARN_ON(1);
2024 return -ENOSYS;
2025 }
2026 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2027 if (err == -ENOENT) {
1a9f5093
MB		 2028 snprintf(ctx->errors[ctx->req_type],
2029 sizeof(ctx->errors[ctx->req_type]),
2030 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2031 return err;
2032 } else if (err) {
1a9f5093
MB		 2033 snprintf(ctx->errors[ctx->req_type],
2034 sizeof(ctx->errors[ctx->req_type]),
2035 "Firmware file \"%s\" request failed (err=%d)\n",
2036 ctx->fwname, err);
e4d6b795
MB		 2037 return err;
2038 }
61cb5dd6 2039 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2040 goto err_format;
61cb5dd6 2041 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2042 switch (hdr->type) {
2043 case B43_FW_TYPE_UCODE:
2044 case B43_FW_TYPE_PCM:
2045 size = be32_to_cpu(hdr->size);
61cb5dd6 2046 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2047 goto err_format;
2048 /* fallthrough */
2049 case B43_FW_TYPE_IV:
2050 if (hdr->ver != 1)
2051 goto err_format;
2052 break;
2053 default:
2054 goto err_format;
2055 }
2056
61cb5dd6
MB		 2057 fw->data = blob;
2058 fw->filename = name;
1a9f5093 2059 fw->type = ctx->req_type;
61cb5dd6
MB		 2060
2061 return 0;
e4d6b795
MB		 2062
2063err_format:
1a9f5093
MB		 2064 snprintf(ctx->errors[ctx->req_type],
2065 sizeof(ctx->errors[ctx->req_type]),
2066 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2067 release_firmware(blob);
2068
e4d6b795
MB		 2069 return -EPROTO;
2070}
2071
1a9f5093 2072static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2073{
1a9f5093
MB		 2074 struct b43_wldev *dev = ctx->dev;
2075 struct b43_firmware *fw = &ctx->dev->fw;
2076 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2077 const char *filename;
2078 u32 tmshigh;
2079 int err;
2080
61cb5dd6 2081 /* Get microcode */
e4d6b795 2082 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2083 if ((rev >= 5) && (rev <= 10))
2084 filename = "ucode5";
2085 else if ((rev >= 11) && (rev <= 12))
2086 filename = "ucode11";
759b973b 2087 else if (rev == 13)
61cb5dd6 2088 filename = "ucode13";
759b973b
GS		 2089 else if (rev == 14)
2090 filename = "ucode14";
2091 else if (rev >= 15)
2092 filename = "ucode15";
61cb5dd6
MB		 2093 else
2094 goto err_no_ucode;
1a9f5093 2095 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2096 if (err)
2097 goto err_load;
2098
2099 /* Get PCM code */
2100 if ((rev >= 5) && (rev <= 10))
2101 filename = "pcm5";
2102 else if (rev >= 11)
2103 filename = NULL;
2104 else
2105 goto err_no_pcm;
68217832 2106 fw->pcm_request_failed = 0;
1a9f5093 2107 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2108 if (err == -ENOENT) {
2109 /* We did not find a PCM file? Not fatal, but
2110 * core rev <= 10 must do without hwcrypto then. */
2111 fw->pcm_request_failed = 1;
2112 } else if (err)
61cb5dd6
MB		 2113 goto err_load;
2114
2115 /* Get initvals */
2116 switch (dev->phy.type) {
2117 case B43_PHYTYPE_A:
2118 if ((rev >= 5) && (rev <= 10)) {
2119 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2120 filename = "a0g1initvals5";
2121 else
2122 filename = "a0g0initvals5";
2123 } else
2124 goto err_no_initvals;
2125 break;
2126 case B43_PHYTYPE_G:
e4d6b795 2127 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2128 filename = "b0g0initvals5";
e4d6b795 2129 else if (rev >= 13)
e9304882 2130 filename = "b0g0initvals13";
e4d6b795 2131 else
61cb5dd6
MB		 2132 goto err_no_initvals;
2133 break;
2134 case B43_PHYTYPE_N:
2135 if ((rev >= 11) && (rev <= 12))
2136 filename = "n0initvals11";
2137 else
2138 goto err_no_initvals;
2139 break;
759b973b
GS		 2140 case B43_PHYTYPE_LP:
2141 if (rev == 13)
2142 filename = "lp0initvals13";
2143 else if (rev == 14)
2144 filename = "lp0initvals14";
2145 else if (rev >= 15)
2146 filename = "lp0initvals15";
2147 else
2148 goto err_no_initvals;
2149 break;
61cb5dd6
MB		 2150 default:
2151 goto err_no_initvals;
e4d6b795 2152 }
1a9f5093 2153 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2154 if (err)
2155 goto err_load;
2156
2157 /* Get bandswitch initvals */
2158 switch (dev->phy.type) {
2159 case B43_PHYTYPE_A:
2160 if ((rev >= 5) && (rev <= 10)) {
2161 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2162 filename = "a0g1bsinitvals5";
2163 else
2164 filename = "a0g0bsinitvals5";
2165 } else if (rev >= 11)
2166 filename = NULL;
2167 else
2168 goto err_no_initvals;
2169 break;
2170 case B43_PHYTYPE_G:
e4d6b795 2171 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2172 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2173 else if (rev >= 11)
2174 filename = NULL;
2175 else
e4d6b795 2176 goto err_no_initvals;
61cb5dd6
MB		 2177 break;
2178 case B43_PHYTYPE_N:
2179 if ((rev >= 11) && (rev <= 12))
2180 filename = "n0bsinitvals11";
2181 else
e4d6b795 2182 goto err_no_initvals;
61cb5dd6 2183 break;
759b973b
GS		 2184 case B43_PHYTYPE_LP:
2185 if (rev == 13)
2186 filename = "lp0bsinitvals13";
2187 else if (rev == 14)
2188 filename = "lp0bsinitvals14";
2189 else if (rev >= 15)
2190 filename = "lp0bsinitvals15";
2191 else
2192 goto err_no_initvals;
2193 break;
61cb5dd6
MB		 2194 default:
2195 goto err_no_initvals;
e4d6b795 2196 }
1a9f5093 2197 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2198 if (err)
2199 goto err_load;
e4d6b795
MB		 2200
2201 return 0;
2202
e4d6b795 2203err_no_ucode:
1a9f5093
MB		 2204 err = ctx->fatal_failure = -EOPNOTSUPP;
2205 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2206 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2207 goto error;
2208
2209err_no_pcm:
1a9f5093
MB		 2210 err = ctx->fatal_failure = -EOPNOTSUPP;
2211 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2212 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2213 goto error;
2214
2215err_no_initvals:
1a9f5093
MB		 2216 err = ctx->fatal_failure = -EOPNOTSUPP;
2217 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2218 "is required for your device (wl-core rev %u)\n", rev);
2219 goto error;
2220
2221err_load:
2222 /* We failed to load this firmware image. The error message
2223 * already is in ctx->errors. Return and let our caller decide
2224 * what to do. */
e4d6b795
MB		 2225 goto error;
2226
2227error:
2228 b43_release_firmware(dev);
2229 return err;
2230}
2231
1a9f5093
MB		 2232static int b43_request_firmware(struct b43_wldev *dev)
2233{
2234 struct b43_request_fw_context *ctx;
2235 unsigned int i;
2236 int err;
2237 const char *errmsg;
2238
2239 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2240 if (!ctx)
2241 return -ENOMEM;
2242 ctx->dev = dev;
2243
2244 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2245 err = b43_try_request_fw(ctx);
2246 if (!err)
2247 goto out; /* Successfully loaded it. */
2248 err = ctx->fatal_failure;
2249 if (err)
2250 goto out;
2251
2252 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2253 err = b43_try_request_fw(ctx);
2254 if (!err)
2255 goto out; /* Successfully loaded it. */
2256 err = ctx->fatal_failure;
2257 if (err)
2258 goto out;
2259
2260 /* Could not find a usable firmware. Print the errors. */
2261 for (i = 0; i < B43_NR_FWTYPES; i++) {
2262 errmsg = ctx->errors[i];
2263 if (strlen(errmsg))
2264 b43err(dev->wl, errmsg);
2265 }
2266 b43_print_fw_helptext(dev->wl, 1);
2267 err = -ENOENT;
2268
2269out:
2270 kfree(ctx);
2271 return err;
2272}
2273
e4d6b795
MB		 2274static int b43_upload_microcode(struct b43_wldev *dev)
2275{
2276 const size_t hdr_len = sizeof(struct b43_fw_header);
2277 const __be32 *data;
2278 unsigned int i, len;
2279 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2280 u32 tmp, macctl;
e4d6b795
MB		 2281 int err = 0;
2282
1f7d87b0
MB		 2283 /* Jump the microcode PSM to offset 0 */
2284 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2285 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2286 macctl |= B43_MACCTL_PSM_JMP0;
2287 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2288 /* Zero out all microcode PSM registers and shared memory. */
2289 for (i = 0; i < 64; i++)
2290 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2291 for (i = 0; i < 4096; i += 2)
2292 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2293
e4d6b795 2294 /* Upload Microcode. */
61cb5dd6
MB		 2295 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2296 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2297 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2298 for (i = 0; i < len; i++) {
2299 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2300 udelay(10);
2301 }
2302
61cb5dd6 2303 if (dev->fw.pcm.data) {
e4d6b795 2304 /* Upload PCM data. */
61cb5dd6
MB		 2305 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2306 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2307 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2308 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2309 /* No need for autoinc bit in SHM_HW */
2310 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2311 for (i = 0; i < len; i++) {
2312 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2313 udelay(10);
2314 }
2315 }
2316
2317 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2318
2319 /* Start the microcode PSM */
2320 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2321 macctl &= ~B43_MACCTL_PSM_JMP0;
2322 macctl |= B43_MACCTL_PSM_RUN;
2323 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2324
2325 /* Wait for the microcode to load and respond */
2326 i = 0;
2327 while (1) {
2328 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2329 if (tmp == B43_IRQ_MAC_SUSPENDED)
2330 break;
2331 i++;
1f7d87b0 2332 if (i >= 20) {
e4d6b795 2333 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2334 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2335 err = -ENODEV;
1f7d87b0
MB		 2336 goto error;
2337 }
2338 msleep_interruptible(50);
2339 if (signal_pending(current)) {
2340 err = -EINTR;
2341 goto error;
e4d6b795 2342 }
e4d6b795
MB		 2343 }
2344 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2345
2346 /* Get and check the revisions. */
2347 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2348 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2349 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2350 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2351
2352 if (fwrev <= 0x128) {
2353 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2354 "binary drivers older than version 4.x is unsupported. "
2355 "You must upgrade your firmware files.\n");
eb189d8b 2356 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2357 err = -EOPNOTSUPP;
1f7d87b0 2358 goto error;
e4d6b795 2359 }
e4d6b795
MB		 2360 dev->fw.rev = fwrev;
2361 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2362 dev->fw.opensource = (fwdate == 0xFFFF);
2363
403a3a13
MB		 2364 /* Default to use-all-queues. */
2365 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2366 dev->qos_enabled = !!modparam_qos;
2367 /* Default to firmware/hardware crypto acceleration. */
2368 dev->hwcrypto_enabled = 1;
2369
e48b0eeb 2370 if (dev->fw.opensource) {
403a3a13
MB		 2371 u16 fwcapa;
2372
e48b0eeb
MB		 2373 /* Patchlevel info is encoded in the "time" field. */
2374 dev->fw.patch = fwtime;
403a3a13
MB		 2375 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2376 dev->fw.rev, dev->fw.patch);
2377
2378 fwcapa = b43_fwcapa_read(dev);
2379 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2380 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2381 /* Disable hardware crypto and fall back to software crypto. */
2382 dev->hwcrypto_enabled = 0;
2383 }
2384 if (!(fwcapa & B43_FWCAPA_QOS)) {
2385 b43info(dev->wl, "QoS not supported by firmware\n");
2386 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2387 * ieee80211_unregister to make sure the networking core can
2388 * properly free possible resources. */
2389 dev->wl->hw->queues = 1;
2390 dev->qos_enabled = 0;
2391 }
e48b0eeb
MB		 2392 } else {
2393 b43info(dev->wl, "Loading firmware version %u.%u "
2394 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2395 fwrev, fwpatch,
2396 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2397 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2398 if (dev->fw.pcm_request_failed) {
2399 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2400 "Hardware accelerated cryptography is disabled.\n");
2401 b43_print_fw_helptext(dev->wl, 0);
2402 }
e48b0eeb 2403 }
e4d6b795 2404
eb189d8b 2405 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2406 /* We're over the deadline, but we keep support for old fw
2407 * until it turns out to be in major conflict with something new. */
eb189d8b 2408 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2409 "Support for old firmware will be removed soon "
2410 "(official deadline was July 2008).\n");
eb189d8b
MB		 2411 b43_print_fw_helptext(dev->wl, 0);
2412 }
2413
1f7d87b0
MB		 2414 return 0;
2415
2416error:
2417 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2418 macctl &= ~B43_MACCTL_PSM_RUN;
2419 macctl |= B43_MACCTL_PSM_JMP0;
2420 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2421
e4d6b795
MB		 2422 return err;
2423}
2424
2425static int b43_write_initvals(struct b43_wldev *dev,
2426 const struct b43_iv *ivals,
2427 size_t count,
2428 size_t array_size)
2429{
2430 const struct b43_iv *iv;
2431 u16 offset;
2432 size_t i;
2433 bool bit32;
2434
2435 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2436 iv = ivals;
2437 for (i = 0; i < count; i++) {
2438 if (array_size < sizeof(iv->offset_size))
2439 goto err_format;
2440 array_size -= sizeof(iv->offset_size);
2441 offset = be16_to_cpu(iv->offset_size);
2442 bit32 = !!(offset & B43_IV_32BIT);
2443 offset &= B43_IV_OFFSET_MASK;
2444 if (offset >= 0x1000)
2445 goto err_format;
2446 if (bit32) {
2447 u32 value;
2448
2449 if (array_size < sizeof(iv->data.d32))
2450 goto err_format;
2451 array_size -= sizeof(iv->data.d32);
2452
533dd1b0 2453 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2454 b43_write32(dev, offset, value);
2455
2456 iv = (const struct b43_iv *)((const uint8_t *)iv +
2457 sizeof(__be16) +
2458 sizeof(__be32));
2459 } else {
2460 u16 value;
2461
2462 if (array_size < sizeof(iv->data.d16))
2463 goto err_format;
2464 array_size -= sizeof(iv->data.d16);
2465
2466 value = be16_to_cpu(iv->data.d16);
2467 b43_write16(dev, offset, value);
2468
2469 iv = (const struct b43_iv *)((const uint8_t *)iv +
2470 sizeof(__be16) +
2471 sizeof(__be16));
2472 }
2473 }
2474 if (array_size)
2475 goto err_format;
2476
2477 return 0;
2478
2479err_format:
2480 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2481 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2482
2483 return -EPROTO;
2484}
2485
2486static int b43_upload_initvals(struct b43_wldev *dev)
2487{
2488 const size_t hdr_len = sizeof(struct b43_fw_header);
2489 const struct b43_fw_header *hdr;
2490 struct b43_firmware *fw = &dev->fw;
2491 const struct b43_iv *ivals;
2492 size_t count;
2493 int err;
2494
61cb5dd6
MB		 2495 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2496 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2497 count = be32_to_cpu(hdr->size);
2498 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2499 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2500 if (err)
2501 goto out;
61cb5dd6
MB		 2502 if (fw->initvals_band.data) {
2503 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2504 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2505 count = be32_to_cpu(hdr->size);
2506 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2507 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2508 if (err)
2509 goto out;
2510 }
2511out:
2512
2513 return err;
2514}
2515
2516/* Initialize the GPIOs
2517 * http://bcm-specs.sipsolutions.net/GPIO
2518 */
2519static int b43_gpio_init(struct b43_wldev *dev)
2520{
2521 struct ssb_bus *bus = dev->dev->bus;
2522 struct ssb_device *gpiodev, *pcidev = NULL;
2523 u32 mask, set;
2524
2525 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2526 & ~B43_MACCTL_GPOUTSMSK);
2527
e4d6b795
MB		 2528 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2529 | 0x000F);
2530
2531 mask = 0x0000001F;
2532 set = 0x0000000F;
2533 if (dev->dev->bus->chip_id == 0x4301) {
2534 mask |= 0x0060;
2535 set |= 0x0060;
2536 }
2537 if (0 /* FIXME: conditional unknown */ ) {
2538 b43_write16(dev, B43_MMIO_GPIO_MASK,
2539 b43_read16(dev, B43_MMIO_GPIO_MASK)
2540 | 0x0100);
2541 mask |= 0x0180;
2542 set |= 0x0180;
2543 }
95de2841 2544 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2545 b43_write16(dev, B43_MMIO_GPIO_MASK,
2546 b43_read16(dev, B43_MMIO_GPIO_MASK)
2547 | 0x0200);
2548 mask |= 0x0200;
2549 set |= 0x0200;
2550 }
2551 if (dev->dev->id.revision >= 2)
2552 mask |= 0x0010; /* FIXME: This is redundant. */
2553
2554#ifdef CONFIG_SSB_DRIVER_PCICORE
2555 pcidev = bus->pcicore.dev;
2556#endif
2557 gpiodev = bus->chipco.dev ? : pcidev;
2558 if (!gpiodev)
2559 return 0;
2560 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2561 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2562 & mask) | set);
2563
2564 return 0;
2565}
2566
2567/* Turn off all GPIO stuff. Call this on module unload, for example. */
2568static void b43_gpio_cleanup(struct b43_wldev *dev)
2569{
2570 struct ssb_bus *bus = dev->dev->bus;
2571 struct ssb_device *gpiodev, *pcidev = NULL;
2572
2573#ifdef CONFIG_SSB_DRIVER_PCICORE
2574 pcidev = bus->pcicore.dev;
2575#endif
2576 gpiodev = bus->chipco.dev ? : pcidev;
2577 if (!gpiodev)
2578 return;
2579 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2580}
2581
2582/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2583void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2584{
923fd703
MB		 2585 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2586 u16 fwstate;
2587
2588 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2589 B43_SHM_SH_UCODESTAT);
2590 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2591 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2592 b43err(dev->wl, "b43_mac_enable(): The firmware "
2593 "should be suspended, but current state is %u\n",
2594 fwstate);
2595 }
2596 }
2597
e4d6b795
MB		 2598 dev->mac_suspended--;
2599 B43_WARN_ON(dev->mac_suspended < 0);
2600 if (dev->mac_suspended == 0) {
2601 b43_write32(dev, B43_MMIO_MACCTL,
2602 b43_read32(dev, B43_MMIO_MACCTL)
2603 | B43_MACCTL_ENABLED);
2604 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2605 B43_IRQ_MAC_SUSPENDED);
2606 /* Commit writes */
2607 b43_read32(dev, B43_MMIO_MACCTL);
2608 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2609 b43_power_saving_ctl_bits(dev, 0);
2610 }
2611}
2612
2613/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2614void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2615{
2616 int i;
2617 u32 tmp;
2618
05b64b36 2619 might_sleep();
e4d6b795 2620 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2621
e4d6b795
MB		 2622 if (dev->mac_suspended == 0) {
2623 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2624 b43_write32(dev, B43_MMIO_MACCTL,
2625 b43_read32(dev, B43_MMIO_MACCTL)
2626 & ~B43_MACCTL_ENABLED);
2627 /* force pci to flush the write */
2628 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2629 for (i = 35; i; i--) {
2630 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2631 if (tmp & B43_IRQ_MAC_SUSPENDED)
2632 goto out;
2633 udelay(10);
2634 }
2635 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2636 for (i = 40; i; i--) {
e4d6b795
MB		 2637 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2638 if (tmp & B43_IRQ_MAC_SUSPENDED)
2639 goto out;
05b64b36 2640 msleep(1);
e4d6b795
MB		 2641 }
2642 b43err(dev->wl, "MAC suspend failed\n");
2643 }
05b64b36 2644out:
e4d6b795
MB		 2645 dev->mac_suspended++;
2646}
2647
2648static void b43_adjust_opmode(struct b43_wldev *dev)
2649{
2650 struct b43_wl *wl = dev->wl;
2651 u32 ctl;
2652 u16 cfp_pretbtt;
2653
2654 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2655 /* Reset status to STA infrastructure mode. */
2656 ctl &= ~B43_MACCTL_AP;
2657 ctl &= ~B43_MACCTL_KEEP_CTL;
2658 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2659 ctl &= ~B43_MACCTL_KEEP_BAD;
2660 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2661 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2662 ctl |= B43_MACCTL_INFRA;
2663
05c914fe
JB		 2664 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2665 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2666 ctl |= B43_MACCTL_AP;
05c914fe 2667 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2668 ctl &= ~B43_MACCTL_INFRA;
2669
2670 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2671 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2672 if (wl->filter_flags & FIF_FCSFAIL)
2673 ctl |= B43_MACCTL_KEEP_BAD;
2674 if (wl->filter_flags & FIF_PLCPFAIL)
2675 ctl |= B43_MACCTL_KEEP_BADPLCP;
2676 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2677 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2678 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2679 ctl |= B43_MACCTL_BEACPROMISC;
2680
e4d6b795
MB		 2681 /* Workaround: On old hardware the HW-MAC-address-filter
2682 * doesn't work properly, so always run promisc in filter
2683 * it in software. */
2684 if (dev->dev->id.revision <= 4)
2685 ctl |= B43_MACCTL_PROMISC;
2686
2687 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2688
2689 cfp_pretbtt = 2;
2690 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2691 if (dev->dev->bus->chip_id == 0x4306 &&
2692 dev->dev->bus->chip_rev == 3)
2693 cfp_pretbtt = 100;
2694 else
2695 cfp_pretbtt = 50;
2696 }
2697 b43_write16(dev, 0x612, cfp_pretbtt);
2698}
2699
2700static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2701{
2702 u16 offset;
2703
2704 if (is_ofdm) {
2705 offset = 0x480;
2706 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2707 } else {
2708 offset = 0x4C0;
2709 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2710 }
2711 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2712 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2713}
2714
2715static void b43_rate_memory_init(struct b43_wldev *dev)
2716{
2717 switch (dev->phy.type) {
2718 case B43_PHYTYPE_A:
2719 case B43_PHYTYPE_G:
53a6e234 2720 case B43_PHYTYPE_N:
9d86a2d5 2721 case B43_PHYTYPE_LP:
e4d6b795
MB		 2722 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2723 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2724 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2725 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2726 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2727 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2728 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2729 if (dev->phy.type == B43_PHYTYPE_A)
2730 break;
2731 /* fallthrough */
2732 case B43_PHYTYPE_B:
2733 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2734 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2735 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2736 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2737 break;
2738 default:
2739 B43_WARN_ON(1);
2740 }
2741}
2742
5042c507
MB		 2743/* Set the default values for the PHY TX Control Words. */
2744static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2745{
2746 u16 ctl = 0;
2747
2748 ctl |= B43_TXH_PHY_ENC_CCK;
2749 ctl |= B43_TXH_PHY_ANT01AUTO;
2750 ctl |= B43_TXH_PHY_TXPWR;
2751
2752 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2753 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2754 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2755}
2756
e4d6b795
MB		 2757/* Set the TX-Antenna for management frames sent by firmware. */
2758static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2759{
5042c507 2760 u16 ant;
e4d6b795
MB		 2761 u16 tmp;
2762
5042c507 2763 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2764
e4d6b795
MB		 2765 /* For ACK/CTS */
2766 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2767 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2768 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2769 /* For Probe Resposes */
2770 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2771 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2772 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2773}
2774
2775/* This is the opposite of b43_chip_init() */
2776static void b43_chip_exit(struct b43_wldev *dev)
2777{
fb11137a 2778 b43_phy_exit(dev);
e4d6b795
MB		 2779 b43_gpio_cleanup(dev);
2780 /* firmware is released later */
2781}
2782
2783/* Initialize the chip
2784 * http://bcm-specs.sipsolutions.net/ChipInit
2785 */
2786static int b43_chip_init(struct b43_wldev *dev)
2787{
2788 struct b43_phy *phy = &dev->phy;
ef1a628d 2789 int err;
1f7d87b0 2790 u32 value32, macctl;
e4d6b795
MB		 2791 u16 value16;
2792
1f7d87b0
MB		 2793 /* Initialize the MAC control */
2794 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2795 if (dev->phy.gmode)
2796 macctl |= B43_MACCTL_GMODE;
2797 macctl |= B43_MACCTL_INFRA;
2798 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2799
2800 err = b43_request_firmware(dev);
2801 if (err)
2802 goto out;
2803 err = b43_upload_microcode(dev);
2804 if (err)
2805 goto out; /* firmware is released later */
2806
2807 err = b43_gpio_init(dev);
2808 if (err)
2809 goto out; /* firmware is released later */
21954c36 2810
e4d6b795
MB		 2811 err = b43_upload_initvals(dev);
2812 if (err)
1a8d1227 2813 goto err_gpio_clean;
e4d6b795 2814
0b7dcd96
MB		 2815 /* Turn the Analog on and initialize the PHY. */
2816 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2817 err = b43_phy_init(dev);
2818 if (err)
ef1a628d 2819 goto err_gpio_clean;
e4d6b795 2820
ef1a628d
MB		 2821 /* Disable Interference Mitigation. */
2822 if (phy->ops->interf_mitigation)
2823 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2824
ef1a628d
MB		 2825 /* Select the antennae */
2826 if (phy->ops->set_rx_antenna)
2827 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2828 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2829
2830 if (phy->type == B43_PHYTYPE_B) {
2831 value16 = b43_read16(dev, 0x005E);
2832 value16 |= 0x0004;
2833 b43_write16(dev, 0x005E, value16);
2834 }
2835 b43_write32(dev, 0x0100, 0x01000000);
2836 if (dev->dev->id.revision < 5)
2837 b43_write32(dev, 0x010C, 0x01000000);
2838
2839 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2840 & ~B43_MACCTL_INFRA);
2841 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2842 | B43_MACCTL_INFRA);
e4d6b795 2843
e4d6b795
MB		 2844 /* Probe Response Timeout value */
2845 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2846 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2847
2848 /* Initially set the wireless operation mode. */
2849 b43_adjust_opmode(dev);
2850
2851 if (dev->dev->id.revision < 3) {
2852 b43_write16(dev, 0x060E, 0x0000);
2853 b43_write16(dev, 0x0610, 0x8000);
2854 b43_write16(dev, 0x0604, 0x0000);
2855 b43_write16(dev, 0x0606, 0x0200);
2856 } else {
2857 b43_write32(dev, 0x0188, 0x80000000);
2858 b43_write32(dev, 0x018C, 0x02000000);
2859 }
2860 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2861 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2862 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2863 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2864 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2865 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2866 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2867
2868 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2869 value32 |= 0x00100000;
2870 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2871
2872 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2873 dev->dev->bus->chipco.fast_pwrup_delay);
2874
2875 err = 0;
2876 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2877out:
e4d6b795
MB		 2878 return err;
2879
1a8d1227 2880err_gpio_clean:
e4d6b795 2881 b43_gpio_cleanup(dev);
21954c36 2882 return err;
e4d6b795
MB		 2883}
2884
e4d6b795
MB		 2885static void b43_periodic_every60sec(struct b43_wldev *dev)
2886{
ef1a628d 2887 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2888
ef1a628d
MB		 2889 if (ops->pwork_60sec)
2890 ops->pwork_60sec(dev);
18c8adeb
MB		 2891
2892 /* Force check the TX power emission now. */
2893 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2894}
2895
2896static void b43_periodic_every30sec(struct b43_wldev *dev)
2897{
2898 /* Update device statistics. */
2899 b43_calculate_link_quality(dev);
2900}
2901
2902static void b43_periodic_every15sec(struct b43_wldev *dev)
2903{
2904 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2905 u16 wdr;
2906
2907 if (dev->fw.opensource) {
2908 /* Check if the firmware is still alive.
2909 * It will reset the watchdog counter to 0 in its idle loop. */
2910 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2911 if (unlikely(wdr)) {
2912 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2913 b43_controller_restart(dev, "Firmware watchdog");
2914 return;
2915 } else {
2916 b43_shm_write16(dev, B43_SHM_SCRATCH,
2917 B43_WATCHDOG_REG, 1);
2918 }
2919 }
e4d6b795 2920
ef1a628d
MB		 2921 if (phy->ops->pwork_15sec)
2922 phy->ops->pwork_15sec(dev);
2923
00e0b8cb
SB		 2924 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2925 wmb();
e4d6b795
MB		 2926}
2927
e4d6b795
MB		 2928static void do_periodic_work(struct b43_wldev *dev)
2929{
2930 unsigned int state;
2931
2932 state = dev->periodic_state;
42bb4cd5 2933 if (state % 4 == 0)
e4d6b795 2934 b43_periodic_every60sec(dev);
42bb4cd5 2935 if (state % 2 == 0)
e4d6b795 2936 b43_periodic_every30sec(dev);
42bb4cd5 2937 b43_periodic_every15sec(dev);
e4d6b795
MB		 2938}
2939
05b64b36
MB		 2940/* Periodic work locking policy:
2941 * The whole periodic work handler is protected by
2942 * wl->mutex. If another lock is needed somewhere in the
2943 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2944 */
e4d6b795
MB		 2945static void b43_periodic_work_handler(struct work_struct *work)
2946{
05b64b36
MB		 2947 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2948 periodic_work.work);
2949 struct b43_wl *wl = dev->wl;
2950 unsigned long delay;
e4d6b795 2951
05b64b36 2952 mutex_lock(&wl->mutex);
e4d6b795
MB		 2953
2954 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2955 goto out;
2956 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2957 goto out_requeue;
2958
05b64b36 2959 do_periodic_work(dev);
e4d6b795 2960
e4d6b795 2961 dev->periodic_state++;
42bb4cd5 2962out_requeue:
e4d6b795
MB		 2963 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2964 delay = msecs_to_jiffies(50);
2965 else
82cd682d 2966 delay = round_jiffies_relative(HZ * 15);
42935eca 2967 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 2968out:
05b64b36 2969 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2970}
2971
2972static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2973{
2974 struct delayed_work *work = &dev->periodic_work;
2975
2976 dev->periodic_state = 0;
2977 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 2978 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 2979}
2980
f3dd3fcc 2981/* Check if communication with the device works correctly. */
e4d6b795
MB		 2982static int b43_validate_chipaccess(struct b43_wldev *dev)
2983{
f62ae6cd 2984 u32 v, backup0, backup4;
e4d6b795 2985
f62ae6cd
MB		 2986 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2987 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 2988
2989 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2990 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2991 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2992 goto error;
f3dd3fcc
MB		 2993 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2994 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2995 goto error;
2996
f62ae6cd
MB		 2997 /* Check if unaligned 32bit SHM_SHARED access works properly.
2998 * However, don't bail out on failure, because it's noncritical. */
2999 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3000 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3001 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3002 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3003 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3004 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3005 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3006 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3007 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3008 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3009 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3010 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3011
3012 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3013 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 3014
3015 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3016 /* The 32bit register shadows the two 16bit registers
3017 * with update sideeffects. Validate this. */
3018 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3019 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3020 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3021 goto error;
3022 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3023 goto error;
3024 }
3025 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3026
3027 v = b43_read32(dev, B43_MMIO_MACCTL);
3028 v |= B43_MACCTL_GMODE;
3029 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3030 goto error;
3031
3032 return 0;
f3dd3fcc 3033error:
e4d6b795
MB		 3034 b43err(dev->wl, "Failed to validate the chipaccess\n");
3035 return -ENODEV;
3036}
3037
3038static void b43_security_init(struct b43_wldev *dev)
3039{
e4d6b795
MB		 3040 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3041 /* KTP is a word address, but we address SHM bytewise.
3042 * So multiply by two.
3043 */
3044 dev->ktp *= 2;
66d2d089
MB		 3045 /* Number of RCMTA address slots */
3046 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3047 /* Clear the key memory. */
e4d6b795
MB		 3048 b43_clear_keys(dev);
3049}
3050
616de35d 3051#ifdef CONFIG_B43_HWRNG
99da185a 3052static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3053{
3054 struct b43_wl *wl = (struct b43_wl *)rng->priv;
e4d6b795 3055
36dbd954
MB		 3056 /* FIXME: We need to take wl->mutex here to make sure the device
3057 * is not going away from under our ass. However it could deadlock
3058 * with hwrng internal locking. */
e4d6b795 3059
e4d6b795 3060 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
e4d6b795
MB		 3061
3062 return (sizeof(u16));
3063}
616de35d 3064#endif /* CONFIG_B43_HWRNG */
e4d6b795 3065
b844eba2 3066static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3067{
616de35d 3068#ifdef CONFIG_B43_HWRNG
e4d6b795 3069 if (wl->rng_initialized)
b844eba2 3070 hwrng_unregister(&wl->rng);
616de35d 3071#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3072}
3073
3074static int b43_rng_init(struct b43_wl *wl)
3075{
616de35d 3076 int err = 0;
e4d6b795 3077
616de35d 3078#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3079 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3080 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3081 wl->rng.name = wl->rng_name;
3082 wl->rng.data_read = b43_rng_read;
3083 wl->rng.priv = (unsigned long)wl;
3084 wl->rng_initialized = 1;
3085 err = hwrng_register(&wl->rng);
3086 if (err) {
3087 wl->rng_initialized = 0;
3088 b43err(wl, "Failed to register the random "
3089 "number generator (%d)\n", err);
3090 }
616de35d 3091#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3092
3093 return err;
3094}
3095
f5d40eed 3096static void b43_tx_work(struct work_struct *work)
e4d6b795 3097{
f5d40eed
MB		 3098 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3099 struct b43_wldev *dev;
3100 struct sk_buff *skb;
3101 int err = 0;
e4d6b795 3102
f5d40eed
MB		 3103 mutex_lock(&wl->mutex);
3104 dev = wl->current_dev;
3105 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3106 mutex_unlock(&wl->mutex);
3107 return;
5100d5ac 3108 }
21a75d77 3109
f5d40eed
MB		 3110 while (skb_queue_len(&wl->tx_queue)) {
3111 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3112
21a75d77 3113 if (b43_using_pio_transfers(dev))
e039fa4a 3114 err = b43_pio_tx(dev, skb);
21a75d77 3115 else
e039fa4a 3116 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3117 if (unlikely(err))
3118 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3119 }
3120
f5d40eed
MB		 3121 mutex_unlock(&wl->mutex);
3122}
21a75d77 3123
f5d40eed
MB		 3124static int b43_op_tx(struct ieee80211_hw *hw,
3125 struct sk_buff *skb)
3126{
3127 struct b43_wl *wl = hw_to_b43_wl(hw);
3128
3129 if (unlikely(skb->len < 2 + 2 + 6)) {
3130 /* Too short, this can't be a valid frame. */
3131 dev_kfree_skb_any(skb);
3132 return NETDEV_TX_OK;
3133 }
3134 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3135
3136 skb_queue_tail(&wl->tx_queue, skb);
3137 ieee80211_queue_work(wl->hw, &wl->tx_work);
c9e8eae0 3138
e4d6b795
MB		 3139 return NETDEV_TX_OK;
3140}
3141
e6f5b934
MB		 3142/* Locking: wl->irq_lock */
3143static void b43_qos_params_upload(struct b43_wldev *dev,
3144 const struct ieee80211_tx_queue_params *p,
3145 u16 shm_offset)
3146{
3147 u16 params[B43_NR_QOSPARAMS];
0b57664c 3148 int bslots, tmp;
e6f5b934
MB		 3149 unsigned int i;
3150
0b57664c 3151 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3152
3153 memset(&params, 0, sizeof(params));
3154
3155 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3156 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3157 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3158 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3159 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3160 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3161 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3162
3163 for (i = 0; i < ARRAY_SIZE(params); i++) {
3164 if (i == B43_QOSPARAM_STATUS) {
3165 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3166 shm_offset + (i * 2));
3167 /* Mark the parameters as updated. */
3168 tmp |= 0x100;
3169 b43_shm_write16(dev, B43_SHM_SHARED,
3170 shm_offset + (i * 2),
3171 tmp);
3172 } else {
3173 b43_shm_write16(dev, B43_SHM_SHARED,
3174 shm_offset + (i * 2),
3175 params[i]);
3176 }
3177 }
3178}
3179
c40c1129
MB		 3180/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3181static const u16 b43_qos_shm_offsets[] = {
3182 /* [mac80211-queue-nr] = SHM_OFFSET, */
3183 [0] = B43_QOS_VOICE,
3184 [1] = B43_QOS_VIDEO,
3185 [2] = B43_QOS_BESTEFFORT,
3186 [3] = B43_QOS_BACKGROUND,
3187};
3188
5a5f3b40
MB		 3189/* Update all QOS parameters in hardware. */
3190static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3191{
3192 struct b43_wl *wl = dev->wl;
3193 struct b43_qos_params *params;
e6f5b934
MB		 3194 unsigned int i;
3195
c40c1129
MB		 3196 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3197 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3198
3199 b43_mac_suspend(dev);
e6f5b934
MB		 3200 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3201 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3202 b43_qos_params_upload(dev, &(params->p),
3203 b43_qos_shm_offsets[i]);
e6f5b934 3204 }
e6f5b934
MB		 3205 b43_mac_enable(dev);
3206}
3207
3208static void b43_qos_clear(struct b43_wl *wl)
3209{
3210 struct b43_qos_params *params;
3211 unsigned int i;
3212
c40c1129
MB		 3213 /* Initialize QoS parameters to sane defaults. */
3214
3215 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3216 ARRAY_SIZE(wl->qos_params));
3217
e6f5b934
MB		 3218 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3219 params = &(wl->qos_params[i]);
3220
c40c1129
MB		 3221 switch (b43_qos_shm_offsets[i]) {
3222 case B43_QOS_VOICE:
3223 params->p.txop = 0;
3224 params->p.aifs = 2;
3225 params->p.cw_min = 0x0001;
3226 params->p.cw_max = 0x0001;
3227 break;
3228 case B43_QOS_VIDEO:
3229 params->p.txop = 0;
3230 params->p.aifs = 2;
3231 params->p.cw_min = 0x0001;
3232 params->p.cw_max = 0x0001;
3233 break;
3234 case B43_QOS_BESTEFFORT:
3235 params->p.txop = 0;
3236 params->p.aifs = 3;
3237 params->p.cw_min = 0x0001;
3238 params->p.cw_max = 0x03FF;
3239 break;
3240 case B43_QOS_BACKGROUND:
3241 params->p.txop = 0;
3242 params->p.aifs = 7;
3243 params->p.cw_min = 0x0001;
3244 params->p.cw_max = 0x03FF;
3245 break;
3246 default:
3247 B43_WARN_ON(1);
3248 }
e6f5b934
MB		 3249 }
3250}
3251
3252/* Initialize the core's QOS capabilities */
3253static void b43_qos_init(struct b43_wldev *dev)
3254{
e6f5b934 3255 /* Upload the current QOS parameters. */
5a5f3b40 3256 b43_qos_upload_all(dev);
e6f5b934
MB		 3257
3258 /* Enable QOS support. */
3259 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3260 b43_write16(dev, B43_MMIO_IFSCTL,
3261 b43_read16(dev, B43_MMIO_IFSCTL)
3262 | B43_MMIO_IFSCTL_USE_EDCF);
3263}
3264
e100bb64 3265static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3266 const struct ieee80211_tx_queue_params *params)
e4d6b795 3267{
e6f5b934 3268 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3269 struct b43_wldev *dev;
e6f5b934 3270 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3271 int err = -ENODEV;
e6f5b934
MB		 3272
3273 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3274 /* Queue not available or don't support setting
3275 * params on this queue. Return success to not
3276 * confuse mac80211. */
3277 return 0;
3278 }
5a5f3b40
MB		 3279 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3280 ARRAY_SIZE(wl->qos_params));
e6f5b934 3281
5a5f3b40
MB		 3282 mutex_lock(&wl->mutex);
3283 dev = wl->current_dev;
3284 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3285 goto out_unlock;
e6f5b934 3286
5a5f3b40
MB		 3287 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3288 b43_mac_suspend(dev);
3289 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3290 b43_qos_shm_offsets[queue]);
3291 b43_mac_enable(dev);
3292 err = 0;
e6f5b934 3293
5a5f3b40
MB		 3294out_unlock:
3295 mutex_unlock(&wl->mutex);
3296
3297 return err;
e4d6b795
MB		 3298}
3299
40faacc4
MB		 3300static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3301 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3302{
3303 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3304 struct b43_wldev *dev;
e4d6b795
MB		 3305 int err = -ENODEV;
3306
36dbd954
MB		 3307 mutex_lock(&wl->mutex);
3308 dev = wl->current_dev;
3309 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
5100d5ac
MB		 3310 if (b43_using_pio_transfers(dev))
3311 b43_pio_get_tx_stats(dev, stats);
3312 else
3313 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3314 err = 0;
3315 }
36dbd954
MB		 3316 mutex_unlock(&wl->mutex);
3317
e4d6b795
MB		 3318 return err;
3319}
3320
40faacc4
MB		 3321static int b43_op_get_stats(struct ieee80211_hw *hw,
3322 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3323{
3324 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3325
36dbd954 3326 mutex_lock(&wl->mutex);
e4d6b795 3327 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3328 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3329
3330 return 0;
3331}
3332
08e87a83
AF		 3333static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3334{
3335 struct b43_wl *wl = hw_to_b43_wl(hw);
3336 struct b43_wldev *dev;
3337 u64 tsf;
3338
3339 mutex_lock(&wl->mutex);
08e87a83
AF		 3340 dev = wl->current_dev;
3341
3342 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3343 b43_tsf_read(dev, &tsf);
3344 else
3345 tsf = 0;
3346
08e87a83
AF		 3347 mutex_unlock(&wl->mutex);
3348
3349 return tsf;
3350}
3351
3352static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3353{
3354 struct b43_wl *wl = hw_to_b43_wl(hw);
3355 struct b43_wldev *dev;
3356
3357 mutex_lock(&wl->mutex);
08e87a83
AF		 3358 dev = wl->current_dev;
3359
3360 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3361 b43_tsf_write(dev, tsf);
3362
08e87a83
AF		 3363 mutex_unlock(&wl->mutex);
3364}
3365
e4d6b795
MB		 3366static void b43_put_phy_into_reset(struct b43_wldev *dev)
3367{
3368 struct ssb_device *sdev = dev->dev;
3369 u32 tmslow;
3370
3371 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3372 tmslow &= ~B43_TMSLOW_GMODE;
3373 tmslow |= B43_TMSLOW_PHYRESET;
3374 tmslow |= SSB_TMSLOW_FGC;
3375 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3376 msleep(1);
3377
3378 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3379 tmslow &= ~SSB_TMSLOW_FGC;
3380 tmslow |= B43_TMSLOW_PHYRESET;
3381 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3382 msleep(1);
3383}
3384
99da185a 3385static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3386{
3387 switch (band) {
3388 case IEEE80211_BAND_5GHZ:
3389 return "5";
3390 case IEEE80211_BAND_2GHZ:
3391 return "2.4";
3392 default:
3393 break;
3394 }
3395 B43_WARN_ON(1);
3396 return "";
3397}
3398
e4d6b795 3399/* Expects wl->mutex locked */
bb1eeff1 3400static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3401{
bb1eeff1 3402 struct b43_wldev *up_dev = NULL;
e4d6b795 3403 struct b43_wldev *down_dev;
bb1eeff1 3404 struct b43_wldev *d;
e4d6b795 3405 int err;
922d8a0b 3406 bool uninitialized_var(gmode);
e4d6b795
MB		 3407 int prev_status;
3408
bb1eeff1
MB		 3409 /* Find a device and PHY which supports the band. */
3410 list_for_each_entry(d, &wl->devlist, list) {
3411 switch (chan->band) {
3412 case IEEE80211_BAND_5GHZ:
3413 if (d->phy.supports_5ghz) {
3414 up_dev = d;
3415 gmode = 0;
3416 }
3417 break;
3418 case IEEE80211_BAND_2GHZ:
3419 if (d->phy.supports_2ghz) {
3420 up_dev = d;
3421 gmode = 1;
3422 }
3423 break;
3424 default:
3425 B43_WARN_ON(1);
3426 return -EINVAL;
3427 }
3428 if (up_dev)
3429 break;
3430 }
3431 if (!up_dev) {
3432 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3433 band_to_string(chan->band));
3434 return -ENODEV;
e4d6b795
MB		 3435 }
3436 if ((up_dev == wl->current_dev) &&
3437 (!!wl->current_dev->phy.gmode == !!gmode)) {
3438 /* This device is already running. */
3439 return 0;
3440 }
bb1eeff1
MB		 3441 b43dbg(wl, "Switching to %s-GHz band\n",
3442 band_to_string(chan->band));
e4d6b795
MB		 3443 down_dev = wl->current_dev;
3444
3445 prev_status = b43_status(down_dev);
3446 /* Shutdown the currently running core. */
3447 if (prev_status >= B43_STAT_STARTED)
36dbd954 3448 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3449 if (prev_status >= B43_STAT_INITIALIZED)
3450 b43_wireless_core_exit(down_dev);
3451
3452 if (down_dev != up_dev) {
3453 /* We switch to a different core, so we put PHY into
3454 * RESET on the old core. */
3455 b43_put_phy_into_reset(down_dev);
3456 }
3457
3458 /* Now start the new core. */
3459 up_dev->phy.gmode = gmode;
3460 if (prev_status >= B43_STAT_INITIALIZED) {
3461 err = b43_wireless_core_init(up_dev);
3462 if (err) {
3463 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3464 "selected %s-GHz band\n",
3465 band_to_string(chan->band));
e4d6b795
MB		 3466 goto init_failure;
3467 }
3468 }
3469 if (prev_status >= B43_STAT_STARTED) {
3470 err = b43_wireless_core_start(up_dev);
3471 if (err) {
3472 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3473 "selected %s-GHz band\n",
3474 band_to_string(chan->band));
e4d6b795
MB		 3475 b43_wireless_core_exit(up_dev);
3476 goto init_failure;
3477 }
3478 }
3479 B43_WARN_ON(b43_status(up_dev) != prev_status);
3480
3481 wl->current_dev = up_dev;
3482
3483 return 0;
bb1eeff1 3484init_failure:
e4d6b795
MB		 3485 /* Whoops, failed to init the new core. No core is operating now. */
3486 wl->current_dev = NULL;
3487 return err;
3488}
3489
9124b077
JB		 3490/* Write the short and long frame retry limit values. */
3491static void b43_set_retry_limits(struct b43_wldev *dev,
3492 unsigned int short_retry,
3493 unsigned int long_retry)
3494{
3495 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3496 * the chip-internal counter. */
3497 short_retry = min(short_retry, (unsigned int)0xF);
3498 long_retry = min(long_retry, (unsigned int)0xF);
3499
3500 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3501 short_retry);
3502 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3503 long_retry);
3504}
3505
e8975581 3506static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3507{
3508 struct b43_wl *wl = hw_to_b43_wl(hw);
3509 struct b43_wldev *dev;
3510 struct b43_phy *phy;
e8975581 3511 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3512 int antenna;
e4d6b795 3513 int err = 0;
e4d6b795 3514
e4d6b795
MB		 3515 mutex_lock(&wl->mutex);
3516
bb1eeff1
MB		 3517 /* Switch the band (if necessary). This might change the active core. */
3518 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3519 if (err)
3520 goto out_unlock_mutex;
3521 dev = wl->current_dev;
3522 phy = &dev->phy;
3523
d10d0e57
MB		 3524 b43_mac_suspend(dev);
3525
9124b077
JB		 3526 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3527 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3528 conf->long_frame_max_tx_count);
3529 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3530 if (!changed)
d10d0e57 3531 goto out_mac_enable;
e4d6b795
MB		 3532
3533 /* Switch to the requested channel.
3534 * The firmware takes care of races with the TX handler. */
8318d78a 3535 if (conf->channel->hw_value != phy->channel)
ef1a628d 3536 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3537
d42ce84a
JB		 3538 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3539
e4d6b795
MB		 3540 /* Adjust the desired TX power level. */
3541 if (conf->power_level != 0) {
18c8adeb
MB		 3542 if (conf->power_level != phy->desired_txpower) {
3543 phy->desired_txpower = conf->power_level;
3544 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3545 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3546 }
3547 }
3548
3549 /* Antennas for RX and management frame TX. */
0f4ac38b 3550 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3551 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3552 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3553 if (phy->ops->set_rx_antenna)
3554 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3555
fd4973c5
LF		 3556 if (wl->radio_enabled != phy->radio_on) {
3557 if (wl->radio_enabled) {
19d337df 3558 b43_software_rfkill(dev, false);
fda9abcf
MB		 3559 b43info(dev->wl, "Radio turned on by software\n");
3560 if (!dev->radio_hw_enable) {
3561 b43info(dev->wl, "The hardware RF-kill button "
3562 "still turns the radio physically off. "
3563 "Press the button to turn it on.\n");
3564 }
3565 } else {
19d337df 3566 b43_software_rfkill(dev, true);
fda9abcf
MB		 3567 b43info(dev->wl, "Radio turned off by software\n");
3568 }
3569 }
3570
d10d0e57
MB		 3571out_mac_enable:
3572 b43_mac_enable(dev);
3573out_unlock_mutex:
e4d6b795
MB		 3574 mutex_unlock(&wl->mutex);
3575
3576 return err;
3577}
3578
881d948c 3579static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3580{
3581 struct ieee80211_supported_band *sband =
3582 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3583 struct ieee80211_rate *rate;
3584 int i;
3585 u16 basic, direct, offset, basic_offset, rateptr;
3586
3587 for (i = 0; i < sband->n_bitrates; i++) {
3588 rate = &sband->bitrates[i];
3589
3590 if (b43_is_cck_rate(rate->hw_value)) {
3591 direct = B43_SHM_SH_CCKDIRECT;
3592 basic = B43_SHM_SH_CCKBASIC;
3593 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3594 offset &= 0xF;
3595 } else {
3596 direct = B43_SHM_SH_OFDMDIRECT;
3597 basic = B43_SHM_SH_OFDMBASIC;
3598 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3599 offset &= 0xF;
3600 }
3601
3602 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3603
3604 if (b43_is_cck_rate(rate->hw_value)) {
3605 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3606 basic_offset &= 0xF;
3607 } else {
3608 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3609 basic_offset &= 0xF;
3610 }
3611
3612 /*
3613 * Get the pointer that we need to point to
3614 * from the direct map
3615 */
3616 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3617 direct + 2 * basic_offset);
3618 /* and write it to the basic map */
3619 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3620 rateptr);
3621 }
3622}
3623
3624static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3625 struct ieee80211_vif *vif,
3626 struct ieee80211_bss_conf *conf,
3627 u32 changed)
3628{
3629 struct b43_wl *wl = hw_to_b43_wl(hw);
3630 struct b43_wldev *dev;
c7ab5ef9
JB		 3631
3632 mutex_lock(&wl->mutex);
3633
3634 dev = wl->current_dev;
d10d0e57 3635 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3636 goto out_unlock_mutex;
2d0ddec5
JB		 3637
3638 B43_WARN_ON(wl->vif != vif);
3639
3640 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3641 if (conf->bssid)
3642 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3643 else
3644 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3645 }
2d0ddec5 3646
3f0d843b
JB		 3647 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3648 if (changed & BSS_CHANGED_BEACON &&
3649 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3650 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3651 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3652 b43_update_templates(wl);
3653
3654 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3655 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3656 }
3657
c7ab5ef9
JB		 3658 b43_mac_suspend(dev);
3659
57c4d7b4
JB		 3660 /* Update templates for AP/mesh mode. */
3661 if (changed & BSS_CHANGED_BEACON_INT &&
3662 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3663 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3664 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3665 b43_set_beacon_int(dev, conf->beacon_int);
3666
c7ab5ef9
JB		 3667 if (changed & BSS_CHANGED_BASIC_RATES)
3668 b43_update_basic_rates(dev, conf->basic_rates);
3669
3670 if (changed & BSS_CHANGED_ERP_SLOT) {
3671 if (conf->use_short_slot)
3672 b43_short_slot_timing_enable(dev);
3673 else
3674 b43_short_slot_timing_disable(dev);
3675 }
3676
3677 b43_mac_enable(dev);
d10d0e57 3678out_unlock_mutex:
c7ab5ef9 3679 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3680}
3681
40faacc4 3682static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3683 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3684 struct ieee80211_key_conf *key)
e4d6b795
MB		 3685{
3686 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3687 struct b43_wldev *dev;
e4d6b795
MB		 3688 u8 algorithm;
3689 u8 index;
c6dfc9a8 3690 int err;
060210f9 3691 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3692
3693 if (modparam_nohwcrypt)
3694 return -ENOSPC; /* User disabled HW-crypto */
3695
c6dfc9a8 3696 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3697
3698 dev = wl->current_dev;
3699 err = -ENODEV;
3700 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3701 goto out_unlock;
3702
403a3a13 3703 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3704 /* We don't have firmware for the crypto engine.
3705 * Must use software-crypto. */
3706 err = -EOPNOTSUPP;
3707 goto out_unlock;
3708 }
3709
c6dfc9a8 3710 err = -EINVAL;
e4d6b795 3711 switch (key->alg) {
e4d6b795 3712 case ALG_WEP:
e31a16d6 3713 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3714 algorithm = B43_SEC_ALGO_WEP40;
3715 else
3716 algorithm = B43_SEC_ALGO_WEP104;
3717 break;
3718 case ALG_TKIP:
3719 algorithm = B43_SEC_ALGO_TKIP;
3720 break;
3721 case ALG_CCMP:
3722 algorithm = B43_SEC_ALGO_AES;
3723 break;
3724 default:
3725 B43_WARN_ON(1);
c6dfc9a8 3726 goto out_unlock;
e4d6b795 3727 }
e4d6b795
MB		 3728 index = (u8) (key->keyidx);
3729 if (index > 3)
e4d6b795 3730 goto out_unlock;
e4d6b795
MB		 3731
3732 switch (cmd) {
3733 case SET_KEY:
035d0243 3734 if (algorithm == B43_SEC_ALGO_TKIP &&
3735 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3736 !modparam_hwtkip)) {
3737 /* We support only pairwise key */
e4d6b795
MB		 3738 err = -EOPNOTSUPP;
3739 goto out_unlock;
3740 }
3741
e808e586 3742 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3743 if (WARN_ON(!sta)) {
3744 err = -EOPNOTSUPP;
3745 goto out_unlock;
3746 }
e808e586 3747 /* Pairwise key with an assigned MAC address. */
e4d6b795 3748 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3749 key->key, key->keylen,
3750 sta->addr, key);
e808e586
MB		 3751 } else {
3752 /* Group key */
3753 err = b43_key_write(dev, index, algorithm,
3754 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3755 }
3756 if (err)
3757 goto out_unlock;
3758
3759 if (algorithm == B43_SEC_ALGO_WEP40 ||
3760 algorithm == B43_SEC_ALGO_WEP104) {
3761 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3762 } else {
3763 b43_hf_write(dev,
3764 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3765 }
3766 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3767 if (algorithm == B43_SEC_ALGO_TKIP)
3768 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3769 break;
3770 case DISABLE_KEY: {
3771 err = b43_key_clear(dev, key->hw_key_idx);
3772 if (err)
3773 goto out_unlock;
3774 break;
3775 }
3776 default:
3777 B43_WARN_ON(1);
3778 }
9cf7f247 3779
e4d6b795 3780out_unlock:
e4d6b795
MB		 3781 if (!err) {
3782 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3783 "mac: %pM\n",
e4d6b795 3784 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3785 sta ? sta->addr : bcast_addr);
9cf7f247 3786 b43_dump_keymemory(dev);
e4d6b795 3787 }
9cf7f247
MB		 3788 mutex_unlock(&wl->mutex);
3789
e4d6b795
MB		 3790 return err;
3791}
3792
40faacc4
MB		 3793static void b43_op_configure_filter(struct ieee80211_hw *hw,
3794 unsigned int changed, unsigned int *fflags,
3ac64bee 3795 u64 multicast)
e4d6b795
MB		 3796{
3797 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3798 struct b43_wldev *dev;
e4d6b795 3799
36dbd954
MB		 3800 mutex_lock(&wl->mutex);
3801 dev = wl->current_dev;
4150c572
JB		 3802 if (!dev) {
3803 *fflags = 0;
36dbd954 3804 goto out_unlock;
e4d6b795 3805 }
4150c572 3806
4150c572
JB		 3807 *fflags &= FIF_PROMISC_IN_BSS |
3808 FIF_ALLMULTI |
3809 FIF_FCSFAIL |
3810 FIF_PLCPFAIL |
3811 FIF_CONTROL |
3812 FIF_OTHER_BSS |
3813 FIF_BCN_PRBRESP_PROMISC;
3814
3815 changed &= FIF_PROMISC_IN_BSS |
3816 FIF_ALLMULTI |
3817 FIF_FCSFAIL |
3818 FIF_PLCPFAIL |
3819 FIF_CONTROL |
3820 FIF_OTHER_BSS |
3821 FIF_BCN_PRBRESP_PROMISC;
3822
3823 wl->filter_flags = *fflags;
3824
3825 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3826 b43_adjust_opmode(dev);
36dbd954
MB		 3827
3828out_unlock:
3829 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3830}
3831
36dbd954
MB		 3832/* Locking: wl->mutex
3833 * Returns the current dev. This might be different from the passed in dev,
3834 * because the core might be gone away while we unlocked the mutex. */
3835static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 3836{
3837 struct b43_wl *wl = dev->wl;
36dbd954 3838 struct b43_wldev *orig_dev;
e4d6b795 3839
36dbd954
MB		 3840redo:
3841 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3842 return dev;
a19d12d7 3843
f5d40eed 3844 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 3845 mutex_unlock(&wl->mutex);
3846 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 3847 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 3848 mutex_lock(&wl->mutex);
3849 dev = wl->current_dev;
3850 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3851 /* Whoops, aliens ate up the device while we were unlocked. */
3852 return dev;
3853 }
a19d12d7 3854
36dbd954 3855 /* Disable interrupts on the device. */
e4d6b795 3856 b43_set_status(dev, B43_STAT_INITIALIZED);
36dbd954
MB		 3857 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
3858 /* wl->mutex is locked. That is enough. */
3859 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3860 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3861 } else {
3862 spin_lock_irq(&wl->hardirq_lock);
3863 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3864 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3865 spin_unlock_irq(&wl->hardirq_lock);
3866 }
3867 /* Synchronize the interrupt handlers. Unlock to avoid deadlocks. */
3868 orig_dev = dev;
e4d6b795 3869 mutex_unlock(&wl->mutex);
36dbd954 3870 synchronize_irq(dev->dev->irq);
e4d6b795 3871 mutex_lock(&wl->mutex);
36dbd954
MB		 3872 dev = wl->current_dev;
3873 if (!dev)
3874 return dev;
3875 if (dev != orig_dev) {
3876 if (b43_status(dev) >= B43_STAT_STARTED)
3877 goto redo;
3878 return dev;
3879 }
3880 B43_WARN_ON(b43_read32(dev, B43_MMIO_GEN_IRQ_MASK));
e4d6b795 3881
f5d40eed
MB		 3882 /* Drain the TX queue */
3883 while (skb_queue_len(&wl->tx_queue))
3884 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3885
e4d6b795
MB		 3886 b43_mac_suspend(dev);
3887 free_irq(dev->dev->irq, dev);
3888 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 3889
3890 return dev;
e4d6b795
MB		 3891}
3892
3893/* Locking: wl->mutex */
3894static int b43_wireless_core_start(struct b43_wldev *dev)
3895{
3896 int err;
3897
3898 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3899
3900 drain_txstatus_queue(dev);
36dbd954
MB		 3901 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3902 b43_interrupt_thread_handler,
3903 IRQF_SHARED, KBUILD_MODNAME, dev);
e4d6b795
MB		 3904 if (err) {
3905 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3906 goto out;
3907 }
3908
3909 /* We are ready to run. */
3910 b43_set_status(dev, B43_STAT_STARTED);
3911
3912 /* Start data flow (TX/RX). */
3913 b43_mac_enable(dev);
13790728 3914 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3915
3916 /* Start maintainance work */
3917 b43_periodic_tasks_setup(dev);
3918
3919 b43dbg(dev->wl, "Wireless interface started\n");
3920 out:
3921 return err;
3922}
3923
3924/* Get PHY and RADIO versioning numbers */
3925static int b43_phy_versioning(struct b43_wldev *dev)
3926{
3927 struct b43_phy *phy = &dev->phy;
3928 u32 tmp;
3929 u8 analog_type;
3930 u8 phy_type;
3931 u8 phy_rev;
3932 u16 radio_manuf;
3933 u16 radio_ver;
3934 u16 radio_rev;
3935 int unsupported = 0;
3936
3937 /* Get PHY versioning */
3938 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3939 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3940 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3941 phy_rev = (tmp & B43_PHYVER_VERSION);
3942 switch (phy_type) {
3943 case B43_PHYTYPE_A:
3944 if (phy_rev >= 4)
3945 unsupported = 1;
3946 break;
3947 case B43_PHYTYPE_B:
3948 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3949 && phy_rev != 7)
3950 unsupported = 1;
3951 break;
3952 case B43_PHYTYPE_G:
013978b6 3953 if (phy_rev > 9)
e4d6b795
MB		 3954 unsupported = 1;
3955 break;
d5c71e46
MB		 3956#ifdef CONFIG_B43_NPHY
3957 case B43_PHYTYPE_N:
bb519bee 3958 if (phy_rev > 4)
d5c71e46
MB		 3959 unsupported = 1;
3960 break;
6b1c7c67
MB		 3961#endif
3962#ifdef CONFIG_B43_PHY_LP
3963 case B43_PHYTYPE_LP:
9d86a2d5 3964 if (phy_rev > 2)
6b1c7c67
MB		 3965 unsupported = 1;
3966 break;
d5c71e46 3967#endif
e4d6b795
MB		 3968 default:
3969 unsupported = 1;
3970 };
3971 if (unsupported) {
3972 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3973 "(Analog %u, Type %u, Revision %u)\n",
3974 analog_type, phy_type, phy_rev);
3975 return -EOPNOTSUPP;
3976 }
3977 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3978 analog_type, phy_type, phy_rev);
3979
3980 /* Get RADIO versioning */
3981 if (dev->dev->bus->chip_id == 0x4317) {
3982 if (dev->dev->bus->chip_rev == 0)
3983 tmp = 0x3205017F;
3984 else if (dev->dev->bus->chip_rev == 1)
3985 tmp = 0x4205017F;
3986 else
3987 tmp = 0x5205017F;
3988 } else {
3989 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3990 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3991 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3992 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3993 }
3994 radio_manuf = (tmp & 0x00000FFF);
3995 radio_ver = (tmp & 0x0FFFF000) >> 12;
3996 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3997 if (radio_manuf != 0x17F /* Broadcom */)
3998 unsupported = 1;
e4d6b795
MB		 3999 switch (phy_type) {
4000 case B43_PHYTYPE_A:
4001 if (radio_ver != 0x2060)
4002 unsupported = 1;
4003 if (radio_rev != 1)
4004 unsupported = 1;
4005 if (radio_manuf != 0x17F)
4006 unsupported = 1;
4007 break;
4008 case B43_PHYTYPE_B:
4009 if ((radio_ver & 0xFFF0) != 0x2050)
4010 unsupported = 1;
4011 break;
4012 case B43_PHYTYPE_G:
4013 if (radio_ver != 0x2050)
4014 unsupported = 1;
4015 break;
96c755a3 4016 case B43_PHYTYPE_N:
bb519bee 4017 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4018 unsupported = 1;
4019 break;
6b1c7c67 4020 case B43_PHYTYPE_LP:
9d86a2d5 4021 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4022 unsupported = 1;
4023 break;
e4d6b795
MB		 4024 default:
4025 B43_WARN_ON(1);
4026 }
4027 if (unsupported) {
4028 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4029 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4030 radio_manuf, radio_ver, radio_rev);
4031 return -EOPNOTSUPP;
4032 }
4033 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4034 radio_manuf, radio_ver, radio_rev);
4035
4036 phy->radio_manuf = radio_manuf;
4037 phy->radio_ver = radio_ver;
4038 phy->radio_rev = radio_rev;
4039
4040 phy->analog = analog_type;
4041 phy->type = phy_type;
4042 phy->rev = phy_rev;
4043
4044 return 0;
4045}
4046
4047static void setup_struct_phy_for_init(struct b43_wldev *dev,
4048 struct b43_phy *phy)
4049{
e4d6b795 4050 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4051 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4052 /* PHY TX errors counter. */
4053 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4054
4055#if B43_DEBUG
4056 phy->phy_locked = 0;
4057 phy->radio_locked = 0;
4058#endif
e4d6b795
MB		 4059}
4060
4061static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4062{
aa6c7ae2
MB		 4063 dev->dfq_valid = 0;
4064
6a724d68
MB		 4065 /* Assume the radio is enabled. If it's not enabled, the state will
4066 * immediately get fixed on the first periodic work run. */
4067 dev->radio_hw_enable = 1;
e4d6b795
MB		 4068
4069 /* Stats */
4070 memset(&dev->stats, 0, sizeof(dev->stats));
4071
4072 setup_struct_phy_for_init(dev, &dev->phy);
4073
4074 /* IRQ related flags */
4075 dev->irq_reason = 0;
4076 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4077 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4078 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4079 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4080
4081 dev->mac_suspended = 1;
4082
4083 /* Noise calculation context */
4084 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4085}
4086
4087static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4088{
4089 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4090 u64 hf;
e4d6b795 4091
1855ba78
MB		 4092 if (!modparam_btcoex)
4093 return;
95de2841 4094 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4095 return;
4096 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4097 return;
4098
4099 hf = b43_hf_read(dev);
95de2841 4100 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4101 hf |= B43_HF_BTCOEXALT;
4102 else
4103 hf |= B43_HF_BTCOEX;
4104 b43_hf_write(dev, hf);
e4d6b795
MB		 4105}
4106
4107static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4108{
4109 if (!modparam_btcoex)
4110 return;
4111 //TODO
e4d6b795
MB		 4112}
4113
4114static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4115{
4116#ifdef CONFIG_SSB_DRIVER_PCICORE
4117 struct ssb_bus *bus = dev->dev->bus;
4118 u32 tmp;
4119
4120 if (bus->pcicore.dev &&
4121 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4122 bus->pcicore.dev->id.revision <= 5) {
4123 /* IMCFGLO timeouts workaround. */
4124 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4125 tmp &= ~SSB_IMCFGLO_REQTO;
4126 tmp &= ~SSB_IMCFGLO_SERTO;
4127 switch (bus->bustype) {
4128 case SSB_BUSTYPE_PCI:
4129 case SSB_BUSTYPE_PCMCIA:
4130 tmp |= 0x32;
4131 break;
4132 case SSB_BUSTYPE_SSB:
4133 tmp |= 0x53;
4134 break;
4135 }
4136 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4137 }
4138#endif /* CONFIG_SSB_DRIVER_PCICORE */
4139}
4140
d59f720d
MB		 4141static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4142{
4143 u16 pu_delay;
4144
4145 /* The time value is in microseconds. */
4146 if (dev->phy.type == B43_PHYTYPE_A)
4147 pu_delay = 3700;
4148 else
4149 pu_delay = 1050;
05c914fe 4150 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4151 pu_delay = 500;
4152 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4153 pu_delay = max(pu_delay, (u16)2400);
4154
4155 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4156}
4157
4158/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4159static void b43_set_pretbtt(struct b43_wldev *dev)
4160{
4161 u16 pretbtt;
4162
4163 /* The time value is in microseconds. */
05c914fe 4164 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4165 pretbtt = 2;
4166 } else {
4167 if (dev->phy.type == B43_PHYTYPE_A)
4168 pretbtt = 120;
4169 else
4170 pretbtt = 250;
4171 }
4172 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4173 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4174}
4175
e4d6b795
MB		 4176/* Shutdown a wireless core */
4177/* Locking: wl->mutex */
4178static void b43_wireless_core_exit(struct b43_wldev *dev)
4179{
1f7d87b0 4180 u32 macctl;
e4d6b795 4181
36dbd954
MB		 4182 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4183 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795
MB		 4184 return;
4185 b43_set_status(dev, B43_STAT_UNINIT);
4186
1f7d87b0
MB		 4187 /* Stop the microcode PSM. */
4188 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4189 macctl &= ~B43_MACCTL_PSM_RUN;
4190 macctl |= B43_MACCTL_PSM_JMP0;
4191 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4192
3506e0c4
RW		 4193 if (!dev->suspend_in_progress) {
4194 b43_leds_exit(dev);
b844eba2 4195 b43_rng_exit(dev->wl);
3506e0c4 4196 }
e4d6b795 4197 b43_dma_free(dev);
5100d5ac 4198 b43_pio_free(dev);
e4d6b795 4199 b43_chip_exit(dev);
cb24f57f 4200 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4201 if (dev->wl->current_beacon) {
4202 dev_kfree_skb_any(dev->wl->current_beacon);
4203 dev->wl->current_beacon = NULL;
4204 }
4205
e4d6b795
MB		 4206 ssb_device_disable(dev->dev, 0);
4207 ssb_bus_may_powerdown(dev->dev->bus);
4208}
4209
4210/* Initialize a wireless core */
4211static int b43_wireless_core_init(struct b43_wldev *dev)
4212{
4213 struct b43_wl *wl = dev->wl;
4214 struct ssb_bus *bus = dev->dev->bus;
4215 struct ssb_sprom *sprom = &bus->sprom;
4216 struct b43_phy *phy = &dev->phy;
4217 int err;
a259d6a4
MB		 4218 u64 hf;
4219 u32 tmp;
e4d6b795
MB		 4220
4221 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4222
4223 err = ssb_bus_powerup(bus, 0);
4224 if (err)
4225 goto out;
4226 if (!ssb_device_is_enabled(dev->dev)) {
4227 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4228 b43_wireless_core_reset(dev, tmp);
4229 }
4230
fb11137a 4231 /* Reset all data structures. */
e4d6b795 4232 setup_struct_wldev_for_init(dev);
fb11137a 4233 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4234
4235 /* Enable IRQ routing to this device. */
4236 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4237
4238 b43_imcfglo_timeouts_workaround(dev);
4239 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4240 if (phy->ops->prepare_hardware) {
4241 err = phy->ops->prepare_hardware(dev);
ef1a628d 4242 if (err)
fb11137a 4243 goto err_busdown;
ef1a628d 4244 }
e4d6b795
MB		 4245 err = b43_chip_init(dev);
4246 if (err)
fb11137a 4247 goto err_busdown;
e4d6b795
MB		 4248 b43_shm_write16(dev, B43_SHM_SHARED,
4249 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4250 hf = b43_hf_read(dev);
4251 if (phy->type == B43_PHYTYPE_G) {
4252 hf |= B43_HF_SYMW;
4253 if (phy->rev == 1)
4254 hf |= B43_HF_GDCW;
95de2841 4255 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4256 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4257 }
4258 if (phy->radio_ver == 0x2050) {
4259 if (phy->radio_rev == 6)
4260 hf |= B43_HF_4318TSSI;
4261 if (phy->radio_rev < 6)
4262 hf |= B43_HF_VCORECALC;
e4d6b795 4263 }
1cc8f476
MB		 4264 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4265 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4266#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4267 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4268 (bus->pcicore.dev->id.revision <= 10))
4269 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4270#endif
25d3ef59 4271 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4272 b43_hf_write(dev, hf);
4273
74cfdba7
MB		 4274 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4275 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4276 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4277 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4278
4279 /* Disable sending probe responses from firmware.
4280 * Setting the MaxTime to one usec will always trigger
4281 * a timeout, so we never send any probe resp.
4282 * A timeout of zero is infinite. */
4283 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4284
4285 b43_rate_memory_init(dev);
5042c507 4286 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4287
4288 /* Minimum Contention Window */
4289 if (phy->type == B43_PHYTYPE_B) {
4290 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4291 } else {
4292 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4293 }
4294 /* Maximum Contention Window */
4295 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4296
5100d5ac
MB		 4297 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4298 dev->__using_pio_transfers = 1;
4299 err = b43_pio_init(dev);
4300 } else {
4301 dev->__using_pio_transfers = 0;
4302 err = b43_dma_init(dev);
4303 }
e4d6b795
MB		 4304 if (err)
4305 goto err_chip_exit;
03b29773 4306 b43_qos_init(dev);
d59f720d 4307 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4308 b43_bluetooth_coext_enable(dev);
4309
1cc8f476 4310 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4311 b43_upload_card_macaddress(dev);
e4d6b795 4312 b43_security_init(dev);
3506e0c4
RW		 4313 if (!dev->suspend_in_progress)
4314 b43_rng_init(wl);
e4d6b795
MB		 4315
4316 b43_set_status(dev, B43_STAT_INITIALIZED);
4317
3506e0c4
RW		 4318 if (!dev->suspend_in_progress)
4319 b43_leds_init(dev);
1a8d1227 4320out:
e4d6b795
MB		 4321 return err;
4322
ef1a628d 4323err_chip_exit:
e4d6b795 4324 b43_chip_exit(dev);
ef1a628d 4325err_busdown:
e4d6b795
MB		 4326 ssb_bus_may_powerdown(bus);
4327 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4328 return err;
4329}
4330
40faacc4
MB		 4331static int b43_op_add_interface(struct ieee80211_hw *hw,
4332 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4333{
4334 struct b43_wl *wl = hw_to_b43_wl(hw);
4335 struct b43_wldev *dev;
e4d6b795 4336 int err = -EOPNOTSUPP;
4150c572
JB		 4337
4338 /* TODO: allow WDS/AP devices to coexist */
4339
05c914fe
JB		 4340 if (conf->type != NL80211_IFTYPE_AP &&
4341 conf->type != NL80211_IFTYPE_MESH_POINT &&
4342 conf->type != NL80211_IFTYPE_STATION &&
4343 conf->type != NL80211_IFTYPE_WDS &&
4344 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4345 return -EOPNOTSUPP;
e4d6b795
MB		 4346
4347 mutex_lock(&wl->mutex);
4150c572 4348 if (wl->operating)
e4d6b795
MB		 4349 goto out_mutex_unlock;
4350
4351 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4352
4353 dev = wl->current_dev;
4150c572 4354 wl->operating = 1;
32bfd35d 4355 wl->vif = conf->vif;
4150c572
JB		 4356 wl->if_type = conf->type;
4357 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4358
4150c572 4359 b43_adjust_opmode(dev);
d59f720d
MB		 4360 b43_set_pretbtt(dev);
4361 b43_set_synth_pu_delay(dev, 0);
4150c572 4362 b43_upload_card_macaddress(dev);
4150c572
JB		 4363
4364 err = 0;
4365 out_mutex_unlock:
4366 mutex_unlock(&wl->mutex);
4367
4368 return err;
4369}
4370
40faacc4
MB		 4371static void b43_op_remove_interface(struct ieee80211_hw *hw,
4372 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4373{
4374 struct b43_wl *wl = hw_to_b43_wl(hw);
4375 struct b43_wldev *dev = wl->current_dev;
4150c572
JB		 4376
4377 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4378
4379 mutex_lock(&wl->mutex);
4380
4381 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4382 B43_WARN_ON(wl->vif != conf->vif);
4383 wl->vif = NULL;
4150c572
JB		 4384
4385 wl->operating = 0;
4386
4150c572
JB		 4387 b43_adjust_opmode(dev);
4388 memset(wl->mac_addr, 0, ETH_ALEN);
4389 b43_upload_card_macaddress(dev);
4150c572
JB		 4390
4391 mutex_unlock(&wl->mutex);
4392}
4393
40faacc4 4394static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4395{
4396 struct b43_wl *wl = hw_to_b43_wl(hw);
4397 struct b43_wldev *dev = wl->current_dev;
4398 int did_init = 0;
923403b8 4399 int err = 0;
4150c572 4400
7be1bb6b
MB		 4401 /* Kill all old instance specific information to make sure
4402 * the card won't use it in the short timeframe between start
4403 * and mac80211 reconfiguring it. */
4404 memset(wl->bssid, 0, ETH_ALEN);
4405 memset(wl->mac_addr, 0, ETH_ALEN);
4406 wl->filter_flags = 0;
4407 wl->radiotap_enabled = 0;
e6f5b934 4408 b43_qos_clear(wl);
6b4bec01
MB		 4409 wl->beacon0_uploaded = 0;
4410 wl->beacon1_uploaded = 0;
4411 wl->beacon_templates_virgin = 1;
fd4973c5 4412 wl->radio_enabled = 1;
7be1bb6b 4413
4150c572
JB		 4414 mutex_lock(&wl->mutex);
4415
e4d6b795
MB		 4416 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4417 err = b43_wireless_core_init(dev);
f41f3f37 4418 if (err)
e4d6b795
MB		 4419 goto out_mutex_unlock;
4420 did_init = 1;
4421 }
4150c572 4422
e4d6b795
MB		 4423 if (b43_status(dev) < B43_STAT_STARTED) {
4424 err = b43_wireless_core_start(dev);
4425 if (err) {
4426 if (did_init)
4427 b43_wireless_core_exit(dev);
4428 goto out_mutex_unlock;
4429 }
4430 }
4431
f41f3f37
JB		 4432 /* XXX: only do if device doesn't support rfkill irq */
4433 wiphy_rfkill_start_polling(hw->wiphy);
4434
4150c572 4435 out_mutex_unlock:
e4d6b795
MB		 4436 mutex_unlock(&wl->mutex);
4437
4438 return err;
4439}
4440
40faacc4 4441static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4442{
4443 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4444 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4445
a82d9922 4446 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4447
e4d6b795 4448 mutex_lock(&wl->mutex);
36dbd954
MB		 4449 if (b43_status(dev) >= B43_STAT_STARTED) {
4450 dev = b43_wireless_core_stop(dev);
4451 if (!dev)
4452 goto out_unlock;
4453 }
4150c572 4454 b43_wireless_core_exit(dev);
fd4973c5 4455 wl->radio_enabled = 0;
36dbd954
MB		 4456
4457out_unlock:
e4d6b795 4458 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4459
4460 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4461}
4462
17741cdc
JB		 4463static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4464 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4465{
4466 struct b43_wl *wl = hw_to_b43_wl(hw);
4467
36dbd954 4468 mutex_lock(&wl->mutex);
9d139c81 4469 b43_update_templates(wl);
36dbd954 4470 mutex_unlock(&wl->mutex);
e66fee6a
MB		 4471
4472 return 0;
4473}
4474
38968d09
JB		 4475static void b43_op_sta_notify(struct ieee80211_hw *hw,
4476 struct ieee80211_vif *vif,
4477 enum sta_notify_cmd notify_cmd,
17741cdc 4478 struct ieee80211_sta *sta)
38968d09
JB		 4479{
4480 struct b43_wl *wl = hw_to_b43_wl(hw);
4481
4482 B43_WARN_ON(!vif || wl->vif != vif);
4483}
4484
25d3ef59
MB		 4485static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4486{
4487 struct b43_wl *wl = hw_to_b43_wl(hw);
4488 struct b43_wldev *dev;
4489
4490 mutex_lock(&wl->mutex);
4491 dev = wl->current_dev;
4492 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4493 /* Disable CFP update during scan on other channels. */
4494 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4495 }
4496 mutex_unlock(&wl->mutex);
4497}
4498
4499static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4500{
4501 struct b43_wl *wl = hw_to_b43_wl(hw);
4502 struct b43_wldev *dev;
4503
4504 mutex_lock(&wl->mutex);
4505 dev = wl->current_dev;
4506 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4507 /* Re-enable CFP update. */
4508 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4509 }
4510 mutex_unlock(&wl->mutex);
4511}
4512
e4d6b795 4513static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4514 .tx = b43_op_tx,
4515 .conf_tx = b43_op_conf_tx,
4516 .add_interface = b43_op_add_interface,
4517 .remove_interface = b43_op_remove_interface,
4518 .config = b43_op_config,
c7ab5ef9 4519 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4520 .configure_filter = b43_op_configure_filter,
4521 .set_key = b43_op_set_key,
035d0243 4522 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4523 .get_stats = b43_op_get_stats,
4524 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4525 .get_tsf = b43_op_get_tsf,
4526 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4527 .start = b43_op_start,
4528 .stop = b43_op_stop,
e66fee6a 4529 .set_tim = b43_op_beacon_set_tim,
38968d09 4530 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4531 .sw_scan_start = b43_op_sw_scan_start_notifier,
4532 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4533 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4534};
4535
4536/* Hard-reset the chip. Do not call this directly.
4537 * Use b43_controller_restart()
4538 */
4539static void b43_chip_reset(struct work_struct *work)
4540{
4541 struct b43_wldev *dev =
4542 container_of(work, struct b43_wldev, restart_work);
4543 struct b43_wl *wl = dev->wl;
4544 int err = 0;
4545 int prev_status;
4546
4547 mutex_lock(&wl->mutex);
4548
4549 prev_status = b43_status(dev);
4550 /* Bring the device down... */
36dbd954
MB		 4551 if (prev_status >= B43_STAT_STARTED) {
4552 dev = b43_wireless_core_stop(dev);
4553 if (!dev) {
4554 err = -ENODEV;
4555 goto out;
4556 }
4557 }
e4d6b795
MB		 4558 if (prev_status >= B43_STAT_INITIALIZED)
4559 b43_wireless_core_exit(dev);
4560
4561 /* ...and up again. */
4562 if (prev_status >= B43_STAT_INITIALIZED) {
4563 err = b43_wireless_core_init(dev);
4564 if (err)
4565 goto out;
4566 }
4567 if (prev_status >= B43_STAT_STARTED) {
4568 err = b43_wireless_core_start(dev);
4569 if (err) {
4570 b43_wireless_core_exit(dev);
4571 goto out;
4572 }
4573 }
3bf0a32e
MB		 4574out:
4575 if (err)
4576 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4577 mutex_unlock(&wl->mutex);
4578 if (err)
4579 b43err(wl, "Controller restart FAILED\n");
4580 else
4581 b43info(wl, "Controller restarted\n");
4582}
4583
bb1eeff1 4584static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4585 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4586{
4587 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4588
bb1eeff1
MB		 4589 if (have_2ghz_phy)
4590 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4591 if (dev->phy.type == B43_PHYTYPE_N) {
4592 if (have_5ghz_phy)
4593 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4594 } else {
4595 if (have_5ghz_phy)
4596 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4597 }
96c755a3 4598
bb1eeff1
MB		 4599 dev->phy.supports_2ghz = have_2ghz_phy;
4600 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4601
4602 return 0;
4603}
4604
4605static void b43_wireless_core_detach(struct b43_wldev *dev)
4606{
4607 /* We release firmware that late to not be required to re-request
4608 * is all the time when we reinit the core. */
4609 b43_release_firmware(dev);
fb11137a 4610 b43_phy_free(dev);
e4d6b795
MB		 4611}
4612
4613static int b43_wireless_core_attach(struct b43_wldev *dev)
4614{
4615 struct b43_wl *wl = dev->wl;
4616 struct ssb_bus *bus = dev->dev->bus;
4617 struct pci_dev *pdev = bus->host_pci;
4618 int err;
96c755a3 4619 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4620 u32 tmp;
4621
4622 /* Do NOT do any device initialization here.
4623 * Do it in wireless_core_init() instead.
4624 * This function is for gathering basic information about the HW, only.
4625 * Also some structs may be set up here. But most likely you want to have
4626 * that in core_init(), too.
4627 */
4628
4629 err = ssb_bus_powerup(bus, 0);
4630 if (err) {
4631 b43err(wl, "Bus powerup failed\n");
4632 goto out;
4633 }
4634 /* Get the PHY type. */
4635 if (dev->dev->id.revision >= 5) {
4636 u32 tmshigh;
4637
4638 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4639 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4640 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4641 } else
96c755a3 4642 B43_WARN_ON(1);
e4d6b795 4643
96c755a3 4644 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4645 dev->phy.radio_on = 1;
e4d6b795
MB		 4646 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4647 b43_wireless_core_reset(dev, tmp);
4648
4649 err = b43_phy_versioning(dev);
4650 if (err)
21954c36 4651 goto err_powerdown;
e4d6b795
MB		 4652 /* Check if this device supports multiband. */
4653 if (!pdev ||
4654 (pdev->device != 0x4312 &&
4655 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4656 /* No multiband support. */
96c755a3
MB		 4657 have_2ghz_phy = 0;
4658 have_5ghz_phy = 0;
e4d6b795
MB		 4659 switch (dev->phy.type) {
4660 case B43_PHYTYPE_A:
96c755a3 4661 have_5ghz_phy = 1;
e4d6b795 4662 break;
9d86a2d5 4663 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4664#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4665 have_5ghz_phy = 1;
86b2892a 4666#endif
e4d6b795 4667 case B43_PHYTYPE_G:
96c755a3
MB		 4668 case B43_PHYTYPE_N:
4669 have_2ghz_phy = 1;
e4d6b795
MB		 4670 break;
4671 default:
4672 B43_WARN_ON(1);
4673 }
4674 }
96c755a3
MB		 4675 if (dev->phy.type == B43_PHYTYPE_A) {
4676 /* FIXME */
4677 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4678 err = -EOPNOTSUPP;
4679 goto err_powerdown;
4680 }
2e35af14
MB		 4681 if (1 /* disable A-PHY */) {
4682 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4683 if (dev->phy.type != B43_PHYTYPE_N &&
4684 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4685 have_2ghz_phy = 1;
4686 have_5ghz_phy = 0;
4687 }
4688 }
4689
fb11137a
MB		 4690 err = b43_phy_allocate(dev);
4691 if (err)
4692 goto err_powerdown;
4693
96c755a3 4694 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4695 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4696 b43_wireless_core_reset(dev, tmp);
4697
4698 err = b43_validate_chipaccess(dev);
4699 if (err)
fb11137a 4700 goto err_phy_free;
bb1eeff1 4701 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4702 if (err)
fb11137a 4703 goto err_phy_free;
e4d6b795
MB		 4704
4705 /* Now set some default "current_dev" */
4706 if (!wl->current_dev)
4707 wl->current_dev = dev;
4708 INIT_WORK(&dev->restart_work, b43_chip_reset);
4709
cb24f57f 4710 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4711 ssb_device_disable(dev->dev, 0);
4712 ssb_bus_may_powerdown(bus);
4713
4714out:
4715 return err;
4716
fb11137a
MB		 4717err_phy_free:
4718 b43_phy_free(dev);
e4d6b795
MB		 4719err_powerdown:
4720 ssb_bus_may_powerdown(bus);
4721 return err;
4722}
4723
4724static void b43_one_core_detach(struct ssb_device *dev)
4725{
4726 struct b43_wldev *wldev;
4727 struct b43_wl *wl;
4728
3bf0a32e
MB		 4729 /* Do not cancel ieee80211-workqueue based work here.
4730 * See comment in b43_remove(). */
4731
e4d6b795
MB		 4732 wldev = ssb_get_drvdata(dev);
4733 wl = wldev->wl;
e4d6b795
MB		 4734 b43_debugfs_remove_device(wldev);
4735 b43_wireless_core_detach(wldev);
4736 list_del(&wldev->list);
4737 wl->nr_devs--;
4738 ssb_set_drvdata(dev, NULL);
4739 kfree(wldev);
4740}
4741
4742static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4743{
4744 struct b43_wldev *wldev;
4745 struct pci_dev *pdev;
4746 int err = -ENOMEM;
4747
4748 if (!list_empty(&wl->devlist)) {
4749 /* We are not the first core on this chip. */
4750 pdev = dev->bus->host_pci;
4751 /* Only special chips support more than one wireless
4752 * core, although some of the other chips have more than
4753 * one wireless core as well. Check for this and
4754 * bail out early.
4755 */
4756 if (!pdev ||
4757 ((pdev->device != 0x4321) &&
4758 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4759 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4760 return -ENODEV;
4761 }
4762 }
4763
4764 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4765 if (!wldev)
4766 goto out;
4767
4768 wldev->dev = dev;
4769 wldev->wl = wl;
4770 b43_set_status(wldev, B43_STAT_UNINIT);
4771 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 4772 INIT_LIST_HEAD(&wldev->list);
4773
4774 err = b43_wireless_core_attach(wldev);
4775 if (err)
4776 goto err_kfree_wldev;
4777
4778 list_add(&wldev->list, &wl->devlist);
4779 wl->nr_devs++;
4780 ssb_set_drvdata(dev, wldev);
4781 b43_debugfs_add_device(wldev);
4782
4783 out:
4784 return err;
4785
4786 err_kfree_wldev:
4787 kfree(wldev);
4788 return err;
4789}
4790
9fc38458
MB		 4791#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4792 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4793 (pdev->device == _device) && \
4794 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4795 (pdev->subsystem_device == _subdevice) )
4796
e4d6b795
MB		 4797static void b43_sprom_fixup(struct ssb_bus *bus)
4798{
1855ba78
MB		 4799 struct pci_dev *pdev;
4800
e4d6b795
MB		 4801 /* boardflags workarounds */
4802 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4803 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4804 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4805 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4806 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4807 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4808 if (bus->bustype == SSB_BUSTYPE_PCI) {
4809 pdev = bus->host_pci;
9fc38458 4810 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4811 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4812 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4813 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4814 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4815 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4816 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4817 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4818 }
e4d6b795
MB		 4819}
4820
4821static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4822{
4823 struct ieee80211_hw *hw = wl->hw;
4824
4825 ssb_set_devtypedata(dev, NULL);
4826 ieee80211_free_hw(hw);
4827}
4828
4829static int b43_wireless_init(struct ssb_device *dev)
4830{
4831 struct ssb_sprom *sprom = &dev->bus->sprom;
4832 struct ieee80211_hw *hw;
4833 struct b43_wl *wl;
4834 int err = -ENOMEM;
4835
4836 b43_sprom_fixup(dev->bus);
4837
4838 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4839 if (!hw) {
4840 b43err(NULL, "Could not allocate ieee80211 device\n");
4841 goto out;
4842 }
403a3a13 4843 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4844
4845 /* fill hw info */
605a0bd6 4846 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4847 IEEE80211_HW_SIGNAL_DBM |
4848 IEEE80211_HW_NOISE_DBM;
4849
f59ac048
LR		 4850 hw->wiphy->interface_modes =
4851 BIT(NL80211_IFTYPE_AP) |
4852 BIT(NL80211_IFTYPE_MESH_POINT) |
4853 BIT(NL80211_IFTYPE_STATION) |
4854 BIT(NL80211_IFTYPE_WDS) |
4855 BIT(NL80211_IFTYPE_ADHOC);
4856
403a3a13
MB		 4857 hw->queues = modparam_qos ? 4 : 1;
4858 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4859 hw->max_rates = 2;
e4d6b795 4860 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4861 if (is_valid_ether_addr(sprom->et1mac))
4862 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4863 else
95de2841 4864 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4865
403a3a13 4866 /* Initialize struct b43_wl */
e4d6b795 4867 wl->hw = hw;
e4d6b795 4868 spin_lock_init(&wl->leds_lock);
280d0e16 4869 spin_lock_init(&wl->shm_lock);
e4d6b795 4870 mutex_init(&wl->mutex);
36dbd954 4871 spin_lock_init(&wl->hardirq_lock);
e4d6b795 4872 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4873 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4874 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 4875 INIT_WORK(&wl->tx_work, b43_tx_work);
4876 skb_queue_head_init(&wl->tx_queue);
e4d6b795
MB		 4877
4878 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4879 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4880 dev->bus->chip_id, dev->id.revision);
e4d6b795 4881 err = 0;
060210f9 4882out:
e4d6b795
MB		 4883 return err;
4884}
4885
4886static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4887{
4888 struct b43_wl *wl;
4889 int err;
4890 int first = 0;
4891
4892 wl = ssb_get_devtypedata(dev);
4893 if (!wl) {
4894 /* Probing the first core. Must setup common struct b43_wl */
4895 first = 1;
4896 err = b43_wireless_init(dev);
4897 if (err)
4898 goto out;
4899 wl = ssb_get_devtypedata(dev);
4900 B43_WARN_ON(!wl);
4901 }
4902 err = b43_one_core_attach(dev, wl);
4903 if (err)
4904 goto err_wireless_exit;
4905
4906 if (first) {
4907 err = ieee80211_register_hw(wl->hw);
4908 if (err)
4909 goto err_one_core_detach;
4910 }
4911
4912 out:
4913 return err;
4914
4915 err_one_core_detach:
4916 b43_one_core_detach(dev);
4917 err_wireless_exit:
4918 if (first)
4919 b43_wireless_exit(dev, wl);
4920 return err;
4921}
4922
4923static void b43_remove(struct ssb_device *dev)
4924{
4925 struct b43_wl *wl = ssb_get_devtypedata(dev);
4926 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4927
3bf0a32e
MB		 4928 /* We must cancel any work here before unregistering from ieee80211,
4929 * as the ieee80211 unreg will destroy the workqueue. */
4930 cancel_work_sync(&wldev->restart_work);
4931
e4d6b795 4932 B43_WARN_ON(!wl);
403a3a13
MB		 4933 if (wl->current_dev == wldev) {
4934 /* Restore the queues count before unregistering, because firmware detect
4935 * might have modified it. Restoring is important, so the networking
4936 * stack can properly free resources. */
4937 wl->hw->queues = wl->mac80211_initially_registered_queues;
e4d6b795 4938 ieee80211_unregister_hw(wl->hw);
403a3a13 4939 }
e4d6b795
MB		 4940
4941 b43_one_core_detach(dev);
4942
4943 if (list_empty(&wl->devlist)) {
4944 /* Last core on the chip unregistered.
4945 * We can destroy common struct b43_wl.
4946 */
4947 b43_wireless_exit(dev, wl);
4948 }
4949}
4950
4951/* Perform a hardware reset. This can be called from any context. */
4952void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4953{
4954 /* Must avoid requeueing, if we are in shutdown. */
4955 if (b43_status(dev) < B43_STAT_INITIALIZED)
4956 return;
4957 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 4958 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 4959}
4960
4961#ifdef CONFIG_PM
4962
4963static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4964{
4965 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4966 struct b43_wl *wl = wldev->wl;
4967
4968 b43dbg(wl, "Suspending...\n");
4969
4970 mutex_lock(&wl->mutex);
3506e0c4 4971 wldev->suspend_in_progress = true;
e4d6b795
MB		 4972 wldev->suspend_init_status = b43_status(wldev);
4973 if (wldev->suspend_init_status >= B43_STAT_STARTED)
36dbd954
MB		 4974 wldev = b43_wireless_core_stop(wldev);
4975 if (wldev && wldev->suspend_init_status >= B43_STAT_INITIALIZED)
e4d6b795
MB		 4976 b43_wireless_core_exit(wldev);
4977 mutex_unlock(&wl->mutex);
4978
4979 b43dbg(wl, "Device suspended.\n");
4980
4981 return 0;
4982}
4983
4984static int b43_resume(struct ssb_device *dev)
4985{
4986 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4987 struct b43_wl *wl = wldev->wl;
4988 int err = 0;
4989
4990 b43dbg(wl, "Resuming...\n");
4991
4992 mutex_lock(&wl->mutex);
4993 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4994 err = b43_wireless_core_init(wldev);
4995 if (err) {
4996 b43err(wl, "Resume failed at core init\n");
4997 goto out;
4998 }
4999 }
5000 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
5001 err = b43_wireless_core_start(wldev);
5002 if (err) {
3506e0c4 5003 b43_leds_exit(wldev);
b844eba2 5004 b43_rng_exit(wldev->wl);
e4d6b795
MB		 5005 b43_wireless_core_exit(wldev);
5006 b43err(wl, "Resume failed at core start\n");
5007 goto out;
5008 }
5009 }
e4d6b795 5010 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 5011 out:
5012 wldev->suspend_in_progress = false;
5013 mutex_unlock(&wl->mutex);
e4d6b795
MB		 5014 return err;
5015}
5016
5017#else /* CONFIG_PM */
5018# define b43_suspend NULL
5019# define b43_resume NULL
5020#endif /* CONFIG_PM */
5021
5022static struct ssb_driver b43_ssb_driver = {
5023 .name = KBUILD_MODNAME,
5024 .id_table = b43_ssb_tbl,
5025 .probe = b43_probe,
5026 .remove = b43_remove,
5027 .suspend = b43_suspend,
5028 .resume = b43_resume,
5029};
5030
26bc783f
MB		 5031static void b43_print_driverinfo(void)
5032{
5033 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
f41f3f37 5034 *feat_leds = "";
26bc783f
MB		 5035
5036#ifdef CONFIG_B43_PCI_AUTOSELECT
5037 feat_pci = "P";
5038#endif
5039#ifdef CONFIG_B43_PCMCIA
5040 feat_pcmcia = "M";
5041#endif
5042#ifdef CONFIG_B43_NPHY
5043 feat_nphy = "N";
5044#endif
5045#ifdef CONFIG_B43_LEDS
5046 feat_leds = "L";
26bc783f
MB		 5047#endif
5048 printk(KERN_INFO "Broadcom 43xx driver loaded "
f41f3f37 5049 "[ Features: %s%s%s%s, Firmware-ID: "
26bc783f
MB		 5050 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5051 feat_pci, feat_pcmcia, feat_nphy,
f41f3f37 5052 feat_leds);
26bc783f
MB		 5053}
5054
e4d6b795
MB		 5055static int __init b43_init(void)
5056{
5057 int err;
5058
5059 b43_debugfs_init();
5060 err = b43_pcmcia_init();
5061 if (err)
5062 goto err_dfs_exit;
5063 err = ssb_driver_register(&b43_ssb_driver);
5064 if (err)
5065 goto err_pcmcia_exit;
26bc783f 5066 b43_print_driverinfo();
e4d6b795
MB		 5067
5068 return err;
5069
5070err_pcmcia_exit:
5071 b43_pcmcia_exit();
5072err_dfs_exit:
5073 b43_debugfs_exit();
5074 return err;
5075}
5076
5077static void __exit b43_exit(void)
5078{
5079 ssb_driver_unregister(&b43_ssb_driver);
5080 b43_pcmcia_exit();
5081 b43_debugfs_exit();
5082}
5083
5084module_init(b43_init)
5085module_exit(b43_exit)
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