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rt2x00: Fix queue_idx initialization
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
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e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
47#include "phy.h"
48#include "dma.h"
e4d6b795
MB		 49#include "sysfs.h"
50#include "xmit.h"
e4d6b795
MB		 51#include "lo.h"
52#include "pcmcia.h"
53
54MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55MODULE_AUTHOR("Martin Langer");
56MODULE_AUTHOR("Stefano Brivio");
57MODULE_AUTHOR("Michael Buesch");
58MODULE_LICENSE("GPL");
59
e4d6b795
MB		 60
61static int modparam_bad_frames_preempt;
62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
65
e4d6b795
MB		 66static char modparam_fwpostfix[16];
67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
69
e4d6b795
MB		 70static int modparam_hwpctl;
71module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
73
74static int modparam_nohwcrypt;
75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77
78static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 86 SSB_DEVTABLE_END
87};
88
89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
90
91/* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95#define RATETAB_ENT(_rateid, _flags) \
96 { \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
98 .val = (_rateid), \
99 .val2 = (_rateid), \
100 .flags = (_flags), \
101 }
102static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
115};
116
117#define b43_a_ratetable (__b43_ratetable + 4)
118#define b43_a_ratetable_size 8
119#define b43_b_ratetable (__b43_ratetable + 0)
120#define b43_b_ratetable_size 4
121#define b43_g_ratetable (__b43_ratetable + 0)
122#define b43_g_ratetable_size 12
123
124#define CHANTAB_ENT(_chanid, _freq) \
125 { \
126 .chan = (_chanid), \
127 .freq = (_freq), \
128 .val = (_chanid), \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
134 }
96c755a3 135static struct ieee80211_channel b43_2ghz_chantable[] = {
e4d6b795
MB		 136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
150};
96c755a3 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
e4d6b795 152
96c755a3
MB		 153#if 0
154static struct ieee80211_channel b43_5ghz_chantable[] = {
e4d6b795
MB		 155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
168};
96c755a3
MB		 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
170#endif
e4d6b795
MB		 171
172static void b43_wireless_core_exit(struct b43_wldev *dev);
173static int b43_wireless_core_init(struct b43_wldev *dev);
174static void b43_wireless_core_stop(struct b43_wldev *dev);
175static int b43_wireless_core_start(struct b43_wldev *dev);
176
177static int b43_ratelimit(struct b43_wl *wl)
178{
179 if (!wl || !wl->current_dev)
180 return 1;
181 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
182 return 1;
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
186}
187
188void b43info(struct b43_wl *wl, const char *fmt, ...)
189{
190 va_list args;
191
192 if (!b43_ratelimit(wl))
193 return;
194 va_start(args, fmt);
195 printk(KERN_INFO "b43-%s: ",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
197 vprintk(fmt, args);
198 va_end(args);
199}
200
201void b43err(struct b43_wl *wl, const char *fmt, ...)
202{
203 va_list args;
204
205 if (!b43_ratelimit(wl))
206 return;
207 va_start(args, fmt);
208 printk(KERN_ERR "b43-%s ERROR: ",
209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
210 vprintk(fmt, args);
211 va_end(args);
212}
213
214void b43warn(struct b43_wl *wl, const char *fmt, ...)
215{
216 va_list args;
217
218 if (!b43_ratelimit(wl))
219 return;
220 va_start(args, fmt);
221 printk(KERN_WARNING "b43-%s warning: ",
222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
223 vprintk(fmt, args);
224 va_end(args);
225}
226
227#if B43_DEBUG
228void b43dbg(struct b43_wl *wl, const char *fmt, ...)
229{
230 va_list args;
231
232 va_start(args, fmt);
233 printk(KERN_DEBUG "b43-%s debug: ",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
235 vprintk(fmt, args);
236 va_end(args);
237}
238#endif /* DEBUG */
239
240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
241{
242 u32 macctl;
243
244 B43_WARN_ON(offset % 4 != 0);
245
246 macctl = b43_read32(dev, B43_MMIO_MACCTL);
247 if (macctl & B43_MACCTL_BE)
248 val = swab32(val);
249
250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
251 mmiowb();
252 b43_write32(dev, B43_MMIO_RAM_DATA, val);
253}
254
280d0e16
MB		 255static inline void b43_shm_control_word(struct b43_wldev *dev,
256 u16 routing, u16 offset)
e4d6b795
MB		 257{
258 u32 control;
259
260 /* "offset" is the WORD offset. */
e4d6b795
MB		 261 control = routing;
262 control <<= 16;
263 control |= offset;
264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
265}
266
267u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
268{
280d0e16
MB		 269 struct b43_wl *wl = dev->wl;
270 unsigned long flags;
e4d6b795
MB		 271 u32 ret;
272
280d0e16 273 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 274 if (routing == B43_SHM_SHARED) {
275 B43_WARN_ON(offset & 0x0001);
276 if (offset & 0x0003) {
277 /* Unaligned access */
278 b43_shm_control_word(dev, routing, offset >> 2);
279 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
280 ret <<= 16;
281 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
282 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
283
280d0e16 284 goto out;
e4d6b795
MB		 285 }
286 offset >>= 2;
287 }
288 b43_shm_control_word(dev, routing, offset);
289 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 290out:
291 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 292
293 return ret;
294}
295
296u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
297{
280d0e16
MB		 298 struct b43_wl *wl = dev->wl;
299 unsigned long flags;
e4d6b795
MB		 300 u16 ret;
301
280d0e16 302 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 303 if (routing == B43_SHM_SHARED) {
304 B43_WARN_ON(offset & 0x0001);
305 if (offset & 0x0003) {
306 /* Unaligned access */
307 b43_shm_control_word(dev, routing, offset >> 2);
308 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
309
280d0e16 310 goto out;
e4d6b795
MB		 311 }
312 offset >>= 2;
313 }
314 b43_shm_control_word(dev, routing, offset);
315 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 316out:
317 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 318
319 return ret;
320}
321
322void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
323{
280d0e16
MB		 324 struct b43_wl *wl = dev->wl;
325 unsigned long flags;
326
327 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 328 if (routing == B43_SHM_SHARED) {
329 B43_WARN_ON(offset & 0x0001);
330 if (offset & 0x0003) {
331 /* Unaligned access */
332 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 333 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
334 (value >> 16) & 0xffff);
e4d6b795 335 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
280d0e16 337 goto out;
e4d6b795
MB		 338 }
339 offset >>= 2;
340 }
341 b43_shm_control_word(dev, routing, offset);
e4d6b795 342 b43_write32(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 343out:
344 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 345}
346
347void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
348{
280d0e16
MB		 349 struct b43_wl *wl = dev->wl;
350 unsigned long flags;
351
352 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 353 if (routing == B43_SHM_SHARED) {
354 B43_WARN_ON(offset & 0x0001);
355 if (offset & 0x0003) {
356 /* Unaligned access */
357 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 358 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
280d0e16 359 goto out;
e4d6b795
MB		 360 }
361 offset >>= 2;
362 }
363 b43_shm_control_word(dev, routing, offset);
e4d6b795 364 b43_write16(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 365out:
366 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 367}
368
369/* Read HostFlags */
370u32 b43_hf_read(struct b43_wldev * dev)
371{
372 u32 ret;
373
374 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
375 ret <<= 16;
376 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
377
378 return ret;
379}
380
381/* Write HostFlags */
382void b43_hf_write(struct b43_wldev *dev, u32 value)
383{
384 b43_shm_write16(dev, B43_SHM_SHARED,
385 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
386 b43_shm_write16(dev, B43_SHM_SHARED,
387 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
388}
389
390void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
391{
392 /* We need to be careful. As we read the TSF from multiple
393 * registers, we should take care of register overflows.
394 * In theory, the whole tsf read process should be atomic.
395 * We try to be atomic here, by restaring the read process,
396 * if any of the high registers changed (overflew).
397 */
398 if (dev->dev->id.revision >= 3) {
399 u32 low, high, high2;
400
401 do {
402 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
403 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
404 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0, v1, v2, v3;
413 u16 test1, test2, test3;
414
415 do {
416 v3 = b43_read16(dev, B43_MMIO_TSF_3);
417 v2 = b43_read16(dev, B43_MMIO_TSF_2);
418 v1 = b43_read16(dev, B43_MMIO_TSF_1);
419 v0 = b43_read16(dev, B43_MMIO_TSF_0);
420
421 test3 = b43_read16(dev, B43_MMIO_TSF_3);
422 test2 = b43_read16(dev, B43_MMIO_TSF_2);
423 test1 = b43_read16(dev, B43_MMIO_TSF_1);
424 } while (v3 != test3 || v2 != test2 || v1 != test1);
425
426 *tsf = v3;
427 *tsf <<= 48;
428 tmp = v2;
429 tmp <<= 32;
430 *tsf |= tmp;
431 tmp = v1;
432 tmp <<= 16;
433 *tsf |= tmp;
434 *tsf |= v0;
435 }
436}
437
438static void b43_time_lock(struct b43_wldev *dev)
439{
440 u32 macctl;
441
442 macctl = b43_read32(dev, B43_MMIO_MACCTL);
443 macctl |= B43_MACCTL_TBTTHOLD;
444 b43_write32(dev, B43_MMIO_MACCTL, macctl);
445 /* Commit the write */
446 b43_read32(dev, B43_MMIO_MACCTL);
447}
448
449static void b43_time_unlock(struct b43_wldev *dev)
450{
451 u32 macctl;
452
453 macctl = b43_read32(dev, B43_MMIO_MACCTL);
454 macctl &= ~B43_MACCTL_TBTTHOLD;
455 b43_write32(dev, B43_MMIO_MACCTL, macctl);
456 /* Commit the write */
457 b43_read32(dev, B43_MMIO_MACCTL);
458}
459
460static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
461{
462 /* Be careful with the in-progress timer.
463 * First zero out the low register, so we have a full
464 * register-overflow duration to complete the operation.
465 */
466 if (dev->dev->id.revision >= 3) {
467 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
468 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
469
470 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
471 mmiowb();
472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
473 mmiowb();
474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
475 } else {
476 u16 v0 = (tsf & 0x000000000000FFFFULL);
477 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
478 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
479 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
480
481 b43_write16(dev, B43_MMIO_TSF_0, 0);
482 mmiowb();
483 b43_write16(dev, B43_MMIO_TSF_3, v3);
484 mmiowb();
485 b43_write16(dev, B43_MMIO_TSF_2, v2);
486 mmiowb();
487 b43_write16(dev, B43_MMIO_TSF_1, v1);
488 mmiowb();
489 b43_write16(dev, B43_MMIO_TSF_0, v0);
490 }
491}
492
493void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
494{
495 b43_time_lock(dev);
496 b43_tsf_write_locked(dev, tsf);
497 b43_time_unlock(dev);
498}
499
500static
501void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
502{
503 static const u8 zero_addr[ETH_ALEN] = { 0 };
504 u16 data;
505
506 if (!mac)
507 mac = zero_addr;
508
509 offset |= 0x0020;
510 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
511
512 data = mac[0];
513 data |= mac[1] << 8;
514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
515 data = mac[2];
516 data |= mac[3] << 8;
517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 data = mac[4];
519 data |= mac[5] << 8;
520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
521}
522
523static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
524{
525 const u8 *mac;
526 const u8 *bssid;
527 u8 mac_bssid[ETH_ALEN * 2];
528 int i;
529 u32 tmp;
530
531 bssid = dev->wl->bssid;
532 mac = dev->wl->mac_addr;
533
534 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
535
536 memcpy(mac_bssid, mac, ETH_ALEN);
537 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
538
539 /* Write our MAC address and BSSID to template ram */
540 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
541 tmp = (u32) (mac_bssid[i + 0]);
542 tmp |= (u32) (mac_bssid[i + 1]) << 8;
543 tmp |= (u32) (mac_bssid[i + 2]) << 16;
544 tmp |= (u32) (mac_bssid[i + 3]) << 24;
545 b43_ram_write(dev, 0x20 + i, tmp);
546 }
547}
548
4150c572 549static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 550{
e4d6b795 551 b43_write_mac_bssid_templates(dev);
4150c572 552 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 553}
554
555static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
556{
557 /* slot_time is in usec. */
558 if (dev->phy.type != B43_PHYTYPE_G)
559 return;
560 b43_write16(dev, 0x684, 510 + slot_time);
561 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
562}
563
564static void b43_short_slot_timing_enable(struct b43_wldev *dev)
565{
566 b43_set_slot_time(dev, 9);
567 dev->short_slot = 1;
568}
569
570static void b43_short_slot_timing_disable(struct b43_wldev *dev)
571{
572 b43_set_slot_time(dev, 20);
573 dev->short_slot = 0;
574}
575
576/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
577 * Returns the _previously_ enabled IRQ mask.
578 */
579static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
580{
581 u32 old_mask;
582
583 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
584 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
585
586 return old_mask;
587}
588
589/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
590 * Returns the _previously_ enabled IRQ mask.
591 */
592static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
593{
594 u32 old_mask;
595
596 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
597 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
598
599 return old_mask;
600}
601
602/* Synchronize IRQ top- and bottom-half.
603 * IRQs must be masked before calling this.
604 * This must not be called with the irq_lock held.
605 */
606static void b43_synchronize_irq(struct b43_wldev *dev)
607{
608 synchronize_irq(dev->dev->irq);
609 tasklet_kill(&dev->isr_tasklet);
610}
611
612/* DummyTransmission function, as documented on
613 * http://bcm-specs.sipsolutions.net/DummyTransmission
614 */
615void b43_dummy_transmission(struct b43_wldev *dev)
616{
617 struct b43_phy *phy = &dev->phy;
618 unsigned int i, max_loop;
619 u16 value;
620 u32 buffer[5] = {
621 0x00000000,
622 0x00D40000,
623 0x00000000,
624 0x01000000,
625 0x00000000,
626 };
627
628 switch (phy->type) {
629 case B43_PHYTYPE_A:
630 max_loop = 0x1E;
631 buffer[0] = 0x000201CC;
632 break;
633 case B43_PHYTYPE_B:
634 case B43_PHYTYPE_G:
635 max_loop = 0xFA;
636 buffer[0] = 0x000B846E;
637 break;
638 default:
639 B43_WARN_ON(1);
640 return;
641 }
642
643 for (i = 0; i < 5; i++)
644 b43_ram_write(dev, i * 4, buffer[i]);
645
646 /* Commit writes */
647 b43_read32(dev, B43_MMIO_MACCTL);
648
649 b43_write16(dev, 0x0568, 0x0000);
650 b43_write16(dev, 0x07C0, 0x0000);
651 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
652 b43_write16(dev, 0x050C, value);
653 b43_write16(dev, 0x0508, 0x0000);
654 b43_write16(dev, 0x050A, 0x0000);
655 b43_write16(dev, 0x054C, 0x0000);
656 b43_write16(dev, 0x056A, 0x0014);
657 b43_write16(dev, 0x0568, 0x0826);
658 b43_write16(dev, 0x0500, 0x0000);
659 b43_write16(dev, 0x0502, 0x0030);
660
661 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
662 b43_radio_write16(dev, 0x0051, 0x0017);
663 for (i = 0x00; i < max_loop; i++) {
664 value = b43_read16(dev, 0x050E);
665 if (value & 0x0080)
666 break;
667 udelay(10);
668 }
669 for (i = 0x00; i < 0x0A; i++) {
670 value = b43_read16(dev, 0x050E);
671 if (value & 0x0400)
672 break;
673 udelay(10);
674 }
675 for (i = 0x00; i < 0x0A; i++) {
676 value = b43_read16(dev, 0x0690);
677 if (!(value & 0x0100))
678 break;
679 udelay(10);
680 }
681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
682 b43_radio_write16(dev, 0x0051, 0x0037);
683}
684
685static void key_write(struct b43_wldev *dev,
686 u8 index, u8 algorithm, const u8 * key)
687{
688 unsigned int i;
689 u32 offset;
690 u16 value;
691 u16 kidx;
692
693 /* Key index/algo block */
694 kidx = b43_kidx_to_fw(dev, index);
695 value = ((kidx << 4) | algorithm);
696 b43_shm_write16(dev, B43_SHM_SHARED,
697 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
698
699 /* Write the key to the Key Table Pointer offset */
700 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
701 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
702 value = key[i];
703 value |= (u16) (key[i + 1]) << 8;
704 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
705 }
706}
707
708static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
709{
710 u32 addrtmp[2] = { 0, 0, };
711 u8 per_sta_keys_start = 8;
712
713 if (b43_new_kidx_api(dev))
714 per_sta_keys_start = 4;
715
716 B43_WARN_ON(index < per_sta_keys_start);
717 /* We have two default TX keys and possibly two default RX keys.
718 * Physical mac 0 is mapped to physical key 4 or 8, depending
719 * on the firmware version.
720 * So we must adjust the index here.
721 */
722 index -= per_sta_keys_start;
723
724 if (addr) {
725 addrtmp[0] = addr[0];
726 addrtmp[0] |= ((u32) (addr[1]) << 8);
727 addrtmp[0] |= ((u32) (addr[2]) << 16);
728 addrtmp[0] |= ((u32) (addr[3]) << 24);
729 addrtmp[1] = addr[4];
730 addrtmp[1] |= ((u32) (addr[5]) << 8);
731 }
732
733 if (dev->dev->id.revision >= 5) {
734 /* Receive match transmitter address mechanism */
735 b43_shm_write32(dev, B43_SHM_RCMTA,
736 (index * 2) + 0, addrtmp[0]);
737 b43_shm_write16(dev, B43_SHM_RCMTA,
738 (index * 2) + 1, addrtmp[1]);
739 } else {
740 /* RXE (Receive Engine) and
741 * PSM (Programmable State Machine) mechanism
742 */
743 if (index < 8) {
744 /* TODO write to RCM 16, 19, 22 and 25 */
745 } else {
746 b43_shm_write32(dev, B43_SHM_SHARED,
747 B43_SHM_SH_PSM + (index * 6) + 0,
748 addrtmp[0]);
749 b43_shm_write16(dev, B43_SHM_SHARED,
750 B43_SHM_SH_PSM + (index * 6) + 4,
751 addrtmp[1]);
752 }
753 }
754}
755
756static void do_key_write(struct b43_wldev *dev,
757 u8 index, u8 algorithm,
758 const u8 * key, size_t key_len, const u8 * mac_addr)
759{
760 u8 buf[B43_SEC_KEYSIZE] = { 0, };
761 u8 per_sta_keys_start = 8;
762
763 if (b43_new_kidx_api(dev))
764 per_sta_keys_start = 4;
765
766 B43_WARN_ON(index >= dev->max_nr_keys);
767 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
768
769 if (index >= per_sta_keys_start)
770 keymac_write(dev, index, NULL); /* First zero out mac. */
771 if (key)
772 memcpy(buf, key, key_len);
773 key_write(dev, index, algorithm, buf);
774 if (index >= per_sta_keys_start)
775 keymac_write(dev, index, mac_addr);
776
777 dev->key[index].algorithm = algorithm;
778}
779
780static int b43_key_write(struct b43_wldev *dev,
781 int index, u8 algorithm,
782 const u8 * key, size_t key_len,
783 const u8 * mac_addr,
784 struct ieee80211_key_conf *keyconf)
785{
786 int i;
787 int sta_keys_start;
788
789 if (key_len > B43_SEC_KEYSIZE)
790 return -EINVAL;
791 for (i = 0; i < dev->max_nr_keys; i++) {
792 /* Check that we don't already have this key. */
793 B43_WARN_ON(dev->key[i].keyconf == keyconf);
794 }
795 if (index < 0) {
796 /* Either pairwise key or address is 00:00:00:00:00:00
797 * for transmit-only keys. Search the index. */
798 if (b43_new_kidx_api(dev))
799 sta_keys_start = 4;
800 else
801 sta_keys_start = 8;
802 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
803 if (!dev->key[i].keyconf) {
804 /* found empty */
805 index = i;
806 break;
807 }
808 }
809 if (index < 0) {
810 b43err(dev->wl, "Out of hardware key memory\n");
811 return -ENOSPC;
812 }
813 } else
814 B43_WARN_ON(index > 3);
815
816 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
817 if ((index <= 3) && !b43_new_kidx_api(dev)) {
818 /* Default RX key */
819 B43_WARN_ON(mac_addr);
820 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
821 }
822 keyconf->hw_key_idx = index;
823 dev->key[index].keyconf = keyconf;
824
825 return 0;
826}
827
828static int b43_key_clear(struct b43_wldev *dev, int index)
829{
830 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
831 return -EINVAL;
832 do_key_write(dev, index, B43_SEC_ALGO_NONE,
833 NULL, B43_SEC_KEYSIZE, NULL);
834 if ((index <= 3) && !b43_new_kidx_api(dev)) {
835 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
836 NULL, B43_SEC_KEYSIZE, NULL);
837 }
838 dev->key[index].keyconf = NULL;
839
840 return 0;
841}
842
843static void b43_clear_keys(struct b43_wldev *dev)
844{
845 int i;
846
847 for (i = 0; i < dev->max_nr_keys; i++)
848 b43_key_clear(dev, i);
849}
850
851void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
852{
853 u32 macctl;
854 u16 ucstat;
855 bool hwps;
856 bool awake;
857 int i;
858
859 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
860 (ps_flags & B43_PS_DISABLED));
861 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
862
863 if (ps_flags & B43_PS_ENABLED) {
864 hwps = 1;
865 } else if (ps_flags & B43_PS_DISABLED) {
866 hwps = 0;
867 } else {
868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
869 // and thus is not an AP and we are associated, set bit 25
870 }
871 if (ps_flags & B43_PS_AWAKE) {
872 awake = 1;
873 } else if (ps_flags & B43_PS_ASLEEP) {
874 awake = 0;
875 } else {
876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
878 // successful, set bit26
879 }
880
881/* FIXME: For now we force awake-on and hwps-off */
882 hwps = 0;
883 awake = 1;
884
885 macctl = b43_read32(dev, B43_MMIO_MACCTL);
886 if (hwps)
887 macctl |= B43_MACCTL_HWPS;
888 else
889 macctl &= ~B43_MACCTL_HWPS;
890 if (awake)
891 macctl |= B43_MACCTL_AWAKE;
892 else
893 macctl &= ~B43_MACCTL_AWAKE;
894 b43_write32(dev, B43_MMIO_MACCTL, macctl);
895 /* Commit write */
896 b43_read32(dev, B43_MMIO_MACCTL);
897 if (awake && dev->dev->id.revision >= 5) {
898 /* Wait for the microcode to wake up. */
899 for (i = 0; i < 100; i++) {
900 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
901 B43_SHM_SH_UCODESTAT);
902 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
903 break;
904 udelay(10);
905 }
906 }
907}
908
909/* Turn the Analog ON/OFF */
910static void b43_switch_analog(struct b43_wldev *dev, int on)
911{
912 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
913}
914
915void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
916{
917 u32 tmslow;
918 u32 macctl;
919
920 flags |= B43_TMSLOW_PHYCLKEN;
921 flags |= B43_TMSLOW_PHYRESET;
922 ssb_device_enable(dev->dev, flags);
923 msleep(2); /* Wait for the PLL to turn on. */
924
925 /* Now take the PHY out of Reset again */
926 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
927 tmslow |= SSB_TMSLOW_FGC;
928 tmslow &= ~B43_TMSLOW_PHYRESET;
929 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
930 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
931 msleep(1);
932 tmslow &= ~SSB_TMSLOW_FGC;
933 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
934 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
935 msleep(1);
936
937 /* Turn Analog ON */
938 b43_switch_analog(dev, 1);
939
940 macctl = b43_read32(dev, B43_MMIO_MACCTL);
941 macctl &= ~B43_MACCTL_GMODE;
942 if (flags & B43_TMSLOW_GMODE)
943 macctl |= B43_MACCTL_GMODE;
944 macctl |= B43_MACCTL_IHR_ENABLED;
945 b43_write32(dev, B43_MMIO_MACCTL, macctl);
946}
947
948static void handle_irq_transmit_status(struct b43_wldev *dev)
949{
950 u32 v0, v1;
951 u16 tmp;
952 struct b43_txstatus stat;
953
954 while (1) {
955 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
956 if (!(v0 & 0x00000001))
957 break;
958 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
959
960 stat.cookie = (v0 >> 16);
961 stat.seq = (v1 & 0x0000FFFF);
962 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
963 tmp = (v0 & 0x0000FFFF);
964 stat.frame_count = ((tmp & 0xF000) >> 12);
965 stat.rts_count = ((tmp & 0x0F00) >> 8);
966 stat.supp_reason = ((tmp & 0x001C) >> 2);
967 stat.pm_indicated = !!(tmp & 0x0080);
968 stat.intermediate = !!(tmp & 0x0040);
969 stat.for_ampdu = !!(tmp & 0x0020);
970 stat.acked = !!(tmp & 0x0002);
971
972 b43_handle_txstatus(dev, &stat);
973 }
974}
975
976static void drain_txstatus_queue(struct b43_wldev *dev)
977{
978 u32 dummy;
979
980 if (dev->dev->id.revision < 5)
981 return;
982 /* Read all entries from the microcode TXstatus FIFO
983 * and throw them away.
984 */
985 while (1) {
986 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
987 if (!(dummy & 0x00000001))
988 break;
989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
990 }
991}
992
993static u32 b43_jssi_read(struct b43_wldev *dev)
994{
995 u32 val = 0;
996
997 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
998 val <<= 16;
999 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1000
1001 return val;
1002}
1003
1004static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1005{
1006 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1008}
1009
1010static void b43_generate_noise_sample(struct b43_wldev *dev)
1011{
1012 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1013 b43_write32(dev, B43_MMIO_MACCMD,
1014 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1015 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1016}
1017
1018static void b43_calculate_link_quality(struct b43_wldev *dev)
1019{
1020 /* Top half of Link Quality calculation. */
1021
1022 if (dev->noisecalc.calculation_running)
1023 return;
1024 dev->noisecalc.channel_at_start = dev->phy.channel;
1025 dev->noisecalc.calculation_running = 1;
1026 dev->noisecalc.nr_samples = 0;
1027
1028 b43_generate_noise_sample(dev);
1029}
1030
1031static void handle_irq_noise(struct b43_wldev *dev)
1032{
1033 struct b43_phy *phy = &dev->phy;
1034 u16 tmp;
1035 u8 noise[4];
1036 u8 i, j;
1037 s32 average;
1038
1039 /* Bottom half of Link Quality calculation. */
1040
1041 B43_WARN_ON(!dev->noisecalc.calculation_running);
1042 if (dev->noisecalc.channel_at_start != phy->channel)
1043 goto drop_calculation;
1a09404a 1044 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1045 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1046 noise[2] == 0x7F || noise[3] == 0x7F)
1047 goto generate_new;
1048
1049 /* Get the noise samples. */
1050 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1051 i = dev->noisecalc.nr_samples;
1052 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1053 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1057 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1058 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1059 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1060 dev->noisecalc.nr_samples++;
1061 if (dev->noisecalc.nr_samples == 8) {
1062 /* Calculate the Link Quality by the noise samples. */
1063 average = 0;
1064 for (i = 0; i < 8; i++) {
1065 for (j = 0; j < 4; j++)
1066 average += dev->noisecalc.samples[i][j];
1067 }
1068 average /= (8 * 4);
1069 average *= 125;
1070 average += 64;
1071 average /= 128;
1072 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1073 tmp = (tmp / 128) & 0x1F;
1074 if (tmp >= 8)
1075 average += 2;
1076 else
1077 average -= 25;
1078 if (tmp == 8)
1079 average -= 72;
1080 else
1081 average -= 48;
1082
1083 dev->stats.link_noise = average;
1084 drop_calculation:
1085 dev->noisecalc.calculation_running = 0;
1086 return;
1087 }
1088 generate_new:
1089 b43_generate_noise_sample(dev);
1090}
1091
1092static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1093{
1094 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1095 ///TODO: PS TBTT
1096 } else {
1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098 b43_power_saving_ctl_bits(dev, 0);
1099 }
e4d6b795 1100 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
aa6c7ae2 1101 dev->dfq_valid = 1;
e4d6b795
MB		 1102}
1103
1104static void handle_irq_atim_end(struct b43_wldev *dev)
1105{
aa6c7ae2
MB		 1106 if (dev->dfq_valid) {
1107 b43_write32(dev, B43_MMIO_MACCMD,
1108 b43_read32(dev, B43_MMIO_MACCMD)
1109 | B43_MACCMD_DFQ_VALID);
1110 dev->dfq_valid = 0;
1111 }
e4d6b795
MB		 1112}
1113
1114static void handle_irq_pmq(struct b43_wldev *dev)
1115{
1116 u32 tmp;
1117
1118 //TODO: AP mode.
1119
1120 while (1) {
1121 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1122 if (!(tmp & 0x00000008))
1123 break;
1124 }
1125 /* 16bit write is odd, but correct. */
1126 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1127}
1128
1129static void b43_write_template_common(struct b43_wldev *dev,
1130 const u8 * data, u16 size,
1131 u16 ram_offset,
1132 u16 shm_size_offset, u8 rate)
1133{
1134 u32 i, tmp;
1135 struct b43_plcp_hdr4 plcp;
1136
1137 plcp.data = 0;
1138 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1139 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1140 ram_offset += sizeof(u32);
1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142 * So leave the first two bytes of the next write blank.
1143 */
1144 tmp = (u32) (data[0]) << 16;
1145 tmp |= (u32) (data[1]) << 24;
1146 b43_ram_write(dev, ram_offset, tmp);
1147 ram_offset += sizeof(u32);
1148 for (i = 2; i < size; i += sizeof(u32)) {
1149 tmp = (u32) (data[i + 0]);
1150 if (i + 1 < size)
1151 tmp |= (u32) (data[i + 1]) << 8;
1152 if (i + 2 < size)
1153 tmp |= (u32) (data[i + 2]) << 16;
1154 if (i + 3 < size)
1155 tmp |= (u32) (data[i + 3]) << 24;
1156 b43_ram_write(dev, ram_offset + i - 2, tmp);
1157 }
1158 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1159 size + sizeof(struct b43_plcp_hdr6));
1160}
1161
1162static void b43_write_beacon_template(struct b43_wldev *dev,
1163 u16 ram_offset,
1164 u16 shm_size_offset, u8 rate)
1165{
47f76ca3 1166 unsigned int i, len, variable_len;
e66fee6a
MB		 1167 const struct ieee80211_mgmt *bcn;
1168 const u8 *ie;
1169 bool tim_found = 0;
e4d6b795 1170
e66fee6a
MB		 1171 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1172 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1173 0x200 - sizeof(struct b43_plcp_hdr6));
e66fee6a
MB		 1174
1175 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1176 len, ram_offset, shm_size_offset, rate);
e66fee6a
MB		 1177
1178 /* Find the position of the TIM and the DTIM_period value
1179 * and write them to SHM. */
1180 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1181 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1182 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1183 uint8_t ie_id, ie_len;
1184
1185 ie_id = ie[i];
1186 ie_len = ie[i + 1];
1187 if (ie_id == 5) {
1188 u16 tim_position;
1189 u16 dtim_period;
1190 /* This is the TIM Information Element */
1191
1192 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1193 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1194 break;
1195 /* A valid TIM is at least 4 bytes long. */
1196 if (ie_len < 4)
1197 break;
1198 tim_found = 1;
1199
1200 tim_position = sizeof(struct b43_plcp_hdr6);
1201 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1202 tim_position += i;
1203
1204 dtim_period = ie[i + 3];
1205
1206 b43_shm_write16(dev, B43_SHM_SHARED,
1207 B43_SHM_SH_TIMBPOS, tim_position);
1208 b43_shm_write16(dev, B43_SHM_SHARED,
1209 B43_SHM_SH_DTIMPER, dtim_period);
1210 break;
1211 }
1212 i += ie_len + 2;
1213 }
1214 if (!tim_found) {
1215 b43warn(dev->wl, "Did not find a valid TIM IE in "
1216 "the beacon template packet. AP or IBSS operation "
1217 "may be broken.\n");
1218 }
e4d6b795
MB		 1219}
1220
1221static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1222 u16 shm_offset, u16 size, u8 rate)
1223{
1224 struct b43_plcp_hdr4 plcp;
1225 u32 tmp;
1226 __le16 dur;
1227
1228 plcp.data = 0;
1229 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1230 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1231 dev->wl->vif, size,
e4d6b795
MB		 1232 B43_RATE_TO_BASE100KBPS(rate));
1233 /* Write PLCP in two parts and timing for packet transfer */
1234 tmp = le32_to_cpu(plcp.data);
1235 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1237 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1238}
1239
1240/* Instead of using custom probe response template, this function
1241 * just patches custom beacon template by:
1242 * 1) Changing packet type
1243 * 2) Patching duration field
1244 * 3) Stripping TIM
1245 */
e66fee6a
MB		 1246static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1247 u16 *dest_size, u8 rate)
e4d6b795
MB		 1248{
1249 const u8 *src_data;
1250 u8 *dest_data;
1251 u16 src_size, elem_size, src_pos, dest_pos;
1252 __le16 dur;
1253 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1254 size_t ie_start;
1255
1256 src_size = dev->wl->current_beacon->len;
1257 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1258
e66fee6a
MB		 1259 /* Get the start offset of the variable IEs in the packet. */
1260 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1261 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1262
e66fee6a 1263 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1264 return NULL;
e4d6b795
MB		 1265
1266 dest_data = kmalloc(src_size, GFP_ATOMIC);
1267 if (unlikely(!dest_data))
1268 return NULL;
1269
e66fee6a
MB		 1270 /* Copy the static data and all Information Elements, except the TIM. */
1271 memcpy(dest_data, src_data, ie_start);
1272 src_pos = ie_start;
1273 dest_pos = ie_start;
1274 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1275 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1276 if (src_data[src_pos] == 5) {
1277 /* This is the TIM. */
1278 continue;
e4d6b795 1279 }
e66fee6a
MB		 1280 memcpy(dest_data + dest_pos, src_data + src_pos,
1281 elem_size);
1282 dest_pos += elem_size;
e4d6b795
MB		 1283 }
1284 *dest_size = dest_pos;
1285 hdr = (struct ieee80211_hdr *)dest_data;
1286
1287 /* Set the frame control. */
1288 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1289 IEEE80211_STYPE_PROBE_RESP);
1290 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1291 dev->wl->vif, *dest_size,
e4d6b795
MB		 1292 B43_RATE_TO_BASE100KBPS(rate));
1293 hdr->duration_id = dur;
1294
1295 return dest_data;
1296}
1297
1298static void b43_write_probe_resp_template(struct b43_wldev *dev,
1299 u16 ram_offset,
1300 u16 shm_size_offset, u8 rate)
1301{
e66fee6a 1302 const u8 *probe_resp_data;
e4d6b795
MB		 1303 u16 size;
1304
e66fee6a 1305 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1306 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1307 if (unlikely(!probe_resp_data))
1308 return;
1309
1310 /* Looks like PLCP headers plus packet timings are stored for
1311 * all possible basic rates
1312 */
1313 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1314 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1315 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1316 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1317
1318 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1319 b43_write_template_common(dev, probe_resp_data,
1320 size, ram_offset, shm_size_offset, rate);
1321 kfree(probe_resp_data);
1322}
1323
d4df6f1a
MB		 1324/* Asynchronously update the packet templates in template RAM.
1325 * Locking: Requires wl->irq_lock to be locked. */
e66fee6a 1326static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
e4d6b795 1327{
e66fee6a
MB		 1328 /* This is the top half of the ansynchronous beacon update.
1329 * The bottom half is the beacon IRQ.
1330 * Beacon update must be asynchronous to avoid sending an
1331 * invalid beacon. This can happen for example, if the firmware
1332 * transmits a beacon while we are updating it. */
e4d6b795 1333
e66fee6a
MB		 1334 if (wl->current_beacon)
1335 dev_kfree_skb_any(wl->current_beacon);
1336 wl->current_beacon = beacon;
1337 wl->beacon0_uploaded = 0;
1338 wl->beacon1_uploaded = 0;
e4d6b795
MB		 1339}
1340
1341static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1342{
1343 u32 tmp;
1344 u16 i, len;
1345
1346 len = min((u16) ssid_len, (u16) 0x100);
1347 for (i = 0; i < len; i += sizeof(u32)) {
1348 tmp = (u32) (ssid[i + 0]);
1349 if (i + 1 < len)
1350 tmp |= (u32) (ssid[i + 1]) << 8;
1351 if (i + 2 < len)
1352 tmp |= (u32) (ssid[i + 2]) << 16;
1353 if (i + 3 < len)
1354 tmp |= (u32) (ssid[i + 3]) << 24;
1355 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1356 }
1357 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1358}
1359
1360static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1361{
1362 b43_time_lock(dev);
1363 if (dev->dev->id.revision >= 3) {
1364 b43_write32(dev, 0x188, (beacon_int << 16));
1365 } else {
1366 b43_write16(dev, 0x606, (beacon_int >> 6));
1367 b43_write16(dev, 0x610, beacon_int);
1368 }
1369 b43_time_unlock(dev);
1370}
1371
1372static void handle_irq_beacon(struct b43_wldev *dev)
1373{
e66fee6a
MB		 1374 struct b43_wl *wl = dev->wl;
1375 u32 cmd;
e4d6b795 1376
e66fee6a 1377 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
e4d6b795
MB		 1378 return;
1379
e66fee6a 1380 /* This is the bottom half of the asynchronous beacon update. */
e4d6b795 1381
e66fee6a
MB		 1382 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1383 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1384 if (!wl->beacon0_uploaded) {
1385 b43_write_beacon_template(dev, 0x68, 0x18,
1386 B43_CCK_RATE_1MB);
1387 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1388 B43_CCK_RATE_11MB);
1389 wl->beacon0_uploaded = 1;
1390 }
1391 cmd |= B43_MACCMD_BEACON0_VALID;
e4d6b795 1392 }
e66fee6a
MB		 1393 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1394 if (!wl->beacon1_uploaded) {
1395 b43_write_beacon_template(dev, 0x468, 0x1A,
1396 B43_CCK_RATE_1MB);
1397 wl->beacon1_uploaded = 1;
1398 }
1399 cmd |= B43_MACCMD_BEACON1_VALID;
e4d6b795 1400 }
e66fee6a 1401 b43_write32(dev, B43_MMIO_MACCMD, cmd);
e4d6b795
MB		 1402}
1403
1404static void handle_irq_ucode_debug(struct b43_wldev *dev)
1405{
1406 //TODO
1407}
1408
1409/* Interrupt handler bottom-half */
1410static void b43_interrupt_tasklet(struct b43_wldev *dev)
1411{
1412 u32 reason;
1413 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1414 u32 merged_dma_reason = 0;
21954c36 1415 int i;
e4d6b795
MB		 1416 unsigned long flags;
1417
1418 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1419
1420 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1421
1422 reason = dev->irq_reason;
1423 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1424 dma_reason[i] = dev->dma_reason[i];
1425 merged_dma_reason |= dma_reason[i];
1426 }
1427
1428 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1429 b43err(dev->wl, "MAC transmission error\n");
1430
00e0b8cb 1431 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1432 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1433 rmb();
1434 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1435 atomic_set(&dev->phy.txerr_cnt,
1436 B43_PHY_TX_BADNESS_LIMIT);
1437 b43err(dev->wl, "Too many PHY TX errors, "
1438 "restarting the controller\n");
1439 b43_controller_restart(dev, "PHY TX errors");
1440 }
1441 }
e4d6b795
MB		 1442
1443 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1444 B43_DMAIRQ_NONFATALMASK))) {
1445 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1446 b43err(dev->wl, "Fatal DMA error: "
1447 "0x%08X, 0x%08X, 0x%08X, "
1448 "0x%08X, 0x%08X, 0x%08X\n",
1449 dma_reason[0], dma_reason[1],
1450 dma_reason[2], dma_reason[3],
1451 dma_reason[4], dma_reason[5]);
1452 b43_controller_restart(dev, "DMA error");
1453 mmiowb();
1454 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1455 return;
1456 }
1457 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1458 b43err(dev->wl, "DMA error: "
1459 "0x%08X, 0x%08X, 0x%08X, "
1460 "0x%08X, 0x%08X, 0x%08X\n",
1461 dma_reason[0], dma_reason[1],
1462 dma_reason[2], dma_reason[3],
1463 dma_reason[4], dma_reason[5]);
1464 }
1465 }
1466
1467 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1468 handle_irq_ucode_debug(dev);
1469 if (reason & B43_IRQ_TBTT_INDI)
1470 handle_irq_tbtt_indication(dev);
1471 if (reason & B43_IRQ_ATIM_END)
1472 handle_irq_atim_end(dev);
1473 if (reason & B43_IRQ_BEACON)
1474 handle_irq_beacon(dev);
1475 if (reason & B43_IRQ_PMQ)
1476 handle_irq_pmq(dev);
21954c36
MB		 1477 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1478 ;/* TODO */
1479 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1480 handle_irq_noise(dev);
1481
1482 /* Check the DMA reason registers for received data. */
03b29773
MB		 1483 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1484 b43_dma_rx(dev->dma.rx_ring0);
1485 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1486 b43_dma_rx(dev->dma.rx_ring3);
e4d6b795
MB		 1487 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1488 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1489 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1490 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1491
21954c36 1492 if (reason & B43_IRQ_TX_OK)
e4d6b795 1493 handle_irq_transmit_status(dev);
e4d6b795 1494
e4d6b795
MB		 1495 b43_interrupt_enable(dev, dev->irq_savedstate);
1496 mmiowb();
1497 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1498}
1499
e4d6b795
MB		 1500static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1501{
e4d6b795
MB		 1502 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1503
1504 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1505 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1506 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1507 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1508 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1509 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1510}
1511
1512/* Interrupt handler top-half */
1513static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1514{
1515 irqreturn_t ret = IRQ_NONE;
1516 struct b43_wldev *dev = dev_id;
1517 u32 reason;
1518
1519 if (!dev)
1520 return IRQ_NONE;
1521
1522 spin_lock(&dev->wl->irq_lock);
1523
1524 if (b43_status(dev) < B43_STAT_STARTED)
1525 goto out;
1526 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1527 if (reason == 0xffffffff) /* shared IRQ */
1528 goto out;
1529 ret = IRQ_HANDLED;
1530 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1531 if (!reason)
1532 goto out;
1533
1534 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1535 & 0x0001DC00;
1536 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1537 & 0x0000DC00;
1538 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1539 & 0x0000DC00;
1540 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1541 & 0x0001DC00;
1542 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1543 & 0x0000DC00;
1544 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1545 & 0x0000DC00;
1546
1547 b43_interrupt_ack(dev, reason);
1548 /* disable all IRQs. They are enabled again in the bottom half. */
1549 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1550 /* save the reason code and call our bottom half. */
1551 dev->irq_reason = reason;
1552 tasklet_schedule(&dev->isr_tasklet);
1553 out:
1554 mmiowb();
1555 spin_unlock(&dev->wl->irq_lock);
1556
1557 return ret;
1558}
1559
1560static void b43_release_firmware(struct b43_wldev *dev)
1561{
1562 release_firmware(dev->fw.ucode);
1563 dev->fw.ucode = NULL;
1564 release_firmware(dev->fw.pcm);
1565 dev->fw.pcm = NULL;
1566 release_firmware(dev->fw.initvals);
1567 dev->fw.initvals = NULL;
1568 release_firmware(dev->fw.initvals_band);
1569 dev->fw.initvals_band = NULL;
1570}
1571
1572static void b43_print_fw_helptext(struct b43_wl *wl)
1573{
1574 b43err(wl, "You must go to "
354807e0 1575 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
e4d6b795
MB		 1576 "and download the correct firmware (version 4).\n");
1577}
1578
1579static int do_request_fw(struct b43_wldev *dev,
1580 const char *name,
1581 const struct firmware **fw)
1582{
1a09404a 1583 char path[sizeof(modparam_fwpostfix) + 32];
e4d6b795
MB		 1584 struct b43_fw_header *hdr;
1585 u32 size;
1586 int err;
1587
1588 if (!name)
1589 return 0;
1590
1591 snprintf(path, ARRAY_SIZE(path),
1592 "b43%s/%s.fw",
1593 modparam_fwpostfix, name);
1594 err = request_firmware(fw, path, dev->dev->dev);
1595 if (err) {
1596 b43err(dev->wl, "Firmware file \"%s\" not found "
1597 "or load failed.\n", path);
1598 return err;
1599 }
1600 if ((*fw)->size < sizeof(struct b43_fw_header))
1601 goto err_format;
1602 hdr = (struct b43_fw_header *)((*fw)->data);
1603 switch (hdr->type) {
1604 case B43_FW_TYPE_UCODE:
1605 case B43_FW_TYPE_PCM:
1606 size = be32_to_cpu(hdr->size);
1607 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1608 goto err_format;
1609 /* fallthrough */
1610 case B43_FW_TYPE_IV:
1611 if (hdr->ver != 1)
1612 goto err_format;
1613 break;
1614 default:
1615 goto err_format;
1616 }
1617
1618 return err;
1619
1620err_format:
1621 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1622 return -EPROTO;
1623}
1624
1625static int b43_request_firmware(struct b43_wldev *dev)
1626{
1627 struct b43_firmware *fw = &dev->fw;
1628 const u8 rev = dev->dev->id.revision;
1629 const char *filename;
1630 u32 tmshigh;
1631 int err;
1632
1633 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1634 if (!fw->ucode) {
1635 if ((rev >= 5) && (rev <= 10))
1636 filename = "ucode5";
1637 else if ((rev >= 11) && (rev <= 12))
1638 filename = "ucode11";
1639 else if (rev >= 13)
1640 filename = "ucode13";
1641 else
1642 goto err_no_ucode;
1643 err = do_request_fw(dev, filename, &fw->ucode);
1644 if (err)
1645 goto err_load;
1646 }
1647 if (!fw->pcm) {
1648 if ((rev >= 5) && (rev <= 10))
1649 filename = "pcm5";
1650 else if (rev >= 11)
1651 filename = NULL;
1652 else
1653 goto err_no_pcm;
1654 err = do_request_fw(dev, filename, &fw->pcm);
1655 if (err)
1656 goto err_load;
1657 }
1658 if (!fw->initvals) {
1659 switch (dev->phy.type) {
1660 case B43_PHYTYPE_A:
1661 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1662 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1663 filename = "a0g1initvals5";
1664 else
1665 filename = "a0g0initvals5";
1666 } else
1667 goto err_no_initvals;
1668 break;
1669 case B43_PHYTYPE_G:
1670 if ((rev >= 5) && (rev <= 10))
1671 filename = "b0g0initvals5";
1672 else if (rev >= 13)
1673 filename = "lp0initvals13";
1674 else
1675 goto err_no_initvals;
1676 break;
dd0d43ea
MB		 1677 case B43_PHYTYPE_N:
1678 if ((rev >= 11) && (rev <= 12))
1679 filename = "n0initvals11";
1680 else
1681 goto err_no_initvals;
1682 break;
e4d6b795
MB		 1683 default:
1684 goto err_no_initvals;
1685 }
1686 err = do_request_fw(dev, filename, &fw->initvals);
1687 if (err)
1688 goto err_load;
1689 }
1690 if (!fw->initvals_band) {
1691 switch (dev->phy.type) {
1692 case B43_PHYTYPE_A:
1693 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1694 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1695 filename = "a0g1bsinitvals5";
1696 else
1697 filename = "a0g0bsinitvals5";
1698 } else if (rev >= 11)
1699 filename = NULL;
1700 else
1701 goto err_no_initvals;
1702 break;
1703 case B43_PHYTYPE_G:
1704 if ((rev >= 5) && (rev <= 10))
1705 filename = "b0g0bsinitvals5";
1706 else if (rev >= 11)
1707 filename = NULL;
1708 else
1709 goto err_no_initvals;
1710 break;
dd0d43ea
MB		 1711 case B43_PHYTYPE_N:
1712 if ((rev >= 11) && (rev <= 12))
1713 filename = "n0bsinitvals11";
1714 else
1715 goto err_no_initvals;
1716 break;
e4d6b795
MB		 1717 default:
1718 goto err_no_initvals;
1719 }
1720 err = do_request_fw(dev, filename, &fw->initvals_band);
1721 if (err)
1722 goto err_load;
1723 }
1724
1725 return 0;
1726
1727err_load:
1728 b43_print_fw_helptext(dev->wl);
1729 goto error;
1730
1731err_no_ucode:
1732 err = -ENODEV;
1733 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1734 goto error;
1735
1736err_no_pcm:
1737 err = -ENODEV;
1738 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1739 goto error;
1740
1741err_no_initvals:
1742 err = -ENODEV;
1743 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1744 "core rev %u\n", dev->phy.type, rev);
1745 goto error;
1746
1747error:
1748 b43_release_firmware(dev);
1749 return err;
1750}
1751
1752static int b43_upload_microcode(struct b43_wldev *dev)
1753{
1754 const size_t hdr_len = sizeof(struct b43_fw_header);
1755 const __be32 *data;
1756 unsigned int i, len;
1757 u16 fwrev, fwpatch, fwdate, fwtime;
1758 u32 tmp;
1759 int err = 0;
1760
1761 /* Upload Microcode. */
1762 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1763 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1764 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1765 for (i = 0; i < len; i++) {
1766 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1767 udelay(10);
1768 }
1769
1770 if (dev->fw.pcm) {
1771 /* Upload PCM data. */
1772 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1773 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1774 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1775 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1776 /* No need for autoinc bit in SHM_HW */
1777 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1778 for (i = 0; i < len; i++) {
1779 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1780 udelay(10);
1781 }
1782 }
1783
1784 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1785 b43_write32(dev, B43_MMIO_MACCTL,
1786 B43_MACCTL_PSM_RUN |
1787 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1788
1789 /* Wait for the microcode to load and respond */
1790 i = 0;
1791 while (1) {
1792 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1793 if (tmp == B43_IRQ_MAC_SUSPENDED)
1794 break;
1795 i++;
1796 if (i >= 50) {
1797 b43err(dev->wl, "Microcode not responding\n");
1798 b43_print_fw_helptext(dev->wl);
1799 err = -ENODEV;
1800 goto out;
1801 }
1802 udelay(10);
1803 }
1804 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1805
1806 /* Get and check the revisions. */
1807 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1808 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1809 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1810 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1811
1812 if (fwrev <= 0x128) {
1813 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1814 "binary drivers older than version 4.x is unsupported. "
1815 "You must upgrade your firmware files.\n");
1816 b43_print_fw_helptext(dev->wl);
1817 b43_write32(dev, B43_MMIO_MACCTL, 0);
1818 err = -EOPNOTSUPP;
1819 goto out;
1820 }
1821 b43dbg(dev->wl, "Loading firmware version %u.%u "
1822 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1823 fwrev, fwpatch,
1824 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1825 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1826
1827 dev->fw.rev = fwrev;
1828 dev->fw.patch = fwpatch;
1829
1830 out:
1831 return err;
1832}
1833
1834static int b43_write_initvals(struct b43_wldev *dev,
1835 const struct b43_iv *ivals,
1836 size_t count,
1837 size_t array_size)
1838{
1839 const struct b43_iv *iv;
1840 u16 offset;
1841 size_t i;
1842 bool bit32;
1843
1844 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1845 iv = ivals;
1846 for (i = 0; i < count; i++) {
1847 if (array_size < sizeof(iv->offset_size))
1848 goto err_format;
1849 array_size -= sizeof(iv->offset_size);
1850 offset = be16_to_cpu(iv->offset_size);
1851 bit32 = !!(offset & B43_IV_32BIT);
1852 offset &= B43_IV_OFFSET_MASK;
1853 if (offset >= 0x1000)
1854 goto err_format;
1855 if (bit32) {
1856 u32 value;
1857
1858 if (array_size < sizeof(iv->data.d32))
1859 goto err_format;
1860 array_size -= sizeof(iv->data.d32);
1861
1862 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1863 b43_write32(dev, offset, value);
1864
1865 iv = (const struct b43_iv *)((const uint8_t *)iv +
1866 sizeof(__be16) +
1867 sizeof(__be32));
1868 } else {
1869 u16 value;
1870
1871 if (array_size < sizeof(iv->data.d16))
1872 goto err_format;
1873 array_size -= sizeof(iv->data.d16);
1874
1875 value = be16_to_cpu(iv->data.d16);
1876 b43_write16(dev, offset, value);
1877
1878 iv = (const struct b43_iv *)((const uint8_t *)iv +
1879 sizeof(__be16) +
1880 sizeof(__be16));
1881 }
1882 }
1883 if (array_size)
1884 goto err_format;
1885
1886 return 0;
1887
1888err_format:
1889 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1890 b43_print_fw_helptext(dev->wl);
1891
1892 return -EPROTO;
1893}
1894
1895static int b43_upload_initvals(struct b43_wldev *dev)
1896{
1897 const size_t hdr_len = sizeof(struct b43_fw_header);
1898 const struct b43_fw_header *hdr;
1899 struct b43_firmware *fw = &dev->fw;
1900 const struct b43_iv *ivals;
1901 size_t count;
1902 int err;
1903
1904 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1905 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1906 count = be32_to_cpu(hdr->size);
1907 err = b43_write_initvals(dev, ivals, count,
1908 fw->initvals->size - hdr_len);
1909 if (err)
1910 goto out;
1911 if (fw->initvals_band) {
1912 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1913 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1914 count = be32_to_cpu(hdr->size);
1915 err = b43_write_initvals(dev, ivals, count,
1916 fw->initvals_band->size - hdr_len);
1917 if (err)
1918 goto out;
1919 }
1920out:
1921
1922 return err;
1923}
1924
1925/* Initialize the GPIOs
1926 * http://bcm-specs.sipsolutions.net/GPIO
1927 */
1928static int b43_gpio_init(struct b43_wldev *dev)
1929{
1930 struct ssb_bus *bus = dev->dev->bus;
1931 struct ssb_device *gpiodev, *pcidev = NULL;
1932 u32 mask, set;
1933
1934 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1935 & ~B43_MACCTL_GPOUTSMSK);
1936
e4d6b795
MB		 1937 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1938 | 0x000F);
1939
1940 mask = 0x0000001F;
1941 set = 0x0000000F;
1942 if (dev->dev->bus->chip_id == 0x4301) {
1943 mask |= 0x0060;
1944 set |= 0x0060;
1945 }
1946 if (0 /* FIXME: conditional unknown */ ) {
1947 b43_write16(dev, B43_MMIO_GPIO_MASK,
1948 b43_read16(dev, B43_MMIO_GPIO_MASK)
1949 | 0x0100);
1950 mask |= 0x0180;
1951 set |= 0x0180;
1952 }
95de2841 1953 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 1954 b43_write16(dev, B43_MMIO_GPIO_MASK,
1955 b43_read16(dev, B43_MMIO_GPIO_MASK)
1956 | 0x0200);
1957 mask |= 0x0200;
1958 set |= 0x0200;
1959 }
1960 if (dev->dev->id.revision >= 2)
1961 mask |= 0x0010; /* FIXME: This is redundant. */
1962
1963#ifdef CONFIG_SSB_DRIVER_PCICORE
1964 pcidev = bus->pcicore.dev;
1965#endif
1966 gpiodev = bus->chipco.dev ? : pcidev;
1967 if (!gpiodev)
1968 return 0;
1969 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1970 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1971 & mask) | set);
1972
1973 return 0;
1974}
1975
1976/* Turn off all GPIO stuff. Call this on module unload, for example. */
1977static void b43_gpio_cleanup(struct b43_wldev *dev)
1978{
1979 struct ssb_bus *bus = dev->dev->bus;
1980 struct ssb_device *gpiodev, *pcidev = NULL;
1981
1982#ifdef CONFIG_SSB_DRIVER_PCICORE
1983 pcidev = bus->pcicore.dev;
1984#endif
1985 gpiodev = bus->chipco.dev ? : pcidev;
1986 if (!gpiodev)
1987 return;
1988 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1989}
1990
1991/* http://bcm-specs.sipsolutions.net/EnableMac */
1992void b43_mac_enable(struct b43_wldev *dev)
1993{
1994 dev->mac_suspended--;
1995 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 1996 B43_WARN_ON(irqs_disabled());
e4d6b795
MB		 1997 if (dev->mac_suspended == 0) {
1998 b43_write32(dev, B43_MMIO_MACCTL,
1999 b43_read32(dev, B43_MMIO_MACCTL)
2000 | B43_MACCTL_ENABLED);
2001 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2002 B43_IRQ_MAC_SUSPENDED);
2003 /* Commit writes */
2004 b43_read32(dev, B43_MMIO_MACCTL);
2005 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2006 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 2007
2008 /* Re-enable IRQs. */
2009 spin_lock_irq(&dev->wl->irq_lock);
2010 b43_interrupt_enable(dev, dev->irq_savedstate);
2011 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 2012 }
2013}
2014
2015/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2016void b43_mac_suspend(struct b43_wldev *dev)
2017{
2018 int i;
2019 u32 tmp;
2020
05b64b36
MB		 2021 might_sleep();
2022 B43_WARN_ON(irqs_disabled());
e4d6b795 2023 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2024
e4d6b795 2025 if (dev->mac_suspended == 0) {
05b64b36
MB		 2026 /* Mask IRQs before suspending MAC. Otherwise
2027 * the MAC stays busy and won't suspend. */
2028 spin_lock_irq(&dev->wl->irq_lock);
2029 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2030 spin_unlock_irq(&dev->wl->irq_lock);
2031 b43_synchronize_irq(dev);
2032 dev->irq_savedstate = tmp;
2033
e4d6b795
MB		 2034 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2035 b43_write32(dev, B43_MMIO_MACCTL,
2036 b43_read32(dev, B43_MMIO_MACCTL)
2037 & ~B43_MACCTL_ENABLED);
2038 /* force pci to flush the write */
2039 b43_read32(dev, B43_MMIO_MACCTL);
05b64b36 2040 for (i = 40; i; i--) {
e4d6b795
MB		 2041 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2042 if (tmp & B43_IRQ_MAC_SUSPENDED)
2043 goto out;
05b64b36 2044 msleep(1);
e4d6b795
MB		 2045 }
2046 b43err(dev->wl, "MAC suspend failed\n");
2047 }
05b64b36 2048out:
e4d6b795
MB		 2049 dev->mac_suspended++;
2050}
2051
2052static void b43_adjust_opmode(struct b43_wldev *dev)
2053{
2054 struct b43_wl *wl = dev->wl;
2055 u32 ctl;
2056 u16 cfp_pretbtt;
2057
2058 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2059 /* Reset status to STA infrastructure mode. */
2060 ctl &= ~B43_MACCTL_AP;
2061 ctl &= ~B43_MACCTL_KEEP_CTL;
2062 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2063 ctl &= ~B43_MACCTL_KEEP_BAD;
2064 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2065 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2066 ctl |= B43_MACCTL_INFRA;
2067
4150c572
JB		 2068 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2069 ctl |= B43_MACCTL_AP;
2070 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2071 ctl &= ~B43_MACCTL_INFRA;
2072
2073 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2074 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2075 if (wl->filter_flags & FIF_FCSFAIL)
2076 ctl |= B43_MACCTL_KEEP_BAD;
2077 if (wl->filter_flags & FIF_PLCPFAIL)
2078 ctl |= B43_MACCTL_KEEP_BADPLCP;
2079 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2080 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2081 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2082 ctl |= B43_MACCTL_BEACPROMISC;
2083
e4d6b795
MB		 2084 /* Workaround: On old hardware the HW-MAC-address-filter
2085 * doesn't work properly, so always run promisc in filter
2086 * it in software. */
2087 if (dev->dev->id.revision <= 4)
2088 ctl |= B43_MACCTL_PROMISC;
2089
2090 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2091
2092 cfp_pretbtt = 2;
2093 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2094 if (dev->dev->bus->chip_id == 0x4306 &&
2095 dev->dev->bus->chip_rev == 3)
2096 cfp_pretbtt = 100;
2097 else
2098 cfp_pretbtt = 50;
2099 }
2100 b43_write16(dev, 0x612, cfp_pretbtt);
2101}
2102
2103static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2104{
2105 u16 offset;
2106
2107 if (is_ofdm) {
2108 offset = 0x480;
2109 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2110 } else {
2111 offset = 0x4C0;
2112 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2113 }
2114 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2115 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2116}
2117
2118static void b43_rate_memory_init(struct b43_wldev *dev)
2119{
2120 switch (dev->phy.type) {
2121 case B43_PHYTYPE_A:
2122 case B43_PHYTYPE_G:
2123 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2124 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2125 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2126 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2127 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2128 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2129 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2130 if (dev->phy.type == B43_PHYTYPE_A)
2131 break;
2132 /* fallthrough */
2133 case B43_PHYTYPE_B:
2134 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2135 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2136 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2137 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2138 break;
2139 default:
2140 B43_WARN_ON(1);
2141 }
2142}
2143
2144/* Set the TX-Antenna for management frames sent by firmware. */
2145static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2146{
2147 u16 ant = 0;
2148 u16 tmp;
2149
2150 switch (antenna) {
2151 case B43_ANTENNA0:
2152 ant |= B43_TX4_PHY_ANT0;
2153 break;
2154 case B43_ANTENNA1:
2155 ant |= B43_TX4_PHY_ANT1;
2156 break;
2157 case B43_ANTENNA_AUTO:
2158 ant |= B43_TX4_PHY_ANTLAST;
2159 break;
2160 default:
2161 B43_WARN_ON(1);
2162 }
2163
2164 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2165
2166 /* For Beacons */
2167 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2168 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2169 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2170 /* For ACK/CTS */
2171 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2172 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2173 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2174 /* For Probe Resposes */
2175 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2176 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2177 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2178}
2179
2180/* This is the opposite of b43_chip_init() */
2181static void b43_chip_exit(struct b43_wldev *dev)
2182{
8e9f7529 2183 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 2184 b43_gpio_cleanup(dev);
2185 /* firmware is released later */
2186}
2187
2188/* Initialize the chip
2189 * http://bcm-specs.sipsolutions.net/ChipInit
2190 */
2191static int b43_chip_init(struct b43_wldev *dev)
2192{
2193 struct b43_phy *phy = &dev->phy;
2194 int err, tmp;
2195 u32 value32;
2196 u16 value16;
2197
2198 b43_write32(dev, B43_MMIO_MACCTL,
2199 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2200
2201 err = b43_request_firmware(dev);
2202 if (err)
2203 goto out;
2204 err = b43_upload_microcode(dev);
2205 if (err)
2206 goto out; /* firmware is released later */
2207
2208 err = b43_gpio_init(dev);
2209 if (err)
2210 goto out; /* firmware is released later */
21954c36 2211
e4d6b795
MB		 2212 err = b43_upload_initvals(dev);
2213 if (err)
1a8d1227 2214 goto err_gpio_clean;
e4d6b795 2215 b43_radio_turn_on(dev);
e4d6b795
MB		 2216
2217 b43_write16(dev, 0x03E6, 0x0000);
2218 err = b43_phy_init(dev);
2219 if (err)
2220 goto err_radio_off;
2221
2222 /* Select initial Interference Mitigation. */
2223 tmp = phy->interfmode;
2224 phy->interfmode = B43_INTERFMODE_NONE;
2225 b43_radio_set_interference_mitigation(dev, tmp);
2226
2227 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2228 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2229
2230 if (phy->type == B43_PHYTYPE_B) {
2231 value16 = b43_read16(dev, 0x005E);
2232 value16 |= 0x0004;
2233 b43_write16(dev, 0x005E, value16);
2234 }
2235 b43_write32(dev, 0x0100, 0x01000000);
2236 if (dev->dev->id.revision < 5)
2237 b43_write32(dev, 0x010C, 0x01000000);
2238
2239 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2240 & ~B43_MACCTL_INFRA);
2241 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2242 | B43_MACCTL_INFRA);
e4d6b795 2243
e4d6b795
MB		 2244 /* Probe Response Timeout value */
2245 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2246 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2247
2248 /* Initially set the wireless operation mode. */
2249 b43_adjust_opmode(dev);
2250
2251 if (dev->dev->id.revision < 3) {
2252 b43_write16(dev, 0x060E, 0x0000);
2253 b43_write16(dev, 0x0610, 0x8000);
2254 b43_write16(dev, 0x0604, 0x0000);
2255 b43_write16(dev, 0x0606, 0x0200);
2256 } else {
2257 b43_write32(dev, 0x0188, 0x80000000);
2258 b43_write32(dev, 0x018C, 0x02000000);
2259 }
2260 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2261 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2262 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2263 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2264 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2265 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2266 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2267
2268 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2269 value32 |= 0x00100000;
2270 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2271
2272 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2273 dev->dev->bus->chipco.fast_pwrup_delay);
2274
2275 err = 0;
2276 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2277out:
e4d6b795
MB		 2278 return err;
2279
21954c36 2280err_radio_off:
8e9f7529 2281 b43_radio_turn_off(dev, 1);
1a8d1227 2282err_gpio_clean:
e4d6b795 2283 b43_gpio_cleanup(dev);
21954c36 2284 return err;
e4d6b795
MB		 2285}
2286
2287static void b43_periodic_every120sec(struct b43_wldev *dev)
2288{
2289 struct b43_phy *phy = &dev->phy;
2290
2291 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2292 return;
2293
2294 b43_mac_suspend(dev);
2295 b43_lo_g_measure(dev);
2296 b43_mac_enable(dev);
2297 if (b43_has_hardware_pctl(phy))
2298 b43_lo_g_ctl_mark_all_unused(dev);
2299}
2300
2301static void b43_periodic_every60sec(struct b43_wldev *dev)
2302{
2303 struct b43_phy *phy = &dev->phy;
2304
2305 if (!b43_has_hardware_pctl(phy))
2306 b43_lo_g_ctl_mark_all_unused(dev);
95de2841 2307 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
e4d6b795
MB		 2308 b43_mac_suspend(dev);
2309 b43_calc_nrssi_slope(dev);
2310 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2311 u8 old_chan = phy->channel;
2312
2313 /* VCO Calibration */
2314 if (old_chan >= 8)
2315 b43_radio_selectchannel(dev, 1, 0);
2316 else
2317 b43_radio_selectchannel(dev, 13, 0);
2318 b43_radio_selectchannel(dev, old_chan, 0);
2319 }
2320 b43_mac_enable(dev);
2321 }
2322}
2323
2324static void b43_periodic_every30sec(struct b43_wldev *dev)
2325{
2326 /* Update device statistics. */
2327 b43_calculate_link_quality(dev);
2328}
2329
2330static void b43_periodic_every15sec(struct b43_wldev *dev)
2331{
2332 struct b43_phy *phy = &dev->phy;
2333
2334 if (phy->type == B43_PHYTYPE_G) {
2335 //TODO: update_aci_moving_average
2336 if (phy->aci_enable && phy->aci_wlan_automatic) {
2337 b43_mac_suspend(dev);
2338 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2339 if (0 /*TODO: bunch of conditions */ ) {
2340 b43_radio_set_interference_mitigation
2341 (dev, B43_INTERFMODE_MANUALWLAN);
2342 }
2343 } else if (1 /*TODO*/) {
2344 /*
2345 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2346 b43_radio_set_interference_mitigation(dev,
2347 B43_INTERFMODE_NONE);
2348 }
2349 */
2350 }
2351 b43_mac_enable(dev);
2352 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2353 phy->rev == 1) {
2354 //TODO: implement rev1 workaround
2355 }
2356 }
2357 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2358 //TODO for APHY (temperature?)
00e0b8cb
SB		 2359
2360 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2361 wmb();
e4d6b795
MB		 2362}
2363
e4d6b795
MB		 2364static void do_periodic_work(struct b43_wldev *dev)
2365{
2366 unsigned int state;
2367
2368 state = dev->periodic_state;
42bb4cd5 2369 if (state % 8 == 0)
e4d6b795 2370 b43_periodic_every120sec(dev);
42bb4cd5 2371 if (state % 4 == 0)
e4d6b795 2372 b43_periodic_every60sec(dev);
42bb4cd5 2373 if (state % 2 == 0)
e4d6b795 2374 b43_periodic_every30sec(dev);
42bb4cd5 2375 b43_periodic_every15sec(dev);
e4d6b795
MB		 2376}
2377
05b64b36
MB		 2378/* Periodic work locking policy:
2379 * The whole periodic work handler is protected by
2380 * wl->mutex. If another lock is needed somewhere in the
2381 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2382 */
e4d6b795
MB		 2383static void b43_periodic_work_handler(struct work_struct *work)
2384{
05b64b36
MB		 2385 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2386 periodic_work.work);
2387 struct b43_wl *wl = dev->wl;
2388 unsigned long delay;
e4d6b795 2389
05b64b36 2390 mutex_lock(&wl->mutex);
e4d6b795
MB		 2391
2392 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2393 goto out;
2394 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2395 goto out_requeue;
2396
05b64b36 2397 do_periodic_work(dev);
e4d6b795 2398
e4d6b795 2399 dev->periodic_state++;
42bb4cd5 2400out_requeue:
e4d6b795
MB		 2401 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2402 delay = msecs_to_jiffies(50);
2403 else
82cd682d 2404 delay = round_jiffies_relative(HZ * 15);
05b64b36 2405 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2406out:
05b64b36 2407 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2408}
2409
2410static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2411{
2412 struct delayed_work *work = &dev->periodic_work;
2413
2414 dev->periodic_state = 0;
2415 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2416 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2417}
2418
f3dd3fcc 2419/* Check if communication with the device works correctly. */
e4d6b795
MB		 2420static int b43_validate_chipaccess(struct b43_wldev *dev)
2421{
f3dd3fcc 2422 u32 v, backup;
e4d6b795 2423
f3dd3fcc
MB		 2424 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2425
2426 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2427 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2428 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2429 goto error;
f3dd3fcc
MB		 2430 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2431 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2432 goto error;
2433
f3dd3fcc
MB		 2434 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2435
2436 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2437 /* The 32bit register shadows the two 16bit registers
2438 * with update sideeffects. Validate this. */
2439 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2440 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2441 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2442 goto error;
2443 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2444 goto error;
2445 }
2446 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2447
2448 v = b43_read32(dev, B43_MMIO_MACCTL);
2449 v |= B43_MACCTL_GMODE;
2450 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2451 goto error;
2452
2453 return 0;
f3dd3fcc 2454error:
e4d6b795
MB		 2455 b43err(dev->wl, "Failed to validate the chipaccess\n");
2456 return -ENODEV;
2457}
2458
2459static void b43_security_init(struct b43_wldev *dev)
2460{
2461 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2462 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2463 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2464 /* KTP is a word address, but we address SHM bytewise.
2465 * So multiply by two.
2466 */
2467 dev->ktp *= 2;
2468 if (dev->dev->id.revision >= 5) {
2469 /* Number of RCMTA address slots */
2470 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2471 }
2472 b43_clear_keys(dev);
2473}
2474
2475static int b43_rng_read(struct hwrng *rng, u32 * data)
2476{
2477 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2478 unsigned long flags;
2479
2480 /* Don't take wl->mutex here, as it could deadlock with
2481 * hwrng internal locking. It's not needed to take
2482 * wl->mutex here, anyway. */
2483
2484 spin_lock_irqsave(&wl->irq_lock, flags);
2485 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2486 spin_unlock_irqrestore(&wl->irq_lock, flags);
2487
2488 return (sizeof(u16));
2489}
2490
2491static void b43_rng_exit(struct b43_wl *wl)
2492{
2493 if (wl->rng_initialized)
2494 hwrng_unregister(&wl->rng);
2495}
2496
2497static int b43_rng_init(struct b43_wl *wl)
2498{
2499 int err;
2500
2501 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2502 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2503 wl->rng.name = wl->rng_name;
2504 wl->rng.data_read = b43_rng_read;
2505 wl->rng.priv = (unsigned long)wl;
2506 wl->rng_initialized = 1;
2507 err = hwrng_register(&wl->rng);
2508 if (err) {
2509 wl->rng_initialized = 0;
2510 b43err(wl, "Failed to register the random "
2511 "number generator (%d)\n", err);
2512 }
2513
2514 return err;
2515}
2516
40faacc4
MB		 2517static int b43_op_tx(struct ieee80211_hw *hw,
2518 struct sk_buff *skb,
2519 struct ieee80211_tx_control *ctl)
e4d6b795
MB		 2520{
2521 struct b43_wl *wl = hw_to_b43_wl(hw);
2522 struct b43_wldev *dev = wl->current_dev;
2523 int err = -ENODEV;
e4d6b795
MB		 2524
2525 if (unlikely(!dev))
2526 goto out;
2527 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2528 goto out;
2529 /* DMA-TX is done without a global lock. */
03b29773 2530 err = b43_dma_tx(dev, skb, ctl);
40faacc4 2531out:
e4d6b795
MB		 2532 if (unlikely(err))
2533 return NETDEV_TX_BUSY;
2534 return NETDEV_TX_OK;
2535}
2536
40faacc4
MB		 2537static int b43_op_conf_tx(struct ieee80211_hw *hw,
2538 int queue,
2539 const struct ieee80211_tx_queue_params *params)
e4d6b795
MB		 2540{
2541 return 0;
2542}
2543
40faacc4
MB		 2544static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2545 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 2546{
2547 struct b43_wl *wl = hw_to_b43_wl(hw);
2548 struct b43_wldev *dev = wl->current_dev;
2549 unsigned long flags;
2550 int err = -ENODEV;
2551
2552 if (!dev)
2553 goto out;
2554 spin_lock_irqsave(&wl->irq_lock, flags);
2555 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
03b29773 2556 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 2557 err = 0;
2558 }
2559 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 2560out:
e4d6b795
MB		 2561 return err;
2562}
2563
40faacc4
MB		 2564static int b43_op_get_stats(struct ieee80211_hw *hw,
2565 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 2566{
2567 struct b43_wl *wl = hw_to_b43_wl(hw);
2568 unsigned long flags;
2569
2570 spin_lock_irqsave(&wl->irq_lock, flags);
2571 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2572 spin_unlock_irqrestore(&wl->irq_lock, flags);
2573
2574 return 0;
2575}
2576
2577static const char *phymode_to_string(unsigned int phymode)
2578{
2579 switch (phymode) {
2580 case B43_PHYMODE_A:
2581 return "A";
2582 case B43_PHYMODE_B:
2583 return "B";
2584 case B43_PHYMODE_G:
2585 return "G";
2586 default:
2587 B43_WARN_ON(1);
2588 }
2589 return "";
2590}
2591
2592static int find_wldev_for_phymode(struct b43_wl *wl,
2593 unsigned int phymode,
2594 struct b43_wldev **dev, bool * gmode)
2595{
2596 struct b43_wldev *d;
2597
2598 list_for_each_entry(d, &wl->devlist, list) {
2599 if (d->phy.possible_phymodes & phymode) {
2600 /* Ok, this device supports the PHY-mode.
2601 * Now figure out how the gmode bit has to be
2602 * set to support it. */
2603 if (phymode == B43_PHYMODE_A)
2604 *gmode = 0;
2605 else
2606 *gmode = 1;
2607 *dev = d;
2608
2609 return 0;
2610 }
2611 }
2612
2613 return -ESRCH;
2614}
2615
2616static void b43_put_phy_into_reset(struct b43_wldev *dev)
2617{
2618 struct ssb_device *sdev = dev->dev;
2619 u32 tmslow;
2620
2621 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2622 tmslow &= ~B43_TMSLOW_GMODE;
2623 tmslow |= B43_TMSLOW_PHYRESET;
2624 tmslow |= SSB_TMSLOW_FGC;
2625 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2626 msleep(1);
2627
2628 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2629 tmslow &= ~SSB_TMSLOW_FGC;
2630 tmslow |= B43_TMSLOW_PHYRESET;
2631 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2632 msleep(1);
2633}
2634
2635/* Expects wl->mutex locked */
2636static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2637{
2638 struct b43_wldev *up_dev;
2639 struct b43_wldev *down_dev;
2640 int err;
2641 bool gmode = 0;
2642 int prev_status;
2643
2644 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2645 if (err) {
2646 b43err(wl, "Could not find a device for %s-PHY mode\n",
2647 phymode_to_string(new_mode));
2648 return err;
2649 }
2650 if ((up_dev == wl->current_dev) &&
2651 (!!wl->current_dev->phy.gmode == !!gmode)) {
2652 /* This device is already running. */
2653 return 0;
2654 }
2655 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2656 phymode_to_string(new_mode));
2657 down_dev = wl->current_dev;
2658
2659 prev_status = b43_status(down_dev);
2660 /* Shutdown the currently running core. */
2661 if (prev_status >= B43_STAT_STARTED)
2662 b43_wireless_core_stop(down_dev);
2663 if (prev_status >= B43_STAT_INITIALIZED)
2664 b43_wireless_core_exit(down_dev);
2665
2666 if (down_dev != up_dev) {
2667 /* We switch to a different core, so we put PHY into
2668 * RESET on the old core. */
2669 b43_put_phy_into_reset(down_dev);
2670 }
2671
2672 /* Now start the new core. */
2673 up_dev->phy.gmode = gmode;
2674 if (prev_status >= B43_STAT_INITIALIZED) {
2675 err = b43_wireless_core_init(up_dev);
2676 if (err) {
2677 b43err(wl, "Fatal: Could not initialize device for "
2678 "newly selected %s-PHY mode\n",
2679 phymode_to_string(new_mode));
2680 goto init_failure;
2681 }
2682 }
2683 if (prev_status >= B43_STAT_STARTED) {
2684 err = b43_wireless_core_start(up_dev);
2685 if (err) {
2686 b43err(wl, "Fatal: Coult not start device for "
2687 "newly selected %s-PHY mode\n",
2688 phymode_to_string(new_mode));
2689 b43_wireless_core_exit(up_dev);
2690 goto init_failure;
2691 }
2692 }
2693 B43_WARN_ON(b43_status(up_dev) != prev_status);
2694
2695 wl->current_dev = up_dev;
2696
2697 return 0;
2698 init_failure:
2699 /* Whoops, failed to init the new core. No core is operating now. */
2700 wl->current_dev = NULL;
2701 return err;
2702}
2703
9db1f6d7
MB		 2704/* Check if the use of the antenna that ieee80211 told us to
2705 * use is possible. This will fall back to DEFAULT.
2706 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2707u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2708 u8 antenna_nr)
e4d6b795 2709{
9db1f6d7
MB		 2710 u8 antenna_mask;
2711
2712 if (antenna_nr == 0) {
2713 /* Zero means "use default antenna". That's always OK. */
2714 return 0;
2715 }
2716
2717 /* Get the mask of available antennas. */
2718 if (dev->phy.gmode)
2719 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2720 else
2721 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2722
2723 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2724 /* This antenna is not available. Fall back to default. */
2725 return 0;
2726 }
2727
2728 return antenna_nr;
2729}
2730
2731static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2732{
2733 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
e4d6b795
MB		 2734 switch (antenna) {
2735 case 0: /* default/diversity */
2736 return B43_ANTENNA_DEFAULT;
2737 case 1: /* Antenna 0 */
2738 return B43_ANTENNA0;
2739 case 2: /* Antenna 1 */
2740 return B43_ANTENNA1;
2741 default:
2742 return B43_ANTENNA_DEFAULT;
2743 }
2744}
2745
40faacc4 2746static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
e4d6b795
MB		 2747{
2748 struct b43_wl *wl = hw_to_b43_wl(hw);
2749 struct b43_wldev *dev;
2750 struct b43_phy *phy;
2751 unsigned long flags;
2752 unsigned int new_phymode = 0xFFFF;
9db1f6d7 2753 int antenna;
e4d6b795
MB		 2754 int err = 0;
2755 u32 savedirqs;
2756
e4d6b795
MB		 2757 mutex_lock(&wl->mutex);
2758
2759 /* Switch the PHY mode (if necessary). */
2760 switch (conf->phymode) {
2761 case MODE_IEEE80211A:
2762 new_phymode = B43_PHYMODE_A;
2763 break;
2764 case MODE_IEEE80211B:
2765 new_phymode = B43_PHYMODE_B;
2766 break;
2767 case MODE_IEEE80211G:
2768 new_phymode = B43_PHYMODE_G;
2769 break;
2770 default:
2771 B43_WARN_ON(1);
2772 }
2773 err = b43_switch_phymode(wl, new_phymode);
2774 if (err)
2775 goto out_unlock_mutex;
2776 dev = wl->current_dev;
2777 phy = &dev->phy;
2778
2779 /* Disable IRQs while reconfiguring the device.
2780 * This makes it possible to drop the spinlock throughout
2781 * the reconfiguration process. */
2782 spin_lock_irqsave(&wl->irq_lock, flags);
2783 if (b43_status(dev) < B43_STAT_STARTED) {
2784 spin_unlock_irqrestore(&wl->irq_lock, flags);
2785 goto out_unlock_mutex;
2786 }
2787 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2788 spin_unlock_irqrestore(&wl->irq_lock, flags);
2789 b43_synchronize_irq(dev);
2790
2791 /* Switch to the requested channel.
2792 * The firmware takes care of races with the TX handler. */
2793 if (conf->channel_val != phy->channel)
2794 b43_radio_selectchannel(dev, conf->channel_val, 0);
2795
2796 /* Enable/Disable ShortSlot timing. */
2797 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2798 dev->short_slot) {
2799 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2800 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2801 b43_short_slot_timing_enable(dev);
2802 else
2803 b43_short_slot_timing_disable(dev);
2804 }
2805
d42ce84a
JB		 2806 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2807
e4d6b795
MB		 2808 /* Adjust the desired TX power level. */
2809 if (conf->power_level != 0) {
2810 if (conf->power_level != phy->power_level) {
2811 phy->power_level = conf->power_level;
2812 b43_phy_xmitpower(dev);
2813 }
2814 }
2815
2816 /* Antennas for RX and management frame TX. */
9db1f6d7
MB		 2817 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2818 b43_mgmtframe_txantenna(dev, antenna);
2819 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2820 b43_set_rx_antenna(dev, antenna);
e4d6b795
MB		 2821
2822 /* Update templates for AP mode. */
2823 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2824 b43_set_beacon_int(dev, conf->beacon_int);
2825
fda9abcf
MB		 2826 if (!!conf->radio_enabled != phy->radio_on) {
2827 if (conf->radio_enabled) {
2828 b43_radio_turn_on(dev);
2829 b43info(dev->wl, "Radio turned on by software\n");
2830 if (!dev->radio_hw_enable) {
2831 b43info(dev->wl, "The hardware RF-kill button "
2832 "still turns the radio physically off. "
2833 "Press the button to turn it on.\n");
2834 }
2835 } else {
8e9f7529 2836 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 2837 b43info(dev->wl, "Radio turned off by software\n");
2838 }
2839 }
2840
e4d6b795
MB		 2841 spin_lock_irqsave(&wl->irq_lock, flags);
2842 b43_interrupt_enable(dev, savedirqs);
2843 mmiowb();
2844 spin_unlock_irqrestore(&wl->irq_lock, flags);
2845 out_unlock_mutex:
2846 mutex_unlock(&wl->mutex);
2847
2848 return err;
2849}
2850
40faacc4 2851static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 2852 const u8 *local_addr, const u8 *addr,
2853 struct ieee80211_key_conf *key)
e4d6b795
MB		 2854{
2855 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 2856 struct b43_wldev *dev;
e4d6b795
MB		 2857 unsigned long flags;
2858 u8 algorithm;
2859 u8 index;
c6dfc9a8 2860 int err;
0795af57 2861 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 2862
2863 if (modparam_nohwcrypt)
2864 return -ENOSPC; /* User disabled HW-crypto */
2865
c6dfc9a8
MB		 2866 mutex_lock(&wl->mutex);
2867 spin_lock_irqsave(&wl->irq_lock, flags);
2868
2869 dev = wl->current_dev;
2870 err = -ENODEV;
2871 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2872 goto out_unlock;
2873
2874 err = -EINVAL;
e4d6b795 2875 switch (key->alg) {
e4d6b795
MB		 2876 case ALG_WEP:
2877 if (key->keylen == 5)
2878 algorithm = B43_SEC_ALGO_WEP40;
2879 else
2880 algorithm = B43_SEC_ALGO_WEP104;
2881 break;
2882 case ALG_TKIP:
2883 algorithm = B43_SEC_ALGO_TKIP;
2884 break;
2885 case ALG_CCMP:
2886 algorithm = B43_SEC_ALGO_AES;
2887 break;
2888 default:
2889 B43_WARN_ON(1);
c6dfc9a8 2890 goto out_unlock;
e4d6b795 2891 }
e4d6b795
MB		 2892 index = (u8) (key->keyidx);
2893 if (index > 3)
e4d6b795 2894 goto out_unlock;
e4d6b795
MB		 2895
2896 switch (cmd) {
2897 case SET_KEY:
2898 if (algorithm == B43_SEC_ALGO_TKIP) {
2899 /* FIXME: No TKIP hardware encryption for now. */
2900 err = -EOPNOTSUPP;
2901 goto out_unlock;
2902 }
2903
2904 if (is_broadcast_ether_addr(addr)) {
2905 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2906 err = b43_key_write(dev, index, algorithm,
2907 key->key, key->keylen, NULL, key);
2908 } else {
2909 /*
2910 * either pairwise key or address is 00:00:00:00:00:00
2911 * for transmit-only keys
2912 */
2913 err = b43_key_write(dev, -1, algorithm,
2914 key->key, key->keylen, addr, key);
2915 }
2916 if (err)
2917 goto out_unlock;
2918
2919 if (algorithm == B43_SEC_ALGO_WEP40 ||
2920 algorithm == B43_SEC_ALGO_WEP104) {
2921 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2922 } else {
2923 b43_hf_write(dev,
2924 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2925 }
2926 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2927 break;
2928 case DISABLE_KEY: {
2929 err = b43_key_clear(dev, key->hw_key_idx);
2930 if (err)
2931 goto out_unlock;
2932 break;
2933 }
2934 default:
2935 B43_WARN_ON(1);
2936 }
2937out_unlock:
2938 spin_unlock_irqrestore(&wl->irq_lock, flags);
2939 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2940 if (!err) {
2941 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 2942 "mac: %s\n",
e4d6b795 2943 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 2944 print_mac(mac, addr));
e4d6b795
MB		 2945 }
2946 return err;
2947}
2948
40faacc4
MB		 2949static void b43_op_configure_filter(struct ieee80211_hw *hw,
2950 unsigned int changed, unsigned int *fflags,
2951 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 2952{
2953 struct b43_wl *wl = hw_to_b43_wl(hw);
2954 struct b43_wldev *dev = wl->current_dev;
2955 unsigned long flags;
2956
4150c572
JB		 2957 if (!dev) {
2958 *fflags = 0;
e4d6b795 2959 return;
e4d6b795 2960 }
4150c572
JB		 2961
2962 spin_lock_irqsave(&wl->irq_lock, flags);
2963 *fflags &= FIF_PROMISC_IN_BSS |
2964 FIF_ALLMULTI |
2965 FIF_FCSFAIL |
2966 FIF_PLCPFAIL |
2967 FIF_CONTROL |
2968 FIF_OTHER_BSS |
2969 FIF_BCN_PRBRESP_PROMISC;
2970
2971 changed &= FIF_PROMISC_IN_BSS |
2972 FIF_ALLMULTI |
2973 FIF_FCSFAIL |
2974 FIF_PLCPFAIL |
2975 FIF_CONTROL |
2976 FIF_OTHER_BSS |
2977 FIF_BCN_PRBRESP_PROMISC;
2978
2979 wl->filter_flags = *fflags;
2980
2981 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2982 b43_adjust_opmode(dev);
e4d6b795
MB		 2983 spin_unlock_irqrestore(&wl->irq_lock, flags);
2984}
2985
40faacc4 2986static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 2987 struct ieee80211_vif *vif,
40faacc4 2988 struct ieee80211_if_conf *conf)
e4d6b795
MB		 2989{
2990 struct b43_wl *wl = hw_to_b43_wl(hw);
2991 struct b43_wldev *dev = wl->current_dev;
2992 unsigned long flags;
2993
2994 if (!dev)
2995 return -ENODEV;
2996 mutex_lock(&wl->mutex);
2997 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 2998 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 2999 if (conf->bssid)
3000 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3001 else
3002 memset(wl->bssid, 0, ETH_ALEN);
3003 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3004 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3005 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3006 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3007 if (conf->beacon)
e66fee6a 3008 b43_update_templates(wl, conf->beacon);
e4d6b795 3009 }
4150c572 3010 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3011 }
3012 spin_unlock_irqrestore(&wl->irq_lock, flags);
3013 mutex_unlock(&wl->mutex);
3014
3015 return 0;
3016}
3017
3018/* Locking: wl->mutex */
3019static void b43_wireless_core_stop(struct b43_wldev *dev)
3020{
3021 struct b43_wl *wl = dev->wl;
3022 unsigned long flags;
3023
3024 if (b43_status(dev) < B43_STAT_STARTED)
3025 return;
a19d12d7
SB		 3026
3027 /* Disable and sync interrupts. We must do this before than
3028 * setting the status to INITIALIZED, as the interrupt handler
3029 * won't care about IRQs then. */
3030 spin_lock_irqsave(&wl->irq_lock, flags);
3031 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3032 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3033 spin_unlock_irqrestore(&wl->irq_lock, flags);
3034 b43_synchronize_irq(dev);
3035
e4d6b795
MB		 3036 b43_set_status(dev, B43_STAT_INITIALIZED);
3037
3038 mutex_unlock(&wl->mutex);
3039 /* Must unlock as it would otherwise deadlock. No races here.
3040 * Cancel the possibly running self-rearming periodic work. */
3041 cancel_delayed_work_sync(&dev->periodic_work);
3042 mutex_lock(&wl->mutex);
3043
3044 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3045
e4d6b795
MB		 3046 b43_mac_suspend(dev);
3047 free_irq(dev->dev->irq, dev);
3048 b43dbg(wl, "Wireless interface stopped\n");
3049}
3050
3051/* Locking: wl->mutex */
3052static int b43_wireless_core_start(struct b43_wldev *dev)
3053{
3054 int err;
3055
3056 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3057
3058 drain_txstatus_queue(dev);
3059 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3060 IRQF_SHARED, KBUILD_MODNAME, dev);
3061 if (err) {
3062 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3063 goto out;
3064 }
3065
3066 /* We are ready to run. */
3067 b43_set_status(dev, B43_STAT_STARTED);
3068
3069 /* Start data flow (TX/RX). */
3070 b43_mac_enable(dev);
3071 b43_interrupt_enable(dev, dev->irq_savedstate);
3072 ieee80211_start_queues(dev->wl->hw);
3073
3074 /* Start maintainance work */
3075 b43_periodic_tasks_setup(dev);
3076
3077 b43dbg(dev->wl, "Wireless interface started\n");
3078 out:
3079 return err;
3080}
3081
3082/* Get PHY and RADIO versioning numbers */
3083static int b43_phy_versioning(struct b43_wldev *dev)
3084{
3085 struct b43_phy *phy = &dev->phy;
3086 u32 tmp;
3087 u8 analog_type;
3088 u8 phy_type;
3089 u8 phy_rev;
3090 u16 radio_manuf;
3091 u16 radio_ver;
3092 u16 radio_rev;
3093 int unsupported = 0;
3094
3095 /* Get PHY versioning */
3096 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3097 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3098 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3099 phy_rev = (tmp & B43_PHYVER_VERSION);
3100 switch (phy_type) {
3101 case B43_PHYTYPE_A:
3102 if (phy_rev >= 4)
3103 unsupported = 1;
3104 break;
3105 case B43_PHYTYPE_B:
3106 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3107 && phy_rev != 7)
3108 unsupported = 1;
3109 break;
3110 case B43_PHYTYPE_G:
013978b6 3111 if (phy_rev > 9)
e4d6b795
MB		 3112 unsupported = 1;
3113 break;
d5c71e46
MB		 3114#ifdef CONFIG_B43_NPHY
3115 case B43_PHYTYPE_N:
3116 if (phy_rev > 1)
3117 unsupported = 1;
3118 break;
3119#endif
e4d6b795
MB		 3120 default:
3121 unsupported = 1;
3122 };
3123 if (unsupported) {
3124 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3125 "(Analog %u, Type %u, Revision %u)\n",
3126 analog_type, phy_type, phy_rev);
3127 return -EOPNOTSUPP;
3128 }
3129 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3130 analog_type, phy_type, phy_rev);
3131
3132 /* Get RADIO versioning */
3133 if (dev->dev->bus->chip_id == 0x4317) {
3134 if (dev->dev->bus->chip_rev == 0)
3135 tmp = 0x3205017F;
3136 else if (dev->dev->bus->chip_rev == 1)
3137 tmp = 0x4205017F;
3138 else
3139 tmp = 0x5205017F;
3140 } else {
3141 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3142 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3143 tmp <<= 16;
3144 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3145 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3146 }
3147 radio_manuf = (tmp & 0x00000FFF);
3148 radio_ver = (tmp & 0x0FFFF000) >> 12;
3149 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3150 if (radio_manuf != 0x17F /* Broadcom */)
3151 unsupported = 1;
e4d6b795
MB		 3152 switch (phy_type) {
3153 case B43_PHYTYPE_A:
3154 if (radio_ver != 0x2060)
3155 unsupported = 1;
3156 if (radio_rev != 1)
3157 unsupported = 1;
3158 if (radio_manuf != 0x17F)
3159 unsupported = 1;
3160 break;
3161 case B43_PHYTYPE_B:
3162 if ((radio_ver & 0xFFF0) != 0x2050)
3163 unsupported = 1;
3164 break;
3165 case B43_PHYTYPE_G:
3166 if (radio_ver != 0x2050)
3167 unsupported = 1;
3168 break;
96c755a3
MB		 3169 case B43_PHYTYPE_N:
3170 if (radio_ver != 5)
3171 unsupported = 1;
3172 break;
e4d6b795
MB		 3173 default:
3174 B43_WARN_ON(1);
3175 }
3176 if (unsupported) {
3177 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3178 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3179 radio_manuf, radio_ver, radio_rev);
3180 return -EOPNOTSUPP;
3181 }
3182 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3183 radio_manuf, radio_ver, radio_rev);
3184
3185 phy->radio_manuf = radio_manuf;
3186 phy->radio_ver = radio_ver;
3187 phy->radio_rev = radio_rev;
3188
3189 phy->analog = analog_type;
3190 phy->type = phy_type;
3191 phy->rev = phy_rev;
3192
3193 return 0;
3194}
3195
3196static void setup_struct_phy_for_init(struct b43_wldev *dev,
3197 struct b43_phy *phy)
3198{
3199 struct b43_txpower_lo_control *lo;
3200 int i;
3201
3202 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3203 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3204
e4d6b795
MB		 3205 phy->aci_enable = 0;
3206 phy->aci_wlan_automatic = 0;
3207 phy->aci_hw_rssi = 0;
3208
fda9abcf
MB		 3209 phy->radio_off_context.valid = 0;
3210
e4d6b795
MB		 3211 lo = phy->lo_control;
3212 if (lo) {
3213 memset(lo, 0, sizeof(*(phy->lo_control)));
3214 lo->rebuild = 1;
3215 lo->tx_bias = 0xFF;
3216 }
3217 phy->max_lb_gain = 0;
3218 phy->trsw_rx_gain = 0;
3219 phy->txpwr_offset = 0;
3220
3221 /* NRSSI */
3222 phy->nrssislope = 0;
3223 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3224 phy->nrssi[i] = -1000;
3225 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3226 phy->nrssi_lt[i] = i;
3227
3228 phy->lofcal = 0xFFFF;
3229 phy->initval = 0xFFFF;
3230
e4d6b795
MB		 3231 phy->interfmode = B43_INTERFMODE_NONE;
3232 phy->channel = 0xFF;
3233
3234 phy->hardware_power_control = !!modparam_hwpctl;
8ed7fc48
MB		 3235
3236 /* PHY TX errors counter. */
3237 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3238
3239 /* OFDM-table address caching. */
3240 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
e4d6b795
MB		 3241}
3242
3243static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3244{
aa6c7ae2
MB		 3245 dev->dfq_valid = 0;
3246
6a724d68
MB		 3247 /* Assume the radio is enabled. If it's not enabled, the state will
3248 * immediately get fixed on the first periodic work run. */
3249 dev->radio_hw_enable = 1;
e4d6b795
MB		 3250
3251 /* Stats */
3252 memset(&dev->stats, 0, sizeof(dev->stats));
3253
3254 setup_struct_phy_for_init(dev, &dev->phy);
3255
3256 /* IRQ related flags */
3257 dev->irq_reason = 0;
3258 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3259 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3260
3261 dev->mac_suspended = 1;
3262
3263 /* Noise calculation context */
3264 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3265}
3266
3267static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3268{
3269 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3270 u32 hf;
3271
95de2841 3272 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3273 return;
3274 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3275 return;
3276
3277 hf = b43_hf_read(dev);
95de2841 3278 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3279 hf |= B43_HF_BTCOEXALT;
3280 else
3281 hf |= B43_HF_BTCOEX;
3282 b43_hf_write(dev, hf);
3283 //TODO
3284}
3285
3286static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3287{ //TODO
3288}
3289
3290static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3291{
3292#ifdef CONFIG_SSB_DRIVER_PCICORE
3293 struct ssb_bus *bus = dev->dev->bus;
3294 u32 tmp;
3295
3296 if (bus->pcicore.dev &&
3297 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3298 bus->pcicore.dev->id.revision <= 5) {
3299 /* IMCFGLO timeouts workaround. */
3300 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3301 tmp &= ~SSB_IMCFGLO_REQTO;
3302 tmp &= ~SSB_IMCFGLO_SERTO;
3303 switch (bus->bustype) {
3304 case SSB_BUSTYPE_PCI:
3305 case SSB_BUSTYPE_PCMCIA:
3306 tmp |= 0x32;
3307 break;
3308 case SSB_BUSTYPE_SSB:
3309 tmp |= 0x53;
3310 break;
3311 }
3312 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3313 }
3314#endif /* CONFIG_SSB_DRIVER_PCICORE */
3315}
3316
74cfdba7
MB		 3317/* Write the short and long frame retry limit values. */
3318static void b43_set_retry_limits(struct b43_wldev *dev,
3319 unsigned int short_retry,
3320 unsigned int long_retry)
3321{
3322 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3323 * the chip-internal counter. */
3324 short_retry = min(short_retry, (unsigned int)0xF);
3325 long_retry = min(long_retry, (unsigned int)0xF);
3326
3327 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3328 short_retry);
3329 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3330 long_retry);
3331}
3332
e4d6b795
MB		 3333/* Shutdown a wireless core */
3334/* Locking: wl->mutex */
3335static void b43_wireless_core_exit(struct b43_wldev *dev)
3336{
3337 struct b43_phy *phy = &dev->phy;
3338
3339 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3340 if (b43_status(dev) != B43_STAT_INITIALIZED)
3341 return;
3342 b43_set_status(dev, B43_STAT_UNINIT);
3343
1a8d1227 3344 b43_leds_exit(dev);
e4d6b795 3345 b43_rng_exit(dev->wl);
e4d6b795
MB		 3346 b43_dma_free(dev);
3347 b43_chip_exit(dev);
8e9f7529 3348 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3349 b43_switch_analog(dev, 0);
3350 if (phy->dyn_tssi_tbl)
3351 kfree(phy->tssi2dbm);
3352 kfree(phy->lo_control);
3353 phy->lo_control = NULL;
e66fee6a
MB		 3354 if (dev->wl->current_beacon) {
3355 dev_kfree_skb_any(dev->wl->current_beacon);
3356 dev->wl->current_beacon = NULL;
3357 }
3358
e4d6b795
MB		 3359 ssb_device_disable(dev->dev, 0);
3360 ssb_bus_may_powerdown(dev->dev->bus);
3361}
3362
3363/* Initialize a wireless core */
3364static int b43_wireless_core_init(struct b43_wldev *dev)
3365{
3366 struct b43_wl *wl = dev->wl;
3367 struct ssb_bus *bus = dev->dev->bus;
3368 struct ssb_sprom *sprom = &bus->sprom;
3369 struct b43_phy *phy = &dev->phy;
3370 int err;
3371 u32 hf, tmp;
3372
3373 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3374
3375 err = ssb_bus_powerup(bus, 0);
3376 if (err)
3377 goto out;
3378 if (!ssb_device_is_enabled(dev->dev)) {
3379 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3380 b43_wireless_core_reset(dev, tmp);
3381 }
3382
3383 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3384 phy->lo_control =
3385 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3386 if (!phy->lo_control) {
3387 err = -ENOMEM;
3388 goto err_busdown;
3389 }
3390 }
3391 setup_struct_wldev_for_init(dev);
3392
3393 err = b43_phy_init_tssi2dbm_table(dev);
3394 if (err)
3395 goto err_kfree_lo_control;
3396
3397 /* Enable IRQ routing to this device. */
3398 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3399
3400 b43_imcfglo_timeouts_workaround(dev);
3401 b43_bluetooth_coext_disable(dev);
3402 b43_phy_early_init(dev);
3403 err = b43_chip_init(dev);
3404 if (err)
3405 goto err_kfree_tssitbl;
3406 b43_shm_write16(dev, B43_SHM_SHARED,
3407 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3408 hf = b43_hf_read(dev);
3409 if (phy->type == B43_PHYTYPE_G) {
3410 hf |= B43_HF_SYMW;
3411 if (phy->rev == 1)
3412 hf |= B43_HF_GDCW;
95de2841 3413 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3414 hf |= B43_HF_OFDMPABOOST;
3415 } else if (phy->type == B43_PHYTYPE_B) {
3416 hf |= B43_HF_SYMW;
3417 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3418 hf &= ~B43_HF_GDCW;
3419 }
3420 b43_hf_write(dev, hf);
3421
74cfdba7
MB		 3422 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3423 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 3424 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3425 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3426
3427 /* Disable sending probe responses from firmware.
3428 * Setting the MaxTime to one usec will always trigger
3429 * a timeout, so we never send any probe resp.
3430 * A timeout of zero is infinite. */
3431 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3432
3433 b43_rate_memory_init(dev);
3434
3435 /* Minimum Contention Window */
3436 if (phy->type == B43_PHYTYPE_B) {
3437 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3438 } else {
3439 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3440 }
3441 /* Maximum Contention Window */
3442 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3443
03b29773 3444 err = b43_dma_init(dev);
e4d6b795
MB		 3445 if (err)
3446 goto err_chip_exit;
03b29773 3447 b43_qos_init(dev);
e4d6b795
MB		 3448
3449//FIXME
3450#if 1
3451 b43_write16(dev, 0x0612, 0x0050);
3452 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3453 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3454#endif
3455
3456 b43_bluetooth_coext_enable(dev);
3457
3458 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3459 memset(wl->bssid, 0, ETH_ALEN);
4150c572
JB		 3460 memset(wl->mac_addr, 0, ETH_ALEN);
3461 b43_upload_card_macaddress(dev);
e4d6b795
MB		 3462 b43_security_init(dev);
3463 b43_rng_init(wl);
3464
3465 b43_set_status(dev, B43_STAT_INITIALIZED);
3466
1a8d1227
LF		 3467 b43_leds_init(dev);
3468out:
e4d6b795
MB		 3469 return err;
3470
3471 err_chip_exit:
3472 b43_chip_exit(dev);
3473 err_kfree_tssitbl:
3474 if (phy->dyn_tssi_tbl)
3475 kfree(phy->tssi2dbm);
3476 err_kfree_lo_control:
3477 kfree(phy->lo_control);
3478 phy->lo_control = NULL;
3479 err_busdown:
3480 ssb_bus_may_powerdown(bus);
3481 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3482 return err;
3483}
3484
40faacc4
MB		 3485static int b43_op_add_interface(struct ieee80211_hw *hw,
3486 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 3487{
3488 struct b43_wl *wl = hw_to_b43_wl(hw);
3489 struct b43_wldev *dev;
3490 unsigned long flags;
3491 int err = -EOPNOTSUPP;
4150c572
JB		 3492
3493 /* TODO: allow WDS/AP devices to coexist */
3494
3495 if (conf->type != IEEE80211_IF_TYPE_AP &&
3496 conf->type != IEEE80211_IF_TYPE_STA &&
3497 conf->type != IEEE80211_IF_TYPE_WDS &&
3498 conf->type != IEEE80211_IF_TYPE_IBSS)
3499 return -EOPNOTSUPP;
e4d6b795
MB		 3500
3501 mutex_lock(&wl->mutex);
4150c572 3502 if (wl->operating)
e4d6b795
MB		 3503 goto out_mutex_unlock;
3504
3505 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3506
3507 dev = wl->current_dev;
4150c572 3508 wl->operating = 1;
32bfd35d 3509 wl->vif = conf->vif;
4150c572
JB		 3510 wl->if_type = conf->type;
3511 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3512
3513 spin_lock_irqsave(&wl->irq_lock, flags);
3514 b43_adjust_opmode(dev);
3515 b43_upload_card_macaddress(dev);
3516 spin_unlock_irqrestore(&wl->irq_lock, flags);
3517
3518 err = 0;
3519 out_mutex_unlock:
3520 mutex_unlock(&wl->mutex);
3521
3522 return err;
3523}
3524
40faacc4
MB		 3525static void b43_op_remove_interface(struct ieee80211_hw *hw,
3526 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3527{
3528 struct b43_wl *wl = hw_to_b43_wl(hw);
3529 struct b43_wldev *dev = wl->current_dev;
3530 unsigned long flags;
3531
3532 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3533
3534 mutex_lock(&wl->mutex);
3535
3536 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 3537 B43_WARN_ON(wl->vif != conf->vif);
3538 wl->vif = NULL;
4150c572
JB		 3539
3540 wl->operating = 0;
3541
3542 spin_lock_irqsave(&wl->irq_lock, flags);
3543 b43_adjust_opmode(dev);
3544 memset(wl->mac_addr, 0, ETH_ALEN);
3545 b43_upload_card_macaddress(dev);
3546 spin_unlock_irqrestore(&wl->irq_lock, flags);
3547
3548 mutex_unlock(&wl->mutex);
3549}
3550
40faacc4 3551static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3552{
3553 struct b43_wl *wl = hw_to_b43_wl(hw);
3554 struct b43_wldev *dev = wl->current_dev;
3555 int did_init = 0;
923403b8 3556 int err = 0;
4150c572 3557
1a8d1227
LF		 3558 /* First register RFkill.
3559 * LEDs that are registered later depend on it. */
3560 b43_rfkill_init(dev);
3561
4150c572
JB		 3562 mutex_lock(&wl->mutex);
3563
e4d6b795
MB		 3564 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3565 err = b43_wireless_core_init(dev);
3566 if (err)
3567 goto out_mutex_unlock;
3568 did_init = 1;
3569 }
4150c572 3570
e4d6b795
MB		 3571 if (b43_status(dev) < B43_STAT_STARTED) {
3572 err = b43_wireless_core_start(dev);
3573 if (err) {
3574 if (did_init)
3575 b43_wireless_core_exit(dev);
3576 goto out_mutex_unlock;
3577 }
3578 }
3579
4150c572 3580 out_mutex_unlock:
e4d6b795
MB		 3581 mutex_unlock(&wl->mutex);
3582
3583 return err;
3584}
3585
40faacc4 3586static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 3587{
3588 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 3589 struct b43_wldev *dev = wl->current_dev;
e4d6b795 3590
1a8d1227
LF		 3591 b43_rfkill_exit(dev);
3592
e4d6b795 3593 mutex_lock(&wl->mutex);
4150c572
JB		 3594 if (b43_status(dev) >= B43_STAT_STARTED)
3595 b43_wireless_core_stop(dev);
3596 b43_wireless_core_exit(dev);
e4d6b795
MB		 3597 mutex_unlock(&wl->mutex);
3598}
3599
74cfdba7
MB		 3600static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3601 u32 short_retry_limit, u32 long_retry_limit)
3602{
3603 struct b43_wl *wl = hw_to_b43_wl(hw);
3604 struct b43_wldev *dev;
3605 int err = 0;
3606
3607 mutex_lock(&wl->mutex);
3608 dev = wl->current_dev;
3609 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3610 err = -ENODEV;
3611 goto out_unlock;
3612 }
3613 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3614out_unlock:
3615 mutex_unlock(&wl->mutex);
3616
3617 return err;
3618}
3619
e66fee6a
MB		 3620static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3621{
3622 struct b43_wl *wl = hw_to_b43_wl(hw);
3623 struct sk_buff *beacon;
d4df6f1a 3624 unsigned long flags;
e66fee6a
MB		 3625
3626 /* We could modify the existing beacon and set the aid bit in
3627 * the TIM field, but that would probably require resizing and
3628 * moving of data within the beacon template.
3629 * Simply request a new beacon and let mac80211 do the hard work. */
3630 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3631 if (unlikely(!beacon))
3632 return -ENOMEM;
d4df6f1a 3633 spin_lock_irqsave(&wl->irq_lock, flags);
e66fee6a 3634 b43_update_templates(wl, beacon);
d4df6f1a 3635 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 3636
3637 return 0;
3638}
3639
3640static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3641 struct sk_buff *beacon,
3642 struct ieee80211_tx_control *ctl)
3643{
3644 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 3645 unsigned long flags;
e66fee6a 3646
d4df6f1a 3647 spin_lock_irqsave(&wl->irq_lock, flags);
e66fee6a 3648 b43_update_templates(wl, beacon);
d4df6f1a 3649 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 3650
3651 return 0;
3652}
3653
e4d6b795 3654static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 3655 .tx = b43_op_tx,
3656 .conf_tx = b43_op_conf_tx,
3657 .add_interface = b43_op_add_interface,
3658 .remove_interface = b43_op_remove_interface,
3659 .config = b43_op_config,
3660 .config_interface = b43_op_config_interface,
3661 .configure_filter = b43_op_configure_filter,
3662 .set_key = b43_op_set_key,
3663 .get_stats = b43_op_get_stats,
3664 .get_tx_stats = b43_op_get_tx_stats,
3665 .start = b43_op_start,
3666 .stop = b43_op_stop,
74cfdba7 3667 .set_retry_limit = b43_op_set_retry_limit,
e66fee6a
MB		 3668 .set_tim = b43_op_beacon_set_tim,
3669 .beacon_update = b43_op_ibss_beacon_update,
e4d6b795
MB		 3670};
3671
3672/* Hard-reset the chip. Do not call this directly.
3673 * Use b43_controller_restart()
3674 */
3675static void b43_chip_reset(struct work_struct *work)
3676{
3677 struct b43_wldev *dev =
3678 container_of(work, struct b43_wldev, restart_work);
3679 struct b43_wl *wl = dev->wl;
3680 int err = 0;
3681 int prev_status;
3682
3683 mutex_lock(&wl->mutex);
3684
3685 prev_status = b43_status(dev);
3686 /* Bring the device down... */
3687 if (prev_status >= B43_STAT_STARTED)
3688 b43_wireless_core_stop(dev);
3689 if (prev_status >= B43_STAT_INITIALIZED)
3690 b43_wireless_core_exit(dev);
3691
3692 /* ...and up again. */
3693 if (prev_status >= B43_STAT_INITIALIZED) {
3694 err = b43_wireless_core_init(dev);
3695 if (err)
3696 goto out;
3697 }
3698 if (prev_status >= B43_STAT_STARTED) {
3699 err = b43_wireless_core_start(dev);
3700 if (err) {
3701 b43_wireless_core_exit(dev);
3702 goto out;
3703 }
3704 }
3705 out:
3706 mutex_unlock(&wl->mutex);
3707 if (err)
3708 b43err(wl, "Controller restart FAILED\n");
3709 else
3710 b43info(wl, "Controller restarted\n");
3711}
3712
3713static int b43_setup_modes(struct b43_wldev *dev,
96c755a3 3714 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 3715{
3716 struct ieee80211_hw *hw = dev->wl->hw;
3717 struct ieee80211_hw_mode *mode;
3718 struct b43_phy *phy = &dev->phy;
e4d6b795
MB		 3719 int err;
3720
96c755a3
MB		 3721 /* XXX: This function will go away soon, when mac80211
3722 * band stuff is rewritten. So this is just a hack.
3723 * For now we always claim GPHY mode, as there is no
3724 * support for NPHY and APHY in the device, yet.
3725 * This assumption is OK, as any B, N or A PHY will already
3726 * have died a horrible sanity check death earlier. */
3727
3728 mode = &phy->hwmodes[0];
3729 mode->mode = MODE_IEEE80211G;
3730 mode->num_channels = b43_2ghz_chantable_size;
3731 mode->channels = b43_2ghz_chantable;
3732 mode->num_rates = b43_g_ratetable_size;
3733 mode->rates = b43_g_ratetable;
3734 err = ieee80211_register_hwmode(hw, mode);
3735 if (err)
3736 return err;
3737 phy->possible_phymodes |= B43_PHYMODE_G;
e4d6b795
MB		 3738
3739 return 0;
3740}
3741
3742static void b43_wireless_core_detach(struct b43_wldev *dev)
3743{
3744 /* We release firmware that late to not be required to re-request
3745 * is all the time when we reinit the core. */
3746 b43_release_firmware(dev);
3747}
3748
3749static int b43_wireless_core_attach(struct b43_wldev *dev)
3750{
3751 struct b43_wl *wl = dev->wl;
3752 struct ssb_bus *bus = dev->dev->bus;
3753 struct pci_dev *pdev = bus->host_pci;
3754 int err;
96c755a3 3755 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 3756 u32 tmp;
3757
3758 /* Do NOT do any device initialization here.
3759 * Do it in wireless_core_init() instead.
3760 * This function is for gathering basic information about the HW, only.
3761 * Also some structs may be set up here. But most likely you want to have
3762 * that in core_init(), too.
3763 */
3764
3765 err = ssb_bus_powerup(bus, 0);
3766 if (err) {
3767 b43err(wl, "Bus powerup failed\n");
3768 goto out;
3769 }
3770 /* Get the PHY type. */
3771 if (dev->dev->id.revision >= 5) {
3772 u32 tmshigh;
3773
3774 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 3775 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3776 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 3777 } else
96c755a3 3778 B43_WARN_ON(1);
e4d6b795 3779
96c755a3 3780 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3781 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3782 b43_wireless_core_reset(dev, tmp);
3783
3784 err = b43_phy_versioning(dev);
3785 if (err)
21954c36 3786 goto err_powerdown;
e4d6b795
MB		 3787 /* Check if this device supports multiband. */
3788 if (!pdev ||
3789 (pdev->device != 0x4312 &&
3790 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3791 /* No multiband support. */
96c755a3
MB		 3792 have_2ghz_phy = 0;
3793 have_5ghz_phy = 0;
e4d6b795
MB		 3794 switch (dev->phy.type) {
3795 case B43_PHYTYPE_A:
96c755a3 3796 have_5ghz_phy = 1;
e4d6b795
MB		 3797 break;
3798 case B43_PHYTYPE_G:
96c755a3
MB		 3799 case B43_PHYTYPE_N:
3800 have_2ghz_phy = 1;
e4d6b795
MB		 3801 break;
3802 default:
3803 B43_WARN_ON(1);
3804 }
3805 }
96c755a3
MB		 3806 if (dev->phy.type == B43_PHYTYPE_A) {
3807 /* FIXME */
3808 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3809 err = -EOPNOTSUPP;
3810 goto err_powerdown;
3811 }
3812 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3813 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3814 b43_wireless_core_reset(dev, tmp);
3815
3816 err = b43_validate_chipaccess(dev);
3817 if (err)
21954c36 3818 goto err_powerdown;
96c755a3 3819 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 3820 if (err)
21954c36 3821 goto err_powerdown;
e4d6b795
MB		 3822
3823 /* Now set some default "current_dev" */
3824 if (!wl->current_dev)
3825 wl->current_dev = dev;
3826 INIT_WORK(&dev->restart_work, b43_chip_reset);
3827
8e9f7529 3828 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3829 b43_switch_analog(dev, 0);
3830 ssb_device_disable(dev->dev, 0);
3831 ssb_bus_may_powerdown(bus);
3832
3833out:
3834 return err;
3835
e4d6b795
MB		 3836err_powerdown:
3837 ssb_bus_may_powerdown(bus);
3838 return err;
3839}
3840
3841static void b43_one_core_detach(struct ssb_device *dev)
3842{
3843 struct b43_wldev *wldev;
3844 struct b43_wl *wl;
3845
3846 wldev = ssb_get_drvdata(dev);
3847 wl = wldev->wl;
3848 cancel_work_sync(&wldev->restart_work);
3849 b43_debugfs_remove_device(wldev);
3850 b43_wireless_core_detach(wldev);
3851 list_del(&wldev->list);
3852 wl->nr_devs--;
3853 ssb_set_drvdata(dev, NULL);
3854 kfree(wldev);
3855}
3856
3857static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3858{
3859 struct b43_wldev *wldev;
3860 struct pci_dev *pdev;
3861 int err = -ENOMEM;
3862
3863 if (!list_empty(&wl->devlist)) {
3864 /* We are not the first core on this chip. */
3865 pdev = dev->bus->host_pci;
3866 /* Only special chips support more than one wireless
3867 * core, although some of the other chips have more than
3868 * one wireless core as well. Check for this and
3869 * bail out early.
3870 */
3871 if (!pdev ||
3872 ((pdev->device != 0x4321) &&
3873 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3874 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3875 return -ENODEV;
3876 }
3877 }
3878
3879 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3880 if (!wldev)
3881 goto out;
3882
3883 wldev->dev = dev;
3884 wldev->wl = wl;
3885 b43_set_status(wldev, B43_STAT_UNINIT);
3886 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3887 tasklet_init(&wldev->isr_tasklet,
3888 (void (*)(unsigned long))b43_interrupt_tasklet,
3889 (unsigned long)wldev);
e4d6b795
MB		 3890 INIT_LIST_HEAD(&wldev->list);
3891
3892 err = b43_wireless_core_attach(wldev);
3893 if (err)
3894 goto err_kfree_wldev;
3895
3896 list_add(&wldev->list, &wl->devlist);
3897 wl->nr_devs++;
3898 ssb_set_drvdata(dev, wldev);
3899 b43_debugfs_add_device(wldev);
3900
3901 out:
3902 return err;
3903
3904 err_kfree_wldev:
3905 kfree(wldev);
3906 return err;
3907}
3908
3909static void b43_sprom_fixup(struct ssb_bus *bus)
3910{
3911 /* boardflags workarounds */
3912 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3913 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 3914 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 3915 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3916 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 3917 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
e4d6b795
MB		 3918}
3919
3920static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3921{
3922 struct ieee80211_hw *hw = wl->hw;
3923
3924 ssb_set_devtypedata(dev, NULL);
3925 ieee80211_free_hw(hw);
3926}
3927
3928static int b43_wireless_init(struct ssb_device *dev)
3929{
3930 struct ssb_sprom *sprom = &dev->bus->sprom;
3931 struct ieee80211_hw *hw;
3932 struct b43_wl *wl;
3933 int err = -ENOMEM;
3934
3935 b43_sprom_fixup(dev->bus);
3936
3937 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3938 if (!hw) {
3939 b43err(NULL, "Could not allocate ieee80211 device\n");
3940 goto out;
3941 }
3942
3943 /* fill hw info */
d8be11ee
JB		 3944 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3945 IEEE80211_HW_RX_INCLUDES_FCS;
e4d6b795
MB		 3946 hw->max_signal = 100;
3947 hw->max_rssi = -110;
3948 hw->max_noise = -110;
3949 hw->queues = 1; /* FIXME: hardware has more queues */
3950 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 3951 if (is_valid_ether_addr(sprom->et1mac))
3952 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 3953 else
95de2841 3954 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 3955
3956 /* Get and initialize struct b43_wl */
3957 wl = hw_to_b43_wl(hw);
3958 memset(wl, 0, sizeof(*wl));
3959 wl->hw = hw;
3960 spin_lock_init(&wl->irq_lock);
3961 spin_lock_init(&wl->leds_lock);
280d0e16 3962 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 3963 mutex_init(&wl->mutex);
3964 INIT_LIST_HEAD(&wl->devlist);
3965
3966 ssb_set_devtypedata(dev, wl);
3967 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3968 err = 0;
3969 out:
3970 return err;
3971}
3972
3973static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3974{
3975 struct b43_wl *wl;
3976 int err;
3977 int first = 0;
3978
3979 wl = ssb_get_devtypedata(dev);
3980 if (!wl) {
3981 /* Probing the first core. Must setup common struct b43_wl */
3982 first = 1;
3983 err = b43_wireless_init(dev);
3984 if (err)
3985 goto out;
3986 wl = ssb_get_devtypedata(dev);
3987 B43_WARN_ON(!wl);
3988 }
3989 err = b43_one_core_attach(dev, wl);
3990 if (err)
3991 goto err_wireless_exit;
3992
3993 if (first) {
3994 err = ieee80211_register_hw(wl->hw);
3995 if (err)
3996 goto err_one_core_detach;
3997 }
3998
3999 out:
4000 return err;
4001
4002 err_one_core_detach:
4003 b43_one_core_detach(dev);
4004 err_wireless_exit:
4005 if (first)
4006 b43_wireless_exit(dev, wl);
4007 return err;
4008}
4009
4010static void b43_remove(struct ssb_device *dev)
4011{
4012 struct b43_wl *wl = ssb_get_devtypedata(dev);
4013 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4014
4015 B43_WARN_ON(!wl);
4016 if (wl->current_dev == wldev)
4017 ieee80211_unregister_hw(wl->hw);
4018
4019 b43_one_core_detach(dev);
4020
4021 if (list_empty(&wl->devlist)) {
4022 /* Last core on the chip unregistered.
4023 * We can destroy common struct b43_wl.
4024 */
4025 b43_wireless_exit(dev, wl);
4026 }
4027}
4028
4029/* Perform a hardware reset. This can be called from any context. */
4030void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4031{
4032 /* Must avoid requeueing, if we are in shutdown. */
4033 if (b43_status(dev) < B43_STAT_INITIALIZED)
4034 return;
4035 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4036 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4037}
4038
4039#ifdef CONFIG_PM
4040
4041static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4042{
4043 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4044 struct b43_wl *wl = wldev->wl;
4045
4046 b43dbg(wl, "Suspending...\n");
4047
4048 mutex_lock(&wl->mutex);
4049 wldev->suspend_init_status = b43_status(wldev);
4050 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4051 b43_wireless_core_stop(wldev);
4052 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4053 b43_wireless_core_exit(wldev);
4054 mutex_unlock(&wl->mutex);
4055
4056 b43dbg(wl, "Device suspended.\n");
4057
4058 return 0;
4059}
4060
4061static int b43_resume(struct ssb_device *dev)
4062{
4063 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4064 struct b43_wl *wl = wldev->wl;
4065 int err = 0;
4066
4067 b43dbg(wl, "Resuming...\n");
4068
4069 mutex_lock(&wl->mutex);
4070 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4071 err = b43_wireless_core_init(wldev);
4072 if (err) {
4073 b43err(wl, "Resume failed at core init\n");
4074 goto out;
4075 }
4076 }
4077 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4078 err = b43_wireless_core_start(wldev);
4079 if (err) {
4080 b43_wireless_core_exit(wldev);
4081 b43err(wl, "Resume failed at core start\n");
4082 goto out;
4083 }
4084 }
4085 mutex_unlock(&wl->mutex);
4086
4087 b43dbg(wl, "Device resumed.\n");
4088 out:
4089 return err;
4090}
4091
4092#else /* CONFIG_PM */
4093# define b43_suspend NULL
4094# define b43_resume NULL
4095#endif /* CONFIG_PM */
4096
4097static struct ssb_driver b43_ssb_driver = {
4098 .name = KBUILD_MODNAME,
4099 .id_table = b43_ssb_tbl,
4100 .probe = b43_probe,
4101 .remove = b43_remove,
4102 .suspend = b43_suspend,
4103 .resume = b43_resume,
4104};
4105
4106static int __init b43_init(void)
4107{
4108 int err;
4109
4110 b43_debugfs_init();
4111 err = b43_pcmcia_init();
4112 if (err)
4113 goto err_dfs_exit;
4114 err = ssb_driver_register(&b43_ssb_driver);
4115 if (err)
4116 goto err_pcmcia_exit;
4117
4118 return err;
4119
4120err_pcmcia_exit:
4121 b43_pcmcia_exit();
4122err_dfs_exit:
4123 b43_debugfs_exit();
4124 return err;
4125}
4126
4127static void __exit b43_exit(void)
4128{
4129 ssb_driver_unregister(&b43_ssb_driver);
4130 b43_pcmcia_exit();
4131 b43_debugfs_exit();
4132}
4133
4134module_init(b43_init)
4135module_exit(b43_exit)
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