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[B43]: RF-kill support
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
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e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
47#include "phy.h"
48#include "dma.h"
49#include "pio.h"
50#include "sysfs.h"
51#include "xmit.h"
52#include "sysfs.h"
53#include "lo.h"
54#include "pcmcia.h"
55
56MODULE_DESCRIPTION("Broadcom B43 wireless driver");
57MODULE_AUTHOR("Martin Langer");
58MODULE_AUTHOR("Stefano Brivio");
59MODULE_AUTHOR("Michael Buesch");
60MODULE_LICENSE("GPL");
61
62extern char *nvram_get(char *name);
63
64#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
65static int modparam_pio;
66module_param_named(pio, modparam_pio, int, 0444);
67MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
68#elif defined(CONFIG_B43_DMA)
69# define modparam_pio 0
70#elif defined(CONFIG_B43_PIO)
71# define modparam_pio 1
72#endif
73
74static int modparam_bad_frames_preempt;
75module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
76MODULE_PARM_DESC(bad_frames_preempt,
77 "enable(1) / disable(0) Bad Frames Preemption");
78
79static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
80module_param_named(short_retry, modparam_short_retry, int, 0444);
81MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
82
83static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
84module_param_named(long_retry, modparam_long_retry, int, 0444);
85MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
86
e4d6b795
MB		 87static char modparam_fwpostfix[16];
88module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
89MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
90
e4d6b795
MB		 91static int modparam_hwpctl;
92module_param_named(hwpctl, modparam_hwpctl, int, 0444);
93MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
94
95static int modparam_nohwcrypt;
96module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
97MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
98
99static const struct ssb_device_id b43_ssb_tbl[] = {
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
105 SSB_DEVTABLE_END
106};
107
108MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
109
110/* Channel and ratetables are shared for all devices.
111 * They can't be const, because ieee80211 puts some precalculated
112 * data in there. This data is the same for all devices, so we don't
113 * get concurrency issues */
114#define RATETAB_ENT(_rateid, _flags) \
115 { \
116 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
117 .val = (_rateid), \
118 .val2 = (_rateid), \
119 .flags = (_flags), \
120 }
121static struct ieee80211_rate __b43_ratetable[] = {
122 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
123 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
124 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
125 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
126 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
127 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
128 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
129 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
130 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
131 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
132 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
133 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
134};
135
136#define b43_a_ratetable (__b43_ratetable + 4)
137#define b43_a_ratetable_size 8
138#define b43_b_ratetable (__b43_ratetable + 0)
139#define b43_b_ratetable_size 4
140#define b43_g_ratetable (__b43_ratetable + 0)
141#define b43_g_ratetable_size 12
142
143#define CHANTAB_ENT(_chanid, _freq) \
144 { \
145 .chan = (_chanid), \
146 .freq = (_freq), \
147 .val = (_chanid), \
148 .flag = IEEE80211_CHAN_W_SCAN | \
149 IEEE80211_CHAN_W_ACTIVE_SCAN | \
150 IEEE80211_CHAN_W_IBSS, \
151 .power_level = 0xFF, \
152 .antenna_max = 0xFF, \
153 }
154static struct ieee80211_channel b43_bg_chantable[] = {
155 CHANTAB_ENT(1, 2412),
156 CHANTAB_ENT(2, 2417),
157 CHANTAB_ENT(3, 2422),
158 CHANTAB_ENT(4, 2427),
159 CHANTAB_ENT(5, 2432),
160 CHANTAB_ENT(6, 2437),
161 CHANTAB_ENT(7, 2442),
162 CHANTAB_ENT(8, 2447),
163 CHANTAB_ENT(9, 2452),
164 CHANTAB_ENT(10, 2457),
165 CHANTAB_ENT(11, 2462),
166 CHANTAB_ENT(12, 2467),
167 CHANTAB_ENT(13, 2472),
168 CHANTAB_ENT(14, 2484),
169};
170
171#define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
172static struct ieee80211_channel b43_a_chantable[] = {
173 CHANTAB_ENT(36, 5180),
174 CHANTAB_ENT(40, 5200),
175 CHANTAB_ENT(44, 5220),
176 CHANTAB_ENT(48, 5240),
177 CHANTAB_ENT(52, 5260),
178 CHANTAB_ENT(56, 5280),
179 CHANTAB_ENT(60, 5300),
180 CHANTAB_ENT(64, 5320),
181 CHANTAB_ENT(149, 5745),
182 CHANTAB_ENT(153, 5765),
183 CHANTAB_ENT(157, 5785),
184 CHANTAB_ENT(161, 5805),
185 CHANTAB_ENT(165, 5825),
186};
187
188#define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
189
190static void b43_wireless_core_exit(struct b43_wldev *dev);
191static int b43_wireless_core_init(struct b43_wldev *dev);
192static void b43_wireless_core_stop(struct b43_wldev *dev);
193static int b43_wireless_core_start(struct b43_wldev *dev);
194
195static int b43_ratelimit(struct b43_wl *wl)
196{
197 if (!wl || !wl->current_dev)
198 return 1;
199 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
200 return 1;
201 /* We are up and running.
202 * Ratelimit the messages to avoid DoS over the net. */
203 return net_ratelimit();
204}
205
206void b43info(struct b43_wl *wl, const char *fmt, ...)
207{
208 va_list args;
209
210 if (!b43_ratelimit(wl))
211 return;
212 va_start(args, fmt);
213 printk(KERN_INFO "b43-%s: ",
214 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
215 vprintk(fmt, args);
216 va_end(args);
217}
218
219void b43err(struct b43_wl *wl, const char *fmt, ...)
220{
221 va_list args;
222
223 if (!b43_ratelimit(wl))
224 return;
225 va_start(args, fmt);
226 printk(KERN_ERR "b43-%s ERROR: ",
227 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
228 vprintk(fmt, args);
229 va_end(args);
230}
231
232void b43warn(struct b43_wl *wl, const char *fmt, ...)
233{
234 va_list args;
235
236 if (!b43_ratelimit(wl))
237 return;
238 va_start(args, fmt);
239 printk(KERN_WARNING "b43-%s warning: ",
240 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
241 vprintk(fmt, args);
242 va_end(args);
243}
244
245#if B43_DEBUG
246void b43dbg(struct b43_wl *wl, const char *fmt, ...)
247{
248 va_list args;
249
250 va_start(args, fmt);
251 printk(KERN_DEBUG "b43-%s debug: ",
252 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
253 vprintk(fmt, args);
254 va_end(args);
255}
256#endif /* DEBUG */
257
258static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
259{
260 u32 macctl;
261
262 B43_WARN_ON(offset % 4 != 0);
263
264 macctl = b43_read32(dev, B43_MMIO_MACCTL);
265 if (macctl & B43_MACCTL_BE)
266 val = swab32(val);
267
268 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
269 mmiowb();
270 b43_write32(dev, B43_MMIO_RAM_DATA, val);
271}
272
273static inline
274 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
275{
276 u32 control;
277
278 /* "offset" is the WORD offset. */
279
280 control = routing;
281 control <<= 16;
282 control |= offset;
283 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
284}
285
286u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
287{
288 u32 ret;
289
290 if (routing == B43_SHM_SHARED) {
291 B43_WARN_ON(offset & 0x0001);
292 if (offset & 0x0003) {
293 /* Unaligned access */
294 b43_shm_control_word(dev, routing, offset >> 2);
295 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
296 ret <<= 16;
297 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
298 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
299
300 return ret;
301 }
302 offset >>= 2;
303 }
304 b43_shm_control_word(dev, routing, offset);
305 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
306
307 return ret;
308}
309
310u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
311{
312 u16 ret;
313
314 if (routing == B43_SHM_SHARED) {
315 B43_WARN_ON(offset & 0x0001);
316 if (offset & 0x0003) {
317 /* Unaligned access */
318 b43_shm_control_word(dev, routing, offset >> 2);
319 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
320
321 return ret;
322 }
323 offset >>= 2;
324 }
325 b43_shm_control_word(dev, routing, offset);
326 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
327
328 return ret;
329}
330
331void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
332{
333 if (routing == B43_SHM_SHARED) {
334 B43_WARN_ON(offset & 0x0001);
335 if (offset & 0x0003) {
336 /* Unaligned access */
337 b43_shm_control_word(dev, routing, offset >> 2);
338 mmiowb();
339 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
340 (value >> 16) & 0xffff);
341 mmiowb();
342 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
343 mmiowb();
344 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
345 return;
346 }
347 offset >>= 2;
348 }
349 b43_shm_control_word(dev, routing, offset);
350 mmiowb();
351 b43_write32(dev, B43_MMIO_SHM_DATA, value);
352}
353
354void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
355{
356 if (routing == B43_SHM_SHARED) {
357 B43_WARN_ON(offset & 0x0001);
358 if (offset & 0x0003) {
359 /* Unaligned access */
360 b43_shm_control_word(dev, routing, offset >> 2);
361 mmiowb();
362 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
363 return;
364 }
365 offset >>= 2;
366 }
367 b43_shm_control_word(dev, routing, offset);
368 mmiowb();
369 b43_write16(dev, B43_MMIO_SHM_DATA, value);
370}
371
372/* Read HostFlags */
373u32 b43_hf_read(struct b43_wldev * dev)
374{
375 u32 ret;
376
377 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
378 ret <<= 16;
379 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
380
381 return ret;
382}
383
384/* Write HostFlags */
385void b43_hf_write(struct b43_wldev *dev, u32 value)
386{
387 b43_shm_write16(dev, B43_SHM_SHARED,
388 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
389 b43_shm_write16(dev, B43_SHM_SHARED,
390 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
391}
392
393void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
394{
395 /* We need to be careful. As we read the TSF from multiple
396 * registers, we should take care of register overflows.
397 * In theory, the whole tsf read process should be atomic.
398 * We try to be atomic here, by restaring the read process,
399 * if any of the high registers changed (overflew).
400 */
401 if (dev->dev->id.revision >= 3) {
402 u32 low, high, high2;
403
404 do {
405 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
406 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
407 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
408 } while (unlikely(high != high2));
409
410 *tsf = high;
411 *tsf <<= 32;
412 *tsf |= low;
413 } else {
414 u64 tmp;
415 u16 v0, v1, v2, v3;
416 u16 test1, test2, test3;
417
418 do {
419 v3 = b43_read16(dev, B43_MMIO_TSF_3);
420 v2 = b43_read16(dev, B43_MMIO_TSF_2);
421 v1 = b43_read16(dev, B43_MMIO_TSF_1);
422 v0 = b43_read16(dev, B43_MMIO_TSF_0);
423
424 test3 = b43_read16(dev, B43_MMIO_TSF_3);
425 test2 = b43_read16(dev, B43_MMIO_TSF_2);
426 test1 = b43_read16(dev, B43_MMIO_TSF_1);
427 } while (v3 != test3 || v2 != test2 || v1 != test1);
428
429 *tsf = v3;
430 *tsf <<= 48;
431 tmp = v2;
432 tmp <<= 32;
433 *tsf |= tmp;
434 tmp = v1;
435 tmp <<= 16;
436 *tsf |= tmp;
437 *tsf |= v0;
438 }
439}
440
441static void b43_time_lock(struct b43_wldev *dev)
442{
443 u32 macctl;
444
445 macctl = b43_read32(dev, B43_MMIO_MACCTL);
446 macctl |= B43_MACCTL_TBTTHOLD;
447 b43_write32(dev, B43_MMIO_MACCTL, macctl);
448 /* Commit the write */
449 b43_read32(dev, B43_MMIO_MACCTL);
450}
451
452static void b43_time_unlock(struct b43_wldev *dev)
453{
454 u32 macctl;
455
456 macctl = b43_read32(dev, B43_MMIO_MACCTL);
457 macctl &= ~B43_MACCTL_TBTTHOLD;
458 b43_write32(dev, B43_MMIO_MACCTL, macctl);
459 /* Commit the write */
460 b43_read32(dev, B43_MMIO_MACCTL);
461}
462
463static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
464{
465 /* Be careful with the in-progress timer.
466 * First zero out the low register, so we have a full
467 * register-overflow duration to complete the operation.
468 */
469 if (dev->dev->id.revision >= 3) {
470 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
471 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
472
473 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
474 mmiowb();
475 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
476 mmiowb();
477 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
478 } else {
479 u16 v0 = (tsf & 0x000000000000FFFFULL);
480 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
481 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
482 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483
484 b43_write16(dev, B43_MMIO_TSF_0, 0);
485 mmiowb();
486 b43_write16(dev, B43_MMIO_TSF_3, v3);
487 mmiowb();
488 b43_write16(dev, B43_MMIO_TSF_2, v2);
489 mmiowb();
490 b43_write16(dev, B43_MMIO_TSF_1, v1);
491 mmiowb();
492 b43_write16(dev, B43_MMIO_TSF_0, v0);
493 }
494}
495
496void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
497{
498 b43_time_lock(dev);
499 b43_tsf_write_locked(dev, tsf);
500 b43_time_unlock(dev);
501}
502
503static
504void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
505{
506 static const u8 zero_addr[ETH_ALEN] = { 0 };
507 u16 data;
508
509 if (!mac)
510 mac = zero_addr;
511
512 offset |= 0x0020;
513 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
514
515 data = mac[0];
516 data |= mac[1] << 8;
517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 data = mac[2];
519 data |= mac[3] << 8;
520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
521 data = mac[4];
522 data |= mac[5] << 8;
523 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
524}
525
526static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
527{
528 const u8 *mac;
529 const u8 *bssid;
530 u8 mac_bssid[ETH_ALEN * 2];
531 int i;
532 u32 tmp;
533
534 bssid = dev->wl->bssid;
535 mac = dev->wl->mac_addr;
536
537 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
538
539 memcpy(mac_bssid, mac, ETH_ALEN);
540 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
541
542 /* Write our MAC address and BSSID to template ram */
543 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
544 tmp = (u32) (mac_bssid[i + 0]);
545 tmp |= (u32) (mac_bssid[i + 1]) << 8;
546 tmp |= (u32) (mac_bssid[i + 2]) << 16;
547 tmp |= (u32) (mac_bssid[i + 3]) << 24;
548 b43_ram_write(dev, 0x20 + i, tmp);
549 }
550}
551
4150c572 552static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 553{
e4d6b795 554 b43_write_mac_bssid_templates(dev);
4150c572 555 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 556}
557
558static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
559{
560 /* slot_time is in usec. */
561 if (dev->phy.type != B43_PHYTYPE_G)
562 return;
563 b43_write16(dev, 0x684, 510 + slot_time);
564 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
565}
566
567static void b43_short_slot_timing_enable(struct b43_wldev *dev)
568{
569 b43_set_slot_time(dev, 9);
570 dev->short_slot = 1;
571}
572
573static void b43_short_slot_timing_disable(struct b43_wldev *dev)
574{
575 b43_set_slot_time(dev, 20);
576 dev->short_slot = 0;
577}
578
579/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
580 * Returns the _previously_ enabled IRQ mask.
581 */
582static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
583{
584 u32 old_mask;
585
586 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
587 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
588
589 return old_mask;
590}
591
592/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
593 * Returns the _previously_ enabled IRQ mask.
594 */
595static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
596{
597 u32 old_mask;
598
599 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
600 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
601
602 return old_mask;
603}
604
605/* Synchronize IRQ top- and bottom-half.
606 * IRQs must be masked before calling this.
607 * This must not be called with the irq_lock held.
608 */
609static void b43_synchronize_irq(struct b43_wldev *dev)
610{
611 synchronize_irq(dev->dev->irq);
612 tasklet_kill(&dev->isr_tasklet);
613}
614
615/* DummyTransmission function, as documented on
616 * http://bcm-specs.sipsolutions.net/DummyTransmission
617 */
618void b43_dummy_transmission(struct b43_wldev *dev)
619{
620 struct b43_phy *phy = &dev->phy;
621 unsigned int i, max_loop;
622 u16 value;
623 u32 buffer[5] = {
624 0x00000000,
625 0x00D40000,
626 0x00000000,
627 0x01000000,
628 0x00000000,
629 };
630
631 switch (phy->type) {
632 case B43_PHYTYPE_A:
633 max_loop = 0x1E;
634 buffer[0] = 0x000201CC;
635 break;
636 case B43_PHYTYPE_B:
637 case B43_PHYTYPE_G:
638 max_loop = 0xFA;
639 buffer[0] = 0x000B846E;
640 break;
641 default:
642 B43_WARN_ON(1);
643 return;
644 }
645
646 for (i = 0; i < 5; i++)
647 b43_ram_write(dev, i * 4, buffer[i]);
648
649 /* Commit writes */
650 b43_read32(dev, B43_MMIO_MACCTL);
651
652 b43_write16(dev, 0x0568, 0x0000);
653 b43_write16(dev, 0x07C0, 0x0000);
654 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
655 b43_write16(dev, 0x050C, value);
656 b43_write16(dev, 0x0508, 0x0000);
657 b43_write16(dev, 0x050A, 0x0000);
658 b43_write16(dev, 0x054C, 0x0000);
659 b43_write16(dev, 0x056A, 0x0014);
660 b43_write16(dev, 0x0568, 0x0826);
661 b43_write16(dev, 0x0500, 0x0000);
662 b43_write16(dev, 0x0502, 0x0030);
663
664 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
665 b43_radio_write16(dev, 0x0051, 0x0017);
666 for (i = 0x00; i < max_loop; i++) {
667 value = b43_read16(dev, 0x050E);
668 if (value & 0x0080)
669 break;
670 udelay(10);
671 }
672 for (i = 0x00; i < 0x0A; i++) {
673 value = b43_read16(dev, 0x050E);
674 if (value & 0x0400)
675 break;
676 udelay(10);
677 }
678 for (i = 0x00; i < 0x0A; i++) {
679 value = b43_read16(dev, 0x0690);
680 if (!(value & 0x0100))
681 break;
682 udelay(10);
683 }
684 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
685 b43_radio_write16(dev, 0x0051, 0x0037);
686}
687
688static void key_write(struct b43_wldev *dev,
689 u8 index, u8 algorithm, const u8 * key)
690{
691 unsigned int i;
692 u32 offset;
693 u16 value;
694 u16 kidx;
695
696 /* Key index/algo block */
697 kidx = b43_kidx_to_fw(dev, index);
698 value = ((kidx << 4) | algorithm);
699 b43_shm_write16(dev, B43_SHM_SHARED,
700 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
701
702 /* Write the key to the Key Table Pointer offset */
703 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
704 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
705 value = key[i];
706 value |= (u16) (key[i + 1]) << 8;
707 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
708 }
709}
710
711static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
712{
713 u32 addrtmp[2] = { 0, 0, };
714 u8 per_sta_keys_start = 8;
715
716 if (b43_new_kidx_api(dev))
717 per_sta_keys_start = 4;
718
719 B43_WARN_ON(index < per_sta_keys_start);
720 /* We have two default TX keys and possibly two default RX keys.
721 * Physical mac 0 is mapped to physical key 4 or 8, depending
722 * on the firmware version.
723 * So we must adjust the index here.
724 */
725 index -= per_sta_keys_start;
726
727 if (addr) {
728 addrtmp[0] = addr[0];
729 addrtmp[0] |= ((u32) (addr[1]) << 8);
730 addrtmp[0] |= ((u32) (addr[2]) << 16);
731 addrtmp[0] |= ((u32) (addr[3]) << 24);
732 addrtmp[1] = addr[4];
733 addrtmp[1] |= ((u32) (addr[5]) << 8);
734 }
735
736 if (dev->dev->id.revision >= 5) {
737 /* Receive match transmitter address mechanism */
738 b43_shm_write32(dev, B43_SHM_RCMTA,
739 (index * 2) + 0, addrtmp[0]);
740 b43_shm_write16(dev, B43_SHM_RCMTA,
741 (index * 2) + 1, addrtmp[1]);
742 } else {
743 /* RXE (Receive Engine) and
744 * PSM (Programmable State Machine) mechanism
745 */
746 if (index < 8) {
747 /* TODO write to RCM 16, 19, 22 and 25 */
748 } else {
749 b43_shm_write32(dev, B43_SHM_SHARED,
750 B43_SHM_SH_PSM + (index * 6) + 0,
751 addrtmp[0]);
752 b43_shm_write16(dev, B43_SHM_SHARED,
753 B43_SHM_SH_PSM + (index * 6) + 4,
754 addrtmp[1]);
755 }
756 }
757}
758
759static void do_key_write(struct b43_wldev *dev,
760 u8 index, u8 algorithm,
761 const u8 * key, size_t key_len, const u8 * mac_addr)
762{
763 u8 buf[B43_SEC_KEYSIZE] = { 0, };
764 u8 per_sta_keys_start = 8;
765
766 if (b43_new_kidx_api(dev))
767 per_sta_keys_start = 4;
768
769 B43_WARN_ON(index >= dev->max_nr_keys);
770 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
771
772 if (index >= per_sta_keys_start)
773 keymac_write(dev, index, NULL); /* First zero out mac. */
774 if (key)
775 memcpy(buf, key, key_len);
776 key_write(dev, index, algorithm, buf);
777 if (index >= per_sta_keys_start)
778 keymac_write(dev, index, mac_addr);
779
780 dev->key[index].algorithm = algorithm;
781}
782
783static int b43_key_write(struct b43_wldev *dev,
784 int index, u8 algorithm,
785 const u8 * key, size_t key_len,
786 const u8 * mac_addr,
787 struct ieee80211_key_conf *keyconf)
788{
789 int i;
790 int sta_keys_start;
791
792 if (key_len > B43_SEC_KEYSIZE)
793 return -EINVAL;
794 for (i = 0; i < dev->max_nr_keys; i++) {
795 /* Check that we don't already have this key. */
796 B43_WARN_ON(dev->key[i].keyconf == keyconf);
797 }
798 if (index < 0) {
799 /* Either pairwise key or address is 00:00:00:00:00:00
800 * for transmit-only keys. Search the index. */
801 if (b43_new_kidx_api(dev))
802 sta_keys_start = 4;
803 else
804 sta_keys_start = 8;
805 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
806 if (!dev->key[i].keyconf) {
807 /* found empty */
808 index = i;
809 break;
810 }
811 }
812 if (index < 0) {
813 b43err(dev->wl, "Out of hardware key memory\n");
814 return -ENOSPC;
815 }
816 } else
817 B43_WARN_ON(index > 3);
818
819 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
820 if ((index <= 3) && !b43_new_kidx_api(dev)) {
821 /* Default RX key */
822 B43_WARN_ON(mac_addr);
823 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
824 }
825 keyconf->hw_key_idx = index;
826 dev->key[index].keyconf = keyconf;
827
828 return 0;
829}
830
831static int b43_key_clear(struct b43_wldev *dev, int index)
832{
833 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
834 return -EINVAL;
835 do_key_write(dev, index, B43_SEC_ALGO_NONE,
836 NULL, B43_SEC_KEYSIZE, NULL);
837 if ((index <= 3) && !b43_new_kidx_api(dev)) {
838 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
839 NULL, B43_SEC_KEYSIZE, NULL);
840 }
841 dev->key[index].keyconf = NULL;
842
843 return 0;
844}
845
846static void b43_clear_keys(struct b43_wldev *dev)
847{
848 int i;
849
850 for (i = 0; i < dev->max_nr_keys; i++)
851 b43_key_clear(dev, i);
852}
853
854void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
855{
856 u32 macctl;
857 u16 ucstat;
858 bool hwps;
859 bool awake;
860 int i;
861
862 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
863 (ps_flags & B43_PS_DISABLED));
864 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
865
866 if (ps_flags & B43_PS_ENABLED) {
867 hwps = 1;
868 } else if (ps_flags & B43_PS_DISABLED) {
869 hwps = 0;
870 } else {
871 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
872 // and thus is not an AP and we are associated, set bit 25
873 }
874 if (ps_flags & B43_PS_AWAKE) {
875 awake = 1;
876 } else if (ps_flags & B43_PS_ASLEEP) {
877 awake = 0;
878 } else {
879 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
880 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
881 // successful, set bit26
882 }
883
884/* FIXME: For now we force awake-on and hwps-off */
885 hwps = 0;
886 awake = 1;
887
888 macctl = b43_read32(dev, B43_MMIO_MACCTL);
889 if (hwps)
890 macctl |= B43_MACCTL_HWPS;
891 else
892 macctl &= ~B43_MACCTL_HWPS;
893 if (awake)
894 macctl |= B43_MACCTL_AWAKE;
895 else
896 macctl &= ~B43_MACCTL_AWAKE;
897 b43_write32(dev, B43_MMIO_MACCTL, macctl);
898 /* Commit write */
899 b43_read32(dev, B43_MMIO_MACCTL);
900 if (awake && dev->dev->id.revision >= 5) {
901 /* Wait for the microcode to wake up. */
902 for (i = 0; i < 100; i++) {
903 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
904 B43_SHM_SH_UCODESTAT);
905 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
906 break;
907 udelay(10);
908 }
909 }
910}
911
912/* Turn the Analog ON/OFF */
913static void b43_switch_analog(struct b43_wldev *dev, int on)
914{
915 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
916}
917
918void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
919{
920 u32 tmslow;
921 u32 macctl;
922
923 flags |= B43_TMSLOW_PHYCLKEN;
924 flags |= B43_TMSLOW_PHYRESET;
925 ssb_device_enable(dev->dev, flags);
926 msleep(2); /* Wait for the PLL to turn on. */
927
928 /* Now take the PHY out of Reset again */
929 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
930 tmslow |= SSB_TMSLOW_FGC;
931 tmslow &= ~B43_TMSLOW_PHYRESET;
932 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
933 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
934 msleep(1);
935 tmslow &= ~SSB_TMSLOW_FGC;
936 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
937 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
938 msleep(1);
939
940 /* Turn Analog ON */
941 b43_switch_analog(dev, 1);
942
943 macctl = b43_read32(dev, B43_MMIO_MACCTL);
944 macctl &= ~B43_MACCTL_GMODE;
945 if (flags & B43_TMSLOW_GMODE)
946 macctl |= B43_MACCTL_GMODE;
947 macctl |= B43_MACCTL_IHR_ENABLED;
948 b43_write32(dev, B43_MMIO_MACCTL, macctl);
949}
950
951static void handle_irq_transmit_status(struct b43_wldev *dev)
952{
953 u32 v0, v1;
954 u16 tmp;
955 struct b43_txstatus stat;
956
957 while (1) {
958 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
959 if (!(v0 & 0x00000001))
960 break;
961 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
962
963 stat.cookie = (v0 >> 16);
964 stat.seq = (v1 & 0x0000FFFF);
965 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
966 tmp = (v0 & 0x0000FFFF);
967 stat.frame_count = ((tmp & 0xF000) >> 12);
968 stat.rts_count = ((tmp & 0x0F00) >> 8);
969 stat.supp_reason = ((tmp & 0x001C) >> 2);
970 stat.pm_indicated = !!(tmp & 0x0080);
971 stat.intermediate = !!(tmp & 0x0040);
972 stat.for_ampdu = !!(tmp & 0x0020);
973 stat.acked = !!(tmp & 0x0002);
974
975 b43_handle_txstatus(dev, &stat);
976 }
977}
978
979static void drain_txstatus_queue(struct b43_wldev *dev)
980{
981 u32 dummy;
982
983 if (dev->dev->id.revision < 5)
984 return;
985 /* Read all entries from the microcode TXstatus FIFO
986 * and throw them away.
987 */
988 while (1) {
989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
990 if (!(dummy & 0x00000001))
991 break;
992 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
993 }
994}
995
996static u32 b43_jssi_read(struct b43_wldev *dev)
997{
998 u32 val = 0;
999
1000 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1001 val <<= 16;
1002 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1003
1004 return val;
1005}
1006
1007static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1008{
1009 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1010 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1011}
1012
1013static void b43_generate_noise_sample(struct b43_wldev *dev)
1014{
1015 b43_jssi_write(dev, 0x7F7F7F7F);
1016 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1017 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1018 | (1 << 4));
1019 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1020}
1021
1022static void b43_calculate_link_quality(struct b43_wldev *dev)
1023{
1024 /* Top half of Link Quality calculation. */
1025
1026 if (dev->noisecalc.calculation_running)
1027 return;
1028 dev->noisecalc.channel_at_start = dev->phy.channel;
1029 dev->noisecalc.calculation_running = 1;
1030 dev->noisecalc.nr_samples = 0;
1031
1032 b43_generate_noise_sample(dev);
1033}
1034
1035static void handle_irq_noise(struct b43_wldev *dev)
1036{
1037 struct b43_phy *phy = &dev->phy;
1038 u16 tmp;
1039 u8 noise[4];
1040 u8 i, j;
1041 s32 average;
1042
1043 /* Bottom half of Link Quality calculation. */
1044
1045 B43_WARN_ON(!dev->noisecalc.calculation_running);
1046 if (dev->noisecalc.channel_at_start != phy->channel)
1047 goto drop_calculation;
1a09404a 1048 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1049 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1050 noise[2] == 0x7F || noise[3] == 0x7F)
1051 goto generate_new;
1052
1053 /* Get the noise samples. */
1054 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1055 i = dev->noisecalc.nr_samples;
1056 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1060 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1061 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1062 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1063 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1064 dev->noisecalc.nr_samples++;
1065 if (dev->noisecalc.nr_samples == 8) {
1066 /* Calculate the Link Quality by the noise samples. */
1067 average = 0;
1068 for (i = 0; i < 8; i++) {
1069 for (j = 0; j < 4; j++)
1070 average += dev->noisecalc.samples[i][j];
1071 }
1072 average /= (8 * 4);
1073 average *= 125;
1074 average += 64;
1075 average /= 128;
1076 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1077 tmp = (tmp / 128) & 0x1F;
1078 if (tmp >= 8)
1079 average += 2;
1080 else
1081 average -= 25;
1082 if (tmp == 8)
1083 average -= 72;
1084 else
1085 average -= 48;
1086
1087 dev->stats.link_noise = average;
1088 drop_calculation:
1089 dev->noisecalc.calculation_running = 0;
1090 return;
1091 }
1092 generate_new:
1093 b43_generate_noise_sample(dev);
1094}
1095
1096static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1097{
1098 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1099 ///TODO: PS TBTT
1100 } else {
1101 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1102 b43_power_saving_ctl_bits(dev, 0);
1103 }
1104 dev->reg124_set_0x4 = 0;
1105 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1106 dev->reg124_set_0x4 = 1;
1107}
1108
1109static void handle_irq_atim_end(struct b43_wldev *dev)
1110{
1111 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1112 return;
1113 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1114 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1115 | 0x4);
1116}
1117
1118static void handle_irq_pmq(struct b43_wldev *dev)
1119{
1120 u32 tmp;
1121
1122 //TODO: AP mode.
1123
1124 while (1) {
1125 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1126 if (!(tmp & 0x00000008))
1127 break;
1128 }
1129 /* 16bit write is odd, but correct. */
1130 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1131}
1132
1133static void b43_write_template_common(struct b43_wldev *dev,
1134 const u8 * data, u16 size,
1135 u16 ram_offset,
1136 u16 shm_size_offset, u8 rate)
1137{
1138 u32 i, tmp;
1139 struct b43_plcp_hdr4 plcp;
1140
1141 plcp.data = 0;
1142 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1143 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1144 ram_offset += sizeof(u32);
1145 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1146 * So leave the first two bytes of the next write blank.
1147 */
1148 tmp = (u32) (data[0]) << 16;
1149 tmp |= (u32) (data[1]) << 24;
1150 b43_ram_write(dev, ram_offset, tmp);
1151 ram_offset += sizeof(u32);
1152 for (i = 2; i < size; i += sizeof(u32)) {
1153 tmp = (u32) (data[i + 0]);
1154 if (i + 1 < size)
1155 tmp |= (u32) (data[i + 1]) << 8;
1156 if (i + 2 < size)
1157 tmp |= (u32) (data[i + 2]) << 16;
1158 if (i + 3 < size)
1159 tmp |= (u32) (data[i + 3]) << 24;
1160 b43_ram_write(dev, ram_offset + i - 2, tmp);
1161 }
1162 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1163 size + sizeof(struct b43_plcp_hdr6));
1164}
1165
1166static void b43_write_beacon_template(struct b43_wldev *dev,
1167 u16 ram_offset,
1168 u16 shm_size_offset, u8 rate)
1169{
1170 int len;
1171 const u8 *data;
1172
1173 B43_WARN_ON(!dev->cached_beacon);
1174 len = min((size_t) dev->cached_beacon->len,
1175 0x200 - sizeof(struct b43_plcp_hdr6));
1176 data = (const u8 *)(dev->cached_beacon->data);
1177 b43_write_template_common(dev, data,
1178 len, ram_offset, shm_size_offset, rate);
1179}
1180
1181static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1182 u16 shm_offset, u16 size, u8 rate)
1183{
1184 struct b43_plcp_hdr4 plcp;
1185 u32 tmp;
1186 __le16 dur;
1187
1188 plcp.data = 0;
1189 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1190 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1191 dev->wl->if_id, size,
1192 B43_RATE_TO_BASE100KBPS(rate));
1193 /* Write PLCP in two parts and timing for packet transfer */
1194 tmp = le32_to_cpu(plcp.data);
1195 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1196 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1197 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1198}
1199
1200/* Instead of using custom probe response template, this function
1201 * just patches custom beacon template by:
1202 * 1) Changing packet type
1203 * 2) Patching duration field
1204 * 3) Stripping TIM
1205 */
1206static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1207 u16 * dest_size, u8 rate)
1208{
1209 const u8 *src_data;
1210 u8 *dest_data;
1211 u16 src_size, elem_size, src_pos, dest_pos;
1212 __le16 dur;
1213 struct ieee80211_hdr *hdr;
1214
1215 B43_WARN_ON(!dev->cached_beacon);
1216 src_size = dev->cached_beacon->len;
1217 src_data = (const u8 *)dev->cached_beacon->data;
1218
1219 if (unlikely(src_size < 0x24)) {
1220 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1221 return NULL;
1222 }
1223
1224 dest_data = kmalloc(src_size, GFP_ATOMIC);
1225 if (unlikely(!dest_data))
1226 return NULL;
1227
1228 /* 0x24 is offset of first variable-len Information-Element
1229 * in beacon frame.
1230 */
1231 memcpy(dest_data, src_data, 0x24);
1232 src_pos = dest_pos = 0x24;
1233 for (; src_pos < src_size - 2; src_pos += elem_size) {
1234 elem_size = src_data[src_pos + 1] + 2;
1235 if (src_data[src_pos] != 0x05) { /* TIM */
1236 memcpy(dest_data + dest_pos, src_data + src_pos,
1237 elem_size);
1238 dest_pos += elem_size;
1239 }
1240 }
1241 *dest_size = dest_pos;
1242 hdr = (struct ieee80211_hdr *)dest_data;
1243
1244 /* Set the frame control. */
1245 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1246 IEEE80211_STYPE_PROBE_RESP);
1247 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1248 dev->wl->if_id, *dest_size,
1249 B43_RATE_TO_BASE100KBPS(rate));
1250 hdr->duration_id = dur;
1251
1252 return dest_data;
1253}
1254
1255static void b43_write_probe_resp_template(struct b43_wldev *dev,
1256 u16 ram_offset,
1257 u16 shm_size_offset, u8 rate)
1258{
1259 u8 *probe_resp_data;
1260 u16 size;
1261
1262 B43_WARN_ON(!dev->cached_beacon);
1263 size = dev->cached_beacon->len;
1264 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1265 if (unlikely(!probe_resp_data))
1266 return;
1267
1268 /* Looks like PLCP headers plus packet timings are stored for
1269 * all possible basic rates
1270 */
1271 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1272 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1273 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1274 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1275
1276 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1277 b43_write_template_common(dev, probe_resp_data,
1278 size, ram_offset, shm_size_offset, rate);
1279 kfree(probe_resp_data);
1280}
1281
1282static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1283 struct sk_buff *beacon)
1284{
1285 if (dev->cached_beacon)
1286 kfree_skb(dev->cached_beacon);
1287 dev->cached_beacon = beacon;
1288
1289 return 0;
1290}
1291
1292static void b43_update_templates(struct b43_wldev *dev)
1293{
1294 u32 status;
1295
1296 B43_WARN_ON(!dev->cached_beacon);
1297
1298 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1299 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1300 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1301
1302 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1303 status |= 0x03;
1304 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1305}
1306
1307static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1308{
1309 int err;
1310
1311 err = b43_refresh_cached_beacon(dev, beacon);
1312 if (unlikely(err))
1313 return;
1314 b43_update_templates(dev);
1315}
1316
1317static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1318{
1319 u32 tmp;
1320 u16 i, len;
1321
1322 len = min((u16) ssid_len, (u16) 0x100);
1323 for (i = 0; i < len; i += sizeof(u32)) {
1324 tmp = (u32) (ssid[i + 0]);
1325 if (i + 1 < len)
1326 tmp |= (u32) (ssid[i + 1]) << 8;
1327 if (i + 2 < len)
1328 tmp |= (u32) (ssid[i + 2]) << 16;
1329 if (i + 3 < len)
1330 tmp |= (u32) (ssid[i + 3]) << 24;
1331 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1332 }
1333 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1334}
1335
1336static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1337{
1338 b43_time_lock(dev);
1339 if (dev->dev->id.revision >= 3) {
1340 b43_write32(dev, 0x188, (beacon_int << 16));
1341 } else {
1342 b43_write16(dev, 0x606, (beacon_int >> 6));
1343 b43_write16(dev, 0x610, beacon_int);
1344 }
1345 b43_time_unlock(dev);
1346}
1347
1348static void handle_irq_beacon(struct b43_wldev *dev)
1349{
1350 u32 status;
1351
1352 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1353 return;
1354
1355 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1356 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1357
1358 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1359 /* ACK beacon IRQ. */
1360 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1361 dev->irq_savedstate |= B43_IRQ_BEACON;
1362 if (dev->cached_beacon)
1363 kfree_skb(dev->cached_beacon);
1364 dev->cached_beacon = NULL;
1365 return;
1366 }
1367 if (!(status & 0x1)) {
1368 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1369 status |= 0x1;
1370 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1371 }
1372 if (!(status & 0x2)) {
1373 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1374 status |= 0x2;
1375 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1376 }
1377}
1378
1379static void handle_irq_ucode_debug(struct b43_wldev *dev)
1380{
1381 //TODO
1382}
1383
1384/* Interrupt handler bottom-half */
1385static void b43_interrupt_tasklet(struct b43_wldev *dev)
1386{
1387 u32 reason;
1388 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1389 u32 merged_dma_reason = 0;
21954c36 1390 int i;
e4d6b795
MB		 1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1394
1395 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1396
1397 reason = dev->irq_reason;
1398 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1399 dma_reason[i] = dev->dma_reason[i];
1400 merged_dma_reason |= dma_reason[i];
1401 }
1402
1403 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1404 b43err(dev->wl, "MAC transmission error\n");
1405
1406 if (unlikely(reason & B43_IRQ_PHY_TXERR))
1407 b43err(dev->wl, "PHY transmission error\n");
1408
1409 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1410 B43_DMAIRQ_NONFATALMASK))) {
1411 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1412 b43err(dev->wl, "Fatal DMA error: "
1413 "0x%08X, 0x%08X, 0x%08X, "
1414 "0x%08X, 0x%08X, 0x%08X\n",
1415 dma_reason[0], dma_reason[1],
1416 dma_reason[2], dma_reason[3],
1417 dma_reason[4], dma_reason[5]);
1418 b43_controller_restart(dev, "DMA error");
1419 mmiowb();
1420 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1421 return;
1422 }
1423 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1424 b43err(dev->wl, "DMA error: "
1425 "0x%08X, 0x%08X, 0x%08X, "
1426 "0x%08X, 0x%08X, 0x%08X\n",
1427 dma_reason[0], dma_reason[1],
1428 dma_reason[2], dma_reason[3],
1429 dma_reason[4], dma_reason[5]);
1430 }
1431 }
1432
1433 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1434 handle_irq_ucode_debug(dev);
1435 if (reason & B43_IRQ_TBTT_INDI)
1436 handle_irq_tbtt_indication(dev);
1437 if (reason & B43_IRQ_ATIM_END)
1438 handle_irq_atim_end(dev);
1439 if (reason & B43_IRQ_BEACON)
1440 handle_irq_beacon(dev);
1441 if (reason & B43_IRQ_PMQ)
1442 handle_irq_pmq(dev);
21954c36
MB		 1443 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1444 ;/* TODO */
1445 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1446 handle_irq_noise(dev);
1447
1448 /* Check the DMA reason registers for received data. */
1449 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1450 if (b43_using_pio(dev))
1451 b43_pio_rx(dev->pio.queue0);
1452 else
1453 b43_dma_rx(dev->dma.rx_ring0);
e4d6b795
MB		 1454 }
1455 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1456 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1457 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1458 if (b43_using_pio(dev))
1459 b43_pio_rx(dev->pio.queue3);
1460 else
1461 b43_dma_rx(dev->dma.rx_ring3);
e4d6b795
MB		 1462 }
1463 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1464 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1465
21954c36 1466 if (reason & B43_IRQ_TX_OK)
e4d6b795 1467 handle_irq_transmit_status(dev);
e4d6b795 1468
e4d6b795
MB		 1469 b43_interrupt_enable(dev, dev->irq_savedstate);
1470 mmiowb();
1471 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1472}
1473
1474static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1475{
1476 u16 rxctl;
1477
1478 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1479 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1480 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1481 else
1482 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1483}
1484
1485static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1486{
1487 if (b43_using_pio(dev) &&
1488 (dev->dev->id.revision < 3) &&
1489 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1490 /* Apply a PIO specific workaround to the dma_reasons */
1491 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1492 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1493 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1494 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1495 }
1496
1497 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1498
1499 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1500 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1501 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1502 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1503 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1504 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1505}
1506
1507/* Interrupt handler top-half */
1508static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1509{
1510 irqreturn_t ret = IRQ_NONE;
1511 struct b43_wldev *dev = dev_id;
1512 u32 reason;
1513
1514 if (!dev)
1515 return IRQ_NONE;
1516
1517 spin_lock(&dev->wl->irq_lock);
1518
1519 if (b43_status(dev) < B43_STAT_STARTED)
1520 goto out;
1521 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1522 if (reason == 0xffffffff) /* shared IRQ */
1523 goto out;
1524 ret = IRQ_HANDLED;
1525 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1526 if (!reason)
1527 goto out;
1528
1529 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1530 & 0x0001DC00;
1531 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1532 & 0x0000DC00;
1533 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1534 & 0x0000DC00;
1535 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1536 & 0x0001DC00;
1537 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1538 & 0x0000DC00;
1539 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1540 & 0x0000DC00;
1541
1542 b43_interrupt_ack(dev, reason);
1543 /* disable all IRQs. They are enabled again in the bottom half. */
1544 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1545 /* save the reason code and call our bottom half. */
1546 dev->irq_reason = reason;
1547 tasklet_schedule(&dev->isr_tasklet);
1548 out:
1549 mmiowb();
1550 spin_unlock(&dev->wl->irq_lock);
1551
1552 return ret;
1553}
1554
1555static void b43_release_firmware(struct b43_wldev *dev)
1556{
1557 release_firmware(dev->fw.ucode);
1558 dev->fw.ucode = NULL;
1559 release_firmware(dev->fw.pcm);
1560 dev->fw.pcm = NULL;
1561 release_firmware(dev->fw.initvals);
1562 dev->fw.initvals = NULL;
1563 release_firmware(dev->fw.initvals_band);
1564 dev->fw.initvals_band = NULL;
1565}
1566
1567static void b43_print_fw_helptext(struct b43_wl *wl)
1568{
1569 b43err(wl, "You must go to "
1570 "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1571 "and download the correct firmware (version 4).\n");
1572}
1573
1574static int do_request_fw(struct b43_wldev *dev,
1575 const char *name,
1576 const struct firmware **fw)
1577{
1a09404a 1578 char path[sizeof(modparam_fwpostfix) + 32];
e4d6b795
MB		 1579 struct b43_fw_header *hdr;
1580 u32 size;
1581 int err;
1582
1583 if (!name)
1584 return 0;
1585
1586 snprintf(path, ARRAY_SIZE(path),
1587 "b43%s/%s.fw",
1588 modparam_fwpostfix, name);
1589 err = request_firmware(fw, path, dev->dev->dev);
1590 if (err) {
1591 b43err(dev->wl, "Firmware file \"%s\" not found "
1592 "or load failed.\n", path);
1593 return err;
1594 }
1595 if ((*fw)->size < sizeof(struct b43_fw_header))
1596 goto err_format;
1597 hdr = (struct b43_fw_header *)((*fw)->data);
1598 switch (hdr->type) {
1599 case B43_FW_TYPE_UCODE:
1600 case B43_FW_TYPE_PCM:
1601 size = be32_to_cpu(hdr->size);
1602 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1603 goto err_format;
1604 /* fallthrough */
1605 case B43_FW_TYPE_IV:
1606 if (hdr->ver != 1)
1607 goto err_format;
1608 break;
1609 default:
1610 goto err_format;
1611 }
1612
1613 return err;
1614
1615err_format:
1616 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1617 return -EPROTO;
1618}
1619
1620static int b43_request_firmware(struct b43_wldev *dev)
1621{
1622 struct b43_firmware *fw = &dev->fw;
1623 const u8 rev = dev->dev->id.revision;
1624 const char *filename;
1625 u32 tmshigh;
1626 int err;
1627
1628 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1629 if (!fw->ucode) {
1630 if ((rev >= 5) && (rev <= 10))
1631 filename = "ucode5";
1632 else if ((rev >= 11) && (rev <= 12))
1633 filename = "ucode11";
1634 else if (rev >= 13)
1635 filename = "ucode13";
1636 else
1637 goto err_no_ucode;
1638 err = do_request_fw(dev, filename, &fw->ucode);
1639 if (err)
1640 goto err_load;
1641 }
1642 if (!fw->pcm) {
1643 if ((rev >= 5) && (rev <= 10))
1644 filename = "pcm5";
1645 else if (rev >= 11)
1646 filename = NULL;
1647 else
1648 goto err_no_pcm;
1649 err = do_request_fw(dev, filename, &fw->pcm);
1650 if (err)
1651 goto err_load;
1652 }
1653 if (!fw->initvals) {
1654 switch (dev->phy.type) {
1655 case B43_PHYTYPE_A:
1656 if ((rev >= 5) && (rev <= 10)) {
1657 if (tmshigh & B43_TMSHIGH_GPHY)
1658 filename = "a0g1initvals5";
1659 else
1660 filename = "a0g0initvals5";
1661 } else
1662 goto err_no_initvals;
1663 break;
1664 case B43_PHYTYPE_G:
1665 if ((rev >= 5) && (rev <= 10))
1666 filename = "b0g0initvals5";
1667 else if (rev >= 13)
1668 filename = "lp0initvals13";
1669 else
1670 goto err_no_initvals;
1671 break;
1672 default:
1673 goto err_no_initvals;
1674 }
1675 err = do_request_fw(dev, filename, &fw->initvals);
1676 if (err)
1677 goto err_load;
1678 }
1679 if (!fw->initvals_band) {
1680 switch (dev->phy.type) {
1681 case B43_PHYTYPE_A:
1682 if ((rev >= 5) && (rev <= 10)) {
1683 if (tmshigh & B43_TMSHIGH_GPHY)
1684 filename = "a0g1bsinitvals5";
1685 else
1686 filename = "a0g0bsinitvals5";
1687 } else if (rev >= 11)
1688 filename = NULL;
1689 else
1690 goto err_no_initvals;
1691 break;
1692 case B43_PHYTYPE_G:
1693 if ((rev >= 5) && (rev <= 10))
1694 filename = "b0g0bsinitvals5";
1695 else if (rev >= 11)
1696 filename = NULL;
1697 else
1698 goto err_no_initvals;
1699 break;
1700 default:
1701 goto err_no_initvals;
1702 }
1703 err = do_request_fw(dev, filename, &fw->initvals_band);
1704 if (err)
1705 goto err_load;
1706 }
1707
1708 return 0;
1709
1710err_load:
1711 b43_print_fw_helptext(dev->wl);
1712 goto error;
1713
1714err_no_ucode:
1715 err = -ENODEV;
1716 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1717 goto error;
1718
1719err_no_pcm:
1720 err = -ENODEV;
1721 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1722 goto error;
1723
1724err_no_initvals:
1725 err = -ENODEV;
1726 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1727 "core rev %u\n", dev->phy.type, rev);
1728 goto error;
1729
1730error:
1731 b43_release_firmware(dev);
1732 return err;
1733}
1734
1735static int b43_upload_microcode(struct b43_wldev *dev)
1736{
1737 const size_t hdr_len = sizeof(struct b43_fw_header);
1738 const __be32 *data;
1739 unsigned int i, len;
1740 u16 fwrev, fwpatch, fwdate, fwtime;
1741 u32 tmp;
1742 int err = 0;
1743
1744 /* Upload Microcode. */
1745 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1746 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1747 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1748 for (i = 0; i < len; i++) {
1749 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1750 udelay(10);
1751 }
1752
1753 if (dev->fw.pcm) {
1754 /* Upload PCM data. */
1755 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1756 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1757 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1758 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1759 /* No need for autoinc bit in SHM_HW */
1760 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1761 for (i = 0; i < len; i++) {
1762 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1763 udelay(10);
1764 }
1765 }
1766
1767 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1768 b43_write32(dev, B43_MMIO_MACCTL,
1769 B43_MACCTL_PSM_RUN |
1770 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1771
1772 /* Wait for the microcode to load and respond */
1773 i = 0;
1774 while (1) {
1775 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1776 if (tmp == B43_IRQ_MAC_SUSPENDED)
1777 break;
1778 i++;
1779 if (i >= 50) {
1780 b43err(dev->wl, "Microcode not responding\n");
1781 b43_print_fw_helptext(dev->wl);
1782 err = -ENODEV;
1783 goto out;
1784 }
1785 udelay(10);
1786 }
1787 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1788
1789 /* Get and check the revisions. */
1790 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1791 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1792 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1793 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1794
1795 if (fwrev <= 0x128) {
1796 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1797 "binary drivers older than version 4.x is unsupported. "
1798 "You must upgrade your firmware files.\n");
1799 b43_print_fw_helptext(dev->wl);
1800 b43_write32(dev, B43_MMIO_MACCTL, 0);
1801 err = -EOPNOTSUPP;
1802 goto out;
1803 }
1804 b43dbg(dev->wl, "Loading firmware version %u.%u "
1805 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1806 fwrev, fwpatch,
1807 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1808 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1809
1810 dev->fw.rev = fwrev;
1811 dev->fw.patch = fwpatch;
1812
1813 out:
1814 return err;
1815}
1816
1817static int b43_write_initvals(struct b43_wldev *dev,
1818 const struct b43_iv *ivals,
1819 size_t count,
1820 size_t array_size)
1821{
1822 const struct b43_iv *iv;
1823 u16 offset;
1824 size_t i;
1825 bool bit32;
1826
1827 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1828 iv = ivals;
1829 for (i = 0; i < count; i++) {
1830 if (array_size < sizeof(iv->offset_size))
1831 goto err_format;
1832 array_size -= sizeof(iv->offset_size);
1833 offset = be16_to_cpu(iv->offset_size);
1834 bit32 = !!(offset & B43_IV_32BIT);
1835 offset &= B43_IV_OFFSET_MASK;
1836 if (offset >= 0x1000)
1837 goto err_format;
1838 if (bit32) {
1839 u32 value;
1840
1841 if (array_size < sizeof(iv->data.d32))
1842 goto err_format;
1843 array_size -= sizeof(iv->data.d32);
1844
1845 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1846 b43_write32(dev, offset, value);
1847
1848 iv = (const struct b43_iv *)((const uint8_t *)iv +
1849 sizeof(__be16) +
1850 sizeof(__be32));
1851 } else {
1852 u16 value;
1853
1854 if (array_size < sizeof(iv->data.d16))
1855 goto err_format;
1856 array_size -= sizeof(iv->data.d16);
1857
1858 value = be16_to_cpu(iv->data.d16);
1859 b43_write16(dev, offset, value);
1860
1861 iv = (const struct b43_iv *)((const uint8_t *)iv +
1862 sizeof(__be16) +
1863 sizeof(__be16));
1864 }
1865 }
1866 if (array_size)
1867 goto err_format;
1868
1869 return 0;
1870
1871err_format:
1872 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1873 b43_print_fw_helptext(dev->wl);
1874
1875 return -EPROTO;
1876}
1877
1878static int b43_upload_initvals(struct b43_wldev *dev)
1879{
1880 const size_t hdr_len = sizeof(struct b43_fw_header);
1881 const struct b43_fw_header *hdr;
1882 struct b43_firmware *fw = &dev->fw;
1883 const struct b43_iv *ivals;
1884 size_t count;
1885 int err;
1886
1887 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1888 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1889 count = be32_to_cpu(hdr->size);
1890 err = b43_write_initvals(dev, ivals, count,
1891 fw->initvals->size - hdr_len);
1892 if (err)
1893 goto out;
1894 if (fw->initvals_band) {
1895 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1896 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1897 count = be32_to_cpu(hdr->size);
1898 err = b43_write_initvals(dev, ivals, count,
1899 fw->initvals_band->size - hdr_len);
1900 if (err)
1901 goto out;
1902 }
1903out:
1904
1905 return err;
1906}
1907
1908/* Initialize the GPIOs
1909 * http://bcm-specs.sipsolutions.net/GPIO
1910 */
1911static int b43_gpio_init(struct b43_wldev *dev)
1912{
1913 struct ssb_bus *bus = dev->dev->bus;
1914 struct ssb_device *gpiodev, *pcidev = NULL;
1915 u32 mask, set;
1916
1917 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1918 & ~B43_MACCTL_GPOUTSMSK);
1919
e4d6b795
MB		 1920 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1921 | 0x000F);
1922
1923 mask = 0x0000001F;
1924 set = 0x0000000F;
1925 if (dev->dev->bus->chip_id == 0x4301) {
1926 mask |= 0x0060;
1927 set |= 0x0060;
1928 }
1929 if (0 /* FIXME: conditional unknown */ ) {
1930 b43_write16(dev, B43_MMIO_GPIO_MASK,
1931 b43_read16(dev, B43_MMIO_GPIO_MASK)
1932 | 0x0100);
1933 mask |= 0x0180;
1934 set |= 0x0180;
1935 }
1936 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1937 b43_write16(dev, B43_MMIO_GPIO_MASK,
1938 b43_read16(dev, B43_MMIO_GPIO_MASK)
1939 | 0x0200);
1940 mask |= 0x0200;
1941 set |= 0x0200;
1942 }
1943 if (dev->dev->id.revision >= 2)
1944 mask |= 0x0010; /* FIXME: This is redundant. */
1945
1946#ifdef CONFIG_SSB_DRIVER_PCICORE
1947 pcidev = bus->pcicore.dev;
1948#endif
1949 gpiodev = bus->chipco.dev ? : pcidev;
1950 if (!gpiodev)
1951 return 0;
1952 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1953 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1954 & mask) | set);
1955
1956 return 0;
1957}
1958
1959/* Turn off all GPIO stuff. Call this on module unload, for example. */
1960static void b43_gpio_cleanup(struct b43_wldev *dev)
1961{
1962 struct ssb_bus *bus = dev->dev->bus;
1963 struct ssb_device *gpiodev, *pcidev = NULL;
1964
1965#ifdef CONFIG_SSB_DRIVER_PCICORE
1966 pcidev = bus->pcicore.dev;
1967#endif
1968 gpiodev = bus->chipco.dev ? : pcidev;
1969 if (!gpiodev)
1970 return;
1971 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1972}
1973
1974/* http://bcm-specs.sipsolutions.net/EnableMac */
1975void b43_mac_enable(struct b43_wldev *dev)
1976{
1977 dev->mac_suspended--;
1978 B43_WARN_ON(dev->mac_suspended < 0);
1979 if (dev->mac_suspended == 0) {
1980 b43_write32(dev, B43_MMIO_MACCTL,
1981 b43_read32(dev, B43_MMIO_MACCTL)
1982 | B43_MACCTL_ENABLED);
1983 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1984 B43_IRQ_MAC_SUSPENDED);
1985 /* Commit writes */
1986 b43_read32(dev, B43_MMIO_MACCTL);
1987 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1988 b43_power_saving_ctl_bits(dev, 0);
1989 }
1990}
1991
1992/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1993void b43_mac_suspend(struct b43_wldev *dev)
1994{
1995 int i;
1996 u32 tmp;
1997
1998 B43_WARN_ON(dev->mac_suspended < 0);
1999 if (dev->mac_suspended == 0) {
2000 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2001 b43_write32(dev, B43_MMIO_MACCTL,
2002 b43_read32(dev, B43_MMIO_MACCTL)
2003 & ~B43_MACCTL_ENABLED);
2004 /* force pci to flush the write */
2005 b43_read32(dev, B43_MMIO_MACCTL);
2006 for (i = 10000; i; i--) {
2007 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2008 if (tmp & B43_IRQ_MAC_SUSPENDED)
2009 goto out;
2010 udelay(1);
2011 }
2012 b43err(dev->wl, "MAC suspend failed\n");
2013 }
2014 out:
2015 dev->mac_suspended++;
2016}
2017
2018static void b43_adjust_opmode(struct b43_wldev *dev)
2019{
2020 struct b43_wl *wl = dev->wl;
2021 u32 ctl;
2022 u16 cfp_pretbtt;
2023
2024 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2025 /* Reset status to STA infrastructure mode. */
2026 ctl &= ~B43_MACCTL_AP;
2027 ctl &= ~B43_MACCTL_KEEP_CTL;
2028 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2029 ctl &= ~B43_MACCTL_KEEP_BAD;
2030 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2031 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2032 ctl |= B43_MACCTL_INFRA;
2033
4150c572
JB		 2034 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2035 ctl |= B43_MACCTL_AP;
2036 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2037 ctl &= ~B43_MACCTL_INFRA;
2038
2039 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2040 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2041 if (wl->filter_flags & FIF_FCSFAIL)
2042 ctl |= B43_MACCTL_KEEP_BAD;
2043 if (wl->filter_flags & FIF_PLCPFAIL)
2044 ctl |= B43_MACCTL_KEEP_BADPLCP;
2045 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2046 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2047 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2048 ctl |= B43_MACCTL_BEACPROMISC;
2049
e4d6b795
MB		 2050 /* Workaround: On old hardware the HW-MAC-address-filter
2051 * doesn't work properly, so always run promisc in filter
2052 * it in software. */
2053 if (dev->dev->id.revision <= 4)
2054 ctl |= B43_MACCTL_PROMISC;
2055
2056 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2057
2058 cfp_pretbtt = 2;
2059 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2060 if (dev->dev->bus->chip_id == 0x4306 &&
2061 dev->dev->bus->chip_rev == 3)
2062 cfp_pretbtt = 100;
2063 else
2064 cfp_pretbtt = 50;
2065 }
2066 b43_write16(dev, 0x612, cfp_pretbtt);
2067}
2068
2069static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2070{
2071 u16 offset;
2072
2073 if (is_ofdm) {
2074 offset = 0x480;
2075 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2076 } else {
2077 offset = 0x4C0;
2078 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2079 }
2080 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2081 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2082}
2083
2084static void b43_rate_memory_init(struct b43_wldev *dev)
2085{
2086 switch (dev->phy.type) {
2087 case B43_PHYTYPE_A:
2088 case B43_PHYTYPE_G:
2089 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2090 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2091 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2092 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2093 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2094 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2095 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2096 if (dev->phy.type == B43_PHYTYPE_A)
2097 break;
2098 /* fallthrough */
2099 case B43_PHYTYPE_B:
2100 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2101 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2102 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2103 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2104 break;
2105 default:
2106 B43_WARN_ON(1);
2107 }
2108}
2109
2110/* Set the TX-Antenna for management frames sent by firmware. */
2111static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2112{
2113 u16 ant = 0;
2114 u16 tmp;
2115
2116 switch (antenna) {
2117 case B43_ANTENNA0:
2118 ant |= B43_TX4_PHY_ANT0;
2119 break;
2120 case B43_ANTENNA1:
2121 ant |= B43_TX4_PHY_ANT1;
2122 break;
2123 case B43_ANTENNA_AUTO:
2124 ant |= B43_TX4_PHY_ANTLAST;
2125 break;
2126 default:
2127 B43_WARN_ON(1);
2128 }
2129
2130 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2131
2132 /* For Beacons */
2133 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2134 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2135 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2136 /* For ACK/CTS */
2137 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2138 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2139 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2140 /* For Probe Resposes */
2141 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2142 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2143 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2144}
2145
05155c83
MB		 2146/* Returns TRUE, if the radio is enabled in hardware. */
2147static bool b43_is_hw_radio_enabled(struct b43_wldev *dev)
2148{
2149 if (dev->phy.rev >= 3) {
2150 if (!(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)
2151 & B43_MMIO_RADIO_HWENABLED_HI_MASK))
2152 return 1;
2153 } else {
2154 if (b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
2155 & B43_MMIO_RADIO_HWENABLED_LO_MASK)
2156 return 1;
2157 }
2158 return 0;
2159}
2160
e4d6b795
MB		 2161/* This is the opposite of b43_chip_init() */
2162static void b43_chip_exit(struct b43_wldev *dev)
2163{
8e9f7529 2164 b43_radio_turn_off(dev, 1);
21954c36 2165 b43_leds_exit(dev);
e4d6b795
MB		 2166 b43_gpio_cleanup(dev);
2167 /* firmware is released later */
2168}
2169
2170/* Initialize the chip
2171 * http://bcm-specs.sipsolutions.net/ChipInit
2172 */
2173static int b43_chip_init(struct b43_wldev *dev)
2174{
2175 struct b43_phy *phy = &dev->phy;
2176 int err, tmp;
2177 u32 value32;
2178 u16 value16;
2179
2180 b43_write32(dev, B43_MMIO_MACCTL,
2181 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2182
2183 err = b43_request_firmware(dev);
2184 if (err)
2185 goto out;
2186 err = b43_upload_microcode(dev);
2187 if (err)
2188 goto out; /* firmware is released later */
2189
2190 err = b43_gpio_init(dev);
2191 if (err)
2192 goto out; /* firmware is released later */
21954c36
MB		 2193 b43_leds_init(dev);
2194
e4d6b795
MB		 2195 err = b43_upload_initvals(dev);
2196 if (err)
21954c36 2197 goto err_leds_exit;
e4d6b795 2198 b43_radio_turn_on(dev);
e4d6b795
MB		 2199
2200 b43_write16(dev, 0x03E6, 0x0000);
2201 err = b43_phy_init(dev);
2202 if (err)
2203 goto err_radio_off;
2204
2205 /* Select initial Interference Mitigation. */
2206 tmp = phy->interfmode;
2207 phy->interfmode = B43_INTERFMODE_NONE;
2208 b43_radio_set_interference_mitigation(dev, tmp);
2209
2210 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2211 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2212
2213 if (phy->type == B43_PHYTYPE_B) {
2214 value16 = b43_read16(dev, 0x005E);
2215 value16 |= 0x0004;
2216 b43_write16(dev, 0x005E, value16);
2217 }
2218 b43_write32(dev, 0x0100, 0x01000000);
2219 if (dev->dev->id.revision < 5)
2220 b43_write32(dev, 0x010C, 0x01000000);
2221
2222 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2223 & ~B43_MACCTL_INFRA);
2224 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2225 | B43_MACCTL_INFRA);
e4d6b795
MB		 2226
2227 if (b43_using_pio(dev)) {
2228 b43_write32(dev, 0x0210, 0x00000100);
2229 b43_write32(dev, 0x0230, 0x00000100);
2230 b43_write32(dev, 0x0250, 0x00000100);
2231 b43_write32(dev, 0x0270, 0x00000100);
2232 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2233 }
2234
2235 /* Probe Response Timeout value */
2236 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2237 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2238
2239 /* Initially set the wireless operation mode. */
2240 b43_adjust_opmode(dev);
2241
2242 if (dev->dev->id.revision < 3) {
2243 b43_write16(dev, 0x060E, 0x0000);
2244 b43_write16(dev, 0x0610, 0x8000);
2245 b43_write16(dev, 0x0604, 0x0000);
2246 b43_write16(dev, 0x0606, 0x0200);
2247 } else {
2248 b43_write32(dev, 0x0188, 0x80000000);
2249 b43_write32(dev, 0x018C, 0x02000000);
2250 }
2251 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2252 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2253 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2254 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2255 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2256 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2257 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2258
2259 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2260 value32 |= 0x00100000;
2261 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2262
2263 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2264 dev->dev->bus->chipco.fast_pwrup_delay);
2265
2266 err = 0;
2267 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2268out:
e4d6b795
MB		 2269 return err;
2270
21954c36 2271err_radio_off:
8e9f7529 2272 b43_radio_turn_off(dev, 1);
21954c36
MB		 2273err_leds_exit:
2274 b43_leds_exit(dev);
e4d6b795 2275 b43_gpio_cleanup(dev);
21954c36 2276 return err;
e4d6b795
MB		 2277}
2278
2279static void b43_periodic_every120sec(struct b43_wldev *dev)
2280{
2281 struct b43_phy *phy = &dev->phy;
2282
2283 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2284 return;
2285
2286 b43_mac_suspend(dev);
2287 b43_lo_g_measure(dev);
2288 b43_mac_enable(dev);
2289 if (b43_has_hardware_pctl(phy))
2290 b43_lo_g_ctl_mark_all_unused(dev);
2291}
2292
2293static void b43_periodic_every60sec(struct b43_wldev *dev)
2294{
2295 struct b43_phy *phy = &dev->phy;
2296
2297 if (!b43_has_hardware_pctl(phy))
2298 b43_lo_g_ctl_mark_all_unused(dev);
2299 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2300 b43_mac_suspend(dev);
2301 b43_calc_nrssi_slope(dev);
2302 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2303 u8 old_chan = phy->channel;
2304
2305 /* VCO Calibration */
2306 if (old_chan >= 8)
2307 b43_radio_selectchannel(dev, 1, 0);
2308 else
2309 b43_radio_selectchannel(dev, 13, 0);
2310 b43_radio_selectchannel(dev, old_chan, 0);
2311 }
2312 b43_mac_enable(dev);
2313 }
2314}
2315
2316static void b43_periodic_every30sec(struct b43_wldev *dev)
2317{
2318 /* Update device statistics. */
2319 b43_calculate_link_quality(dev);
2320}
2321
2322static void b43_periodic_every15sec(struct b43_wldev *dev)
2323{
2324 struct b43_phy *phy = &dev->phy;
2325
2326 if (phy->type == B43_PHYTYPE_G) {
2327 //TODO: update_aci_moving_average
2328 if (phy->aci_enable && phy->aci_wlan_automatic) {
2329 b43_mac_suspend(dev);
2330 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2331 if (0 /*TODO: bunch of conditions */ ) {
2332 b43_radio_set_interference_mitigation
2333 (dev, B43_INTERFMODE_MANUALWLAN);
2334 }
2335 } else if (1 /*TODO*/) {
2336 /*
2337 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2338 b43_radio_set_interference_mitigation(dev,
2339 B43_INTERFMODE_NONE);
2340 }
2341 */
2342 }
2343 b43_mac_enable(dev);
2344 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2345 phy->rev == 1) {
2346 //TODO: implement rev1 workaround
2347 }
2348 }
2349 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2350 //TODO for APHY (temperature?)
2351}
2352
2353static void b43_periodic_every1sec(struct b43_wldev *dev)
2354{
05155c83 2355 bool radio_hw_enable;
e4d6b795
MB		 2356
2357 /* check if radio hardware enabled status changed */
2358 radio_hw_enable = b43_is_hw_radio_enabled(dev);
2359 if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
2360 dev->radio_hw_enable = radio_hw_enable;
8e9f7529 2361 b43_rfkill_toggled(dev, radio_hw_enable);
e4d6b795
MB		 2362 }
2363}
2364
2365static void do_periodic_work(struct b43_wldev *dev)
2366{
2367 unsigned int state;
2368
2369 state = dev->periodic_state;
2370 if (state % 120 == 0)
2371 b43_periodic_every120sec(dev);
2372 if (state % 60 == 0)
2373 b43_periodic_every60sec(dev);
2374 if (state % 30 == 0)
2375 b43_periodic_every30sec(dev);
2376 if (state % 15 == 0)
2377 b43_periodic_every15sec(dev);
2378 b43_periodic_every1sec(dev);
2379}
2380
2381/* Estimate a "Badness" value based on the periodic work
2382 * state-machine state. "Badness" is worse (bigger), if the
2383 * periodic work will take longer.
2384 */
2385static int estimate_periodic_work_badness(unsigned int state)
2386{
2387 int badness = 0;
2388
2389 if (state % 120 == 0) /* every 120 sec */
2390 badness += 10;
2391 if (state % 60 == 0) /* every 60 sec */
2392 badness += 5;
2393 if (state % 30 == 0) /* every 30 sec */
2394 badness += 1;
2395 if (state % 15 == 0) /* every 15 sec */
2396 badness += 1;
2397
2398#define BADNESS_LIMIT 4
2399 return badness;
2400}
2401
2402static void b43_periodic_work_handler(struct work_struct *work)
2403{
2404 struct b43_wldev *dev =
2405 container_of(work, struct b43_wldev, periodic_work.work);
2406 unsigned long flags, delay;
2407 u32 savedirqs = 0;
2408 int badness;
2409
2410 mutex_lock(&dev->wl->mutex);
2411
2412 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2413 goto out;
2414 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2415 goto out_requeue;
2416
2417 badness = estimate_periodic_work_badness(dev->periodic_state);
2418 if (badness > BADNESS_LIMIT) {
2419 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2420 /* Suspend TX as we don't want to transmit packets while
2421 * we recalibrate the hardware. */
2422 b43_tx_suspend(dev);
2423 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2424 /* Periodic work will take a long time, so we want it to
2425 * be preemtible and release the spinlock. */
2426 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2427 b43_synchronize_irq(dev);
2428
2429 do_periodic_work(dev);
2430
2431 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2432 b43_interrupt_enable(dev, savedirqs);
2433 b43_tx_resume(dev);
2434 mmiowb();
2435 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2436 } else {
2437 /* Take the global driver lock. This will lock any operation. */
2438 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2439
2440 do_periodic_work(dev);
2441
2442 mmiowb();
2443 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2444 }
2445 dev->periodic_state++;
2446 out_requeue:
2447 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2448 delay = msecs_to_jiffies(50);
2449 else
2450 delay = round_jiffies(HZ);
2451 queue_delayed_work(dev->wl->hw->workqueue, &dev->periodic_work, delay);
2452 out:
2453 mutex_unlock(&dev->wl->mutex);
2454}
2455
2456static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2457{
2458 struct delayed_work *work = &dev->periodic_work;
2459
2460 dev->periodic_state = 0;
2461 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2462 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2463}
2464
2465/* Validate access to the chip (SHM) */
2466static int b43_validate_chipaccess(struct b43_wldev *dev)
2467{
2468 u32 value;
2469 u32 shm_backup;
2470
2471 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2472 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2473 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2474 goto error;
2475 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2476 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2477 goto error;
2478 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2479
2480 value = b43_read32(dev, B43_MMIO_MACCTL);
2481 if ((value | B43_MACCTL_GMODE) !=
2482 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2483 goto error;
2484
2485 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2486 if (value)
2487 goto error;
2488
2489 return 0;
2490 error:
2491 b43err(dev->wl, "Failed to validate the chipaccess\n");
2492 return -ENODEV;
2493}
2494
2495static void b43_security_init(struct b43_wldev *dev)
2496{
2497 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2498 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2499 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2500 /* KTP is a word address, but we address SHM bytewise.
2501 * So multiply by two.
2502 */
2503 dev->ktp *= 2;
2504 if (dev->dev->id.revision >= 5) {
2505 /* Number of RCMTA address slots */
2506 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2507 }
2508 b43_clear_keys(dev);
2509}
2510
2511static int b43_rng_read(struct hwrng *rng, u32 * data)
2512{
2513 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2514 unsigned long flags;
2515
2516 /* Don't take wl->mutex here, as it could deadlock with
2517 * hwrng internal locking. It's not needed to take
2518 * wl->mutex here, anyway. */
2519
2520 spin_lock_irqsave(&wl->irq_lock, flags);
2521 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2522 spin_unlock_irqrestore(&wl->irq_lock, flags);
2523
2524 return (sizeof(u16));
2525}
2526
2527static void b43_rng_exit(struct b43_wl *wl)
2528{
2529 if (wl->rng_initialized)
2530 hwrng_unregister(&wl->rng);
2531}
2532
2533static int b43_rng_init(struct b43_wl *wl)
2534{
2535 int err;
2536
2537 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2538 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2539 wl->rng.name = wl->rng_name;
2540 wl->rng.data_read = b43_rng_read;
2541 wl->rng.priv = (unsigned long)wl;
2542 wl->rng_initialized = 1;
2543 err = hwrng_register(&wl->rng);
2544 if (err) {
2545 wl->rng_initialized = 0;
2546 b43err(wl, "Failed to register the random "
2547 "number generator (%d)\n", err);
2548 }
2549
2550 return err;
2551}
2552
2553static int b43_tx(struct ieee80211_hw *hw,
2554 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2555{
2556 struct b43_wl *wl = hw_to_b43_wl(hw);
2557 struct b43_wldev *dev = wl->current_dev;
2558 int err = -ENODEV;
2559 unsigned long flags;
2560
2561 if (unlikely(!dev))
2562 goto out;
2563 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2564 goto out;
2565 /* DMA-TX is done without a global lock. */
2566 if (b43_using_pio(dev)) {
2567 spin_lock_irqsave(&wl->irq_lock, flags);
2568 err = b43_pio_tx(dev, skb, ctl);
2569 spin_unlock_irqrestore(&wl->irq_lock, flags);
2570 } else
2571 err = b43_dma_tx(dev, skb, ctl);
2572 out:
2573 if (unlikely(err))
2574 return NETDEV_TX_BUSY;
2575 return NETDEV_TX_OK;
2576}
2577
2578static int b43_conf_tx(struct ieee80211_hw *hw,
2579 int queue,
2580 const struct ieee80211_tx_queue_params *params)
2581{
2582 return 0;
2583}
2584
2585static int b43_get_tx_stats(struct ieee80211_hw *hw,
2586 struct ieee80211_tx_queue_stats *stats)
2587{
2588 struct b43_wl *wl = hw_to_b43_wl(hw);
2589 struct b43_wldev *dev = wl->current_dev;
2590 unsigned long flags;
2591 int err = -ENODEV;
2592
2593 if (!dev)
2594 goto out;
2595 spin_lock_irqsave(&wl->irq_lock, flags);
2596 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2597 if (b43_using_pio(dev))
2598 b43_pio_get_tx_stats(dev, stats);
2599 else
2600 b43_dma_get_tx_stats(dev, stats);
2601 err = 0;
2602 }
2603 spin_unlock_irqrestore(&wl->irq_lock, flags);
2604 out:
2605 return err;
2606}
2607
2608static int b43_get_stats(struct ieee80211_hw *hw,
2609 struct ieee80211_low_level_stats *stats)
2610{
2611 struct b43_wl *wl = hw_to_b43_wl(hw);
2612 unsigned long flags;
2613
2614 spin_lock_irqsave(&wl->irq_lock, flags);
2615 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2616 spin_unlock_irqrestore(&wl->irq_lock, flags);
2617
2618 return 0;
2619}
2620
2621static const char *phymode_to_string(unsigned int phymode)
2622{
2623 switch (phymode) {
2624 case B43_PHYMODE_A:
2625 return "A";
2626 case B43_PHYMODE_B:
2627 return "B";
2628 case B43_PHYMODE_G:
2629 return "G";
2630 default:
2631 B43_WARN_ON(1);
2632 }
2633 return "";
2634}
2635
2636static int find_wldev_for_phymode(struct b43_wl *wl,
2637 unsigned int phymode,
2638 struct b43_wldev **dev, bool * gmode)
2639{
2640 struct b43_wldev *d;
2641
2642 list_for_each_entry(d, &wl->devlist, list) {
2643 if (d->phy.possible_phymodes & phymode) {
2644 /* Ok, this device supports the PHY-mode.
2645 * Now figure out how the gmode bit has to be
2646 * set to support it. */
2647 if (phymode == B43_PHYMODE_A)
2648 *gmode = 0;
2649 else
2650 *gmode = 1;
2651 *dev = d;
2652
2653 return 0;
2654 }
2655 }
2656
2657 return -ESRCH;
2658}
2659
2660static void b43_put_phy_into_reset(struct b43_wldev *dev)
2661{
2662 struct ssb_device *sdev = dev->dev;
2663 u32 tmslow;
2664
2665 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2666 tmslow &= ~B43_TMSLOW_GMODE;
2667 tmslow |= B43_TMSLOW_PHYRESET;
2668 tmslow |= SSB_TMSLOW_FGC;
2669 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2670 msleep(1);
2671
2672 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2673 tmslow &= ~SSB_TMSLOW_FGC;
2674 tmslow |= B43_TMSLOW_PHYRESET;
2675 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2676 msleep(1);
2677}
2678
2679/* Expects wl->mutex locked */
2680static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2681{
2682 struct b43_wldev *up_dev;
2683 struct b43_wldev *down_dev;
2684 int err;
2685 bool gmode = 0;
2686 int prev_status;
2687
2688 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2689 if (err) {
2690 b43err(wl, "Could not find a device for %s-PHY mode\n",
2691 phymode_to_string(new_mode));
2692 return err;
2693 }
2694 if ((up_dev == wl->current_dev) &&
2695 (!!wl->current_dev->phy.gmode == !!gmode)) {
2696 /* This device is already running. */
2697 return 0;
2698 }
2699 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2700 phymode_to_string(new_mode));
2701 down_dev = wl->current_dev;
2702
2703 prev_status = b43_status(down_dev);
2704 /* Shutdown the currently running core. */
2705 if (prev_status >= B43_STAT_STARTED)
2706 b43_wireless_core_stop(down_dev);
2707 if (prev_status >= B43_STAT_INITIALIZED)
2708 b43_wireless_core_exit(down_dev);
2709
2710 if (down_dev != up_dev) {
2711 /* We switch to a different core, so we put PHY into
2712 * RESET on the old core. */
2713 b43_put_phy_into_reset(down_dev);
2714 }
2715
2716 /* Now start the new core. */
2717 up_dev->phy.gmode = gmode;
2718 if (prev_status >= B43_STAT_INITIALIZED) {
2719 err = b43_wireless_core_init(up_dev);
2720 if (err) {
2721 b43err(wl, "Fatal: Could not initialize device for "
2722 "newly selected %s-PHY mode\n",
2723 phymode_to_string(new_mode));
2724 goto init_failure;
2725 }
2726 }
2727 if (prev_status >= B43_STAT_STARTED) {
2728 err = b43_wireless_core_start(up_dev);
2729 if (err) {
2730 b43err(wl, "Fatal: Coult not start device for "
2731 "newly selected %s-PHY mode\n",
2732 phymode_to_string(new_mode));
2733 b43_wireless_core_exit(up_dev);
2734 goto init_failure;
2735 }
2736 }
2737 B43_WARN_ON(b43_status(up_dev) != prev_status);
2738
2739 wl->current_dev = up_dev;
2740
2741 return 0;
2742 init_failure:
2743 /* Whoops, failed to init the new core. No core is operating now. */
2744 wl->current_dev = NULL;
2745 return err;
2746}
2747
2748static int b43_antenna_from_ieee80211(u8 antenna)
2749{
2750 switch (antenna) {
2751 case 0: /* default/diversity */
2752 return B43_ANTENNA_DEFAULT;
2753 case 1: /* Antenna 0 */
2754 return B43_ANTENNA0;
2755 case 2: /* Antenna 1 */
2756 return B43_ANTENNA1;
2757 default:
2758 return B43_ANTENNA_DEFAULT;
2759 }
2760}
2761
2762static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2763{
2764 struct b43_wl *wl = hw_to_b43_wl(hw);
2765 struct b43_wldev *dev;
2766 struct b43_phy *phy;
2767 unsigned long flags;
2768 unsigned int new_phymode = 0xFFFF;
2769 int antenna_tx;
2770 int antenna_rx;
2771 int err = 0;
2772 u32 savedirqs;
2773
2774 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2775 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2776
2777 mutex_lock(&wl->mutex);
2778
2779 /* Switch the PHY mode (if necessary). */
2780 switch (conf->phymode) {
2781 case MODE_IEEE80211A:
2782 new_phymode = B43_PHYMODE_A;
2783 break;
2784 case MODE_IEEE80211B:
2785 new_phymode = B43_PHYMODE_B;
2786 break;
2787 case MODE_IEEE80211G:
2788 new_phymode = B43_PHYMODE_G;
2789 break;
2790 default:
2791 B43_WARN_ON(1);
2792 }
2793 err = b43_switch_phymode(wl, new_phymode);
2794 if (err)
2795 goto out_unlock_mutex;
2796 dev = wl->current_dev;
2797 phy = &dev->phy;
2798
2799 /* Disable IRQs while reconfiguring the device.
2800 * This makes it possible to drop the spinlock throughout
2801 * the reconfiguration process. */
2802 spin_lock_irqsave(&wl->irq_lock, flags);
2803 if (b43_status(dev) < B43_STAT_STARTED) {
2804 spin_unlock_irqrestore(&wl->irq_lock, flags);
2805 goto out_unlock_mutex;
2806 }
2807 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2808 spin_unlock_irqrestore(&wl->irq_lock, flags);
2809 b43_synchronize_irq(dev);
2810
2811 /* Switch to the requested channel.
2812 * The firmware takes care of races with the TX handler. */
2813 if (conf->channel_val != phy->channel)
2814 b43_radio_selectchannel(dev, conf->channel_val, 0);
2815
2816 /* Enable/Disable ShortSlot timing. */
2817 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2818 dev->short_slot) {
2819 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2820 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2821 b43_short_slot_timing_enable(dev);
2822 else
2823 b43_short_slot_timing_disable(dev);
2824 }
2825
2826 /* Adjust the desired TX power level. */
2827 if (conf->power_level != 0) {
2828 if (conf->power_level != phy->power_level) {
2829 phy->power_level = conf->power_level;
2830 b43_phy_xmitpower(dev);
2831 }
2832 }
2833
2834 /* Antennas for RX and management frame TX. */
2835 b43_mgmtframe_txantenna(dev, antenna_tx);
2836 b43_set_rx_antenna(dev, antenna_rx);
2837
2838 /* Update templates for AP mode. */
2839 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2840 b43_set_beacon_int(dev, conf->beacon_int);
2841
fda9abcf
MB		 2842 if (!!conf->radio_enabled != phy->radio_on) {
2843 if (conf->radio_enabled) {
2844 b43_radio_turn_on(dev);
2845 b43info(dev->wl, "Radio turned on by software\n");
2846 if (!dev->radio_hw_enable) {
2847 b43info(dev->wl, "The hardware RF-kill button "
2848 "still turns the radio physically off. "
2849 "Press the button to turn it on.\n");
2850 }
2851 } else {
8e9f7529 2852 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 2853 b43info(dev->wl, "Radio turned off by software\n");
2854 }
2855 }
2856
e4d6b795
MB		 2857 spin_lock_irqsave(&wl->irq_lock, flags);
2858 b43_interrupt_enable(dev, savedirqs);
2859 mmiowb();
2860 spin_unlock_irqrestore(&wl->irq_lock, flags);
2861 out_unlock_mutex:
2862 mutex_unlock(&wl->mutex);
2863
2864 return err;
2865}
2866
4150c572
JB		 2867static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2868 const u8 *local_addr, const u8 *addr,
2869 struct ieee80211_key_conf *key)
e4d6b795
MB		 2870{
2871 struct b43_wl *wl = hw_to_b43_wl(hw);
2872 struct b43_wldev *dev = wl->current_dev;
2873 unsigned long flags;
2874 u8 algorithm;
2875 u8 index;
2876 int err = -EINVAL;
0795af57 2877 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 2878
2879 if (modparam_nohwcrypt)
2880 return -ENOSPC; /* User disabled HW-crypto */
2881
2882 if (!dev)
2883 return -ENODEV;
2884 switch (key->alg) {
2885 case ALG_NONE:
2886 algorithm = B43_SEC_ALGO_NONE;
2887 break;
2888 case ALG_WEP:
2889 if (key->keylen == 5)
2890 algorithm = B43_SEC_ALGO_WEP40;
2891 else
2892 algorithm = B43_SEC_ALGO_WEP104;
2893 break;
2894 case ALG_TKIP:
2895 algorithm = B43_SEC_ALGO_TKIP;
2896 break;
2897 case ALG_CCMP:
2898 algorithm = B43_SEC_ALGO_AES;
2899 break;
2900 default:
2901 B43_WARN_ON(1);
2902 goto out;
2903 }
2904
2905 index = (u8) (key->keyidx);
2906 if (index > 3)
2907 goto out;
2908
2909 mutex_lock(&wl->mutex);
2910 spin_lock_irqsave(&wl->irq_lock, flags);
2911
2912 if (b43_status(dev) < B43_STAT_INITIALIZED) {
2913 err = -ENODEV;
2914 goto out_unlock;
2915 }
2916
2917 switch (cmd) {
2918 case SET_KEY:
2919 if (algorithm == B43_SEC_ALGO_TKIP) {
2920 /* FIXME: No TKIP hardware encryption for now. */
2921 err = -EOPNOTSUPP;
2922 goto out_unlock;
2923 }
2924
2925 if (is_broadcast_ether_addr(addr)) {
2926 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2927 err = b43_key_write(dev, index, algorithm,
2928 key->key, key->keylen, NULL, key);
2929 } else {
2930 /*
2931 * either pairwise key or address is 00:00:00:00:00:00
2932 * for transmit-only keys
2933 */
2934 err = b43_key_write(dev, -1, algorithm,
2935 key->key, key->keylen, addr, key);
2936 }
2937 if (err)
2938 goto out_unlock;
2939
2940 if (algorithm == B43_SEC_ALGO_WEP40 ||
2941 algorithm == B43_SEC_ALGO_WEP104) {
2942 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2943 } else {
2944 b43_hf_write(dev,
2945 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2946 }
2947 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2948 break;
2949 case DISABLE_KEY: {
2950 err = b43_key_clear(dev, key->hw_key_idx);
2951 if (err)
2952 goto out_unlock;
2953 break;
2954 }
2955 default:
2956 B43_WARN_ON(1);
2957 }
2958out_unlock:
2959 spin_unlock_irqrestore(&wl->irq_lock, flags);
2960 mutex_unlock(&wl->mutex);
2961out:
2962 if (!err) {
2963 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 2964 "mac: %s\n",
e4d6b795 2965 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 2966 print_mac(mac, addr));
e4d6b795
MB		 2967 }
2968 return err;
2969}
2970
4150c572
JB		 2971static void b43_configure_filter(struct ieee80211_hw *hw,
2972 unsigned int changed, unsigned int *fflags,
2973 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 2974{
2975 struct b43_wl *wl = hw_to_b43_wl(hw);
2976 struct b43_wldev *dev = wl->current_dev;
2977 unsigned long flags;
2978
4150c572
JB		 2979 if (!dev) {
2980 *fflags = 0;
e4d6b795 2981 return;
e4d6b795 2982 }
4150c572
JB		 2983
2984 spin_lock_irqsave(&wl->irq_lock, flags);
2985 *fflags &= FIF_PROMISC_IN_BSS |
2986 FIF_ALLMULTI |
2987 FIF_FCSFAIL |
2988 FIF_PLCPFAIL |
2989 FIF_CONTROL |
2990 FIF_OTHER_BSS |
2991 FIF_BCN_PRBRESP_PROMISC;
2992
2993 changed &= FIF_PROMISC_IN_BSS |
2994 FIF_ALLMULTI |
2995 FIF_FCSFAIL |
2996 FIF_PLCPFAIL |
2997 FIF_CONTROL |
2998 FIF_OTHER_BSS |
2999 FIF_BCN_PRBRESP_PROMISC;
3000
3001 wl->filter_flags = *fflags;
3002
3003 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3004 b43_adjust_opmode(dev);
e4d6b795
MB		 3005 spin_unlock_irqrestore(&wl->irq_lock, flags);
3006}
3007
3008static int b43_config_interface(struct ieee80211_hw *hw,
3009 int if_id, struct ieee80211_if_conf *conf)
3010{
3011 struct b43_wl *wl = hw_to_b43_wl(hw);
3012 struct b43_wldev *dev = wl->current_dev;
3013 unsigned long flags;
3014
3015 if (!dev)
3016 return -ENODEV;
3017 mutex_lock(&wl->mutex);
3018 spin_lock_irqsave(&wl->irq_lock, flags);
4150c572
JB		 3019 B43_WARN_ON(wl->if_id != if_id);
3020 if (conf->bssid)
3021 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3022 else
3023 memset(wl->bssid, 0, ETH_ALEN);
3024 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3025 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3026 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3027 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3028 if (conf->beacon)
3029 b43_refresh_templates(dev, conf->beacon);
e4d6b795 3030 }
4150c572 3031 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3032 }
3033 spin_unlock_irqrestore(&wl->irq_lock, flags);
3034 mutex_unlock(&wl->mutex);
3035
3036 return 0;
3037}
3038
3039/* Locking: wl->mutex */
3040static void b43_wireless_core_stop(struct b43_wldev *dev)
3041{
3042 struct b43_wl *wl = dev->wl;
3043 unsigned long flags;
3044
3045 if (b43_status(dev) < B43_STAT_STARTED)
3046 return;
3047 b43_set_status(dev, B43_STAT_INITIALIZED);
3048
3049 mutex_unlock(&wl->mutex);
3050 /* Must unlock as it would otherwise deadlock. No races here.
3051 * Cancel the possibly running self-rearming periodic work. */
3052 cancel_delayed_work_sync(&dev->periodic_work);
3053 mutex_lock(&wl->mutex);
3054
3055 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3056
3057 /* Disable and sync interrupts. */
3058 spin_lock_irqsave(&wl->irq_lock, flags);
3059 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3060 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3061 spin_unlock_irqrestore(&wl->irq_lock, flags);
3062 b43_synchronize_irq(dev);
3063
3064 b43_mac_suspend(dev);
3065 free_irq(dev->dev->irq, dev);
3066 b43dbg(wl, "Wireless interface stopped\n");
3067}
3068
3069/* Locking: wl->mutex */
3070static int b43_wireless_core_start(struct b43_wldev *dev)
3071{
3072 int err;
3073
3074 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3075
3076 drain_txstatus_queue(dev);
3077 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3078 IRQF_SHARED, KBUILD_MODNAME, dev);
3079 if (err) {
3080 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3081 goto out;
3082 }
3083
3084 /* We are ready to run. */
3085 b43_set_status(dev, B43_STAT_STARTED);
3086
3087 /* Start data flow (TX/RX). */
3088 b43_mac_enable(dev);
3089 b43_interrupt_enable(dev, dev->irq_savedstate);
3090 ieee80211_start_queues(dev->wl->hw);
3091
3092 /* Start maintainance work */
3093 b43_periodic_tasks_setup(dev);
3094
3095 b43dbg(dev->wl, "Wireless interface started\n");
3096 out:
3097 return err;
3098}
3099
3100/* Get PHY and RADIO versioning numbers */
3101static int b43_phy_versioning(struct b43_wldev *dev)
3102{
3103 struct b43_phy *phy = &dev->phy;
3104 u32 tmp;
3105 u8 analog_type;
3106 u8 phy_type;
3107 u8 phy_rev;
3108 u16 radio_manuf;
3109 u16 radio_ver;
3110 u16 radio_rev;
3111 int unsupported = 0;
3112
3113 /* Get PHY versioning */
3114 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3115 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3116 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3117 phy_rev = (tmp & B43_PHYVER_VERSION);
3118 switch (phy_type) {
3119 case B43_PHYTYPE_A:
3120 if (phy_rev >= 4)
3121 unsupported = 1;
3122 break;
3123 case B43_PHYTYPE_B:
3124 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3125 && phy_rev != 7)
3126 unsupported = 1;
3127 break;
3128 case B43_PHYTYPE_G:
3129 if (phy_rev > 8)
3130 unsupported = 1;
3131 break;
3132 default:
3133 unsupported = 1;
3134 };
3135 if (unsupported) {
3136 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3137 "(Analog %u, Type %u, Revision %u)\n",
3138 analog_type, phy_type, phy_rev);
3139 return -EOPNOTSUPP;
3140 }
3141 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3142 analog_type, phy_type, phy_rev);
3143
3144 /* Get RADIO versioning */
3145 if (dev->dev->bus->chip_id == 0x4317) {
3146 if (dev->dev->bus->chip_rev == 0)
3147 tmp = 0x3205017F;
3148 else if (dev->dev->bus->chip_rev == 1)
3149 tmp = 0x4205017F;
3150 else
3151 tmp = 0x5205017F;
3152 } else {
3153 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3154 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3155 tmp <<= 16;
3156 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3157 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3158 }
3159 radio_manuf = (tmp & 0x00000FFF);
3160 radio_ver = (tmp & 0x0FFFF000) >> 12;
3161 radio_rev = (tmp & 0xF0000000) >> 28;
3162 switch (phy_type) {
3163 case B43_PHYTYPE_A:
3164 if (radio_ver != 0x2060)
3165 unsupported = 1;
3166 if (radio_rev != 1)
3167 unsupported = 1;
3168 if (radio_manuf != 0x17F)
3169 unsupported = 1;
3170 break;
3171 case B43_PHYTYPE_B:
3172 if ((radio_ver & 0xFFF0) != 0x2050)
3173 unsupported = 1;
3174 break;
3175 case B43_PHYTYPE_G:
3176 if (radio_ver != 0x2050)
3177 unsupported = 1;
3178 break;
3179 default:
3180 B43_WARN_ON(1);
3181 }
3182 if (unsupported) {
3183 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3184 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3185 radio_manuf, radio_ver, radio_rev);
3186 return -EOPNOTSUPP;
3187 }
3188 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3189 radio_manuf, radio_ver, radio_rev);
3190
3191 phy->radio_manuf = radio_manuf;
3192 phy->radio_ver = radio_ver;
3193 phy->radio_rev = radio_rev;
3194
3195 phy->analog = analog_type;
3196 phy->type = phy_type;
3197 phy->rev = phy_rev;
3198
3199 return 0;
3200}
3201
3202static void setup_struct_phy_for_init(struct b43_wldev *dev,
3203 struct b43_phy *phy)
3204{
3205 struct b43_txpower_lo_control *lo;
3206 int i;
3207
3208 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3209 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3210
3211 /* Flags */
3212 phy->locked = 0;
3213
3214 phy->aci_enable = 0;
3215 phy->aci_wlan_automatic = 0;
3216 phy->aci_hw_rssi = 0;
3217
fda9abcf
MB		 3218 phy->radio_off_context.valid = 0;
3219
e4d6b795
MB		 3220 lo = phy->lo_control;
3221 if (lo) {
3222 memset(lo, 0, sizeof(*(phy->lo_control)));
3223 lo->rebuild = 1;
3224 lo->tx_bias = 0xFF;
3225 }
3226 phy->max_lb_gain = 0;
3227 phy->trsw_rx_gain = 0;
3228 phy->txpwr_offset = 0;
3229
3230 /* NRSSI */
3231 phy->nrssislope = 0;
3232 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3233 phy->nrssi[i] = -1000;
3234 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3235 phy->nrssi_lt[i] = i;
3236
3237 phy->lofcal = 0xFFFF;
3238 phy->initval = 0xFFFF;
3239
3240 spin_lock_init(&phy->lock);
3241 phy->interfmode = B43_INTERFMODE_NONE;
3242 phy->channel = 0xFF;
3243
3244 phy->hardware_power_control = !!modparam_hwpctl;
3245}
3246
3247static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3248{
3249 /* Flags */
3250 dev->reg124_set_0x4 = 0;
6a724d68
MB		 3251 /* Assume the radio is enabled. If it's not enabled, the state will
3252 * immediately get fixed on the first periodic work run. */
3253 dev->radio_hw_enable = 1;
e4d6b795
MB		 3254
3255 /* Stats */
3256 memset(&dev->stats, 0, sizeof(dev->stats));
3257
3258 setup_struct_phy_for_init(dev, &dev->phy);
3259
3260 /* IRQ related flags */
3261 dev->irq_reason = 0;
3262 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3263 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3264
3265 dev->mac_suspended = 1;
3266
3267 /* Noise calculation context */
3268 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3269}
3270
3271static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3272{
3273 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3274 u32 hf;
3275
3276 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3277 return;
3278 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3279 return;
3280
3281 hf = b43_hf_read(dev);
3282 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3283 hf |= B43_HF_BTCOEXALT;
3284 else
3285 hf |= B43_HF_BTCOEX;
3286 b43_hf_write(dev, hf);
3287 //TODO
3288}
3289
3290static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3291{ //TODO
3292}
3293
3294static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3295{
3296#ifdef CONFIG_SSB_DRIVER_PCICORE
3297 struct ssb_bus *bus = dev->dev->bus;
3298 u32 tmp;
3299
3300 if (bus->pcicore.dev &&
3301 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3302 bus->pcicore.dev->id.revision <= 5) {
3303 /* IMCFGLO timeouts workaround. */
3304 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3305 tmp &= ~SSB_IMCFGLO_REQTO;
3306 tmp &= ~SSB_IMCFGLO_SERTO;
3307 switch (bus->bustype) {
3308 case SSB_BUSTYPE_PCI:
3309 case SSB_BUSTYPE_PCMCIA:
3310 tmp |= 0x32;
3311 break;
3312 case SSB_BUSTYPE_SSB:
3313 tmp |= 0x53;
3314 break;
3315 }
3316 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3317 }
3318#endif /* CONFIG_SSB_DRIVER_PCICORE */
3319}
3320
3321/* Shutdown a wireless core */
3322/* Locking: wl->mutex */
3323static void b43_wireless_core_exit(struct b43_wldev *dev)
3324{
3325 struct b43_phy *phy = &dev->phy;
3326
3327 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3328 if (b43_status(dev) != B43_STAT_INITIALIZED)
3329 return;
3330 b43_set_status(dev, B43_STAT_UNINIT);
3331
8e9f7529
MB		 3332 mutex_unlock(&dev->wl->mutex);
3333 b43_rfkill_exit(dev);
3334 mutex_lock(&dev->wl->mutex);
3335
e4d6b795
MB		 3336 b43_rng_exit(dev->wl);
3337 b43_pio_free(dev);
3338 b43_dma_free(dev);
3339 b43_chip_exit(dev);
8e9f7529 3340 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3341 b43_switch_analog(dev, 0);
3342 if (phy->dyn_tssi_tbl)
3343 kfree(phy->tssi2dbm);
3344 kfree(phy->lo_control);
3345 phy->lo_control = NULL;
3346 ssb_device_disable(dev->dev, 0);
3347 ssb_bus_may_powerdown(dev->dev->bus);
3348}
3349
3350/* Initialize a wireless core */
3351static int b43_wireless_core_init(struct b43_wldev *dev)
3352{
3353 struct b43_wl *wl = dev->wl;
3354 struct ssb_bus *bus = dev->dev->bus;
3355 struct ssb_sprom *sprom = &bus->sprom;
3356 struct b43_phy *phy = &dev->phy;
3357 int err;
3358 u32 hf, tmp;
3359
3360 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3361
3362 err = ssb_bus_powerup(bus, 0);
3363 if (err)
3364 goto out;
3365 if (!ssb_device_is_enabled(dev->dev)) {
3366 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3367 b43_wireless_core_reset(dev, tmp);
3368 }
3369
3370 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3371 phy->lo_control =
3372 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3373 if (!phy->lo_control) {
3374 err = -ENOMEM;
3375 goto err_busdown;
3376 }
3377 }
3378 setup_struct_wldev_for_init(dev);
3379
3380 err = b43_phy_init_tssi2dbm_table(dev);
3381 if (err)
3382 goto err_kfree_lo_control;
3383
3384 /* Enable IRQ routing to this device. */
3385 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3386
3387 b43_imcfglo_timeouts_workaround(dev);
3388 b43_bluetooth_coext_disable(dev);
3389 b43_phy_early_init(dev);
3390 err = b43_chip_init(dev);
3391 if (err)
3392 goto err_kfree_tssitbl;
3393 b43_shm_write16(dev, B43_SHM_SHARED,
3394 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3395 hf = b43_hf_read(dev);
3396 if (phy->type == B43_PHYTYPE_G) {
3397 hf |= B43_HF_SYMW;
3398 if (phy->rev == 1)
3399 hf |= B43_HF_GDCW;
3400 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3401 hf |= B43_HF_OFDMPABOOST;
3402 } else if (phy->type == B43_PHYTYPE_B) {
3403 hf |= B43_HF_SYMW;
3404 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3405 hf &= ~B43_HF_GDCW;
3406 }
3407 b43_hf_write(dev, hf);
3408
3409 /* Short/Long Retry Limit.
3410 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3411 * the chip-internal counter.
3412 */
3413 tmp = limit_value(modparam_short_retry, 0, 0xF);
3414 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3415 tmp = limit_value(modparam_long_retry, 0, 0xF);
3416 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3417
3418 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3419 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3420
3421 /* Disable sending probe responses from firmware.
3422 * Setting the MaxTime to one usec will always trigger
3423 * a timeout, so we never send any probe resp.
3424 * A timeout of zero is infinite. */
3425 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3426
3427 b43_rate_memory_init(dev);
3428
3429 /* Minimum Contention Window */
3430 if (phy->type == B43_PHYTYPE_B) {
3431 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3432 } else {
3433 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3434 }
3435 /* Maximum Contention Window */
3436 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3437
3438 do {
3439 if (b43_using_pio(dev)) {
3440 err = b43_pio_init(dev);
3441 } else {
3442 err = b43_dma_init(dev);
3443 if (!err)
3444 b43_qos_init(dev);
3445 }
3446 } while (err == -EAGAIN);
3447 if (err)
3448 goto err_chip_exit;
3449
3450//FIXME
3451#if 1
3452 b43_write16(dev, 0x0612, 0x0050);
3453 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3454 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3455#endif
3456
3457 b43_bluetooth_coext_enable(dev);
3458
3459 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3460 memset(wl->bssid, 0, ETH_ALEN);
4150c572
JB		 3461 memset(wl->mac_addr, 0, ETH_ALEN);
3462 b43_upload_card_macaddress(dev);
e4d6b795 3463 b43_security_init(dev);
8e9f7529 3464 b43_rfkill_init(dev);
e4d6b795
MB		 3465 b43_rng_init(wl);
3466
3467 b43_set_status(dev, B43_STAT_INITIALIZED);
3468
3469 out:
3470 return err;
3471
3472 err_chip_exit:
3473 b43_chip_exit(dev);
3474 err_kfree_tssitbl:
3475 if (phy->dyn_tssi_tbl)
3476 kfree(phy->tssi2dbm);
3477 err_kfree_lo_control:
3478 kfree(phy->lo_control);
3479 phy->lo_control = NULL;
3480 err_busdown:
3481 ssb_bus_may_powerdown(bus);
3482 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3483 return err;
3484}
3485
3486static int b43_add_interface(struct ieee80211_hw *hw,
3487 struct ieee80211_if_init_conf *conf)
3488{
3489 struct b43_wl *wl = hw_to_b43_wl(hw);
3490 struct b43_wldev *dev;
3491 unsigned long flags;
3492 int err = -EOPNOTSUPP;
4150c572
JB		 3493
3494 /* TODO: allow WDS/AP devices to coexist */
3495
3496 if (conf->type != IEEE80211_IF_TYPE_AP &&
3497 conf->type != IEEE80211_IF_TYPE_STA &&
3498 conf->type != IEEE80211_IF_TYPE_WDS &&
3499 conf->type != IEEE80211_IF_TYPE_IBSS)
3500 return -EOPNOTSUPP;
e4d6b795
MB		 3501
3502 mutex_lock(&wl->mutex);
4150c572 3503 if (wl->operating)
e4d6b795
MB		 3504 goto out_mutex_unlock;
3505
3506 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3507
3508 dev = wl->current_dev;
4150c572
JB		 3509 wl->operating = 1;
3510 wl->if_id = conf->if_id;
3511 wl->if_type = conf->type;
3512 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3513
3514 spin_lock_irqsave(&wl->irq_lock, flags);
3515 b43_adjust_opmode(dev);
3516 b43_upload_card_macaddress(dev);
3517 spin_unlock_irqrestore(&wl->irq_lock, flags);
3518
3519 err = 0;
3520 out_mutex_unlock:
3521 mutex_unlock(&wl->mutex);
3522
3523 return err;
3524}
3525
3526static void b43_remove_interface(struct ieee80211_hw *hw,
3527 struct ieee80211_if_init_conf *conf)
3528{
3529 struct b43_wl *wl = hw_to_b43_wl(hw);
3530 struct b43_wldev *dev = wl->current_dev;
3531 unsigned long flags;
3532
3533 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3534
3535 mutex_lock(&wl->mutex);
3536
3537 B43_WARN_ON(!wl->operating);
3538 B43_WARN_ON(wl->if_id != conf->if_id);
3539
3540 wl->operating = 0;
3541
3542 spin_lock_irqsave(&wl->irq_lock, flags);
3543 b43_adjust_opmode(dev);
3544 memset(wl->mac_addr, 0, ETH_ALEN);
3545 b43_upload_card_macaddress(dev);
3546 spin_unlock_irqrestore(&wl->irq_lock, flags);
3547
3548 mutex_unlock(&wl->mutex);
3549}
3550
3551static int b43_start(struct ieee80211_hw *hw)
3552{
3553 struct b43_wl *wl = hw_to_b43_wl(hw);
3554 struct b43_wldev *dev = wl->current_dev;
3555 int did_init = 0;
3556 int err;
3557
3558 mutex_lock(&wl->mutex);
3559
e4d6b795
MB		 3560 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3561 err = b43_wireless_core_init(dev);
3562 if (err)
3563 goto out_mutex_unlock;
3564 did_init = 1;
3565 }
4150c572 3566
e4d6b795
MB		 3567 if (b43_status(dev) < B43_STAT_STARTED) {
3568 err = b43_wireless_core_start(dev);
3569 if (err) {
3570 if (did_init)
3571 b43_wireless_core_exit(dev);
3572 goto out_mutex_unlock;
3573 }
3574 }
3575
4150c572 3576 out_mutex_unlock:
e4d6b795
MB		 3577 mutex_unlock(&wl->mutex);
3578
3579 return err;
3580}
3581
4150c572 3582void b43_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 3583{
3584 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 3585 struct b43_wldev *dev = wl->current_dev;
e4d6b795
MB		 3586
3587 mutex_lock(&wl->mutex);
4150c572
JB		 3588 if (b43_status(dev) >= B43_STAT_STARTED)
3589 b43_wireless_core_stop(dev);
3590 b43_wireless_core_exit(dev);
e4d6b795
MB		 3591 mutex_unlock(&wl->mutex);
3592}
3593
3594static const struct ieee80211_ops b43_hw_ops = {
3595 .tx = b43_tx,
3596 .conf_tx = b43_conf_tx,
3597 .add_interface = b43_add_interface,
3598 .remove_interface = b43_remove_interface,
3599 .config = b43_dev_config,
3600 .config_interface = b43_config_interface,
4150c572 3601 .configure_filter = b43_configure_filter,
e4d6b795
MB		 3602 .set_key = b43_dev_set_key,
3603 .get_stats = b43_get_stats,
3604 .get_tx_stats = b43_get_tx_stats,
4150c572
JB		 3605 .start = b43_start,
3606 .stop = b43_stop,
e4d6b795
MB		 3607};
3608
3609/* Hard-reset the chip. Do not call this directly.
3610 * Use b43_controller_restart()
3611 */
3612static void b43_chip_reset(struct work_struct *work)
3613{
3614 struct b43_wldev *dev =
3615 container_of(work, struct b43_wldev, restart_work);
3616 struct b43_wl *wl = dev->wl;
3617 int err = 0;
3618 int prev_status;
3619
3620 mutex_lock(&wl->mutex);
3621
3622 prev_status = b43_status(dev);
3623 /* Bring the device down... */
3624 if (prev_status >= B43_STAT_STARTED)
3625 b43_wireless_core_stop(dev);
3626 if (prev_status >= B43_STAT_INITIALIZED)
3627 b43_wireless_core_exit(dev);
3628
3629 /* ...and up again. */
3630 if (prev_status >= B43_STAT_INITIALIZED) {
3631 err = b43_wireless_core_init(dev);
3632 if (err)
3633 goto out;
3634 }
3635 if (prev_status >= B43_STAT_STARTED) {
3636 err = b43_wireless_core_start(dev);
3637 if (err) {
3638 b43_wireless_core_exit(dev);
3639 goto out;
3640 }
3641 }
3642 out:
3643 mutex_unlock(&wl->mutex);
3644 if (err)
3645 b43err(wl, "Controller restart FAILED\n");
3646 else
3647 b43info(wl, "Controller restarted\n");
3648}
3649
3650static int b43_setup_modes(struct b43_wldev *dev,
3651 int have_aphy, int have_bphy, int have_gphy)
3652{
3653 struct ieee80211_hw *hw = dev->wl->hw;
3654 struct ieee80211_hw_mode *mode;
3655 struct b43_phy *phy = &dev->phy;
3656 int cnt = 0;
3657 int err;
3658
3659/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3660 have_aphy = 0;
3661
3662 phy->possible_phymodes = 0;
3663 for (; 1; cnt++) {
3664 if (have_aphy) {
3665 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3666 mode = &phy->hwmodes[cnt];
3667
3668 mode->mode = MODE_IEEE80211A;
3669 mode->num_channels = b43_a_chantable_size;
3670 mode->channels = b43_a_chantable;
3671 mode->num_rates = b43_a_ratetable_size;
3672 mode->rates = b43_a_ratetable;
3673 err = ieee80211_register_hwmode(hw, mode);
3674 if (err)
3675 return err;
3676
3677 phy->possible_phymodes |= B43_PHYMODE_A;
3678 have_aphy = 0;
3679 continue;
3680 }
3681 if (have_bphy) {
3682 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3683 mode = &phy->hwmodes[cnt];
3684
3685 mode->mode = MODE_IEEE80211B;
3686 mode->num_channels = b43_bg_chantable_size;
3687 mode->channels = b43_bg_chantable;
3688 mode->num_rates = b43_b_ratetable_size;
3689 mode->rates = b43_b_ratetable;
3690 err = ieee80211_register_hwmode(hw, mode);
3691 if (err)
3692 return err;
3693
3694 phy->possible_phymodes |= B43_PHYMODE_B;
3695 have_bphy = 0;
3696 continue;
3697 }
3698 if (have_gphy) {
3699 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3700 mode = &phy->hwmodes[cnt];
3701
3702 mode->mode = MODE_IEEE80211G;
3703 mode->num_channels = b43_bg_chantable_size;
3704 mode->channels = b43_bg_chantable;
3705 mode->num_rates = b43_g_ratetable_size;
3706 mode->rates = b43_g_ratetable;
3707 err = ieee80211_register_hwmode(hw, mode);
3708 if (err)
3709 return err;
3710
3711 phy->possible_phymodes |= B43_PHYMODE_G;
3712 have_gphy = 0;
3713 continue;
3714 }
3715 break;
3716 }
3717
3718 return 0;
3719}
3720
3721static void b43_wireless_core_detach(struct b43_wldev *dev)
3722{
3723 /* We release firmware that late to not be required to re-request
3724 * is all the time when we reinit the core. */
3725 b43_release_firmware(dev);
3726}
3727
3728static int b43_wireless_core_attach(struct b43_wldev *dev)
3729{
3730 struct b43_wl *wl = dev->wl;
3731 struct ssb_bus *bus = dev->dev->bus;
3732 struct pci_dev *pdev = bus->host_pci;
3733 int err;
3734 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3735 u32 tmp;
3736
3737 /* Do NOT do any device initialization here.
3738 * Do it in wireless_core_init() instead.
3739 * This function is for gathering basic information about the HW, only.
3740 * Also some structs may be set up here. But most likely you want to have
3741 * that in core_init(), too.
3742 */
3743
3744 err = ssb_bus_powerup(bus, 0);
3745 if (err) {
3746 b43err(wl, "Bus powerup failed\n");
3747 goto out;
3748 }
3749 /* Get the PHY type. */
3750 if (dev->dev->id.revision >= 5) {
3751 u32 tmshigh;
3752
3753 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3754 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3755 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3756 if (!have_aphy && !have_gphy)
3757 have_bphy = 1;
3758 } else if (dev->dev->id.revision == 4) {
3759 have_gphy = 1;
3760 have_aphy = 1;
3761 } else
3762 have_bphy = 1;
3763
e4d6b795
MB		 3764 dev->phy.gmode = (have_gphy || have_bphy);
3765 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3766 b43_wireless_core_reset(dev, tmp);
3767
3768 err = b43_phy_versioning(dev);
3769 if (err)
21954c36 3770 goto err_powerdown;
e4d6b795
MB		 3771 /* Check if this device supports multiband. */
3772 if (!pdev ||
3773 (pdev->device != 0x4312 &&
3774 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3775 /* No multiband support. */
3776 have_aphy = 0;
3777 have_bphy = 0;
3778 have_gphy = 0;
3779 switch (dev->phy.type) {
3780 case B43_PHYTYPE_A:
3781 have_aphy = 1;
3782 break;
3783 case B43_PHYTYPE_B:
3784 have_bphy = 1;
3785 break;
3786 case B43_PHYTYPE_G:
3787 have_gphy = 1;
3788 break;
3789 default:
3790 B43_WARN_ON(1);
3791 }
3792 }
3793 dev->phy.gmode = (have_gphy || have_bphy);
3794 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3795 b43_wireless_core_reset(dev, tmp);
3796
3797 err = b43_validate_chipaccess(dev);
3798 if (err)
21954c36 3799 goto err_powerdown;
e4d6b795
MB		 3800 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3801 if (err)
21954c36 3802 goto err_powerdown;
e4d6b795
MB		 3803
3804 /* Now set some default "current_dev" */
3805 if (!wl->current_dev)
3806 wl->current_dev = dev;
3807 INIT_WORK(&dev->restart_work, b43_chip_reset);
3808
8e9f7529 3809 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3810 b43_switch_analog(dev, 0);
3811 ssb_device_disable(dev->dev, 0);
3812 ssb_bus_may_powerdown(bus);
3813
3814out:
3815 return err;
3816
e4d6b795
MB		 3817err_powerdown:
3818 ssb_bus_may_powerdown(bus);
3819 return err;
3820}
3821
3822static void b43_one_core_detach(struct ssb_device *dev)
3823{
3824 struct b43_wldev *wldev;
3825 struct b43_wl *wl;
3826
3827 wldev = ssb_get_drvdata(dev);
3828 wl = wldev->wl;
3829 cancel_work_sync(&wldev->restart_work);
3830 b43_debugfs_remove_device(wldev);
3831 b43_wireless_core_detach(wldev);
3832 list_del(&wldev->list);
3833 wl->nr_devs--;
3834 ssb_set_drvdata(dev, NULL);
3835 kfree(wldev);
3836}
3837
3838static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3839{
3840 struct b43_wldev *wldev;
3841 struct pci_dev *pdev;
3842 int err = -ENOMEM;
3843
3844 if (!list_empty(&wl->devlist)) {
3845 /* We are not the first core on this chip. */
3846 pdev = dev->bus->host_pci;
3847 /* Only special chips support more than one wireless
3848 * core, although some of the other chips have more than
3849 * one wireless core as well. Check for this and
3850 * bail out early.
3851 */
3852 if (!pdev ||
3853 ((pdev->device != 0x4321) &&
3854 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3855 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3856 return -ENODEV;
3857 }
3858 }
3859
3860 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3861 if (!wldev)
3862 goto out;
3863
3864 wldev->dev = dev;
3865 wldev->wl = wl;
3866 b43_set_status(wldev, B43_STAT_UNINIT);
3867 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3868 tasklet_init(&wldev->isr_tasklet,
3869 (void (*)(unsigned long))b43_interrupt_tasklet,
3870 (unsigned long)wldev);
3871 if (modparam_pio)
3872 wldev->__using_pio = 1;
3873 INIT_LIST_HEAD(&wldev->list);
3874
3875 err = b43_wireless_core_attach(wldev);
3876 if (err)
3877 goto err_kfree_wldev;
3878
3879 list_add(&wldev->list, &wl->devlist);
3880 wl->nr_devs++;
3881 ssb_set_drvdata(dev, wldev);
3882 b43_debugfs_add_device(wldev);
3883
3884 out:
3885 return err;
3886
3887 err_kfree_wldev:
3888 kfree(wldev);
3889 return err;
3890}
3891
3892static void b43_sprom_fixup(struct ssb_bus *bus)
3893{
3894 /* boardflags workarounds */
3895 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3896 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3897 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3898 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3899 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3900 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3901
3902 /* Handle case when gain is not set in sprom */
3903 if (bus->sprom.r1.antenna_gain_a == 0xFF)
3904 bus->sprom.r1.antenna_gain_a = 2;
3905 if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3906 bus->sprom.r1.antenna_gain_bg = 2;
3907
3908 /* Convert Antennagain values to Q5.2 */
3909 bus->sprom.r1.antenna_gain_a <<= 2;
3910 bus->sprom.r1.antenna_gain_bg <<= 2;
3911}
3912
3913static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3914{
3915 struct ieee80211_hw *hw = wl->hw;
3916
3917 ssb_set_devtypedata(dev, NULL);
3918 ieee80211_free_hw(hw);
3919}
3920
3921static int b43_wireless_init(struct ssb_device *dev)
3922{
3923 struct ssb_sprom *sprom = &dev->bus->sprom;
3924 struct ieee80211_hw *hw;
3925 struct b43_wl *wl;
3926 int err = -ENOMEM;
3927
3928 b43_sprom_fixup(dev->bus);
3929
3930 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3931 if (!hw) {
3932 b43err(NULL, "Could not allocate ieee80211 device\n");
3933 goto out;
3934 }
3935
3936 /* fill hw info */
4150c572 3937 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
e4d6b795
MB		 3938 hw->max_signal = 100;
3939 hw->max_rssi = -110;
3940 hw->max_noise = -110;
3941 hw->queues = 1; /* FIXME: hardware has more queues */
3942 SET_IEEE80211_DEV(hw, dev->dev);
3943 if (is_valid_ether_addr(sprom->r1.et1mac))
3944 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3945 else
3946 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3947
3948 /* Get and initialize struct b43_wl */
3949 wl = hw_to_b43_wl(hw);
3950 memset(wl, 0, sizeof(*wl));
3951 wl->hw = hw;
3952 spin_lock_init(&wl->irq_lock);
3953 spin_lock_init(&wl->leds_lock);
3954 mutex_init(&wl->mutex);
3955 INIT_LIST_HEAD(&wl->devlist);
3956
3957 ssb_set_devtypedata(dev, wl);
3958 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3959 err = 0;
3960 out:
3961 return err;
3962}
3963
3964static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3965{
3966 struct b43_wl *wl;
3967 int err;
3968 int first = 0;
3969
3970 wl = ssb_get_devtypedata(dev);
3971 if (!wl) {
3972 /* Probing the first core. Must setup common struct b43_wl */
3973 first = 1;
3974 err = b43_wireless_init(dev);
3975 if (err)
3976 goto out;
3977 wl = ssb_get_devtypedata(dev);
3978 B43_WARN_ON(!wl);
3979 }
3980 err = b43_one_core_attach(dev, wl);
3981 if (err)
3982 goto err_wireless_exit;
3983
3984 if (first) {
3985 err = ieee80211_register_hw(wl->hw);
3986 if (err)
3987 goto err_one_core_detach;
3988 }
3989
3990 out:
3991 return err;
3992
3993 err_one_core_detach:
3994 b43_one_core_detach(dev);
3995 err_wireless_exit:
3996 if (first)
3997 b43_wireless_exit(dev, wl);
3998 return err;
3999}
4000
4001static void b43_remove(struct ssb_device *dev)
4002{
4003 struct b43_wl *wl = ssb_get_devtypedata(dev);
4004 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4005
4006 B43_WARN_ON(!wl);
4007 if (wl->current_dev == wldev)
4008 ieee80211_unregister_hw(wl->hw);
4009
4010 b43_one_core_detach(dev);
4011
4012 if (list_empty(&wl->devlist)) {
4013 /* Last core on the chip unregistered.
4014 * We can destroy common struct b43_wl.
4015 */
4016 b43_wireless_exit(dev, wl);
4017 }
4018}
4019
4020/* Perform a hardware reset. This can be called from any context. */
4021void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4022{
4023 /* Must avoid requeueing, if we are in shutdown. */
4024 if (b43_status(dev) < B43_STAT_INITIALIZED)
4025 return;
4026 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4027 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4028}
4029
4030#ifdef CONFIG_PM
4031
4032static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4033{
4034 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4035 struct b43_wl *wl = wldev->wl;
4036
4037 b43dbg(wl, "Suspending...\n");
4038
4039 mutex_lock(&wl->mutex);
4040 wldev->suspend_init_status = b43_status(wldev);
4041 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4042 b43_wireless_core_stop(wldev);
4043 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4044 b43_wireless_core_exit(wldev);
4045 mutex_unlock(&wl->mutex);
4046
4047 b43dbg(wl, "Device suspended.\n");
4048
4049 return 0;
4050}
4051
4052static int b43_resume(struct ssb_device *dev)
4053{
4054 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4055 struct b43_wl *wl = wldev->wl;
4056 int err = 0;
4057
4058 b43dbg(wl, "Resuming...\n");
4059
4060 mutex_lock(&wl->mutex);
4061 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4062 err = b43_wireless_core_init(wldev);
4063 if (err) {
4064 b43err(wl, "Resume failed at core init\n");
4065 goto out;
4066 }
4067 }
4068 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4069 err = b43_wireless_core_start(wldev);
4070 if (err) {
4071 b43_wireless_core_exit(wldev);
4072 b43err(wl, "Resume failed at core start\n");
4073 goto out;
4074 }
4075 }
4076 mutex_unlock(&wl->mutex);
4077
4078 b43dbg(wl, "Device resumed.\n");
4079 out:
4080 return err;
4081}
4082
4083#else /* CONFIG_PM */
4084# define b43_suspend NULL
4085# define b43_resume NULL
4086#endif /* CONFIG_PM */
4087
4088static struct ssb_driver b43_ssb_driver = {
4089 .name = KBUILD_MODNAME,
4090 .id_table = b43_ssb_tbl,
4091 .probe = b43_probe,
4092 .remove = b43_remove,
4093 .suspend = b43_suspend,
4094 .resume = b43_resume,
4095};
4096
4097static int __init b43_init(void)
4098{
4099 int err;
4100
4101 b43_debugfs_init();
4102 err = b43_pcmcia_init();
4103 if (err)
4104 goto err_dfs_exit;
4105 err = ssb_driver_register(&b43_ssb_driver);
4106 if (err)
4107 goto err_pcmcia_exit;
4108
4109 return err;
4110
4111err_pcmcia_exit:
4112 b43_pcmcia_exit();
4113err_dfs_exit:
4114 b43_debugfs_exit();
4115 return err;
4116}
4117
4118static void __exit b43_exit(void)
4119{
4120 ssb_driver_unregister(&b43_ssb_driver);
4121 b43_pcmcia_exit();
4122 b43_debugfs_exit();
4123}
4124
4125module_init(b43_init)
4126module_exit(b43_exit)
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