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cfg80211: fix SME connect
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
0136e51e 61MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 62MODULE_LICENSE("GPL");
63
9c7d99d6
MB		 64MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
65
e4d6b795
MB		 66
67static int modparam_bad_frames_preempt;
68module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
69MODULE_PARM_DESC(bad_frames_preempt,
70 "enable(1) / disable(0) Bad Frames Preemption");
71
e4d6b795
MB		 72static char modparam_fwpostfix[16];
73module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
74MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75
e4d6b795
MB		 76static int modparam_hwpctl;
77module_param_named(hwpctl, modparam_hwpctl, int, 0444);
78MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79
80static int modparam_nohwcrypt;
81module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
82MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83
035d0243 84static int modparam_hwtkip;
85module_param_named(hwtkip, modparam_hwtkip, int, 0444);
86MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
87
403a3a13
MB		 88static int modparam_qos = 1;
89module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 90MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
91
1855ba78
MB		 92static int modparam_btcoex = 1;
93module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 94MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 95
060210f9
MB		 96int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
97module_param_named(verbose, b43_modparam_verbose, int, 0644);
98MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
99
e6f5b934 100
e4d6b795
MB		 101static const struct ssb_device_id b43_ssb_tbl[] = {
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 111 SSB_DEVTABLE_END
112};
113
114MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
115
116/* Channel and ratetables are shared for all devices.
117 * They can't be const, because ieee80211 puts some precalculated
118 * data in there. This data is the same for all devices, so we don't
119 * get concurrency issues */
120#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 121 { \
122 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
123 .hw_value = (_rateid), \
124 .flags = (_flags), \
e4d6b795 125 }
8318d78a
JB		 126
127/*
128 * NOTE: When changing this, sync with xmit.c's
129 * b43_plcp_get_bitrate_idx_* functions!
130 */
e4d6b795 131static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 132 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
133 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 144};
145
146#define b43_a_ratetable (__b43_ratetable + 4)
147#define b43_a_ratetable_size 8
148#define b43_b_ratetable (__b43_ratetable + 0)
149#define b43_b_ratetable_size 4
150#define b43_g_ratetable (__b43_ratetable + 0)
151#define b43_g_ratetable_size 12
152
bb1eeff1
MB		 153#define CHAN4G(_channel, _freq, _flags) { \
154 .band = IEEE80211_BAND_2GHZ, \
155 .center_freq = (_freq), \
156 .hw_value = (_channel), \
157 .flags = (_flags), \
158 .max_antenna_gain = 0, \
159 .max_power = 30, \
160}
96c755a3 161static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 162 CHAN4G(1, 2412, 0),
163 CHAN4G(2, 2417, 0),
164 CHAN4G(3, 2422, 0),
165 CHAN4G(4, 2427, 0),
166 CHAN4G(5, 2432, 0),
167 CHAN4G(6, 2437, 0),
168 CHAN4G(7, 2442, 0),
169 CHAN4G(8, 2447, 0),
170 CHAN4G(9, 2452, 0),
171 CHAN4G(10, 2457, 0),
172 CHAN4G(11, 2462, 0),
173 CHAN4G(12, 2467, 0),
174 CHAN4G(13, 2472, 0),
175 CHAN4G(14, 2484, 0),
176};
177#undef CHAN4G
178
179#define CHAN5G(_channel, _flags) { \
180 .band = IEEE80211_BAND_5GHZ, \
181 .center_freq = 5000 + (5 * (_channel)), \
182 .hw_value = (_channel), \
183 .flags = (_flags), \
184 .max_antenna_gain = 0, \
185 .max_power = 30, \
186}
187static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
188 CHAN5G(32, 0), CHAN5G(34, 0),
189 CHAN5G(36, 0), CHAN5G(38, 0),
190 CHAN5G(40, 0), CHAN5G(42, 0),
191 CHAN5G(44, 0), CHAN5G(46, 0),
192 CHAN5G(48, 0), CHAN5G(50, 0),
193 CHAN5G(52, 0), CHAN5G(54, 0),
194 CHAN5G(56, 0), CHAN5G(58, 0),
195 CHAN5G(60, 0), CHAN5G(62, 0),
196 CHAN5G(64, 0), CHAN5G(66, 0),
197 CHAN5G(68, 0), CHAN5G(70, 0),
198 CHAN5G(72, 0), CHAN5G(74, 0),
199 CHAN5G(76, 0), CHAN5G(78, 0),
200 CHAN5G(80, 0), CHAN5G(82, 0),
201 CHAN5G(84, 0), CHAN5G(86, 0),
202 CHAN5G(88, 0), CHAN5G(90, 0),
203 CHAN5G(92, 0), CHAN5G(94, 0),
204 CHAN5G(96, 0), CHAN5G(98, 0),
205 CHAN5G(100, 0), CHAN5G(102, 0),
206 CHAN5G(104, 0), CHAN5G(106, 0),
207 CHAN5G(108, 0), CHAN5G(110, 0),
208 CHAN5G(112, 0), CHAN5G(114, 0),
209 CHAN5G(116, 0), CHAN5G(118, 0),
210 CHAN5G(120, 0), CHAN5G(122, 0),
211 CHAN5G(124, 0), CHAN5G(126, 0),
212 CHAN5G(128, 0), CHAN5G(130, 0),
213 CHAN5G(132, 0), CHAN5G(134, 0),
214 CHAN5G(136, 0), CHAN5G(138, 0),
215 CHAN5G(140, 0), CHAN5G(142, 0),
216 CHAN5G(144, 0), CHAN5G(145, 0),
217 CHAN5G(146, 0), CHAN5G(147, 0),
218 CHAN5G(148, 0), CHAN5G(149, 0),
219 CHAN5G(150, 0), CHAN5G(151, 0),
220 CHAN5G(152, 0), CHAN5G(153, 0),
221 CHAN5G(154, 0), CHAN5G(155, 0),
222 CHAN5G(156, 0), CHAN5G(157, 0),
223 CHAN5G(158, 0), CHAN5G(159, 0),
224 CHAN5G(160, 0), CHAN5G(161, 0),
225 CHAN5G(162, 0), CHAN5G(163, 0),
226 CHAN5G(164, 0), CHAN5G(165, 0),
227 CHAN5G(166, 0), CHAN5G(168, 0),
228 CHAN5G(170, 0), CHAN5G(172, 0),
229 CHAN5G(174, 0), CHAN5G(176, 0),
230 CHAN5G(178, 0), CHAN5G(180, 0),
231 CHAN5G(182, 0), CHAN5G(184, 0),
232 CHAN5G(186, 0), CHAN5G(188, 0),
233 CHAN5G(190, 0), CHAN5G(192, 0),
234 CHAN5G(194, 0), CHAN5G(196, 0),
235 CHAN5G(198, 0), CHAN5G(200, 0),
236 CHAN5G(202, 0), CHAN5G(204, 0),
237 CHAN5G(206, 0), CHAN5G(208, 0),
238 CHAN5G(210, 0), CHAN5G(212, 0),
239 CHAN5G(214, 0), CHAN5G(216, 0),
240 CHAN5G(218, 0), CHAN5G(220, 0),
241 CHAN5G(222, 0), CHAN5G(224, 0),
242 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 243};
244
bb1eeff1
MB		 245static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
246 CHAN5G(34, 0), CHAN5G(36, 0),
247 CHAN5G(38, 0), CHAN5G(40, 0),
248 CHAN5G(42, 0), CHAN5G(44, 0),
249 CHAN5G(46, 0), CHAN5G(48, 0),
250 CHAN5G(52, 0), CHAN5G(56, 0),
251 CHAN5G(60, 0), CHAN5G(64, 0),
252 CHAN5G(100, 0), CHAN5G(104, 0),
253 CHAN5G(108, 0), CHAN5G(112, 0),
254 CHAN5G(116, 0), CHAN5G(120, 0),
255 CHAN5G(124, 0), CHAN5G(128, 0),
256 CHAN5G(132, 0), CHAN5G(136, 0),
257 CHAN5G(140, 0), CHAN5G(149, 0),
258 CHAN5G(153, 0), CHAN5G(157, 0),
259 CHAN5G(161, 0), CHAN5G(165, 0),
260 CHAN5G(184, 0), CHAN5G(188, 0),
261 CHAN5G(192, 0), CHAN5G(196, 0),
262 CHAN5G(200, 0), CHAN5G(204, 0),
263 CHAN5G(208, 0), CHAN5G(212, 0),
264 CHAN5G(216, 0),
265};
266#undef CHAN5G
267
268static struct ieee80211_supported_band b43_band_5GHz_nphy = {
269 .band = IEEE80211_BAND_5GHZ,
270 .channels = b43_5ghz_nphy_chantable,
271 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
272 .bitrates = b43_a_ratetable,
273 .n_bitrates = b43_a_ratetable_size,
e4d6b795 274};
8318d78a 275
bb1eeff1
MB		 276static struct ieee80211_supported_band b43_band_5GHz_aphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_aphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
8318d78a 282};
e4d6b795 283
8318d78a 284static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 285 .band = IEEE80211_BAND_2GHZ,
286 .channels = b43_2ghz_chantable,
287 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
288 .bitrates = b43_g_ratetable,
289 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 290};
291
e4d6b795
MB		 292static void b43_wireless_core_exit(struct b43_wldev *dev);
293static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 294static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795
MB		 295static int b43_wireless_core_start(struct b43_wldev *dev);
296
297static int b43_ratelimit(struct b43_wl *wl)
298{
299 if (!wl || !wl->current_dev)
300 return 1;
301 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
302 return 1;
303 /* We are up and running.
304 * Ratelimit the messages to avoid DoS over the net. */
305 return net_ratelimit();
306}
307
308void b43info(struct b43_wl *wl, const char *fmt, ...)
309{
310 va_list args;
311
060210f9
MB		 312 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
313 return;
e4d6b795
MB		 314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_INFO "b43-%s: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43err(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
060210f9
MB		 327 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
328 return;
e4d6b795
MB		 329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_ERR "b43-%s ERROR: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336}
337
338void b43warn(struct b43_wl *wl, const char *fmt, ...)
339{
340 va_list args;
341
060210f9
MB		 342 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
343 return;
e4d6b795
MB		 344 if (!b43_ratelimit(wl))
345 return;
346 va_start(args, fmt);
347 printk(KERN_WARNING "b43-%s warning: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 vprintk(fmt, args);
350 va_end(args);
351}
352
e4d6b795
MB		 353void b43dbg(struct b43_wl *wl, const char *fmt, ...)
354{
355 va_list args;
356
060210f9
MB		 357 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
358 return;
e4d6b795
MB		 359 va_start(args, fmt);
360 printk(KERN_DEBUG "b43-%s debug: ",
361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
362 vprintk(fmt, args);
363 va_end(args);
364}
e4d6b795
MB		 365
366static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
367{
368 u32 macctl;
369
370 B43_WARN_ON(offset % 4 != 0);
371
372 macctl = b43_read32(dev, B43_MMIO_MACCTL);
373 if (macctl & B43_MACCTL_BE)
374 val = swab32(val);
375
376 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
377 mmiowb();
378 b43_write32(dev, B43_MMIO_RAM_DATA, val);
379}
380
280d0e16
MB		 381static inline void b43_shm_control_word(struct b43_wldev *dev,
382 u16 routing, u16 offset)
e4d6b795
MB		 383{
384 u32 control;
385
386 /* "offset" is the WORD offset. */
e4d6b795
MB		 387 control = routing;
388 control <<= 16;
389 control |= offset;
390 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
391}
392
69eddc8a 393u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 394{
395 u32 ret;
396
397 if (routing == B43_SHM_SHARED) {
398 B43_WARN_ON(offset & 0x0001);
399 if (offset & 0x0003) {
400 /* Unaligned access */
401 b43_shm_control_word(dev, routing, offset >> 2);
402 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 403 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 404 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 405
280d0e16 406 goto out;
e4d6b795
MB		 407 }
408 offset >>= 2;
409 }
410 b43_shm_control_word(dev, routing, offset);
411 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 412out:
e4d6b795
MB		 413 return ret;
414}
415
69eddc8a 416u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 417{
418 u16 ret;
419
e4d6b795
MB		 420 if (routing == B43_SHM_SHARED) {
421 B43_WARN_ON(offset & 0x0001);
422 if (offset & 0x0003) {
423 /* Unaligned access */
424 b43_shm_control_word(dev, routing, offset >> 2);
425 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
426
280d0e16 427 goto out;
e4d6b795
MB		 428 }
429 offset >>= 2;
430 }
431 b43_shm_control_word(dev, routing, offset);
432 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 433out:
e4d6b795
MB		 434 return ret;
435}
436
69eddc8a 437void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 438{
e4d6b795
MB		 439 if (routing == B43_SHM_SHARED) {
440 B43_WARN_ON(offset & 0x0001);
441 if (offset & 0x0003) {
442 /* Unaligned access */
443 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 444 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 445 value & 0xFFFF);
e4d6b795 446 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 447 b43_write16(dev, B43_MMIO_SHM_DATA,
448 (value >> 16) & 0xFFFF);
6bbc321a 449 return;
e4d6b795
MB		 450 }
451 offset >>= 2;
452 }
453 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 454 b43_write32(dev, B43_MMIO_SHM_DATA, value);
455}
456
69eddc8a 457void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 458{
e4d6b795
MB		 459 if (routing == B43_SHM_SHARED) {
460 B43_WARN_ON(offset & 0x0001);
461 if (offset & 0x0003) {
462 /* Unaligned access */
463 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 464 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 465 return;
e4d6b795
MB		 466 }
467 offset >>= 2;
468 }
469 b43_shm_control_word(dev, routing, offset);
e4d6b795 470 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 471}
472
e4d6b795 473/* Read HostFlags */
99da185a 474u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 475{
35f0d354 476 u64 ret;
e4d6b795
MB		 477
478 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
479 ret <<= 16;
35f0d354
MB		 480 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
481 ret <<= 16;
e4d6b795
MB		 482 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
483
484 return ret;
485}
486
487/* Write HostFlags */
35f0d354 488void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 489{
35f0d354
MB		 490 u16 lo, mi, hi;
491
492 lo = (value & 0x00000000FFFFULL);
493 mi = (value & 0x0000FFFF0000ULL) >> 16;
494 hi = (value & 0xFFFF00000000ULL) >> 32;
495 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
496 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 498}
499
403a3a13
MB		 500/* Read the firmware capabilities bitmask (Opensource firmware only) */
501static u16 b43_fwcapa_read(struct b43_wldev *dev)
502{
503 B43_WARN_ON(!dev->fw.opensource);
504 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
505}
506
3ebbbb56 507void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 508{
3ebbbb56
MB		 509 u32 low, high;
510
511 B43_WARN_ON(dev->dev->id.revision < 3);
512
513 /* The hardware guarantees us an atomic read, if we
514 * read the low register first. */
515 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
516 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
517
518 *tsf = high;
519 *tsf <<= 32;
520 *tsf |= low;
e4d6b795
MB		 521}
522
523static void b43_time_lock(struct b43_wldev *dev)
524{
525 u32 macctl;
526
527 macctl = b43_read32(dev, B43_MMIO_MACCTL);
528 macctl |= B43_MACCTL_TBTTHOLD;
529 b43_write32(dev, B43_MMIO_MACCTL, macctl);
530 /* Commit the write */
531 b43_read32(dev, B43_MMIO_MACCTL);
532}
533
534static void b43_time_unlock(struct b43_wldev *dev)
535{
536 u32 macctl;
537
538 macctl = b43_read32(dev, B43_MMIO_MACCTL);
539 macctl &= ~B43_MACCTL_TBTTHOLD;
540 b43_write32(dev, B43_MMIO_MACCTL, macctl);
541 /* Commit the write */
542 b43_read32(dev, B43_MMIO_MACCTL);
543}
544
545static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
546{
3ebbbb56
MB		 547 u32 low, high;
548
549 B43_WARN_ON(dev->dev->id.revision < 3);
550
551 low = tsf;
552 high = (tsf >> 32);
553 /* The hardware guarantees us an atomic write, if we
554 * write the low register first. */
555 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
556 mmiowb();
557 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
558 mmiowb();
e4d6b795
MB		 559}
560
561void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
562{
563 b43_time_lock(dev);
564 b43_tsf_write_locked(dev, tsf);
565 b43_time_unlock(dev);
566}
567
568static
99da185a 569void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 570{
571 static const u8 zero_addr[ETH_ALEN] = { 0 };
572 u16 data;
573
574 if (!mac)
575 mac = zero_addr;
576
577 offset |= 0x0020;
578 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
579
580 data = mac[0];
581 data |= mac[1] << 8;
582 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
583 data = mac[2];
584 data |= mac[3] << 8;
585 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
586 data = mac[4];
587 data |= mac[5] << 8;
588 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
589}
590
591static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
592{
593 const u8 *mac;
594 const u8 *bssid;
595 u8 mac_bssid[ETH_ALEN * 2];
596 int i;
597 u32 tmp;
598
599 bssid = dev->wl->bssid;
600 mac = dev->wl->mac_addr;
601
602 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
603
604 memcpy(mac_bssid, mac, ETH_ALEN);
605 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
606
607 /* Write our MAC address and BSSID to template ram */
608 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
609 tmp = (u32) (mac_bssid[i + 0]);
610 tmp |= (u32) (mac_bssid[i + 1]) << 8;
611 tmp |= (u32) (mac_bssid[i + 2]) << 16;
612 tmp |= (u32) (mac_bssid[i + 3]) << 24;
613 b43_ram_write(dev, 0x20 + i, tmp);
614 }
615}
616
4150c572 617static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 618{
e4d6b795 619 b43_write_mac_bssid_templates(dev);
4150c572 620 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 621}
622
623static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
624{
625 /* slot_time is in usec. */
626 if (dev->phy.type != B43_PHYTYPE_G)
627 return;
628 b43_write16(dev, 0x684, 510 + slot_time);
629 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
630}
631
632static void b43_short_slot_timing_enable(struct b43_wldev *dev)
633{
634 b43_set_slot_time(dev, 9);
e4d6b795
MB		 635}
636
637static void b43_short_slot_timing_disable(struct b43_wldev *dev)
638{
639 b43_set_slot_time(dev, 20);
e4d6b795
MB		 640}
641
e4d6b795 642/* DummyTransmission function, as documented on
2f19c287 643 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 644 */
2f19c287 645void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 646{
647 struct b43_phy *phy = &dev->phy;
648 unsigned int i, max_loop;
649 u16 value;
650 u32 buffer[5] = {
651 0x00000000,
652 0x00D40000,
653 0x00000000,
654 0x01000000,
655 0x00000000,
656 };
657
2f19c287 658 if (ofdm) {
e4d6b795
MB		 659 max_loop = 0x1E;
660 buffer[0] = 0x000201CC;
2f19c287 661 } else {
e4d6b795
MB		 662 max_loop = 0xFA;
663 buffer[0] = 0x000B846E;
e4d6b795
MB		 664 }
665
666 for (i = 0; i < 5; i++)
667 b43_ram_write(dev, i * 4, buffer[i]);
668
e4d6b795 669 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 670 if (dev->dev->id.revision < 11)
671 b43_write16(dev, 0x07C0, 0x0000);
672 else
673 b43_write16(dev, 0x07C0, 0x0100);
674 value = (ofdm ? 0x41 : 0x40);
e4d6b795 675 b43_write16(dev, 0x050C, value);
2f19c287
GS		 676 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
677 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 678 b43_write16(dev, 0x0508, 0x0000);
679 b43_write16(dev, 0x050A, 0x0000);
680 b43_write16(dev, 0x054C, 0x0000);
681 b43_write16(dev, 0x056A, 0x0014);
682 b43_write16(dev, 0x0568, 0x0826);
683 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 684 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
685 //SPEC TODO
686 }
687
688 switch (phy->type) {
689 case B43_PHYTYPE_N:
690 b43_write16(dev, 0x0502, 0x00D0);
691 break;
692 case B43_PHYTYPE_LP:
693 b43_write16(dev, 0x0502, 0x0050);
694 break;
695 default:
696 b43_write16(dev, 0x0502, 0x0030);
697 }
e4d6b795
MB		 698
699 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
700 b43_radio_write16(dev, 0x0051, 0x0017);
701 for (i = 0x00; i < max_loop; i++) {
702 value = b43_read16(dev, 0x050E);
703 if (value & 0x0080)
704 break;
705 udelay(10);
706 }
707 for (i = 0x00; i < 0x0A; i++) {
708 value = b43_read16(dev, 0x050E);
709 if (value & 0x0400)
710 break;
711 udelay(10);
712 }
1d280ddc 713 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 714 value = b43_read16(dev, 0x0690);
715 if (!(value & 0x0100))
716 break;
717 udelay(10);
718 }
719 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
720 b43_radio_write16(dev, 0x0051, 0x0037);
721}
722
723static void key_write(struct b43_wldev *dev,
99da185a 724 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 725{
726 unsigned int i;
727 u32 offset;
728 u16 value;
729 u16 kidx;
730
731 /* Key index/algo block */
732 kidx = b43_kidx_to_fw(dev, index);
733 value = ((kidx << 4) | algorithm);
734 b43_shm_write16(dev, B43_SHM_SHARED,
735 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
736
737 /* Write the key to the Key Table Pointer offset */
738 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
739 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
740 value = key[i];
741 value |= (u16) (key[i + 1]) << 8;
742 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
743 }
744}
745
99da185a 746static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 747{
748 u32 addrtmp[2] = { 0, 0, };
66d2d089 749 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 750
751 if (b43_new_kidx_api(dev))
66d2d089 752 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 753
66d2d089
MB		 754 B43_WARN_ON(index < pairwise_keys_start);
755 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 756 * Physical mac 0 is mapped to physical key 4 or 8, depending
757 * on the firmware version.
758 * So we must adjust the index here.
759 */
66d2d089
MB		 760 index -= pairwise_keys_start;
761 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 762
763 if (addr) {
764 addrtmp[0] = addr[0];
765 addrtmp[0] |= ((u32) (addr[1]) << 8);
766 addrtmp[0] |= ((u32) (addr[2]) << 16);
767 addrtmp[0] |= ((u32) (addr[3]) << 24);
768 addrtmp[1] = addr[4];
769 addrtmp[1] |= ((u32) (addr[5]) << 8);
770 }
771
66d2d089
MB		 772 /* Receive match transmitter address (RCMTA) mechanism */
773 b43_shm_write32(dev, B43_SHM_RCMTA,
774 (index * 2) + 0, addrtmp[0]);
775 b43_shm_write16(dev, B43_SHM_RCMTA,
776 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 777}
778
035d0243 779/* The ucode will use phase1 key with TEK key to decrypt rx packets.
780 * When a packet is received, the iv32 is checked.
781 * - if it doesn't the packet is returned without modification (and software
782 * decryption can be done). That's what happen when iv16 wrap.
783 * - if it does, the rc4 key is computed, and decryption is tried.
784 * Either it will success and B43_RX_MAC_DEC is returned,
785 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
786 * and the packet is not usable (it got modified by the ucode).
787 * So in order to never have B43_RX_MAC_DECERR, we should provide
788 * a iv32 and phase1key that match. Because we drop packets in case of
789 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
790 * packets will be lost without higher layer knowing (ie no resync possible
791 * until next wrap).
792 *
793 * NOTE : this should support 50 key like RCMTA because
794 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
795 */
796static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
797 u16 *phase1key)
798{
799 unsigned int i;
800 u32 offset;
801 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
802
803 if (!modparam_hwtkip)
804 return;
805
806 if (b43_new_kidx_api(dev))
807 pairwise_keys_start = B43_NR_GROUP_KEYS;
808
809 B43_WARN_ON(index < pairwise_keys_start);
810 /* We have four default TX keys and possibly four default RX keys.
811 * Physical mac 0 is mapped to physical key 4 or 8, depending
812 * on the firmware version.
813 * So we must adjust the index here.
814 */
815 index -= pairwise_keys_start;
816 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
817
818 if (b43_debug(dev, B43_DBG_KEYS)) {
819 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
820 index, iv32);
821 }
822 /* Write the key to the RX tkip shared mem */
823 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
824 for (i = 0; i < 10; i += 2) {
825 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
826 phase1key ? phase1key[i / 2] : 0);
827 }
828 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
829 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
830}
831
832static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
833 struct ieee80211_key_conf *keyconf, const u8 *addr,
834 u32 iv32, u16 *phase1key)
835{
836 struct b43_wl *wl = hw_to_b43_wl(hw);
837 struct b43_wldev *dev;
838 int index = keyconf->hw_key_idx;
839
840 if (B43_WARN_ON(!modparam_hwtkip))
841 return;
842
843 mutex_lock(&wl->mutex);
844
845 dev = wl->current_dev;
846 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
847 goto out_unlock;
848
849 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
850
851 rx_tkip_phase1_write(dev, index, iv32, phase1key);
852 keymac_write(dev, index, addr);
853
854out_unlock:
855 mutex_unlock(&wl->mutex);
856}
857
e4d6b795
MB		 858static void do_key_write(struct b43_wldev *dev,
859 u8 index, u8 algorithm,
99da185a 860 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 861{
862 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 864
865 if (b43_new_kidx_api(dev))
66d2d089 866 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 867
66d2d089 868 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 869 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
870
66d2d089 871 if (index >= pairwise_keys_start)
e4d6b795 872 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 873 if (algorithm == B43_SEC_ALGO_TKIP) {
874 /*
875 * We should provide an initial iv32, phase1key pair.
876 * We could start with iv32=0 and compute the corresponding
877 * phase1key, but this means calling ieee80211_get_tkip_key
878 * with a fake skb (or export other tkip function).
879 * Because we are lazy we hope iv32 won't start with
880 * 0xffffffff and let's b43_op_update_tkip_key provide a
881 * correct pair.
882 */
883 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
884 } else if (index >= pairwise_keys_start) /* clear it */
885 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 886 if (key)
887 memcpy(buf, key, key_len);
888 key_write(dev, index, algorithm, buf);
66d2d089 889 if (index >= pairwise_keys_start)
e4d6b795
MB		 890 keymac_write(dev, index, mac_addr);
891
892 dev->key[index].algorithm = algorithm;
893}
894
895static int b43_key_write(struct b43_wldev *dev,
896 int index, u8 algorithm,
99da185a
JD		 897 const u8 *key, size_t key_len,
898 const u8 *mac_addr,
e4d6b795
MB		 899 struct ieee80211_key_conf *keyconf)
900{
901 int i;
66d2d089 902 int pairwise_keys_start;
e4d6b795 903
035d0243 904 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
905 * - Temporal Encryption Key (128 bits)
906 * - Temporal Authenticator Tx MIC Key (64 bits)
907 * - Temporal Authenticator Rx MIC Key (64 bits)
908 *
909 * Hardware only store TEK
910 */
911 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
912 key_len = 16;
e4d6b795
MB		 913 if (key_len > B43_SEC_KEYSIZE)
914 return -EINVAL;
66d2d089 915 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 916 /* Check that we don't already have this key. */
917 B43_WARN_ON(dev->key[i].keyconf == keyconf);
918 }
919 if (index < 0) {
e808e586 920 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 921 if (b43_new_kidx_api(dev))
66d2d089 922 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 923 else
66d2d089
MB		 924 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
925 for (i = pairwise_keys_start;
926 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
927 i++) {
928 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 929 if (!dev->key[i].keyconf) {
930 /* found empty */
931 index = i;
932 break;
933 }
934 }
935 if (index < 0) {
e808e586 936 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 937 return -ENOSPC;
938 }
939 } else
940 B43_WARN_ON(index > 3);
941
942 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
943 if ((index <= 3) && !b43_new_kidx_api(dev)) {
944 /* Default RX key */
945 B43_WARN_ON(mac_addr);
946 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
947 }
948 keyconf->hw_key_idx = index;
949 dev->key[index].keyconf = keyconf;
950
951 return 0;
952}
953
954static int b43_key_clear(struct b43_wldev *dev, int index)
955{
66d2d089 956 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 957 return -EINVAL;
958 do_key_write(dev, index, B43_SEC_ALGO_NONE,
959 NULL, B43_SEC_KEYSIZE, NULL);
960 if ((index <= 3) && !b43_new_kidx_api(dev)) {
961 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
962 NULL, B43_SEC_KEYSIZE, NULL);
963 }
964 dev->key[index].keyconf = NULL;
965
966 return 0;
967}
968
969static void b43_clear_keys(struct b43_wldev *dev)
970{
66d2d089 971 int i, count;
e4d6b795 972
66d2d089
MB		 973 if (b43_new_kidx_api(dev))
974 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
975 else
976 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
977 for (i = 0; i < count; i++)
e4d6b795
MB		 978 b43_key_clear(dev, i);
979}
980
9cf7f247
MB		 981static void b43_dump_keymemory(struct b43_wldev *dev)
982{
66d2d089 983 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 984 u8 mac[ETH_ALEN];
985 u16 algo;
986 u32 rcmta0;
987 u16 rcmta1;
988 u64 hf;
989 struct b43_key *key;
990
991 if (!b43_debug(dev, B43_DBG_KEYS))
992 return;
993
994 hf = b43_hf_read(dev);
995 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
996 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 997 if (b43_new_kidx_api(dev)) {
998 pairwise_keys_start = B43_NR_GROUP_KEYS;
999 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1000 } else {
1001 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1002 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1003 }
1004 for (index = 0; index < count; index++) {
9cf7f247
MB		 1005 key = &(dev->key[index]);
1006 printk(KERN_DEBUG "Key slot %02u: %s",
1007 index, (key->keyconf == NULL) ? " " : "*");
1008 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1009 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1010 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1011 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1012 }
1013
1014 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1015 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1016 printk(" Algo: %04X/%02X", algo, key->algorithm);
1017
66d2d089 1018 if (index >= pairwise_keys_start) {
035d0243 1019 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1020 printk(" TKIP: ");
1021 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1022 for (i = 0; i < 14; i += 2) {
1023 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1024 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1025 }
1026 }
9cf7f247 1027 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1028 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1029 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1030 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1031 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1032 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1033 printk(" MAC: %pM", mac);
9cf7f247
MB		 1034 } else
1035 printk(" DEFAULT KEY");
1036 printk("\n");
1037 }
1038}
1039
e4d6b795
MB		 1040void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1041{
1042 u32 macctl;
1043 u16 ucstat;
1044 bool hwps;
1045 bool awake;
1046 int i;
1047
1048 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1049 (ps_flags & B43_PS_DISABLED));
1050 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1051
1052 if (ps_flags & B43_PS_ENABLED) {
1053 hwps = 1;
1054 } else if (ps_flags & B43_PS_DISABLED) {
1055 hwps = 0;
1056 } else {
1057 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1058 // and thus is not an AP and we are associated, set bit 25
1059 }
1060 if (ps_flags & B43_PS_AWAKE) {
1061 awake = 1;
1062 } else if (ps_flags & B43_PS_ASLEEP) {
1063 awake = 0;
1064 } else {
1065 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1066 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1067 // successful, set bit26
1068 }
1069
1070/* FIXME: For now we force awake-on and hwps-off */
1071 hwps = 0;
1072 awake = 1;
1073
1074 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1075 if (hwps)
1076 macctl |= B43_MACCTL_HWPS;
1077 else
1078 macctl &= ~B43_MACCTL_HWPS;
1079 if (awake)
1080 macctl |= B43_MACCTL_AWAKE;
1081 else
1082 macctl &= ~B43_MACCTL_AWAKE;
1083 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1084 /* Commit write */
1085 b43_read32(dev, B43_MMIO_MACCTL);
1086 if (awake && dev->dev->id.revision >= 5) {
1087 /* Wait for the microcode to wake up. */
1088 for (i = 0; i < 100; i++) {
1089 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1090 B43_SHM_SH_UCODESTAT);
1091 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1092 break;
1093 udelay(10);
1094 }
1095 }
1096}
1097
e4d6b795
MB		 1098void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1099{
1100 u32 tmslow;
1101 u32 macctl;
1102
1103 flags |= B43_TMSLOW_PHYCLKEN;
1104 flags |= B43_TMSLOW_PHYRESET;
1105 ssb_device_enable(dev->dev, flags);
1106 msleep(2); /* Wait for the PLL to turn on. */
1107
1108 /* Now take the PHY out of Reset again */
1109 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1110 tmslow |= SSB_TMSLOW_FGC;
1111 tmslow &= ~B43_TMSLOW_PHYRESET;
1112 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1113 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1114 msleep(1);
1115 tmslow &= ~SSB_TMSLOW_FGC;
1116 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1117 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1118 msleep(1);
1119
fb11137a
MB		 1120 /* Turn Analog ON, but only if we already know the PHY-type.
1121 * This protects against very early setup where we don't know the
1122 * PHY-type, yet. wireless_core_reset will be called once again later,
1123 * when we know the PHY-type. */
1124 if (dev->phy.ops)
cb24f57f 1125 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1126
1127 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1128 macctl &= ~B43_MACCTL_GMODE;
1129 if (flags & B43_TMSLOW_GMODE)
1130 macctl |= B43_MACCTL_GMODE;
1131 macctl |= B43_MACCTL_IHR_ENABLED;
1132 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1133}
1134
1135static void handle_irq_transmit_status(struct b43_wldev *dev)
1136{
1137 u32 v0, v1;
1138 u16 tmp;
1139 struct b43_txstatus stat;
1140
1141 while (1) {
1142 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1143 if (!(v0 & 0x00000001))
1144 break;
1145 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1146
1147 stat.cookie = (v0 >> 16);
1148 stat.seq = (v1 & 0x0000FFFF);
1149 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1150 tmp = (v0 & 0x0000FFFF);
1151 stat.frame_count = ((tmp & 0xF000) >> 12);
1152 stat.rts_count = ((tmp & 0x0F00) >> 8);
1153 stat.supp_reason = ((tmp & 0x001C) >> 2);
1154 stat.pm_indicated = !!(tmp & 0x0080);
1155 stat.intermediate = !!(tmp & 0x0040);
1156 stat.for_ampdu = !!(tmp & 0x0020);
1157 stat.acked = !!(tmp & 0x0002);
1158
1159 b43_handle_txstatus(dev, &stat);
1160 }
1161}
1162
1163static void drain_txstatus_queue(struct b43_wldev *dev)
1164{
1165 u32 dummy;
1166
1167 if (dev->dev->id.revision < 5)
1168 return;
1169 /* Read all entries from the microcode TXstatus FIFO
1170 * and throw them away.
1171 */
1172 while (1) {
1173 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1174 if (!(dummy & 0x00000001))
1175 break;
1176 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1177 }
1178}
1179
1180static u32 b43_jssi_read(struct b43_wldev *dev)
1181{
1182 u32 val = 0;
1183
1184 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1185 val <<= 16;
1186 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1187
1188 return val;
1189}
1190
1191static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1192{
1193 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1194 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1195}
1196
1197static void b43_generate_noise_sample(struct b43_wldev *dev)
1198{
1199 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1200 b43_write32(dev, B43_MMIO_MACCMD,
1201 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1202}
1203
1204static void b43_calculate_link_quality(struct b43_wldev *dev)
1205{
1206 /* Top half of Link Quality calculation. */
1207
ef1a628d
MB		 1208 if (dev->phy.type != B43_PHYTYPE_G)
1209 return;
e4d6b795
MB		 1210 if (dev->noisecalc.calculation_running)
1211 return;
e4d6b795
MB		 1212 dev->noisecalc.calculation_running = 1;
1213 dev->noisecalc.nr_samples = 0;
1214
1215 b43_generate_noise_sample(dev);
1216}
1217
1218static void handle_irq_noise(struct b43_wldev *dev)
1219{
ef1a628d 1220 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1221 u16 tmp;
1222 u8 noise[4];
1223 u8 i, j;
1224 s32 average;
1225
1226 /* Bottom half of Link Quality calculation. */
1227
ef1a628d
MB		 1228 if (dev->phy.type != B43_PHYTYPE_G)
1229 return;
1230
98a3b2fe
MB		 1231 /* Possible race condition: It might be possible that the user
1232 * changed to a different channel in the meantime since we
1233 * started the calculation. We ignore that fact, since it's
1234 * not really that much of a problem. The background noise is
1235 * an estimation only anyway. Slightly wrong results will get damped
1236 * by the averaging of the 8 sample rounds. Additionally the
1237 * value is shortlived. So it will be replaced by the next noise
1238 * calculation round soon. */
1239
e4d6b795 1240 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1241 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1242 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1243 noise[2] == 0x7F || noise[3] == 0x7F)
1244 goto generate_new;
1245
1246 /* Get the noise samples. */
1247 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1248 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1249 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1250 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1251 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1252 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1253 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1254 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1255 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1256 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1257 dev->noisecalc.nr_samples++;
1258 if (dev->noisecalc.nr_samples == 8) {
1259 /* Calculate the Link Quality by the noise samples. */
1260 average = 0;
1261 for (i = 0; i < 8; i++) {
1262 for (j = 0; j < 4; j++)
1263 average += dev->noisecalc.samples[i][j];
1264 }
1265 average /= (8 * 4);
1266 average *= 125;
1267 average += 64;
1268 average /= 128;
1269 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1270 tmp = (tmp / 128) & 0x1F;
1271 if (tmp >= 8)
1272 average += 2;
1273 else
1274 average -= 25;
1275 if (tmp == 8)
1276 average -= 72;
1277 else
1278 average -= 48;
1279
1280 dev->stats.link_noise = average;
e4d6b795
MB		 1281 dev->noisecalc.calculation_running = 0;
1282 return;
1283 }
98a3b2fe 1284generate_new:
e4d6b795
MB		 1285 b43_generate_noise_sample(dev);
1286}
1287
1288static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1289{
05c914fe 1290 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1291 ///TODO: PS TBTT
1292 } else {
1293 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1294 b43_power_saving_ctl_bits(dev, 0);
1295 }
05c914fe 1296 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1297 dev->dfq_valid = 1;
e4d6b795
MB		 1298}
1299
1300static void handle_irq_atim_end(struct b43_wldev *dev)
1301{
aa6c7ae2
MB		 1302 if (dev->dfq_valid) {
1303 b43_write32(dev, B43_MMIO_MACCMD,
1304 b43_read32(dev, B43_MMIO_MACCMD)
1305 | B43_MACCMD_DFQ_VALID);
1306 dev->dfq_valid = 0;
1307 }
e4d6b795
MB		 1308}
1309
1310static void handle_irq_pmq(struct b43_wldev *dev)
1311{
1312 u32 tmp;
1313
1314 //TODO: AP mode.
1315
1316 while (1) {
1317 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1318 if (!(tmp & 0x00000008))
1319 break;
1320 }
1321 /* 16bit write is odd, but correct. */
1322 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1323}
1324
1325static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1326 const u8 *data, u16 size,
e4d6b795
MB		 1327 u16 ram_offset,
1328 u16 shm_size_offset, u8 rate)
1329{
1330 u32 i, tmp;
1331 struct b43_plcp_hdr4 plcp;
1332
1333 plcp.data = 0;
1334 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1335 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1336 ram_offset += sizeof(u32);
1337 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1338 * So leave the first two bytes of the next write blank.
1339 */
1340 tmp = (u32) (data[0]) << 16;
1341 tmp |= (u32) (data[1]) << 24;
1342 b43_ram_write(dev, ram_offset, tmp);
1343 ram_offset += sizeof(u32);
1344 for (i = 2; i < size; i += sizeof(u32)) {
1345 tmp = (u32) (data[i + 0]);
1346 if (i + 1 < size)
1347 tmp |= (u32) (data[i + 1]) << 8;
1348 if (i + 2 < size)
1349 tmp |= (u32) (data[i + 2]) << 16;
1350 if (i + 3 < size)
1351 tmp |= (u32) (data[i + 3]) << 24;
1352 b43_ram_write(dev, ram_offset + i - 2, tmp);
1353 }
1354 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1355 size + sizeof(struct b43_plcp_hdr6));
1356}
1357
5042c507
MB		 1358/* Check if the use of the antenna that ieee80211 told us to
1359 * use is possible. This will fall back to DEFAULT.
1360 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1361u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1362 u8 antenna_nr)
1363{
1364 u8 antenna_mask;
1365
1366 if (antenna_nr == 0) {
1367 /* Zero means "use default antenna". That's always OK. */
1368 return 0;
1369 }
1370
1371 /* Get the mask of available antennas. */
1372 if (dev->phy.gmode)
1373 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1374 else
1375 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1376
1377 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1378 /* This antenna is not available. Fall back to default. */
1379 return 0;
1380 }
1381
1382 return antenna_nr;
1383}
1384
5042c507
MB		 1385/* Convert a b43 antenna number value to the PHY TX control value. */
1386static u16 b43_antenna_to_phyctl(int antenna)
1387{
1388 switch (antenna) {
1389 case B43_ANTENNA0:
1390 return B43_TXH_PHY_ANT0;
1391 case B43_ANTENNA1:
1392 return B43_TXH_PHY_ANT1;
1393 case B43_ANTENNA2:
1394 return B43_TXH_PHY_ANT2;
1395 case B43_ANTENNA3:
1396 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1397 case B43_ANTENNA_AUTO0:
1398 case B43_ANTENNA_AUTO1:
5042c507
MB		 1399 return B43_TXH_PHY_ANT01AUTO;
1400 }
1401 B43_WARN_ON(1);
1402 return 0;
1403}
1404
e4d6b795
MB		 1405static void b43_write_beacon_template(struct b43_wldev *dev,
1406 u16 ram_offset,
5042c507 1407 u16 shm_size_offset)
e4d6b795 1408{
47f76ca3 1409 unsigned int i, len, variable_len;
e66fee6a
MB		 1410 const struct ieee80211_mgmt *bcn;
1411 const u8 *ie;
1412 bool tim_found = 0;
5042c507
MB		 1413 unsigned int rate;
1414 u16 ctl;
1415 int antenna;
e039fa4a 1416 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1417
e66fee6a
MB		 1418 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1419 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1420 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1421 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1422
1423 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1424 len, ram_offset, shm_size_offset, rate);
e66fee6a 1425
5042c507 1426 /* Write the PHY TX control parameters. */
0f4ac38b 1427 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1428 antenna = b43_antenna_to_phyctl(antenna);
1429 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1430 /* We can't send beacons with short preamble. Would get PHY errors. */
1431 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1432 ctl &= ~B43_TXH_PHY_ANT;
1433 ctl &= ~B43_TXH_PHY_ENC;
1434 ctl |= antenna;
1435 if (b43_is_cck_rate(rate))
1436 ctl |= B43_TXH_PHY_ENC_CCK;
1437 else
1438 ctl |= B43_TXH_PHY_ENC_OFDM;
1439 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1440
e66fee6a
MB		 1441 /* Find the position of the TIM and the DTIM_period value
1442 * and write them to SHM. */
1443 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1444 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1445 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1446 uint8_t ie_id, ie_len;
1447
1448 ie_id = ie[i];
1449 ie_len = ie[i + 1];
1450 if (ie_id == 5) {
1451 u16 tim_position;
1452 u16 dtim_period;
1453 /* This is the TIM Information Element */
1454
1455 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1456 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1457 break;
1458 /* A valid TIM is at least 4 bytes long. */
1459 if (ie_len < 4)
1460 break;
1461 tim_found = 1;
1462
1463 tim_position = sizeof(struct b43_plcp_hdr6);
1464 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1465 tim_position += i;
1466
1467 dtim_period = ie[i + 3];
1468
1469 b43_shm_write16(dev, B43_SHM_SHARED,
1470 B43_SHM_SH_TIMBPOS, tim_position);
1471 b43_shm_write16(dev, B43_SHM_SHARED,
1472 B43_SHM_SH_DTIMPER, dtim_period);
1473 break;
1474 }
1475 i += ie_len + 2;
1476 }
1477 if (!tim_found) {
04dea136
JB		 1478 /*
1479 * If ucode wants to modify TIM do it behind the beacon, this
1480 * will happen, for example, when doing mesh networking.
1481 */
1482 b43_shm_write16(dev, B43_SHM_SHARED,
1483 B43_SHM_SH_TIMBPOS,
1484 len + sizeof(struct b43_plcp_hdr6));
1485 b43_shm_write16(dev, B43_SHM_SHARED,
1486 B43_SHM_SH_DTIMPER, 0);
1487 }
1488 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1489}
1490
6b4bec01
MB		 1491static void b43_upload_beacon0(struct b43_wldev *dev)
1492{
1493 struct b43_wl *wl = dev->wl;
1494
1495 if (wl->beacon0_uploaded)
1496 return;
1497 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1498 wl->beacon0_uploaded = 1;
1499}
1500
1501static void b43_upload_beacon1(struct b43_wldev *dev)
1502{
1503 struct b43_wl *wl = dev->wl;
1504
1505 if (wl->beacon1_uploaded)
1506 return;
1507 b43_write_beacon_template(dev, 0x468, 0x1A);
1508 wl->beacon1_uploaded = 1;
1509}
1510
c97a4ccc
MB		 1511static void handle_irq_beacon(struct b43_wldev *dev)
1512{
1513 struct b43_wl *wl = dev->wl;
1514 u32 cmd, beacon0_valid, beacon1_valid;
1515
05c914fe
JB		 1516 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1517 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1518 return;
1519
1520 /* This is the bottom half of the asynchronous beacon update. */
1521
1522 /* Ignore interrupt in the future. */
13790728 1523 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1524
1525 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1526 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1527 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1528
1529 /* Schedule interrupt manually, if busy. */
1530 if (beacon0_valid && beacon1_valid) {
1531 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1532 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1533 return;
1534 }
1535
6b4bec01
MB		 1536 if (unlikely(wl->beacon_templates_virgin)) {
1537 /* We never uploaded a beacon before.
1538 * Upload both templates now, but only mark one valid. */
1539 wl->beacon_templates_virgin = 0;
1540 b43_upload_beacon0(dev);
1541 b43_upload_beacon1(dev);
c97a4ccc
MB		 1542 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1543 cmd |= B43_MACCMD_BEACON0_VALID;
1544 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1545 } else {
1546 if (!beacon0_valid) {
1547 b43_upload_beacon0(dev);
1548 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1549 cmd |= B43_MACCMD_BEACON0_VALID;
1550 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1551 } else if (!beacon1_valid) {
1552 b43_upload_beacon1(dev);
1553 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1554 cmd |= B43_MACCMD_BEACON1_VALID;
1555 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1556 }
c97a4ccc
MB		 1557 }
1558}
1559
36dbd954
MB		 1560static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1561{
1562 u32 old_irq_mask = dev->irq_mask;
1563
1564 /* update beacon right away or defer to irq */
1565 handle_irq_beacon(dev);
1566 if (old_irq_mask != dev->irq_mask) {
1567 /* The handler updated the IRQ mask. */
1568 B43_WARN_ON(!dev->irq_mask);
1569 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1570 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1571 } else {
1572 /* Device interrupts are currently disabled. That means
1573 * we just ran the hardirq handler and scheduled the
1574 * IRQ thread. The thread will write the IRQ mask when
1575 * it finished, so there's nothing to do here. Writing
1576 * the mask _here_ would incorrectly re-enable IRQs. */
1577 }
1578 }
1579}
1580
a82d9922
MB		 1581static void b43_beacon_update_trigger_work(struct work_struct *work)
1582{
1583 struct b43_wl *wl = container_of(work, struct b43_wl,
1584 beacon_update_trigger);
1585 struct b43_wldev *dev;
1586
1587 mutex_lock(&wl->mutex);
1588 dev = wl->current_dev;
1589 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
36dbd954
MB		 1590 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
1591 /* wl->mutex is enough. */
1592 b43_do_beacon_update_trigger_work(dev);
1593 mmiowb();
1594 } else {
1595 spin_lock_irq(&wl->hardirq_lock);
1596 b43_do_beacon_update_trigger_work(dev);
1597 mmiowb();
1598 spin_unlock_irq(&wl->hardirq_lock);
1599 }
a82d9922
MB		 1600 }
1601 mutex_unlock(&wl->mutex);
1602}
1603
d4df6f1a 1604/* Asynchronously update the packet templates in template RAM.
36dbd954 1605 * Locking: Requires wl->mutex to be locked. */
9d139c81 1606static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1607{
9d139c81
JB		 1608 struct sk_buff *beacon;
1609
e66fee6a
MB		 1610 /* This is the top half of the ansynchronous beacon update.
1611 * The bottom half is the beacon IRQ.
1612 * Beacon update must be asynchronous to avoid sending an
1613 * invalid beacon. This can happen for example, if the firmware
1614 * transmits a beacon while we are updating it. */
e4d6b795 1615
9d139c81
JB		 1616 /* We could modify the existing beacon and set the aid bit in
1617 * the TIM field, but that would probably require resizing and
1618 * moving of data within the beacon template.
1619 * Simply request a new beacon and let mac80211 do the hard work. */
1620 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1621 if (unlikely(!beacon))
1622 return;
1623
e66fee6a
MB		 1624 if (wl->current_beacon)
1625 dev_kfree_skb_any(wl->current_beacon);
1626 wl->current_beacon = beacon;
1627 wl->beacon0_uploaded = 0;
1628 wl->beacon1_uploaded = 0;
42935eca 1629 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1630}
1631
e4d6b795
MB		 1632static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1633{
1634 b43_time_lock(dev);
1635 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1636 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1637 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1638 } else {
1639 b43_write16(dev, 0x606, (beacon_int >> 6));
1640 b43_write16(dev, 0x610, beacon_int);
1641 }
1642 b43_time_unlock(dev);
a82d9922 1643 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1644}
1645
afa83e23
MB		 1646static void b43_handle_firmware_panic(struct b43_wldev *dev)
1647{
1648 u16 reason;
1649
1650 /* Read the register that contains the reason code for the panic. */
1651 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1652 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1653
1654 switch (reason) {
1655 default:
1656 b43dbg(dev->wl, "The panic reason is unknown.\n");
1657 /* fallthrough */
1658 case B43_FWPANIC_DIE:
1659 /* Do not restart the controller or firmware.
1660 * The device is nonfunctional from now on.
1661 * Restarting would result in this panic to trigger again,
1662 * so we avoid that recursion. */
1663 break;
1664 case B43_FWPANIC_RESTART:
1665 b43_controller_restart(dev, "Microcode panic");
1666 break;
1667 }
1668}
1669
e4d6b795
MB		 1670static void handle_irq_ucode_debug(struct b43_wldev *dev)
1671{
e48b0eeb 1672 unsigned int i, cnt;
53c06856 1673 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1674 __le16 *buf;
1675
1676 /* The proprietary firmware doesn't have this IRQ. */
1677 if (!dev->fw.opensource)
1678 return;
1679
afa83e23
MB		 1680 /* Read the register that contains the reason code for this IRQ. */
1681 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1682
e48b0eeb
MB		 1683 switch (reason) {
1684 case B43_DEBUGIRQ_PANIC:
afa83e23 1685 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1686 break;
1687 case B43_DEBUGIRQ_DUMP_SHM:
1688 if (!B43_DEBUG)
1689 break; /* Only with driver debugging enabled. */
1690 buf = kmalloc(4096, GFP_ATOMIC);
1691 if (!buf) {
1692 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1693 goto out;
1694 }
1695 for (i = 0; i < 4096; i += 2) {
1696 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1697 buf[i / 2] = cpu_to_le16(tmp);
1698 }
1699 b43info(dev->wl, "Shared memory dump:\n");
1700 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1701 16, 2, buf, 4096, 1);
1702 kfree(buf);
1703 break;
1704 case B43_DEBUGIRQ_DUMP_REGS:
1705 if (!B43_DEBUG)
1706 break; /* Only with driver debugging enabled. */
1707 b43info(dev->wl, "Microcode register dump:\n");
1708 for (i = 0, cnt = 0; i < 64; i++) {
1709 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1710 if (cnt == 0)
1711 printk(KERN_INFO);
1712 printk("r%02u: 0x%04X ", i, tmp);
1713 cnt++;
1714 if (cnt == 6) {
1715 printk("\n");
1716 cnt = 0;
1717 }
1718 }
1719 printk("\n");
1720 break;
53c06856
MB		 1721 case B43_DEBUGIRQ_MARKER:
1722 if (!B43_DEBUG)
1723 break; /* Only with driver debugging enabled. */
1724 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1725 B43_MARKER_ID_REG);
1726 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1727 B43_MARKER_LINE_REG);
1728 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1729 "at line number %u\n",
1730 marker_id, marker_line);
1731 break;
e48b0eeb
MB		 1732 default:
1733 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1734 reason);
1735 }
1736out:
afa83e23
MB		 1737 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1738 b43_shm_write16(dev, B43_SHM_SCRATCH,
1739 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1740}
1741
36dbd954 1742static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1743{
1744 u32 reason;
1745 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1746 u32 merged_dma_reason = 0;
21954c36 1747 int i;
e4d6b795 1748
36dbd954
MB		 1749 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1750 return;
e4d6b795
MB		 1751
1752 reason = dev->irq_reason;
1753 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1754 dma_reason[i] = dev->dma_reason[i];
1755 merged_dma_reason |= dma_reason[i];
1756 }
1757
1758 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1759 b43err(dev->wl, "MAC transmission error\n");
1760
00e0b8cb 1761 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1762 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1763 rmb();
1764 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1765 atomic_set(&dev->phy.txerr_cnt,
1766 B43_PHY_TX_BADNESS_LIMIT);
1767 b43err(dev->wl, "Too many PHY TX errors, "
1768 "restarting the controller\n");
1769 b43_controller_restart(dev, "PHY TX errors");
1770 }
1771 }
e4d6b795
MB		 1772
1773 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1774 B43_DMAIRQ_NONFATALMASK))) {
1775 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1776 b43err(dev->wl, "Fatal DMA error: "
1777 "0x%08X, 0x%08X, 0x%08X, "
1778 "0x%08X, 0x%08X, 0x%08X\n",
1779 dma_reason[0], dma_reason[1],
1780 dma_reason[2], dma_reason[3],
1781 dma_reason[4], dma_reason[5]);
1782 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1783 return;
1784 }
1785 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1786 b43err(dev->wl, "DMA error: "
1787 "0x%08X, 0x%08X, 0x%08X, "
1788 "0x%08X, 0x%08X, 0x%08X\n",
1789 dma_reason[0], dma_reason[1],
1790 dma_reason[2], dma_reason[3],
1791 dma_reason[4], dma_reason[5]);
1792 }
1793 }
1794
1795 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1796 handle_irq_ucode_debug(dev);
1797 if (reason & B43_IRQ_TBTT_INDI)
1798 handle_irq_tbtt_indication(dev);
1799 if (reason & B43_IRQ_ATIM_END)
1800 handle_irq_atim_end(dev);
1801 if (reason & B43_IRQ_BEACON)
1802 handle_irq_beacon(dev);
1803 if (reason & B43_IRQ_PMQ)
1804 handle_irq_pmq(dev);
21954c36
MB		 1805 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1806 ;/* TODO */
1807 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1808 handle_irq_noise(dev);
1809
1810 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1811 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1812 if (b43_using_pio_transfers(dev))
1813 b43_pio_rx(dev->pio.rx_queue);
1814 else
1815 b43_dma_rx(dev->dma.rx_ring);
1816 }
e4d6b795
MB		 1817 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1818 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1819 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1820 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1821 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1822
21954c36 1823 if (reason & B43_IRQ_TX_OK)
e4d6b795 1824 handle_irq_transmit_status(dev);
e4d6b795 1825
36dbd954 1826 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1827 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1828}
1829
36dbd954
MB		 1830/* Interrupt thread handler. Handles device interrupts in thread context. */
1831static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1832{
36dbd954 1833 struct b43_wldev *dev = dev_id;
e4d6b795 1834
36dbd954
MB		 1835 mutex_lock(&dev->wl->mutex);
1836 b43_do_interrupt_thread(dev);
1837 mmiowb();
1838 mutex_unlock(&dev->wl->mutex);
1839
1840 return IRQ_HANDLED;
e4d6b795
MB		 1841}
1842
36dbd954 1843static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1844{
e4d6b795
MB		 1845 u32 reason;
1846
36dbd954
MB		 1847 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1848 * On SDIO, this runs under wl->mutex. */
e4d6b795 1849
e4d6b795
MB		 1850 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1851 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1852 return IRQ_NONE;
13790728 1853 reason &= dev->irq_mask;
e4d6b795 1854 if (!reason)
36dbd954 1855 return IRQ_HANDLED;
e4d6b795
MB		 1856
1857 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1858 & 0x0001DC00;
1859 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1860 & 0x0000DC00;
1861 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1862 & 0x0000DC00;
1863 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1864 & 0x0001DC00;
1865 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1866 & 0x0000DC00;
13790728 1867/* Unused ring
e4d6b795
MB		 1868 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1869 & 0x0000DC00;
13790728 1870*/
e4d6b795 1871
36dbd954
MB		 1872 /* ACK the interrupt. */
1873 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1874 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1875 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1876 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1877 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1878 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1879/* Unused ring
1880 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1881*/
1882
1883 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 1884 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 1885 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 1886 dev->irq_reason = reason;
36dbd954
MB		 1887
1888 return IRQ_WAKE_THREAD;
1889}
1890
1891/* Interrupt handler top-half. This runs with interrupts disabled. */
1892static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1893{
1894 struct b43_wldev *dev = dev_id;
1895 irqreturn_t ret;
1896
1897 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1898 return IRQ_NONE;
1899
1900 spin_lock(&dev->wl->hardirq_lock);
1901 ret = b43_do_interrupt(dev);
e4d6b795 1902 mmiowb();
36dbd954 1903 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 1904
1905 return ret;
1906}
1907
1a9f5093 1908void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1909{
1910 release_firmware(fw->data);
1911 fw->data = NULL;
1912 fw->filename = NULL;
1913}
1914
e4d6b795
MB		 1915static void b43_release_firmware(struct b43_wldev *dev)
1916{
1a9f5093
MB		 1917 b43_do_release_fw(&dev->fw.ucode);
1918 b43_do_release_fw(&dev->fw.pcm);
1919 b43_do_release_fw(&dev->fw.initvals);
1920 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1921}
1922
eb189d8b 1923static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1924{
fc68ed4f
HE		 1925 const char text[] =
1926 "You must go to " \
1927 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1928 "and download the correct firmware for this driver version. " \
1929 "Please carefully read all instructions on this website.\n";
eb189d8b 1930
eb189d8b
MB		 1931 if (error)
1932 b43err(wl, text);
1933 else
1934 b43warn(wl, text);
e4d6b795
MB		 1935}
1936
1a9f5093
MB		 1937int b43_do_request_fw(struct b43_request_fw_context *ctx,
1938 const char *name,
1939 struct b43_firmware_file *fw)
e4d6b795 1940{
61cb5dd6 1941 const struct firmware *blob;
e4d6b795
MB		 1942 struct b43_fw_header *hdr;
1943 u32 size;
1944 int err;
1945
61cb5dd6
MB		 1946 if (!name) {
1947 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1948 /* FIXME: We should probably keep it anyway, to save some headache
1949 * on suspend/resume with multiband devices. */
1950 b43_do_release_fw(fw);
e4d6b795 1951 return 0;
61cb5dd6
MB		 1952 }
1953 if (fw->filename) {
1a9f5093
MB		 1954 if ((fw->type == ctx->req_type) &&
1955 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1956 return 0; /* Already have this fw. */
1957 /* Free the cached firmware first. */
1a9f5093
MB		 1958 /* FIXME: We should probably do this later after we successfully
1959 * got the new fw. This could reduce headache with multiband devices.
1960 * We could also redesign this to cache the firmware for all possible
1961 * bands all the time. */
1962 b43_do_release_fw(fw);
61cb5dd6 1963 }
e4d6b795 1964
1a9f5093
MB		 1965 switch (ctx->req_type) {
1966 case B43_FWTYPE_PROPRIETARY:
1967 snprintf(ctx->fwname, sizeof(ctx->fwname),
1968 "b43%s/%s.fw",
1969 modparam_fwpostfix, name);
1970 break;
1971 case B43_FWTYPE_OPENSOURCE:
1972 snprintf(ctx->fwname, sizeof(ctx->fwname),
1973 "b43-open%s/%s.fw",
1974 modparam_fwpostfix, name);
1975 break;
1976 default:
1977 B43_WARN_ON(1);
1978 return -ENOSYS;
1979 }
1980 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 1981 if (err == -ENOENT) {
1a9f5093
MB		 1982 snprintf(ctx->errors[ctx->req_type],
1983 sizeof(ctx->errors[ctx->req_type]),
1984 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 1985 return err;
1986 } else if (err) {
1a9f5093
MB		 1987 snprintf(ctx->errors[ctx->req_type],
1988 sizeof(ctx->errors[ctx->req_type]),
1989 "Firmware file \"%s\" request failed (err=%d)\n",
1990 ctx->fwname, err);
e4d6b795
MB		 1991 return err;
1992 }
61cb5dd6 1993 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 1994 goto err_format;
61cb5dd6 1995 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 1996 switch (hdr->type) {
1997 case B43_FW_TYPE_UCODE:
1998 case B43_FW_TYPE_PCM:
1999 size = be32_to_cpu(hdr->size);
61cb5dd6 2000 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2001 goto err_format;
2002 /* fallthrough */
2003 case B43_FW_TYPE_IV:
2004 if (hdr->ver != 1)
2005 goto err_format;
2006 break;
2007 default:
2008 goto err_format;
2009 }
2010
61cb5dd6
MB		 2011 fw->data = blob;
2012 fw->filename = name;
1a9f5093 2013 fw->type = ctx->req_type;
61cb5dd6
MB		 2014
2015 return 0;
e4d6b795
MB		 2016
2017err_format:
1a9f5093
MB		 2018 snprintf(ctx->errors[ctx->req_type],
2019 sizeof(ctx->errors[ctx->req_type]),
2020 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2021 release_firmware(blob);
2022
e4d6b795
MB		 2023 return -EPROTO;
2024}
2025
1a9f5093 2026static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2027{
1a9f5093
MB		 2028 struct b43_wldev *dev = ctx->dev;
2029 struct b43_firmware *fw = &ctx->dev->fw;
2030 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2031 const char *filename;
2032 u32 tmshigh;
2033 int err;
2034
61cb5dd6 2035 /* Get microcode */
e4d6b795 2036 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2037 if ((rev >= 5) && (rev <= 10))
2038 filename = "ucode5";
2039 else if ((rev >= 11) && (rev <= 12))
2040 filename = "ucode11";
759b973b 2041 else if (rev == 13)
61cb5dd6 2042 filename = "ucode13";
759b973b
GS		 2043 else if (rev == 14)
2044 filename = "ucode14";
2045 else if (rev >= 15)
2046 filename = "ucode15";
61cb5dd6
MB		 2047 else
2048 goto err_no_ucode;
1a9f5093 2049 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2050 if (err)
2051 goto err_load;
2052
2053 /* Get PCM code */
2054 if ((rev >= 5) && (rev <= 10))
2055 filename = "pcm5";
2056 else if (rev >= 11)
2057 filename = NULL;
2058 else
2059 goto err_no_pcm;
68217832 2060 fw->pcm_request_failed = 0;
1a9f5093 2061 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2062 if (err == -ENOENT) {
2063 /* We did not find a PCM file? Not fatal, but
2064 * core rev <= 10 must do without hwcrypto then. */
2065 fw->pcm_request_failed = 1;
2066 } else if (err)
61cb5dd6
MB		 2067 goto err_load;
2068
2069 /* Get initvals */
2070 switch (dev->phy.type) {
2071 case B43_PHYTYPE_A:
2072 if ((rev >= 5) && (rev <= 10)) {
2073 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2074 filename = "a0g1initvals5";
2075 else
2076 filename = "a0g0initvals5";
2077 } else
2078 goto err_no_initvals;
2079 break;
2080 case B43_PHYTYPE_G:
e4d6b795 2081 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2082 filename = "b0g0initvals5";
e4d6b795 2083 else if (rev >= 13)
e9304882 2084 filename = "b0g0initvals13";
e4d6b795 2085 else
61cb5dd6
MB		 2086 goto err_no_initvals;
2087 break;
2088 case B43_PHYTYPE_N:
2089 if ((rev >= 11) && (rev <= 12))
2090 filename = "n0initvals11";
2091 else
2092 goto err_no_initvals;
2093 break;
759b973b
GS		 2094 case B43_PHYTYPE_LP:
2095 if (rev == 13)
2096 filename = "lp0initvals13";
2097 else if (rev == 14)
2098 filename = "lp0initvals14";
2099 else if (rev >= 15)
2100 filename = "lp0initvals15";
2101 else
2102 goto err_no_initvals;
2103 break;
61cb5dd6
MB		 2104 default:
2105 goto err_no_initvals;
e4d6b795 2106 }
1a9f5093 2107 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2108 if (err)
2109 goto err_load;
2110
2111 /* Get bandswitch initvals */
2112 switch (dev->phy.type) {
2113 case B43_PHYTYPE_A:
2114 if ((rev >= 5) && (rev <= 10)) {
2115 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2116 filename = "a0g1bsinitvals5";
2117 else
2118 filename = "a0g0bsinitvals5";
2119 } else if (rev >= 11)
2120 filename = NULL;
2121 else
2122 goto err_no_initvals;
2123 break;
2124 case B43_PHYTYPE_G:
e4d6b795 2125 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2126 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2127 else if (rev >= 11)
2128 filename = NULL;
2129 else
e4d6b795 2130 goto err_no_initvals;
61cb5dd6
MB		 2131 break;
2132 case B43_PHYTYPE_N:
2133 if ((rev >= 11) && (rev <= 12))
2134 filename = "n0bsinitvals11";
2135 else
e4d6b795 2136 goto err_no_initvals;
61cb5dd6 2137 break;
759b973b
GS		 2138 case B43_PHYTYPE_LP:
2139 if (rev == 13)
2140 filename = "lp0bsinitvals13";
2141 else if (rev == 14)
2142 filename = "lp0bsinitvals14";
2143 else if (rev >= 15)
2144 filename = "lp0bsinitvals15";
2145 else
2146 goto err_no_initvals;
2147 break;
61cb5dd6
MB		 2148 default:
2149 goto err_no_initvals;
e4d6b795 2150 }
1a9f5093 2151 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2152 if (err)
2153 goto err_load;
e4d6b795
MB		 2154
2155 return 0;
2156
e4d6b795 2157err_no_ucode:
1a9f5093
MB		 2158 err = ctx->fatal_failure = -EOPNOTSUPP;
2159 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2160 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2161 goto error;
2162
2163err_no_pcm:
1a9f5093
MB		 2164 err = ctx->fatal_failure = -EOPNOTSUPP;
2165 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2166 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2167 goto error;
2168
2169err_no_initvals:
1a9f5093
MB		 2170 err = ctx->fatal_failure = -EOPNOTSUPP;
2171 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2172 "is required for your device (wl-core rev %u)\n", rev);
2173 goto error;
2174
2175err_load:
2176 /* We failed to load this firmware image. The error message
2177 * already is in ctx->errors. Return and let our caller decide
2178 * what to do. */
e4d6b795
MB		 2179 goto error;
2180
2181error:
2182 b43_release_firmware(dev);
2183 return err;
2184}
2185
1a9f5093
MB		 2186static int b43_request_firmware(struct b43_wldev *dev)
2187{
2188 struct b43_request_fw_context *ctx;
2189 unsigned int i;
2190 int err;
2191 const char *errmsg;
2192
2193 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2194 if (!ctx)
2195 return -ENOMEM;
2196 ctx->dev = dev;
2197
2198 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2199 err = b43_try_request_fw(ctx);
2200 if (!err)
2201 goto out; /* Successfully loaded it. */
2202 err = ctx->fatal_failure;
2203 if (err)
2204 goto out;
2205
2206 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2207 err = b43_try_request_fw(ctx);
2208 if (!err)
2209 goto out; /* Successfully loaded it. */
2210 err = ctx->fatal_failure;
2211 if (err)
2212 goto out;
2213
2214 /* Could not find a usable firmware. Print the errors. */
2215 for (i = 0; i < B43_NR_FWTYPES; i++) {
2216 errmsg = ctx->errors[i];
2217 if (strlen(errmsg))
2218 b43err(dev->wl, errmsg);
2219 }
2220 b43_print_fw_helptext(dev->wl, 1);
2221 err = -ENOENT;
2222
2223out:
2224 kfree(ctx);
2225 return err;
2226}
2227
e4d6b795
MB		 2228static int b43_upload_microcode(struct b43_wldev *dev)
2229{
2230 const size_t hdr_len = sizeof(struct b43_fw_header);
2231 const __be32 *data;
2232 unsigned int i, len;
2233 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2234 u32 tmp, macctl;
e4d6b795
MB		 2235 int err = 0;
2236
1f7d87b0
MB		 2237 /* Jump the microcode PSM to offset 0 */
2238 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2239 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2240 macctl |= B43_MACCTL_PSM_JMP0;
2241 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2242 /* Zero out all microcode PSM registers and shared memory. */
2243 for (i = 0; i < 64; i++)
2244 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2245 for (i = 0; i < 4096; i += 2)
2246 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2247
e4d6b795 2248 /* Upload Microcode. */
61cb5dd6
MB		 2249 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2250 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2251 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2252 for (i = 0; i < len; i++) {
2253 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2254 udelay(10);
2255 }
2256
61cb5dd6 2257 if (dev->fw.pcm.data) {
e4d6b795 2258 /* Upload PCM data. */
61cb5dd6
MB		 2259 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2260 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2261 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2262 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2263 /* No need for autoinc bit in SHM_HW */
2264 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2265 for (i = 0; i < len; i++) {
2266 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2267 udelay(10);
2268 }
2269 }
2270
2271 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2272
2273 /* Start the microcode PSM */
2274 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2275 macctl &= ~B43_MACCTL_PSM_JMP0;
2276 macctl |= B43_MACCTL_PSM_RUN;
2277 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2278
2279 /* Wait for the microcode to load and respond */
2280 i = 0;
2281 while (1) {
2282 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2283 if (tmp == B43_IRQ_MAC_SUSPENDED)
2284 break;
2285 i++;
1f7d87b0 2286 if (i >= 20) {
e4d6b795 2287 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2288 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2289 err = -ENODEV;
1f7d87b0
MB		 2290 goto error;
2291 }
91d372c0 2292 msleep(50);
e4d6b795
MB		 2293 }
2294 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2295
2296 /* Get and check the revisions. */
2297 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2298 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2299 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2300 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2301
2302 if (fwrev <= 0x128) {
2303 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2304 "binary drivers older than version 4.x is unsupported. "
2305 "You must upgrade your firmware files.\n");
eb189d8b 2306 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2307 err = -EOPNOTSUPP;
1f7d87b0 2308 goto error;
e4d6b795 2309 }
e4d6b795
MB		 2310 dev->fw.rev = fwrev;
2311 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2312 dev->fw.opensource = (fwdate == 0xFFFF);
2313
403a3a13
MB		 2314 /* Default to use-all-queues. */
2315 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2316 dev->qos_enabled = !!modparam_qos;
2317 /* Default to firmware/hardware crypto acceleration. */
2318 dev->hwcrypto_enabled = 1;
2319
e48b0eeb 2320 if (dev->fw.opensource) {
403a3a13
MB		 2321 u16 fwcapa;
2322
e48b0eeb
MB		 2323 /* Patchlevel info is encoded in the "time" field. */
2324 dev->fw.patch = fwtime;
403a3a13
MB		 2325 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2326 dev->fw.rev, dev->fw.patch);
2327
2328 fwcapa = b43_fwcapa_read(dev);
2329 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2330 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2331 /* Disable hardware crypto and fall back to software crypto. */
2332 dev->hwcrypto_enabled = 0;
2333 }
2334 if (!(fwcapa & B43_FWCAPA_QOS)) {
2335 b43info(dev->wl, "QoS not supported by firmware\n");
2336 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2337 * ieee80211_unregister to make sure the networking core can
2338 * properly free possible resources. */
2339 dev->wl->hw->queues = 1;
2340 dev->qos_enabled = 0;
2341 }
e48b0eeb
MB		 2342 } else {
2343 b43info(dev->wl, "Loading firmware version %u.%u "
2344 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2345 fwrev, fwpatch,
2346 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2347 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2348 if (dev->fw.pcm_request_failed) {
2349 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2350 "Hardware accelerated cryptography is disabled.\n");
2351 b43_print_fw_helptext(dev->wl, 0);
2352 }
e48b0eeb 2353 }
e4d6b795 2354
eb189d8b 2355 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2356 /* We're over the deadline, but we keep support for old fw
2357 * until it turns out to be in major conflict with something new. */
eb189d8b 2358 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2359 "Support for old firmware will be removed soon "
2360 "(official deadline was July 2008).\n");
eb189d8b
MB		 2361 b43_print_fw_helptext(dev->wl, 0);
2362 }
2363
1f7d87b0
MB		 2364 return 0;
2365
2366error:
2367 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2368 macctl &= ~B43_MACCTL_PSM_RUN;
2369 macctl |= B43_MACCTL_PSM_JMP0;
2370 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2371
e4d6b795
MB		 2372 return err;
2373}
2374
2375static int b43_write_initvals(struct b43_wldev *dev,
2376 const struct b43_iv *ivals,
2377 size_t count,
2378 size_t array_size)
2379{
2380 const struct b43_iv *iv;
2381 u16 offset;
2382 size_t i;
2383 bool bit32;
2384
2385 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2386 iv = ivals;
2387 for (i = 0; i < count; i++) {
2388 if (array_size < sizeof(iv->offset_size))
2389 goto err_format;
2390 array_size -= sizeof(iv->offset_size);
2391 offset = be16_to_cpu(iv->offset_size);
2392 bit32 = !!(offset & B43_IV_32BIT);
2393 offset &= B43_IV_OFFSET_MASK;
2394 if (offset >= 0x1000)
2395 goto err_format;
2396 if (bit32) {
2397 u32 value;
2398
2399 if (array_size < sizeof(iv->data.d32))
2400 goto err_format;
2401 array_size -= sizeof(iv->data.d32);
2402
533dd1b0 2403 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2404 b43_write32(dev, offset, value);
2405
2406 iv = (const struct b43_iv *)((const uint8_t *)iv +
2407 sizeof(__be16) +
2408 sizeof(__be32));
2409 } else {
2410 u16 value;
2411
2412 if (array_size < sizeof(iv->data.d16))
2413 goto err_format;
2414 array_size -= sizeof(iv->data.d16);
2415
2416 value = be16_to_cpu(iv->data.d16);
2417 b43_write16(dev, offset, value);
2418
2419 iv = (const struct b43_iv *)((const uint8_t *)iv +
2420 sizeof(__be16) +
2421 sizeof(__be16));
2422 }
2423 }
2424 if (array_size)
2425 goto err_format;
2426
2427 return 0;
2428
2429err_format:
2430 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2431 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2432
2433 return -EPROTO;
2434}
2435
2436static int b43_upload_initvals(struct b43_wldev *dev)
2437{
2438 const size_t hdr_len = sizeof(struct b43_fw_header);
2439 const struct b43_fw_header *hdr;
2440 struct b43_firmware *fw = &dev->fw;
2441 const struct b43_iv *ivals;
2442 size_t count;
2443 int err;
2444
61cb5dd6
MB		 2445 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2446 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2447 count = be32_to_cpu(hdr->size);
2448 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2449 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2450 if (err)
2451 goto out;
61cb5dd6
MB		 2452 if (fw->initvals_band.data) {
2453 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2454 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2455 count = be32_to_cpu(hdr->size);
2456 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2457 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2458 if (err)
2459 goto out;
2460 }
2461out:
2462
2463 return err;
2464}
2465
2466/* Initialize the GPIOs
2467 * http://bcm-specs.sipsolutions.net/GPIO
2468 */
2469static int b43_gpio_init(struct b43_wldev *dev)
2470{
2471 struct ssb_bus *bus = dev->dev->bus;
2472 struct ssb_device *gpiodev, *pcidev = NULL;
2473 u32 mask, set;
2474
2475 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2476 & ~B43_MACCTL_GPOUTSMSK);
2477
e4d6b795
MB		 2478 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2479 | 0x000F);
2480
2481 mask = 0x0000001F;
2482 set = 0x0000000F;
2483 if (dev->dev->bus->chip_id == 0x4301) {
2484 mask |= 0x0060;
2485 set |= 0x0060;
2486 }
2487 if (0 /* FIXME: conditional unknown */ ) {
2488 b43_write16(dev, B43_MMIO_GPIO_MASK,
2489 b43_read16(dev, B43_MMIO_GPIO_MASK)
2490 | 0x0100);
2491 mask |= 0x0180;
2492 set |= 0x0180;
2493 }
95de2841 2494 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2495 b43_write16(dev, B43_MMIO_GPIO_MASK,
2496 b43_read16(dev, B43_MMIO_GPIO_MASK)
2497 | 0x0200);
2498 mask |= 0x0200;
2499 set |= 0x0200;
2500 }
2501 if (dev->dev->id.revision >= 2)
2502 mask |= 0x0010; /* FIXME: This is redundant. */
2503
2504#ifdef CONFIG_SSB_DRIVER_PCICORE
2505 pcidev = bus->pcicore.dev;
2506#endif
2507 gpiodev = bus->chipco.dev ? : pcidev;
2508 if (!gpiodev)
2509 return 0;
2510 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2511 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2512 & mask) | set);
2513
2514 return 0;
2515}
2516
2517/* Turn off all GPIO stuff. Call this on module unload, for example. */
2518static void b43_gpio_cleanup(struct b43_wldev *dev)
2519{
2520 struct ssb_bus *bus = dev->dev->bus;
2521 struct ssb_device *gpiodev, *pcidev = NULL;
2522
2523#ifdef CONFIG_SSB_DRIVER_PCICORE
2524 pcidev = bus->pcicore.dev;
2525#endif
2526 gpiodev = bus->chipco.dev ? : pcidev;
2527 if (!gpiodev)
2528 return;
2529 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2530}
2531
2532/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2533void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2534{
923fd703
MB		 2535 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2536 u16 fwstate;
2537
2538 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2539 B43_SHM_SH_UCODESTAT);
2540 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2541 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2542 b43err(dev->wl, "b43_mac_enable(): The firmware "
2543 "should be suspended, but current state is %u\n",
2544 fwstate);
2545 }
2546 }
2547
e4d6b795
MB		 2548 dev->mac_suspended--;
2549 B43_WARN_ON(dev->mac_suspended < 0);
2550 if (dev->mac_suspended == 0) {
2551 b43_write32(dev, B43_MMIO_MACCTL,
2552 b43_read32(dev, B43_MMIO_MACCTL)
2553 | B43_MACCTL_ENABLED);
2554 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2555 B43_IRQ_MAC_SUSPENDED);
2556 /* Commit writes */
2557 b43_read32(dev, B43_MMIO_MACCTL);
2558 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2559 b43_power_saving_ctl_bits(dev, 0);
2560 }
2561}
2562
2563/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2564void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2565{
2566 int i;
2567 u32 tmp;
2568
05b64b36 2569 might_sleep();
e4d6b795 2570 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2571
e4d6b795
MB		 2572 if (dev->mac_suspended == 0) {
2573 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2574 b43_write32(dev, B43_MMIO_MACCTL,
2575 b43_read32(dev, B43_MMIO_MACCTL)
2576 & ~B43_MACCTL_ENABLED);
2577 /* force pci to flush the write */
2578 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2579 for (i = 35; i; i--) {
2580 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2581 if (tmp & B43_IRQ_MAC_SUSPENDED)
2582 goto out;
2583 udelay(10);
2584 }
2585 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2586 for (i = 40; i; i--) {
e4d6b795
MB		 2587 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2588 if (tmp & B43_IRQ_MAC_SUSPENDED)
2589 goto out;
05b64b36 2590 msleep(1);
e4d6b795
MB		 2591 }
2592 b43err(dev->wl, "MAC suspend failed\n");
2593 }
05b64b36 2594out:
e4d6b795
MB		 2595 dev->mac_suspended++;
2596}
2597
2598static void b43_adjust_opmode(struct b43_wldev *dev)
2599{
2600 struct b43_wl *wl = dev->wl;
2601 u32 ctl;
2602 u16 cfp_pretbtt;
2603
2604 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2605 /* Reset status to STA infrastructure mode. */
2606 ctl &= ~B43_MACCTL_AP;
2607 ctl &= ~B43_MACCTL_KEEP_CTL;
2608 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2609 ctl &= ~B43_MACCTL_KEEP_BAD;
2610 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2611 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2612 ctl |= B43_MACCTL_INFRA;
2613
05c914fe
JB		 2614 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2615 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2616 ctl |= B43_MACCTL_AP;
05c914fe 2617 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2618 ctl &= ~B43_MACCTL_INFRA;
2619
2620 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2621 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2622 if (wl->filter_flags & FIF_FCSFAIL)
2623 ctl |= B43_MACCTL_KEEP_BAD;
2624 if (wl->filter_flags & FIF_PLCPFAIL)
2625 ctl |= B43_MACCTL_KEEP_BADPLCP;
2626 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2627 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2628 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2629 ctl |= B43_MACCTL_BEACPROMISC;
2630
e4d6b795
MB		 2631 /* Workaround: On old hardware the HW-MAC-address-filter
2632 * doesn't work properly, so always run promisc in filter
2633 * it in software. */
2634 if (dev->dev->id.revision <= 4)
2635 ctl |= B43_MACCTL_PROMISC;
2636
2637 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2638
2639 cfp_pretbtt = 2;
2640 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2641 if (dev->dev->bus->chip_id == 0x4306 &&
2642 dev->dev->bus->chip_rev == 3)
2643 cfp_pretbtt = 100;
2644 else
2645 cfp_pretbtt = 50;
2646 }
2647 b43_write16(dev, 0x612, cfp_pretbtt);
2648}
2649
2650static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2651{
2652 u16 offset;
2653
2654 if (is_ofdm) {
2655 offset = 0x480;
2656 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2657 } else {
2658 offset = 0x4C0;
2659 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2660 }
2661 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2662 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2663}
2664
2665static void b43_rate_memory_init(struct b43_wldev *dev)
2666{
2667 switch (dev->phy.type) {
2668 case B43_PHYTYPE_A:
2669 case B43_PHYTYPE_G:
53a6e234 2670 case B43_PHYTYPE_N:
9d86a2d5 2671 case B43_PHYTYPE_LP:
e4d6b795
MB		 2672 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2673 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2674 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2675 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2676 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2677 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2678 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2679 if (dev->phy.type == B43_PHYTYPE_A)
2680 break;
2681 /* fallthrough */
2682 case B43_PHYTYPE_B:
2683 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2684 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2685 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2686 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2687 break;
2688 default:
2689 B43_WARN_ON(1);
2690 }
2691}
2692
5042c507
MB		 2693/* Set the default values for the PHY TX Control Words. */
2694static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2695{
2696 u16 ctl = 0;
2697
2698 ctl |= B43_TXH_PHY_ENC_CCK;
2699 ctl |= B43_TXH_PHY_ANT01AUTO;
2700 ctl |= B43_TXH_PHY_TXPWR;
2701
2702 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2703 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2704 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2705}
2706
e4d6b795
MB		 2707/* Set the TX-Antenna for management frames sent by firmware. */
2708static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2709{
5042c507 2710 u16 ant;
e4d6b795
MB		 2711 u16 tmp;
2712
5042c507 2713 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2714
e4d6b795
MB		 2715 /* For ACK/CTS */
2716 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2717 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2718 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2719 /* For Probe Resposes */
2720 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2721 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2723}
2724
2725/* This is the opposite of b43_chip_init() */
2726static void b43_chip_exit(struct b43_wldev *dev)
2727{
fb11137a 2728 b43_phy_exit(dev);
e4d6b795
MB		 2729 b43_gpio_cleanup(dev);
2730 /* firmware is released later */
2731}
2732
2733/* Initialize the chip
2734 * http://bcm-specs.sipsolutions.net/ChipInit
2735 */
2736static int b43_chip_init(struct b43_wldev *dev)
2737{
2738 struct b43_phy *phy = &dev->phy;
ef1a628d 2739 int err;
1f7d87b0 2740 u32 value32, macctl;
e4d6b795
MB		 2741 u16 value16;
2742
1f7d87b0
MB		 2743 /* Initialize the MAC control */
2744 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2745 if (dev->phy.gmode)
2746 macctl |= B43_MACCTL_GMODE;
2747 macctl |= B43_MACCTL_INFRA;
2748 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2749
2750 err = b43_request_firmware(dev);
2751 if (err)
2752 goto out;
2753 err = b43_upload_microcode(dev);
2754 if (err)
2755 goto out; /* firmware is released later */
2756
2757 err = b43_gpio_init(dev);
2758 if (err)
2759 goto out; /* firmware is released later */
21954c36 2760
e4d6b795
MB		 2761 err = b43_upload_initvals(dev);
2762 if (err)
1a8d1227 2763 goto err_gpio_clean;
e4d6b795 2764
0b7dcd96
MB		 2765 /* Turn the Analog on and initialize the PHY. */
2766 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2767 err = b43_phy_init(dev);
2768 if (err)
ef1a628d 2769 goto err_gpio_clean;
e4d6b795 2770
ef1a628d
MB		 2771 /* Disable Interference Mitigation. */
2772 if (phy->ops->interf_mitigation)
2773 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2774
ef1a628d
MB		 2775 /* Select the antennae */
2776 if (phy->ops->set_rx_antenna)
2777 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2778 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2779
2780 if (phy->type == B43_PHYTYPE_B) {
2781 value16 = b43_read16(dev, 0x005E);
2782 value16 |= 0x0004;
2783 b43_write16(dev, 0x005E, value16);
2784 }
2785 b43_write32(dev, 0x0100, 0x01000000);
2786 if (dev->dev->id.revision < 5)
2787 b43_write32(dev, 0x010C, 0x01000000);
2788
2789 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2790 & ~B43_MACCTL_INFRA);
2791 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2792 | B43_MACCTL_INFRA);
e4d6b795 2793
e4d6b795
MB		 2794 /* Probe Response Timeout value */
2795 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2796 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2797
2798 /* Initially set the wireless operation mode. */
2799 b43_adjust_opmode(dev);
2800
2801 if (dev->dev->id.revision < 3) {
2802 b43_write16(dev, 0x060E, 0x0000);
2803 b43_write16(dev, 0x0610, 0x8000);
2804 b43_write16(dev, 0x0604, 0x0000);
2805 b43_write16(dev, 0x0606, 0x0200);
2806 } else {
2807 b43_write32(dev, 0x0188, 0x80000000);
2808 b43_write32(dev, 0x018C, 0x02000000);
2809 }
2810 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2811 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2812 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2813 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2814 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2815 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2816 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2817
2818 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2819 value32 |= 0x00100000;
2820 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2821
2822 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2823 dev->dev->bus->chipco.fast_pwrup_delay);
2824
2825 err = 0;
2826 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2827out:
e4d6b795
MB		 2828 return err;
2829
1a8d1227 2830err_gpio_clean:
e4d6b795 2831 b43_gpio_cleanup(dev);
21954c36 2832 return err;
e4d6b795
MB		 2833}
2834
e4d6b795
MB		 2835static void b43_periodic_every60sec(struct b43_wldev *dev)
2836{
ef1a628d 2837 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2838
ef1a628d
MB		 2839 if (ops->pwork_60sec)
2840 ops->pwork_60sec(dev);
18c8adeb
MB		 2841
2842 /* Force check the TX power emission now. */
2843 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2844}
2845
2846static void b43_periodic_every30sec(struct b43_wldev *dev)
2847{
2848 /* Update device statistics. */
2849 b43_calculate_link_quality(dev);
2850}
2851
2852static void b43_periodic_every15sec(struct b43_wldev *dev)
2853{
2854 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2855 u16 wdr;
2856
2857 if (dev->fw.opensource) {
2858 /* Check if the firmware is still alive.
2859 * It will reset the watchdog counter to 0 in its idle loop. */
2860 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2861 if (unlikely(wdr)) {
2862 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2863 b43_controller_restart(dev, "Firmware watchdog");
2864 return;
2865 } else {
2866 b43_shm_write16(dev, B43_SHM_SCRATCH,
2867 B43_WATCHDOG_REG, 1);
2868 }
2869 }
e4d6b795 2870
ef1a628d
MB		 2871 if (phy->ops->pwork_15sec)
2872 phy->ops->pwork_15sec(dev);
2873
00e0b8cb
SB		 2874 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2875 wmb();
e4d6b795
MB		 2876}
2877
e4d6b795
MB		 2878static void do_periodic_work(struct b43_wldev *dev)
2879{
2880 unsigned int state;
2881
2882 state = dev->periodic_state;
42bb4cd5 2883 if (state % 4 == 0)
e4d6b795 2884 b43_periodic_every60sec(dev);
42bb4cd5 2885 if (state % 2 == 0)
e4d6b795 2886 b43_periodic_every30sec(dev);
42bb4cd5 2887 b43_periodic_every15sec(dev);
e4d6b795
MB		 2888}
2889
05b64b36
MB		 2890/* Periodic work locking policy:
2891 * The whole periodic work handler is protected by
2892 * wl->mutex. If another lock is needed somewhere in the
2893 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2894 */
e4d6b795
MB		 2895static void b43_periodic_work_handler(struct work_struct *work)
2896{
05b64b36
MB		 2897 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2898 periodic_work.work);
2899 struct b43_wl *wl = dev->wl;
2900 unsigned long delay;
e4d6b795 2901
05b64b36 2902 mutex_lock(&wl->mutex);
e4d6b795
MB		 2903
2904 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2905 goto out;
2906 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2907 goto out_requeue;
2908
05b64b36 2909 do_periodic_work(dev);
e4d6b795 2910
e4d6b795 2911 dev->periodic_state++;
42bb4cd5 2912out_requeue:
e4d6b795
MB		 2913 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2914 delay = msecs_to_jiffies(50);
2915 else
82cd682d 2916 delay = round_jiffies_relative(HZ * 15);
42935eca 2917 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 2918out:
05b64b36 2919 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2920}
2921
2922static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2923{
2924 struct delayed_work *work = &dev->periodic_work;
2925
2926 dev->periodic_state = 0;
2927 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 2928 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 2929}
2930
f3dd3fcc 2931/* Check if communication with the device works correctly. */
e4d6b795
MB		 2932static int b43_validate_chipaccess(struct b43_wldev *dev)
2933{
f62ae6cd 2934 u32 v, backup0, backup4;
e4d6b795 2935
f62ae6cd
MB		 2936 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2937 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 2938
2939 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2940 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2941 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2942 goto error;
f3dd3fcc
MB		 2943 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2944 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2945 goto error;
2946
f62ae6cd
MB		 2947 /* Check if unaligned 32bit SHM_SHARED access works properly.
2948 * However, don't bail out on failure, because it's noncritical. */
2949 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
2950 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
2951 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
2952 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
2953 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
2954 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
2955 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
2956 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
2957 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
2958 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
2959 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
2960 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
2961
2962 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
2963 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 2964
2965 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2966 /* The 32bit register shadows the two 16bit registers
2967 * with update sideeffects. Validate this. */
2968 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2969 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2970 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2971 goto error;
2972 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2973 goto error;
2974 }
2975 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2976
2977 v = b43_read32(dev, B43_MMIO_MACCTL);
2978 v |= B43_MACCTL_GMODE;
2979 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2980 goto error;
2981
2982 return 0;
f3dd3fcc 2983error:
e4d6b795
MB		 2984 b43err(dev->wl, "Failed to validate the chipaccess\n");
2985 return -ENODEV;
2986}
2987
2988static void b43_security_init(struct b43_wldev *dev)
2989{
e4d6b795
MB		 2990 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2991 /* KTP is a word address, but we address SHM bytewise.
2992 * So multiply by two.
2993 */
2994 dev->ktp *= 2;
66d2d089
MB		 2995 /* Number of RCMTA address slots */
2996 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
2997 /* Clear the key memory. */
e4d6b795
MB		 2998 b43_clear_keys(dev);
2999}
3000
616de35d 3001#ifdef CONFIG_B43_HWRNG
99da185a 3002static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3003{
3004 struct b43_wl *wl = (struct b43_wl *)rng->priv;
e4d6b795 3005
36dbd954
MB		 3006 /* FIXME: We need to take wl->mutex here to make sure the device
3007 * is not going away from under our ass. However it could deadlock
3008 * with hwrng internal locking. */
e4d6b795 3009
e4d6b795 3010 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
e4d6b795
MB		 3011
3012 return (sizeof(u16));
3013}
616de35d 3014#endif /* CONFIG_B43_HWRNG */
e4d6b795 3015
b844eba2 3016static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3017{
616de35d 3018#ifdef CONFIG_B43_HWRNG
e4d6b795 3019 if (wl->rng_initialized)
b844eba2 3020 hwrng_unregister(&wl->rng);
616de35d 3021#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3022}
3023
3024static int b43_rng_init(struct b43_wl *wl)
3025{
616de35d 3026 int err = 0;
e4d6b795 3027
616de35d 3028#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3029 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3030 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3031 wl->rng.name = wl->rng_name;
3032 wl->rng.data_read = b43_rng_read;
3033 wl->rng.priv = (unsigned long)wl;
3034 wl->rng_initialized = 1;
3035 err = hwrng_register(&wl->rng);
3036 if (err) {
3037 wl->rng_initialized = 0;
3038 b43err(wl, "Failed to register the random "
3039 "number generator (%d)\n", err);
3040 }
616de35d 3041#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3042
3043 return err;
3044}
3045
f5d40eed 3046static void b43_tx_work(struct work_struct *work)
e4d6b795 3047{
f5d40eed
MB		 3048 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3049 struct b43_wldev *dev;
3050 struct sk_buff *skb;
3051 int err = 0;
e4d6b795 3052
f5d40eed
MB		 3053 mutex_lock(&wl->mutex);
3054 dev = wl->current_dev;
3055 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3056 mutex_unlock(&wl->mutex);
3057 return;
5100d5ac 3058 }
21a75d77 3059
f5d40eed
MB		 3060 while (skb_queue_len(&wl->tx_queue)) {
3061 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3062
21a75d77 3063 if (b43_using_pio_transfers(dev))
e039fa4a 3064 err = b43_pio_tx(dev, skb);
21a75d77 3065 else
e039fa4a 3066 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3067 if (unlikely(err))
3068 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3069 }
3070
f5d40eed
MB		 3071 mutex_unlock(&wl->mutex);
3072}
21a75d77 3073
f5d40eed
MB		 3074static int b43_op_tx(struct ieee80211_hw *hw,
3075 struct sk_buff *skb)
3076{
3077 struct b43_wl *wl = hw_to_b43_wl(hw);
3078
3079 if (unlikely(skb->len < 2 + 2 + 6)) {
3080 /* Too short, this can't be a valid frame. */
3081 dev_kfree_skb_any(skb);
3082 return NETDEV_TX_OK;
3083 }
3084 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3085
3086 skb_queue_tail(&wl->tx_queue, skb);
3087 ieee80211_queue_work(wl->hw, &wl->tx_work);
c9e8eae0 3088
e4d6b795
MB		 3089 return NETDEV_TX_OK;
3090}
3091
e6f5b934
MB		 3092static void b43_qos_params_upload(struct b43_wldev *dev,
3093 const struct ieee80211_tx_queue_params *p,
3094 u16 shm_offset)
3095{
3096 u16 params[B43_NR_QOSPARAMS];
0b57664c 3097 int bslots, tmp;
e6f5b934
MB		 3098 unsigned int i;
3099
b0544eb6
MB		 3100 if (!dev->qos_enabled)
3101 return;
3102
0b57664c 3103 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3104
3105 memset(&params, 0, sizeof(params));
3106
3107 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3108 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3109 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3110 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3111 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3112 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3113 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3114
3115 for (i = 0; i < ARRAY_SIZE(params); i++) {
3116 if (i == B43_QOSPARAM_STATUS) {
3117 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3118 shm_offset + (i * 2));
3119 /* Mark the parameters as updated. */
3120 tmp |= 0x100;
3121 b43_shm_write16(dev, B43_SHM_SHARED,
3122 shm_offset + (i * 2),
3123 tmp);
3124 } else {
3125 b43_shm_write16(dev, B43_SHM_SHARED,
3126 shm_offset + (i * 2),
3127 params[i]);
3128 }
3129 }
3130}
3131
c40c1129
MB		 3132/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3133static const u16 b43_qos_shm_offsets[] = {
3134 /* [mac80211-queue-nr] = SHM_OFFSET, */
3135 [0] = B43_QOS_VOICE,
3136 [1] = B43_QOS_VIDEO,
3137 [2] = B43_QOS_BESTEFFORT,
3138 [3] = B43_QOS_BACKGROUND,
3139};
3140
5a5f3b40
MB		 3141/* Update all QOS parameters in hardware. */
3142static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3143{
3144 struct b43_wl *wl = dev->wl;
3145 struct b43_qos_params *params;
e6f5b934
MB		 3146 unsigned int i;
3147
b0544eb6
MB		 3148 if (!dev->qos_enabled)
3149 return;
3150
c40c1129
MB		 3151 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3152 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3153
3154 b43_mac_suspend(dev);
e6f5b934
MB		 3155 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3156 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3157 b43_qos_params_upload(dev, &(params->p),
3158 b43_qos_shm_offsets[i]);
e6f5b934 3159 }
e6f5b934
MB		 3160 b43_mac_enable(dev);
3161}
3162
3163static void b43_qos_clear(struct b43_wl *wl)
3164{
3165 struct b43_qos_params *params;
3166 unsigned int i;
3167
c40c1129
MB		 3168 /* Initialize QoS parameters to sane defaults. */
3169
3170 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3171 ARRAY_SIZE(wl->qos_params));
3172
e6f5b934
MB		 3173 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3174 params = &(wl->qos_params[i]);
3175
c40c1129
MB		 3176 switch (b43_qos_shm_offsets[i]) {
3177 case B43_QOS_VOICE:
3178 params->p.txop = 0;
3179 params->p.aifs = 2;
3180 params->p.cw_min = 0x0001;
3181 params->p.cw_max = 0x0001;
3182 break;
3183 case B43_QOS_VIDEO:
3184 params->p.txop = 0;
3185 params->p.aifs = 2;
3186 params->p.cw_min = 0x0001;
3187 params->p.cw_max = 0x0001;
3188 break;
3189 case B43_QOS_BESTEFFORT:
3190 params->p.txop = 0;
3191 params->p.aifs = 3;
3192 params->p.cw_min = 0x0001;
3193 params->p.cw_max = 0x03FF;
3194 break;
3195 case B43_QOS_BACKGROUND:
3196 params->p.txop = 0;
3197 params->p.aifs = 7;
3198 params->p.cw_min = 0x0001;
3199 params->p.cw_max = 0x03FF;
3200 break;
3201 default:
3202 B43_WARN_ON(1);
3203 }
e6f5b934
MB		 3204 }
3205}
3206
3207/* Initialize the core's QOS capabilities */
3208static void b43_qos_init(struct b43_wldev *dev)
3209{
b0544eb6
MB		 3210 if (!dev->qos_enabled) {
3211 /* Disable QOS support. */
3212 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3213 b43_write16(dev, B43_MMIO_IFSCTL,
3214 b43_read16(dev, B43_MMIO_IFSCTL)
3215 & ~B43_MMIO_IFSCTL_USE_EDCF);
3216 b43dbg(dev->wl, "QoS disabled\n");
3217 return;
3218 }
3219
e6f5b934 3220 /* Upload the current QOS parameters. */
5a5f3b40 3221 b43_qos_upload_all(dev);
e6f5b934
MB		 3222
3223 /* Enable QOS support. */
3224 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3225 b43_write16(dev, B43_MMIO_IFSCTL,
3226 b43_read16(dev, B43_MMIO_IFSCTL)
3227 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3228 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3229}
3230
e100bb64 3231static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3232 const struct ieee80211_tx_queue_params *params)
e4d6b795 3233{
e6f5b934 3234 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3235 struct b43_wldev *dev;
e6f5b934 3236 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3237 int err = -ENODEV;
e6f5b934
MB		 3238
3239 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3240 /* Queue not available or don't support setting
3241 * params on this queue. Return success to not
3242 * confuse mac80211. */
3243 return 0;
3244 }
5a5f3b40
MB		 3245 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3246 ARRAY_SIZE(wl->qos_params));
e6f5b934 3247
5a5f3b40
MB		 3248 mutex_lock(&wl->mutex);
3249 dev = wl->current_dev;
3250 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3251 goto out_unlock;
e6f5b934 3252
5a5f3b40
MB		 3253 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3254 b43_mac_suspend(dev);
3255 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3256 b43_qos_shm_offsets[queue]);
3257 b43_mac_enable(dev);
3258 err = 0;
e6f5b934 3259
5a5f3b40
MB		 3260out_unlock:
3261 mutex_unlock(&wl->mutex);
3262
3263 return err;
e4d6b795
MB		 3264}
3265
40faacc4
MB		 3266static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3267 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3268{
3269 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3270 struct b43_wldev *dev;
e4d6b795
MB		 3271 int err = -ENODEV;
3272
36dbd954
MB		 3273 mutex_lock(&wl->mutex);
3274 dev = wl->current_dev;
3275 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
5100d5ac
MB		 3276 if (b43_using_pio_transfers(dev))
3277 b43_pio_get_tx_stats(dev, stats);
3278 else
3279 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3280 err = 0;
3281 }
36dbd954
MB		 3282 mutex_unlock(&wl->mutex);
3283
e4d6b795
MB		 3284 return err;
3285}
3286
40faacc4
MB		 3287static int b43_op_get_stats(struct ieee80211_hw *hw,
3288 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3289{
3290 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3291
36dbd954 3292 mutex_lock(&wl->mutex);
e4d6b795 3293 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3294 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3295
3296 return 0;
3297}
3298
08e87a83
AF		 3299static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3300{
3301 struct b43_wl *wl = hw_to_b43_wl(hw);
3302 struct b43_wldev *dev;
3303 u64 tsf;
3304
3305 mutex_lock(&wl->mutex);
08e87a83
AF		 3306 dev = wl->current_dev;
3307
3308 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3309 b43_tsf_read(dev, &tsf);
3310 else
3311 tsf = 0;
3312
08e87a83
AF		 3313 mutex_unlock(&wl->mutex);
3314
3315 return tsf;
3316}
3317
3318static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3319{
3320 struct b43_wl *wl = hw_to_b43_wl(hw);
3321 struct b43_wldev *dev;
3322
3323 mutex_lock(&wl->mutex);
08e87a83
AF		 3324 dev = wl->current_dev;
3325
3326 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3327 b43_tsf_write(dev, tsf);
3328
08e87a83
AF		 3329 mutex_unlock(&wl->mutex);
3330}
3331
e4d6b795
MB		 3332static void b43_put_phy_into_reset(struct b43_wldev *dev)
3333{
3334 struct ssb_device *sdev = dev->dev;
3335 u32 tmslow;
3336
3337 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3338 tmslow &= ~B43_TMSLOW_GMODE;
3339 tmslow |= B43_TMSLOW_PHYRESET;
3340 tmslow |= SSB_TMSLOW_FGC;
3341 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3342 msleep(1);
3343
3344 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3345 tmslow &= ~SSB_TMSLOW_FGC;
3346 tmslow |= B43_TMSLOW_PHYRESET;
3347 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3348 msleep(1);
3349}
3350
99da185a 3351static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3352{
3353 switch (band) {
3354 case IEEE80211_BAND_5GHZ:
3355 return "5";
3356 case IEEE80211_BAND_2GHZ:
3357 return "2.4";
3358 default:
3359 break;
3360 }
3361 B43_WARN_ON(1);
3362 return "";
3363}
3364
e4d6b795 3365/* Expects wl->mutex locked */
bb1eeff1 3366static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3367{
bb1eeff1 3368 struct b43_wldev *up_dev = NULL;
e4d6b795 3369 struct b43_wldev *down_dev;
bb1eeff1 3370 struct b43_wldev *d;
e4d6b795 3371 int err;
922d8a0b 3372 bool uninitialized_var(gmode);
e4d6b795
MB		 3373 int prev_status;
3374
bb1eeff1
MB		 3375 /* Find a device and PHY which supports the band. */
3376 list_for_each_entry(d, &wl->devlist, list) {
3377 switch (chan->band) {
3378 case IEEE80211_BAND_5GHZ:
3379 if (d->phy.supports_5ghz) {
3380 up_dev = d;
3381 gmode = 0;
3382 }
3383 break;
3384 case IEEE80211_BAND_2GHZ:
3385 if (d->phy.supports_2ghz) {
3386 up_dev = d;
3387 gmode = 1;
3388 }
3389 break;
3390 default:
3391 B43_WARN_ON(1);
3392 return -EINVAL;
3393 }
3394 if (up_dev)
3395 break;
3396 }
3397 if (!up_dev) {
3398 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3399 band_to_string(chan->band));
3400 return -ENODEV;
e4d6b795
MB		 3401 }
3402 if ((up_dev == wl->current_dev) &&
3403 (!!wl->current_dev->phy.gmode == !!gmode)) {
3404 /* This device is already running. */
3405 return 0;
3406 }
bb1eeff1
MB		 3407 b43dbg(wl, "Switching to %s-GHz band\n",
3408 band_to_string(chan->band));
e4d6b795
MB		 3409 down_dev = wl->current_dev;
3410
3411 prev_status = b43_status(down_dev);
3412 /* Shutdown the currently running core. */
3413 if (prev_status >= B43_STAT_STARTED)
36dbd954 3414 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3415 if (prev_status >= B43_STAT_INITIALIZED)
3416 b43_wireless_core_exit(down_dev);
3417
3418 if (down_dev != up_dev) {
3419 /* We switch to a different core, so we put PHY into
3420 * RESET on the old core. */
3421 b43_put_phy_into_reset(down_dev);
3422 }
3423
3424 /* Now start the new core. */
3425 up_dev->phy.gmode = gmode;
3426 if (prev_status >= B43_STAT_INITIALIZED) {
3427 err = b43_wireless_core_init(up_dev);
3428 if (err) {
3429 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3430 "selected %s-GHz band\n",
3431 band_to_string(chan->band));
e4d6b795
MB		 3432 goto init_failure;
3433 }
3434 }
3435 if (prev_status >= B43_STAT_STARTED) {
3436 err = b43_wireless_core_start(up_dev);
3437 if (err) {
3438 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3439 "selected %s-GHz band\n",
3440 band_to_string(chan->band));
e4d6b795
MB		 3441 b43_wireless_core_exit(up_dev);
3442 goto init_failure;
3443 }
3444 }
3445 B43_WARN_ON(b43_status(up_dev) != prev_status);
3446
3447 wl->current_dev = up_dev;
3448
3449 return 0;
bb1eeff1 3450init_failure:
e4d6b795
MB		 3451 /* Whoops, failed to init the new core. No core is operating now. */
3452 wl->current_dev = NULL;
3453 return err;
3454}
3455
9124b077
JB		 3456/* Write the short and long frame retry limit values. */
3457static void b43_set_retry_limits(struct b43_wldev *dev,
3458 unsigned int short_retry,
3459 unsigned int long_retry)
3460{
3461 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3462 * the chip-internal counter. */
3463 short_retry = min(short_retry, (unsigned int)0xF);
3464 long_retry = min(long_retry, (unsigned int)0xF);
3465
3466 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3467 short_retry);
3468 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3469 long_retry);
3470}
3471
e8975581 3472static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3473{
3474 struct b43_wl *wl = hw_to_b43_wl(hw);
3475 struct b43_wldev *dev;
3476 struct b43_phy *phy;
e8975581 3477 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3478 int antenna;
e4d6b795 3479 int err = 0;
e4d6b795 3480
e4d6b795
MB		 3481 mutex_lock(&wl->mutex);
3482
bb1eeff1
MB		 3483 /* Switch the band (if necessary). This might change the active core. */
3484 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3485 if (err)
3486 goto out_unlock_mutex;
3487 dev = wl->current_dev;
3488 phy = &dev->phy;
3489
d10d0e57
MB		 3490 b43_mac_suspend(dev);
3491
9124b077
JB		 3492 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3493 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3494 conf->long_frame_max_tx_count);
3495 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3496 if (!changed)
d10d0e57 3497 goto out_mac_enable;
e4d6b795
MB		 3498
3499 /* Switch to the requested channel.
3500 * The firmware takes care of races with the TX handler. */
8318d78a 3501 if (conf->channel->hw_value != phy->channel)
ef1a628d 3502 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3503
d42ce84a
JB		 3504 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3505
e4d6b795
MB		 3506 /* Adjust the desired TX power level. */
3507 if (conf->power_level != 0) {
18c8adeb
MB		 3508 if (conf->power_level != phy->desired_txpower) {
3509 phy->desired_txpower = conf->power_level;
3510 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3511 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3512 }
3513 }
3514
3515 /* Antennas for RX and management frame TX. */
0f4ac38b 3516 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3517 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3518 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3519 if (phy->ops->set_rx_antenna)
3520 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3521
fd4973c5
LF		 3522 if (wl->radio_enabled != phy->radio_on) {
3523 if (wl->radio_enabled) {
19d337df 3524 b43_software_rfkill(dev, false);
fda9abcf
MB		 3525 b43info(dev->wl, "Radio turned on by software\n");
3526 if (!dev->radio_hw_enable) {
3527 b43info(dev->wl, "The hardware RF-kill button "
3528 "still turns the radio physically off. "
3529 "Press the button to turn it on.\n");
3530 }
3531 } else {
19d337df 3532 b43_software_rfkill(dev, true);
fda9abcf
MB		 3533 b43info(dev->wl, "Radio turned off by software\n");
3534 }
3535 }
3536
d10d0e57
MB		 3537out_mac_enable:
3538 b43_mac_enable(dev);
3539out_unlock_mutex:
e4d6b795
MB		 3540 mutex_unlock(&wl->mutex);
3541
3542 return err;
3543}
3544
881d948c 3545static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3546{
3547 struct ieee80211_supported_band *sband =
3548 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3549 struct ieee80211_rate *rate;
3550 int i;
3551 u16 basic, direct, offset, basic_offset, rateptr;
3552
3553 for (i = 0; i < sband->n_bitrates; i++) {
3554 rate = &sband->bitrates[i];
3555
3556 if (b43_is_cck_rate(rate->hw_value)) {
3557 direct = B43_SHM_SH_CCKDIRECT;
3558 basic = B43_SHM_SH_CCKBASIC;
3559 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3560 offset &= 0xF;
3561 } else {
3562 direct = B43_SHM_SH_OFDMDIRECT;
3563 basic = B43_SHM_SH_OFDMBASIC;
3564 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3565 offset &= 0xF;
3566 }
3567
3568 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3569
3570 if (b43_is_cck_rate(rate->hw_value)) {
3571 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3572 basic_offset &= 0xF;
3573 } else {
3574 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3575 basic_offset &= 0xF;
3576 }
3577
3578 /*
3579 * Get the pointer that we need to point to
3580 * from the direct map
3581 */
3582 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3583 direct + 2 * basic_offset);
3584 /* and write it to the basic map */
3585 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3586 rateptr);
3587 }
3588}
3589
3590static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3591 struct ieee80211_vif *vif,
3592 struct ieee80211_bss_conf *conf,
3593 u32 changed)
3594{
3595 struct b43_wl *wl = hw_to_b43_wl(hw);
3596 struct b43_wldev *dev;
c7ab5ef9
JB		 3597
3598 mutex_lock(&wl->mutex);
3599
3600 dev = wl->current_dev;
d10d0e57 3601 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3602 goto out_unlock_mutex;
2d0ddec5
JB		 3603
3604 B43_WARN_ON(wl->vif != vif);
3605
3606 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3607 if (conf->bssid)
3608 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3609 else
3610 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3611 }
2d0ddec5 3612
3f0d843b
JB		 3613 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3614 if (changed & BSS_CHANGED_BEACON &&
3615 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3616 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3617 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3618 b43_update_templates(wl);
3619
3620 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3621 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3622 }
3623
c7ab5ef9
JB		 3624 b43_mac_suspend(dev);
3625
57c4d7b4
JB		 3626 /* Update templates for AP/mesh mode. */
3627 if (changed & BSS_CHANGED_BEACON_INT &&
3628 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3629 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3630 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3631 b43_set_beacon_int(dev, conf->beacon_int);
3632
c7ab5ef9
JB		 3633 if (changed & BSS_CHANGED_BASIC_RATES)
3634 b43_update_basic_rates(dev, conf->basic_rates);
3635
3636 if (changed & BSS_CHANGED_ERP_SLOT) {
3637 if (conf->use_short_slot)
3638 b43_short_slot_timing_enable(dev);
3639 else
3640 b43_short_slot_timing_disable(dev);
3641 }
3642
3643 b43_mac_enable(dev);
d10d0e57 3644out_unlock_mutex:
c7ab5ef9 3645 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3646}
3647
40faacc4 3648static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3649 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3650 struct ieee80211_key_conf *key)
e4d6b795
MB		 3651{
3652 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3653 struct b43_wldev *dev;
e4d6b795
MB		 3654 u8 algorithm;
3655 u8 index;
c6dfc9a8 3656 int err;
060210f9 3657 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3658
3659 if (modparam_nohwcrypt)
3660 return -ENOSPC; /* User disabled HW-crypto */
3661
c6dfc9a8 3662 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3663
3664 dev = wl->current_dev;
3665 err = -ENODEV;
3666 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3667 goto out_unlock;
3668
403a3a13 3669 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3670 /* We don't have firmware for the crypto engine.
3671 * Must use software-crypto. */
3672 err = -EOPNOTSUPP;
3673 goto out_unlock;
3674 }
3675
c6dfc9a8 3676 err = -EINVAL;
e4d6b795 3677 switch (key->alg) {
e4d6b795 3678 case ALG_WEP:
e31a16d6 3679 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3680 algorithm = B43_SEC_ALGO_WEP40;
3681 else
3682 algorithm = B43_SEC_ALGO_WEP104;
3683 break;
3684 case ALG_TKIP:
3685 algorithm = B43_SEC_ALGO_TKIP;
3686 break;
3687 case ALG_CCMP:
3688 algorithm = B43_SEC_ALGO_AES;
3689 break;
3690 default:
3691 B43_WARN_ON(1);
c6dfc9a8 3692 goto out_unlock;
e4d6b795 3693 }
e4d6b795
MB		 3694 index = (u8) (key->keyidx);
3695 if (index > 3)
e4d6b795 3696 goto out_unlock;
e4d6b795
MB		 3697
3698 switch (cmd) {
3699 case SET_KEY:
035d0243 3700 if (algorithm == B43_SEC_ALGO_TKIP &&
3701 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3702 !modparam_hwtkip)) {
3703 /* We support only pairwise key */
e4d6b795
MB		 3704 err = -EOPNOTSUPP;
3705 goto out_unlock;
3706 }
3707
e808e586 3708 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3709 if (WARN_ON(!sta)) {
3710 err = -EOPNOTSUPP;
3711 goto out_unlock;
3712 }
e808e586 3713 /* Pairwise key with an assigned MAC address. */
e4d6b795 3714 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3715 key->key, key->keylen,
3716 sta->addr, key);
e808e586
MB		 3717 } else {
3718 /* Group key */
3719 err = b43_key_write(dev, index, algorithm,
3720 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3721 }
3722 if (err)
3723 goto out_unlock;
3724
3725 if (algorithm == B43_SEC_ALGO_WEP40 ||
3726 algorithm == B43_SEC_ALGO_WEP104) {
3727 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3728 } else {
3729 b43_hf_write(dev,
3730 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3731 }
3732 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3733 if (algorithm == B43_SEC_ALGO_TKIP)
3734 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3735 break;
3736 case DISABLE_KEY: {
3737 err = b43_key_clear(dev, key->hw_key_idx);
3738 if (err)
3739 goto out_unlock;
3740 break;
3741 }
3742 default:
3743 B43_WARN_ON(1);
3744 }
9cf7f247 3745
e4d6b795 3746out_unlock:
e4d6b795
MB		 3747 if (!err) {
3748 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3749 "mac: %pM\n",
e4d6b795 3750 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3751 sta ? sta->addr : bcast_addr);
9cf7f247 3752 b43_dump_keymemory(dev);
e4d6b795 3753 }
9cf7f247
MB		 3754 mutex_unlock(&wl->mutex);
3755
e4d6b795
MB		 3756 return err;
3757}
3758
40faacc4
MB		 3759static void b43_op_configure_filter(struct ieee80211_hw *hw,
3760 unsigned int changed, unsigned int *fflags,
3ac64bee 3761 u64 multicast)
e4d6b795
MB		 3762{
3763 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3764 struct b43_wldev *dev;
e4d6b795 3765
36dbd954
MB		 3766 mutex_lock(&wl->mutex);
3767 dev = wl->current_dev;
4150c572
JB		 3768 if (!dev) {
3769 *fflags = 0;
36dbd954 3770 goto out_unlock;
e4d6b795 3771 }
4150c572 3772
4150c572
JB		 3773 *fflags &= FIF_PROMISC_IN_BSS |
3774 FIF_ALLMULTI |
3775 FIF_FCSFAIL |
3776 FIF_PLCPFAIL |
3777 FIF_CONTROL |
3778 FIF_OTHER_BSS |
3779 FIF_BCN_PRBRESP_PROMISC;
3780
3781 changed &= FIF_PROMISC_IN_BSS |
3782 FIF_ALLMULTI |
3783 FIF_FCSFAIL |
3784 FIF_PLCPFAIL |
3785 FIF_CONTROL |
3786 FIF_OTHER_BSS |
3787 FIF_BCN_PRBRESP_PROMISC;
3788
3789 wl->filter_flags = *fflags;
3790
3791 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3792 b43_adjust_opmode(dev);
36dbd954
MB		 3793
3794out_unlock:
3795 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3796}
3797
36dbd954
MB		 3798/* Locking: wl->mutex
3799 * Returns the current dev. This might be different from the passed in dev,
3800 * because the core might be gone away while we unlocked the mutex. */
3801static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 3802{
3803 struct b43_wl *wl = dev->wl;
36dbd954 3804 struct b43_wldev *orig_dev;
e4d6b795 3805
36dbd954
MB		 3806redo:
3807 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3808 return dev;
a19d12d7 3809
f5d40eed 3810 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 3811 mutex_unlock(&wl->mutex);
3812 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 3813 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 3814 mutex_lock(&wl->mutex);
3815 dev = wl->current_dev;
3816 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3817 /* Whoops, aliens ate up the device while we were unlocked. */
3818 return dev;
3819 }
a19d12d7 3820
36dbd954 3821 /* Disable interrupts on the device. */
e4d6b795 3822 b43_set_status(dev, B43_STAT_INITIALIZED);
36dbd954
MB		 3823 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
3824 /* wl->mutex is locked. That is enough. */
3825 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3826 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3827 } else {
3828 spin_lock_irq(&wl->hardirq_lock);
3829 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3830 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3831 spin_unlock_irq(&wl->hardirq_lock);
3832 }
3833 /* Synchronize the interrupt handlers. Unlock to avoid deadlocks. */
3834 orig_dev = dev;
e4d6b795 3835 mutex_unlock(&wl->mutex);
36dbd954 3836 synchronize_irq(dev->dev->irq);
e4d6b795 3837 mutex_lock(&wl->mutex);
36dbd954
MB		 3838 dev = wl->current_dev;
3839 if (!dev)
3840 return dev;
3841 if (dev != orig_dev) {
3842 if (b43_status(dev) >= B43_STAT_STARTED)
3843 goto redo;
3844 return dev;
3845 }
3846 B43_WARN_ON(b43_read32(dev, B43_MMIO_GEN_IRQ_MASK));
e4d6b795 3847
f5d40eed
MB		 3848 /* Drain the TX queue */
3849 while (skb_queue_len(&wl->tx_queue))
3850 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3851
e4d6b795
MB		 3852 b43_mac_suspend(dev);
3853 free_irq(dev->dev->irq, dev);
3854 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 3855
3856 return dev;
e4d6b795
MB		 3857}
3858
3859/* Locking: wl->mutex */
3860static int b43_wireless_core_start(struct b43_wldev *dev)
3861{
3862 int err;
3863
3864 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3865
3866 drain_txstatus_queue(dev);
36dbd954
MB		 3867 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3868 b43_interrupt_thread_handler,
3869 IRQF_SHARED, KBUILD_MODNAME, dev);
e4d6b795
MB		 3870 if (err) {
3871 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3872 goto out;
3873 }
3874
3875 /* We are ready to run. */
3876 b43_set_status(dev, B43_STAT_STARTED);
3877
3878 /* Start data flow (TX/RX). */
3879 b43_mac_enable(dev);
13790728 3880 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3881
3882 /* Start maintainance work */
3883 b43_periodic_tasks_setup(dev);
3884
3885 b43dbg(dev->wl, "Wireless interface started\n");
3886 out:
3887 return err;
3888}
3889
3890/* Get PHY and RADIO versioning numbers */
3891static int b43_phy_versioning(struct b43_wldev *dev)
3892{
3893 struct b43_phy *phy = &dev->phy;
3894 u32 tmp;
3895 u8 analog_type;
3896 u8 phy_type;
3897 u8 phy_rev;
3898 u16 radio_manuf;
3899 u16 radio_ver;
3900 u16 radio_rev;
3901 int unsupported = 0;
3902
3903 /* Get PHY versioning */
3904 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3905 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3906 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3907 phy_rev = (tmp & B43_PHYVER_VERSION);
3908 switch (phy_type) {
3909 case B43_PHYTYPE_A:
3910 if (phy_rev >= 4)
3911 unsupported = 1;
3912 break;
3913 case B43_PHYTYPE_B:
3914 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3915 && phy_rev != 7)
3916 unsupported = 1;
3917 break;
3918 case B43_PHYTYPE_G:
013978b6 3919 if (phy_rev > 9)
e4d6b795
MB		 3920 unsupported = 1;
3921 break;
d5c71e46
MB		 3922#ifdef CONFIG_B43_NPHY
3923 case B43_PHYTYPE_N:
bb519bee 3924 if (phy_rev > 4)
d5c71e46
MB		 3925 unsupported = 1;
3926 break;
6b1c7c67
MB		 3927#endif
3928#ifdef CONFIG_B43_PHY_LP
3929 case B43_PHYTYPE_LP:
9d86a2d5 3930 if (phy_rev > 2)
6b1c7c67
MB		 3931 unsupported = 1;
3932 break;
d5c71e46 3933#endif
e4d6b795
MB		 3934 default:
3935 unsupported = 1;
3936 };
3937 if (unsupported) {
3938 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3939 "(Analog %u, Type %u, Revision %u)\n",
3940 analog_type, phy_type, phy_rev);
3941 return -EOPNOTSUPP;
3942 }
3943 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3944 analog_type, phy_type, phy_rev);
3945
3946 /* Get RADIO versioning */
3947 if (dev->dev->bus->chip_id == 0x4317) {
3948 if (dev->dev->bus->chip_rev == 0)
3949 tmp = 0x3205017F;
3950 else if (dev->dev->bus->chip_rev == 1)
3951 tmp = 0x4205017F;
3952 else
3953 tmp = 0x5205017F;
3954 } else {
3955 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3956 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3957 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3958 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3959 }
3960 radio_manuf = (tmp & 0x00000FFF);
3961 radio_ver = (tmp & 0x0FFFF000) >> 12;
3962 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3963 if (radio_manuf != 0x17F /* Broadcom */)
3964 unsupported = 1;
e4d6b795
MB		 3965 switch (phy_type) {
3966 case B43_PHYTYPE_A:
3967 if (radio_ver != 0x2060)
3968 unsupported = 1;
3969 if (radio_rev != 1)
3970 unsupported = 1;
3971 if (radio_manuf != 0x17F)
3972 unsupported = 1;
3973 break;
3974 case B43_PHYTYPE_B:
3975 if ((radio_ver & 0xFFF0) != 0x2050)
3976 unsupported = 1;
3977 break;
3978 case B43_PHYTYPE_G:
3979 if (radio_ver != 0x2050)
3980 unsupported = 1;
3981 break;
96c755a3 3982 case B43_PHYTYPE_N:
bb519bee 3983 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3984 unsupported = 1;
3985 break;
6b1c7c67 3986 case B43_PHYTYPE_LP:
9d86a2d5 3987 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 3988 unsupported = 1;
3989 break;
e4d6b795
MB		 3990 default:
3991 B43_WARN_ON(1);
3992 }
3993 if (unsupported) {
3994 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3995 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3996 radio_manuf, radio_ver, radio_rev);
3997 return -EOPNOTSUPP;
3998 }
3999 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4000 radio_manuf, radio_ver, radio_rev);
4001
4002 phy->radio_manuf = radio_manuf;
4003 phy->radio_ver = radio_ver;
4004 phy->radio_rev = radio_rev;
4005
4006 phy->analog = analog_type;
4007 phy->type = phy_type;
4008 phy->rev = phy_rev;
4009
4010 return 0;
4011}
4012
4013static void setup_struct_phy_for_init(struct b43_wldev *dev,
4014 struct b43_phy *phy)
4015{
e4d6b795 4016 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4017 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4018 /* PHY TX errors counter. */
4019 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4020
4021#if B43_DEBUG
4022 phy->phy_locked = 0;
4023 phy->radio_locked = 0;
4024#endif
e4d6b795
MB		 4025}
4026
4027static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4028{
aa6c7ae2
MB		 4029 dev->dfq_valid = 0;
4030
6a724d68
MB		 4031 /* Assume the radio is enabled. If it's not enabled, the state will
4032 * immediately get fixed on the first periodic work run. */
4033 dev->radio_hw_enable = 1;
e4d6b795
MB		 4034
4035 /* Stats */
4036 memset(&dev->stats, 0, sizeof(dev->stats));
4037
4038 setup_struct_phy_for_init(dev, &dev->phy);
4039
4040 /* IRQ related flags */
4041 dev->irq_reason = 0;
4042 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4043 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4044 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4045 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4046
4047 dev->mac_suspended = 1;
4048
4049 /* Noise calculation context */
4050 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4051}
4052
4053static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4054{
4055 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4056 u64 hf;
e4d6b795 4057
1855ba78
MB		 4058 if (!modparam_btcoex)
4059 return;
95de2841 4060 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4061 return;
4062 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4063 return;
4064
4065 hf = b43_hf_read(dev);
95de2841 4066 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4067 hf |= B43_HF_BTCOEXALT;
4068 else
4069 hf |= B43_HF_BTCOEX;
4070 b43_hf_write(dev, hf);
e4d6b795
MB		 4071}
4072
4073static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4074{
4075 if (!modparam_btcoex)
4076 return;
4077 //TODO
e4d6b795
MB		 4078}
4079
4080static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4081{
4082#ifdef CONFIG_SSB_DRIVER_PCICORE
4083 struct ssb_bus *bus = dev->dev->bus;
4084 u32 tmp;
4085
4086 if (bus->pcicore.dev &&
4087 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4088 bus->pcicore.dev->id.revision <= 5) {
4089 /* IMCFGLO timeouts workaround. */
4090 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
e4d6b795
MB		 4091 switch (bus->bustype) {
4092 case SSB_BUSTYPE_PCI:
4093 case SSB_BUSTYPE_PCMCIA:
98a1e2a9
MB		 4094 tmp &= ~SSB_IMCFGLO_REQTO;
4095 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4096 tmp |= 0x32;
4097 break;
4098 case SSB_BUSTYPE_SSB:
98a1e2a9
MB		 4099 tmp &= ~SSB_IMCFGLO_REQTO;
4100 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4101 tmp |= 0x53;
4102 break;
98a1e2a9
MB		 4103 default:
4104 break;
e4d6b795
MB		 4105 }
4106 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4107 }
4108#endif /* CONFIG_SSB_DRIVER_PCICORE */
4109}
4110
d59f720d
MB		 4111static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4112{
4113 u16 pu_delay;
4114
4115 /* The time value is in microseconds. */
4116 if (dev->phy.type == B43_PHYTYPE_A)
4117 pu_delay = 3700;
4118 else
4119 pu_delay = 1050;
05c914fe 4120 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4121 pu_delay = 500;
4122 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4123 pu_delay = max(pu_delay, (u16)2400);
4124
4125 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4126}
4127
4128/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4129static void b43_set_pretbtt(struct b43_wldev *dev)
4130{
4131 u16 pretbtt;
4132
4133 /* The time value is in microseconds. */
05c914fe 4134 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4135 pretbtt = 2;
4136 } else {
4137 if (dev->phy.type == B43_PHYTYPE_A)
4138 pretbtt = 120;
4139 else
4140 pretbtt = 250;
4141 }
4142 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4143 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4144}
4145
e4d6b795
MB		 4146/* Shutdown a wireless core */
4147/* Locking: wl->mutex */
4148static void b43_wireless_core_exit(struct b43_wldev *dev)
4149{
1f7d87b0 4150 u32 macctl;
e4d6b795 4151
36dbd954
MB		 4152 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4153 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795
MB		 4154 return;
4155 b43_set_status(dev, B43_STAT_UNINIT);
4156
1f7d87b0
MB		 4157 /* Stop the microcode PSM. */
4158 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4159 macctl &= ~B43_MACCTL_PSM_RUN;
4160 macctl |= B43_MACCTL_PSM_JMP0;
4161 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4162
3506e0c4
RW		 4163 if (!dev->suspend_in_progress) {
4164 b43_leds_exit(dev);
b844eba2 4165 b43_rng_exit(dev->wl);
3506e0c4 4166 }
e4d6b795 4167 b43_dma_free(dev);
5100d5ac 4168 b43_pio_free(dev);
e4d6b795 4169 b43_chip_exit(dev);
cb24f57f 4170 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4171 if (dev->wl->current_beacon) {
4172 dev_kfree_skb_any(dev->wl->current_beacon);
4173 dev->wl->current_beacon = NULL;
4174 }
4175
e4d6b795
MB		 4176 ssb_device_disable(dev->dev, 0);
4177 ssb_bus_may_powerdown(dev->dev->bus);
4178}
4179
4180/* Initialize a wireless core */
4181static int b43_wireless_core_init(struct b43_wldev *dev)
4182{
4183 struct b43_wl *wl = dev->wl;
4184 struct ssb_bus *bus = dev->dev->bus;
4185 struct ssb_sprom *sprom = &bus->sprom;
4186 struct b43_phy *phy = &dev->phy;
4187 int err;
a259d6a4
MB		 4188 u64 hf;
4189 u32 tmp;
e4d6b795
MB		 4190
4191 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4192
4193 err = ssb_bus_powerup(bus, 0);
4194 if (err)
4195 goto out;
4196 if (!ssb_device_is_enabled(dev->dev)) {
4197 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4198 b43_wireless_core_reset(dev, tmp);
4199 }
4200
fb11137a 4201 /* Reset all data structures. */
e4d6b795 4202 setup_struct_wldev_for_init(dev);
fb11137a 4203 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4204
4205 /* Enable IRQ routing to this device. */
4206 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4207
4208 b43_imcfglo_timeouts_workaround(dev);
4209 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4210 if (phy->ops->prepare_hardware) {
4211 err = phy->ops->prepare_hardware(dev);
ef1a628d 4212 if (err)
fb11137a 4213 goto err_busdown;
ef1a628d 4214 }
e4d6b795
MB		 4215 err = b43_chip_init(dev);
4216 if (err)
fb11137a 4217 goto err_busdown;
e4d6b795
MB		 4218 b43_shm_write16(dev, B43_SHM_SHARED,
4219 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4220 hf = b43_hf_read(dev);
4221 if (phy->type == B43_PHYTYPE_G) {
4222 hf |= B43_HF_SYMW;
4223 if (phy->rev == 1)
4224 hf |= B43_HF_GDCW;
95de2841 4225 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4226 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4227 }
4228 if (phy->radio_ver == 0x2050) {
4229 if (phy->radio_rev == 6)
4230 hf |= B43_HF_4318TSSI;
4231 if (phy->radio_rev < 6)
4232 hf |= B43_HF_VCORECALC;
e4d6b795 4233 }
1cc8f476
MB		 4234 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4235 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4236#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4237 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4238 (bus->pcicore.dev->id.revision <= 10))
4239 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4240#endif
25d3ef59 4241 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4242 b43_hf_write(dev, hf);
4243
74cfdba7
MB		 4244 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4245 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4246 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4247 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4248
4249 /* Disable sending probe responses from firmware.
4250 * Setting the MaxTime to one usec will always trigger
4251 * a timeout, so we never send any probe resp.
4252 * A timeout of zero is infinite. */
4253 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4254
4255 b43_rate_memory_init(dev);
5042c507 4256 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4257
4258 /* Minimum Contention Window */
4259 if (phy->type == B43_PHYTYPE_B) {
4260 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4261 } else {
4262 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4263 }
4264 /* Maximum Contention Window */
4265 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4266
5100d5ac
MB		 4267 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4268 dev->__using_pio_transfers = 1;
4269 err = b43_pio_init(dev);
4270 } else {
4271 dev->__using_pio_transfers = 0;
4272 err = b43_dma_init(dev);
4273 }
e4d6b795
MB		 4274 if (err)
4275 goto err_chip_exit;
03b29773 4276 b43_qos_init(dev);
d59f720d 4277 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4278 b43_bluetooth_coext_enable(dev);
4279
1cc8f476 4280 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4281 b43_upload_card_macaddress(dev);
e4d6b795 4282 b43_security_init(dev);
3506e0c4
RW		 4283 if (!dev->suspend_in_progress)
4284 b43_rng_init(wl);
e4d6b795 4285
5ab9549a
MB		 4286 ieee80211_wake_queues(dev->wl->hw);
4287
e4d6b795
MB		 4288 b43_set_status(dev, B43_STAT_INITIALIZED);
4289
3506e0c4
RW		 4290 if (!dev->suspend_in_progress)
4291 b43_leds_init(dev);
1a8d1227 4292out:
e4d6b795
MB		 4293 return err;
4294
ef1a628d 4295err_chip_exit:
e4d6b795 4296 b43_chip_exit(dev);
ef1a628d 4297err_busdown:
e4d6b795
MB		 4298 ssb_bus_may_powerdown(bus);
4299 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4300 return err;
4301}
4302
40faacc4
MB		 4303static int b43_op_add_interface(struct ieee80211_hw *hw,
4304 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4305{
4306 struct b43_wl *wl = hw_to_b43_wl(hw);
4307 struct b43_wldev *dev;
e4d6b795 4308 int err = -EOPNOTSUPP;
4150c572
JB		 4309
4310 /* TODO: allow WDS/AP devices to coexist */
4311
05c914fe
JB		 4312 if (conf->type != NL80211_IFTYPE_AP &&
4313 conf->type != NL80211_IFTYPE_MESH_POINT &&
4314 conf->type != NL80211_IFTYPE_STATION &&
4315 conf->type != NL80211_IFTYPE_WDS &&
4316 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4317 return -EOPNOTSUPP;
e4d6b795
MB		 4318
4319 mutex_lock(&wl->mutex);
4150c572 4320 if (wl->operating)
e4d6b795
MB		 4321 goto out_mutex_unlock;
4322
4323 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4324
4325 dev = wl->current_dev;
4150c572 4326 wl->operating = 1;
32bfd35d 4327 wl->vif = conf->vif;
4150c572
JB		 4328 wl->if_type = conf->type;
4329 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4330
4150c572 4331 b43_adjust_opmode(dev);
d59f720d
MB		 4332 b43_set_pretbtt(dev);
4333 b43_set_synth_pu_delay(dev, 0);
4150c572 4334 b43_upload_card_macaddress(dev);
4150c572
JB		 4335
4336 err = 0;
4337 out_mutex_unlock:
4338 mutex_unlock(&wl->mutex);
4339
4340 return err;
4341}
4342
40faacc4
MB		 4343static void b43_op_remove_interface(struct ieee80211_hw *hw,
4344 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4345{
4346 struct b43_wl *wl = hw_to_b43_wl(hw);
4347 struct b43_wldev *dev = wl->current_dev;
4150c572
JB		 4348
4349 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4350
4351 mutex_lock(&wl->mutex);
4352
4353 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4354 B43_WARN_ON(wl->vif != conf->vif);
4355 wl->vif = NULL;
4150c572
JB		 4356
4357 wl->operating = 0;
4358
4150c572
JB		 4359 b43_adjust_opmode(dev);
4360 memset(wl->mac_addr, 0, ETH_ALEN);
4361 b43_upload_card_macaddress(dev);
4150c572
JB		 4362
4363 mutex_unlock(&wl->mutex);
4364}
4365
40faacc4 4366static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4367{
4368 struct b43_wl *wl = hw_to_b43_wl(hw);
4369 struct b43_wldev *dev = wl->current_dev;
4370 int did_init = 0;
923403b8 4371 int err = 0;
4150c572 4372
7be1bb6b
MB		 4373 /* Kill all old instance specific information to make sure
4374 * the card won't use it in the short timeframe between start
4375 * and mac80211 reconfiguring it. */
4376 memset(wl->bssid, 0, ETH_ALEN);
4377 memset(wl->mac_addr, 0, ETH_ALEN);
4378 wl->filter_flags = 0;
4379 wl->radiotap_enabled = 0;
e6f5b934 4380 b43_qos_clear(wl);
6b4bec01
MB		 4381 wl->beacon0_uploaded = 0;
4382 wl->beacon1_uploaded = 0;
4383 wl->beacon_templates_virgin = 1;
fd4973c5 4384 wl->radio_enabled = 1;
7be1bb6b 4385
4150c572
JB		 4386 mutex_lock(&wl->mutex);
4387
e4d6b795
MB		 4388 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4389 err = b43_wireless_core_init(dev);
f41f3f37 4390 if (err)
e4d6b795
MB		 4391 goto out_mutex_unlock;
4392 did_init = 1;
4393 }
4150c572 4394
e4d6b795
MB		 4395 if (b43_status(dev) < B43_STAT_STARTED) {
4396 err = b43_wireless_core_start(dev);
4397 if (err) {
4398 if (did_init)
4399 b43_wireless_core_exit(dev);
4400 goto out_mutex_unlock;
4401 }
4402 }
4403
f41f3f37
JB		 4404 /* XXX: only do if device doesn't support rfkill irq */
4405 wiphy_rfkill_start_polling(hw->wiphy);
4406
4150c572 4407 out_mutex_unlock:
e4d6b795
MB		 4408 mutex_unlock(&wl->mutex);
4409
4410 return err;
4411}
4412
40faacc4 4413static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4414{
4415 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4416 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4417
a82d9922 4418 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4419
e4d6b795 4420 mutex_lock(&wl->mutex);
36dbd954
MB		 4421 if (b43_status(dev) >= B43_STAT_STARTED) {
4422 dev = b43_wireless_core_stop(dev);
4423 if (!dev)
4424 goto out_unlock;
4425 }
4150c572 4426 b43_wireless_core_exit(dev);
fd4973c5 4427 wl->radio_enabled = 0;
36dbd954
MB		 4428
4429out_unlock:
e4d6b795 4430 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4431
4432 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4433}
4434
17741cdc
JB		 4435static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4436 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4437{
4438 struct b43_wl *wl = hw_to_b43_wl(hw);
4439
36dbd954 4440 mutex_lock(&wl->mutex);
9d139c81 4441 b43_update_templates(wl);
36dbd954 4442 mutex_unlock(&wl->mutex);
e66fee6a
MB		 4443
4444 return 0;
4445}
4446
38968d09
JB		 4447static void b43_op_sta_notify(struct ieee80211_hw *hw,
4448 struct ieee80211_vif *vif,
4449 enum sta_notify_cmd notify_cmd,
17741cdc 4450 struct ieee80211_sta *sta)
38968d09
JB		 4451{
4452 struct b43_wl *wl = hw_to_b43_wl(hw);
4453
4454 B43_WARN_ON(!vif || wl->vif != vif);
4455}
4456
25d3ef59
MB		 4457static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4458{
4459 struct b43_wl *wl = hw_to_b43_wl(hw);
4460 struct b43_wldev *dev;
4461
4462 mutex_lock(&wl->mutex);
4463 dev = wl->current_dev;
4464 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4465 /* Disable CFP update during scan on other channels. */
4466 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4467 }
4468 mutex_unlock(&wl->mutex);
4469}
4470
4471static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4472{
4473 struct b43_wl *wl = hw_to_b43_wl(hw);
4474 struct b43_wldev *dev;
4475
4476 mutex_lock(&wl->mutex);
4477 dev = wl->current_dev;
4478 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4479 /* Re-enable CFP update. */
4480 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4481 }
4482 mutex_unlock(&wl->mutex);
4483}
4484
e4d6b795 4485static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4486 .tx = b43_op_tx,
4487 .conf_tx = b43_op_conf_tx,
4488 .add_interface = b43_op_add_interface,
4489 .remove_interface = b43_op_remove_interface,
4490 .config = b43_op_config,
c7ab5ef9 4491 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4492 .configure_filter = b43_op_configure_filter,
4493 .set_key = b43_op_set_key,
035d0243 4494 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4495 .get_stats = b43_op_get_stats,
4496 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4497 .get_tsf = b43_op_get_tsf,
4498 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4499 .start = b43_op_start,
4500 .stop = b43_op_stop,
e66fee6a 4501 .set_tim = b43_op_beacon_set_tim,
38968d09 4502 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4503 .sw_scan_start = b43_op_sw_scan_start_notifier,
4504 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4505 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4506};
4507
4508/* Hard-reset the chip. Do not call this directly.
4509 * Use b43_controller_restart()
4510 */
4511static void b43_chip_reset(struct work_struct *work)
4512{
4513 struct b43_wldev *dev =
4514 container_of(work, struct b43_wldev, restart_work);
4515 struct b43_wl *wl = dev->wl;
4516 int err = 0;
4517 int prev_status;
4518
4519 mutex_lock(&wl->mutex);
4520
4521 prev_status = b43_status(dev);
4522 /* Bring the device down... */
36dbd954
MB		 4523 if (prev_status >= B43_STAT_STARTED) {
4524 dev = b43_wireless_core_stop(dev);
4525 if (!dev) {
4526 err = -ENODEV;
4527 goto out;
4528 }
4529 }
e4d6b795
MB		 4530 if (prev_status >= B43_STAT_INITIALIZED)
4531 b43_wireless_core_exit(dev);
4532
4533 /* ...and up again. */
4534 if (prev_status >= B43_STAT_INITIALIZED) {
4535 err = b43_wireless_core_init(dev);
4536 if (err)
4537 goto out;
4538 }
4539 if (prev_status >= B43_STAT_STARTED) {
4540 err = b43_wireless_core_start(dev);
4541 if (err) {
4542 b43_wireless_core_exit(dev);
4543 goto out;
4544 }
4545 }
3bf0a32e
MB		 4546out:
4547 if (err)
4548 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4549 mutex_unlock(&wl->mutex);
4550 if (err)
4551 b43err(wl, "Controller restart FAILED\n");
4552 else
4553 b43info(wl, "Controller restarted\n");
4554}
4555
bb1eeff1 4556static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4557 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4558{
4559 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4560
bb1eeff1
MB		 4561 if (have_2ghz_phy)
4562 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4563 if (dev->phy.type == B43_PHYTYPE_N) {
4564 if (have_5ghz_phy)
4565 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4566 } else {
4567 if (have_5ghz_phy)
4568 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4569 }
96c755a3 4570
bb1eeff1
MB		 4571 dev->phy.supports_2ghz = have_2ghz_phy;
4572 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4573
4574 return 0;
4575}
4576
4577static void b43_wireless_core_detach(struct b43_wldev *dev)
4578{
4579 /* We release firmware that late to not be required to re-request
4580 * is all the time when we reinit the core. */
4581 b43_release_firmware(dev);
fb11137a 4582 b43_phy_free(dev);
e4d6b795
MB		 4583}
4584
4585static int b43_wireless_core_attach(struct b43_wldev *dev)
4586{
4587 struct b43_wl *wl = dev->wl;
4588 struct ssb_bus *bus = dev->dev->bus;
4589 struct pci_dev *pdev = bus->host_pci;
4590 int err;
96c755a3 4591 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4592 u32 tmp;
4593
4594 /* Do NOT do any device initialization here.
4595 * Do it in wireless_core_init() instead.
4596 * This function is for gathering basic information about the HW, only.
4597 * Also some structs may be set up here. But most likely you want to have
4598 * that in core_init(), too.
4599 */
4600
4601 err = ssb_bus_powerup(bus, 0);
4602 if (err) {
4603 b43err(wl, "Bus powerup failed\n");
4604 goto out;
4605 }
4606 /* Get the PHY type. */
4607 if (dev->dev->id.revision >= 5) {
4608 u32 tmshigh;
4609
4610 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4611 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4612 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4613 } else
96c755a3 4614 B43_WARN_ON(1);
e4d6b795 4615
96c755a3 4616 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4617 dev->phy.radio_on = 1;
e4d6b795
MB		 4618 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4619 b43_wireless_core_reset(dev, tmp);
4620
4621 err = b43_phy_versioning(dev);
4622 if (err)
21954c36 4623 goto err_powerdown;
e4d6b795
MB		 4624 /* Check if this device supports multiband. */
4625 if (!pdev ||
4626 (pdev->device != 0x4312 &&
4627 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4628 /* No multiband support. */
96c755a3
MB		 4629 have_2ghz_phy = 0;
4630 have_5ghz_phy = 0;
e4d6b795
MB		 4631 switch (dev->phy.type) {
4632 case B43_PHYTYPE_A:
96c755a3 4633 have_5ghz_phy = 1;
e4d6b795 4634 break;
9d86a2d5 4635 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4636#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4637 have_5ghz_phy = 1;
86b2892a 4638#endif
e4d6b795 4639 case B43_PHYTYPE_G:
96c755a3
MB		 4640 case B43_PHYTYPE_N:
4641 have_2ghz_phy = 1;
e4d6b795
MB		 4642 break;
4643 default:
4644 B43_WARN_ON(1);
4645 }
4646 }
96c755a3
MB		 4647 if (dev->phy.type == B43_PHYTYPE_A) {
4648 /* FIXME */
4649 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4650 err = -EOPNOTSUPP;
4651 goto err_powerdown;
4652 }
2e35af14
MB		 4653 if (1 /* disable A-PHY */) {
4654 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4655 if (dev->phy.type != B43_PHYTYPE_N &&
4656 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4657 have_2ghz_phy = 1;
4658 have_5ghz_phy = 0;
4659 }
4660 }
4661
fb11137a
MB		 4662 err = b43_phy_allocate(dev);
4663 if (err)
4664 goto err_powerdown;
4665
96c755a3 4666 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4667 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4668 b43_wireless_core_reset(dev, tmp);
4669
4670 err = b43_validate_chipaccess(dev);
4671 if (err)
fb11137a 4672 goto err_phy_free;
bb1eeff1 4673 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4674 if (err)
fb11137a 4675 goto err_phy_free;
e4d6b795
MB		 4676
4677 /* Now set some default "current_dev" */
4678 if (!wl->current_dev)
4679 wl->current_dev = dev;
4680 INIT_WORK(&dev->restart_work, b43_chip_reset);
4681
cb24f57f 4682 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4683 ssb_device_disable(dev->dev, 0);
4684 ssb_bus_may_powerdown(bus);
4685
4686out:
4687 return err;
4688
fb11137a
MB		 4689err_phy_free:
4690 b43_phy_free(dev);
e4d6b795
MB		 4691err_powerdown:
4692 ssb_bus_may_powerdown(bus);
4693 return err;
4694}
4695
4696static void b43_one_core_detach(struct ssb_device *dev)
4697{
4698 struct b43_wldev *wldev;
4699 struct b43_wl *wl;
4700
3bf0a32e
MB		 4701 /* Do not cancel ieee80211-workqueue based work here.
4702 * See comment in b43_remove(). */
4703
e4d6b795
MB		 4704 wldev = ssb_get_drvdata(dev);
4705 wl = wldev->wl;
e4d6b795
MB		 4706 b43_debugfs_remove_device(wldev);
4707 b43_wireless_core_detach(wldev);
4708 list_del(&wldev->list);
4709 wl->nr_devs--;
4710 ssb_set_drvdata(dev, NULL);
4711 kfree(wldev);
4712}
4713
4714static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4715{
4716 struct b43_wldev *wldev;
4717 struct pci_dev *pdev;
4718 int err = -ENOMEM;
4719
4720 if (!list_empty(&wl->devlist)) {
4721 /* We are not the first core on this chip. */
4722 pdev = dev->bus->host_pci;
4723 /* Only special chips support more than one wireless
4724 * core, although some of the other chips have more than
4725 * one wireless core as well. Check for this and
4726 * bail out early.
4727 */
4728 if (!pdev ||
4729 ((pdev->device != 0x4321) &&
4730 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4731 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4732 return -ENODEV;
4733 }
4734 }
4735
4736 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4737 if (!wldev)
4738 goto out;
4739
4740 wldev->dev = dev;
4741 wldev->wl = wl;
4742 b43_set_status(wldev, B43_STAT_UNINIT);
4743 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 4744 INIT_LIST_HEAD(&wldev->list);
4745
4746 err = b43_wireless_core_attach(wldev);
4747 if (err)
4748 goto err_kfree_wldev;
4749
4750 list_add(&wldev->list, &wl->devlist);
4751 wl->nr_devs++;
4752 ssb_set_drvdata(dev, wldev);
4753 b43_debugfs_add_device(wldev);
4754
4755 out:
4756 return err;
4757
4758 err_kfree_wldev:
4759 kfree(wldev);
4760 return err;
4761}
4762
9fc38458
MB		 4763#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4764 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4765 (pdev->device == _device) && \
4766 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4767 (pdev->subsystem_device == _subdevice) )
4768
e4d6b795
MB		 4769static void b43_sprom_fixup(struct ssb_bus *bus)
4770{
1855ba78
MB		 4771 struct pci_dev *pdev;
4772
e4d6b795
MB		 4773 /* boardflags workarounds */
4774 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4775 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4776 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4777 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4778 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4779 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4780 if (bus->bustype == SSB_BUSTYPE_PCI) {
4781 pdev = bus->host_pci;
9fc38458 4782 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4783 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4784 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4785 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4786 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4787 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4788 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4789 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4790 }
e4d6b795
MB		 4791}
4792
4793static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4794{
4795 struct ieee80211_hw *hw = wl->hw;
4796
4797 ssb_set_devtypedata(dev, NULL);
4798 ieee80211_free_hw(hw);
4799}
4800
4801static int b43_wireless_init(struct ssb_device *dev)
4802{
4803 struct ssb_sprom *sprom = &dev->bus->sprom;
4804 struct ieee80211_hw *hw;
4805 struct b43_wl *wl;
4806 int err = -ENOMEM;
4807
4808 b43_sprom_fixup(dev->bus);
4809
4810 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4811 if (!hw) {
4812 b43err(NULL, "Could not allocate ieee80211 device\n");
4813 goto out;
4814 }
403a3a13 4815 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4816
4817 /* fill hw info */
605a0bd6 4818 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4819 IEEE80211_HW_SIGNAL_DBM |
4820 IEEE80211_HW_NOISE_DBM;
4821
f59ac048
LR		 4822 hw->wiphy->interface_modes =
4823 BIT(NL80211_IFTYPE_AP) |
4824 BIT(NL80211_IFTYPE_MESH_POINT) |
4825 BIT(NL80211_IFTYPE_STATION) |
4826 BIT(NL80211_IFTYPE_WDS) |
4827 BIT(NL80211_IFTYPE_ADHOC);
4828
403a3a13
MB		 4829 hw->queues = modparam_qos ? 4 : 1;
4830 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4831 hw->max_rates = 2;
e4d6b795 4832 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4833 if (is_valid_ether_addr(sprom->et1mac))
4834 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4835 else
95de2841 4836 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4837
403a3a13 4838 /* Initialize struct b43_wl */
e4d6b795 4839 wl->hw = hw;
e4d6b795
MB		 4840 spin_lock_init(&wl->leds_lock);
4841 mutex_init(&wl->mutex);
36dbd954 4842 spin_lock_init(&wl->hardirq_lock);
e4d6b795 4843 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4844 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4845 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 4846 INIT_WORK(&wl->tx_work, b43_tx_work);
4847 skb_queue_head_init(&wl->tx_queue);
e4d6b795
MB		 4848
4849 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4850 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4851 dev->bus->chip_id, dev->id.revision);
e4d6b795 4852 err = 0;
060210f9 4853out:
e4d6b795
MB		 4854 return err;
4855}
4856
4857static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4858{
4859 struct b43_wl *wl;
4860 int err;
4861 int first = 0;
4862
4863 wl = ssb_get_devtypedata(dev);
4864 if (!wl) {
4865 /* Probing the first core. Must setup common struct b43_wl */
4866 first = 1;
4867 err = b43_wireless_init(dev);
4868 if (err)
4869 goto out;
4870 wl = ssb_get_devtypedata(dev);
4871 B43_WARN_ON(!wl);
4872 }
4873 err = b43_one_core_attach(dev, wl);
4874 if (err)
4875 goto err_wireless_exit;
4876
4877 if (first) {
4878 err = ieee80211_register_hw(wl->hw);
4879 if (err)
4880 goto err_one_core_detach;
4881 }
4882
4883 out:
4884 return err;
4885
4886 err_one_core_detach:
4887 b43_one_core_detach(dev);
4888 err_wireless_exit:
4889 if (first)
4890 b43_wireless_exit(dev, wl);
4891 return err;
4892}
4893
4894static void b43_remove(struct ssb_device *dev)
4895{
4896 struct b43_wl *wl = ssb_get_devtypedata(dev);
4897 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4898
3bf0a32e
MB		 4899 /* We must cancel any work here before unregistering from ieee80211,
4900 * as the ieee80211 unreg will destroy the workqueue. */
4901 cancel_work_sync(&wldev->restart_work);
4902
e4d6b795 4903 B43_WARN_ON(!wl);
403a3a13
MB		 4904 if (wl->current_dev == wldev) {
4905 /* Restore the queues count before unregistering, because firmware detect
4906 * might have modified it. Restoring is important, so the networking
4907 * stack can properly free resources. */
4908 wl->hw->queues = wl->mac80211_initially_registered_queues;
e4d6b795 4909 ieee80211_unregister_hw(wl->hw);
403a3a13 4910 }
e4d6b795
MB		 4911
4912 b43_one_core_detach(dev);
4913
4914 if (list_empty(&wl->devlist)) {
4915 /* Last core on the chip unregistered.
4916 * We can destroy common struct b43_wl.
4917 */
4918 b43_wireless_exit(dev, wl);
4919 }
4920}
4921
4922/* Perform a hardware reset. This can be called from any context. */
4923void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4924{
4925 /* Must avoid requeueing, if we are in shutdown. */
4926 if (b43_status(dev) < B43_STAT_INITIALIZED)
4927 return;
4928 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 4929 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 4930}
4931
4932#ifdef CONFIG_PM
4933
4934static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4935{
4936 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4937 struct b43_wl *wl = wldev->wl;
4938
4939 b43dbg(wl, "Suspending...\n");
4940
4941 mutex_lock(&wl->mutex);
3506e0c4 4942 wldev->suspend_in_progress = true;
e4d6b795
MB		 4943 wldev->suspend_init_status = b43_status(wldev);
4944 if (wldev->suspend_init_status >= B43_STAT_STARTED)
36dbd954
MB		 4945 wldev = b43_wireless_core_stop(wldev);
4946 if (wldev && wldev->suspend_init_status >= B43_STAT_INITIALIZED)
e4d6b795
MB		 4947 b43_wireless_core_exit(wldev);
4948 mutex_unlock(&wl->mutex);
4949
4950 b43dbg(wl, "Device suspended.\n");
4951
4952 return 0;
4953}
4954
4955static int b43_resume(struct ssb_device *dev)
4956{
4957 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4958 struct b43_wl *wl = wldev->wl;
4959 int err = 0;
4960
4961 b43dbg(wl, "Resuming...\n");
4962
4963 mutex_lock(&wl->mutex);
4964 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4965 err = b43_wireless_core_init(wldev);
4966 if (err) {
4967 b43err(wl, "Resume failed at core init\n");
4968 goto out;
4969 }
4970 }
4971 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4972 err = b43_wireless_core_start(wldev);
4973 if (err) {
3506e0c4 4974 b43_leds_exit(wldev);
b844eba2 4975 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4976 b43_wireless_core_exit(wldev);
4977 b43err(wl, "Resume failed at core start\n");
4978 goto out;
4979 }
4980 }
e4d6b795 4981 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4982 out:
4983 wldev->suspend_in_progress = false;
4984 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4985 return err;
4986}
4987
4988#else /* CONFIG_PM */
4989# define b43_suspend NULL
4990# define b43_resume NULL
4991#endif /* CONFIG_PM */
4992
4993static struct ssb_driver b43_ssb_driver = {
4994 .name = KBUILD_MODNAME,
4995 .id_table = b43_ssb_tbl,
4996 .probe = b43_probe,
4997 .remove = b43_remove,
4998 .suspend = b43_suspend,
4999 .resume = b43_resume,
5000};
5001
26bc783f
MB		 5002static void b43_print_driverinfo(void)
5003{
5004 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
f41f3f37 5005 *feat_leds = "";
26bc783f
MB		 5006
5007#ifdef CONFIG_B43_PCI_AUTOSELECT
5008 feat_pci = "P";
5009#endif
5010#ifdef CONFIG_B43_PCMCIA
5011 feat_pcmcia = "M";
5012#endif
5013#ifdef CONFIG_B43_NPHY
5014 feat_nphy = "N";
5015#endif
5016#ifdef CONFIG_B43_LEDS
5017 feat_leds = "L";
26bc783f
MB		 5018#endif
5019 printk(KERN_INFO "Broadcom 43xx driver loaded "
f41f3f37 5020 "[ Features: %s%s%s%s, Firmware-ID: "
26bc783f
MB		 5021 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5022 feat_pci, feat_pcmcia, feat_nphy,
f41f3f37 5023 feat_leds);
26bc783f
MB		 5024}
5025
e4d6b795
MB		 5026static int __init b43_init(void)
5027{
5028 int err;
5029
5030 b43_debugfs_init();
5031 err = b43_pcmcia_init();
5032 if (err)
5033 goto err_dfs_exit;
5034 err = ssb_driver_register(&b43_ssb_driver);
5035 if (err)
5036 goto err_pcmcia_exit;
26bc783f 5037 b43_print_driverinfo();
e4d6b795
MB		 5038
5039 return err;
5040
5041err_pcmcia_exit:
5042 b43_pcmcia_exit();
5043err_dfs_exit:
5044 b43_debugfs_exit();
5045 return err;
5046}
5047
5048static void __exit b43_exit(void)
5049{
5050 ssb_driver_unregister(&b43_ssb_driver);
5051 b43_pcmcia_exit();
5052 b43_debugfs_exit();
5053}
5054
5055module_init(b43_init)
5056module_exit(b43_exit)
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