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ssb: Add boardflags_hi field to the sprom data structure
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
47#include "phy.h"
48#include "dma.h"
e4d6b795
MB		 49#include "sysfs.h"
50#include "xmit.h"
e4d6b795
MB		 51#include "lo.h"
52#include "pcmcia.h"
53
54MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55MODULE_AUTHOR("Martin Langer");
56MODULE_AUTHOR("Stefano Brivio");
57MODULE_AUTHOR("Michael Buesch");
58MODULE_LICENSE("GPL");
59
e4d6b795
MB		 60
61static int modparam_bad_frames_preempt;
62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
65
e4d6b795
MB		 66static char modparam_fwpostfix[16];
67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
69
e4d6b795
MB		 70static int modparam_hwpctl;
71module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
73
74static int modparam_nohwcrypt;
75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77
78static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 86 SSB_DEVTABLE_END
87};
88
89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
90
91/* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95#define RATETAB_ENT(_rateid, _flags) \
96 { \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
98 .val = (_rateid), \
99 .val2 = (_rateid), \
100 .flags = (_flags), \
101 }
102static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
115};
116
117#define b43_a_ratetable (__b43_ratetable + 4)
118#define b43_a_ratetable_size 8
119#define b43_b_ratetable (__b43_ratetable + 0)
120#define b43_b_ratetable_size 4
121#define b43_g_ratetable (__b43_ratetable + 0)
122#define b43_g_ratetable_size 12
123
124#define CHANTAB_ENT(_chanid, _freq) \
125 { \
126 .chan = (_chanid), \
127 .freq = (_freq), \
128 .val = (_chanid), \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
134 }
96c755a3 135static struct ieee80211_channel b43_2ghz_chantable[] = {
e4d6b795
MB		 136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
150};
96c755a3 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
e4d6b795 152
96c755a3
MB		 153#if 0
154static struct ieee80211_channel b43_5ghz_chantable[] = {
e4d6b795
MB		 155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
168};
96c755a3
MB		 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
170#endif
e4d6b795
MB		 171
172static void b43_wireless_core_exit(struct b43_wldev *dev);
173static int b43_wireless_core_init(struct b43_wldev *dev);
174static void b43_wireless_core_stop(struct b43_wldev *dev);
175static int b43_wireless_core_start(struct b43_wldev *dev);
176
177static int b43_ratelimit(struct b43_wl *wl)
178{
179 if (!wl || !wl->current_dev)
180 return 1;
181 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
182 return 1;
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
186}
187
188void b43info(struct b43_wl *wl, const char *fmt, ...)
189{
190 va_list args;
191
192 if (!b43_ratelimit(wl))
193 return;
194 va_start(args, fmt);
195 printk(KERN_INFO "b43-%s: ",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
197 vprintk(fmt, args);
198 va_end(args);
199}
200
201void b43err(struct b43_wl *wl, const char *fmt, ...)
202{
203 va_list args;
204
205 if (!b43_ratelimit(wl))
206 return;
207 va_start(args, fmt);
208 printk(KERN_ERR "b43-%s ERROR: ",
209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
210 vprintk(fmt, args);
211 va_end(args);
212}
213
214void b43warn(struct b43_wl *wl, const char *fmt, ...)
215{
216 va_list args;
217
218 if (!b43_ratelimit(wl))
219 return;
220 va_start(args, fmt);
221 printk(KERN_WARNING "b43-%s warning: ",
222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
223 vprintk(fmt, args);
224 va_end(args);
225}
226
227#if B43_DEBUG
228void b43dbg(struct b43_wl *wl, const char *fmt, ...)
229{
230 va_list args;
231
232 va_start(args, fmt);
233 printk(KERN_DEBUG "b43-%s debug: ",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
235 vprintk(fmt, args);
236 va_end(args);
237}
238#endif /* DEBUG */
239
240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
241{
242 u32 macctl;
243
244 B43_WARN_ON(offset % 4 != 0);
245
246 macctl = b43_read32(dev, B43_MMIO_MACCTL);
247 if (macctl & B43_MACCTL_BE)
248 val = swab32(val);
249
250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
251 mmiowb();
252 b43_write32(dev, B43_MMIO_RAM_DATA, val);
253}
254
280d0e16
MB		 255static inline void b43_shm_control_word(struct b43_wldev *dev,
256 u16 routing, u16 offset)
e4d6b795
MB		 257{
258 u32 control;
259
260 /* "offset" is the WORD offset. */
e4d6b795
MB		 261 control = routing;
262 control <<= 16;
263 control |= offset;
264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
265}
266
267u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
268{
280d0e16
MB		 269 struct b43_wl *wl = dev->wl;
270 unsigned long flags;
e4d6b795
MB		 271 u32 ret;
272
280d0e16 273 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 274 if (routing == B43_SHM_SHARED) {
275 B43_WARN_ON(offset & 0x0001);
276 if (offset & 0x0003) {
277 /* Unaligned access */
278 b43_shm_control_word(dev, routing, offset >> 2);
279 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
280 ret <<= 16;
281 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
282 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
283
280d0e16 284 goto out;
e4d6b795
MB		 285 }
286 offset >>= 2;
287 }
288 b43_shm_control_word(dev, routing, offset);
289 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 290out:
291 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 292
293 return ret;
294}
295
296u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
297{
280d0e16
MB		 298 struct b43_wl *wl = dev->wl;
299 unsigned long flags;
e4d6b795
MB		 300 u16 ret;
301
280d0e16 302 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 303 if (routing == B43_SHM_SHARED) {
304 B43_WARN_ON(offset & 0x0001);
305 if (offset & 0x0003) {
306 /* Unaligned access */
307 b43_shm_control_word(dev, routing, offset >> 2);
308 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
309
280d0e16 310 goto out;
e4d6b795
MB		 311 }
312 offset >>= 2;
313 }
314 b43_shm_control_word(dev, routing, offset);
315 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 316out:
317 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 318
319 return ret;
320}
321
322void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
323{
280d0e16
MB		 324 struct b43_wl *wl = dev->wl;
325 unsigned long flags;
326
327 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 328 if (routing == B43_SHM_SHARED) {
329 B43_WARN_ON(offset & 0x0001);
330 if (offset & 0x0003) {
331 /* Unaligned access */
332 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 333 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
334 (value >> 16) & 0xffff);
e4d6b795 335 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
280d0e16 337 goto out;
e4d6b795
MB		 338 }
339 offset >>= 2;
340 }
341 b43_shm_control_word(dev, routing, offset);
e4d6b795 342 b43_write32(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 343out:
344 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 345}
346
347void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
348{
280d0e16
MB		 349 struct b43_wl *wl = dev->wl;
350 unsigned long flags;
351
352 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 353 if (routing == B43_SHM_SHARED) {
354 B43_WARN_ON(offset & 0x0001);
355 if (offset & 0x0003) {
356 /* Unaligned access */
357 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 358 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
280d0e16 359 goto out;
e4d6b795
MB		 360 }
361 offset >>= 2;
362 }
363 b43_shm_control_word(dev, routing, offset);
e4d6b795 364 b43_write16(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 365out:
366 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 367}
368
369/* Read HostFlags */
370u32 b43_hf_read(struct b43_wldev * dev)
371{
372 u32 ret;
373
374 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
375 ret <<= 16;
376 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
377
378 return ret;
379}
380
381/* Write HostFlags */
382void b43_hf_write(struct b43_wldev *dev, u32 value)
383{
384 b43_shm_write16(dev, B43_SHM_SHARED,
385 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
386 b43_shm_write16(dev, B43_SHM_SHARED,
387 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
388}
389
390void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
391{
392 /* We need to be careful. As we read the TSF from multiple
393 * registers, we should take care of register overflows.
394 * In theory, the whole tsf read process should be atomic.
395 * We try to be atomic here, by restaring the read process,
396 * if any of the high registers changed (overflew).
397 */
398 if (dev->dev->id.revision >= 3) {
399 u32 low, high, high2;
400
401 do {
402 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
403 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
404 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0, v1, v2, v3;
413 u16 test1, test2, test3;
414
415 do {
416 v3 = b43_read16(dev, B43_MMIO_TSF_3);
417 v2 = b43_read16(dev, B43_MMIO_TSF_2);
418 v1 = b43_read16(dev, B43_MMIO_TSF_1);
419 v0 = b43_read16(dev, B43_MMIO_TSF_0);
420
421 test3 = b43_read16(dev, B43_MMIO_TSF_3);
422 test2 = b43_read16(dev, B43_MMIO_TSF_2);
423 test1 = b43_read16(dev, B43_MMIO_TSF_1);
424 } while (v3 != test3 || v2 != test2 || v1 != test1);
425
426 *tsf = v3;
427 *tsf <<= 48;
428 tmp = v2;
429 tmp <<= 32;
430 *tsf |= tmp;
431 tmp = v1;
432 tmp <<= 16;
433 *tsf |= tmp;
434 *tsf |= v0;
435 }
436}
437
438static void b43_time_lock(struct b43_wldev *dev)
439{
440 u32 macctl;
441
442 macctl = b43_read32(dev, B43_MMIO_MACCTL);
443 macctl |= B43_MACCTL_TBTTHOLD;
444 b43_write32(dev, B43_MMIO_MACCTL, macctl);
445 /* Commit the write */
446 b43_read32(dev, B43_MMIO_MACCTL);
447}
448
449static void b43_time_unlock(struct b43_wldev *dev)
450{
451 u32 macctl;
452
453 macctl = b43_read32(dev, B43_MMIO_MACCTL);
454 macctl &= ~B43_MACCTL_TBTTHOLD;
455 b43_write32(dev, B43_MMIO_MACCTL, macctl);
456 /* Commit the write */
457 b43_read32(dev, B43_MMIO_MACCTL);
458}
459
460static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
461{
462 /* Be careful with the in-progress timer.
463 * First zero out the low register, so we have a full
464 * register-overflow duration to complete the operation.
465 */
466 if (dev->dev->id.revision >= 3) {
467 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
468 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
469
470 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
471 mmiowb();
472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
473 mmiowb();
474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
475 } else {
476 u16 v0 = (tsf & 0x000000000000FFFFULL);
477 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
478 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
479 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
480
481 b43_write16(dev, B43_MMIO_TSF_0, 0);
482 mmiowb();
483 b43_write16(dev, B43_MMIO_TSF_3, v3);
484 mmiowb();
485 b43_write16(dev, B43_MMIO_TSF_2, v2);
486 mmiowb();
487 b43_write16(dev, B43_MMIO_TSF_1, v1);
488 mmiowb();
489 b43_write16(dev, B43_MMIO_TSF_0, v0);
490 }
491}
492
493void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
494{
495 b43_time_lock(dev);
496 b43_tsf_write_locked(dev, tsf);
497 b43_time_unlock(dev);
498}
499
500static
501void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
502{
503 static const u8 zero_addr[ETH_ALEN] = { 0 };
504 u16 data;
505
506 if (!mac)
507 mac = zero_addr;
508
509 offset |= 0x0020;
510 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
511
512 data = mac[0];
513 data |= mac[1] << 8;
514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
515 data = mac[2];
516 data |= mac[3] << 8;
517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 data = mac[4];
519 data |= mac[5] << 8;
520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
521}
522
523static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
524{
525 const u8 *mac;
526 const u8 *bssid;
527 u8 mac_bssid[ETH_ALEN * 2];
528 int i;
529 u32 tmp;
530
531 bssid = dev->wl->bssid;
532 mac = dev->wl->mac_addr;
533
534 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
535
536 memcpy(mac_bssid, mac, ETH_ALEN);
537 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
538
539 /* Write our MAC address and BSSID to template ram */
540 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
541 tmp = (u32) (mac_bssid[i + 0]);
542 tmp |= (u32) (mac_bssid[i + 1]) << 8;
543 tmp |= (u32) (mac_bssid[i + 2]) << 16;
544 tmp |= (u32) (mac_bssid[i + 3]) << 24;
545 b43_ram_write(dev, 0x20 + i, tmp);
546 }
547}
548
4150c572 549static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 550{
e4d6b795 551 b43_write_mac_bssid_templates(dev);
4150c572 552 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 553}
554
555static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
556{
557 /* slot_time is in usec. */
558 if (dev->phy.type != B43_PHYTYPE_G)
559 return;
560 b43_write16(dev, 0x684, 510 + slot_time);
561 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
562}
563
564static void b43_short_slot_timing_enable(struct b43_wldev *dev)
565{
566 b43_set_slot_time(dev, 9);
567 dev->short_slot = 1;
568}
569
570static void b43_short_slot_timing_disable(struct b43_wldev *dev)
571{
572 b43_set_slot_time(dev, 20);
573 dev->short_slot = 0;
574}
575
576/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
577 * Returns the _previously_ enabled IRQ mask.
578 */
579static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
580{
581 u32 old_mask;
582
583 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
584 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
585
586 return old_mask;
587}
588
589/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
590 * Returns the _previously_ enabled IRQ mask.
591 */
592static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
593{
594 u32 old_mask;
595
596 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
597 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
598
599 return old_mask;
600}
601
602/* Synchronize IRQ top- and bottom-half.
603 * IRQs must be masked before calling this.
604 * This must not be called with the irq_lock held.
605 */
606static void b43_synchronize_irq(struct b43_wldev *dev)
607{
608 synchronize_irq(dev->dev->irq);
609 tasklet_kill(&dev->isr_tasklet);
610}
611
612/* DummyTransmission function, as documented on
613 * http://bcm-specs.sipsolutions.net/DummyTransmission
614 */
615void b43_dummy_transmission(struct b43_wldev *dev)
616{
617 struct b43_phy *phy = &dev->phy;
618 unsigned int i, max_loop;
619 u16 value;
620 u32 buffer[5] = {
621 0x00000000,
622 0x00D40000,
623 0x00000000,
624 0x01000000,
625 0x00000000,
626 };
627
628 switch (phy->type) {
629 case B43_PHYTYPE_A:
630 max_loop = 0x1E;
631 buffer[0] = 0x000201CC;
632 break;
633 case B43_PHYTYPE_B:
634 case B43_PHYTYPE_G:
635 max_loop = 0xFA;
636 buffer[0] = 0x000B846E;
637 break;
638 default:
639 B43_WARN_ON(1);
640 return;
641 }
642
643 for (i = 0; i < 5; i++)
644 b43_ram_write(dev, i * 4, buffer[i]);
645
646 /* Commit writes */
647 b43_read32(dev, B43_MMIO_MACCTL);
648
649 b43_write16(dev, 0x0568, 0x0000);
650 b43_write16(dev, 0x07C0, 0x0000);
651 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
652 b43_write16(dev, 0x050C, value);
653 b43_write16(dev, 0x0508, 0x0000);
654 b43_write16(dev, 0x050A, 0x0000);
655 b43_write16(dev, 0x054C, 0x0000);
656 b43_write16(dev, 0x056A, 0x0014);
657 b43_write16(dev, 0x0568, 0x0826);
658 b43_write16(dev, 0x0500, 0x0000);
659 b43_write16(dev, 0x0502, 0x0030);
660
661 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
662 b43_radio_write16(dev, 0x0051, 0x0017);
663 for (i = 0x00; i < max_loop; i++) {
664 value = b43_read16(dev, 0x050E);
665 if (value & 0x0080)
666 break;
667 udelay(10);
668 }
669 for (i = 0x00; i < 0x0A; i++) {
670 value = b43_read16(dev, 0x050E);
671 if (value & 0x0400)
672 break;
673 udelay(10);
674 }
675 for (i = 0x00; i < 0x0A; i++) {
676 value = b43_read16(dev, 0x0690);
677 if (!(value & 0x0100))
678 break;
679 udelay(10);
680 }
681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
682 b43_radio_write16(dev, 0x0051, 0x0037);
683}
684
685static void key_write(struct b43_wldev *dev,
686 u8 index, u8 algorithm, const u8 * key)
687{
688 unsigned int i;
689 u32 offset;
690 u16 value;
691 u16 kidx;
692
693 /* Key index/algo block */
694 kidx = b43_kidx_to_fw(dev, index);
695 value = ((kidx << 4) | algorithm);
696 b43_shm_write16(dev, B43_SHM_SHARED,
697 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
698
699 /* Write the key to the Key Table Pointer offset */
700 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
701 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
702 value = key[i];
703 value |= (u16) (key[i + 1]) << 8;
704 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
705 }
706}
707
708static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
709{
710 u32 addrtmp[2] = { 0, 0, };
711 u8 per_sta_keys_start = 8;
712
713 if (b43_new_kidx_api(dev))
714 per_sta_keys_start = 4;
715
716 B43_WARN_ON(index < per_sta_keys_start);
717 /* We have two default TX keys and possibly two default RX keys.
718 * Physical mac 0 is mapped to physical key 4 or 8, depending
719 * on the firmware version.
720 * So we must adjust the index here.
721 */
722 index -= per_sta_keys_start;
723
724 if (addr) {
725 addrtmp[0] = addr[0];
726 addrtmp[0] |= ((u32) (addr[1]) << 8);
727 addrtmp[0] |= ((u32) (addr[2]) << 16);
728 addrtmp[0] |= ((u32) (addr[3]) << 24);
729 addrtmp[1] = addr[4];
730 addrtmp[1] |= ((u32) (addr[5]) << 8);
731 }
732
733 if (dev->dev->id.revision >= 5) {
734 /* Receive match transmitter address mechanism */
735 b43_shm_write32(dev, B43_SHM_RCMTA,
736 (index * 2) + 0, addrtmp[0]);
737 b43_shm_write16(dev, B43_SHM_RCMTA,
738 (index * 2) + 1, addrtmp[1]);
739 } else {
740 /* RXE (Receive Engine) and
741 * PSM (Programmable State Machine) mechanism
742 */
743 if (index < 8) {
744 /* TODO write to RCM 16, 19, 22 and 25 */
745 } else {
746 b43_shm_write32(dev, B43_SHM_SHARED,
747 B43_SHM_SH_PSM + (index * 6) + 0,
748 addrtmp[0]);
749 b43_shm_write16(dev, B43_SHM_SHARED,
750 B43_SHM_SH_PSM + (index * 6) + 4,
751 addrtmp[1]);
752 }
753 }
754}
755
756static void do_key_write(struct b43_wldev *dev,
757 u8 index, u8 algorithm,
758 const u8 * key, size_t key_len, const u8 * mac_addr)
759{
760 u8 buf[B43_SEC_KEYSIZE] = { 0, };
761 u8 per_sta_keys_start = 8;
762
763 if (b43_new_kidx_api(dev))
764 per_sta_keys_start = 4;
765
766 B43_WARN_ON(index >= dev->max_nr_keys);
767 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
768
769 if (index >= per_sta_keys_start)
770 keymac_write(dev, index, NULL); /* First zero out mac. */
771 if (key)
772 memcpy(buf, key, key_len);
773 key_write(dev, index, algorithm, buf);
774 if (index >= per_sta_keys_start)
775 keymac_write(dev, index, mac_addr);
776
777 dev->key[index].algorithm = algorithm;
778}
779
780static int b43_key_write(struct b43_wldev *dev,
781 int index, u8 algorithm,
782 const u8 * key, size_t key_len,
783 const u8 * mac_addr,
784 struct ieee80211_key_conf *keyconf)
785{
786 int i;
787 int sta_keys_start;
788
789 if (key_len > B43_SEC_KEYSIZE)
790 return -EINVAL;
791 for (i = 0; i < dev->max_nr_keys; i++) {
792 /* Check that we don't already have this key. */
793 B43_WARN_ON(dev->key[i].keyconf == keyconf);
794 }
795 if (index < 0) {
796 /* Either pairwise key or address is 00:00:00:00:00:00
797 * for transmit-only keys. Search the index. */
798 if (b43_new_kidx_api(dev))
799 sta_keys_start = 4;
800 else
801 sta_keys_start = 8;
802 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
803 if (!dev->key[i].keyconf) {
804 /* found empty */
805 index = i;
806 break;
807 }
808 }
809 if (index < 0) {
810 b43err(dev->wl, "Out of hardware key memory\n");
811 return -ENOSPC;
812 }
813 } else
814 B43_WARN_ON(index > 3);
815
816 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
817 if ((index <= 3) && !b43_new_kidx_api(dev)) {
818 /* Default RX key */
819 B43_WARN_ON(mac_addr);
820 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
821 }
822 keyconf->hw_key_idx = index;
823 dev->key[index].keyconf = keyconf;
824
825 return 0;
826}
827
828static int b43_key_clear(struct b43_wldev *dev, int index)
829{
830 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
831 return -EINVAL;
832 do_key_write(dev, index, B43_SEC_ALGO_NONE,
833 NULL, B43_SEC_KEYSIZE, NULL);
834 if ((index <= 3) && !b43_new_kidx_api(dev)) {
835 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
836 NULL, B43_SEC_KEYSIZE, NULL);
837 }
838 dev->key[index].keyconf = NULL;
839
840 return 0;
841}
842
843static void b43_clear_keys(struct b43_wldev *dev)
844{
845 int i;
846
847 for (i = 0; i < dev->max_nr_keys; i++)
848 b43_key_clear(dev, i);
849}
850
851void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
852{
853 u32 macctl;
854 u16 ucstat;
855 bool hwps;
856 bool awake;
857 int i;
858
859 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
860 (ps_flags & B43_PS_DISABLED));
861 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
862
863 if (ps_flags & B43_PS_ENABLED) {
864 hwps = 1;
865 } else if (ps_flags & B43_PS_DISABLED) {
866 hwps = 0;
867 } else {
868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
869 // and thus is not an AP and we are associated, set bit 25
870 }
871 if (ps_flags & B43_PS_AWAKE) {
872 awake = 1;
873 } else if (ps_flags & B43_PS_ASLEEP) {
874 awake = 0;
875 } else {
876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
878 // successful, set bit26
879 }
880
881/* FIXME: For now we force awake-on and hwps-off */
882 hwps = 0;
883 awake = 1;
884
885 macctl = b43_read32(dev, B43_MMIO_MACCTL);
886 if (hwps)
887 macctl |= B43_MACCTL_HWPS;
888 else
889 macctl &= ~B43_MACCTL_HWPS;
890 if (awake)
891 macctl |= B43_MACCTL_AWAKE;
892 else
893 macctl &= ~B43_MACCTL_AWAKE;
894 b43_write32(dev, B43_MMIO_MACCTL, macctl);
895 /* Commit write */
896 b43_read32(dev, B43_MMIO_MACCTL);
897 if (awake && dev->dev->id.revision >= 5) {
898 /* Wait for the microcode to wake up. */
899 for (i = 0; i < 100; i++) {
900 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
901 B43_SHM_SH_UCODESTAT);
902 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
903 break;
904 udelay(10);
905 }
906 }
907}
908
909/* Turn the Analog ON/OFF */
910static void b43_switch_analog(struct b43_wldev *dev, int on)
911{
912 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
913}
914
915void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
916{
917 u32 tmslow;
918 u32 macctl;
919
920 flags |= B43_TMSLOW_PHYCLKEN;
921 flags |= B43_TMSLOW_PHYRESET;
922 ssb_device_enable(dev->dev, flags);
923 msleep(2); /* Wait for the PLL to turn on. */
924
925 /* Now take the PHY out of Reset again */
926 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
927 tmslow |= SSB_TMSLOW_FGC;
928 tmslow &= ~B43_TMSLOW_PHYRESET;
929 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
930 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
931 msleep(1);
932 tmslow &= ~SSB_TMSLOW_FGC;
933 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
934 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
935 msleep(1);
936
937 /* Turn Analog ON */
938 b43_switch_analog(dev, 1);
939
940 macctl = b43_read32(dev, B43_MMIO_MACCTL);
941 macctl &= ~B43_MACCTL_GMODE;
942 if (flags & B43_TMSLOW_GMODE)
943 macctl |= B43_MACCTL_GMODE;
944 macctl |= B43_MACCTL_IHR_ENABLED;
945 b43_write32(dev, B43_MMIO_MACCTL, macctl);
946}
947
948static void handle_irq_transmit_status(struct b43_wldev *dev)
949{
950 u32 v0, v1;
951 u16 tmp;
952 struct b43_txstatus stat;
953
954 while (1) {
955 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
956 if (!(v0 & 0x00000001))
957 break;
958 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
959
960 stat.cookie = (v0 >> 16);
961 stat.seq = (v1 & 0x0000FFFF);
962 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
963 tmp = (v0 & 0x0000FFFF);
964 stat.frame_count = ((tmp & 0xF000) >> 12);
965 stat.rts_count = ((tmp & 0x0F00) >> 8);
966 stat.supp_reason = ((tmp & 0x001C) >> 2);
967 stat.pm_indicated = !!(tmp & 0x0080);
968 stat.intermediate = !!(tmp & 0x0040);
969 stat.for_ampdu = !!(tmp & 0x0020);
970 stat.acked = !!(tmp & 0x0002);
971
972 b43_handle_txstatus(dev, &stat);
973 }
974}
975
976static void drain_txstatus_queue(struct b43_wldev *dev)
977{
978 u32 dummy;
979
980 if (dev->dev->id.revision < 5)
981 return;
982 /* Read all entries from the microcode TXstatus FIFO
983 * and throw them away.
984 */
985 while (1) {
986 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
987 if (!(dummy & 0x00000001))
988 break;
989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
990 }
991}
992
993static u32 b43_jssi_read(struct b43_wldev *dev)
994{
995 u32 val = 0;
996
997 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
998 val <<= 16;
999 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1000
1001 return val;
1002}
1003
1004static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1005{
1006 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1008}
1009
1010static void b43_generate_noise_sample(struct b43_wldev *dev)
1011{
1012 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1013 b43_write32(dev, B43_MMIO_MACCMD,
1014 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1015 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1016}
1017
1018static void b43_calculate_link_quality(struct b43_wldev *dev)
1019{
1020 /* Top half of Link Quality calculation. */
1021
1022 if (dev->noisecalc.calculation_running)
1023 return;
1024 dev->noisecalc.channel_at_start = dev->phy.channel;
1025 dev->noisecalc.calculation_running = 1;
1026 dev->noisecalc.nr_samples = 0;
1027
1028 b43_generate_noise_sample(dev);
1029}
1030
1031static void handle_irq_noise(struct b43_wldev *dev)
1032{
1033 struct b43_phy *phy = &dev->phy;
1034 u16 tmp;
1035 u8 noise[4];
1036 u8 i, j;
1037 s32 average;
1038
1039 /* Bottom half of Link Quality calculation. */
1040
1041 B43_WARN_ON(!dev->noisecalc.calculation_running);
1042 if (dev->noisecalc.channel_at_start != phy->channel)
1043 goto drop_calculation;
1a09404a 1044 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1045 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1046 noise[2] == 0x7F || noise[3] == 0x7F)
1047 goto generate_new;
1048
1049 /* Get the noise samples. */
1050 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1051 i = dev->noisecalc.nr_samples;
1052 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1053 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1057 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1058 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1059 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1060 dev->noisecalc.nr_samples++;
1061 if (dev->noisecalc.nr_samples == 8) {
1062 /* Calculate the Link Quality by the noise samples. */
1063 average = 0;
1064 for (i = 0; i < 8; i++) {
1065 for (j = 0; j < 4; j++)
1066 average += dev->noisecalc.samples[i][j];
1067 }
1068 average /= (8 * 4);
1069 average *= 125;
1070 average += 64;
1071 average /= 128;
1072 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1073 tmp = (tmp / 128) & 0x1F;
1074 if (tmp >= 8)
1075 average += 2;
1076 else
1077 average -= 25;
1078 if (tmp == 8)
1079 average -= 72;
1080 else
1081 average -= 48;
1082
1083 dev->stats.link_noise = average;
1084 drop_calculation:
1085 dev->noisecalc.calculation_running = 0;
1086 return;
1087 }
1088 generate_new:
1089 b43_generate_noise_sample(dev);
1090}
1091
1092static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1093{
1094 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1095 ///TODO: PS TBTT
1096 } else {
1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098 b43_power_saving_ctl_bits(dev, 0);
1099 }
e4d6b795 1100 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
aa6c7ae2 1101 dev->dfq_valid = 1;
e4d6b795
MB		 1102}
1103
1104static void handle_irq_atim_end(struct b43_wldev *dev)
1105{
aa6c7ae2
MB		 1106 if (dev->dfq_valid) {
1107 b43_write32(dev, B43_MMIO_MACCMD,
1108 b43_read32(dev, B43_MMIO_MACCMD)
1109 | B43_MACCMD_DFQ_VALID);
1110 dev->dfq_valid = 0;
1111 }
e4d6b795
MB		 1112}
1113
1114static void handle_irq_pmq(struct b43_wldev *dev)
1115{
1116 u32 tmp;
1117
1118 //TODO: AP mode.
1119
1120 while (1) {
1121 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1122 if (!(tmp & 0x00000008))
1123 break;
1124 }
1125 /* 16bit write is odd, but correct. */
1126 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1127}
1128
1129static void b43_write_template_common(struct b43_wldev *dev,
1130 const u8 * data, u16 size,
1131 u16 ram_offset,
1132 u16 shm_size_offset, u8 rate)
1133{
1134 u32 i, tmp;
1135 struct b43_plcp_hdr4 plcp;
1136
1137 plcp.data = 0;
1138 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1139 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1140 ram_offset += sizeof(u32);
1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142 * So leave the first two bytes of the next write blank.
1143 */
1144 tmp = (u32) (data[0]) << 16;
1145 tmp |= (u32) (data[1]) << 24;
1146 b43_ram_write(dev, ram_offset, tmp);
1147 ram_offset += sizeof(u32);
1148 for (i = 2; i < size; i += sizeof(u32)) {
1149 tmp = (u32) (data[i + 0]);
1150 if (i + 1 < size)
1151 tmp |= (u32) (data[i + 1]) << 8;
1152 if (i + 2 < size)
1153 tmp |= (u32) (data[i + 2]) << 16;
1154 if (i + 3 < size)
1155 tmp |= (u32) (data[i + 3]) << 24;
1156 b43_ram_write(dev, ram_offset + i - 2, tmp);
1157 }
1158 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1159 size + sizeof(struct b43_plcp_hdr6));
1160}
1161
1162static void b43_write_beacon_template(struct b43_wldev *dev,
1163 u16 ram_offset,
1164 u16 shm_size_offset, u8 rate)
1165{
47f76ca3 1166 unsigned int i, len, variable_len;
e66fee6a
MB		 1167 const struct ieee80211_mgmt *bcn;
1168 const u8 *ie;
1169 bool tim_found = 0;
e4d6b795 1170
e66fee6a
MB		 1171 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1172 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1173 0x200 - sizeof(struct b43_plcp_hdr6));
e66fee6a
MB		 1174
1175 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1176 len, ram_offset, shm_size_offset, rate);
e66fee6a
MB		 1177
1178 /* Find the position of the TIM and the DTIM_period value
1179 * and write them to SHM. */
1180 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1181 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1182 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1183 uint8_t ie_id, ie_len;
1184
1185 ie_id = ie[i];
1186 ie_len = ie[i + 1];
1187 if (ie_id == 5) {
1188 u16 tim_position;
1189 u16 dtim_period;
1190 /* This is the TIM Information Element */
1191
1192 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1193 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1194 break;
1195 /* A valid TIM is at least 4 bytes long. */
1196 if (ie_len < 4)
1197 break;
1198 tim_found = 1;
1199
1200 tim_position = sizeof(struct b43_plcp_hdr6);
1201 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1202 tim_position += i;
1203
1204 dtim_period = ie[i + 3];
1205
1206 b43_shm_write16(dev, B43_SHM_SHARED,
1207 B43_SHM_SH_TIMBPOS, tim_position);
1208 b43_shm_write16(dev, B43_SHM_SHARED,
1209 B43_SHM_SH_DTIMPER, dtim_period);
1210 break;
1211 }
1212 i += ie_len + 2;
1213 }
1214 if (!tim_found) {
1215 b43warn(dev->wl, "Did not find a valid TIM IE in "
1216 "the beacon template packet. AP or IBSS operation "
1217 "may be broken.\n");
1218 }
e4d6b795
MB		 1219}
1220
1221static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1222 u16 shm_offset, u16 size, u8 rate)
1223{
1224 struct b43_plcp_hdr4 plcp;
1225 u32 tmp;
1226 __le16 dur;
1227
1228 plcp.data = 0;
1229 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1230 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1231 dev->wl->vif, size,
e4d6b795
MB		 1232 B43_RATE_TO_BASE100KBPS(rate));
1233 /* Write PLCP in two parts and timing for packet transfer */
1234 tmp = le32_to_cpu(plcp.data);
1235 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1237 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1238}
1239
1240/* Instead of using custom probe response template, this function
1241 * just patches custom beacon template by:
1242 * 1) Changing packet type
1243 * 2) Patching duration field
1244 * 3) Stripping TIM
1245 */
e66fee6a
MB		 1246static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1247 u16 *dest_size, u8 rate)
e4d6b795
MB		 1248{
1249 const u8 *src_data;
1250 u8 *dest_data;
1251 u16 src_size, elem_size, src_pos, dest_pos;
1252 __le16 dur;
1253 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1254 size_t ie_start;
1255
1256 src_size = dev->wl->current_beacon->len;
1257 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1258
e66fee6a
MB		 1259 /* Get the start offset of the variable IEs in the packet. */
1260 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1261 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1262
e66fee6a 1263 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1264 return NULL;
e4d6b795
MB		 1265
1266 dest_data = kmalloc(src_size, GFP_ATOMIC);
1267 if (unlikely(!dest_data))
1268 return NULL;
1269
e66fee6a
MB		 1270 /* Copy the static data and all Information Elements, except the TIM. */
1271 memcpy(dest_data, src_data, ie_start);
1272 src_pos = ie_start;
1273 dest_pos = ie_start;
1274 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1275 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1276 if (src_data[src_pos] == 5) {
1277 /* This is the TIM. */
1278 continue;
e4d6b795 1279 }
e66fee6a
MB		 1280 memcpy(dest_data + dest_pos, src_data + src_pos,
1281 elem_size);
1282 dest_pos += elem_size;
e4d6b795
MB		 1283 }
1284 *dest_size = dest_pos;
1285 hdr = (struct ieee80211_hdr *)dest_data;
1286
1287 /* Set the frame control. */
1288 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1289 IEEE80211_STYPE_PROBE_RESP);
1290 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1291 dev->wl->vif, *dest_size,
e4d6b795
MB		 1292 B43_RATE_TO_BASE100KBPS(rate));
1293 hdr->duration_id = dur;
1294
1295 return dest_data;
1296}
1297
1298static void b43_write_probe_resp_template(struct b43_wldev *dev,
1299 u16 ram_offset,
1300 u16 shm_size_offset, u8 rate)
1301{
e66fee6a 1302 const u8 *probe_resp_data;
e4d6b795
MB		 1303 u16 size;
1304
e66fee6a 1305 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1306 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1307 if (unlikely(!probe_resp_data))
1308 return;
1309
1310 /* Looks like PLCP headers plus packet timings are stored for
1311 * all possible basic rates
1312 */
1313 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1314 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1315 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1316 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1317
1318 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1319 b43_write_template_common(dev, probe_resp_data,
1320 size, ram_offset, shm_size_offset, rate);
1321 kfree(probe_resp_data);
1322}
1323
d4df6f1a
MB		 1324/* Asynchronously update the packet templates in template RAM.
1325 * Locking: Requires wl->irq_lock to be locked. */
e66fee6a 1326static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
e4d6b795 1327{
e66fee6a
MB		 1328 /* This is the top half of the ansynchronous beacon update.
1329 * The bottom half is the beacon IRQ.
1330 * Beacon update must be asynchronous to avoid sending an
1331 * invalid beacon. This can happen for example, if the firmware
1332 * transmits a beacon while we are updating it. */
e4d6b795 1333
e66fee6a
MB		 1334 if (wl->current_beacon)
1335 dev_kfree_skb_any(wl->current_beacon);
1336 wl->current_beacon = beacon;
1337 wl->beacon0_uploaded = 0;
1338 wl->beacon1_uploaded = 0;
e4d6b795
MB		 1339}
1340
1341static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1342{
1343 u32 tmp;
1344 u16 i, len;
1345
1346 len = min((u16) ssid_len, (u16) 0x100);
1347 for (i = 0; i < len; i += sizeof(u32)) {
1348 tmp = (u32) (ssid[i + 0]);
1349 if (i + 1 < len)
1350 tmp |= (u32) (ssid[i + 1]) << 8;
1351 if (i + 2 < len)
1352 tmp |= (u32) (ssid[i + 2]) << 16;
1353 if (i + 3 < len)
1354 tmp |= (u32) (ssid[i + 3]) << 24;
1355 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1356 }
1357 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1358}
1359
1360static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1361{
1362 b43_time_lock(dev);
1363 if (dev->dev->id.revision >= 3) {
1364 b43_write32(dev, 0x188, (beacon_int << 16));
1365 } else {
1366 b43_write16(dev, 0x606, (beacon_int >> 6));
1367 b43_write16(dev, 0x610, beacon_int);
1368 }
1369 b43_time_unlock(dev);
1370}
1371
1372static void handle_irq_beacon(struct b43_wldev *dev)
1373{
e66fee6a
MB		 1374 struct b43_wl *wl = dev->wl;
1375 u32 cmd;
e4d6b795 1376
e66fee6a 1377 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
e4d6b795
MB		 1378 return;
1379
e66fee6a 1380 /* This is the bottom half of the asynchronous beacon update. */
e4d6b795 1381
e66fee6a
MB		 1382 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1383 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1384 if (!wl->beacon0_uploaded) {
1385 b43_write_beacon_template(dev, 0x68, 0x18,
1386 B43_CCK_RATE_1MB);
1387 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1388 B43_CCK_RATE_11MB);
1389 wl->beacon0_uploaded = 1;
1390 }
1391 cmd |= B43_MACCMD_BEACON0_VALID;
e4d6b795 1392 }
e66fee6a
MB		 1393 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1394 if (!wl->beacon1_uploaded) {
1395 b43_write_beacon_template(dev, 0x468, 0x1A,
1396 B43_CCK_RATE_1MB);
1397 wl->beacon1_uploaded = 1;
1398 }
1399 cmd |= B43_MACCMD_BEACON1_VALID;
e4d6b795 1400 }
e66fee6a 1401 b43_write32(dev, B43_MMIO_MACCMD, cmd);
e4d6b795
MB		 1402}
1403
1404static void handle_irq_ucode_debug(struct b43_wldev *dev)
1405{
1406 //TODO
1407}
1408
1409/* Interrupt handler bottom-half */
1410static void b43_interrupt_tasklet(struct b43_wldev *dev)
1411{
1412 u32 reason;
1413 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1414 u32 merged_dma_reason = 0;
21954c36 1415 int i;
e4d6b795
MB		 1416 unsigned long flags;
1417
1418 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1419
1420 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1421
1422 reason = dev->irq_reason;
1423 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1424 dma_reason[i] = dev->dma_reason[i];
1425 merged_dma_reason |= dma_reason[i];
1426 }
1427
1428 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1429 b43err(dev->wl, "MAC transmission error\n");
1430
00e0b8cb 1431 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1432 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1433 rmb();
1434 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1435 atomic_set(&dev->phy.txerr_cnt,
1436 B43_PHY_TX_BADNESS_LIMIT);
1437 b43err(dev->wl, "Too many PHY TX errors, "
1438 "restarting the controller\n");
1439 b43_controller_restart(dev, "PHY TX errors");
1440 }
1441 }
e4d6b795
MB		 1442
1443 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1444 B43_DMAIRQ_NONFATALMASK))) {
1445 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1446 b43err(dev->wl, "Fatal DMA error: "
1447 "0x%08X, 0x%08X, 0x%08X, "
1448 "0x%08X, 0x%08X, 0x%08X\n",
1449 dma_reason[0], dma_reason[1],
1450 dma_reason[2], dma_reason[3],
1451 dma_reason[4], dma_reason[5]);
1452 b43_controller_restart(dev, "DMA error");
1453 mmiowb();
1454 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1455 return;
1456 }
1457 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1458 b43err(dev->wl, "DMA error: "
1459 "0x%08X, 0x%08X, 0x%08X, "
1460 "0x%08X, 0x%08X, 0x%08X\n",
1461 dma_reason[0], dma_reason[1],
1462 dma_reason[2], dma_reason[3],
1463 dma_reason[4], dma_reason[5]);
1464 }
1465 }
1466
1467 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1468 handle_irq_ucode_debug(dev);
1469 if (reason & B43_IRQ_TBTT_INDI)
1470 handle_irq_tbtt_indication(dev);
1471 if (reason & B43_IRQ_ATIM_END)
1472 handle_irq_atim_end(dev);
1473 if (reason & B43_IRQ_BEACON)
1474 handle_irq_beacon(dev);
1475 if (reason & B43_IRQ_PMQ)
1476 handle_irq_pmq(dev);
21954c36
MB		 1477 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1478 ;/* TODO */
1479 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1480 handle_irq_noise(dev);
1481
1482 /* Check the DMA reason registers for received data. */
03b29773
MB		 1483 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1484 b43_dma_rx(dev->dma.rx_ring0);
1485 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1486 b43_dma_rx(dev->dma.rx_ring3);
e4d6b795
MB		 1487 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1488 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1489 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1490 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1491
21954c36 1492 if (reason & B43_IRQ_TX_OK)
e4d6b795 1493 handle_irq_transmit_status(dev);
e4d6b795 1494
e4d6b795
MB		 1495 b43_interrupt_enable(dev, dev->irq_savedstate);
1496 mmiowb();
1497 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1498}
1499
e4d6b795
MB		 1500static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1501{
e4d6b795
MB		 1502 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1503
1504 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1505 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1506 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1507 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1508 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1509 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1510}
1511
1512/* Interrupt handler top-half */
1513static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1514{
1515 irqreturn_t ret = IRQ_NONE;
1516 struct b43_wldev *dev = dev_id;
1517 u32 reason;
1518
1519 if (!dev)
1520 return IRQ_NONE;
1521
1522 spin_lock(&dev->wl->irq_lock);
1523
1524 if (b43_status(dev) < B43_STAT_STARTED)
1525 goto out;
1526 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1527 if (reason == 0xffffffff) /* shared IRQ */
1528 goto out;
1529 ret = IRQ_HANDLED;
1530 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1531 if (!reason)
1532 goto out;
1533
1534 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1535 & 0x0001DC00;
1536 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1537 & 0x0000DC00;
1538 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1539 & 0x0000DC00;
1540 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1541 & 0x0001DC00;
1542 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1543 & 0x0000DC00;
1544 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1545 & 0x0000DC00;
1546
1547 b43_interrupt_ack(dev, reason);
1548 /* disable all IRQs. They are enabled again in the bottom half. */
1549 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1550 /* save the reason code and call our bottom half. */
1551 dev->irq_reason = reason;
1552 tasklet_schedule(&dev->isr_tasklet);
1553 out:
1554 mmiowb();
1555 spin_unlock(&dev->wl->irq_lock);
1556
1557 return ret;
1558}
1559
1560static void b43_release_firmware(struct b43_wldev *dev)
1561{
1562 release_firmware(dev->fw.ucode);
1563 dev->fw.ucode = NULL;
1564 release_firmware(dev->fw.pcm);
1565 dev->fw.pcm = NULL;
1566 release_firmware(dev->fw.initvals);
1567 dev->fw.initvals = NULL;
1568 release_firmware(dev->fw.initvals_band);
1569 dev->fw.initvals_band = NULL;
1570}
1571
eb189d8b 1572static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1573{
eb189d8b
MB		 1574 const char *text;
1575
1576 text = "You must go to "
354807e0 1577 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 1578 "and download the latest firmware (version 4).\n";
1579 if (error)
1580 b43err(wl, text);
1581 else
1582 b43warn(wl, text);
e4d6b795
MB		 1583}
1584
1585static int do_request_fw(struct b43_wldev *dev,
1586 const char *name,
1587 const struct firmware **fw)
1588{
1a09404a 1589 char path[sizeof(modparam_fwpostfix) + 32];
e4d6b795
MB		 1590 struct b43_fw_header *hdr;
1591 u32 size;
1592 int err;
1593
1594 if (!name)
1595 return 0;
1596
1597 snprintf(path, ARRAY_SIZE(path),
1598 "b43%s/%s.fw",
1599 modparam_fwpostfix, name);
1600 err = request_firmware(fw, path, dev->dev->dev);
1601 if (err) {
1602 b43err(dev->wl, "Firmware file \"%s\" not found "
1603 "or load failed.\n", path);
1604 return err;
1605 }
1606 if ((*fw)->size < sizeof(struct b43_fw_header))
1607 goto err_format;
1608 hdr = (struct b43_fw_header *)((*fw)->data);
1609 switch (hdr->type) {
1610 case B43_FW_TYPE_UCODE:
1611 case B43_FW_TYPE_PCM:
1612 size = be32_to_cpu(hdr->size);
1613 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1614 goto err_format;
1615 /* fallthrough */
1616 case B43_FW_TYPE_IV:
1617 if (hdr->ver != 1)
1618 goto err_format;
1619 break;
1620 default:
1621 goto err_format;
1622 }
1623
1624 return err;
1625
1626err_format:
1627 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1628 return -EPROTO;
1629}
1630
1631static int b43_request_firmware(struct b43_wldev *dev)
1632{
1633 struct b43_firmware *fw = &dev->fw;
1634 const u8 rev = dev->dev->id.revision;
1635 const char *filename;
1636 u32 tmshigh;
1637 int err;
1638
1639 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1640 if (!fw->ucode) {
1641 if ((rev >= 5) && (rev <= 10))
1642 filename = "ucode5";
1643 else if ((rev >= 11) && (rev <= 12))
1644 filename = "ucode11";
1645 else if (rev >= 13)
1646 filename = "ucode13";
1647 else
1648 goto err_no_ucode;
1649 err = do_request_fw(dev, filename, &fw->ucode);
1650 if (err)
1651 goto err_load;
1652 }
1653 if (!fw->pcm) {
1654 if ((rev >= 5) && (rev <= 10))
1655 filename = "pcm5";
1656 else if (rev >= 11)
1657 filename = NULL;
1658 else
1659 goto err_no_pcm;
1660 err = do_request_fw(dev, filename, &fw->pcm);
1661 if (err)
1662 goto err_load;
1663 }
1664 if (!fw->initvals) {
1665 switch (dev->phy.type) {
1666 case B43_PHYTYPE_A:
1667 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1668 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1669 filename = "a0g1initvals5";
1670 else
1671 filename = "a0g0initvals5";
1672 } else
1673 goto err_no_initvals;
1674 break;
1675 case B43_PHYTYPE_G:
1676 if ((rev >= 5) && (rev <= 10))
1677 filename = "b0g0initvals5";
1678 else if (rev >= 13)
1679 filename = "lp0initvals13";
1680 else
1681 goto err_no_initvals;
1682 break;
dd0d43ea
MB		 1683 case B43_PHYTYPE_N:
1684 if ((rev >= 11) && (rev <= 12))
1685 filename = "n0initvals11";
1686 else
1687 goto err_no_initvals;
1688 break;
e4d6b795
MB		 1689 default:
1690 goto err_no_initvals;
1691 }
1692 err = do_request_fw(dev, filename, &fw->initvals);
1693 if (err)
1694 goto err_load;
1695 }
1696 if (!fw->initvals_band) {
1697 switch (dev->phy.type) {
1698 case B43_PHYTYPE_A:
1699 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1700 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1701 filename = "a0g1bsinitvals5";
1702 else
1703 filename = "a0g0bsinitvals5";
1704 } else if (rev >= 11)
1705 filename = NULL;
1706 else
1707 goto err_no_initvals;
1708 break;
1709 case B43_PHYTYPE_G:
1710 if ((rev >= 5) && (rev <= 10))
1711 filename = "b0g0bsinitvals5";
1712 else if (rev >= 11)
1713 filename = NULL;
1714 else
1715 goto err_no_initvals;
1716 break;
dd0d43ea
MB		 1717 case B43_PHYTYPE_N:
1718 if ((rev >= 11) && (rev <= 12))
1719 filename = "n0bsinitvals11";
1720 else
1721 goto err_no_initvals;
1722 break;
e4d6b795
MB		 1723 default:
1724 goto err_no_initvals;
1725 }
1726 err = do_request_fw(dev, filename, &fw->initvals_band);
1727 if (err)
1728 goto err_load;
1729 }
1730
1731 return 0;
1732
1733err_load:
eb189d8b 1734 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 1735 goto error;
1736
1737err_no_ucode:
1738 err = -ENODEV;
1739 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1740 goto error;
1741
1742err_no_pcm:
1743 err = -ENODEV;
1744 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1745 goto error;
1746
1747err_no_initvals:
1748 err = -ENODEV;
1749 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1750 "core rev %u\n", dev->phy.type, rev);
1751 goto error;
1752
1753error:
1754 b43_release_firmware(dev);
1755 return err;
1756}
1757
1758static int b43_upload_microcode(struct b43_wldev *dev)
1759{
1760 const size_t hdr_len = sizeof(struct b43_fw_header);
1761 const __be32 *data;
1762 unsigned int i, len;
1763 u16 fwrev, fwpatch, fwdate, fwtime;
1764 u32 tmp;
1765 int err = 0;
1766
1767 /* Upload Microcode. */
1768 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1769 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1770 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1771 for (i = 0; i < len; i++) {
1772 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1773 udelay(10);
1774 }
1775
1776 if (dev->fw.pcm) {
1777 /* Upload PCM data. */
1778 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1779 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1780 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1781 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1782 /* No need for autoinc bit in SHM_HW */
1783 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1784 for (i = 0; i < len; i++) {
1785 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1786 udelay(10);
1787 }
1788 }
1789
1790 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1791 b43_write32(dev, B43_MMIO_MACCTL,
1792 B43_MACCTL_PSM_RUN |
1793 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1794
1795 /* Wait for the microcode to load and respond */
1796 i = 0;
1797 while (1) {
1798 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1799 if (tmp == B43_IRQ_MAC_SUSPENDED)
1800 break;
1801 i++;
1802 if (i >= 50) {
1803 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 1804 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 1805 err = -ENODEV;
1806 goto out;
1807 }
1808 udelay(10);
1809 }
1810 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1811
1812 /* Get and check the revisions. */
1813 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1814 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1815 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1816 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1817
1818 if (fwrev <= 0x128) {
1819 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1820 "binary drivers older than version 4.x is unsupported. "
1821 "You must upgrade your firmware files.\n");
eb189d8b 1822 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 1823 b43_write32(dev, B43_MMIO_MACCTL, 0);
1824 err = -EOPNOTSUPP;
1825 goto out;
1826 }
1827 b43dbg(dev->wl, "Loading firmware version %u.%u "
1828 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1829 fwrev, fwpatch,
1830 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1831 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1832
1833 dev->fw.rev = fwrev;
1834 dev->fw.patch = fwpatch;
1835
eb189d8b
MB		 1836 if (b43_is_old_txhdr_format(dev)) {
1837 b43warn(dev->wl, "You are using an old firmware image. "
1838 "Support for old firmware will be removed in July 2008.\n");
1839 b43_print_fw_helptext(dev->wl, 0);
1840 }
1841
1842out:
e4d6b795
MB		 1843 return err;
1844}
1845
1846static int b43_write_initvals(struct b43_wldev *dev,
1847 const struct b43_iv *ivals,
1848 size_t count,
1849 size_t array_size)
1850{
1851 const struct b43_iv *iv;
1852 u16 offset;
1853 size_t i;
1854 bool bit32;
1855
1856 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1857 iv = ivals;
1858 for (i = 0; i < count; i++) {
1859 if (array_size < sizeof(iv->offset_size))
1860 goto err_format;
1861 array_size -= sizeof(iv->offset_size);
1862 offset = be16_to_cpu(iv->offset_size);
1863 bit32 = !!(offset & B43_IV_32BIT);
1864 offset &= B43_IV_OFFSET_MASK;
1865 if (offset >= 0x1000)
1866 goto err_format;
1867 if (bit32) {
1868 u32 value;
1869
1870 if (array_size < sizeof(iv->data.d32))
1871 goto err_format;
1872 array_size -= sizeof(iv->data.d32);
1873
1874 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1875 b43_write32(dev, offset, value);
1876
1877 iv = (const struct b43_iv *)((const uint8_t *)iv +
1878 sizeof(__be16) +
1879 sizeof(__be32));
1880 } else {
1881 u16 value;
1882
1883 if (array_size < sizeof(iv->data.d16))
1884 goto err_format;
1885 array_size -= sizeof(iv->data.d16);
1886
1887 value = be16_to_cpu(iv->data.d16);
1888 b43_write16(dev, offset, value);
1889
1890 iv = (const struct b43_iv *)((const uint8_t *)iv +
1891 sizeof(__be16) +
1892 sizeof(__be16));
1893 }
1894 }
1895 if (array_size)
1896 goto err_format;
1897
1898 return 0;
1899
1900err_format:
1901 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 1902 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 1903
1904 return -EPROTO;
1905}
1906
1907static int b43_upload_initvals(struct b43_wldev *dev)
1908{
1909 const size_t hdr_len = sizeof(struct b43_fw_header);
1910 const struct b43_fw_header *hdr;
1911 struct b43_firmware *fw = &dev->fw;
1912 const struct b43_iv *ivals;
1913 size_t count;
1914 int err;
1915
1916 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1917 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1918 count = be32_to_cpu(hdr->size);
1919 err = b43_write_initvals(dev, ivals, count,
1920 fw->initvals->size - hdr_len);
1921 if (err)
1922 goto out;
1923 if (fw->initvals_band) {
1924 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1925 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1926 count = be32_to_cpu(hdr->size);
1927 err = b43_write_initvals(dev, ivals, count,
1928 fw->initvals_band->size - hdr_len);
1929 if (err)
1930 goto out;
1931 }
1932out:
1933
1934 return err;
1935}
1936
1937/* Initialize the GPIOs
1938 * http://bcm-specs.sipsolutions.net/GPIO
1939 */
1940static int b43_gpio_init(struct b43_wldev *dev)
1941{
1942 struct ssb_bus *bus = dev->dev->bus;
1943 struct ssb_device *gpiodev, *pcidev = NULL;
1944 u32 mask, set;
1945
1946 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1947 & ~B43_MACCTL_GPOUTSMSK);
1948
e4d6b795
MB		 1949 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1950 | 0x000F);
1951
1952 mask = 0x0000001F;
1953 set = 0x0000000F;
1954 if (dev->dev->bus->chip_id == 0x4301) {
1955 mask |= 0x0060;
1956 set |= 0x0060;
1957 }
1958 if (0 /* FIXME: conditional unknown */ ) {
1959 b43_write16(dev, B43_MMIO_GPIO_MASK,
1960 b43_read16(dev, B43_MMIO_GPIO_MASK)
1961 | 0x0100);
1962 mask |= 0x0180;
1963 set |= 0x0180;
1964 }
95de2841 1965 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 1966 b43_write16(dev, B43_MMIO_GPIO_MASK,
1967 b43_read16(dev, B43_MMIO_GPIO_MASK)
1968 | 0x0200);
1969 mask |= 0x0200;
1970 set |= 0x0200;
1971 }
1972 if (dev->dev->id.revision >= 2)
1973 mask |= 0x0010; /* FIXME: This is redundant. */
1974
1975#ifdef CONFIG_SSB_DRIVER_PCICORE
1976 pcidev = bus->pcicore.dev;
1977#endif
1978 gpiodev = bus->chipco.dev ? : pcidev;
1979 if (!gpiodev)
1980 return 0;
1981 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1982 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1983 & mask) | set);
1984
1985 return 0;
1986}
1987
1988/* Turn off all GPIO stuff. Call this on module unload, for example. */
1989static void b43_gpio_cleanup(struct b43_wldev *dev)
1990{
1991 struct ssb_bus *bus = dev->dev->bus;
1992 struct ssb_device *gpiodev, *pcidev = NULL;
1993
1994#ifdef CONFIG_SSB_DRIVER_PCICORE
1995 pcidev = bus->pcicore.dev;
1996#endif
1997 gpiodev = bus->chipco.dev ? : pcidev;
1998 if (!gpiodev)
1999 return;
2000 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2001}
2002
2003/* http://bcm-specs.sipsolutions.net/EnableMac */
2004void b43_mac_enable(struct b43_wldev *dev)
2005{
2006 dev->mac_suspended--;
2007 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2008 B43_WARN_ON(irqs_disabled());
e4d6b795
MB		 2009 if (dev->mac_suspended == 0) {
2010 b43_write32(dev, B43_MMIO_MACCTL,
2011 b43_read32(dev, B43_MMIO_MACCTL)
2012 | B43_MACCTL_ENABLED);
2013 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2014 B43_IRQ_MAC_SUSPENDED);
2015 /* Commit writes */
2016 b43_read32(dev, B43_MMIO_MACCTL);
2017 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2018 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 2019
2020 /* Re-enable IRQs. */
2021 spin_lock_irq(&dev->wl->irq_lock);
2022 b43_interrupt_enable(dev, dev->irq_savedstate);
2023 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 2024 }
2025}
2026
2027/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2028void b43_mac_suspend(struct b43_wldev *dev)
2029{
2030 int i;
2031 u32 tmp;
2032
05b64b36
MB		 2033 might_sleep();
2034 B43_WARN_ON(irqs_disabled());
e4d6b795 2035 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2036
e4d6b795 2037 if (dev->mac_suspended == 0) {
05b64b36
MB		 2038 /* Mask IRQs before suspending MAC. Otherwise
2039 * the MAC stays busy and won't suspend. */
2040 spin_lock_irq(&dev->wl->irq_lock);
2041 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2042 spin_unlock_irq(&dev->wl->irq_lock);
2043 b43_synchronize_irq(dev);
2044 dev->irq_savedstate = tmp;
2045
e4d6b795
MB		 2046 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2047 b43_write32(dev, B43_MMIO_MACCTL,
2048 b43_read32(dev, B43_MMIO_MACCTL)
2049 & ~B43_MACCTL_ENABLED);
2050 /* force pci to flush the write */
2051 b43_read32(dev, B43_MMIO_MACCTL);
05b64b36 2052 for (i = 40; i; i--) {
e4d6b795
MB		 2053 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2054 if (tmp & B43_IRQ_MAC_SUSPENDED)
2055 goto out;
05b64b36 2056 msleep(1);
e4d6b795
MB		 2057 }
2058 b43err(dev->wl, "MAC suspend failed\n");
2059 }
05b64b36 2060out:
e4d6b795
MB		 2061 dev->mac_suspended++;
2062}
2063
2064static void b43_adjust_opmode(struct b43_wldev *dev)
2065{
2066 struct b43_wl *wl = dev->wl;
2067 u32 ctl;
2068 u16 cfp_pretbtt;
2069
2070 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2071 /* Reset status to STA infrastructure mode. */
2072 ctl &= ~B43_MACCTL_AP;
2073 ctl &= ~B43_MACCTL_KEEP_CTL;
2074 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2075 ctl &= ~B43_MACCTL_KEEP_BAD;
2076 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2077 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2078 ctl |= B43_MACCTL_INFRA;
2079
4150c572
JB		 2080 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2081 ctl |= B43_MACCTL_AP;
2082 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2083 ctl &= ~B43_MACCTL_INFRA;
2084
2085 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2086 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2087 if (wl->filter_flags & FIF_FCSFAIL)
2088 ctl |= B43_MACCTL_KEEP_BAD;
2089 if (wl->filter_flags & FIF_PLCPFAIL)
2090 ctl |= B43_MACCTL_KEEP_BADPLCP;
2091 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2092 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2093 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2094 ctl |= B43_MACCTL_BEACPROMISC;
2095
e4d6b795
MB		 2096 /* Workaround: On old hardware the HW-MAC-address-filter
2097 * doesn't work properly, so always run promisc in filter
2098 * it in software. */
2099 if (dev->dev->id.revision <= 4)
2100 ctl |= B43_MACCTL_PROMISC;
2101
2102 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2103
2104 cfp_pretbtt = 2;
2105 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2106 if (dev->dev->bus->chip_id == 0x4306 &&
2107 dev->dev->bus->chip_rev == 3)
2108 cfp_pretbtt = 100;
2109 else
2110 cfp_pretbtt = 50;
2111 }
2112 b43_write16(dev, 0x612, cfp_pretbtt);
2113}
2114
2115static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2116{
2117 u16 offset;
2118
2119 if (is_ofdm) {
2120 offset = 0x480;
2121 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2122 } else {
2123 offset = 0x4C0;
2124 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2125 }
2126 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2127 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2128}
2129
2130static void b43_rate_memory_init(struct b43_wldev *dev)
2131{
2132 switch (dev->phy.type) {
2133 case B43_PHYTYPE_A:
2134 case B43_PHYTYPE_G:
2135 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2136 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2137 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2138 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2139 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2140 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2141 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2142 if (dev->phy.type == B43_PHYTYPE_A)
2143 break;
2144 /* fallthrough */
2145 case B43_PHYTYPE_B:
2146 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2147 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2148 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2149 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2150 break;
2151 default:
2152 B43_WARN_ON(1);
2153 }
2154}
2155
2156/* Set the TX-Antenna for management frames sent by firmware. */
2157static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2158{
2159 u16 ant = 0;
2160 u16 tmp;
2161
2162 switch (antenna) {
2163 case B43_ANTENNA0:
eb189d8b 2164 ant |= B43_TXH_PHY_ANT0;
e4d6b795
MB		 2165 break;
2166 case B43_ANTENNA1:
eb189d8b
MB		 2167 ant |= B43_TXH_PHY_ANT1;
2168 break;
2169 case B43_ANTENNA2:
2170 ant |= B43_TXH_PHY_ANT2;
2171 break;
2172 case B43_ANTENNA3:
2173 ant |= B43_TXH_PHY_ANT3;
e4d6b795
MB		 2174 break;
2175 case B43_ANTENNA_AUTO:
eb189d8b 2176 ant |= B43_TXH_PHY_ANT01AUTO;
e4d6b795
MB		 2177 break;
2178 default:
2179 B43_WARN_ON(1);
2180 }
2181
2182 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2183
2184 /* For Beacons */
2185 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
eb189d8b 2186 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2187 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2188 /* For ACK/CTS */
2189 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2190 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2191 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2192 /* For Probe Resposes */
2193 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2194 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2195 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2196}
2197
2198/* This is the opposite of b43_chip_init() */
2199static void b43_chip_exit(struct b43_wldev *dev)
2200{
8e9f7529 2201 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 2202 b43_gpio_cleanup(dev);
2203 /* firmware is released later */
2204}
2205
2206/* Initialize the chip
2207 * http://bcm-specs.sipsolutions.net/ChipInit
2208 */
2209static int b43_chip_init(struct b43_wldev *dev)
2210{
2211 struct b43_phy *phy = &dev->phy;
2212 int err, tmp;
2213 u32 value32;
2214 u16 value16;
2215
2216 b43_write32(dev, B43_MMIO_MACCTL,
2217 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2218
2219 err = b43_request_firmware(dev);
2220 if (err)
2221 goto out;
2222 err = b43_upload_microcode(dev);
2223 if (err)
2224 goto out; /* firmware is released later */
2225
2226 err = b43_gpio_init(dev);
2227 if (err)
2228 goto out; /* firmware is released later */
21954c36 2229
e4d6b795
MB		 2230 err = b43_upload_initvals(dev);
2231 if (err)
1a8d1227 2232 goto err_gpio_clean;
e4d6b795 2233 b43_radio_turn_on(dev);
e4d6b795
MB		 2234
2235 b43_write16(dev, 0x03E6, 0x0000);
2236 err = b43_phy_init(dev);
2237 if (err)
2238 goto err_radio_off;
2239
2240 /* Select initial Interference Mitigation. */
2241 tmp = phy->interfmode;
2242 phy->interfmode = B43_INTERFMODE_NONE;
2243 b43_radio_set_interference_mitigation(dev, tmp);
2244
2245 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2246 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2247
2248 if (phy->type == B43_PHYTYPE_B) {
2249 value16 = b43_read16(dev, 0x005E);
2250 value16 |= 0x0004;
2251 b43_write16(dev, 0x005E, value16);
2252 }
2253 b43_write32(dev, 0x0100, 0x01000000);
2254 if (dev->dev->id.revision < 5)
2255 b43_write32(dev, 0x010C, 0x01000000);
2256
2257 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2258 & ~B43_MACCTL_INFRA);
2259 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2260 | B43_MACCTL_INFRA);
e4d6b795 2261
e4d6b795
MB		 2262 /* Probe Response Timeout value */
2263 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2264 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2265
2266 /* Initially set the wireless operation mode. */
2267 b43_adjust_opmode(dev);
2268
2269 if (dev->dev->id.revision < 3) {
2270 b43_write16(dev, 0x060E, 0x0000);
2271 b43_write16(dev, 0x0610, 0x8000);
2272 b43_write16(dev, 0x0604, 0x0000);
2273 b43_write16(dev, 0x0606, 0x0200);
2274 } else {
2275 b43_write32(dev, 0x0188, 0x80000000);
2276 b43_write32(dev, 0x018C, 0x02000000);
2277 }
2278 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2279 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2280 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2281 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2282 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2283 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2284 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2285
2286 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2287 value32 |= 0x00100000;
2288 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2289
2290 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2291 dev->dev->bus->chipco.fast_pwrup_delay);
2292
2293 err = 0;
2294 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2295out:
e4d6b795
MB		 2296 return err;
2297
21954c36 2298err_radio_off:
8e9f7529 2299 b43_radio_turn_off(dev, 1);
1a8d1227 2300err_gpio_clean:
e4d6b795 2301 b43_gpio_cleanup(dev);
21954c36 2302 return err;
e4d6b795
MB		 2303}
2304
2305static void b43_periodic_every120sec(struct b43_wldev *dev)
2306{
2307 struct b43_phy *phy = &dev->phy;
2308
2309 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2310 return;
2311
2312 b43_mac_suspend(dev);
2313 b43_lo_g_measure(dev);
2314 b43_mac_enable(dev);
2315 if (b43_has_hardware_pctl(phy))
2316 b43_lo_g_ctl_mark_all_unused(dev);
2317}
2318
2319static void b43_periodic_every60sec(struct b43_wldev *dev)
2320{
2321 struct b43_phy *phy = &dev->phy;
2322
2323 if (!b43_has_hardware_pctl(phy))
2324 b43_lo_g_ctl_mark_all_unused(dev);
95de2841 2325 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
e4d6b795
MB		 2326 b43_mac_suspend(dev);
2327 b43_calc_nrssi_slope(dev);
2328 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2329 u8 old_chan = phy->channel;
2330
2331 /* VCO Calibration */
2332 if (old_chan >= 8)
2333 b43_radio_selectchannel(dev, 1, 0);
2334 else
2335 b43_radio_selectchannel(dev, 13, 0);
2336 b43_radio_selectchannel(dev, old_chan, 0);
2337 }
2338 b43_mac_enable(dev);
2339 }
2340}
2341
2342static void b43_periodic_every30sec(struct b43_wldev *dev)
2343{
2344 /* Update device statistics. */
2345 b43_calculate_link_quality(dev);
2346}
2347
2348static void b43_periodic_every15sec(struct b43_wldev *dev)
2349{
2350 struct b43_phy *phy = &dev->phy;
2351
2352 if (phy->type == B43_PHYTYPE_G) {
2353 //TODO: update_aci_moving_average
2354 if (phy->aci_enable && phy->aci_wlan_automatic) {
2355 b43_mac_suspend(dev);
2356 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2357 if (0 /*TODO: bunch of conditions */ ) {
2358 b43_radio_set_interference_mitigation
2359 (dev, B43_INTERFMODE_MANUALWLAN);
2360 }
2361 } else if (1 /*TODO*/) {
2362 /*
2363 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2364 b43_radio_set_interference_mitigation(dev,
2365 B43_INTERFMODE_NONE);
2366 }
2367 */
2368 }
2369 b43_mac_enable(dev);
2370 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2371 phy->rev == 1) {
2372 //TODO: implement rev1 workaround
2373 }
2374 }
2375 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2376 //TODO for APHY (temperature?)
00e0b8cb
SB		 2377
2378 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2379 wmb();
e4d6b795
MB		 2380}
2381
e4d6b795
MB		 2382static void do_periodic_work(struct b43_wldev *dev)
2383{
2384 unsigned int state;
2385
2386 state = dev->periodic_state;
42bb4cd5 2387 if (state % 8 == 0)
e4d6b795 2388 b43_periodic_every120sec(dev);
42bb4cd5 2389 if (state % 4 == 0)
e4d6b795 2390 b43_periodic_every60sec(dev);
42bb4cd5 2391 if (state % 2 == 0)
e4d6b795 2392 b43_periodic_every30sec(dev);
42bb4cd5 2393 b43_periodic_every15sec(dev);
e4d6b795
MB		 2394}
2395
05b64b36
MB		 2396/* Periodic work locking policy:
2397 * The whole periodic work handler is protected by
2398 * wl->mutex. If another lock is needed somewhere in the
2399 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2400 */
e4d6b795
MB		 2401static void b43_periodic_work_handler(struct work_struct *work)
2402{
05b64b36
MB		 2403 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2404 periodic_work.work);
2405 struct b43_wl *wl = dev->wl;
2406 unsigned long delay;
e4d6b795 2407
05b64b36 2408 mutex_lock(&wl->mutex);
e4d6b795
MB		 2409
2410 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2411 goto out;
2412 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2413 goto out_requeue;
2414
05b64b36 2415 do_periodic_work(dev);
e4d6b795 2416
e4d6b795 2417 dev->periodic_state++;
42bb4cd5 2418out_requeue:
e4d6b795
MB		 2419 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2420 delay = msecs_to_jiffies(50);
2421 else
82cd682d 2422 delay = round_jiffies_relative(HZ * 15);
05b64b36 2423 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2424out:
05b64b36 2425 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2426}
2427
2428static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2429{
2430 struct delayed_work *work = &dev->periodic_work;
2431
2432 dev->periodic_state = 0;
2433 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2434 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2435}
2436
f3dd3fcc 2437/* Check if communication with the device works correctly. */
e4d6b795
MB		 2438static int b43_validate_chipaccess(struct b43_wldev *dev)
2439{
f3dd3fcc 2440 u32 v, backup;
e4d6b795 2441
f3dd3fcc
MB		 2442 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2443
2444 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2445 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2446 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2447 goto error;
f3dd3fcc
MB		 2448 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2449 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2450 goto error;
2451
f3dd3fcc
MB		 2452 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2453
2454 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2455 /* The 32bit register shadows the two 16bit registers
2456 * with update sideeffects. Validate this. */
2457 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2458 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2459 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2460 goto error;
2461 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2462 goto error;
2463 }
2464 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2465
2466 v = b43_read32(dev, B43_MMIO_MACCTL);
2467 v |= B43_MACCTL_GMODE;
2468 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2469 goto error;
2470
2471 return 0;
f3dd3fcc 2472error:
e4d6b795
MB		 2473 b43err(dev->wl, "Failed to validate the chipaccess\n");
2474 return -ENODEV;
2475}
2476
2477static void b43_security_init(struct b43_wldev *dev)
2478{
2479 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2480 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2481 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2482 /* KTP is a word address, but we address SHM bytewise.
2483 * So multiply by two.
2484 */
2485 dev->ktp *= 2;
2486 if (dev->dev->id.revision >= 5) {
2487 /* Number of RCMTA address slots */
2488 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2489 }
2490 b43_clear_keys(dev);
2491}
2492
2493static int b43_rng_read(struct hwrng *rng, u32 * data)
2494{
2495 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2496 unsigned long flags;
2497
2498 /* Don't take wl->mutex here, as it could deadlock with
2499 * hwrng internal locking. It's not needed to take
2500 * wl->mutex here, anyway. */
2501
2502 spin_lock_irqsave(&wl->irq_lock, flags);
2503 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2504 spin_unlock_irqrestore(&wl->irq_lock, flags);
2505
2506 return (sizeof(u16));
2507}
2508
2509static void b43_rng_exit(struct b43_wl *wl)
2510{
2511 if (wl->rng_initialized)
2512 hwrng_unregister(&wl->rng);
2513}
2514
2515static int b43_rng_init(struct b43_wl *wl)
2516{
2517 int err;
2518
2519 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2520 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2521 wl->rng.name = wl->rng_name;
2522 wl->rng.data_read = b43_rng_read;
2523 wl->rng.priv = (unsigned long)wl;
2524 wl->rng_initialized = 1;
2525 err = hwrng_register(&wl->rng);
2526 if (err) {
2527 wl->rng_initialized = 0;
2528 b43err(wl, "Failed to register the random "
2529 "number generator (%d)\n", err);
2530 }
2531
2532 return err;
2533}
2534
40faacc4
MB		 2535static int b43_op_tx(struct ieee80211_hw *hw,
2536 struct sk_buff *skb,
2537 struct ieee80211_tx_control *ctl)
e4d6b795
MB		 2538{
2539 struct b43_wl *wl = hw_to_b43_wl(hw);
2540 struct b43_wldev *dev = wl->current_dev;
2541 int err = -ENODEV;
e4d6b795
MB		 2542
2543 if (unlikely(!dev))
2544 goto out;
2545 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2546 goto out;
2547 /* DMA-TX is done without a global lock. */
03b29773 2548 err = b43_dma_tx(dev, skb, ctl);
40faacc4 2549out:
e4d6b795
MB		 2550 if (unlikely(err))
2551 return NETDEV_TX_BUSY;
2552 return NETDEV_TX_OK;
2553}
2554
40faacc4
MB		 2555static int b43_op_conf_tx(struct ieee80211_hw *hw,
2556 int queue,
2557 const struct ieee80211_tx_queue_params *params)
e4d6b795
MB		 2558{
2559 return 0;
2560}
2561
40faacc4
MB		 2562static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2563 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 2564{
2565 struct b43_wl *wl = hw_to_b43_wl(hw);
2566 struct b43_wldev *dev = wl->current_dev;
2567 unsigned long flags;
2568 int err = -ENODEV;
2569
2570 if (!dev)
2571 goto out;
2572 spin_lock_irqsave(&wl->irq_lock, flags);
2573 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
03b29773 2574 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 2575 err = 0;
2576 }
2577 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 2578out:
e4d6b795
MB		 2579 return err;
2580}
2581
40faacc4
MB		 2582static int b43_op_get_stats(struct ieee80211_hw *hw,
2583 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 2584{
2585 struct b43_wl *wl = hw_to_b43_wl(hw);
2586 unsigned long flags;
2587
2588 spin_lock_irqsave(&wl->irq_lock, flags);
2589 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2590 spin_unlock_irqrestore(&wl->irq_lock, flags);
2591
2592 return 0;
2593}
2594
2595static const char *phymode_to_string(unsigned int phymode)
2596{
2597 switch (phymode) {
2598 case B43_PHYMODE_A:
2599 return "A";
2600 case B43_PHYMODE_B:
2601 return "B";
2602 case B43_PHYMODE_G:
2603 return "G";
2604 default:
2605 B43_WARN_ON(1);
2606 }
2607 return "";
2608}
2609
2610static int find_wldev_for_phymode(struct b43_wl *wl,
2611 unsigned int phymode,
2612 struct b43_wldev **dev, bool * gmode)
2613{
2614 struct b43_wldev *d;
2615
2616 list_for_each_entry(d, &wl->devlist, list) {
2617 if (d->phy.possible_phymodes & phymode) {
2618 /* Ok, this device supports the PHY-mode.
2619 * Now figure out how the gmode bit has to be
2620 * set to support it. */
2621 if (phymode == B43_PHYMODE_A)
2622 *gmode = 0;
2623 else
2624 *gmode = 1;
2625 *dev = d;
2626
2627 return 0;
2628 }
2629 }
2630
2631 return -ESRCH;
2632}
2633
2634static void b43_put_phy_into_reset(struct b43_wldev *dev)
2635{
2636 struct ssb_device *sdev = dev->dev;
2637 u32 tmslow;
2638
2639 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2640 tmslow &= ~B43_TMSLOW_GMODE;
2641 tmslow |= B43_TMSLOW_PHYRESET;
2642 tmslow |= SSB_TMSLOW_FGC;
2643 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2644 msleep(1);
2645
2646 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2647 tmslow &= ~SSB_TMSLOW_FGC;
2648 tmslow |= B43_TMSLOW_PHYRESET;
2649 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2650 msleep(1);
2651}
2652
2653/* Expects wl->mutex locked */
2654static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2655{
2656 struct b43_wldev *up_dev;
2657 struct b43_wldev *down_dev;
2658 int err;
2659 bool gmode = 0;
2660 int prev_status;
2661
2662 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2663 if (err) {
2664 b43err(wl, "Could not find a device for %s-PHY mode\n",
2665 phymode_to_string(new_mode));
2666 return err;
2667 }
2668 if ((up_dev == wl->current_dev) &&
2669 (!!wl->current_dev->phy.gmode == !!gmode)) {
2670 /* This device is already running. */
2671 return 0;
2672 }
2673 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2674 phymode_to_string(new_mode));
2675 down_dev = wl->current_dev;
2676
2677 prev_status = b43_status(down_dev);
2678 /* Shutdown the currently running core. */
2679 if (prev_status >= B43_STAT_STARTED)
2680 b43_wireless_core_stop(down_dev);
2681 if (prev_status >= B43_STAT_INITIALIZED)
2682 b43_wireless_core_exit(down_dev);
2683
2684 if (down_dev != up_dev) {
2685 /* We switch to a different core, so we put PHY into
2686 * RESET on the old core. */
2687 b43_put_phy_into_reset(down_dev);
2688 }
2689
2690 /* Now start the new core. */
2691 up_dev->phy.gmode = gmode;
2692 if (prev_status >= B43_STAT_INITIALIZED) {
2693 err = b43_wireless_core_init(up_dev);
2694 if (err) {
2695 b43err(wl, "Fatal: Could not initialize device for "
2696 "newly selected %s-PHY mode\n",
2697 phymode_to_string(new_mode));
2698 goto init_failure;
2699 }
2700 }
2701 if (prev_status >= B43_STAT_STARTED) {
2702 err = b43_wireless_core_start(up_dev);
2703 if (err) {
2704 b43err(wl, "Fatal: Coult not start device for "
2705 "newly selected %s-PHY mode\n",
2706 phymode_to_string(new_mode));
2707 b43_wireless_core_exit(up_dev);
2708 goto init_failure;
2709 }
2710 }
2711 B43_WARN_ON(b43_status(up_dev) != prev_status);
2712
2713 wl->current_dev = up_dev;
2714
2715 return 0;
2716 init_failure:
2717 /* Whoops, failed to init the new core. No core is operating now. */
2718 wl->current_dev = NULL;
2719 return err;
2720}
2721
9db1f6d7
MB		 2722/* Check if the use of the antenna that ieee80211 told us to
2723 * use is possible. This will fall back to DEFAULT.
2724 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2725u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2726 u8 antenna_nr)
e4d6b795 2727{
9db1f6d7
MB		 2728 u8 antenna_mask;
2729
2730 if (antenna_nr == 0) {
2731 /* Zero means "use default antenna". That's always OK. */
2732 return 0;
2733 }
2734
2735 /* Get the mask of available antennas. */
2736 if (dev->phy.gmode)
2737 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2738 else
2739 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2740
2741 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2742 /* This antenna is not available. Fall back to default. */
2743 return 0;
2744 }
2745
2746 return antenna_nr;
2747}
2748
2749static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2750{
2751 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
e4d6b795
MB		 2752 switch (antenna) {
2753 case 0: /* default/diversity */
2754 return B43_ANTENNA_DEFAULT;
2755 case 1: /* Antenna 0 */
2756 return B43_ANTENNA0;
2757 case 2: /* Antenna 1 */
2758 return B43_ANTENNA1;
eb189d8b
MB		 2759 case 3: /* Antenna 2 */
2760 return B43_ANTENNA2;
2761 case 4: /* Antenna 3 */
2762 return B43_ANTENNA3;
e4d6b795
MB		 2763 default:
2764 return B43_ANTENNA_DEFAULT;
2765 }
2766}
2767
40faacc4 2768static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
e4d6b795
MB		 2769{
2770 struct b43_wl *wl = hw_to_b43_wl(hw);
2771 struct b43_wldev *dev;
2772 struct b43_phy *phy;
2773 unsigned long flags;
2774 unsigned int new_phymode = 0xFFFF;
9db1f6d7 2775 int antenna;
e4d6b795
MB		 2776 int err = 0;
2777 u32 savedirqs;
2778
e4d6b795
MB		 2779 mutex_lock(&wl->mutex);
2780
2781 /* Switch the PHY mode (if necessary). */
2782 switch (conf->phymode) {
2783 case MODE_IEEE80211A:
2784 new_phymode = B43_PHYMODE_A;
2785 break;
2786 case MODE_IEEE80211B:
2787 new_phymode = B43_PHYMODE_B;
2788 break;
2789 case MODE_IEEE80211G:
2790 new_phymode = B43_PHYMODE_G;
2791 break;
2792 default:
2793 B43_WARN_ON(1);
2794 }
2795 err = b43_switch_phymode(wl, new_phymode);
2796 if (err)
2797 goto out_unlock_mutex;
2798 dev = wl->current_dev;
2799 phy = &dev->phy;
2800
2801 /* Disable IRQs while reconfiguring the device.
2802 * This makes it possible to drop the spinlock throughout
2803 * the reconfiguration process. */
2804 spin_lock_irqsave(&wl->irq_lock, flags);
2805 if (b43_status(dev) < B43_STAT_STARTED) {
2806 spin_unlock_irqrestore(&wl->irq_lock, flags);
2807 goto out_unlock_mutex;
2808 }
2809 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2810 spin_unlock_irqrestore(&wl->irq_lock, flags);
2811 b43_synchronize_irq(dev);
2812
2813 /* Switch to the requested channel.
2814 * The firmware takes care of races with the TX handler. */
2815 if (conf->channel_val != phy->channel)
2816 b43_radio_selectchannel(dev, conf->channel_val, 0);
2817
2818 /* Enable/Disable ShortSlot timing. */
2819 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2820 dev->short_slot) {
2821 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2822 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2823 b43_short_slot_timing_enable(dev);
2824 else
2825 b43_short_slot_timing_disable(dev);
2826 }
2827
d42ce84a
JB		 2828 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2829
e4d6b795
MB		 2830 /* Adjust the desired TX power level. */
2831 if (conf->power_level != 0) {
2832 if (conf->power_level != phy->power_level) {
2833 phy->power_level = conf->power_level;
2834 b43_phy_xmitpower(dev);
2835 }
2836 }
2837
2838 /* Antennas for RX and management frame TX. */
9db1f6d7
MB		 2839 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2840 b43_mgmtframe_txantenna(dev, antenna);
2841 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2842 b43_set_rx_antenna(dev, antenna);
e4d6b795
MB		 2843
2844 /* Update templates for AP mode. */
2845 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2846 b43_set_beacon_int(dev, conf->beacon_int);
2847
fda9abcf
MB		 2848 if (!!conf->radio_enabled != phy->radio_on) {
2849 if (conf->radio_enabled) {
2850 b43_radio_turn_on(dev);
2851 b43info(dev->wl, "Radio turned on by software\n");
2852 if (!dev->radio_hw_enable) {
2853 b43info(dev->wl, "The hardware RF-kill button "
2854 "still turns the radio physically off. "
2855 "Press the button to turn it on.\n");
2856 }
2857 } else {
8e9f7529 2858 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 2859 b43info(dev->wl, "Radio turned off by software\n");
2860 }
2861 }
2862
e4d6b795
MB		 2863 spin_lock_irqsave(&wl->irq_lock, flags);
2864 b43_interrupt_enable(dev, savedirqs);
2865 mmiowb();
2866 spin_unlock_irqrestore(&wl->irq_lock, flags);
2867 out_unlock_mutex:
2868 mutex_unlock(&wl->mutex);
2869
2870 return err;
2871}
2872
40faacc4 2873static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 2874 const u8 *local_addr, const u8 *addr,
2875 struct ieee80211_key_conf *key)
e4d6b795
MB		 2876{
2877 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 2878 struct b43_wldev *dev;
e4d6b795
MB		 2879 unsigned long flags;
2880 u8 algorithm;
2881 u8 index;
c6dfc9a8 2882 int err;
0795af57 2883 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 2884
2885 if (modparam_nohwcrypt)
2886 return -ENOSPC; /* User disabled HW-crypto */
2887
c6dfc9a8
MB		 2888 mutex_lock(&wl->mutex);
2889 spin_lock_irqsave(&wl->irq_lock, flags);
2890
2891 dev = wl->current_dev;
2892 err = -ENODEV;
2893 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2894 goto out_unlock;
2895
2896 err = -EINVAL;
e4d6b795 2897 switch (key->alg) {
e4d6b795
MB		 2898 case ALG_WEP:
2899 if (key->keylen == 5)
2900 algorithm = B43_SEC_ALGO_WEP40;
2901 else
2902 algorithm = B43_SEC_ALGO_WEP104;
2903 break;
2904 case ALG_TKIP:
2905 algorithm = B43_SEC_ALGO_TKIP;
2906 break;
2907 case ALG_CCMP:
2908 algorithm = B43_SEC_ALGO_AES;
2909 break;
2910 default:
2911 B43_WARN_ON(1);
c6dfc9a8 2912 goto out_unlock;
e4d6b795 2913 }
e4d6b795
MB		 2914 index = (u8) (key->keyidx);
2915 if (index > 3)
e4d6b795 2916 goto out_unlock;
e4d6b795
MB		 2917
2918 switch (cmd) {
2919 case SET_KEY:
2920 if (algorithm == B43_SEC_ALGO_TKIP) {
2921 /* FIXME: No TKIP hardware encryption for now. */
2922 err = -EOPNOTSUPP;
2923 goto out_unlock;
2924 }
2925
2926 if (is_broadcast_ether_addr(addr)) {
2927 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2928 err = b43_key_write(dev, index, algorithm,
2929 key->key, key->keylen, NULL, key);
2930 } else {
2931 /*
2932 * either pairwise key or address is 00:00:00:00:00:00
2933 * for transmit-only keys
2934 */
2935 err = b43_key_write(dev, -1, algorithm,
2936 key->key, key->keylen, addr, key);
2937 }
2938 if (err)
2939 goto out_unlock;
2940
2941 if (algorithm == B43_SEC_ALGO_WEP40 ||
2942 algorithm == B43_SEC_ALGO_WEP104) {
2943 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2944 } else {
2945 b43_hf_write(dev,
2946 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2947 }
2948 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2949 break;
2950 case DISABLE_KEY: {
2951 err = b43_key_clear(dev, key->hw_key_idx);
2952 if (err)
2953 goto out_unlock;
2954 break;
2955 }
2956 default:
2957 B43_WARN_ON(1);
2958 }
2959out_unlock:
2960 spin_unlock_irqrestore(&wl->irq_lock, flags);
2961 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2962 if (!err) {
2963 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 2964 "mac: %s\n",
e4d6b795 2965 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 2966 print_mac(mac, addr));
e4d6b795
MB		 2967 }
2968 return err;
2969}
2970
40faacc4
MB		 2971static void b43_op_configure_filter(struct ieee80211_hw *hw,
2972 unsigned int changed, unsigned int *fflags,
2973 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 2974{
2975 struct b43_wl *wl = hw_to_b43_wl(hw);
2976 struct b43_wldev *dev = wl->current_dev;
2977 unsigned long flags;
2978
4150c572
JB		 2979 if (!dev) {
2980 *fflags = 0;
e4d6b795 2981 return;
e4d6b795 2982 }
4150c572
JB		 2983
2984 spin_lock_irqsave(&wl->irq_lock, flags);
2985 *fflags &= FIF_PROMISC_IN_BSS |
2986 FIF_ALLMULTI |
2987 FIF_FCSFAIL |
2988 FIF_PLCPFAIL |
2989 FIF_CONTROL |
2990 FIF_OTHER_BSS |
2991 FIF_BCN_PRBRESP_PROMISC;
2992
2993 changed &= FIF_PROMISC_IN_BSS |
2994 FIF_ALLMULTI |
2995 FIF_FCSFAIL |
2996 FIF_PLCPFAIL |
2997 FIF_CONTROL |
2998 FIF_OTHER_BSS |
2999 FIF_BCN_PRBRESP_PROMISC;
3000
3001 wl->filter_flags = *fflags;
3002
3003 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3004 b43_adjust_opmode(dev);
e4d6b795
MB		 3005 spin_unlock_irqrestore(&wl->irq_lock, flags);
3006}
3007
40faacc4 3008static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3009 struct ieee80211_vif *vif,
40faacc4 3010 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3011{
3012 struct b43_wl *wl = hw_to_b43_wl(hw);
3013 struct b43_wldev *dev = wl->current_dev;
3014 unsigned long flags;
3015
3016 if (!dev)
3017 return -ENODEV;
3018 mutex_lock(&wl->mutex);
3019 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3020 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3021 if (conf->bssid)
3022 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3023 else
3024 memset(wl->bssid, 0, ETH_ALEN);
3025 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3026 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3027 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3028 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3029 if (conf->beacon)
e66fee6a 3030 b43_update_templates(wl, conf->beacon);
e4d6b795 3031 }
4150c572 3032 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3033 }
3034 spin_unlock_irqrestore(&wl->irq_lock, flags);
3035 mutex_unlock(&wl->mutex);
3036
3037 return 0;
3038}
3039
3040/* Locking: wl->mutex */
3041static void b43_wireless_core_stop(struct b43_wldev *dev)
3042{
3043 struct b43_wl *wl = dev->wl;
3044 unsigned long flags;
3045
3046 if (b43_status(dev) < B43_STAT_STARTED)
3047 return;
a19d12d7
SB		 3048
3049 /* Disable and sync interrupts. We must do this before than
3050 * setting the status to INITIALIZED, as the interrupt handler
3051 * won't care about IRQs then. */
3052 spin_lock_irqsave(&wl->irq_lock, flags);
3053 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3054 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3055 spin_unlock_irqrestore(&wl->irq_lock, flags);
3056 b43_synchronize_irq(dev);
3057
e4d6b795
MB		 3058 b43_set_status(dev, B43_STAT_INITIALIZED);
3059
3060 mutex_unlock(&wl->mutex);
3061 /* Must unlock as it would otherwise deadlock. No races here.
3062 * Cancel the possibly running self-rearming periodic work. */
3063 cancel_delayed_work_sync(&dev->periodic_work);
3064 mutex_lock(&wl->mutex);
3065
3066 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3067
e4d6b795
MB		 3068 b43_mac_suspend(dev);
3069 free_irq(dev->dev->irq, dev);
3070 b43dbg(wl, "Wireless interface stopped\n");
3071}
3072
3073/* Locking: wl->mutex */
3074static int b43_wireless_core_start(struct b43_wldev *dev)
3075{
3076 int err;
3077
3078 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3079
3080 drain_txstatus_queue(dev);
3081 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3082 IRQF_SHARED, KBUILD_MODNAME, dev);
3083 if (err) {
3084 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3085 goto out;
3086 }
3087
3088 /* We are ready to run. */
3089 b43_set_status(dev, B43_STAT_STARTED);
3090
3091 /* Start data flow (TX/RX). */
3092 b43_mac_enable(dev);
3093 b43_interrupt_enable(dev, dev->irq_savedstate);
3094 ieee80211_start_queues(dev->wl->hw);
3095
3096 /* Start maintainance work */
3097 b43_periodic_tasks_setup(dev);
3098
3099 b43dbg(dev->wl, "Wireless interface started\n");
3100 out:
3101 return err;
3102}
3103
3104/* Get PHY and RADIO versioning numbers */
3105static int b43_phy_versioning(struct b43_wldev *dev)
3106{
3107 struct b43_phy *phy = &dev->phy;
3108 u32 tmp;
3109 u8 analog_type;
3110 u8 phy_type;
3111 u8 phy_rev;
3112 u16 radio_manuf;
3113 u16 radio_ver;
3114 u16 radio_rev;
3115 int unsupported = 0;
3116
3117 /* Get PHY versioning */
3118 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3119 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3120 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3121 phy_rev = (tmp & B43_PHYVER_VERSION);
3122 switch (phy_type) {
3123 case B43_PHYTYPE_A:
3124 if (phy_rev >= 4)
3125 unsupported = 1;
3126 break;
3127 case B43_PHYTYPE_B:
3128 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3129 && phy_rev != 7)
3130 unsupported = 1;
3131 break;
3132 case B43_PHYTYPE_G:
013978b6 3133 if (phy_rev > 9)
e4d6b795
MB		 3134 unsupported = 1;
3135 break;
d5c71e46
MB		 3136#ifdef CONFIG_B43_NPHY
3137 case B43_PHYTYPE_N:
3138 if (phy_rev > 1)
3139 unsupported = 1;
3140 break;
3141#endif
e4d6b795
MB		 3142 default:
3143 unsupported = 1;
3144 };
3145 if (unsupported) {
3146 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3147 "(Analog %u, Type %u, Revision %u)\n",
3148 analog_type, phy_type, phy_rev);
3149 return -EOPNOTSUPP;
3150 }
3151 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3152 analog_type, phy_type, phy_rev);
3153
3154 /* Get RADIO versioning */
3155 if (dev->dev->bus->chip_id == 0x4317) {
3156 if (dev->dev->bus->chip_rev == 0)
3157 tmp = 0x3205017F;
3158 else if (dev->dev->bus->chip_rev == 1)
3159 tmp = 0x4205017F;
3160 else
3161 tmp = 0x5205017F;
3162 } else {
3163 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3164 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3165 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3166 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3167 }
3168 radio_manuf = (tmp & 0x00000FFF);
3169 radio_ver = (tmp & 0x0FFFF000) >> 12;
3170 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3171 if (radio_manuf != 0x17F /* Broadcom */)
3172 unsupported = 1;
e4d6b795
MB		 3173 switch (phy_type) {
3174 case B43_PHYTYPE_A:
3175 if (radio_ver != 0x2060)
3176 unsupported = 1;
3177 if (radio_rev != 1)
3178 unsupported = 1;
3179 if (radio_manuf != 0x17F)
3180 unsupported = 1;
3181 break;
3182 case B43_PHYTYPE_B:
3183 if ((radio_ver & 0xFFF0) != 0x2050)
3184 unsupported = 1;
3185 break;
3186 case B43_PHYTYPE_G:
3187 if (radio_ver != 0x2050)
3188 unsupported = 1;
3189 break;
96c755a3 3190 case B43_PHYTYPE_N:
243dcfcc 3191 if (radio_ver != 0x2055)
96c755a3
MB		 3192 unsupported = 1;
3193 break;
e4d6b795
MB		 3194 default:
3195 B43_WARN_ON(1);
3196 }
3197 if (unsupported) {
3198 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3199 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3200 radio_manuf, radio_ver, radio_rev);
3201 return -EOPNOTSUPP;
3202 }
3203 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3204 radio_manuf, radio_ver, radio_rev);
3205
3206 phy->radio_manuf = radio_manuf;
3207 phy->radio_ver = radio_ver;
3208 phy->radio_rev = radio_rev;
3209
3210 phy->analog = analog_type;
3211 phy->type = phy_type;
3212 phy->rev = phy_rev;
3213
3214 return 0;
3215}
3216
3217static void setup_struct_phy_for_init(struct b43_wldev *dev,
3218 struct b43_phy *phy)
3219{
3220 struct b43_txpower_lo_control *lo;
3221 int i;
3222
3223 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3224 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3225
e4d6b795
MB		 3226 phy->aci_enable = 0;
3227 phy->aci_wlan_automatic = 0;
3228 phy->aci_hw_rssi = 0;
3229
fda9abcf
MB		 3230 phy->radio_off_context.valid = 0;
3231
e4d6b795
MB		 3232 lo = phy->lo_control;
3233 if (lo) {
3234 memset(lo, 0, sizeof(*(phy->lo_control)));
3235 lo->rebuild = 1;
3236 lo->tx_bias = 0xFF;
3237 }
3238 phy->max_lb_gain = 0;
3239 phy->trsw_rx_gain = 0;
3240 phy->txpwr_offset = 0;
3241
3242 /* NRSSI */
3243 phy->nrssislope = 0;
3244 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3245 phy->nrssi[i] = -1000;
3246 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3247 phy->nrssi_lt[i] = i;
3248
3249 phy->lofcal = 0xFFFF;
3250 phy->initval = 0xFFFF;
3251
e4d6b795
MB		 3252 phy->interfmode = B43_INTERFMODE_NONE;
3253 phy->channel = 0xFF;
3254
3255 phy->hardware_power_control = !!modparam_hwpctl;
8ed7fc48
MB		 3256
3257 /* PHY TX errors counter. */
3258 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3259
3260 /* OFDM-table address caching. */
3261 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
e4d6b795
MB		 3262}
3263
3264static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3265{
aa6c7ae2
MB		 3266 dev->dfq_valid = 0;
3267
6a724d68
MB		 3268 /* Assume the radio is enabled. If it's not enabled, the state will
3269 * immediately get fixed on the first periodic work run. */
3270 dev->radio_hw_enable = 1;
e4d6b795
MB		 3271
3272 /* Stats */
3273 memset(&dev->stats, 0, sizeof(dev->stats));
3274
3275 setup_struct_phy_for_init(dev, &dev->phy);
3276
3277 /* IRQ related flags */
3278 dev->irq_reason = 0;
3279 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3280 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3281
3282 dev->mac_suspended = 1;
3283
3284 /* Noise calculation context */
3285 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3286}
3287
3288static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3289{
3290 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3291 u32 hf;
3292
95de2841 3293 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3294 return;
3295 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3296 return;
3297
3298 hf = b43_hf_read(dev);
95de2841 3299 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3300 hf |= B43_HF_BTCOEXALT;
3301 else
3302 hf |= B43_HF_BTCOEX;
3303 b43_hf_write(dev, hf);
3304 //TODO
3305}
3306
3307static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3308{ //TODO
3309}
3310
3311static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3312{
3313#ifdef CONFIG_SSB_DRIVER_PCICORE
3314 struct ssb_bus *bus = dev->dev->bus;
3315 u32 tmp;
3316
3317 if (bus->pcicore.dev &&
3318 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3319 bus->pcicore.dev->id.revision <= 5) {
3320 /* IMCFGLO timeouts workaround. */
3321 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3322 tmp &= ~SSB_IMCFGLO_REQTO;
3323 tmp &= ~SSB_IMCFGLO_SERTO;
3324 switch (bus->bustype) {
3325 case SSB_BUSTYPE_PCI:
3326 case SSB_BUSTYPE_PCMCIA:
3327 tmp |= 0x32;
3328 break;
3329 case SSB_BUSTYPE_SSB:
3330 tmp |= 0x53;
3331 break;
3332 }
3333 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3334 }
3335#endif /* CONFIG_SSB_DRIVER_PCICORE */
3336}
3337
74cfdba7
MB		 3338/* Write the short and long frame retry limit values. */
3339static void b43_set_retry_limits(struct b43_wldev *dev,
3340 unsigned int short_retry,
3341 unsigned int long_retry)
3342{
3343 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3344 * the chip-internal counter. */
3345 short_retry = min(short_retry, (unsigned int)0xF);
3346 long_retry = min(long_retry, (unsigned int)0xF);
3347
3348 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3349 short_retry);
3350 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3351 long_retry);
3352}
3353
e4d6b795
MB		 3354/* Shutdown a wireless core */
3355/* Locking: wl->mutex */
3356static void b43_wireless_core_exit(struct b43_wldev *dev)
3357{
3358 struct b43_phy *phy = &dev->phy;
3359
3360 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3361 if (b43_status(dev) != B43_STAT_INITIALIZED)
3362 return;
3363 b43_set_status(dev, B43_STAT_UNINIT);
3364
1a8d1227 3365 b43_leds_exit(dev);
e4d6b795 3366 b43_rng_exit(dev->wl);
e4d6b795
MB		 3367 b43_dma_free(dev);
3368 b43_chip_exit(dev);
8e9f7529 3369 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3370 b43_switch_analog(dev, 0);
3371 if (phy->dyn_tssi_tbl)
3372 kfree(phy->tssi2dbm);
3373 kfree(phy->lo_control);
3374 phy->lo_control = NULL;
e66fee6a
MB		 3375 if (dev->wl->current_beacon) {
3376 dev_kfree_skb_any(dev->wl->current_beacon);
3377 dev->wl->current_beacon = NULL;
3378 }
3379
e4d6b795
MB		 3380 ssb_device_disable(dev->dev, 0);
3381 ssb_bus_may_powerdown(dev->dev->bus);
3382}
3383
3384/* Initialize a wireless core */
3385static int b43_wireless_core_init(struct b43_wldev *dev)
3386{
3387 struct b43_wl *wl = dev->wl;
3388 struct ssb_bus *bus = dev->dev->bus;
3389 struct ssb_sprom *sprom = &bus->sprom;
3390 struct b43_phy *phy = &dev->phy;
3391 int err;
3392 u32 hf, tmp;
3393
3394 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3395
3396 err = ssb_bus_powerup(bus, 0);
3397 if (err)
3398 goto out;
3399 if (!ssb_device_is_enabled(dev->dev)) {
3400 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3401 b43_wireless_core_reset(dev, tmp);
3402 }
3403
3404 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3405 phy->lo_control =
3406 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3407 if (!phy->lo_control) {
3408 err = -ENOMEM;
3409 goto err_busdown;
3410 }
3411 }
3412 setup_struct_wldev_for_init(dev);
3413
3414 err = b43_phy_init_tssi2dbm_table(dev);
3415 if (err)
3416 goto err_kfree_lo_control;
3417
3418 /* Enable IRQ routing to this device. */
3419 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3420
3421 b43_imcfglo_timeouts_workaround(dev);
3422 b43_bluetooth_coext_disable(dev);
3423 b43_phy_early_init(dev);
3424 err = b43_chip_init(dev);
3425 if (err)
3426 goto err_kfree_tssitbl;
3427 b43_shm_write16(dev, B43_SHM_SHARED,
3428 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3429 hf = b43_hf_read(dev);
3430 if (phy->type == B43_PHYTYPE_G) {
3431 hf |= B43_HF_SYMW;
3432 if (phy->rev == 1)
3433 hf |= B43_HF_GDCW;
95de2841 3434 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3435 hf |= B43_HF_OFDMPABOOST;
3436 } else if (phy->type == B43_PHYTYPE_B) {
3437 hf |= B43_HF_SYMW;
3438 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3439 hf &= ~B43_HF_GDCW;
3440 }
3441 b43_hf_write(dev, hf);
3442
74cfdba7
MB		 3443 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3444 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 3445 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3446 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3447
3448 /* Disable sending probe responses from firmware.
3449 * Setting the MaxTime to one usec will always trigger
3450 * a timeout, so we never send any probe resp.
3451 * A timeout of zero is infinite. */
3452 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3453
3454 b43_rate_memory_init(dev);
3455
3456 /* Minimum Contention Window */
3457 if (phy->type == B43_PHYTYPE_B) {
3458 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3459 } else {
3460 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3461 }
3462 /* Maximum Contention Window */
3463 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3464
03b29773 3465 err = b43_dma_init(dev);
e4d6b795
MB		 3466 if (err)
3467 goto err_chip_exit;
03b29773 3468 b43_qos_init(dev);
e4d6b795
MB		 3469
3470//FIXME
3471#if 1
3472 b43_write16(dev, 0x0612, 0x0050);
3473 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3474 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3475#endif
3476
3477 b43_bluetooth_coext_enable(dev);
3478
3479 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3480 memset(wl->bssid, 0, ETH_ALEN);
4150c572
JB		 3481 memset(wl->mac_addr, 0, ETH_ALEN);
3482 b43_upload_card_macaddress(dev);
e4d6b795
MB		 3483 b43_security_init(dev);
3484 b43_rng_init(wl);
3485
3486 b43_set_status(dev, B43_STAT_INITIALIZED);
3487
1a8d1227
LF		 3488 b43_leds_init(dev);
3489out:
e4d6b795
MB		 3490 return err;
3491
3492 err_chip_exit:
3493 b43_chip_exit(dev);
3494 err_kfree_tssitbl:
3495 if (phy->dyn_tssi_tbl)
3496 kfree(phy->tssi2dbm);
3497 err_kfree_lo_control:
3498 kfree(phy->lo_control);
3499 phy->lo_control = NULL;
3500 err_busdown:
3501 ssb_bus_may_powerdown(bus);
3502 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3503 return err;
3504}
3505
40faacc4
MB		 3506static int b43_op_add_interface(struct ieee80211_hw *hw,
3507 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 3508{
3509 struct b43_wl *wl = hw_to_b43_wl(hw);
3510 struct b43_wldev *dev;
3511 unsigned long flags;
3512 int err = -EOPNOTSUPP;
4150c572
JB		 3513
3514 /* TODO: allow WDS/AP devices to coexist */
3515
3516 if (conf->type != IEEE80211_IF_TYPE_AP &&
3517 conf->type != IEEE80211_IF_TYPE_STA &&
3518 conf->type != IEEE80211_IF_TYPE_WDS &&
3519 conf->type != IEEE80211_IF_TYPE_IBSS)
3520 return -EOPNOTSUPP;
e4d6b795
MB		 3521
3522 mutex_lock(&wl->mutex);
4150c572 3523 if (wl->operating)
e4d6b795
MB		 3524 goto out_mutex_unlock;
3525
3526 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3527
3528 dev = wl->current_dev;
4150c572 3529 wl->operating = 1;
32bfd35d 3530 wl->vif = conf->vif;
4150c572
JB		 3531 wl->if_type = conf->type;
3532 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3533
3534 spin_lock_irqsave(&wl->irq_lock, flags);
3535 b43_adjust_opmode(dev);
3536 b43_upload_card_macaddress(dev);
3537 spin_unlock_irqrestore(&wl->irq_lock, flags);
3538
3539 err = 0;
3540 out_mutex_unlock:
3541 mutex_unlock(&wl->mutex);
3542
3543 return err;
3544}
3545
40faacc4
MB		 3546static void b43_op_remove_interface(struct ieee80211_hw *hw,
3547 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3548{
3549 struct b43_wl *wl = hw_to_b43_wl(hw);
3550 struct b43_wldev *dev = wl->current_dev;
3551 unsigned long flags;
3552
3553 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3554
3555 mutex_lock(&wl->mutex);
3556
3557 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 3558 B43_WARN_ON(wl->vif != conf->vif);
3559 wl->vif = NULL;
4150c572
JB		 3560
3561 wl->operating = 0;
3562
3563 spin_lock_irqsave(&wl->irq_lock, flags);
3564 b43_adjust_opmode(dev);
3565 memset(wl->mac_addr, 0, ETH_ALEN);
3566 b43_upload_card_macaddress(dev);
3567 spin_unlock_irqrestore(&wl->irq_lock, flags);
3568
3569 mutex_unlock(&wl->mutex);
3570}
3571
40faacc4 3572static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3573{
3574 struct b43_wl *wl = hw_to_b43_wl(hw);
3575 struct b43_wldev *dev = wl->current_dev;
3576 int did_init = 0;
923403b8 3577 int err = 0;
4150c572 3578
1a8d1227
LF		 3579 /* First register RFkill.
3580 * LEDs that are registered later depend on it. */
3581 b43_rfkill_init(dev);
3582
4150c572
JB		 3583 mutex_lock(&wl->mutex);
3584
e4d6b795
MB		 3585 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3586 err = b43_wireless_core_init(dev);
3587 if (err)
3588 goto out_mutex_unlock;
3589 did_init = 1;
3590 }
4150c572 3591
e4d6b795
MB		 3592 if (b43_status(dev) < B43_STAT_STARTED) {
3593 err = b43_wireless_core_start(dev);
3594 if (err) {
3595 if (did_init)
3596 b43_wireless_core_exit(dev);
3597 goto out_mutex_unlock;
3598 }
3599 }
3600
4150c572 3601 out_mutex_unlock:
e4d6b795
MB		 3602 mutex_unlock(&wl->mutex);
3603
3604 return err;
3605}
3606
40faacc4 3607static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 3608{
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 3610 struct b43_wldev *dev = wl->current_dev;
e4d6b795 3611
1a8d1227
LF		 3612 b43_rfkill_exit(dev);
3613
e4d6b795 3614 mutex_lock(&wl->mutex);
4150c572
JB		 3615 if (b43_status(dev) >= B43_STAT_STARTED)
3616 b43_wireless_core_stop(dev);
3617 b43_wireless_core_exit(dev);
e4d6b795
MB		 3618 mutex_unlock(&wl->mutex);
3619}
3620
74cfdba7
MB		 3621static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3622 u32 short_retry_limit, u32 long_retry_limit)
3623{
3624 struct b43_wl *wl = hw_to_b43_wl(hw);
3625 struct b43_wldev *dev;
3626 int err = 0;
3627
3628 mutex_lock(&wl->mutex);
3629 dev = wl->current_dev;
3630 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3631 err = -ENODEV;
3632 goto out_unlock;
3633 }
3634 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3635out_unlock:
3636 mutex_unlock(&wl->mutex);
3637
3638 return err;
3639}
3640
e66fee6a
MB		 3641static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3642{
3643 struct b43_wl *wl = hw_to_b43_wl(hw);
3644 struct sk_buff *beacon;
d4df6f1a 3645 unsigned long flags;
e66fee6a
MB		 3646
3647 /* We could modify the existing beacon and set the aid bit in
3648 * the TIM field, but that would probably require resizing and
3649 * moving of data within the beacon template.
3650 * Simply request a new beacon and let mac80211 do the hard work. */
3651 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3652 if (unlikely(!beacon))
3653 return -ENOMEM;
d4df6f1a 3654 spin_lock_irqsave(&wl->irq_lock, flags);
e66fee6a 3655 b43_update_templates(wl, beacon);
d4df6f1a 3656 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 3657
3658 return 0;
3659}
3660
3661static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3662 struct sk_buff *beacon,
3663 struct ieee80211_tx_control *ctl)
3664{
3665 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 3666 unsigned long flags;
e66fee6a 3667
d4df6f1a 3668 spin_lock_irqsave(&wl->irq_lock, flags);
e66fee6a 3669 b43_update_templates(wl, beacon);
d4df6f1a 3670 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 3671
3672 return 0;
3673}
3674
e4d6b795 3675static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 3676 .tx = b43_op_tx,
3677 .conf_tx = b43_op_conf_tx,
3678 .add_interface = b43_op_add_interface,
3679 .remove_interface = b43_op_remove_interface,
3680 .config = b43_op_config,
3681 .config_interface = b43_op_config_interface,
3682 .configure_filter = b43_op_configure_filter,
3683 .set_key = b43_op_set_key,
3684 .get_stats = b43_op_get_stats,
3685 .get_tx_stats = b43_op_get_tx_stats,
3686 .start = b43_op_start,
3687 .stop = b43_op_stop,
74cfdba7 3688 .set_retry_limit = b43_op_set_retry_limit,
e66fee6a
MB		 3689 .set_tim = b43_op_beacon_set_tim,
3690 .beacon_update = b43_op_ibss_beacon_update,
e4d6b795
MB		 3691};
3692
3693/* Hard-reset the chip. Do not call this directly.
3694 * Use b43_controller_restart()
3695 */
3696static void b43_chip_reset(struct work_struct *work)
3697{
3698 struct b43_wldev *dev =
3699 container_of(work, struct b43_wldev, restart_work);
3700 struct b43_wl *wl = dev->wl;
3701 int err = 0;
3702 int prev_status;
3703
3704 mutex_lock(&wl->mutex);
3705
3706 prev_status = b43_status(dev);
3707 /* Bring the device down... */
3708 if (prev_status >= B43_STAT_STARTED)
3709 b43_wireless_core_stop(dev);
3710 if (prev_status >= B43_STAT_INITIALIZED)
3711 b43_wireless_core_exit(dev);
3712
3713 /* ...and up again. */
3714 if (prev_status >= B43_STAT_INITIALIZED) {
3715 err = b43_wireless_core_init(dev);
3716 if (err)
3717 goto out;
3718 }
3719 if (prev_status >= B43_STAT_STARTED) {
3720 err = b43_wireless_core_start(dev);
3721 if (err) {
3722 b43_wireless_core_exit(dev);
3723 goto out;
3724 }
3725 }
3726 out:
3727 mutex_unlock(&wl->mutex);
3728 if (err)
3729 b43err(wl, "Controller restart FAILED\n");
3730 else
3731 b43info(wl, "Controller restarted\n");
3732}
3733
3734static int b43_setup_modes(struct b43_wldev *dev,
96c755a3 3735 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 3736{
3737 struct ieee80211_hw *hw = dev->wl->hw;
3738 struct ieee80211_hw_mode *mode;
3739 struct b43_phy *phy = &dev->phy;
e4d6b795
MB		 3740 int err;
3741
96c755a3
MB		 3742 /* XXX: This function will go away soon, when mac80211
3743 * band stuff is rewritten. So this is just a hack.
3744 * For now we always claim GPHY mode, as there is no
3745 * support for NPHY and APHY in the device, yet.
3746 * This assumption is OK, as any B, N or A PHY will already
3747 * have died a horrible sanity check death earlier. */
3748
3749 mode = &phy->hwmodes[0];
3750 mode->mode = MODE_IEEE80211G;
3751 mode->num_channels = b43_2ghz_chantable_size;
3752 mode->channels = b43_2ghz_chantable;
3753 mode->num_rates = b43_g_ratetable_size;
3754 mode->rates = b43_g_ratetable;
3755 err = ieee80211_register_hwmode(hw, mode);
3756 if (err)
3757 return err;
3758 phy->possible_phymodes |= B43_PHYMODE_G;
e4d6b795
MB		 3759
3760 return 0;
3761}
3762
3763static void b43_wireless_core_detach(struct b43_wldev *dev)
3764{
3765 /* We release firmware that late to not be required to re-request
3766 * is all the time when we reinit the core. */
3767 b43_release_firmware(dev);
3768}
3769
3770static int b43_wireless_core_attach(struct b43_wldev *dev)
3771{
3772 struct b43_wl *wl = dev->wl;
3773 struct ssb_bus *bus = dev->dev->bus;
3774 struct pci_dev *pdev = bus->host_pci;
3775 int err;
96c755a3 3776 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 3777 u32 tmp;
3778
3779 /* Do NOT do any device initialization here.
3780 * Do it in wireless_core_init() instead.
3781 * This function is for gathering basic information about the HW, only.
3782 * Also some structs may be set up here. But most likely you want to have
3783 * that in core_init(), too.
3784 */
3785
3786 err = ssb_bus_powerup(bus, 0);
3787 if (err) {
3788 b43err(wl, "Bus powerup failed\n");
3789 goto out;
3790 }
3791 /* Get the PHY type. */
3792 if (dev->dev->id.revision >= 5) {
3793 u32 tmshigh;
3794
3795 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 3796 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3797 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 3798 } else
96c755a3 3799 B43_WARN_ON(1);
e4d6b795 3800
96c755a3 3801 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3802 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3803 b43_wireless_core_reset(dev, tmp);
3804
3805 err = b43_phy_versioning(dev);
3806 if (err)
21954c36 3807 goto err_powerdown;
e4d6b795
MB		 3808 /* Check if this device supports multiband. */
3809 if (!pdev ||
3810 (pdev->device != 0x4312 &&
3811 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3812 /* No multiband support. */
96c755a3
MB		 3813 have_2ghz_phy = 0;
3814 have_5ghz_phy = 0;
e4d6b795
MB		 3815 switch (dev->phy.type) {
3816 case B43_PHYTYPE_A:
96c755a3 3817 have_5ghz_phy = 1;
e4d6b795
MB		 3818 break;
3819 case B43_PHYTYPE_G:
96c755a3
MB		 3820 case B43_PHYTYPE_N:
3821 have_2ghz_phy = 1;
e4d6b795
MB		 3822 break;
3823 default:
3824 B43_WARN_ON(1);
3825 }
3826 }
96c755a3
MB		 3827 if (dev->phy.type == B43_PHYTYPE_A) {
3828 /* FIXME */
3829 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3830 err = -EOPNOTSUPP;
3831 goto err_powerdown;
3832 }
3833 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3834 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3835 b43_wireless_core_reset(dev, tmp);
3836
3837 err = b43_validate_chipaccess(dev);
3838 if (err)
21954c36 3839 goto err_powerdown;
96c755a3 3840 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 3841 if (err)
21954c36 3842 goto err_powerdown;
e4d6b795
MB		 3843
3844 /* Now set some default "current_dev" */
3845 if (!wl->current_dev)
3846 wl->current_dev = dev;
3847 INIT_WORK(&dev->restart_work, b43_chip_reset);
3848
8e9f7529 3849 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3850 b43_switch_analog(dev, 0);
3851 ssb_device_disable(dev->dev, 0);
3852 ssb_bus_may_powerdown(bus);
3853
3854out:
3855 return err;
3856
e4d6b795
MB		 3857err_powerdown:
3858 ssb_bus_may_powerdown(bus);
3859 return err;
3860}
3861
3862static void b43_one_core_detach(struct ssb_device *dev)
3863{
3864 struct b43_wldev *wldev;
3865 struct b43_wl *wl;
3866
3867 wldev = ssb_get_drvdata(dev);
3868 wl = wldev->wl;
3869 cancel_work_sync(&wldev->restart_work);
3870 b43_debugfs_remove_device(wldev);
3871 b43_wireless_core_detach(wldev);
3872 list_del(&wldev->list);
3873 wl->nr_devs--;
3874 ssb_set_drvdata(dev, NULL);
3875 kfree(wldev);
3876}
3877
3878static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3879{
3880 struct b43_wldev *wldev;
3881 struct pci_dev *pdev;
3882 int err = -ENOMEM;
3883
3884 if (!list_empty(&wl->devlist)) {
3885 /* We are not the first core on this chip. */
3886 pdev = dev->bus->host_pci;
3887 /* Only special chips support more than one wireless
3888 * core, although some of the other chips have more than
3889 * one wireless core as well. Check for this and
3890 * bail out early.
3891 */
3892 if (!pdev ||
3893 ((pdev->device != 0x4321) &&
3894 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3895 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3896 return -ENODEV;
3897 }
3898 }
3899
3900 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3901 if (!wldev)
3902 goto out;
3903
3904 wldev->dev = dev;
3905 wldev->wl = wl;
3906 b43_set_status(wldev, B43_STAT_UNINIT);
3907 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3908 tasklet_init(&wldev->isr_tasklet,
3909 (void (*)(unsigned long))b43_interrupt_tasklet,
3910 (unsigned long)wldev);
e4d6b795
MB		 3911 INIT_LIST_HEAD(&wldev->list);
3912
3913 err = b43_wireless_core_attach(wldev);
3914 if (err)
3915 goto err_kfree_wldev;
3916
3917 list_add(&wldev->list, &wl->devlist);
3918 wl->nr_devs++;
3919 ssb_set_drvdata(dev, wldev);
3920 b43_debugfs_add_device(wldev);
3921
3922 out:
3923 return err;
3924
3925 err_kfree_wldev:
3926 kfree(wldev);
3927 return err;
3928}
3929
3930static void b43_sprom_fixup(struct ssb_bus *bus)
3931{
3932 /* boardflags workarounds */
3933 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3934 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 3935 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 3936 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3937 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 3938 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
e4d6b795
MB		 3939}
3940
3941static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3942{
3943 struct ieee80211_hw *hw = wl->hw;
3944
3945 ssb_set_devtypedata(dev, NULL);
3946 ieee80211_free_hw(hw);
3947}
3948
3949static int b43_wireless_init(struct ssb_device *dev)
3950{
3951 struct ssb_sprom *sprom = &dev->bus->sprom;
3952 struct ieee80211_hw *hw;
3953 struct b43_wl *wl;
3954 int err = -ENOMEM;
3955
3956 b43_sprom_fixup(dev->bus);
3957
3958 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3959 if (!hw) {
3960 b43err(NULL, "Could not allocate ieee80211 device\n");
3961 goto out;
3962 }
3963
3964 /* fill hw info */
d8be11ee
JB		 3965 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3966 IEEE80211_HW_RX_INCLUDES_FCS;
e4d6b795
MB		 3967 hw->max_signal = 100;
3968 hw->max_rssi = -110;
3969 hw->max_noise = -110;
3970 hw->queues = 1; /* FIXME: hardware has more queues */
3971 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 3972 if (is_valid_ether_addr(sprom->et1mac))
3973 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 3974 else
95de2841 3975 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 3976
3977 /* Get and initialize struct b43_wl */
3978 wl = hw_to_b43_wl(hw);
3979 memset(wl, 0, sizeof(*wl));
3980 wl->hw = hw;
3981 spin_lock_init(&wl->irq_lock);
3982 spin_lock_init(&wl->leds_lock);
280d0e16 3983 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 3984 mutex_init(&wl->mutex);
3985 INIT_LIST_HEAD(&wl->devlist);
3986
3987 ssb_set_devtypedata(dev, wl);
3988 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3989 err = 0;
3990 out:
3991 return err;
3992}
3993
3994static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3995{
3996 struct b43_wl *wl;
3997 int err;
3998 int first = 0;
3999
4000 wl = ssb_get_devtypedata(dev);
4001 if (!wl) {
4002 /* Probing the first core. Must setup common struct b43_wl */
4003 first = 1;
4004 err = b43_wireless_init(dev);
4005 if (err)
4006 goto out;
4007 wl = ssb_get_devtypedata(dev);
4008 B43_WARN_ON(!wl);
4009 }
4010 err = b43_one_core_attach(dev, wl);
4011 if (err)
4012 goto err_wireless_exit;
4013
4014 if (first) {
4015 err = ieee80211_register_hw(wl->hw);
4016 if (err)
4017 goto err_one_core_detach;
4018 }
4019
4020 out:
4021 return err;
4022
4023 err_one_core_detach:
4024 b43_one_core_detach(dev);
4025 err_wireless_exit:
4026 if (first)
4027 b43_wireless_exit(dev, wl);
4028 return err;
4029}
4030
4031static void b43_remove(struct ssb_device *dev)
4032{
4033 struct b43_wl *wl = ssb_get_devtypedata(dev);
4034 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4035
4036 B43_WARN_ON(!wl);
4037 if (wl->current_dev == wldev)
4038 ieee80211_unregister_hw(wl->hw);
4039
4040 b43_one_core_detach(dev);
4041
4042 if (list_empty(&wl->devlist)) {
4043 /* Last core on the chip unregistered.
4044 * We can destroy common struct b43_wl.
4045 */
4046 b43_wireless_exit(dev, wl);
4047 }
4048}
4049
4050/* Perform a hardware reset. This can be called from any context. */
4051void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4052{
4053 /* Must avoid requeueing, if we are in shutdown. */
4054 if (b43_status(dev) < B43_STAT_INITIALIZED)
4055 return;
4056 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4057 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4058}
4059
4060#ifdef CONFIG_PM
4061
4062static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4063{
4064 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4065 struct b43_wl *wl = wldev->wl;
4066
4067 b43dbg(wl, "Suspending...\n");
4068
4069 mutex_lock(&wl->mutex);
4070 wldev->suspend_init_status = b43_status(wldev);
4071 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4072 b43_wireless_core_stop(wldev);
4073 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4074 b43_wireless_core_exit(wldev);
4075 mutex_unlock(&wl->mutex);
4076
4077 b43dbg(wl, "Device suspended.\n");
4078
4079 return 0;
4080}
4081
4082static int b43_resume(struct ssb_device *dev)
4083{
4084 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4085 struct b43_wl *wl = wldev->wl;
4086 int err = 0;
4087
4088 b43dbg(wl, "Resuming...\n");
4089
4090 mutex_lock(&wl->mutex);
4091 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4092 err = b43_wireless_core_init(wldev);
4093 if (err) {
4094 b43err(wl, "Resume failed at core init\n");
4095 goto out;
4096 }
4097 }
4098 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4099 err = b43_wireless_core_start(wldev);
4100 if (err) {
4101 b43_wireless_core_exit(wldev);
4102 b43err(wl, "Resume failed at core start\n");
4103 goto out;
4104 }
4105 }
4106 mutex_unlock(&wl->mutex);
4107
4108 b43dbg(wl, "Device resumed.\n");
4109 out:
4110 return err;
4111}
4112
4113#else /* CONFIG_PM */
4114# define b43_suspend NULL
4115# define b43_resume NULL
4116#endif /* CONFIG_PM */
4117
4118static struct ssb_driver b43_ssb_driver = {
4119 .name = KBUILD_MODNAME,
4120 .id_table = b43_ssb_tbl,
4121 .probe = b43_probe,
4122 .remove = b43_remove,
4123 .suspend = b43_suspend,
4124 .resume = b43_resume,
4125};
4126
4127static int __init b43_init(void)
4128{
4129 int err;
4130
4131 b43_debugfs_init();
4132 err = b43_pcmcia_init();
4133 if (err)
4134 goto err_dfs_exit;
4135 err = ssb_driver_register(&b43_ssb_driver);
4136 if (err)
4137 goto err_pcmcia_exit;
4138
4139 return err;
4140
4141err_pcmcia_exit:
4142 b43_pcmcia_exit();
4143err_dfs_exit:
4144 b43_debugfs_exit();
4145 return err;
4146}
4147
4148static void __exit b43_exit(void)
4149{
4150 ssb_driver_unregister(&b43_ssb_driver);
4151 b43_pcmcia_exit();
4152 b43_debugfs_exit();
4153}
4154
4155module_init(b43_init)
4156module_exit(b43_exit)
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