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Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetoot...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
8960400e
RM		 116static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119
3c65ab62
RM		 120#ifdef CONFIG_B43_BCMA
121static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
15be8e89 125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
3c65ab62 126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
15be8e89
RM		 127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
3c65ab62
RM		 130 BCMA_CORETABLE_END
131};
132MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
133#endif
134
aec7ffdf 135#ifdef CONFIG_B43_SSB
e4d6b795
MB		 136static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 147 SSB_DEVTABLE_END
148};
e4d6b795 149MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 150#endif
e4d6b795
MB		 151
152/* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 157 { \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
160 .flags = (_flags), \
e4d6b795 161 }
8318d78a
JB		 162
163/*
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
166 */
e4d6b795 167static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 180};
181
182#define b43_a_ratetable (__b43_ratetable + 4)
183#define b43_a_ratetable_size 8
184#define b43_b_ratetable (__b43_ratetable + 0)
185#define b43_b_ratetable_size 4
186#define b43_g_ratetable (__b43_ratetable + 0)
187#define b43_g_ratetable_size 12
188
e9cdcb74 189#define CHAN2G(_channel, _freq, _flags) { \
bb1eeff1
MB		 190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
193 .flags = (_flags), \
194 .max_antenna_gain = 0, \
195 .max_power = 30, \
196}
96c755a3 197static struct ieee80211_channel b43_2ghz_chantable[] = {
e9cdcb74
RM		 198 CHAN2G(1, 2412, 0),
199 CHAN2G(2, 2417, 0),
200 CHAN2G(3, 2422, 0),
201 CHAN2G(4, 2427, 0),
202 CHAN2G(5, 2432, 0),
203 CHAN2G(6, 2437, 0),
204 CHAN2G(7, 2442, 0),
205 CHAN2G(8, 2447, 0),
206 CHAN2G(9, 2452, 0),
207 CHAN2G(10, 2457, 0),
208 CHAN2G(11, 2462, 0),
209 CHAN2G(12, 2467, 0),
210 CHAN2G(13, 2472, 0),
211 CHAN2G(14, 2484, 0),
bb1eeff1 212};
e9cdcb74 213#undef CHAN2G
bb1eeff1 214
91211739
RM		 215#define CHAN4G(_channel, _flags) { \
216 .band = IEEE80211_BAND_5GHZ, \
217 .center_freq = 4000 + (5 * (_channel)), \
218 .hw_value = (_channel), \
219 .flags = (_flags), \
220 .max_antenna_gain = 0, \
221 .max_power = 30, \
222}
bb1eeff1
MB		 223#define CHAN5G(_channel, _flags) { \
224 .band = IEEE80211_BAND_5GHZ, \
225 .center_freq = 5000 + (5 * (_channel)), \
226 .hw_value = (_channel), \
227 .flags = (_flags), \
228 .max_antenna_gain = 0, \
229 .max_power = 30, \
230}
231static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
91211739
RM		 232 CHAN4G(184, 0), CHAN4G(186, 0),
233 CHAN4G(188, 0), CHAN4G(190, 0),
234 CHAN4G(192, 0), CHAN4G(194, 0),
235 CHAN4G(196, 0), CHAN4G(198, 0),
236 CHAN4G(200, 0), CHAN4G(202, 0),
237 CHAN4G(204, 0), CHAN4G(206, 0),
238 CHAN4G(208, 0), CHAN4G(210, 0),
239 CHAN4G(212, 0), CHAN4G(214, 0),
240 CHAN4G(216, 0), CHAN4G(218, 0),
241 CHAN4G(220, 0), CHAN4G(222, 0),
242 CHAN4G(224, 0), CHAN4G(226, 0),
243 CHAN4G(228, 0),
bb1eeff1
MB		 244 CHAN5G(32, 0), CHAN5G(34, 0),
245 CHAN5G(36, 0), CHAN5G(38, 0),
246 CHAN5G(40, 0), CHAN5G(42, 0),
247 CHAN5G(44, 0), CHAN5G(46, 0),
248 CHAN5G(48, 0), CHAN5G(50, 0),
249 CHAN5G(52, 0), CHAN5G(54, 0),
250 CHAN5G(56, 0), CHAN5G(58, 0),
251 CHAN5G(60, 0), CHAN5G(62, 0),
252 CHAN5G(64, 0), CHAN5G(66, 0),
253 CHAN5G(68, 0), CHAN5G(70, 0),
254 CHAN5G(72, 0), CHAN5G(74, 0),
255 CHAN5G(76, 0), CHAN5G(78, 0),
256 CHAN5G(80, 0), CHAN5G(82, 0),
257 CHAN5G(84, 0), CHAN5G(86, 0),
258 CHAN5G(88, 0), CHAN5G(90, 0),
259 CHAN5G(92, 0), CHAN5G(94, 0),
260 CHAN5G(96, 0), CHAN5G(98, 0),
261 CHAN5G(100, 0), CHAN5G(102, 0),
262 CHAN5G(104, 0), CHAN5G(106, 0),
263 CHAN5G(108, 0), CHAN5G(110, 0),
264 CHAN5G(112, 0), CHAN5G(114, 0),
265 CHAN5G(116, 0), CHAN5G(118, 0),
266 CHAN5G(120, 0), CHAN5G(122, 0),
267 CHAN5G(124, 0), CHAN5G(126, 0),
268 CHAN5G(128, 0), CHAN5G(130, 0),
269 CHAN5G(132, 0), CHAN5G(134, 0),
270 CHAN5G(136, 0), CHAN5G(138, 0),
271 CHAN5G(140, 0), CHAN5G(142, 0),
272 CHAN5G(144, 0), CHAN5G(145, 0),
273 CHAN5G(146, 0), CHAN5G(147, 0),
274 CHAN5G(148, 0), CHAN5G(149, 0),
275 CHAN5G(150, 0), CHAN5G(151, 0),
276 CHAN5G(152, 0), CHAN5G(153, 0),
277 CHAN5G(154, 0), CHAN5G(155, 0),
278 CHAN5G(156, 0), CHAN5G(157, 0),
279 CHAN5G(158, 0), CHAN5G(159, 0),
280 CHAN5G(160, 0), CHAN5G(161, 0),
281 CHAN5G(162, 0), CHAN5G(163, 0),
282 CHAN5G(164, 0), CHAN5G(165, 0),
283 CHAN5G(166, 0), CHAN5G(168, 0),
284 CHAN5G(170, 0), CHAN5G(172, 0),
285 CHAN5G(174, 0), CHAN5G(176, 0),
286 CHAN5G(178, 0), CHAN5G(180, 0),
91211739 287 CHAN5G(182, 0),
e4d6b795
MB		 288};
289
bb1eeff1
MB		 290static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
291 CHAN5G(34, 0), CHAN5G(36, 0),
292 CHAN5G(38, 0), CHAN5G(40, 0),
293 CHAN5G(42, 0), CHAN5G(44, 0),
294 CHAN5G(46, 0), CHAN5G(48, 0),
295 CHAN5G(52, 0), CHAN5G(56, 0),
296 CHAN5G(60, 0), CHAN5G(64, 0),
297 CHAN5G(100, 0), CHAN5G(104, 0),
298 CHAN5G(108, 0), CHAN5G(112, 0),
299 CHAN5G(116, 0), CHAN5G(120, 0),
300 CHAN5G(124, 0), CHAN5G(128, 0),
301 CHAN5G(132, 0), CHAN5G(136, 0),
302 CHAN5G(140, 0), CHAN5G(149, 0),
303 CHAN5G(153, 0), CHAN5G(157, 0),
304 CHAN5G(161, 0), CHAN5G(165, 0),
305 CHAN5G(184, 0), CHAN5G(188, 0),
306 CHAN5G(192, 0), CHAN5G(196, 0),
307 CHAN5G(200, 0), CHAN5G(204, 0),
308 CHAN5G(208, 0), CHAN5G(212, 0),
309 CHAN5G(216, 0),
310};
91211739 311#undef CHAN4G
bb1eeff1
MB		 312#undef CHAN5G
313
314static struct ieee80211_supported_band b43_band_5GHz_nphy = {
315 .band = IEEE80211_BAND_5GHZ,
316 .channels = b43_5ghz_nphy_chantable,
317 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
318 .bitrates = b43_a_ratetable,
319 .n_bitrates = b43_a_ratetable_size,
e4d6b795 320};
8318d78a 321
bb1eeff1
MB		 322static struct ieee80211_supported_band b43_band_5GHz_aphy = {
323 .band = IEEE80211_BAND_5GHZ,
324 .channels = b43_5ghz_aphy_chantable,
325 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
326 .bitrates = b43_a_ratetable,
327 .n_bitrates = b43_a_ratetable_size,
8318d78a 328};
e4d6b795 329
8318d78a 330static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 331 .band = IEEE80211_BAND_2GHZ,
332 .channels = b43_2ghz_chantable,
333 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
334 .bitrates = b43_g_ratetable,
335 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 336};
337
e4d6b795
MB		 338static void b43_wireless_core_exit(struct b43_wldev *dev);
339static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 340static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 341static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 342static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
343 struct ieee80211_vif *vif,
344 struct ieee80211_bss_conf *conf,
345 u32 changed);
e4d6b795
MB		 346
347static int b43_ratelimit(struct b43_wl *wl)
348{
349 if (!wl || !wl->current_dev)
350 return 1;
351 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
352 return 1;
353 /* We are up and running.
354 * Ratelimit the messages to avoid DoS over the net. */
355 return net_ratelimit();
356}
357
358void b43info(struct b43_wl *wl, const char *fmt, ...)
359{
5b736d42 360 struct va_format vaf;
e4d6b795
MB		 361 va_list args;
362
060210f9
MB		 363 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
364 return;
e4d6b795
MB		 365 if (!b43_ratelimit(wl))
366 return;
5b736d42 367
e4d6b795 368 va_start(args, fmt);
5b736d42
JP		 369
370 vaf.fmt = fmt;
371 vaf.va = &args;
372
373 printk(KERN_INFO "b43-%s: %pV",
374 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
375
e4d6b795
MB		 376 va_end(args);
377}
378
379void b43err(struct b43_wl *wl, const char *fmt, ...)
380{
5b736d42 381 struct va_format vaf;
e4d6b795
MB		 382 va_list args;
383
060210f9
MB		 384 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
385 return;
e4d6b795
MB		 386 if (!b43_ratelimit(wl))
387 return;
5b736d42 388
e4d6b795 389 va_start(args, fmt);
5b736d42
JP		 390
391 vaf.fmt = fmt;
392 vaf.va = &args;
393
394 printk(KERN_ERR "b43-%s ERROR: %pV",
395 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
396
e4d6b795
MB		 397 va_end(args);
398}
399
400void b43warn(struct b43_wl *wl, const char *fmt, ...)
401{
5b736d42 402 struct va_format vaf;
e4d6b795
MB		 403 va_list args;
404
060210f9
MB		 405 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
406 return;
e4d6b795
MB		 407 if (!b43_ratelimit(wl))
408 return;
5b736d42 409
e4d6b795 410 va_start(args, fmt);
5b736d42
JP		 411
412 vaf.fmt = fmt;
413 vaf.va = &args;
414
415 printk(KERN_WARNING "b43-%s warning: %pV",
416 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
417
e4d6b795
MB		 418 va_end(args);
419}
420
e4d6b795
MB		 421void b43dbg(struct b43_wl *wl, const char *fmt, ...)
422{
5b736d42 423 struct va_format vaf;
e4d6b795
MB		 424 va_list args;
425
060210f9
MB		 426 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
427 return;
5b736d42 428
e4d6b795 429 va_start(args, fmt);
5b736d42
JP		 430
431 vaf.fmt = fmt;
432 vaf.va = &args;
433
434 printk(KERN_DEBUG "b43-%s debug: %pV",
435 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
436
e4d6b795
MB		 437 va_end(args);
438}
e4d6b795
MB		 439
440static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
441{
442 u32 macctl;
443
444 B43_WARN_ON(offset % 4 != 0);
445
446 macctl = b43_read32(dev, B43_MMIO_MACCTL);
447 if (macctl & B43_MACCTL_BE)
448 val = swab32(val);
449
450 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
451 mmiowb();
452 b43_write32(dev, B43_MMIO_RAM_DATA, val);
453}
454
280d0e16
MB		 455static inline void b43_shm_control_word(struct b43_wldev *dev,
456 u16 routing, u16 offset)
e4d6b795
MB		 457{
458 u32 control;
459
460 /* "offset" is the WORD offset. */
e4d6b795
MB		 461 control = routing;
462 control <<= 16;
463 control |= offset;
464 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
465}
466
69eddc8a 467u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 468{
469 u32 ret;
470
471 if (routing == B43_SHM_SHARED) {
472 B43_WARN_ON(offset & 0x0001);
473 if (offset & 0x0003) {
474 /* Unaligned access */
475 b43_shm_control_word(dev, routing, offset >> 2);
476 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 477 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 478 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 479
280d0e16 480 goto out;
e4d6b795
MB		 481 }
482 offset >>= 2;
483 }
484 b43_shm_control_word(dev, routing, offset);
485 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 486out:
e4d6b795
MB		 487 return ret;
488}
489
69eddc8a 490u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 491{
492 u16 ret;
493
e4d6b795
MB		 494 if (routing == B43_SHM_SHARED) {
495 B43_WARN_ON(offset & 0x0001);
496 if (offset & 0x0003) {
497 /* Unaligned access */
498 b43_shm_control_word(dev, routing, offset >> 2);
499 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
500
280d0e16 501 goto out;
e4d6b795
MB		 502 }
503 offset >>= 2;
504 }
505 b43_shm_control_word(dev, routing, offset);
506 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 507out:
e4d6b795
MB		 508 return ret;
509}
510
69eddc8a 511void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 512{
e4d6b795
MB		 513 if (routing == B43_SHM_SHARED) {
514 B43_WARN_ON(offset & 0x0001);
515 if (offset & 0x0003) {
516 /* Unaligned access */
517 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 518 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 519 value & 0xFFFF);
e4d6b795 520 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 521 b43_write16(dev, B43_MMIO_SHM_DATA,
522 (value >> 16) & 0xFFFF);
6bbc321a 523 return;
e4d6b795
MB		 524 }
525 offset >>= 2;
526 }
527 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 528 b43_write32(dev, B43_MMIO_SHM_DATA, value);
529}
530
69eddc8a 531void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 532{
e4d6b795
MB		 533 if (routing == B43_SHM_SHARED) {
534 B43_WARN_ON(offset & 0x0001);
535 if (offset & 0x0003) {
536 /* Unaligned access */
537 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 538 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 539 return;
e4d6b795
MB		 540 }
541 offset >>= 2;
542 }
543 b43_shm_control_word(dev, routing, offset);
e4d6b795 544 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 545}
546
e4d6b795 547/* Read HostFlags */
99da185a 548u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 549{
35f0d354 550 u64 ret;
e4d6b795 551
6e6a2cd5 552 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
e4d6b795 553 ret <<= 16;
6e6a2cd5 554 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
35f0d354 555 ret <<= 16;
6e6a2cd5 556 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
e4d6b795
MB		 557
558 return ret;
559}
560
561/* Write HostFlags */
35f0d354 562void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 563{
35f0d354
MB		 564 u16 lo, mi, hi;
565
566 lo = (value & 0x00000000FFFFULL);
567 mi = (value & 0x0000FFFF0000ULL) >> 16;
568 hi = (value & 0xFFFF00000000ULL) >> 32;
6e6a2cd5
RM		 569 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
570 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
571 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
e4d6b795
MB		 572}
573
403a3a13
MB		 574/* Read the firmware capabilities bitmask (Opensource firmware only) */
575static u16 b43_fwcapa_read(struct b43_wldev *dev)
576{
577 B43_WARN_ON(!dev->fw.opensource);
578 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
579}
580
3ebbbb56 581void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 582{
3ebbbb56
MB		 583 u32 low, high;
584
21d889d4 585 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 586
587 /* The hardware guarantees us an atomic read, if we
588 * read the low register first. */
589 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
590 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
591
592 *tsf = high;
593 *tsf <<= 32;
594 *tsf |= low;
e4d6b795
MB		 595}
596
597static void b43_time_lock(struct b43_wldev *dev)
598{
5056635c 599 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 600 /* Commit the write */
601 b43_read32(dev, B43_MMIO_MACCTL);
602}
603
604static void b43_time_unlock(struct b43_wldev *dev)
605{
5056635c 606 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 607 /* Commit the write */
608 b43_read32(dev, B43_MMIO_MACCTL);
609}
610
611static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
612{
3ebbbb56
MB		 613 u32 low, high;
614
21d889d4 615 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 616
617 low = tsf;
618 high = (tsf >> 32);
619 /* The hardware guarantees us an atomic write, if we
620 * write the low register first. */
621 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
622 mmiowb();
623 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
624 mmiowb();
e4d6b795
MB		 625}
626
627void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
628{
629 b43_time_lock(dev);
630 b43_tsf_write_locked(dev, tsf);
631 b43_time_unlock(dev);
632}
633
634static
99da185a 635void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 636{
637 static const u8 zero_addr[ETH_ALEN] = { 0 };
638 u16 data;
639
640 if (!mac)
641 mac = zero_addr;
642
643 offset |= 0x0020;
644 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
645
646 data = mac[0];
647 data |= mac[1] << 8;
648 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
649 data = mac[2];
650 data |= mac[3] << 8;
651 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
652 data = mac[4];
653 data |= mac[5] << 8;
654 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
655}
656
657static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
658{
659 const u8 *mac;
660 const u8 *bssid;
661 u8 mac_bssid[ETH_ALEN * 2];
662 int i;
663 u32 tmp;
664
665 bssid = dev->wl->bssid;
666 mac = dev->wl->mac_addr;
667
668 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
669
670 memcpy(mac_bssid, mac, ETH_ALEN);
671 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
672
673 /* Write our MAC address and BSSID to template ram */
674 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
675 tmp = (u32) (mac_bssid[i + 0]);
676 tmp |= (u32) (mac_bssid[i + 1]) << 8;
677 tmp |= (u32) (mac_bssid[i + 2]) << 16;
678 tmp |= (u32) (mac_bssid[i + 3]) << 24;
679 b43_ram_write(dev, 0x20 + i, tmp);
680 }
681}
682
4150c572 683static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 684{
e4d6b795 685 b43_write_mac_bssid_templates(dev);
4150c572 686 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 687}
688
689static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
690{
691 /* slot_time is in usec. */
b6c3f5be
LF		 692 /* This test used to exit for all but a G PHY. */
693 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 694 return;
b6c3f5be
LF		 695 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
696 /* Shared memory location 0x0010 is the slot time and should be
697 * set to slot_time; however, this register is initially 0 and changing
698 * the value adversely affects the transmit rate for BCM4311
699 * devices. Until this behavior is unterstood, delete this step
700 *
701 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
702 */
e4d6b795
MB		 703}
704
705static void b43_short_slot_timing_enable(struct b43_wldev *dev)
706{
707 b43_set_slot_time(dev, 9);
e4d6b795
MB		 708}
709
710static void b43_short_slot_timing_disable(struct b43_wldev *dev)
711{
712 b43_set_slot_time(dev, 20);
e4d6b795
MB		 713}
714
e4d6b795 715/* DummyTransmission function, as documented on
2f19c287 716 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 717 */
2f19c287 718void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 719{
720 struct b43_phy *phy = &dev->phy;
721 unsigned int i, max_loop;
722 u16 value;
723 u32 buffer[5] = {
724 0x00000000,
725 0x00D40000,
726 0x00000000,
727 0x01000000,
728 0x00000000,
729 };
730
2f19c287 731 if (ofdm) {
e4d6b795
MB		 732 max_loop = 0x1E;
733 buffer[0] = 0x000201CC;
2f19c287 734 } else {
e4d6b795
MB		 735 max_loop = 0xFA;
736 buffer[0] = 0x000B846E;
e4d6b795
MB		 737 }
738
739 for (i = 0; i < 5; i++)
740 b43_ram_write(dev, i * 4, buffer[i]);
741
7955d87f
RM		 742 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
743
21d889d4 744 if (dev->dev->core_rev < 11)
7955d87f 745 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 746 else
7955d87f
RM		 747 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
748
2f19c287 749 value = (ofdm ? 0x41 : 0x40);
7955d87f 750 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 751 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
752 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 753 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
754
755 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
756 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
757
758 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
759 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
760 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
761 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 762
763 if (!pa_on && phy->type == B43_PHYTYPE_N)
764 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 765
766 switch (phy->type) {
767 case B43_PHYTYPE_N:
93dbd828 768 case B43_PHYTYPE_LCN:
7955d87f 769 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 770 break;
771 case B43_PHYTYPE_LP:
7955d87f 772 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 773 break;
774 default:
7955d87f 775 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 776 }
93dbd828 777 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 778
779 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
780 b43_radio_write16(dev, 0x0051, 0x0017);
781 for (i = 0x00; i < max_loop; i++) {
7955d87f 782 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 783 if (value & 0x0080)
784 break;
785 udelay(10);
786 }
787 for (i = 0x00; i < 0x0A; i++) {
7955d87f 788 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 789 if (value & 0x0400)
790 break;
791 udelay(10);
792 }
1d280ddc 793 for (i = 0x00; i < 0x19; i++) {
7955d87f 794 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 795 if (!(value & 0x0100))
796 break;
797 udelay(10);
798 }
799 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
800 b43_radio_write16(dev, 0x0051, 0x0037);
801}
802
803static void key_write(struct b43_wldev *dev,
99da185a 804 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 805{
806 unsigned int i;
807 u32 offset;
808 u16 value;
809 u16 kidx;
810
811 /* Key index/algo block */
812 kidx = b43_kidx_to_fw(dev, index);
813 value = ((kidx << 4) | algorithm);
814 b43_shm_write16(dev, B43_SHM_SHARED,
815 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
816
817 /* Write the key to the Key Table Pointer offset */
818 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
819 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
820 value = key[i];
821 value |= (u16) (key[i + 1]) << 8;
822 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
823 }
824}
825
99da185a 826static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 827{
828 u32 addrtmp[2] = { 0, 0, };
66d2d089 829 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 830
831 if (b43_new_kidx_api(dev))
66d2d089 832 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 833
66d2d089
MB		 834 B43_WARN_ON(index < pairwise_keys_start);
835 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 836 * Physical mac 0 is mapped to physical key 4 or 8, depending
837 * on the firmware version.
838 * So we must adjust the index here.
839 */
66d2d089
MB		 840 index -= pairwise_keys_start;
841 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 842
843 if (addr) {
844 addrtmp[0] = addr[0];
845 addrtmp[0] |= ((u32) (addr[1]) << 8);
846 addrtmp[0] |= ((u32) (addr[2]) << 16);
847 addrtmp[0] |= ((u32) (addr[3]) << 24);
848 addrtmp[1] = addr[4];
849 addrtmp[1] |= ((u32) (addr[5]) << 8);
850 }
851
66d2d089
MB		 852 /* Receive match transmitter address (RCMTA) mechanism */
853 b43_shm_write32(dev, B43_SHM_RCMTA,
854 (index * 2) + 0, addrtmp[0]);
855 b43_shm_write16(dev, B43_SHM_RCMTA,
856 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 857}
858
035d0243 859/* The ucode will use phase1 key with TEK key to decrypt rx packets.
860 * When a packet is received, the iv32 is checked.
861 * - if it doesn't the packet is returned without modification (and software
862 * decryption can be done). That's what happen when iv16 wrap.
863 * - if it does, the rc4 key is computed, and decryption is tried.
864 * Either it will success and B43_RX_MAC_DEC is returned,
865 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
866 * and the packet is not usable (it got modified by the ucode).
867 * So in order to never have B43_RX_MAC_DECERR, we should provide
868 * a iv32 and phase1key that match. Because we drop packets in case of
869 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
870 * packets will be lost without higher layer knowing (ie no resync possible
871 * until next wrap).
872 *
873 * NOTE : this should support 50 key like RCMTA because
874 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
875 */
876static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
877 u16 *phase1key)
878{
879 unsigned int i;
880 u32 offset;
881 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
882
883 if (!modparam_hwtkip)
884 return;
885
886 if (b43_new_kidx_api(dev))
887 pairwise_keys_start = B43_NR_GROUP_KEYS;
888
889 B43_WARN_ON(index < pairwise_keys_start);
890 /* We have four default TX keys and possibly four default RX keys.
891 * Physical mac 0 is mapped to physical key 4 or 8, depending
892 * on the firmware version.
893 * So we must adjust the index here.
894 */
895 index -= pairwise_keys_start;
896 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
897
898 if (b43_debug(dev, B43_DBG_KEYS)) {
899 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
900 index, iv32);
901 }
902 /* Write the key to the RX tkip shared mem */
903 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
904 for (i = 0; i < 10; i += 2) {
905 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
906 phase1key ? phase1key[i / 2] : 0);
907 }
908 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
909 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
910}
911
912static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 913 struct ieee80211_vif *vif,
914 struct ieee80211_key_conf *keyconf,
915 struct ieee80211_sta *sta,
916 u32 iv32, u16 *phase1key)
035d0243 917{
918 struct b43_wl *wl = hw_to_b43_wl(hw);
919 struct b43_wldev *dev;
920 int index = keyconf->hw_key_idx;
921
922 if (B43_WARN_ON(!modparam_hwtkip))
923 return;
924
96869a39
MB		 925 /* This is only called from the RX path through mac80211, where
926 * our mutex is already locked. */
927 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 928 dev = wl->current_dev;
96869a39 929 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 930
931 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
932
933 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 934 /* only pairwise TKIP keys are supported right now */
935 if (WARN_ON(!sta))
96869a39 936 return;
b3fbdcf4 937 keymac_write(dev, index, sta->addr);
035d0243 938}
939
e4d6b795
MB		 940static void do_key_write(struct b43_wldev *dev,
941 u8 index, u8 algorithm,
99da185a 942 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 943{
944 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 945 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 946
947 if (b43_new_kidx_api(dev))
66d2d089 948 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 949
66d2d089 950 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 951 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
952
66d2d089 953 if (index >= pairwise_keys_start)
e4d6b795 954 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 955 if (algorithm == B43_SEC_ALGO_TKIP) {
956 /*
957 * We should provide an initial iv32, phase1key pair.
958 * We could start with iv32=0 and compute the corresponding
959 * phase1key, but this means calling ieee80211_get_tkip_key
960 * with a fake skb (or export other tkip function).
961 * Because we are lazy we hope iv32 won't start with
962 * 0xffffffff and let's b43_op_update_tkip_key provide a
963 * correct pair.
964 */
965 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
966 } else if (index >= pairwise_keys_start) /* clear it */
967 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 968 if (key)
969 memcpy(buf, key, key_len);
970 key_write(dev, index, algorithm, buf);
66d2d089 971 if (index >= pairwise_keys_start)
e4d6b795
MB		 972 keymac_write(dev, index, mac_addr);
973
974 dev->key[index].algorithm = algorithm;
975}
976
977static int b43_key_write(struct b43_wldev *dev,
978 int index, u8 algorithm,
99da185a
JD		 979 const u8 *key, size_t key_len,
980 const u8 *mac_addr,
e4d6b795
MB		 981 struct ieee80211_key_conf *keyconf)
982{
983 int i;
66d2d089 984 int pairwise_keys_start;
e4d6b795 985
035d0243 986 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
987 * - Temporal Encryption Key (128 bits)
988 * - Temporal Authenticator Tx MIC Key (64 bits)
989 * - Temporal Authenticator Rx MIC Key (64 bits)
990 *
991 * Hardware only store TEK
992 */
993 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
994 key_len = 16;
e4d6b795
MB		 995 if (key_len > B43_SEC_KEYSIZE)
996 return -EINVAL;
66d2d089 997 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 998 /* Check that we don't already have this key. */
999 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1000 }
1001 if (index < 0) {
e808e586 1002 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 1003 if (b43_new_kidx_api(dev))
66d2d089 1004 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 1005 else
66d2d089
MB		 1006 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1007 for (i = pairwise_keys_start;
1008 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1009 i++) {
1010 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 1011 if (!dev->key[i].keyconf) {
1012 /* found empty */
1013 index = i;
1014 break;
1015 }
1016 }
1017 if (index < 0) {
e808e586 1018 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1019 return -ENOSPC;
1020 }
1021 } else
1022 B43_WARN_ON(index > 3);
1023
1024 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1025 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1026 /* Default RX key */
1027 B43_WARN_ON(mac_addr);
1028 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1029 }
1030 keyconf->hw_key_idx = index;
1031 dev->key[index].keyconf = keyconf;
1032
1033 return 0;
1034}
1035
1036static int b43_key_clear(struct b43_wldev *dev, int index)
1037{
66d2d089 1038 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1039 return -EINVAL;
1040 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1041 NULL, B43_SEC_KEYSIZE, NULL);
1042 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1043 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1044 NULL, B43_SEC_KEYSIZE, NULL);
1045 }
1046 dev->key[index].keyconf = NULL;
1047
1048 return 0;
1049}
1050
1051static void b43_clear_keys(struct b43_wldev *dev)
1052{
66d2d089 1053 int i, count;
e4d6b795 1054
66d2d089
MB		 1055 if (b43_new_kidx_api(dev))
1056 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1057 else
1058 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1059 for (i = 0; i < count; i++)
e4d6b795
MB		 1060 b43_key_clear(dev, i);
1061}
1062
9cf7f247
MB		 1063static void b43_dump_keymemory(struct b43_wldev *dev)
1064{
66d2d089 1065 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1066 u8 mac[ETH_ALEN];
1067 u16 algo;
1068 u32 rcmta0;
1069 u16 rcmta1;
1070 u64 hf;
1071 struct b43_key *key;
1072
1073 if (!b43_debug(dev, B43_DBG_KEYS))
1074 return;
1075
1076 hf = b43_hf_read(dev);
1077 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1078 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1079 if (b43_new_kidx_api(dev)) {
1080 pairwise_keys_start = B43_NR_GROUP_KEYS;
1081 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1082 } else {
1083 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1084 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1085 }
1086 for (index = 0; index < count; index++) {
9cf7f247
MB		 1087 key = &(dev->key[index]);
1088 printk(KERN_DEBUG "Key slot %02u: %s",
1089 index, (key->keyconf == NULL) ? " " : "*");
1090 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1091 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1092 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1093 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1094 }
1095
1096 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1097 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1098 printk(" Algo: %04X/%02X", algo, key->algorithm);
1099
66d2d089 1100 if (index >= pairwise_keys_start) {
035d0243 1101 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1102 printk(" TKIP: ");
1103 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1104 for (i = 0; i < 14; i += 2) {
1105 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1106 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1107 }
1108 }
9cf7f247 1109 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1110 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1111 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1112 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1113 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1114 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1115 printk(" MAC: %pM", mac);
9cf7f247
MB		 1116 } else
1117 printk(" DEFAULT KEY");
1118 printk("\n");
1119 }
1120}
1121
e4d6b795
MB		 1122void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1123{
1124 u32 macctl;
1125 u16 ucstat;
1126 bool hwps;
1127 bool awake;
1128 int i;
1129
1130 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1131 (ps_flags & B43_PS_DISABLED));
1132 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1133
1134 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1135 hwps = true;
e4d6b795 1136 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1137 hwps = false;
e4d6b795
MB		 1138 } else {
1139 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1140 // and thus is not an AP and we are associated, set bit 25
1141 }
1142 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1143 awake = true;
e4d6b795 1144 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1145 awake = false;
e4d6b795
MB		 1146 } else {
1147 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1148 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1149 // successful, set bit26
1150 }
1151
1152/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1153 hwps = false;
1154 awake = true;
e4d6b795
MB		 1155
1156 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1157 if (hwps)
1158 macctl |= B43_MACCTL_HWPS;
1159 else
1160 macctl &= ~B43_MACCTL_HWPS;
1161 if (awake)
1162 macctl |= B43_MACCTL_AWAKE;
1163 else
1164 macctl &= ~B43_MACCTL_AWAKE;
1165 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1166 /* Commit write */
1167 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1168 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1169 /* Wait for the microcode to wake up. */
1170 for (i = 0; i < 100; i++) {
1171 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1172 B43_SHM_SH_UCODESTAT);
1173 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1174 break;
1175 udelay(10);
1176 }
1177 }
1178}
1179
42c9a458 1180#ifdef CONFIG_B43_BCMA
49173592 1181static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1182{
49173592 1183 u32 flags;
42c9a458 1184
49173592
RM		 1185 /* Put PHY into reset */
1186 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1187 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1188 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1189 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1190 udelay(2);
1191
50c1b59e 1192 b43_phy_take_out_of_reset(dev);
49173592 1193}
42c9a458 1194
49173592
RM		 1195static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1196{
88cceab5
RM		 1197 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1198 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1199 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1200 B43_BCMA_CLKCTLST_PHY_PLL_ST;
6b9e03e6
RM		 1201 u32 flags;
1202
1203 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1204 if (gmode)
1205 flags |= B43_BCMA_IOCTL_GMODE;
1206 b43_device_enable(dev, flags);
88cceab5 1207
49173592
RM		 1208 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1209 b43_bcma_phy_reset(dev);
88cceab5 1210 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
42c9a458
RM		 1211}
1212#endif
1213
bd7c8a59 1214#ifdef CONFIG_B43_SSB
4da909e7 1215static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1216{
4da909e7 1217 u32 flags = 0;
e4d6b795 1218
4da909e7
RM		 1219 if (gmode)
1220 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1221 flags |= B43_TMSLOW_PHYCLKEN;
1222 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1223 if (dev->phy.type == B43_PHYTYPE_N)
1224 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1225 b43_device_enable(dev, flags);
e4d6b795
MB		 1226 msleep(2); /* Wait for the PLL to turn on. */
1227
50c1b59e 1228 b43_phy_take_out_of_reset(dev);
1495298d 1229}
bd7c8a59 1230#endif
1495298d 1231
4da909e7 1232void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1233{
1234 u32 macctl;
1235
6cbab0d9 1236 switch (dev->dev->bus_type) {
42c9a458
RM		 1237#ifdef CONFIG_B43_BCMA
1238 case B43_BUS_BCMA:
1239 b43_bcma_wireless_core_reset(dev, gmode);
1240 break;
1241#endif
6cbab0d9
RM		 1242#ifdef CONFIG_B43_SSB
1243 case B43_BUS_SSB:
1244 b43_ssb_wireless_core_reset(dev, gmode);
1245 break;
1246#endif
1247 }
e4d6b795 1248
fb11137a
MB		 1249 /* Turn Analog ON, but only if we already know the PHY-type.
1250 * This protects against very early setup where we don't know the
1251 * PHY-type, yet. wireless_core_reset will be called once again later,
1252 * when we know the PHY-type. */
1253 if (dev->phy.ops)
cb24f57f 1254 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1255
1256 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1257 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1258 if (gmode)
e4d6b795
MB		 1259 macctl |= B43_MACCTL_GMODE;
1260 macctl |= B43_MACCTL_IHR_ENABLED;
1261 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1262}
1263
1264static void handle_irq_transmit_status(struct b43_wldev *dev)
1265{
1266 u32 v0, v1;
1267 u16 tmp;
1268 struct b43_txstatus stat;
1269
1270 while (1) {
1271 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1272 if (!(v0 & 0x00000001))
1273 break;
1274 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1275
1276 stat.cookie = (v0 >> 16);
1277 stat.seq = (v1 & 0x0000FFFF);
1278 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1279 tmp = (v0 & 0x0000FFFF);
1280 stat.frame_count = ((tmp & 0xF000) >> 12);
1281 stat.rts_count = ((tmp & 0x0F00) >> 8);
1282 stat.supp_reason = ((tmp & 0x001C) >> 2);
1283 stat.pm_indicated = !!(tmp & 0x0080);
1284 stat.intermediate = !!(tmp & 0x0040);
1285 stat.for_ampdu = !!(tmp & 0x0020);
1286 stat.acked = !!(tmp & 0x0002);
1287
1288 b43_handle_txstatus(dev, &stat);
1289 }
1290}
1291
1292static void drain_txstatus_queue(struct b43_wldev *dev)
1293{
1294 u32 dummy;
1295
21d889d4 1296 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1297 return;
1298 /* Read all entries from the microcode TXstatus FIFO
1299 * and throw them away.
1300 */
1301 while (1) {
1302 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1303 if (!(dummy & 0x00000001))
1304 break;
1305 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1306 }
1307}
1308
1309static u32 b43_jssi_read(struct b43_wldev *dev)
1310{
1311 u32 val = 0;
1312
5c1da23b 1313 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
e4d6b795 1314 val <<= 16;
5c1da23b 1315 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
e4d6b795
MB		 1316
1317 return val;
1318}
1319
1320static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1321{
5c1da23b
HM		 1322 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1323 (jssi & 0x0000FFFF));
1324 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1325 (jssi & 0xFFFF0000) >> 16);
e4d6b795
MB		 1326}
1327
1328static void b43_generate_noise_sample(struct b43_wldev *dev)
1329{
1330 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1331 b43_write32(dev, B43_MMIO_MACCMD,
1332 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1333}
1334
1335static void b43_calculate_link_quality(struct b43_wldev *dev)
1336{
1337 /* Top half of Link Quality calculation. */
1338
ef1a628d
MB		 1339 if (dev->phy.type != B43_PHYTYPE_G)
1340 return;
e4d6b795
MB		 1341 if (dev->noisecalc.calculation_running)
1342 return;
3db1cd5c 1343 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1344 dev->noisecalc.nr_samples = 0;
1345
1346 b43_generate_noise_sample(dev);
1347}
1348
1349static void handle_irq_noise(struct b43_wldev *dev)
1350{
ef1a628d 1351 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1352 u16 tmp;
1353 u8 noise[4];
1354 u8 i, j;
1355 s32 average;
1356
1357 /* Bottom half of Link Quality calculation. */
1358
ef1a628d
MB		 1359 if (dev->phy.type != B43_PHYTYPE_G)
1360 return;
1361
98a3b2fe
MB		 1362 /* Possible race condition: It might be possible that the user
1363 * changed to a different channel in the meantime since we
1364 * started the calculation. We ignore that fact, since it's
1365 * not really that much of a problem. The background noise is
1366 * an estimation only anyway. Slightly wrong results will get damped
1367 * by the averaging of the 8 sample rounds. Additionally the
1368 * value is shortlived. So it will be replaced by the next noise
1369 * calculation round soon. */
1370
e4d6b795 1371 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1372 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1373 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1374 noise[2] == 0x7F || noise[3] == 0x7F)
1375 goto generate_new;
1376
1377 /* Get the noise samples. */
1378 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1379 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1380 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1381 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1382 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1383 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1384 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1385 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1386 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1387 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1388 dev->noisecalc.nr_samples++;
1389 if (dev->noisecalc.nr_samples == 8) {
1390 /* Calculate the Link Quality by the noise samples. */
1391 average = 0;
1392 for (i = 0; i < 8; i++) {
1393 for (j = 0; j < 4; j++)
1394 average += dev->noisecalc.samples[i][j];
1395 }
1396 average /= (8 * 4);
1397 average *= 125;
1398 average += 64;
1399 average /= 128;
1400 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1401 tmp = (tmp / 128) & 0x1F;
1402 if (tmp >= 8)
1403 average += 2;
1404 else
1405 average -= 25;
1406 if (tmp == 8)
1407 average -= 72;
1408 else
1409 average -= 48;
1410
1411 dev->stats.link_noise = average;
3db1cd5c 1412 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1413 return;
1414 }
98a3b2fe 1415generate_new:
e4d6b795
MB		 1416 b43_generate_noise_sample(dev);
1417}
1418
1419static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1420{
05c914fe 1421 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1422 ///TODO: PS TBTT
1423 } else {
1424 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1425 b43_power_saving_ctl_bits(dev, 0);
1426 }
05c914fe 1427 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1428 dev->dfq_valid = true;
e4d6b795
MB		 1429}
1430
1431static void handle_irq_atim_end(struct b43_wldev *dev)
1432{
aa6c7ae2
MB		 1433 if (dev->dfq_valid) {
1434 b43_write32(dev, B43_MMIO_MACCMD,
1435 b43_read32(dev, B43_MMIO_MACCMD)
1436 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1437 dev->dfq_valid = false;
aa6c7ae2 1438 }
e4d6b795
MB		 1439}
1440
1441static void handle_irq_pmq(struct b43_wldev *dev)
1442{
1443 u32 tmp;
1444
1445 //TODO: AP mode.
1446
1447 while (1) {
1448 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1449 if (!(tmp & 0x00000008))
1450 break;
1451 }
1452 /* 16bit write is odd, but correct. */
1453 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1454}
1455
1456static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1457 const u8 *data, u16 size,
e4d6b795
MB		 1458 u16 ram_offset,
1459 u16 shm_size_offset, u8 rate)
1460{
1461 u32 i, tmp;
1462 struct b43_plcp_hdr4 plcp;
1463
1464 plcp.data = 0;
1465 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1466 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1467 ram_offset += sizeof(u32);
1468 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1469 * So leave the first two bytes of the next write blank.
1470 */
1471 tmp = (u32) (data[0]) << 16;
1472 tmp |= (u32) (data[1]) << 24;
1473 b43_ram_write(dev, ram_offset, tmp);
1474 ram_offset += sizeof(u32);
1475 for (i = 2; i < size; i += sizeof(u32)) {
1476 tmp = (u32) (data[i + 0]);
1477 if (i + 1 < size)
1478 tmp |= (u32) (data[i + 1]) << 8;
1479 if (i + 2 < size)
1480 tmp |= (u32) (data[i + 2]) << 16;
1481 if (i + 3 < size)
1482 tmp |= (u32) (data[i + 3]) << 24;
1483 b43_ram_write(dev, ram_offset + i - 2, tmp);
1484 }
1485 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1486 size + sizeof(struct b43_plcp_hdr6));
1487}
1488
5042c507
MB		 1489/* Check if the use of the antenna that ieee80211 told us to
1490 * use is possible. This will fall back to DEFAULT.
1491 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1492u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1493 u8 antenna_nr)
1494{
1495 u8 antenna_mask;
1496
1497 if (antenna_nr == 0) {
1498 /* Zero means "use default antenna". That's always OK. */
1499 return 0;
1500 }
1501
1502 /* Get the mask of available antennas. */
1503 if (dev->phy.gmode)
0581483a 1504 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1505 else
0581483a 1506 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1507
1508 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1509 /* This antenna is not available. Fall back to default. */
1510 return 0;
1511 }
1512
1513 return antenna_nr;
1514}
1515
5042c507
MB		 1516/* Convert a b43 antenna number value to the PHY TX control value. */
1517static u16 b43_antenna_to_phyctl(int antenna)
1518{
1519 switch (antenna) {
1520 case B43_ANTENNA0:
1521 return B43_TXH_PHY_ANT0;
1522 case B43_ANTENNA1:
1523 return B43_TXH_PHY_ANT1;
1524 case B43_ANTENNA2:
1525 return B43_TXH_PHY_ANT2;
1526 case B43_ANTENNA3:
1527 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1528 case B43_ANTENNA_AUTO0:
1529 case B43_ANTENNA_AUTO1:
5042c507
MB		 1530 return B43_TXH_PHY_ANT01AUTO;
1531 }
1532 B43_WARN_ON(1);
1533 return 0;
1534}
1535
e4d6b795
MB		 1536static void b43_write_beacon_template(struct b43_wldev *dev,
1537 u16 ram_offset,
5042c507 1538 u16 shm_size_offset)
e4d6b795 1539{
47f76ca3 1540 unsigned int i, len, variable_len;
e66fee6a
MB		 1541 const struct ieee80211_mgmt *bcn;
1542 const u8 *ie;
3db1cd5c 1543 bool tim_found = false;
5042c507
MB		 1544 unsigned int rate;
1545 u16 ctl;
1546 int antenna;
e039fa4a 1547 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1548
e66fee6a 1549 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
c8e49556 1550 len = min_t(size_t, dev->wl->current_beacon->len,
e4d6b795 1551 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1552 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1553
1554 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1555 len, ram_offset, shm_size_offset, rate);
e66fee6a 1556
5042c507 1557 /* Write the PHY TX control parameters. */
0f4ac38b 1558 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1559 antenna = b43_antenna_to_phyctl(antenna);
1560 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1561 /* We can't send beacons with short preamble. Would get PHY errors. */
1562 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1563 ctl &= ~B43_TXH_PHY_ANT;
1564 ctl &= ~B43_TXH_PHY_ENC;
1565 ctl |= antenna;
1566 if (b43_is_cck_rate(rate))
1567 ctl |= B43_TXH_PHY_ENC_CCK;
1568 else
1569 ctl |= B43_TXH_PHY_ENC_OFDM;
1570 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1571
e66fee6a
MB		 1572 /* Find the position of the TIM and the DTIM_period value
1573 * and write them to SHM. */
1574 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1575 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1576 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1577 uint8_t ie_id, ie_len;
1578
1579 ie_id = ie[i];
1580 ie_len = ie[i + 1];
1581 if (ie_id == 5) {
1582 u16 tim_position;
1583 u16 dtim_period;
1584 /* This is the TIM Information Element */
1585
1586 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1587 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1588 break;
1589 /* A valid TIM is at least 4 bytes long. */
1590 if (ie_len < 4)
1591 break;
3db1cd5c 1592 tim_found = true;
e66fee6a
MB		 1593
1594 tim_position = sizeof(struct b43_plcp_hdr6);
1595 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1596 tim_position += i;
1597
1598 dtim_period = ie[i + 3];
1599
1600 b43_shm_write16(dev, B43_SHM_SHARED,
1601 B43_SHM_SH_TIMBPOS, tim_position);
1602 b43_shm_write16(dev, B43_SHM_SHARED,
1603 B43_SHM_SH_DTIMPER, dtim_period);
1604 break;
1605 }
1606 i += ie_len + 2;
1607 }
1608 if (!tim_found) {
04dea136
JB		 1609 /*
1610 * If ucode wants to modify TIM do it behind the beacon, this
1611 * will happen, for example, when doing mesh networking.
1612 */
1613 b43_shm_write16(dev, B43_SHM_SHARED,
1614 B43_SHM_SH_TIMBPOS,
1615 len + sizeof(struct b43_plcp_hdr6));
1616 b43_shm_write16(dev, B43_SHM_SHARED,
1617 B43_SHM_SH_DTIMPER, 0);
1618 }
1619 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1620}
1621
6b4bec01
MB		 1622static void b43_upload_beacon0(struct b43_wldev *dev)
1623{
1624 struct b43_wl *wl = dev->wl;
1625
1626 if (wl->beacon0_uploaded)
1627 return;
5c1da23b 1628 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
3db1cd5c 1629 wl->beacon0_uploaded = true;
6b4bec01
MB		 1630}
1631
1632static void b43_upload_beacon1(struct b43_wldev *dev)
1633{
1634 struct b43_wl *wl = dev->wl;
1635
1636 if (wl->beacon1_uploaded)
1637 return;
5c1da23b 1638 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
3db1cd5c 1639 wl->beacon1_uploaded = true;
6b4bec01
MB		 1640}
1641
c97a4ccc
MB		 1642static void handle_irq_beacon(struct b43_wldev *dev)
1643{
1644 struct b43_wl *wl = dev->wl;
1645 u32 cmd, beacon0_valid, beacon1_valid;
1646
05c914fe 1647 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1648 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1649 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1650 return;
1651
1652 /* This is the bottom half of the asynchronous beacon update. */
1653
1654 /* Ignore interrupt in the future. */
13790728 1655 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1656
1657 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1658 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1659 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1660
1661 /* Schedule interrupt manually, if busy. */
1662 if (beacon0_valid && beacon1_valid) {
1663 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1664 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1665 return;
1666 }
1667
6b4bec01
MB		 1668 if (unlikely(wl->beacon_templates_virgin)) {
1669 /* We never uploaded a beacon before.
1670 * Upload both templates now, but only mark one valid. */
3db1cd5c 1671 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1672 b43_upload_beacon0(dev);
1673 b43_upload_beacon1(dev);
c97a4ccc
MB		 1674 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1675 cmd |= B43_MACCMD_BEACON0_VALID;
1676 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1677 } else {
1678 if (!beacon0_valid) {
1679 b43_upload_beacon0(dev);
1680 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1681 cmd |= B43_MACCMD_BEACON0_VALID;
1682 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1683 } else if (!beacon1_valid) {
1684 b43_upload_beacon1(dev);
1685 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1686 cmd |= B43_MACCMD_BEACON1_VALID;
1687 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1688 }
c97a4ccc
MB		 1689 }
1690}
1691
36dbd954
MB		 1692static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1693{
1694 u32 old_irq_mask = dev->irq_mask;
1695
1696 /* update beacon right away or defer to irq */
1697 handle_irq_beacon(dev);
1698 if (old_irq_mask != dev->irq_mask) {
1699 /* The handler updated the IRQ mask. */
1700 B43_WARN_ON(!dev->irq_mask);
1701 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1702 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1703 } else {
1704 /* Device interrupts are currently disabled. That means
1705 * we just ran the hardirq handler and scheduled the
1706 * IRQ thread. The thread will write the IRQ mask when
1707 * it finished, so there's nothing to do here. Writing
1708 * the mask _here_ would incorrectly re-enable IRQs. */
1709 }
1710 }
1711}
1712
a82d9922
MB		 1713static void b43_beacon_update_trigger_work(struct work_struct *work)
1714{
1715 struct b43_wl *wl = container_of(work, struct b43_wl,
1716 beacon_update_trigger);
1717 struct b43_wldev *dev;
1718
1719 mutex_lock(&wl->mutex);
1720 dev = wl->current_dev;
1721 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1722 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1723 /* wl->mutex is enough. */
1724 b43_do_beacon_update_trigger_work(dev);
1725 mmiowb();
1726 } else {
1727 spin_lock_irq(&wl->hardirq_lock);
1728 b43_do_beacon_update_trigger_work(dev);
1729 mmiowb();
1730 spin_unlock_irq(&wl->hardirq_lock);
1731 }
a82d9922
MB		 1732 }
1733 mutex_unlock(&wl->mutex);
1734}
1735
d4df6f1a 1736/* Asynchronously update the packet templates in template RAM.
36dbd954 1737 * Locking: Requires wl->mutex to be locked. */
9d139c81 1738static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1739{
9d139c81
JB		 1740 struct sk_buff *beacon;
1741
e66fee6a
MB		 1742 /* This is the top half of the ansynchronous beacon update.
1743 * The bottom half is the beacon IRQ.
1744 * Beacon update must be asynchronous to avoid sending an
1745 * invalid beacon. This can happen for example, if the firmware
1746 * transmits a beacon while we are updating it. */
e4d6b795 1747
9d139c81
JB		 1748 /* We could modify the existing beacon and set the aid bit in
1749 * the TIM field, but that would probably require resizing and
1750 * moving of data within the beacon template.
1751 * Simply request a new beacon and let mac80211 do the hard work. */
1752 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1753 if (unlikely(!beacon))
1754 return;
1755
e66fee6a
MB		 1756 if (wl->current_beacon)
1757 dev_kfree_skb_any(wl->current_beacon);
1758 wl->current_beacon = beacon;
3db1cd5c
RR		 1759 wl->beacon0_uploaded = false;
1760 wl->beacon1_uploaded = false;
42935eca 1761 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1762}
1763
e4d6b795
MB		 1764static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1765{
1766 b43_time_lock(dev);
21d889d4 1767 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1768 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1769 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1770 } else {
1771 b43_write16(dev, 0x606, (beacon_int >> 6));
1772 b43_write16(dev, 0x610, beacon_int);
1773 }
1774 b43_time_unlock(dev);
a82d9922 1775 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1776}
1777
afa83e23
MB		 1778static void b43_handle_firmware_panic(struct b43_wldev *dev)
1779{
1780 u16 reason;
1781
1782 /* Read the register that contains the reason code for the panic. */
1783 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1784 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1785
1786 switch (reason) {
1787 default:
1788 b43dbg(dev->wl, "The panic reason is unknown.\n");
1789 /* fallthrough */
1790 case B43_FWPANIC_DIE:
1791 /* Do not restart the controller or firmware.
1792 * The device is nonfunctional from now on.
1793 * Restarting would result in this panic to trigger again,
1794 * so we avoid that recursion. */
1795 break;
1796 case B43_FWPANIC_RESTART:
1797 b43_controller_restart(dev, "Microcode panic");
1798 break;
1799 }
1800}
1801
e4d6b795
MB		 1802static void handle_irq_ucode_debug(struct b43_wldev *dev)
1803{
e48b0eeb 1804 unsigned int i, cnt;
53c06856 1805 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1806 __le16 *buf;
1807
1808 /* The proprietary firmware doesn't have this IRQ. */
1809 if (!dev->fw.opensource)
1810 return;
1811
afa83e23
MB		 1812 /* Read the register that contains the reason code for this IRQ. */
1813 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1814
e48b0eeb
MB		 1815 switch (reason) {
1816 case B43_DEBUGIRQ_PANIC:
afa83e23 1817 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1818 break;
1819 case B43_DEBUGIRQ_DUMP_SHM:
1820 if (!B43_DEBUG)
1821 break; /* Only with driver debugging enabled. */
1822 buf = kmalloc(4096, GFP_ATOMIC);
1823 if (!buf) {
1824 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1825 goto out;
1826 }
1827 for (i = 0; i < 4096; i += 2) {
1828 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1829 buf[i / 2] = cpu_to_le16(tmp);
1830 }
1831 b43info(dev->wl, "Shared memory dump:\n");
1832 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1833 16, 2, buf, 4096, 1);
1834 kfree(buf);
1835 break;
1836 case B43_DEBUGIRQ_DUMP_REGS:
1837 if (!B43_DEBUG)
1838 break; /* Only with driver debugging enabled. */
1839 b43info(dev->wl, "Microcode register dump:\n");
1840 for (i = 0, cnt = 0; i < 64; i++) {
1841 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1842 if (cnt == 0)
1843 printk(KERN_INFO);
1844 printk("r%02u: 0x%04X ", i, tmp);
1845 cnt++;
1846 if (cnt == 6) {
1847 printk("\n");
1848 cnt = 0;
1849 }
1850 }
1851 printk("\n");
1852 break;
53c06856
MB		 1853 case B43_DEBUGIRQ_MARKER:
1854 if (!B43_DEBUG)
1855 break; /* Only with driver debugging enabled. */
1856 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1857 B43_MARKER_ID_REG);
1858 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1859 B43_MARKER_LINE_REG);
1860 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1861 "at line number %u\n",
1862 marker_id, marker_line);
1863 break;
e48b0eeb
MB		 1864 default:
1865 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1866 reason);
1867 }
1868out:
afa83e23
MB		 1869 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1870 b43_shm_write16(dev, B43_SHM_SCRATCH,
1871 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1872}
1873
36dbd954 1874static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1875{
1876 u32 reason;
1877 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1878 u32 merged_dma_reason = 0;
21954c36 1879 int i;
e4d6b795 1880
36dbd954
MB		 1881 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1882 return;
e4d6b795
MB		 1883
1884 reason = dev->irq_reason;
1885 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1886 dma_reason[i] = dev->dma_reason[i];
1887 merged_dma_reason |= dma_reason[i];
1888 }
1889
1890 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1891 b43err(dev->wl, "MAC transmission error\n");
1892
00e0b8cb 1893 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1894 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1895 rmb();
1896 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1897 atomic_set(&dev->phy.txerr_cnt,
1898 B43_PHY_TX_BADNESS_LIMIT);
1899 b43err(dev->wl, "Too many PHY TX errors, "
1900 "restarting the controller\n");
1901 b43_controller_restart(dev, "PHY TX errors");
1902 }
1903 }
e4d6b795 1904
73b82bf0
TJ		 1905 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1906 b43err(dev->wl,
1907 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1908 dma_reason[0], dma_reason[1],
1909 dma_reason[2], dma_reason[3],
1910 dma_reason[4], dma_reason[5]);
1911 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1912 "on your system. It will now be switched to PIO.\n");
73b82bf0
TJ		 1913 /* Fall back to PIO transfers if we get fatal DMA errors! */
1914 dev->use_pio = true;
1915 b43_controller_restart(dev, "DMA error");
1916 return;
e4d6b795
MB		 1917 }
1918
1919 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1920 handle_irq_ucode_debug(dev);
1921 if (reason & B43_IRQ_TBTT_INDI)
1922 handle_irq_tbtt_indication(dev);
1923 if (reason & B43_IRQ_ATIM_END)
1924 handle_irq_atim_end(dev);
1925 if (reason & B43_IRQ_BEACON)
1926 handle_irq_beacon(dev);
1927 if (reason & B43_IRQ_PMQ)
1928 handle_irq_pmq(dev);
21954c36
MB		 1929 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1930 ;/* TODO */
1931 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1932 handle_irq_noise(dev);
1933
1934 /* Check the DMA reason registers for received data. */
73b82bf0
TJ		 1935 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1936 if (B43_DEBUG)
1937 b43warn(dev->wl, "RX descriptor underrun\n");
1938 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1939 }
5100d5ac
MB		 1940 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941 if (b43_using_pio_transfers(dev))
1942 b43_pio_rx(dev->pio.rx_queue);
1943 else
1944 b43_dma_rx(dev->dma.rx_ring);
1945 }
e4d6b795
MB		 1946 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1948 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1949 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1951
21954c36 1952 if (reason & B43_IRQ_TX_OK)
e4d6b795 1953 handle_irq_transmit_status(dev);
e4d6b795 1954
36dbd954 1955 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1956 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1957
1958#if B43_DEBUG
1959 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1960 dev->irq_count++;
1961 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962 if (reason & (1 << i))
1963 dev->irq_bit_count[i]++;
1964 }
1965 }
1966#endif
e4d6b795
MB		 1967}
1968
36dbd954
MB		 1969/* Interrupt thread handler. Handles device interrupts in thread context. */
1970static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1971{
36dbd954 1972 struct b43_wldev *dev = dev_id;
e4d6b795 1973
36dbd954
MB		 1974 mutex_lock(&dev->wl->mutex);
1975 b43_do_interrupt_thread(dev);
1976 mmiowb();
1977 mutex_unlock(&dev->wl->mutex);
1978
1979 return IRQ_HANDLED;
e4d6b795
MB		 1980}
1981
36dbd954 1982static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1983{
e4d6b795
MB		 1984 u32 reason;
1985
36dbd954
MB		 1986 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987 * On SDIO, this runs under wl->mutex. */
e4d6b795 1988
e4d6b795
MB		 1989 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1991 return IRQ_NONE;
13790728 1992 reason &= dev->irq_mask;
e4d6b795 1993 if (!reason)
cae56147 1994 return IRQ_NONE;
e4d6b795
MB		 1995
1996 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
73b82bf0 1997 & 0x0001FC00;
e4d6b795
MB		 1998 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1999 & 0x0000DC00;
2000 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2001 & 0x0000DC00;
2002 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2003 & 0x0001DC00;
2004 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2005 & 0x0000DC00;
13790728 2006/* Unused ring
e4d6b795
MB		 2007 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2008 & 0x0000DC00;
13790728 2009*/
e4d6b795 2010
36dbd954
MB		 2011 /* ACK the interrupt. */
2012 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2018/* Unused ring
2019 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2020*/
2021
2022 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2023 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2024 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2025 dev->irq_reason = reason;
36dbd954
MB		 2026
2027 return IRQ_WAKE_THREAD;
2028}
2029
2030/* Interrupt handler top-half. This runs with interrupts disabled. */
2031static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2032{
2033 struct b43_wldev *dev = dev_id;
2034 irqreturn_t ret;
2035
2036 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2037 return IRQ_NONE;
2038
2039 spin_lock(&dev->wl->hardirq_lock);
2040 ret = b43_do_interrupt(dev);
e4d6b795 2041 mmiowb();
36dbd954 2042 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2043
2044 return ret;
2045}
2046
3dbba8e2
AH		 2047/* SDIO interrupt handler. This runs in process context. */
2048static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2049{
2050 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2051 irqreturn_t ret;
2052
3dbba8e2 2053 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2054
2055 ret = b43_do_interrupt(dev);
2056 if (ret == IRQ_WAKE_THREAD)
2057 b43_do_interrupt_thread(dev);
2058
3dbba8e2
AH		 2059 mutex_unlock(&wl->mutex);
2060}
2061
1a9f5093 2062void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2063{
2064 release_firmware(fw->data);
2065 fw->data = NULL;
2066 fw->filename = NULL;
2067}
2068
e4d6b795
MB		 2069static void b43_release_firmware(struct b43_wldev *dev)
2070{
0673effd 2071 complete(&dev->fw_load_complete);
1a9f5093
MB		 2072 b43_do_release_fw(&dev->fw.ucode);
2073 b43_do_release_fw(&dev->fw.pcm);
2074 b43_do_release_fw(&dev->fw.initvals);
2075 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2076}
2077
eb189d8b 2078static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2079{
fc68ed4f
HE		 2080 const char text[] =
2081 "You must go to " \
2082 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2083 "and download the correct firmware for this driver version. " \
2084 "Please carefully read all instructions on this website.\n";
eb189d8b 2085
eb189d8b
MB		 2086 if (error)
2087 b43err(wl, text);
2088 else
2089 b43warn(wl, text);
e4d6b795
MB		 2090}
2091
5e20a4b5
LF		 2092static void b43_fw_cb(const struct firmware *firmware, void *context)
2093{
2094 struct b43_request_fw_context *ctx = context;
2095
2096 ctx->blob = firmware;
0673effd 2097 complete(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2098}
2099
1a9f5093
MB		 2100int b43_do_request_fw(struct b43_request_fw_context *ctx,
2101 const char *name,
5e20a4b5 2102 struct b43_firmware_file *fw, bool async)
e4d6b795 2103{
e4d6b795
MB		 2104 struct b43_fw_header *hdr;
2105 u32 size;
2106 int err;
2107
61cb5dd6
MB		 2108 if (!name) {
2109 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2110 /* FIXME: We should probably keep it anyway, to save some headache
2111 * on suspend/resume with multiband devices. */
2112 b43_do_release_fw(fw);
e4d6b795 2113 return 0;
61cb5dd6
MB		 2114 }
2115 if (fw->filename) {
1a9f5093
MB		 2116 if ((fw->type == ctx->req_type) &&
2117 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2118 return 0; /* Already have this fw. */
2119 /* Free the cached firmware first. */
1a9f5093
MB		 2120 /* FIXME: We should probably do this later after we successfully
2121 * got the new fw. This could reduce headache with multiband devices.
2122 * We could also redesign this to cache the firmware for all possible
2123 * bands all the time. */
2124 b43_do_release_fw(fw);
61cb5dd6 2125 }
e4d6b795 2126
1a9f5093
MB		 2127 switch (ctx->req_type) {
2128 case B43_FWTYPE_PROPRIETARY:
2129 snprintf(ctx->fwname, sizeof(ctx->fwname),
2130 "b43%s/%s.fw",
2131 modparam_fwpostfix, name);
2132 break;
2133 case B43_FWTYPE_OPENSOURCE:
2134 snprintf(ctx->fwname, sizeof(ctx->fwname),
2135 "b43-open%s/%s.fw",
2136 modparam_fwpostfix, name);
2137 break;
2138 default:
2139 B43_WARN_ON(1);
2140 return -ENOSYS;
2141 }
5e20a4b5
LF		 2142 if (async) {
2143 /* do this part asynchronously */
0673effd 2144 init_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2145 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2146 ctx->dev->dev->dev, GFP_KERNEL,
2147 ctx, b43_fw_cb);
2148 if (err < 0) {
2149 pr_err("Unable to load firmware\n");
2150 return err;
2151 }
0673effd 2152 wait_for_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2153 if (ctx->blob)
2154 goto fw_ready;
2155 /* On some ARM systems, the async request will fail, but the next sync
0673effd 2156 * request works. For this reason, we fall through here
5e20a4b5
LF		 2157 */
2158 }
2159 err = request_firmware(&ctx->blob, ctx->fwname,
2160 ctx->dev->dev->dev);
68217832 2161 if (err == -ENOENT) {
1a9f5093
MB		 2162 snprintf(ctx->errors[ctx->req_type],
2163 sizeof(ctx->errors[ctx->req_type]),
5e20a4b5
LF		 2164 "Firmware file \"%s\" not found\n",
2165 ctx->fwname);
68217832
MB		 2166 return err;
2167 } else if (err) {
1a9f5093
MB		 2168 snprintf(ctx->errors[ctx->req_type],
2169 sizeof(ctx->errors[ctx->req_type]),
2170 "Firmware file \"%s\" request failed (err=%d)\n",
2171 ctx->fwname, err);
e4d6b795
MB		 2172 return err;
2173 }
5e20a4b5
LF		 2174fw_ready:
2175 if (ctx->blob->size < sizeof(struct b43_fw_header))
e4d6b795 2176 goto err_format;
5e20a4b5 2177 hdr = (struct b43_fw_header *)(ctx->blob->data);
e4d6b795
MB		 2178 switch (hdr->type) {
2179 case B43_FW_TYPE_UCODE:
2180 case B43_FW_TYPE_PCM:
2181 size = be32_to_cpu(hdr->size);
5e20a4b5 2182 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2183 goto err_format;
2184 /* fallthrough */
2185 case B43_FW_TYPE_IV:
2186 if (hdr->ver != 1)
2187 goto err_format;
2188 break;
2189 default:
2190 goto err_format;
2191 }
2192
5e20a4b5 2193 fw->data = ctx->blob;
61cb5dd6 2194 fw->filename = name;
1a9f5093 2195 fw->type = ctx->req_type;
61cb5dd6
MB		 2196
2197 return 0;
e4d6b795
MB		 2198
2199err_format:
1a9f5093
MB		 2200 snprintf(ctx->errors[ctx->req_type],
2201 sizeof(ctx->errors[ctx->req_type]),
2202 "Firmware file \"%s\" format error.\n", ctx->fwname);
5e20a4b5 2203 release_firmware(ctx->blob);
61cb5dd6 2204
e4d6b795
MB		 2205 return -EPROTO;
2206}
2207
a60f99f7 2208/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
1a9f5093 2209static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2210{
1a9f5093
MB		 2211 struct b43_wldev *dev = ctx->dev;
2212 struct b43_firmware *fw = &ctx->dev->fw;
a60f99f7 2213 struct b43_phy *phy = &dev->phy;
21d889d4 2214 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795 2215 const char *filename;
e4d6b795
MB		 2216 int err;
2217
61cb5dd6 2218 /* Get microcode */
a60f99f7
RM		 2219 filename = NULL;
2220 switch (rev) {
2221 case 42:
2222 if (phy->type == B43_PHYTYPE_AC)
2223 filename = "ucode42";
2224 break;
15be8e89
RM		 2225 case 40:
2226 if (phy->type == B43_PHYTYPE_AC)
2227 filename = "ucode40";
2228 break;
a60f99f7
RM		 2229 case 33:
2230 if (phy->type == B43_PHYTYPE_LCN40)
2231 filename = "ucode33_lcn40";
2232 break;
2233 case 30:
2234 if (phy->type == B43_PHYTYPE_N)
2235 filename = "ucode30_mimo";
2236 break;
2237 case 29:
2238 if (phy->type == B43_PHYTYPE_HT)
2239 filename = "ucode29_mimo";
2240 break;
2241 case 26:
2242 if (phy->type == B43_PHYTYPE_HT)
2243 filename = "ucode26_mimo";
2244 break;
2245 case 28:
2246 case 25:
2247 if (phy->type == B43_PHYTYPE_N)
2248 filename = "ucode25_mimo";
2249 else if (phy->type == B43_PHYTYPE_LCN)
2250 filename = "ucode25_lcn";
2251 break;
2252 case 24:
2253 if (phy->type == B43_PHYTYPE_LCN)
2254 filename = "ucode24_lcn";
2255 break;
2256 case 23:
2257 if (phy->type == B43_PHYTYPE_N)
2258 filename = "ucode16_mimo";
2259 break;
2260 case 16 ... 19:
2261 if (phy->type == B43_PHYTYPE_N)
2262 filename = "ucode16_mimo";
2263 else if (phy->type == B43_PHYTYPE_LP)
2264 filename = "ucode16_lp";
2265 break;
2266 case 15:
759b973b 2267 filename = "ucode15";
a60f99f7
RM		 2268 break;
2269 case 14:
2270 filename = "ucode14";
2271 break;
2272 case 13:
2273 filename = "ucode13";
2274 break;
2275 case 11 ... 12:
2276 filename = "ucode11";
2277 break;
2278 case 5 ... 10:
2279 filename = "ucode5";
2280 break;
6ff1e5cf 2281 }
a60f99f7
RM		 2282 if (!filename)
2283 goto err_no_ucode;
5e20a4b5 2284 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
61cb5dd6
MB		 2285 if (err)
2286 goto err_load;
2287
2288 /* Get PCM code */
2289 if ((rev >= 5) && (rev <= 10))
2290 filename = "pcm5";
2291 else if (rev >= 11)
2292 filename = NULL;
2293 else
2294 goto err_no_pcm;
3db1cd5c 2295 fw->pcm_request_failed = false;
5e20a4b5 2296 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
68217832
MB		 2297 if (err == -ENOENT) {
2298 /* We did not find a PCM file? Not fatal, but
2299 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2300 fw->pcm_request_failed = true;
68217832 2301 } else if (err)
61cb5dd6
MB		 2302 goto err_load;
2303
2304 /* Get initvals */
a60f99f7 2305 filename = NULL;
61cb5dd6 2306 switch (dev->phy.type) {
61cb5dd6 2307 case B43_PHYTYPE_G:
a60f99f7 2308 if (rev == 13)
e9304882 2309 filename = "b0g0initvals13";
a60f99f7
RM		 2310 else if (rev >= 5 && rev <= 10)
2311 filename = "b0g0initvals5";
61cb5dd6
MB		 2312 break;
2313 case B43_PHYTYPE_N:
a60f99f7
RM		 2314 if (rev == 30)
2315 filename = "n16initvals30";
2316 else if (rev == 28 || rev == 25)
2317 filename = "n0initvals25";
2318 else if (rev == 24)
2319 filename = "n0initvals24";
2320 else if (rev == 23)
2321 filename = "n0initvals16"; /* What about n0initvals22? */
2322 else if (rev >= 16 && rev <= 18)
e41596a1 2323 filename = "n0initvals16";
a60f99f7 2324 else if (rev >= 11 && rev <= 12)
61cb5dd6 2325 filename = "n0initvals11";
61cb5dd6 2326 break;
759b973b 2327 case B43_PHYTYPE_LP:
a60f99f7
RM		 2328 if (rev >= 16 && rev <= 18)
2329 filename = "lp0initvals16";
2330 else if (rev == 15)
2331 filename = "lp0initvals15";
759b973b
GS		 2332 else if (rev == 14)
2333 filename = "lp0initvals14";
a60f99f7
RM		 2334 else if (rev == 13)
2335 filename = "lp0initvals13";
759b973b 2336 break;
8b9bda75
RM		 2337 case B43_PHYTYPE_HT:
2338 if (rev == 29)
2339 filename = "ht0initvals29";
a60f99f7
RM		 2340 else if (rev == 26)
2341 filename = "ht0initvals26";
8b9bda75
RM		 2342 break;
2343 case B43_PHYTYPE_LCN:
2344 if (rev == 24)
2345 filename = "lcn0initvals24";
8b9bda75 2346 break;
a60f99f7
RM		 2347 case B43_PHYTYPE_LCN40:
2348 if (rev == 33)
2349 filename = "lcn400initvals33";
2350 break;
2351 case B43_PHYTYPE_AC:
2352 if (rev == 42)
2353 filename = "ac1initvals42";
15be8e89
RM		 2354 else if (rev == 40)
2355 filename = "ac0initvals40";
a60f99f7 2356 break;
e4d6b795 2357 }
a60f99f7
RM		 2358 if (!filename)
2359 goto err_no_initvals;
5e20a4b5 2360 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
61cb5dd6
MB		 2361 if (err)
2362 goto err_load;
2363
2364 /* Get bandswitch initvals */
a60f99f7 2365 filename = NULL;
61cb5dd6 2366 switch (dev->phy.type) {
61cb5dd6 2367 case B43_PHYTYPE_G:
a60f99f7
RM		 2368 if (rev == 13)
2369 filename = "b0g0bsinitvals13";
2370 else if (rev >= 5 && rev <= 10)
61cb5dd6 2371 filename = "b0g0bsinitvals5";
61cb5dd6
MB		 2372 break;
2373 case B43_PHYTYPE_N:
a60f99f7
RM		 2374 if (rev == 30)
2375 filename = "n16bsinitvals30";
2376 else if (rev == 28 || rev == 25)
2377 filename = "n0bsinitvals25";
2378 else if (rev == 24)
2379 filename = "n0bsinitvals24";
2380 else if (rev == 23)
2381 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2382 else if (rev >= 16 && rev <= 18)
e41596a1 2383 filename = "n0bsinitvals16";
a60f99f7 2384 else if (rev >= 11 && rev <= 12)
61cb5dd6 2385 filename = "n0bsinitvals11";
61cb5dd6 2386 break;
759b973b 2387 case B43_PHYTYPE_LP:
a60f99f7
RM		 2388 if (rev >= 16 && rev <= 18)
2389 filename = "lp0bsinitvals16";
2390 else if (rev == 15)
2391 filename = "lp0bsinitvals15";
759b973b
GS		 2392 else if (rev == 14)
2393 filename = "lp0bsinitvals14";
a60f99f7
RM		 2394 else if (rev == 13)
2395 filename = "lp0bsinitvals13";
759b973b 2396 break;
8b9bda75
RM		 2397 case B43_PHYTYPE_HT:
2398 if (rev == 29)
2399 filename = "ht0bsinitvals29";
a60f99f7
RM		 2400 else if (rev == 26)
2401 filename = "ht0bsinitvals26";
8b9bda75
RM		 2402 break;
2403 case B43_PHYTYPE_LCN:
2404 if (rev == 24)
2405 filename = "lcn0bsinitvals24";
8b9bda75 2406 break;
a60f99f7
RM		 2407 case B43_PHYTYPE_LCN40:
2408 if (rev == 33)
2409 filename = "lcn400bsinitvals33";
2410 break;
2411 case B43_PHYTYPE_AC:
2412 if (rev == 42)
2413 filename = "ac1bsinitvals42";
15be8e89
RM		 2414 else if (rev == 40)
2415 filename = "ac0bsinitvals40";
a60f99f7 2416 break;
e4d6b795 2417 }
a60f99f7
RM		 2418 if (!filename)
2419 goto err_no_initvals;
5e20a4b5 2420 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
61cb5dd6
MB		 2421 if (err)
2422 goto err_load;
e4d6b795 2423
097b0e1b
JB		 2424 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2425
e4d6b795
MB		 2426 return 0;
2427
e4d6b795 2428err_no_ucode:
1a9f5093
MB		 2429 err = ctx->fatal_failure = -EOPNOTSUPP;
2430 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2431 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2432 goto error;
2433
2434err_no_pcm:
1a9f5093
MB		 2435 err = ctx->fatal_failure = -EOPNOTSUPP;
2436 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2437 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2438 goto error;
2439
2440err_no_initvals:
1a9f5093
MB		 2441 err = ctx->fatal_failure = -EOPNOTSUPP;
2442 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2443 "is required for your device (wl-core rev %u)\n", rev);
2444 goto error;
2445
2446err_load:
2447 /* We failed to load this firmware image. The error message
2448 * already is in ctx->errors. Return and let our caller decide
2449 * what to do. */
e4d6b795
MB		 2450 goto error;
2451
2452error:
2453 b43_release_firmware(dev);
2454 return err;
2455}
2456
6b6fa586
LF		 2457static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2458static void b43_one_core_detach(struct b43_bus_dev *dev);
09164043 2459static int b43_rng_init(struct b43_wl *wl);
6b6fa586
LF		 2460
2461static void b43_request_firmware(struct work_struct *work)
1a9f5093 2462{
6b6fa586
LF		 2463 struct b43_wl *wl = container_of(work,
2464 struct b43_wl, firmware_load);
2465 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2466 struct b43_request_fw_context *ctx;
2467 unsigned int i;
2468 int err;
2469 const char *errmsg;
2470
2471 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2472 if (!ctx)
6b6fa586 2473 return;
1a9f5093
MB		 2474 ctx->dev = dev;
2475
2476 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2477 err = b43_try_request_fw(ctx);
2478 if (!err)
6b6fa586
LF		 2479 goto start_ieee80211; /* Successfully loaded it. */
2480 /* Was fw version known? */
2481 if (ctx->fatal_failure)
1a9f5093
MB		 2482 goto out;
2483
6b6fa586 2484 /* proprietary fw not found, try open source */
1a9f5093
MB		 2485 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2486 err = b43_try_request_fw(ctx);
2487 if (!err)
6b6fa586
LF		 2488 goto start_ieee80211; /* Successfully loaded it. */
2489 if(ctx->fatal_failure)
1a9f5093
MB		 2490 goto out;
2491
2492 /* Could not find a usable firmware. Print the errors. */
2493 for (i = 0; i < B43_NR_FWTYPES; i++) {
2494 errmsg = ctx->errors[i];
2495 if (strlen(errmsg))
e0e29b68 2496 b43err(dev->wl, "%s", errmsg);
1a9f5093
MB		 2497 }
2498 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2499 goto out;
2500
2501start_ieee80211:
097b0e1b
JB		 2502 wl->hw->queues = B43_QOS_QUEUE_NUM;
2503 if (!modparam_qos || dev->fw.opensource)
2504 wl->hw->queues = 1;
2505
6b6fa586
LF		 2506 err = ieee80211_register_hw(wl->hw);
2507 if (err)
2508 goto err_one_core_detach;
e64add27 2509 wl->hw_registred = true;
6b6fa586 2510 b43_leds_register(wl->current_dev);
09164043
LF		 2511
2512 /* Register HW RNG driver */
2513 b43_rng_init(wl);
2514
6b6fa586
LF		 2515 goto out;
2516
2517err_one_core_detach:
2518 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2519
2520out:
2521 kfree(ctx);
1a9f5093
MB		 2522}
2523
e4d6b795
MB		 2524static int b43_upload_microcode(struct b43_wldev *dev)
2525{
652caa5b 2526 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2527 const size_t hdr_len = sizeof(struct b43_fw_header);
2528 const __be32 *data;
2529 unsigned int i, len;
2530 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2531 u32 tmp, macctl;
e4d6b795
MB		 2532 int err = 0;
2533
1f7d87b0
MB		 2534 /* Jump the microcode PSM to offset 0 */
2535 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2536 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2537 macctl |= B43_MACCTL_PSM_JMP0;
2538 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2539 /* Zero out all microcode PSM registers and shared memory. */
2540 for (i = 0; i < 64; i++)
2541 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2542 for (i = 0; i < 4096; i += 2)
2543 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2544
e4d6b795 2545 /* Upload Microcode. */
61cb5dd6
MB		 2546 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2547 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2548 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2549 for (i = 0; i < len; i++) {
2550 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2551 udelay(10);
2552 }
2553
61cb5dd6 2554 if (dev->fw.pcm.data) {
e4d6b795 2555 /* Upload PCM data. */
61cb5dd6
MB		 2556 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2557 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2558 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2559 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2560 /* No need for autoinc bit in SHM_HW */
2561 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2562 for (i = 0; i < len; i++) {
2563 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2564 udelay(10);
2565 }
2566 }
2567
2568 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2569
2570 /* Start the microcode PSM */
5056635c
RM		 2571 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2572 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2573
2574 /* Wait for the microcode to load and respond */
2575 i = 0;
2576 while (1) {
2577 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2578 if (tmp == B43_IRQ_MAC_SUSPENDED)
2579 break;
2580 i++;
1f7d87b0 2581 if (i >= 20) {
e4d6b795 2582 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2583 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2584 err = -ENODEV;
1f7d87b0
MB		 2585 goto error;
2586 }
e175e996 2587 msleep(50);
e4d6b795
MB		 2588 }
2589 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2590
2591 /* Get and check the revisions. */
2592 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2593 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2594 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2595 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2596
2597 if (fwrev <= 0x128) {
2598 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2599 "binary drivers older than version 4.x is unsupported. "
2600 "You must upgrade your firmware files.\n");
eb189d8b 2601 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2602 err = -EOPNOTSUPP;
1f7d87b0 2603 goto error;
e4d6b795 2604 }
e4d6b795
MB		 2605 dev->fw.rev = fwrev;
2606 dev->fw.patch = fwpatch;
5d852905
RM		 2607 if (dev->fw.rev >= 598)
2608 dev->fw.hdr_format = B43_FW_HDR_598;
2609 else if (dev->fw.rev >= 410)
efe0249b
RM		 2610 dev->fw.hdr_format = B43_FW_HDR_410;
2611 else
2612 dev->fw.hdr_format = B43_FW_HDR_351;
097b0e1b 2613 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
e48b0eeb 2614
097b0e1b 2615 dev->qos_enabled = dev->wl->hw->queues > 1;
403a3a13 2616 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2617 dev->hwcrypto_enabled = true;
403a3a13 2618
e48b0eeb 2619 if (dev->fw.opensource) {
403a3a13
MB		 2620 u16 fwcapa;
2621
e48b0eeb
MB		 2622 /* Patchlevel info is encoded in the "time" field. */
2623 dev->fw.patch = fwtime;
403a3a13
MB		 2624 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2625 dev->fw.rev, dev->fw.patch);
2626
2627 fwcapa = b43_fwcapa_read(dev);
2628 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2629 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2630 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2631 dev->hwcrypto_enabled = false;
403a3a13 2632 }
097b0e1b
JB		 2633 /* adding QoS support should use an offline discovery mechanism */
2634 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
e48b0eeb
MB		 2635 } else {
2636 b43info(dev->wl, "Loading firmware version %u.%u "
2637 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2638 fwrev, fwpatch,
2639 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2640 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2641 if (dev->fw.pcm_request_failed) {
2642 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2643 "Hardware accelerated cryptography is disabled.\n");
2644 b43_print_fw_helptext(dev->wl, 0);
2645 }
e48b0eeb 2646 }
e4d6b795 2647
652caa5b
JL		 2648 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2649 dev->fw.rev, dev->fw.patch);
21d889d4 2650 wiphy->hw_version = dev->dev->core_id;
652caa5b 2651
efe0249b 2652 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2653 /* We're over the deadline, but we keep support for old fw
2654 * until it turns out to be in major conflict with something new. */
eb189d8b 2655 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2656 "Support for old firmware will be removed soon "
2657 "(official deadline was July 2008).\n");
eb189d8b
MB		 2658 b43_print_fw_helptext(dev->wl, 0);
2659 }
2660
1f7d87b0
MB		 2661 return 0;
2662
2663error:
5056635c
RM		 2664 /* Stop the microcode PSM. */
2665 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2666 B43_MACCTL_PSM_JMP0);
1f7d87b0 2667
e4d6b795
MB		 2668 return err;
2669}
2670
2671static int b43_write_initvals(struct b43_wldev *dev,
2672 const struct b43_iv *ivals,
2673 size_t count,
2674 size_t array_size)
2675{
2676 const struct b43_iv *iv;
2677 u16 offset;
2678 size_t i;
2679 bool bit32;
2680
2681 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2682 iv = ivals;
2683 for (i = 0; i < count; i++) {
2684 if (array_size < sizeof(iv->offset_size))
2685 goto err_format;
2686 array_size -= sizeof(iv->offset_size);
2687 offset = be16_to_cpu(iv->offset_size);
2688 bit32 = !!(offset & B43_IV_32BIT);
2689 offset &= B43_IV_OFFSET_MASK;
2690 if (offset >= 0x1000)
2691 goto err_format;
2692 if (bit32) {
2693 u32 value;
2694
2695 if (array_size < sizeof(iv->data.d32))
2696 goto err_format;
2697 array_size -= sizeof(iv->data.d32);
2698
533dd1b0 2699 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2700 b43_write32(dev, offset, value);
2701
2702 iv = (const struct b43_iv *)((const uint8_t *)iv +
2703 sizeof(__be16) +
2704 sizeof(__be32));
2705 } else {
2706 u16 value;
2707
2708 if (array_size < sizeof(iv->data.d16))
2709 goto err_format;
2710 array_size -= sizeof(iv->data.d16);
2711
2712 value = be16_to_cpu(iv->data.d16);
2713 b43_write16(dev, offset, value);
2714
2715 iv = (const struct b43_iv *)((const uint8_t *)iv +
2716 sizeof(__be16) +
2717 sizeof(__be16));
2718 }
2719 }
2720 if (array_size)
2721 goto err_format;
2722
2723 return 0;
2724
2725err_format:
2726 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2727 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2728
2729 return -EPROTO;
2730}
2731
2732static int b43_upload_initvals(struct b43_wldev *dev)
2733{
2734 const size_t hdr_len = sizeof(struct b43_fw_header);
2735 const struct b43_fw_header *hdr;
2736 struct b43_firmware *fw = &dev->fw;
2737 const struct b43_iv *ivals;
2738 size_t count;
e4d6b795 2739
61cb5dd6
MB		 2740 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2741 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795 2742 count = be32_to_cpu(hdr->size);
0f68423f 2743 return b43_write_initvals(dev, ivals, count,
61cb5dd6 2744 fw->initvals.data->size - hdr_len);
0f68423f 2745}
e4d6b795 2746
0f68423f
RM		 2747static int b43_upload_initvals_band(struct b43_wldev *dev)
2748{
2749 const size_t hdr_len = sizeof(struct b43_fw_header);
2750 const struct b43_fw_header *hdr;
2751 struct b43_firmware *fw = &dev->fw;
2752 const struct b43_iv *ivals;
2753 size_t count;
2754
2755 if (!fw->initvals_band.data)
2756 return 0;
2757
2758 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2759 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2760 count = be32_to_cpu(hdr->size);
2761 return b43_write_initvals(dev, ivals, count,
2762 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2763}
2764
2765/* Initialize the GPIOs
2766 * http://bcm-specs.sipsolutions.net/GPIO
2767 */
bd7c8a59
RM		 2768
2769#ifdef CONFIG_B43_SSB
c4a2a081 2770static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2771{
d48ae5c8 2772 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2773
2774#ifdef CONFIG_SSB_DRIVER_PCICORE
2775 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2776#else
2777 return bus->chipco.dev;
2778#endif
2779}
bd7c8a59 2780#endif
c4a2a081 2781
e4d6b795
MB		 2782static int b43_gpio_init(struct b43_wldev *dev)
2783{
bd7c8a59 2784#ifdef CONFIG_B43_SSB
c4a2a081 2785 struct ssb_device *gpiodev;
bd7c8a59 2786#endif
e4d6b795
MB		 2787 u32 mask, set;
2788
5056635c
RM		 2789 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2790 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2791
2792 mask = 0x0000001F;
2793 set = 0x0000000F;
c244e08c 2794 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2795 mask |= 0x0060;
2796 set |= 0x0060;
828afd26
RM		 2797 } else if (dev->dev->chip_id == 0x5354) {
2798 /* Don't allow overtaking buttons GPIOs */
2799 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
e4d6b795 2800 }
828afd26 2801
e4d6b795
MB		 2802 if (0 /* FIXME: conditional unknown */ ) {
2803 b43_write16(dev, B43_MMIO_GPIO_MASK,
2804 b43_read16(dev, B43_MMIO_GPIO_MASK)
2805 | 0x0100);
828afd26
RM		 2806 /* BT Coexistance Input */
2807 mask |= 0x0080;
2808 set |= 0x0080;
2809 /* BT Coexistance Out */
2810 mask |= 0x0100;
2811 set |= 0x0100;
e4d6b795 2812 }
0581483a 2813 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
828afd26 2814 /* PA is controlled by gpio 9, let ucode handle it */
e4d6b795
MB		 2815 b43_write16(dev, B43_MMIO_GPIO_MASK,
2816 b43_read16(dev, B43_MMIO_GPIO_MASK)
2817 | 0x0200);
2818 mask |= 0x0200;
2819 set |= 0x0200;
2820 }
e4d6b795 2821
6cbab0d9 2822 switch (dev->dev->bus_type) {
42c9a458
RM		 2823#ifdef CONFIG_B43_BCMA
2824 case B43_BUS_BCMA:
0a64baea 2825 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
42c9a458
RM		 2826 break;
2827#endif
6cbab0d9
RM		 2828#ifdef CONFIG_B43_SSB
2829 case B43_BUS_SSB:
2830 gpiodev = b43_ssb_gpio_dev(dev);
2831 if (gpiodev)
2832 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2833 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
828afd26 2834 & ~mask) | set);
6cbab0d9
RM		 2835 break;
2836#endif
2837 }
e4d6b795
MB		 2838
2839 return 0;
2840}
2841
2842/* Turn off all GPIO stuff. Call this on module unload, for example. */
2843static void b43_gpio_cleanup(struct b43_wldev *dev)
2844{
bd7c8a59 2845#ifdef CONFIG_B43_SSB
c4a2a081 2846 struct ssb_device *gpiodev;
bd7c8a59 2847#endif
e4d6b795 2848
6cbab0d9 2849 switch (dev->dev->bus_type) {
42c9a458
RM		 2850#ifdef CONFIG_B43_BCMA
2851 case B43_BUS_BCMA:
0a64baea 2852 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
42c9a458
RM		 2853 break;
2854#endif
6cbab0d9
RM		 2855#ifdef CONFIG_B43_SSB
2856 case B43_BUS_SSB:
2857 gpiodev = b43_ssb_gpio_dev(dev);
2858 if (gpiodev)
2859 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2860 break;
2861#endif
2862 }
e4d6b795
MB		 2863}
2864
2865/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2866void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2867{
923fd703
MB		 2868 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2869 u16 fwstate;
2870
2871 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2872 B43_SHM_SH_UCODESTAT);
2873 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2874 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2875 b43err(dev->wl, "b43_mac_enable(): The firmware "
2876 "should be suspended, but current state is %u\n",
2877 fwstate);
2878 }
2879 }
2880
e4d6b795
MB		 2881 dev->mac_suspended--;
2882 B43_WARN_ON(dev->mac_suspended < 0);
2883 if (dev->mac_suspended == 0) {
5056635c 2884 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2885 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2886 B43_IRQ_MAC_SUSPENDED);
2887 /* Commit writes */
2888 b43_read32(dev, B43_MMIO_MACCTL);
2889 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2890 b43_power_saving_ctl_bits(dev, 0);
2891 }
2892}
2893
2894/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2895void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2896{
2897 int i;
2898 u32 tmp;
2899
05b64b36 2900 might_sleep();
e4d6b795 2901 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2902
e4d6b795
MB		 2903 if (dev->mac_suspended == 0) {
2904 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2905 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2906 /* force pci to flush the write */
2907 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2908 for (i = 35; i; i--) {
2909 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2910 if (tmp & B43_IRQ_MAC_SUSPENDED)
2911 goto out;
2912 udelay(10);
2913 }
2914 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2915 for (i = 40; i; i--) {
e4d6b795
MB		 2916 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2917 if (tmp & B43_IRQ_MAC_SUSPENDED)
2918 goto out;
05b64b36 2919 msleep(1);
e4d6b795
MB		 2920 }
2921 b43err(dev->wl, "MAC suspend failed\n");
2922 }
05b64b36 2923out:
e4d6b795
MB		 2924 dev->mac_suspended++;
2925}
2926
858a1652
RM		 2927/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2928void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2929{
6cbab0d9
RM		 2930 u32 tmp;
2931
2932 switch (dev->dev->bus_type) {
42c9a458
RM		 2933#ifdef CONFIG_B43_BCMA
2934 case B43_BUS_BCMA:
36677874 2935 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2936 if (on)
2937 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2938 else
2939 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2940 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2941 break;
2942#endif
6cbab0d9
RM		 2943#ifdef CONFIG_B43_SSB
2944 case B43_BUS_SSB:
2945 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2946 if (on)
2947 tmp |= B43_TMSLOW_MACPHYCLKEN;
2948 else
2949 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2950 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2951 break;
2952#endif
2953 }
858a1652
RM		 2954}
2955
e4d6b795
MB		 2956static void b43_adjust_opmode(struct b43_wldev *dev)
2957{
2958 struct b43_wl *wl = dev->wl;
2959 u32 ctl;
2960 u16 cfp_pretbtt;
2961
2962 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2963 /* Reset status to STA infrastructure mode. */
2964 ctl &= ~B43_MACCTL_AP;
2965 ctl &= ~B43_MACCTL_KEEP_CTL;
2966 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2967 ctl &= ~B43_MACCTL_KEEP_BAD;
2968 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2969 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2970 ctl |= B43_MACCTL_INFRA;
2971
05c914fe
JB		 2972 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2973 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2974 ctl |= B43_MACCTL_AP;
05c914fe 2975 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2976 ctl &= ~B43_MACCTL_INFRA;
2977
2978 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2979 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2980 if (wl->filter_flags & FIF_FCSFAIL)
2981 ctl |= B43_MACCTL_KEEP_BAD;
2982 if (wl->filter_flags & FIF_PLCPFAIL)
2983 ctl |= B43_MACCTL_KEEP_BADPLCP;
2984 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2985 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2986 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2987 ctl |= B43_MACCTL_BEACPROMISC;
2988
e4d6b795
MB		 2989 /* Workaround: On old hardware the HW-MAC-address-filter
2990 * doesn't work properly, so always run promisc in filter
2991 * it in software. */
21d889d4 2992 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2993 ctl |= B43_MACCTL_PROMISC;
2994
2995 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2996
2997 cfp_pretbtt = 2;
2998 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2999 if (dev->dev->chip_id == 0x4306 &&
3000 dev->dev->chip_rev == 3)
e4d6b795
MB		 3001 cfp_pretbtt = 100;
3002 else
3003 cfp_pretbtt = 50;
3004 }
3005 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 3006
3007 /* FIXME: We don't currently implement the PMQ mechanism,
3008 * so always disable it. If we want to implement PMQ,
3009 * we need to enable it here (clear DISCPMQ) in AP mode.
3010 */
5056635c
RM		 3011 if (0 /* ctl & B43_MACCTL_AP */)
3012 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3013 else
3014 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 3015}
3016
3017static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3018{
3019 u16 offset;
3020
3021 if (is_ofdm) {
3022 offset = 0x480;
3023 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3024 } else {
3025 offset = 0x4C0;
3026 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3027 }
3028 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3029 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3030}
3031
3032static void b43_rate_memory_init(struct b43_wldev *dev)
3033{
3034 switch (dev->phy.type) {
3035 case B43_PHYTYPE_A:
3036 case B43_PHYTYPE_G:
53a6e234 3037 case B43_PHYTYPE_N:
9d86a2d5 3038 case B43_PHYTYPE_LP:
6a461c23 3039 case B43_PHYTYPE_HT:
0b4ff45d 3040 case B43_PHYTYPE_LCN:
e4d6b795
MB		 3041 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3042 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3043 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3044 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3045 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3046 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3047 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3048 if (dev->phy.type == B43_PHYTYPE_A)
3049 break;
3050 /* fallthrough */
3051 case B43_PHYTYPE_B:
3052 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3053 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3054 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3055 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3056 break;
3057 default:
3058 B43_WARN_ON(1);
3059 }
3060}
3061
5042c507
MB		 3062/* Set the default values for the PHY TX Control Words. */
3063static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3064{
3065 u16 ctl = 0;
3066
3067 ctl |= B43_TXH_PHY_ENC_CCK;
3068 ctl |= B43_TXH_PHY_ANT01AUTO;
3069 ctl |= B43_TXH_PHY_TXPWR;
3070
3071 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3072 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3073 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3074}
3075
e4d6b795
MB		 3076/* Set the TX-Antenna for management frames sent by firmware. */
3077static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3078{
5042c507 3079 u16 ant;
e4d6b795
MB		 3080 u16 tmp;
3081
5042c507 3082 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3083
e4d6b795
MB		 3084 /* For ACK/CTS */
3085 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3086 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3087 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3088 /* For Probe Resposes */
3089 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3090 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3091 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3092}
3093
3094/* This is the opposite of b43_chip_init() */
3095static void b43_chip_exit(struct b43_wldev *dev)
3096{
fb11137a 3097 b43_phy_exit(dev);
e4d6b795
MB		 3098 b43_gpio_cleanup(dev);
3099 /* firmware is released later */
3100}
3101
3102/* Initialize the chip
3103 * http://bcm-specs.sipsolutions.net/ChipInit
3104 */
3105static int b43_chip_init(struct b43_wldev *dev)
3106{
3107 struct b43_phy *phy = &dev->phy;
ef1a628d 3108 int err;
858a1652 3109 u32 macctl;
e4d6b795
MB		 3110 u16 value16;
3111
1f7d87b0
MB		 3112 /* Initialize the MAC control */
3113 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3114 if (dev->phy.gmode)
3115 macctl |= B43_MACCTL_GMODE;
3116 macctl |= B43_MACCTL_INFRA;
3117 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3118
e4d6b795
MB		 3119 err = b43_upload_microcode(dev);
3120 if (err)
3121 goto out; /* firmware is released later */
3122
3123 err = b43_gpio_init(dev);
3124 if (err)
3125 goto out; /* firmware is released later */
21954c36 3126
e4d6b795
MB		 3127 err = b43_upload_initvals(dev);
3128 if (err)
1a8d1227 3129 goto err_gpio_clean;
e4d6b795 3130
0f68423f
RM		 3131 err = b43_upload_initvals_band(dev);
3132 if (err)
3133 goto err_gpio_clean;
3134
0b7dcd96
MB		 3135 /* Turn the Analog on and initialize the PHY. */
3136 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3137 err = b43_phy_init(dev);
3138 if (err)
ef1a628d 3139 goto err_gpio_clean;
e4d6b795 3140
ef1a628d
MB		 3141 /* Disable Interference Mitigation. */
3142 if (phy->ops->interf_mitigation)
3143 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3144
ef1a628d
MB		 3145 /* Select the antennae */
3146 if (phy->ops->set_rx_antenna)
3147 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3148 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3149
3150 if (phy->type == B43_PHYTYPE_B) {
3151 value16 = b43_read16(dev, 0x005E);
3152 value16 |= 0x0004;
3153 b43_write16(dev, 0x005E, value16);
3154 }
3155 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3156 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3157 b43_write32(dev, 0x010C, 0x01000000);
3158
5056635c
RM		 3159 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3160 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3161
e4d6b795
MB		 3162 /* Probe Response Timeout value */
3163 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
5c1da23b 3164 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
e4d6b795
MB		 3165
3166 /* Initially set the wireless operation mode. */
3167 b43_adjust_opmode(dev);
3168
21d889d4 3169 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3170 b43_write16(dev, 0x060E, 0x0000);
3171 b43_write16(dev, 0x0610, 0x8000);
3172 b43_write16(dev, 0x0604, 0x0000);
3173 b43_write16(dev, 0x0606, 0x0200);
3174 } else {
3175 b43_write32(dev, 0x0188, 0x80000000);
3176 b43_write32(dev, 0x018C, 0x02000000);
3177 }
3178 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
73b82bf0 3179 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
e4d6b795
MB		 3180 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3181 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3182 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3183 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3184 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3185
858a1652 3186 b43_mac_phy_clock_set(dev, true);
e4d6b795 3187
6cbab0d9 3188 switch (dev->dev->bus_type) {
42c9a458
RM		 3189#ifdef CONFIG_B43_BCMA
3190 case B43_BUS_BCMA:
3191 /* FIXME: 0xE74 is quite common, but should be read from CC */
3192 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3193 break;
3194#endif
6cbab0d9
RM		 3195#ifdef CONFIG_B43_SSB
3196 case B43_BUS_SSB:
3197 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3198 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3199 break;
3200#endif
3201 }
e4d6b795
MB		 3202
3203 err = 0;
3204 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3205out:
e4d6b795
MB		 3206 return err;
3207
1a8d1227 3208err_gpio_clean:
e4d6b795 3209 b43_gpio_cleanup(dev);
21954c36 3210 return err;
e4d6b795
MB		 3211}
3212
e4d6b795
MB		 3213static void b43_periodic_every60sec(struct b43_wldev *dev)
3214{
ef1a628d 3215 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3216
ef1a628d
MB		 3217 if (ops->pwork_60sec)
3218 ops->pwork_60sec(dev);
18c8adeb
MB		 3219
3220 /* Force check the TX power emission now. */
3221 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3222}
3223
3224static void b43_periodic_every30sec(struct b43_wldev *dev)
3225{
3226 /* Update device statistics. */
3227 b43_calculate_link_quality(dev);
3228}
3229
3230static void b43_periodic_every15sec(struct b43_wldev *dev)
3231{
3232 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3233 u16 wdr;
3234
3235 if (dev->fw.opensource) {
3236 /* Check if the firmware is still alive.
3237 * It will reset the watchdog counter to 0 in its idle loop. */
3238 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3239 if (unlikely(wdr)) {
3240 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3241 b43_controller_restart(dev, "Firmware watchdog");
3242 return;
3243 } else {
3244 b43_shm_write16(dev, B43_SHM_SCRATCH,
3245 B43_WATCHDOG_REG, 1);
3246 }
3247 }
e4d6b795 3248
ef1a628d
MB		 3249 if (phy->ops->pwork_15sec)
3250 phy->ops->pwork_15sec(dev);
3251
00e0b8cb
SB		 3252 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3253 wmb();
990b86f4
MB		 3254
3255#if B43_DEBUG
3256 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3257 unsigned int i;
3258
3259 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3260 dev->irq_count / 15,
3261 dev->tx_count / 15,
3262 dev->rx_count / 15);
3263 dev->irq_count = 0;
3264 dev->tx_count = 0;
3265 dev->rx_count = 0;
3266 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3267 if (dev->irq_bit_count[i]) {
3268 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3269 dev->irq_bit_count[i] / 15, i, (1 << i));
3270 dev->irq_bit_count[i] = 0;
3271 }
3272 }
3273 }
3274#endif
e4d6b795
MB		 3275}
3276
e4d6b795
MB		 3277static void do_periodic_work(struct b43_wldev *dev)
3278{
3279 unsigned int state;
3280
3281 state = dev->periodic_state;
42bb4cd5 3282 if (state % 4 == 0)
e4d6b795 3283 b43_periodic_every60sec(dev);
42bb4cd5 3284 if (state % 2 == 0)
e4d6b795 3285 b43_periodic_every30sec(dev);
42bb4cd5 3286 b43_periodic_every15sec(dev);
e4d6b795
MB		 3287}
3288
05b64b36
MB		 3289/* Periodic work locking policy:
3290 * The whole periodic work handler is protected by
3291 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3292 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3293 */
e4d6b795
MB		 3294static void b43_periodic_work_handler(struct work_struct *work)
3295{
05b64b36
MB		 3296 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3297 periodic_work.work);
3298 struct b43_wl *wl = dev->wl;
3299 unsigned long delay;
e4d6b795 3300
05b64b36 3301 mutex_lock(&wl->mutex);
e4d6b795
MB		 3302
3303 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3304 goto out;
3305 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3306 goto out_requeue;
3307
05b64b36 3308 do_periodic_work(dev);
e4d6b795 3309
e4d6b795 3310 dev->periodic_state++;
42bb4cd5 3311out_requeue:
e4d6b795
MB		 3312 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3313 delay = msecs_to_jiffies(50);
3314 else
82cd682d 3315 delay = round_jiffies_relative(HZ * 15);
42935eca 3316 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3317out:
05b64b36 3318 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3319}
3320
3321static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3322{
3323 struct delayed_work *work = &dev->periodic_work;
3324
3325 dev->periodic_state = 0;
3326 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3327 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3328}
3329
f3dd3fcc 3330/* Check if communication with the device works correctly. */
e4d6b795
MB		 3331static int b43_validate_chipaccess(struct b43_wldev *dev)
3332{
f62ae6cd 3333 u32 v, backup0, backup4;
e4d6b795 3334
f62ae6cd
MB		 3335 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3336 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3337
3338 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3339 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3340 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3341 goto error;
f3dd3fcc
MB		 3342 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3343 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3344 goto error;
3345
f62ae6cd
MB		 3346 /* Check if unaligned 32bit SHM_SHARED access works properly.
3347 * However, don't bail out on failure, because it's noncritical. */
3348 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3349 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3350 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3351 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3352 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3353 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3354 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3355 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3356 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3357 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3358 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3359 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3360
3361 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3362 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3363
21d889d4 3364 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3365 /* The 32bit register shadows the two 16bit registers
3366 * with update sideeffects. Validate this. */
3367 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3368 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3369 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3370 goto error;
3371 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3372 goto error;
3373 }
3374 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3375
3376 v = b43_read32(dev, B43_MMIO_MACCTL);
3377 v |= B43_MACCTL_GMODE;
3378 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3379 goto error;
3380
3381 return 0;
f3dd3fcc 3382error:
e4d6b795
MB		 3383 b43err(dev->wl, "Failed to validate the chipaccess\n");
3384 return -ENODEV;
3385}
3386
3387static void b43_security_init(struct b43_wldev *dev)
3388{
e4d6b795
MB		 3389 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3390 /* KTP is a word address, but we address SHM bytewise.
3391 * So multiply by two.
3392 */
3393 dev->ktp *= 2;
66d2d089
MB		 3394 /* Number of RCMTA address slots */
3395 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3396 /* Clear the key memory. */
e4d6b795
MB		 3397 b43_clear_keys(dev);
3398}
3399
616de35d 3400#ifdef CONFIG_B43_HWRNG
99da185a 3401static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3402{
3403 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3404 struct b43_wldev *dev;
3405 int count = -ENODEV;
e4d6b795 3406
a78b3bb2
MB		 3407 mutex_lock(&wl->mutex);
3408 dev = wl->current_dev;
3409 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3410 *data = b43_read16(dev, B43_MMIO_RNG);
3411 count = sizeof(u16);
3412 }
3413 mutex_unlock(&wl->mutex);
e4d6b795 3414
a78b3bb2 3415 return count;
e4d6b795 3416}
616de35d 3417#endif /* CONFIG_B43_HWRNG */
e4d6b795 3418
b844eba2 3419static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3420{
616de35d 3421#ifdef CONFIG_B43_HWRNG
e4d6b795 3422 if (wl->rng_initialized)
b844eba2 3423 hwrng_unregister(&wl->rng);
616de35d 3424#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3425}
3426
3427static int b43_rng_init(struct b43_wl *wl)
3428{
616de35d 3429 int err = 0;
e4d6b795 3430
616de35d 3431#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3432 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3433 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3434 wl->rng.name = wl->rng_name;
3435 wl->rng.data_read = b43_rng_read;
3436 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3437 wl->rng_initialized = true;
e4d6b795
MB		 3438 err = hwrng_register(&wl->rng);
3439 if (err) {
3db1cd5c 3440 wl->rng_initialized = false;
e4d6b795
MB		 3441 b43err(wl, "Failed to register the random "
3442 "number generator (%d)\n", err);
3443 }
616de35d 3444#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3445
3446 return err;
3447}
3448
f5d40eed 3449static void b43_tx_work(struct work_struct *work)
e4d6b795 3450{
f5d40eed
MB		 3451 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3452 struct b43_wldev *dev;
3453 struct sk_buff *skb;
bad69194 3454 int queue_num;
f5d40eed 3455 int err = 0;
e4d6b795 3456
f5d40eed
MB		 3457 mutex_lock(&wl->mutex);
3458 dev = wl->current_dev;
3459 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3460 mutex_unlock(&wl->mutex);
3461 return;
5100d5ac 3462 }
21a75d77 3463
bad69194 3464 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3465 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3466 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3467 if (b43_using_pio_transfers(dev))
3468 err = b43_pio_tx(dev, skb);
3469 else
3470 err = b43_dma_tx(dev, skb);
3471 if (err == -ENOSPC) {
3472 wl->tx_queue_stopped[queue_num] = 1;
3473 ieee80211_stop_queue(wl->hw, queue_num);
3474 skb_queue_head(&wl->tx_queue[queue_num], skb);
3475 break;
3476 }
3477 if (unlikely(err))
78f18df4 3478 ieee80211_free_txskb(wl->hw, skb);
bad69194 3479 err = 0;
3480 }
21a75d77 3481
bad69194 3482 if (!err)
3483 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3484 }
3485
990b86f4
MB		 3486#if B43_DEBUG
3487 dev->tx_count++;
3488#endif
f5d40eed
MB		 3489 mutex_unlock(&wl->mutex);
3490}
21a75d77 3491
7bb45683 3492static void b43_op_tx(struct ieee80211_hw *hw,
36323f81
TH		 3493 struct ieee80211_tx_control *control,
3494 struct sk_buff *skb)
f5d40eed
MB		 3495{
3496 struct b43_wl *wl = hw_to_b43_wl(hw);
3497
3498 if (unlikely(skb->len < 2 + 2 + 6)) {
3499 /* Too short, this can't be a valid frame. */
78f18df4 3500 ieee80211_free_txskb(hw, skb);
7bb45683 3501 return;
f5d40eed
MB		 3502 }
3503 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3504
bad69194 3505 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3506 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3507 ieee80211_queue_work(wl->hw, &wl->tx_work);
3508 } else {
3509 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3510 }
e4d6b795
MB		 3511}
3512
e6f5b934
MB		 3513static void b43_qos_params_upload(struct b43_wldev *dev,
3514 const struct ieee80211_tx_queue_params *p,
3515 u16 shm_offset)
3516{
3517 u16 params[B43_NR_QOSPARAMS];
0b57664c 3518 int bslots, tmp;
e6f5b934
MB		 3519 unsigned int i;
3520
b0544eb6
MB		 3521 if (!dev->qos_enabled)
3522 return;
3523
0b57664c 3524 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3525
3526 memset(&params, 0, sizeof(params));
3527
3528 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3529 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3530 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3531 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3532 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3533 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3534 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3535
3536 for (i = 0; i < ARRAY_SIZE(params); i++) {
3537 if (i == B43_QOSPARAM_STATUS) {
3538 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3539 shm_offset + (i * 2));
3540 /* Mark the parameters as updated. */
3541 tmp |= 0x100;
3542 b43_shm_write16(dev, B43_SHM_SHARED,
3543 shm_offset + (i * 2),
3544 tmp);
3545 } else {
3546 b43_shm_write16(dev, B43_SHM_SHARED,
3547 shm_offset + (i * 2),
3548 params[i]);
3549 }
3550 }
3551}
3552
c40c1129
MB		 3553/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3554static const u16 b43_qos_shm_offsets[] = {
3555 /* [mac80211-queue-nr] = SHM_OFFSET, */
3556 [0] = B43_QOS_VOICE,
3557 [1] = B43_QOS_VIDEO,
3558 [2] = B43_QOS_BESTEFFORT,
3559 [3] = B43_QOS_BACKGROUND,
3560};
3561
5a5f3b40
MB		 3562/* Update all QOS parameters in hardware. */
3563static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3564{
3565 struct b43_wl *wl = dev->wl;
3566 struct b43_qos_params *params;
e6f5b934
MB		 3567 unsigned int i;
3568
b0544eb6
MB		 3569 if (!dev->qos_enabled)
3570 return;
3571
c40c1129
MB		 3572 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3573 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3574
3575 b43_mac_suspend(dev);
e6f5b934
MB		 3576 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3577 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3578 b43_qos_params_upload(dev, &(params->p),
3579 b43_qos_shm_offsets[i]);
e6f5b934 3580 }
e6f5b934
MB		 3581 b43_mac_enable(dev);
3582}
3583
3584static void b43_qos_clear(struct b43_wl *wl)
3585{
3586 struct b43_qos_params *params;
3587 unsigned int i;
3588
c40c1129
MB		 3589 /* Initialize QoS parameters to sane defaults. */
3590
3591 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3592 ARRAY_SIZE(wl->qos_params));
3593
e6f5b934
MB		 3594 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3595 params = &(wl->qos_params[i]);
3596
c40c1129
MB		 3597 switch (b43_qos_shm_offsets[i]) {
3598 case B43_QOS_VOICE:
3599 params->p.txop = 0;
3600 params->p.aifs = 2;
3601 params->p.cw_min = 0x0001;
3602 params->p.cw_max = 0x0001;
3603 break;
3604 case B43_QOS_VIDEO:
3605 params->p.txop = 0;
3606 params->p.aifs = 2;
3607 params->p.cw_min = 0x0001;
3608 params->p.cw_max = 0x0001;
3609 break;
3610 case B43_QOS_BESTEFFORT:
3611 params->p.txop = 0;
3612 params->p.aifs = 3;
3613 params->p.cw_min = 0x0001;
3614 params->p.cw_max = 0x03FF;
3615 break;
3616 case B43_QOS_BACKGROUND:
3617 params->p.txop = 0;
3618 params->p.aifs = 7;
3619 params->p.cw_min = 0x0001;
3620 params->p.cw_max = 0x03FF;
3621 break;
3622 default:
3623 B43_WARN_ON(1);
3624 }
e6f5b934
MB		 3625 }
3626}
3627
3628/* Initialize the core's QOS capabilities */
3629static void b43_qos_init(struct b43_wldev *dev)
3630{
b0544eb6
MB		 3631 if (!dev->qos_enabled) {
3632 /* Disable QOS support. */
3633 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3634 b43_write16(dev, B43_MMIO_IFSCTL,
3635 b43_read16(dev, B43_MMIO_IFSCTL)
3636 & ~B43_MMIO_IFSCTL_USE_EDCF);
3637 b43dbg(dev->wl, "QoS disabled\n");
3638 return;
3639 }
3640
e6f5b934 3641 /* Upload the current QOS parameters. */
5a5f3b40 3642 b43_qos_upload_all(dev);
e6f5b934
MB		 3643
3644 /* Enable QOS support. */
3645 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3646 b43_write16(dev, B43_MMIO_IFSCTL,
3647 b43_read16(dev, B43_MMIO_IFSCTL)
3648 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3649 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3650}
3651
8a3a3c85
EP		 3652static int b43_op_conf_tx(struct ieee80211_hw *hw,
3653 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3654 const struct ieee80211_tx_queue_params *params)
e4d6b795 3655{
e6f5b934 3656 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3657 struct b43_wldev *dev;
e6f5b934 3658 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3659 int err = -ENODEV;
e6f5b934
MB		 3660
3661 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3662 /* Queue not available or don't support setting
3663 * params on this queue. Return success to not
3664 * confuse mac80211. */
3665 return 0;
3666 }
5a5f3b40
MB		 3667 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3668 ARRAY_SIZE(wl->qos_params));
e6f5b934 3669
5a5f3b40
MB		 3670 mutex_lock(&wl->mutex);
3671 dev = wl->current_dev;
3672 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3673 goto out_unlock;
e6f5b934 3674
5a5f3b40
MB		 3675 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3676 b43_mac_suspend(dev);
3677 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3678 b43_qos_shm_offsets[queue]);
3679 b43_mac_enable(dev);
3680 err = 0;
e6f5b934 3681
5a5f3b40
MB		 3682out_unlock:
3683 mutex_unlock(&wl->mutex);
3684
3685 return err;
e4d6b795
MB		 3686}
3687
40faacc4
MB		 3688static int b43_op_get_stats(struct ieee80211_hw *hw,
3689 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3690{
3691 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3692
36dbd954 3693 mutex_lock(&wl->mutex);
e4d6b795 3694 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3695 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3696
3697 return 0;
3698}
3699
37a41b4a 3700static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3701{
3702 struct b43_wl *wl = hw_to_b43_wl(hw);
3703 struct b43_wldev *dev;
3704 u64 tsf;
3705
3706 mutex_lock(&wl->mutex);
08e87a83
AF		 3707 dev = wl->current_dev;
3708
3709 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3710 b43_tsf_read(dev, &tsf);
3711 else
3712 tsf = 0;
3713
08e87a83
AF		 3714 mutex_unlock(&wl->mutex);
3715
3716 return tsf;
3717}
3718
37a41b4a
EP		 3719static void b43_op_set_tsf(struct ieee80211_hw *hw,
3720 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3721{
3722 struct b43_wl *wl = hw_to_b43_wl(hw);
3723 struct b43_wldev *dev;
3724
3725 mutex_lock(&wl->mutex);
08e87a83
AF		 3726 dev = wl->current_dev;
3727
3728 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3729 b43_tsf_write(dev, tsf);
3730
08e87a83
AF		 3731 mutex_unlock(&wl->mutex);
3732}
3733
99da185a 3734static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3735{
3736 switch (band) {
3737 case IEEE80211_BAND_5GHZ:
3738 return "5";
3739 case IEEE80211_BAND_2GHZ:
3740 return "2.4";
3741 default:
3742 break;
3743 }
3744 B43_WARN_ON(1);
3745 return "";
3746}
3747
e4d6b795 3748/* Expects wl->mutex locked */
7a8af8cf
RM		 3749static int b43_switch_band(struct b43_wldev *dev,
3750 struct ieee80211_channel *chan)
e4d6b795 3751{
7a8af8cf
RM		 3752 struct b43_phy *phy = &dev->phy;
3753 bool gmode;
3754 u32 tmp;
e4d6b795 3755
644aa4d6
RM		 3756 switch (chan->band) {
3757 case IEEE80211_BAND_5GHZ:
7a8af8cf 3758 gmode = false;
644aa4d6
RM		 3759 break;
3760 case IEEE80211_BAND_2GHZ:
7a8af8cf 3761 gmode = true;
644aa4d6
RM		 3762 break;
3763 default:
3764 B43_WARN_ON(1);
3765 return -EINVAL;
bb1eeff1 3766 }
644aa4d6 3767
7a8af8cf
RM		 3768 if (!((gmode && phy->supports_2ghz) ||
3769 (!gmode && phy->supports_5ghz))) {
3770 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
bb1eeff1
MB		 3771 band_to_string(chan->band));
3772 return -ENODEV;
e4d6b795 3773 }
7a8af8cf
RM		 3774
3775 if (!!phy->gmode == !!gmode) {
e4d6b795
MB		 3776 /* This device is already running. */
3777 return 0;
3778 }
7a8af8cf
RM		 3779
3780 b43dbg(dev->wl, "Switching to %s GHz band\n",
bb1eeff1 3781 band_to_string(chan->band));
7a8af8cf 3782
6fe55143
RM		 3783 /* Some new devices don't need disabling radio for band switching */
3784 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3785 b43_software_rfkill(dev, true);
7a8af8cf
RM		 3786
3787 phy->gmode = gmode;
3788 b43_phy_put_into_reset(dev);
3789 switch (dev->dev->bus_type) {
3790#ifdef CONFIG_B43_BCMA
3791 case B43_BUS_BCMA:
3792 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3793 if (gmode)
3794 tmp |= B43_BCMA_IOCTL_GMODE;
3795 else
3796 tmp &= ~B43_BCMA_IOCTL_GMODE;
3797 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3798 break;
3799#endif
3800#ifdef CONFIG_B43_SSB
3801 case B43_BUS_SSB:
3802 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3803 if (gmode)
3804 tmp |= B43_TMSLOW_GMODE;
3805 else
3806 tmp &= ~B43_TMSLOW_GMODE;
3807 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3808 break;
3809#endif
e4d6b795 3810 }
7a8af8cf 3811 b43_phy_take_out_of_reset(dev);
e4d6b795 3812
7a8af8cf
RM		 3813 b43_upload_initvals_band(dev);
3814
3815 b43_phy_init(dev);
e4d6b795
MB		 3816
3817 return 0;
e4d6b795
MB		 3818}
3819
9124b077
JB		 3820/* Write the short and long frame retry limit values. */
3821static void b43_set_retry_limits(struct b43_wldev *dev,
3822 unsigned int short_retry,
3823 unsigned int long_retry)
3824{
3825 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3826 * the chip-internal counter. */
3827 short_retry = min(short_retry, (unsigned int)0xF);
3828 long_retry = min(long_retry, (unsigned int)0xF);
3829
3830 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3831 short_retry);
3832 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3833 long_retry);
3834}
3835
e8975581 3836static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3837{
3838 struct b43_wl *wl = hw_to_b43_wl(hw);
53256511
RM		 3839 struct b43_wldev *dev = wl->current_dev;
3840 struct b43_phy *phy = &dev->phy;
e8975581 3841 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3842 int antenna;
e4d6b795 3843 int err = 0;
e4d6b795 3844
e4d6b795 3845 mutex_lock(&wl->mutex);
7a8af8cf
RM		 3846 b43_mac_suspend(dev);
3847
8c79e5ee 3848 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ea42e71c 3849 phy->chandef = &conf->chandef;
f9471e99 3850 phy->channel = conf->chandef.chan->hw_value;
2a190322 3851
8c79e5ee
RM		 3852 /* Switch the band (if necessary). */
3853 err = b43_switch_band(dev, conf->chandef.chan);
3854 if (err)
3855 goto out_mac_enable;
3856
3857 /* Switch to the requested channel.
3858 * The firmware takes care of races with the TX handler.
3859 */
f9471e99 3860 b43_switch_channel(dev, phy->channel);
8c79e5ee 3861 }
aa4c7b2a 3862
9124b077
JB		 3863 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3864 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3865 conf->long_frame_max_tx_count);
3866 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3867 if (!changed)
d10d0e57 3868 goto out_mac_enable;
e4d6b795 3869
0869aea0 3870 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3871
e4d6b795
MB		 3872 /* Adjust the desired TX power level. */
3873 if (conf->power_level != 0) {
18c8adeb
MB		 3874 if (conf->power_level != phy->desired_txpower) {
3875 phy->desired_txpower = conf->power_level;
3876 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3877 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3878 }
3879 }
3880
3881 /* Antennas for RX and management frame TX. */
0f4ac38b 3882 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3883 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3884 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3885 if (phy->ops->set_rx_antenna)
3886 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3887
fd4973c5
LF		 3888 if (wl->radio_enabled != phy->radio_on) {
3889 if (wl->radio_enabled) {
19d337df 3890 b43_software_rfkill(dev, false);
fda9abcf
MB		 3891 b43info(dev->wl, "Radio turned on by software\n");
3892 if (!dev->radio_hw_enable) {
3893 b43info(dev->wl, "The hardware RF-kill button "
3894 "still turns the radio physically off. "
3895 "Press the button to turn it on.\n");
3896 }
3897 } else {
19d337df 3898 b43_software_rfkill(dev, true);
fda9abcf
MB		 3899 b43info(dev->wl, "Radio turned off by software\n");
3900 }
3901 }
3902
d10d0e57
MB		 3903out_mac_enable:
3904 b43_mac_enable(dev);
e4d6b795
MB		 3905 mutex_unlock(&wl->mutex);
3906
3907 return err;
3908}
3909
881d948c 3910static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3911{
3912 struct ieee80211_supported_band *sband =
3913 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3914 struct ieee80211_rate *rate;
3915 int i;
3916 u16 basic, direct, offset, basic_offset, rateptr;
3917
3918 for (i = 0; i < sband->n_bitrates; i++) {
3919 rate = &sband->bitrates[i];
3920
3921 if (b43_is_cck_rate(rate->hw_value)) {
3922 direct = B43_SHM_SH_CCKDIRECT;
3923 basic = B43_SHM_SH_CCKBASIC;
3924 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3925 offset &= 0xF;
3926 } else {
3927 direct = B43_SHM_SH_OFDMDIRECT;
3928 basic = B43_SHM_SH_OFDMBASIC;
3929 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3930 offset &= 0xF;
3931 }
3932
3933 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3934
3935 if (b43_is_cck_rate(rate->hw_value)) {
3936 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3937 basic_offset &= 0xF;
3938 } else {
3939 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3940 basic_offset &= 0xF;
3941 }
3942
3943 /*
3944 * Get the pointer that we need to point to
3945 * from the direct map
3946 */
3947 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3948 direct + 2 * basic_offset);
3949 /* and write it to the basic map */
3950 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3951 rateptr);
3952 }
3953}
3954
3955static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3956 struct ieee80211_vif *vif,
3957 struct ieee80211_bss_conf *conf,
3958 u32 changed)
3959{
3960 struct b43_wl *wl = hw_to_b43_wl(hw);
3961 struct b43_wldev *dev;
c7ab5ef9
JB		 3962
3963 mutex_lock(&wl->mutex);
3964
3965 dev = wl->current_dev;
d10d0e57 3966 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3967 goto out_unlock_mutex;
2d0ddec5
JB		 3968
3969 B43_WARN_ON(wl->vif != vif);
3970
3971 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3972 if (conf->bssid)
3973 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3974 else
3975 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3976 }
2d0ddec5 3977
3f0d843b
JB		 3978 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3979 if (changed & BSS_CHANGED_BEACON &&
3980 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3981 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3982 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3983 b43_update_templates(wl);
3984
3985 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3986 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3987 }
3988
c7ab5ef9
JB		 3989 b43_mac_suspend(dev);
3990
57c4d7b4
JB		 3991 /* Update templates for AP/mesh mode. */
3992 if (changed & BSS_CHANGED_BEACON_INT &&
3993 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3994 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3995 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3996 conf->beacon_int)
57c4d7b4
JB		 3997 b43_set_beacon_int(dev, conf->beacon_int);
3998
c7ab5ef9
JB		 3999 if (changed & BSS_CHANGED_BASIC_RATES)
4000 b43_update_basic_rates(dev, conf->basic_rates);
4001
4002 if (changed & BSS_CHANGED_ERP_SLOT) {
4003 if (conf->use_short_slot)
4004 b43_short_slot_timing_enable(dev);
4005 else
4006 b43_short_slot_timing_disable(dev);
4007 }
4008
4009 b43_mac_enable(dev);
d10d0e57 4010out_unlock_mutex:
c7ab5ef9 4011 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 4012}
4013
40faacc4 4014static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4015 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4016 struct ieee80211_key_conf *key)
e4d6b795
MB		 4017{
4018 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4019 struct b43_wldev *dev;
e4d6b795
MB		 4020 u8 algorithm;
4021 u8 index;
c6dfc9a8 4022 int err;
060210f9 4023 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4024
4025 if (modparam_nohwcrypt)
4026 return -ENOSPC; /* User disabled HW-crypto */
4027
78f9c850
AQ		 4028 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4029 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4030 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4031 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4032 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4033 /*
4034 * For now, disable hw crypto for the RSN IBSS group keys. This
4035 * could be optimized in the future, but until that gets
4036 * implemented, use of software crypto for group addressed
4037 * frames is a acceptable to allow RSN IBSS to be used.
4038 */
4039 return -EOPNOTSUPP;
4040 }
4041
c6dfc9a8 4042 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4043
4044 dev = wl->current_dev;
4045 err = -ENODEV;
4046 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4047 goto out_unlock;
4048
403a3a13 4049 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4050 /* We don't have firmware for the crypto engine.
4051 * Must use software-crypto. */
4052 err = -EOPNOTSUPP;
4053 goto out_unlock;
4054 }
4055
c6dfc9a8 4056 err = -EINVAL;
97359d12
JB		 4057 switch (key->cipher) {
4058 case WLAN_CIPHER_SUITE_WEP40:
4059 algorithm = B43_SEC_ALGO_WEP40;
4060 break;
4061 case WLAN_CIPHER_SUITE_WEP104:
4062 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4063 break;
97359d12 4064 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4065 algorithm = B43_SEC_ALGO_TKIP;
4066 break;
97359d12 4067 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4068 algorithm = B43_SEC_ALGO_AES;
4069 break;
4070 default:
4071 B43_WARN_ON(1);
c6dfc9a8 4072 goto out_unlock;
e4d6b795 4073 }
e4d6b795
MB		 4074 index = (u8) (key->keyidx);
4075 if (index > 3)
e4d6b795 4076 goto out_unlock;
e4d6b795
MB		 4077
4078 switch (cmd) {
4079 case SET_KEY:
035d0243 4080 if (algorithm == B43_SEC_ALGO_TKIP &&
4081 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4082 !modparam_hwtkip)) {
4083 /* We support only pairwise key */
e4d6b795
MB		 4084 err = -EOPNOTSUPP;
4085 goto out_unlock;
4086 }
4087
e808e586 4088 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4089 if (WARN_ON(!sta)) {
4090 err = -EOPNOTSUPP;
4091 goto out_unlock;
4092 }
e808e586 4093 /* Pairwise key with an assigned MAC address. */
e4d6b795 4094 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4095 key->key, key->keylen,
4096 sta->addr, key);
e808e586
MB		 4097 } else {
4098 /* Group key */
4099 err = b43_key_write(dev, index, algorithm,
4100 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4101 }
4102 if (err)
4103 goto out_unlock;
4104
4105 if (algorithm == B43_SEC_ALGO_WEP40 ||
4106 algorithm == B43_SEC_ALGO_WEP104) {
4107 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4108 } else {
4109 b43_hf_write(dev,
4110 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4111 }
4112 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4113 if (algorithm == B43_SEC_ALGO_TKIP)
4114 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4115 break;
4116 case DISABLE_KEY: {
4117 err = b43_key_clear(dev, key->hw_key_idx);
4118 if (err)
4119 goto out_unlock;
4120 break;
4121 }
4122 default:
4123 B43_WARN_ON(1);
4124 }
9cf7f247 4125
e4d6b795 4126out_unlock:
e4d6b795
MB		 4127 if (!err) {
4128 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4129 "mac: %pM\n",
e4d6b795 4130 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4131 sta ? sta->addr : bcast_addr);
9cf7f247 4132 b43_dump_keymemory(dev);
e4d6b795 4133 }
9cf7f247
MB		 4134 mutex_unlock(&wl->mutex);
4135
e4d6b795
MB		 4136 return err;
4137}
4138
40faacc4
MB		 4139static void b43_op_configure_filter(struct ieee80211_hw *hw,
4140 unsigned int changed, unsigned int *fflags,
3ac64bee 4141 u64 multicast)
e4d6b795
MB		 4142{
4143 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4144 struct b43_wldev *dev;
e4d6b795 4145
36dbd954
MB		 4146 mutex_lock(&wl->mutex);
4147 dev = wl->current_dev;
4150c572
JB		 4148 if (!dev) {
4149 *fflags = 0;
36dbd954 4150 goto out_unlock;
e4d6b795 4151 }
4150c572 4152
4150c572
JB		 4153 *fflags &= FIF_PROMISC_IN_BSS |
4154 FIF_ALLMULTI |
4155 FIF_FCSFAIL |
4156 FIF_PLCPFAIL |
4157 FIF_CONTROL |
4158 FIF_OTHER_BSS |
4159 FIF_BCN_PRBRESP_PROMISC;
4160
4161 changed &= FIF_PROMISC_IN_BSS |
4162 FIF_ALLMULTI |
4163 FIF_FCSFAIL |
4164 FIF_PLCPFAIL |
4165 FIF_CONTROL |
4166 FIF_OTHER_BSS |
4167 FIF_BCN_PRBRESP_PROMISC;
4168
4169 wl->filter_flags = *fflags;
4170
4171 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4172 b43_adjust_opmode(dev);
36dbd954
MB		 4173
4174out_unlock:
4175 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4176}
4177
36dbd954
MB		 4178/* Locking: wl->mutex
4179 * Returns the current dev. This might be different from the passed in dev,
4180 * because the core might be gone away while we unlocked the mutex. */
4181static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4182{
9a53bf54 4183 struct b43_wl *wl;
36dbd954 4184 struct b43_wldev *orig_dev;
49d965c8 4185 u32 mask;
bad69194 4186 int queue_num;
e4d6b795 4187
9a53bf54
LF		 4188 if (!dev)
4189 return NULL;
4190 wl = dev->wl;
36dbd954
MB		 4191redo:
4192 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4193 return dev;
a19d12d7 4194
f5d40eed 4195 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4196 mutex_unlock(&wl->mutex);
4197 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4198 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4199 mutex_lock(&wl->mutex);
4200 dev = wl->current_dev;
4201 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4202 /* Whoops, aliens ate up the device while we were unlocked. */
4203 return dev;
4204 }
a19d12d7 4205
36dbd954 4206 /* Disable interrupts on the device. */
e4d6b795 4207 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4208 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4209 /* wl->mutex is locked. That is enough. */
4210 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4211 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4212 } else {
4213 spin_lock_irq(&wl->hardirq_lock);
4214 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4215 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4216 spin_unlock_irq(&wl->hardirq_lock);
4217 }
176e9f6a 4218 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4219 orig_dev = dev;
e4d6b795 4220 mutex_unlock(&wl->mutex);
505fb019 4221 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4222 b43_sdio_free_irq(dev);
4223 } else {
a18c715e
RM		 4224 synchronize_irq(dev->dev->irq);
4225 free_irq(dev->dev->irq, dev);
176e9f6a 4226 }
e4d6b795 4227 mutex_lock(&wl->mutex);
36dbd954
MB		 4228 dev = wl->current_dev;
4229 if (!dev)
4230 return dev;
4231 if (dev != orig_dev) {
4232 if (b43_status(dev) >= B43_STAT_STARTED)
4233 goto redo;
4234 return dev;
4235 }
49d965c8
MB		 4236 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4237 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4238
bad69194 4239 /* Drain all TX queues. */
4240 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
78f18df4
FF		 4241 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4242 struct sk_buff *skb;
4243
4244 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4245 ieee80211_free_txskb(wl->hw, skb);
4246 }
bad69194 4247 }
f5d40eed 4248
e4d6b795 4249 b43_mac_suspend(dev);
a78b3bb2 4250 b43_leds_exit(dev);
e4d6b795 4251 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4252
4253 return dev;
e4d6b795
MB		 4254}
4255
4256/* Locking: wl->mutex */
4257static int b43_wireless_core_start(struct b43_wldev *dev)
4258{
4259 int err;
4260
4261 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4262
4263 drain_txstatus_queue(dev);
505fb019 4264 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4265 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4266 if (err) {
4267 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4268 goto out;
4269 }
4270 } else {
a18c715e 4271 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4272 b43_interrupt_thread_handler,
4273 IRQF_SHARED, KBUILD_MODNAME, dev);
4274 if (err) {
dedb1eb9 4275 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4276 dev->dev->irq);
3dbba8e2
AH		 4277 goto out;
4278 }
e4d6b795
MB		 4279 }
4280
4281 /* We are ready to run. */
0866b03c 4282 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4283 b43_set_status(dev, B43_STAT_STARTED);
4284
4285 /* Start data flow (TX/RX). */
4286 b43_mac_enable(dev);
13790728 4287 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4288
25985edc 4289 /* Start maintenance work */
e4d6b795
MB		 4290 b43_periodic_tasks_setup(dev);
4291
a78b3bb2
MB		 4292 b43_leds_init(dev);
4293
e4d6b795 4294 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4295out:
e4d6b795
MB		 4296 return err;
4297}
4298
2fdf8c54
RM		 4299static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4300{
4301 switch (phy_type) {
4302 case B43_PHYTYPE_A:
4303 return "A";
4304 case B43_PHYTYPE_B:
4305 return "B";
4306 case B43_PHYTYPE_G:
4307 return "G";
4308 case B43_PHYTYPE_N:
4309 return "N";
4310 case B43_PHYTYPE_LP:
4311 return "LP";
4312 case B43_PHYTYPE_SSLPN:
4313 return "SSLPN";
4314 case B43_PHYTYPE_HT:
4315 return "HT";
4316 case B43_PHYTYPE_LCN:
4317 return "LCN";
4318 case B43_PHYTYPE_LCNXN:
4319 return "LCNXN";
4320 case B43_PHYTYPE_LCN40:
4321 return "LCN40";
4322 case B43_PHYTYPE_AC:
4323 return "AC";
4324 }
4325 return "UNKNOWN";
4326}
4327
e4d6b795
MB		 4328/* Get PHY and RADIO versioning numbers */
4329static int b43_phy_versioning(struct b43_wldev *dev)
4330{
4331 struct b43_phy *phy = &dev->phy;
fe5e499f 4332 const u8 core_rev = dev->dev->core_rev;
e4d6b795
MB		 4333 u32 tmp;
4334 u8 analog_type;
4335 u8 phy_type;
4336 u8 phy_rev;
4337 u16 radio_manuf;
4338 u16 radio_ver;
4339 u16 radio_rev;
4340 int unsupported = 0;
4341
4342 /* Get PHY versioning */
4343 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4344 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4345 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4346 phy_rev = (tmp & B43_PHYVER_VERSION);
b49c3caf
RM		 4347
4348 /* LCNXN is continuation of N which run out of revisions */
4349 if (phy_type == B43_PHYTYPE_LCNXN) {
4350 phy_type = B43_PHYTYPE_N;
4351 phy_rev += 16;
4352 }
4353
e4d6b795 4354 switch (phy_type) {
418378fe 4355#ifdef CONFIG_B43_PHY_G
e4d6b795 4356 case B43_PHYTYPE_G:
013978b6 4357 if (phy_rev > 9)
e4d6b795
MB		 4358 unsupported = 1;
4359 break;
418378fe 4360#endif
692d2c0f 4361#ifdef CONFIG_B43_PHY_N
d5c71e46 4362 case B43_PHYTYPE_N:
ab72efdf 4363 if (phy_rev > 9)
d5c71e46
MB		 4364 unsupported = 1;
4365 break;
6b1c7c67
MB		 4366#endif
4367#ifdef CONFIG_B43_PHY_LP
4368 case B43_PHYTYPE_LP:
9d86a2d5 4369 if (phy_rev > 2)
6b1c7c67
MB		 4370 unsupported = 1;
4371 break;
d7520b1d
RM		 4372#endif
4373#ifdef CONFIG_B43_PHY_HT
4374 case B43_PHYTYPE_HT:
4375 if (phy_rev > 1)
4376 unsupported = 1;
4377 break;
1d738e64
RM		 4378#endif
4379#ifdef CONFIG_B43_PHY_LCN
4380 case B43_PHYTYPE_LCN:
4381 if (phy_rev > 1)
4382 unsupported = 1;
4383 break;
d5c71e46 4384#endif
e4d6b795
MB		 4385 default:
4386 unsupported = 1;
6403eab1 4387 }
e4d6b795 4388 if (unsupported) {
2fdf8c54
RM		 4389 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4390 analog_type, phy_type, b43_phy_name(dev, phy_type),
4391 phy_rev);
e4d6b795
MB		 4392 return -EOPNOTSUPP;
4393 }
2fdf8c54
RM		 4394 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4395 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
e4d6b795
MB		 4396
4397 /* Get RADIO versioning */
fe5e499f
RM		 4398 if (core_rev == 40 || core_rev == 42) {
4399 radio_manuf = 0x17F;
4400
4401 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 0);
4402 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4403
4404 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1);
4405 radio_ver = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4406 } else if (core_rev >= 24) {
544e5d8b
RM		 4407 u16 radio24[3];
4408
4409 for (tmp = 0; tmp < 3; tmp++) {
4410 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4411 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4412 }
4413
4414 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4415 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4416
4417 radio_manuf = 0x17F;
4418 radio_ver = (radio24[2] << 8) | radio24[1];
4419 radio_rev = (radio24[0] & 0xF);
e4d6b795 4420 } else {
3fd48508
RM		 4421 if (dev->dev->chip_id == 0x4317) {
4422 if (dev->dev->chip_rev == 0)
4423 tmp = 0x3205017F;
4424 else if (dev->dev->chip_rev == 1)
4425 tmp = 0x4205017F;
4426 else
4427 tmp = 0x5205017F;
4428 } else {
4429 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4430 B43_RADIOCTL_ID);
4431 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4432 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4433 B43_RADIOCTL_ID);
4434 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4435 << 16;
4436 }
4437 radio_manuf = (tmp & 0x00000FFF);
4438 radio_ver = (tmp & 0x0FFFF000) >> 12;
4439 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4440 }
3fd48508 4441
96c755a3
MB		 4442 if (radio_manuf != 0x17F /* Broadcom */)
4443 unsupported = 1;
e4d6b795
MB		 4444 switch (phy_type) {
4445 case B43_PHYTYPE_A:
4446 if (radio_ver != 0x2060)
4447 unsupported = 1;
4448 if (radio_rev != 1)
4449 unsupported = 1;
4450 if (radio_manuf != 0x17F)
4451 unsupported = 1;
4452 break;
4453 case B43_PHYTYPE_B:
4454 if ((radio_ver & 0xFFF0) != 0x2050)
4455 unsupported = 1;
4456 break;
4457 case B43_PHYTYPE_G:
4458 if (radio_ver != 0x2050)
4459 unsupported = 1;
4460 break;
96c755a3 4461 case B43_PHYTYPE_N:
bb519bee 4462 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4463 unsupported = 1;
4464 break;
6b1c7c67 4465 case B43_PHYTYPE_LP:
9d86a2d5 4466 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4467 unsupported = 1;
4468 break;
d7520b1d
RM		 4469 case B43_PHYTYPE_HT:
4470 if (radio_ver != 0x2059)
4471 unsupported = 1;
4472 break;
1d738e64
RM		 4473 case B43_PHYTYPE_LCN:
4474 if (radio_ver != 0x2064)
4475 unsupported = 1;
4476 break;
e4d6b795
MB		 4477 default:
4478 B43_WARN_ON(1);
4479 }
4480 if (unsupported) {
4481 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4482 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4483 radio_manuf, radio_ver, radio_rev);
4484 return -EOPNOTSUPP;
4485 }
4486 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4487 radio_manuf, radio_ver, radio_rev);
4488
4489 phy->radio_manuf = radio_manuf;
4490 phy->radio_ver = radio_ver;
4491 phy->radio_rev = radio_rev;
4492
4493 phy->analog = analog_type;
4494 phy->type = phy_type;
4495 phy->rev = phy_rev;
4496
4497 return 0;
4498}
4499
4500static void setup_struct_phy_for_init(struct b43_wldev *dev,
4501 struct b43_phy *phy)
4502{
e4d6b795 4503 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4504 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4505 /* PHY TX errors counter. */
4506 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4507
4508#if B43_DEBUG
3db1cd5c
RR		 4509 phy->phy_locked = false;
4510 phy->radio_locked = false;
591f3dc2 4511#endif
e4d6b795
MB		 4512}
4513
4514static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4515{
3db1cd5c 4516 dev->dfq_valid = false;
aa6c7ae2 4517
6a724d68
MB		 4518 /* Assume the radio is enabled. If it's not enabled, the state will
4519 * immediately get fixed on the first periodic work run. */
3db1cd5c 4520 dev->radio_hw_enable = true;
e4d6b795
MB		 4521
4522 /* Stats */
4523 memset(&dev->stats, 0, sizeof(dev->stats));
4524
4525 setup_struct_phy_for_init(dev, &dev->phy);
4526
4527 /* IRQ related flags */
4528 dev->irq_reason = 0;
4529 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4530 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4531 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4532 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4533
4534 dev->mac_suspended = 1;
4535
4536 /* Noise calculation context */
4537 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4538}
4539
4540static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4541{
0581483a 4542 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4543 u64 hf;
e4d6b795 4544
1855ba78
MB		 4545 if (!modparam_btcoex)
4546 return;
95de2841 4547 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4548 return;
4549 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4550 return;
4551
4552 hf = b43_hf_read(dev);
95de2841 4553 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4554 hf |= B43_HF_BTCOEXALT;
4555 else
4556 hf |= B43_HF_BTCOEX;
4557 b43_hf_write(dev, hf);
e4d6b795
MB		 4558}
4559
4560static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4561{
4562 if (!modparam_btcoex)
4563 return;
4564 //TODO
e4d6b795
MB		 4565}
4566
4567static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4568{
d48ae5c8 4569 struct ssb_bus *bus;
e4d6b795
MB		 4570 u32 tmp;
4571
bd7c8a59 4572#ifdef CONFIG_B43_SSB
d48ae5c8
RM		 4573 if (dev->dev->bus_type != B43_BUS_SSB)
4574 return;
bd7c8a59
RM		 4575#else
4576 return;
4577#endif
d48ae5c8
RM		 4578
4579 bus = dev->dev->sdev->bus;
4580
0fd82eaf
RM		 4581 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4582 (bus->chip_id == 0x4312)) {
d48ae5c8 4583 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4584 tmp &= ~SSB_IMCFGLO_REQTO;
4585 tmp &= ~SSB_IMCFGLO_SERTO;
4586 tmp |= 0x3;
d48ae5c8 4587 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4588 ssb_commit_settings(bus);
e4d6b795 4589 }
e4d6b795
MB		 4590}
4591
d59f720d
MB		 4592static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4593{
4594 u16 pu_delay;
4595
4596 /* The time value is in microseconds. */
4597 if (dev->phy.type == B43_PHYTYPE_A)
4598 pu_delay = 3700;
4599 else
4600 pu_delay = 1050;
05c914fe 4601 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4602 pu_delay = 500;
4603 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4604 pu_delay = max(pu_delay, (u16)2400);
4605
4606 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4607}
4608
4609/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4610static void b43_set_pretbtt(struct b43_wldev *dev)
4611{
4612 u16 pretbtt;
4613
4614 /* The time value is in microseconds. */
05c914fe 4615 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4616 pretbtt = 2;
4617 } else {
4618 if (dev->phy.type == B43_PHYTYPE_A)
4619 pretbtt = 120;
4620 else
4621 pretbtt = 250;
4622 }
4623 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4624 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4625}
4626
e4d6b795
MB		 4627/* Shutdown a wireless core */
4628/* Locking: wl->mutex */
4629static void b43_wireless_core_exit(struct b43_wldev *dev)
4630{
36dbd954
MB		 4631 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4632 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4633 return;
84c164a3 4634
e4d6b795
MB		 4635 b43_set_status(dev, B43_STAT_UNINIT);
4636
1f7d87b0 4637 /* Stop the microcode PSM. */
5056635c
RM		 4638 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4639 B43_MACCTL_PSM_JMP0);
1f7d87b0 4640
50023008
HM		 4641 switch (dev->dev->bus_type) {
4642#ifdef CONFIG_B43_BCMA
4643 case B43_BUS_BCMA:
4644 bcma_core_pci_down(dev->dev->bdev->bus);
4645 break;
4646#endif
4647#ifdef CONFIG_B43_SSB
4648 case B43_BUS_SSB:
4649 /* TODO */
4650 break;
4651#endif
4652 }
4653
e4d6b795 4654 b43_dma_free(dev);
5100d5ac 4655 b43_pio_free(dev);
e4d6b795 4656 b43_chip_exit(dev);
cb24f57f 4657 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4658 if (dev->wl->current_beacon) {
4659 dev_kfree_skb_any(dev->wl->current_beacon);
4660 dev->wl->current_beacon = NULL;
4661 }
4662
24ca39d6
RM		 4663 b43_device_disable(dev, 0);
4664 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4665}
4666
4667/* Initialize a wireless core */
4668static int b43_wireless_core_init(struct b43_wldev *dev)
4669{
0581483a 4670 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4671 struct b43_phy *phy = &dev->phy;
4672 int err;
a259d6a4 4673 u64 hf;
e4d6b795
MB		 4674
4675 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4676
24ca39d6 4677 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4678 if (err)
4679 goto out;
4da909e7
RM		 4680 if (!b43_device_is_enabled(dev))
4681 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4682
fb11137a 4683 /* Reset all data structures. */
e4d6b795 4684 setup_struct_wldev_for_init(dev);
fb11137a 4685 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4686
4687 /* Enable IRQ routing to this device. */
6cbab0d9 4688 switch (dev->dev->bus_type) {
42c9a458
RM		 4689#ifdef CONFIG_B43_BCMA
4690 case B43_BUS_BCMA:
dfae7143 4691 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
42c9a458 4692 dev->dev->bdev, true);
50023008 4693 bcma_core_pci_up(dev->dev->bdev->bus);
42c9a458
RM		 4694 break;
4695#endif
6cbab0d9
RM		 4696#ifdef CONFIG_B43_SSB
4697 case B43_BUS_SSB:
4698 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4699 dev->dev->sdev);
4700 break;
4701#endif
4702 }
e4d6b795
MB		 4703
4704 b43_imcfglo_timeouts_workaround(dev);
4705 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4706 if (phy->ops->prepare_hardware) {
4707 err = phy->ops->prepare_hardware(dev);
ef1a628d 4708 if (err)
fb11137a 4709 goto err_busdown;
ef1a628d 4710 }
e4d6b795
MB		 4711 err = b43_chip_init(dev);
4712 if (err)
fb11137a 4713 goto err_busdown;
e4d6b795 4714 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4715 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4716 hf = b43_hf_read(dev);
4717 if (phy->type == B43_PHYTYPE_G) {
4718 hf |= B43_HF_SYMW;
4719 if (phy->rev == 1)
4720 hf |= B43_HF_GDCW;
95de2841 4721 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4722 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4723 }
4724 if (phy->radio_ver == 0x2050) {
4725 if (phy->radio_rev == 6)
4726 hf |= B43_HF_4318TSSI;
4727 if (phy->radio_rev < 6)
4728 hf |= B43_HF_VCORECALC;
e4d6b795 4729 }
1cc8f476
MB		 4730 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4731 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
bd7c8a59 4732#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
6cbab0d9
RM		 4733 if (dev->dev->bus_type == B43_BUS_SSB &&
4734 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4735 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4736 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4737#endif
25d3ef59 4738 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4739 b43_hf_write(dev, hf);
4740
74cfdba7
MB		 4741 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4742 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4743 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4744 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4745
4746 /* Disable sending probe responses from firmware.
4747 * Setting the MaxTime to one usec will always trigger
4748 * a timeout, so we never send any probe resp.
4749 * A timeout of zero is infinite. */
4750 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4751
4752 b43_rate_memory_init(dev);
5042c507 4753 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4754
4755 /* Minimum Contention Window */
c5a079f4 4756 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4757 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4758 else
e4d6b795 4759 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4760 /* Maximum Contention Window */
4761 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4762
505fb019 4763 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4764 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4765 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4766 err = b43_pio_init(dev);
4767 } else if (dev->use_pio) {
4768 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4769 "This should not be needed and will result in lower "
4770 "performance.\n");
3db1cd5c 4771 dev->__using_pio_transfers = true;
5100d5ac
MB		 4772 err = b43_pio_init(dev);
4773 } else {
3db1cd5c 4774 dev->__using_pio_transfers = false;
5100d5ac
MB		 4775 err = b43_dma_init(dev);
4776 }
e4d6b795
MB		 4777 if (err)
4778 goto err_chip_exit;
03b29773 4779 b43_qos_init(dev);
d59f720d 4780 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4781 b43_bluetooth_coext_enable(dev);
4782
24ca39d6 4783 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4784 b43_upload_card_macaddress(dev);
e4d6b795 4785 b43_security_init(dev);
e4d6b795 4786
5ab9549a 4787 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4788
4789 b43_set_status(dev, B43_STAT_INITIALIZED);
4790
1a8d1227 4791out:
e4d6b795
MB		 4792 return err;
4793
ef1a628d 4794err_chip_exit:
e4d6b795 4795 b43_chip_exit(dev);
ef1a628d 4796err_busdown:
24ca39d6 4797 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4798 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4799 return err;
4800}
4801
40faacc4 4802static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4803 struct ieee80211_vif *vif)
e4d6b795
MB		 4804{
4805 struct b43_wl *wl = hw_to_b43_wl(hw);
4806 struct b43_wldev *dev;
e4d6b795 4807 int err = -EOPNOTSUPP;
4150c572
JB		 4808
4809 /* TODO: allow WDS/AP devices to coexist */
4810
1ed32e4f
JB		 4811 if (vif->type != NL80211_IFTYPE_AP &&
4812 vif->type != NL80211_IFTYPE_MESH_POINT &&
4813 vif->type != NL80211_IFTYPE_STATION &&
4814 vif->type != NL80211_IFTYPE_WDS &&
4815 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4816 return -EOPNOTSUPP;
e4d6b795
MB		 4817
4818 mutex_lock(&wl->mutex);
4150c572 4819 if (wl->operating)
e4d6b795
MB		 4820 goto out_mutex_unlock;
4821
1ed32e4f 4822 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4823
4824 dev = wl->current_dev;
3db1cd5c 4825 wl->operating = true;
1ed32e4f
JB		 4826 wl->vif = vif;
4827 wl->if_type = vif->type;
4828 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4829
4150c572 4830 b43_adjust_opmode(dev);
d59f720d
MB		 4831 b43_set_pretbtt(dev);
4832 b43_set_synth_pu_delay(dev, 0);
4150c572 4833 b43_upload_card_macaddress(dev);
4150c572
JB		 4834
4835 err = 0;
4836 out_mutex_unlock:
4837 mutex_unlock(&wl->mutex);
4838
2a190322
FF		 4839 if (err == 0)
4840 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4841
4150c572
JB		 4842 return err;
4843}
4844
40faacc4 4845static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4846 struct ieee80211_vif *vif)
4150c572
JB		 4847{
4848 struct b43_wl *wl = hw_to_b43_wl(hw);
4849 struct b43_wldev *dev = wl->current_dev;
4150c572 4850
1ed32e4f 4851 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4852
4853 mutex_lock(&wl->mutex);
4854
4855 B43_WARN_ON(!wl->operating);
1ed32e4f 4856 B43_WARN_ON(wl->vif != vif);
32bfd35d 4857 wl->vif = NULL;
4150c572 4858
3db1cd5c 4859 wl->operating = false;
4150c572 4860
4150c572
JB		 4861 b43_adjust_opmode(dev);
4862 memset(wl->mac_addr, 0, ETH_ALEN);
4863 b43_upload_card_macaddress(dev);
4150c572
JB		 4864
4865 mutex_unlock(&wl->mutex);
4866}
4867
40faacc4 4868static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4869{
4870 struct b43_wl *wl = hw_to_b43_wl(hw);
4871 struct b43_wldev *dev = wl->current_dev;
4872 int did_init = 0;
923403b8 4873 int err = 0;
4150c572 4874
7be1bb6b
MB		 4875 /* Kill all old instance specific information to make sure
4876 * the card won't use it in the short timeframe between start
4877 * and mac80211 reconfiguring it. */
4878 memset(wl->bssid, 0, ETH_ALEN);
4879 memset(wl->mac_addr, 0, ETH_ALEN);
4880 wl->filter_flags = 0;
3db1cd5c 4881 wl->radiotap_enabled = false;
e6f5b934 4882 b43_qos_clear(wl);
3db1cd5c
RR		 4883 wl->beacon0_uploaded = false;
4884 wl->beacon1_uploaded = false;
4885 wl->beacon_templates_virgin = true;
4886 wl->radio_enabled = true;
7be1bb6b 4887
4150c572
JB		 4888 mutex_lock(&wl->mutex);
4889
e4d6b795
MB		 4890 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4891 err = b43_wireless_core_init(dev);
f41f3f37 4892 if (err)
e4d6b795
MB		 4893 goto out_mutex_unlock;
4894 did_init = 1;
4895 }
4150c572 4896
e4d6b795
MB		 4897 if (b43_status(dev) < B43_STAT_STARTED) {
4898 err = b43_wireless_core_start(dev);
4899 if (err) {
4900 if (did_init)
4901 b43_wireless_core_exit(dev);
4902 goto out_mutex_unlock;
4903 }
4904 }
4905
f41f3f37
JB		 4906 /* XXX: only do if device doesn't support rfkill irq */
4907 wiphy_rfkill_start_polling(hw->wiphy);
4908
4150c572 4909 out_mutex_unlock:
e4d6b795
MB		 4910 mutex_unlock(&wl->mutex);
4911
dbdedbdf
SF		 4912 /*
4913 * Configuration may have been overwritten during initialization.
4914 * Reload the configuration, but only if initialization was
4915 * successful. Reloading the configuration after a failed init
4916 * may hang the system.
4917 */
4918 if (!err)
4919 b43_op_config(hw, ~0);
2a190322 4920
e4d6b795
MB		 4921 return err;
4922}
4923
40faacc4 4924static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4925{
4926 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4927 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4928
a82d9922 4929 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4930
ccde8a45
GL		 4931 if (!dev)
4932 goto out;
4933
e4d6b795 4934 mutex_lock(&wl->mutex);
36dbd954
MB		 4935 if (b43_status(dev) >= B43_STAT_STARTED) {
4936 dev = b43_wireless_core_stop(dev);
4937 if (!dev)
4938 goto out_unlock;
4939 }
4150c572 4940 b43_wireless_core_exit(dev);
3db1cd5c 4941 wl->radio_enabled = false;
36dbd954
MB		 4942
4943out_unlock:
e4d6b795 4944 mutex_unlock(&wl->mutex);
ccde8a45 4945out:
18c8adeb 4946 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4947}
4948
17741cdc
JB		 4949static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4950 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4951{
4952 struct b43_wl *wl = hw_to_b43_wl(hw);
4953
8f611288 4954 /* FIXME: add locking */
9d139c81 4955 b43_update_templates(wl);
e66fee6a
MB		 4956
4957 return 0;
4958}
4959
38968d09
JB		 4960static void b43_op_sta_notify(struct ieee80211_hw *hw,
4961 struct ieee80211_vif *vif,
4962 enum sta_notify_cmd notify_cmd,
17741cdc 4963 struct ieee80211_sta *sta)
38968d09
JB		 4964{
4965 struct b43_wl *wl = hw_to_b43_wl(hw);
4966
4967 B43_WARN_ON(!vif || wl->vif != vif);
4968}
4969
25d3ef59
MB		 4970static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4971{
4972 struct b43_wl *wl = hw_to_b43_wl(hw);
4973 struct b43_wldev *dev;
4974
4975 mutex_lock(&wl->mutex);
4976 dev = wl->current_dev;
4977 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4978 /* Disable CFP update during scan on other channels. */
4979 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4980 }
4981 mutex_unlock(&wl->mutex);
4982}
4983
4984static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4985{
4986 struct b43_wl *wl = hw_to_b43_wl(hw);
4987 struct b43_wldev *dev;
4988
4989 mutex_lock(&wl->mutex);
4990 dev = wl->current_dev;
4991 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4992 /* Re-enable CFP update. */
4993 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4994 }
4995 mutex_unlock(&wl->mutex);
4996}
4997
354b4f04
JL		 4998static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4999 struct survey_info *survey)
5000{
5001 struct b43_wl *wl = hw_to_b43_wl(hw);
5002 struct b43_wldev *dev = wl->current_dev;
5003 struct ieee80211_conf *conf = &hw->conf;
5004
5005 if (idx != 0)
5006 return -ENOENT;
5007
675a0b04 5008 survey->channel = conf->chandef.chan;
354b4f04
JL		 5009 survey->filled = SURVEY_INFO_NOISE_DBM;
5010 survey->noise = dev->stats.link_noise;
5011
5012 return 0;
5013}
5014
e4d6b795 5015static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 5016 .tx = b43_op_tx,
5017 .conf_tx = b43_op_conf_tx,
5018 .add_interface = b43_op_add_interface,
5019 .remove_interface = b43_op_remove_interface,
5020 .config = b43_op_config,
c7ab5ef9 5021 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 5022 .configure_filter = b43_op_configure_filter,
5023 .set_key = b43_op_set_key,
035d0243 5024 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 5025 .get_stats = b43_op_get_stats,
08e87a83
AF		 5026 .get_tsf = b43_op_get_tsf,
5027 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 5028 .start = b43_op_start,
5029 .stop = b43_op_stop,
e66fee6a 5030 .set_tim = b43_op_beacon_set_tim,
38968d09 5031 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 5032 .sw_scan_start = b43_op_sw_scan_start_notifier,
5033 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 5034 .get_survey = b43_op_get_survey,
f41f3f37 5035 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 5036};
5037
5038/* Hard-reset the chip. Do not call this directly.
5039 * Use b43_controller_restart()
5040 */
5041static void b43_chip_reset(struct work_struct *work)
5042{
5043 struct b43_wldev *dev =
5044 container_of(work, struct b43_wldev, restart_work);
5045 struct b43_wl *wl = dev->wl;
5046 int err = 0;
5047 int prev_status;
5048
5049 mutex_lock(&wl->mutex);
5050
5051 prev_status = b43_status(dev);
5052 /* Bring the device down... */
36dbd954
MB		 5053 if (prev_status >= B43_STAT_STARTED) {
5054 dev = b43_wireless_core_stop(dev);
5055 if (!dev) {
5056 err = -ENODEV;
5057 goto out;
5058 }
5059 }
e4d6b795
MB		 5060 if (prev_status >= B43_STAT_INITIALIZED)
5061 b43_wireless_core_exit(dev);
5062
5063 /* ...and up again. */
5064 if (prev_status >= B43_STAT_INITIALIZED) {
5065 err = b43_wireless_core_init(dev);
5066 if (err)
5067 goto out;
5068 }
5069 if (prev_status >= B43_STAT_STARTED) {
5070 err = b43_wireless_core_start(dev);
5071 if (err) {
5072 b43_wireless_core_exit(dev);
5073 goto out;
5074 }
5075 }
3bf0a32e
MB		 5076out:
5077 if (err)
5078 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5079 mutex_unlock(&wl->mutex);
2a190322
FF		 5080
5081 if (err) {
e4d6b795 5082 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5083 return;
5084 }
5085
5086 /* reload configuration */
5087 b43_op_config(wl->hw, ~0);
5088 if (wl->vif)
5089 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5090
5091 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5092}
5093
bb1eeff1 5094static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5095 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5096{
5097 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 5098
bb1eeff1
MB		 5099 if (have_2ghz_phy)
5100 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5101 if (dev->phy.type == B43_PHYTYPE_N) {
5102 if (have_5ghz_phy)
5103 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5104 } else {
5105 if (have_5ghz_phy)
5106 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5107 }
96c755a3 5108
bb1eeff1
MB		 5109 dev->phy.supports_2ghz = have_2ghz_phy;
5110 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5111
5112 return 0;
5113}
5114
5115static void b43_wireless_core_detach(struct b43_wldev *dev)
5116{
5117 /* We release firmware that late to not be required to re-request
5118 * is all the time when we reinit the core. */
5119 b43_release_firmware(dev);
fb11137a 5120 b43_phy_free(dev);
e4d6b795
MB		 5121}
5122
075ca604
RM		 5123static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5124 bool *have_5ghz_phy)
5125{
5126 u16 dev_id = 0;
5127
773cfc50
RM		 5128#ifdef CONFIG_B43_BCMA
5129 if (dev->dev->bus_type == B43_BUS_BCMA &&
5130 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5131 dev_id = dev->dev->bdev->bus->host_pci->device;
5132#endif
075ca604
RM		 5133#ifdef CONFIG_B43_SSB
5134 if (dev->dev->bus_type == B43_BUS_SSB &&
5135 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5136 dev_id = dev->dev->sdev->bus->host_pci->device;
5137#endif
773cfc50
RM		 5138 /* Override with SPROM value if available */
5139 if (dev->dev->bus_sprom->dev_id)
5140 dev_id = dev->dev->bus_sprom->dev_id;
075ca604
RM		 5141
5142 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5143 switch (dev_id) {
5144 case 0x4324: /* BCM4306 */
5145 case 0x4312: /* BCM4311 */
5146 case 0x4319: /* BCM4318 */
773cfc50
RM		 5147 case 0x4328: /* BCM4321 */
5148 case 0x432b: /* BCM4322 */
5149 case 0x4350: /* BCM43222 */
5150 case 0x4353: /* BCM43224 */
5151 case 0x0576: /* BCM43224 */
5152 case 0x435f: /* BCM6362 */
5153 case 0x4331: /* BCM4331 */
5154 case 0x4359: /* BCM43228 */
5155 case 0x43a0: /* BCM4360 */
5156 case 0x43b1: /* BCM4352 */
075ca604
RM		 5157 /* Dual band devices */
5158 *have_2ghz_phy = true;
5159 *have_5ghz_phy = true;
5160 return;
773cfc50
RM		 5161 case 0x4321: /* BCM4306 */
5162 case 0x4313: /* BCM4311 */
5163 case 0x431a: /* BCM4318 */
5164 case 0x432a: /* BCM4321 */
5165 case 0x432d: /* BCM4322 */
5166 case 0x4352: /* BCM43222 */
5167 case 0x4333: /* BCM4331 */
5168 case 0x43a2: /* BCM4360 */
5169 case 0x43b3: /* BCM4352 */
5170 /* 5 GHz only devices */
5171 *have_2ghz_phy = false;
5172 *have_5ghz_phy = true;
5173 return;
075ca604
RM		 5174 }
5175
5176 /* As a fallback, try to guess using PHY type */
5177 switch (dev->phy.type) {
5178 case B43_PHYTYPE_A:
5179 *have_2ghz_phy = false;
5180 *have_5ghz_phy = true;
5181 return;
5182 case B43_PHYTYPE_G:
5183 case B43_PHYTYPE_N:
5184 case B43_PHYTYPE_LP:
5185 case B43_PHYTYPE_HT:
5186 case B43_PHYTYPE_LCN:
5187 *have_2ghz_phy = true;
5188 *have_5ghz_phy = false;
5189 return;
5190 }
5191
5192 B43_WARN_ON(1);
5193}
5194
e4d6b795
MB		 5195static int b43_wireless_core_attach(struct b43_wldev *dev)
5196{
5197 struct b43_wl *wl = dev->wl;
09951ad4 5198 struct b43_phy *phy = &dev->phy;
e4d6b795 5199 int err;
40c62269 5200 u32 tmp;
3db1cd5c 5201 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5202
5203 /* Do NOT do any device initialization here.
5204 * Do it in wireless_core_init() instead.
5205 * This function is for gathering basic information about the HW, only.
5206 * Also some structs may be set up here. But most likely you want to have
5207 * that in core_init(), too.
5208 */
5209
24ca39d6 5210 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5211 if (err) {
5212 b43err(wl, "Bus powerup failed\n");
5213 goto out;
5214 }
e4d6b795 5215
09951ad4
RM		 5216 phy->do_full_init = true;
5217
075ca604 5218 /* Try to guess supported bands for the first init needs */
6cbab0d9 5219 switch (dev->dev->bus_type) {
42c9a458
RM		 5220#ifdef CONFIG_B43_BCMA
5221 case B43_BUS_BCMA:
40c62269
RM		 5222 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5223 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5224 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5225 break;
5226#endif
6cbab0d9
RM		 5227#ifdef CONFIG_B43_SSB
5228 case B43_BUS_SSB:
5229 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5230 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5231 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5232 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5233 } else
5234 B43_WARN_ON(1);
5235 break;
5236#endif
5237 }
e4d6b795 5238
96c755a3 5239 dev->phy.gmode = have_2ghz_phy;
4da909e7 5240 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795 5241
075ca604 5242 /* Get the PHY type. */
e4d6b795
MB		 5243 err = b43_phy_versioning(dev);
5244 if (err)
21954c36 5245 goto err_powerdown;
075ca604
RM		 5246
5247 /* Get real info about supported bands */
5248 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5249
5250 /* We don't support 5 GHz on some PHYs yet */
5251 switch (dev->phy.type) {
5252 case B43_PHYTYPE_A:
f15ec345 5253 case B43_PHYTYPE_G:
075ca604
RM		 5254 case B43_PHYTYPE_N:
5255 case B43_PHYTYPE_LP:
773cfc50 5256 case B43_PHYTYPE_HT:
075ca604 5257 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
3db1cd5c 5258 have_5ghz_phy = false;
e4d6b795 5259 }
075ca604
RM		 5260
5261 if (!have_2ghz_phy && !have_5ghz_phy) {
5262 b43err(wl, "b43 can't support any band on this device\n");
96c755a3
MB		 5263 err = -EOPNOTSUPP;
5264 goto err_powerdown;
5265 }
2e35af14 5266
fb11137a
MB		 5267 err = b43_phy_allocate(dev);
5268 if (err)
5269 goto err_powerdown;
5270
96c755a3 5271 dev->phy.gmode = have_2ghz_phy;
4da909e7 5272 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5273
5274 err = b43_validate_chipaccess(dev);
5275 if (err)
fb11137a 5276 goto err_phy_free;
bb1eeff1 5277 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5278 if (err)
fb11137a 5279 goto err_phy_free;
e4d6b795
MB		 5280
5281 /* Now set some default "current_dev" */
5282 if (!wl->current_dev)
5283 wl->current_dev = dev;
5284 INIT_WORK(&dev->restart_work, b43_chip_reset);
5285
cb24f57f 5286 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5287 b43_device_disable(dev, 0);
5288 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5289
5290out:
5291 return err;
5292
fb11137a
MB		 5293err_phy_free:
5294 b43_phy_free(dev);
e4d6b795 5295err_powerdown:
24ca39d6 5296 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5297 return err;
5298}
5299
482f0538 5300static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5301{
5302 struct b43_wldev *wldev;
5303 struct b43_wl *wl;
5304
3bf0a32e
MB		 5305 /* Do not cancel ieee80211-workqueue based work here.
5306 * See comment in b43_remove(). */
5307
74abacb6 5308 wldev = b43_bus_get_wldev(dev);
e4d6b795 5309 wl = wldev->wl;
e4d6b795
MB		 5310 b43_debugfs_remove_device(wldev);
5311 b43_wireless_core_detach(wldev);
5312 list_del(&wldev->list);
74abacb6 5313 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5314 kfree(wldev);
5315}
5316
482f0538 5317static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5318{
5319 struct b43_wldev *wldev;
e4d6b795
MB		 5320 int err = -ENOMEM;
5321
e4d6b795
MB		 5322 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5323 if (!wldev)
5324 goto out;
5325
9e3bd919 5326 wldev->use_pio = b43_modparam_pio;
482f0538 5327 wldev->dev = dev;
e4d6b795
MB		 5328 wldev->wl = wl;
5329 b43_set_status(wldev, B43_STAT_UNINIT);
5330 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5331 INIT_LIST_HEAD(&wldev->list);
5332
5333 err = b43_wireless_core_attach(wldev);
5334 if (err)
5335 goto err_kfree_wldev;
5336
74abacb6 5337 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5338 b43_debugfs_add_device(wldev);
5339
5340 out:
5341 return err;
5342
5343 err_kfree_wldev:
5344 kfree(wldev);
5345 return err;
5346}
5347
9fc38458
MB		 5348#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5349 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5350 (pdev->device == _device) && \
5351 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5352 (pdev->subsystem_device == _subdevice) )
5353
bd7c8a59 5354#ifdef CONFIG_B43_SSB
e4d6b795
MB		 5355static void b43_sprom_fixup(struct ssb_bus *bus)
5356{
1855ba78
MB		 5357 struct pci_dev *pdev;
5358
e4d6b795
MB		 5359 /* boardflags workarounds */
5360 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5361 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5362 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5363 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5364 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5365 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5366 if (bus->bustype == SSB_BUSTYPE_PCI) {
5367 pdev = bus->host_pci;
9fc38458 5368 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5369 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5370 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5371 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5372 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5373 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5374 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5375 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5376 }
e4d6b795
MB		 5377}
5378
482f0538 5379static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5380{
5381 struct ieee80211_hw *hw = wl->hw;
5382
482f0538 5383 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5384 ieee80211_free_hw(hw);
5385}
bd7c8a59 5386#endif
e4d6b795 5387
d1507051 5388static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5389{
d1507051 5390 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5391 struct ieee80211_hw *hw;
5392 struct b43_wl *wl;
2729df25 5393 char chip_name[6];
bad69194 5394 int queue_num;
e4d6b795
MB		 5395
5396 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5397 if (!hw) {
5398 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5399 return ERR_PTR(-ENOMEM);
e4d6b795 5400 }
403a3a13 5401 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5402
5403 /* fill hw info */
605a0bd6 5404 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5405 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5406
f59ac048
LR		 5407 hw->wiphy->interface_modes =
5408 BIT(NL80211_IFTYPE_AP) |
5409 BIT(NL80211_IFTYPE_MESH_POINT) |
5410 BIT(NL80211_IFTYPE_STATION) |
5411 BIT(NL80211_IFTYPE_WDS) |
5412 BIT(NL80211_IFTYPE_ADHOC);
5413
78f9c850
AQ		 5414 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5415
e64add27 5416 wl->hw_registred = false;
e6a9854b 5417 hw->max_rates = 2;
e4d6b795 5418 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5419 if (is_valid_ether_addr(sprom->et1mac))
5420 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5421 else
95de2841 5422 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5423
403a3a13 5424 /* Initialize struct b43_wl */
e4d6b795 5425 wl->hw = hw;
e4d6b795 5426 mutex_init(&wl->mutex);
36dbd954 5427 spin_lock_init(&wl->hardirq_lock);
a82d9922 5428 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5429 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5430 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5431
5432 /* Initialize queues and flags. */
5433 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5434 skb_queue_head_init(&wl->tx_queue[queue_num]);
5435 wl->tx_queue_stopped[queue_num] = 0;
5436 }
e4d6b795 5437
2729df25
RM		 5438 snprintf(chip_name, ARRAY_SIZE(chip_name),
5439 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5440 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5441 dev->core_rev);
0355a345 5442 return wl;
e4d6b795
MB		 5443}
5444
3c65ab62
RM		 5445#ifdef CONFIG_B43_BCMA
5446static int b43_bcma_probe(struct bcma_device *core)
5447{
397915c3 5448 struct b43_bus_dev *dev;
24aad3f4
RM		 5449 struct b43_wl *wl;
5450 int err;
397915c3 5451
8960400e
RM		 5452 if (!modparam_allhwsupport &&
5453 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5454 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5455 return -ENOTSUPP;
5456 }
5457
397915c3
RM		 5458 dev = b43_bus_dev_bcma_init(core);
5459 if (!dev)
5460 return -ENODEV;
5461
24aad3f4
RM		 5462 wl = b43_wireless_init(dev);
5463 if (IS_ERR(wl)) {
5464 err = PTR_ERR(wl);
5465 goto bcma_out;
5466 }
5467
5468 err = b43_one_core_attach(dev, wl);
5469 if (err)
5470 goto bcma_err_wireless_exit;
5471
6b6fa586
LF		 5472 /* setup and start work to load firmware */
5473 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5474 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5475
5476bcma_out:
5477 return err;
5478
24aad3f4
RM		 5479bcma_err_wireless_exit:
5480 ieee80211_free_hw(wl->hw);
5481 return err;
3c65ab62
RM		 5482}
5483
5484static void b43_bcma_remove(struct bcma_device *core)
5485{
24aad3f4
RM		 5486 struct b43_wldev *wldev = bcma_get_drvdata(core);
5487 struct b43_wl *wl = wldev->wl;
5488
5489 /* We must cancel any work here before unregistering from ieee80211,
5490 * as the ieee80211 unreg will destroy the workqueue. */
5491 cancel_work_sync(&wldev->restart_work);
63a02ce1 5492 cancel_work_sync(&wl->firmware_load);
24aad3f4 5493
e64add27 5494 B43_WARN_ON(!wl);
f89ff644
LF		 5495 if (!wldev->fw.ucode.data)
5496 return; /* NULL if firmware never loaded */
e64add27 5497 if (wl->current_dev == wldev && wl->hw_registred) {
e64add27
OR		 5498 b43_leds_stop(wldev);
5499 ieee80211_unregister_hw(wl->hw);
5500 }
24aad3f4
RM		 5501
5502 b43_one_core_detach(wldev->dev);
5503
09164043
LF		 5504 /* Unregister HW RNG driver */
5505 b43_rng_exit(wl);
5506
24aad3f4
RM		 5507 b43_leds_unregister(wl);
5508
5509 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5510}
5511
5512static struct bcma_driver b43_bcma_driver = {
5513 .name = KBUILD_MODNAME,
5514 .id_table = b43_bcma_tbl,
5515 .probe = b43_bcma_probe,
5516 .remove = b43_bcma_remove,
5517};
5518#endif
5519
aec7ffdf 5520#ifdef CONFIG_B43_SSB
aa63418a
RM		 5521static
5522int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5523{
482f0538 5524 struct b43_bus_dev *dev;
e4d6b795
MB		 5525 struct b43_wl *wl;
5526 int err;
e4d6b795 5527
482f0538 5528 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5529 if (!dev)
5530 return -ENOMEM;
482f0538 5531
aa63418a 5532 wl = ssb_get_devtypedata(sdev);
8f15e287
RM		 5533 if (wl) {
5534 b43err(NULL, "Dual-core devices are not supported\n");
5535 err = -ENOTSUPP;
5536 goto err_ssb_kfree_dev;
e4d6b795 5537 }
8f15e287
RM		 5538
5539 b43_sprom_fixup(sdev->bus);
5540
5541 wl = b43_wireless_init(dev);
5542 if (IS_ERR(wl)) {
5543 err = PTR_ERR(wl);
5544 goto err_ssb_kfree_dev;
5545 }
5546 ssb_set_devtypedata(sdev, wl);
5547 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5548
e4d6b795
MB		 5549 err = b43_one_core_attach(dev, wl);
5550 if (err)
8f15e287 5551 goto err_ssb_wireless_exit;
e4d6b795 5552
6b6fa586
LF		 5553 /* setup and start work to load firmware */
5554 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5555 schedule_work(&wl->firmware_load);
e4d6b795 5556
e4d6b795
MB		 5557 return err;
5558
8f15e287
RM		 5559err_ssb_wireless_exit:
5560 b43_wireless_exit(dev, wl);
5561err_ssb_kfree_dev:
5562 kfree(dev);
e4d6b795
MB		 5563 return err;
5564}
5565
aa63418a 5566static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5567{
aa63418a
RM		 5568 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5569 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5570 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5571
3bf0a32e
MB		 5572 /* We must cancel any work here before unregistering from ieee80211,
5573 * as the ieee80211 unreg will destroy the workqueue. */
5574 cancel_work_sync(&wldev->restart_work);
63a02ce1 5575 cancel_work_sync(&wl->firmware_load);
3bf0a32e 5576
e4d6b795 5577 B43_WARN_ON(!wl);
f89ff644
LF		 5578 if (!wldev->fw.ucode.data)
5579 return; /* NULL if firmware never loaded */
e64add27 5580 if (wl->current_dev == wldev && wl->hw_registred) {
82905ace 5581 b43_leds_stop(wldev);
e4d6b795 5582 ieee80211_unregister_hw(wl->hw);
403a3a13 5583 }
e4d6b795 5584
e61b52d1 5585 b43_one_core_detach(dev);
e4d6b795 5586
09164043
LF		 5587 /* Unregister HW RNG driver */
5588 b43_rng_exit(wl);
5589
644aa4d6
RM		 5590 b43_leds_unregister(wl);
5591 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5592}
5593
aec7ffdf
RM		 5594static struct ssb_driver b43_ssb_driver = {
5595 .name = KBUILD_MODNAME,
5596 .id_table = b43_ssb_tbl,
5597 .probe = b43_ssb_probe,
5598 .remove = b43_ssb_remove,
5599};
5600#endif /* CONFIG_B43_SSB */
5601
e4d6b795
MB		 5602/* Perform a hardware reset. This can be called from any context. */
5603void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5604{
5605 /* Must avoid requeueing, if we are in shutdown. */
5606 if (b43_status(dev) < B43_STAT_INITIALIZED)
5607 return;
5608 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5609 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5610}
5611
26bc783f
MB		 5612static void b43_print_driverinfo(void)
5613{
5614 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5615 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5616
5617#ifdef CONFIG_B43_PCI_AUTOSELECT
5618 feat_pci = "P";
5619#endif
5620#ifdef CONFIG_B43_PCMCIA
5621 feat_pcmcia = "M";
5622#endif
692d2c0f 5623#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5624 feat_nphy = "N";
5625#endif
5626#ifdef CONFIG_B43_LEDS
5627 feat_leds = "L";
3dbba8e2
AH		 5628#endif
5629#ifdef CONFIG_B43_SDIO
5630 feat_sdio = "S";
26bc783f
MB		 5631#endif
5632 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5633 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5634 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5635 feat_leds, feat_sdio);
26bc783f
MB		 5636}
5637
e4d6b795
MB		 5638static int __init b43_init(void)
5639{
5640 int err;
5641
5642 b43_debugfs_init();
5643 err = b43_pcmcia_init();
5644 if (err)
5645 goto err_dfs_exit;
3dbba8e2 5646 err = b43_sdio_init();
e4d6b795
MB		 5647 if (err)
5648 goto err_pcmcia_exit;
3c65ab62
RM		 5649#ifdef CONFIG_B43_BCMA
5650 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5651 if (err)
5652 goto err_sdio_exit;
3c65ab62 5653#endif
aec7ffdf 5654#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5655 err = ssb_driver_register(&b43_ssb_driver);
5656 if (err)
5657 goto err_bcma_driver_exit;
aec7ffdf 5658#endif
26bc783f 5659 b43_print_driverinfo();
e4d6b795
MB		 5660
5661 return err;
5662
aec7ffdf 5663#ifdef CONFIG_B43_SSB
3c65ab62 5664err_bcma_driver_exit:
aec7ffdf 5665#endif
3c65ab62
RM		 5666#ifdef CONFIG_B43_BCMA
5667 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5668err_sdio_exit:
3c65ab62 5669#endif
3dbba8e2 5670 b43_sdio_exit();
e4d6b795
MB		 5671err_pcmcia_exit:
5672 b43_pcmcia_exit();
5673err_dfs_exit:
5674 b43_debugfs_exit();
5675 return err;
5676}
5677
5678static void __exit b43_exit(void)
5679{
aec7ffdf 5680#ifdef CONFIG_B43_SSB
e4d6b795 5681 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5682#endif
3c65ab62
RM		 5683#ifdef CONFIG_B43_BCMA
5684 bcma_driver_unregister(&b43_bcma_driver);
5685#endif
3dbba8e2 5686 b43_sdio_exit();
e4d6b795
MB		 5687 b43_pcmcia_exit();
5688 b43_debugfs_exit();
5689}
5690
5691module_init(b43_init)
5692module_exit(b43_exit)
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